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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
744093c9 BH |
11 | #ifndef EFX_NIC_H |
12 | #define EFX_NIC_H | |
8ceee660 | 13 | |
7c236c43 | 14 | #include <linux/net_tstamp.h> |
5c16a96c | 15 | #include <linux/i2c-algo-bit.h> |
8ceee660 | 16 | #include "net_driver.h" |
177dfcd8 | 17 | #include "efx.h" |
8880f4ec | 18 | #include "mcdi.h" |
8ceee660 | 19 | |
daeda630 | 20 | enum { |
42e6cae1 BK |
21 | /* Revisions 0-2 were Falcon A0, A1 and B0 respectively. |
22 | * They are not supported by this driver but these revision numbers | |
23 | * form part of the ethtool API for register dumping. | |
24 | */ | |
25 | EFX_REV_SIENA_A0 = 3, | |
26 | EFX_REV_HUNT_A0 = 4, | |
8ceee660 BH |
27 | }; |
28 | ||
daeda630 | 29 | static inline int efx_nic_rev(struct efx_nic *efx) |
55668611 | 30 | { |
daeda630 | 31 | return efx->type->revision; |
55668611 | 32 | } |
8ceee660 | 33 | |
00aef986 | 34 | u32 efx_farch_fpga_ver(struct efx_nic *efx); |
152b6a62 | 35 | |
86094f7f BH |
36 | /* Read the current event from the event queue */ |
37 | static inline efx_qword_t *efx_event(struct efx_channel *channel, | |
38 | unsigned int index) | |
39 | { | |
40 | return ((efx_qword_t *) (channel->eventq.buf.addr)) + | |
41 | (index & channel->eventq_mask); | |
42 | } | |
43 | ||
44 | /* See if an event is present | |
45 | * | |
46 | * We check both the high and low dword of the event for all ones. We | |
47 | * wrote all ones when we cleared the event, and no valid event can | |
48 | * have all ones in either its high or low dwords. This approach is | |
49 | * robust against reordering. | |
50 | * | |
51 | * Note that using a single 64-bit comparison is incorrect; even | |
52 | * though the CPU read will be atomic, the DMA write may not be. | |
53 | */ | |
54 | static inline int efx_event_present(efx_qword_t *event) | |
55 | { | |
56 | return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
57 | EFX_DWORD_IS_ALL_ONES(event->dword[1])); | |
58 | } | |
59 | ||
60 | /* Returns a pointer to the specified transmit descriptor in the TX | |
61 | * descriptor queue belonging to the specified channel. | |
62 | */ | |
63 | static inline efx_qword_t * | |
64 | efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) | |
65 | { | |
66 | return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; | |
67 | } | |
68 | ||
70b33fb0 EC |
69 | /* Get partner of a TX queue, seen as part of the same net core queue */ |
70 | static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue) | |
71 | { | |
72 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) | |
73 | return tx_queue - EFX_TXQ_TYPE_OFFLOAD; | |
74 | else | |
75 | return tx_queue + EFX_TXQ_TYPE_OFFLOAD; | |
76 | } | |
77 | ||
78 | /* Report whether this TX queue would be empty for the given write_count. | |
79 | * May return false negative. | |
306a2782 BH |
80 | */ |
81 | static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, | |
82 | unsigned int write_count) | |
83 | { | |
84 | unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count); | |
85 | ||
86 | if (empty_read_count == 0) | |
87 | return false; | |
88 | ||
89 | return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; | |
90 | } | |
91 | ||
de1deff9 EC |
92 | /* Report whether the NIC considers this TX queue empty, using |
93 | * packet_write_count (the write count recorded for the last completable | |
94 | * doorbell push). May return false negative. EF10 only, which is OK | |
95 | * because only EF10 supports PIO. | |
96 | */ | |
97 | static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue) | |
98 | { | |
99 | EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors); | |
100 | return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count); | |
101 | } | |
102 | ||
70b33fb0 EC |
103 | /* Decide whether we can use TX PIO, ie. write packet data directly into |
104 | * a buffer on the device. This can reduce latency at the expense of | |
105 | * throughput, so we only do this if both hardware and software TX rings | |
106 | * are empty. This also ensures that only one packet at a time can be | |
107 | * using the PIO buffer. | |
108 | */ | |
109 | static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue) | |
306a2782 | 110 | { |
70b33fb0 | 111 | struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue); |
de1deff9 EC |
112 | |
113 | return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) && | |
114 | efx_nic_tx_is_empty(partner); | |
306a2782 BH |
115 | } |
116 | ||
86094f7f BH |
117 | /* Decide whether to push a TX descriptor to the NIC vs merely writing |
118 | * the doorbell. This can reduce latency when we are adding a single | |
119 | * descriptor to an empty queue, but is otherwise pointless. Further, | |
120 | * Falcon and Siena have hardware bugs (SF bug 33851) that may be | |
121 | * triggered if we don't check this. | |
70b33fb0 EC |
122 | * We use the write_count used for the last doorbell push, to get the |
123 | * NIC's view of the tx queue. | |
86094f7f BH |
124 | */ |
125 | static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, | |
126 | unsigned int write_count) | |
127 | { | |
306a2782 | 128 | bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); |
86094f7f BH |
129 | |
130 | tx_queue->empty_read_count = 0; | |
306a2782 | 131 | return was_empty && tx_queue->write_count - write_count == 1; |
86094f7f BH |
132 | } |
133 | ||
134 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
135 | static inline efx_qword_t * | |
136 | efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
137 | { | |
138 | return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; | |
139 | } | |
140 | ||
c1c4f453 BH |
141 | enum { |
142 | PHY_TYPE_NONE = 0, | |
143 | PHY_TYPE_TXC43128 = 1, | |
144 | PHY_TYPE_88E1111 = 2, | |
145 | PHY_TYPE_SFX7101 = 3, | |
146 | PHY_TYPE_QT2022C2 = 4, | |
147 | PHY_TYPE_PM8358 = 6, | |
148 | PHY_TYPE_SFT9001A = 8, | |
149 | PHY_TYPE_QT2025C = 9, | |
150 | PHY_TYPE_SFT9001B = 10, | |
151 | }; | |
152 | ||
5b6262d0 BH |
153 | /* Alignment of PCIe DMA boundaries (4KB) */ |
154 | #define EFX_PAGE_SIZE 4096 | |
155 | /* Size and alignment of buffer table entries (same) */ | |
156 | #define EFX_BUF_SIZE EFX_PAGE_SIZE | |
157 | ||
e4d112e4 EC |
158 | /* NIC-generic software stats */ |
159 | enum { | |
160 | GENERIC_STAT_rx_noskb_drops, | |
161 | GENERIC_STAT_rx_nodesc_trunc, | |
162 | GENERIC_STAT_COUNT | |
163 | }; | |
164 | ||
cd0ecc9a | 165 | enum { |
e4d112e4 | 166 | SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT, |
cd0ecc9a BH |
167 | SIENA_STAT_tx_good_bytes, |
168 | SIENA_STAT_tx_bad_bytes, | |
169 | SIENA_STAT_tx_packets, | |
170 | SIENA_STAT_tx_bad, | |
171 | SIENA_STAT_tx_pause, | |
172 | SIENA_STAT_tx_control, | |
173 | SIENA_STAT_tx_unicast, | |
174 | SIENA_STAT_tx_multicast, | |
175 | SIENA_STAT_tx_broadcast, | |
176 | SIENA_STAT_tx_lt64, | |
177 | SIENA_STAT_tx_64, | |
178 | SIENA_STAT_tx_65_to_127, | |
179 | SIENA_STAT_tx_128_to_255, | |
180 | SIENA_STAT_tx_256_to_511, | |
181 | SIENA_STAT_tx_512_to_1023, | |
182 | SIENA_STAT_tx_1024_to_15xx, | |
183 | SIENA_STAT_tx_15xx_to_jumbo, | |
184 | SIENA_STAT_tx_gtjumbo, | |
185 | SIENA_STAT_tx_collision, | |
186 | SIENA_STAT_tx_single_collision, | |
187 | SIENA_STAT_tx_multiple_collision, | |
188 | SIENA_STAT_tx_excessive_collision, | |
189 | SIENA_STAT_tx_deferred, | |
190 | SIENA_STAT_tx_late_collision, | |
191 | SIENA_STAT_tx_excessive_deferred, | |
192 | SIENA_STAT_tx_non_tcpudp, | |
193 | SIENA_STAT_tx_mac_src_error, | |
194 | SIENA_STAT_tx_ip_src_error, | |
195 | SIENA_STAT_rx_bytes, | |
196 | SIENA_STAT_rx_good_bytes, | |
197 | SIENA_STAT_rx_bad_bytes, | |
198 | SIENA_STAT_rx_packets, | |
199 | SIENA_STAT_rx_good, | |
200 | SIENA_STAT_rx_bad, | |
201 | SIENA_STAT_rx_pause, | |
202 | SIENA_STAT_rx_control, | |
203 | SIENA_STAT_rx_unicast, | |
204 | SIENA_STAT_rx_multicast, | |
205 | SIENA_STAT_rx_broadcast, | |
206 | SIENA_STAT_rx_lt64, | |
207 | SIENA_STAT_rx_64, | |
208 | SIENA_STAT_rx_65_to_127, | |
209 | SIENA_STAT_rx_128_to_255, | |
210 | SIENA_STAT_rx_256_to_511, | |
211 | SIENA_STAT_rx_512_to_1023, | |
212 | SIENA_STAT_rx_1024_to_15xx, | |
213 | SIENA_STAT_rx_15xx_to_jumbo, | |
214 | SIENA_STAT_rx_gtjumbo, | |
215 | SIENA_STAT_rx_bad_gtjumbo, | |
216 | SIENA_STAT_rx_overflow, | |
217 | SIENA_STAT_rx_false_carrier, | |
218 | SIENA_STAT_rx_symbol_error, | |
219 | SIENA_STAT_rx_align_error, | |
220 | SIENA_STAT_rx_length_error, | |
221 | SIENA_STAT_rx_internal_error, | |
222 | SIENA_STAT_rx_nodesc_drop_cnt, | |
223 | SIENA_STAT_COUNT | |
224 | }; | |
225 | ||
8880f4ec BH |
226 | /** |
227 | * struct siena_nic_data - Siena NIC state | |
2dc313ec | 228 | * @efx: Pointer back to main interface structure |
8880f4ec | 229 | * @wol_filter_id: Wake-on-LAN packet filter id |
cd0ecc9a | 230 | * @stats: Hardware statistics |
bf3d0156 | 231 | * @vf: Array of &struct siena_vf objects |
2dc313ec SS |
232 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. |
233 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
234 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
235 | * @local_page_list: List of DMA addressable pages used to broadcast | |
236 | * %local_addr_list. Protected by %local_lock. | |
237 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
238 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
8880f4ec BH |
239 | */ |
240 | struct siena_nic_data { | |
2dc313ec | 241 | struct efx_nic *efx; |
8880f4ec | 242 | int wol_filter_id; |
cd0ecc9a | 243 | u64 stats[SIENA_STAT_COUNT]; |
2dc313ec | 244 | #ifdef CONFIG_SFC_SRIOV |
bf3d0156 | 245 | struct siena_vf *vf; |
2dc313ec SS |
246 | struct efx_channel *vfdi_channel; |
247 | unsigned vf_buftbl_base; | |
248 | struct efx_buffer vfdi_status; | |
249 | struct list_head local_addr_list; | |
250 | struct list_head local_page_list; | |
251 | struct mutex local_lock; | |
252 | struct work_struct peer_work; | |
253 | #endif | |
8880f4ec BH |
254 | }; |
255 | ||
8127d661 | 256 | enum { |
e80ca013 DP |
257 | EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT, |
258 | EF10_STAT_port_tx_packets, | |
259 | EF10_STAT_port_tx_pause, | |
260 | EF10_STAT_port_tx_control, | |
261 | EF10_STAT_port_tx_unicast, | |
262 | EF10_STAT_port_tx_multicast, | |
263 | EF10_STAT_port_tx_broadcast, | |
264 | EF10_STAT_port_tx_lt64, | |
265 | EF10_STAT_port_tx_64, | |
266 | EF10_STAT_port_tx_65_to_127, | |
267 | EF10_STAT_port_tx_128_to_255, | |
268 | EF10_STAT_port_tx_256_to_511, | |
269 | EF10_STAT_port_tx_512_to_1023, | |
270 | EF10_STAT_port_tx_1024_to_15xx, | |
271 | EF10_STAT_port_tx_15xx_to_jumbo, | |
272 | EF10_STAT_port_rx_bytes, | |
273 | EF10_STAT_port_rx_bytes_minus_good_bytes, | |
274 | EF10_STAT_port_rx_good_bytes, | |
275 | EF10_STAT_port_rx_bad_bytes, | |
276 | EF10_STAT_port_rx_packets, | |
277 | EF10_STAT_port_rx_good, | |
278 | EF10_STAT_port_rx_bad, | |
279 | EF10_STAT_port_rx_pause, | |
280 | EF10_STAT_port_rx_control, | |
281 | EF10_STAT_port_rx_unicast, | |
282 | EF10_STAT_port_rx_multicast, | |
283 | EF10_STAT_port_rx_broadcast, | |
284 | EF10_STAT_port_rx_lt64, | |
285 | EF10_STAT_port_rx_64, | |
286 | EF10_STAT_port_rx_65_to_127, | |
287 | EF10_STAT_port_rx_128_to_255, | |
288 | EF10_STAT_port_rx_256_to_511, | |
289 | EF10_STAT_port_rx_512_to_1023, | |
290 | EF10_STAT_port_rx_1024_to_15xx, | |
291 | EF10_STAT_port_rx_15xx_to_jumbo, | |
292 | EF10_STAT_port_rx_gtjumbo, | |
293 | EF10_STAT_port_rx_bad_gtjumbo, | |
294 | EF10_STAT_port_rx_overflow, | |
295 | EF10_STAT_port_rx_align_error, | |
296 | EF10_STAT_port_rx_length_error, | |
297 | EF10_STAT_port_rx_nodesc_drops, | |
298 | EF10_STAT_port_rx_pm_trunc_bb_overflow, | |
299 | EF10_STAT_port_rx_pm_discard_bb_overflow, | |
300 | EF10_STAT_port_rx_pm_trunc_vfifo_full, | |
301 | EF10_STAT_port_rx_pm_discard_vfifo_full, | |
302 | EF10_STAT_port_rx_pm_trunc_qbb, | |
303 | EF10_STAT_port_rx_pm_discard_qbb, | |
304 | EF10_STAT_port_rx_pm_discard_mapping, | |
305 | EF10_STAT_port_rx_dp_q_disabled_packets, | |
306 | EF10_STAT_port_rx_dp_di_dropped_packets, | |
307 | EF10_STAT_port_rx_dp_streaming_packets, | |
308 | EF10_STAT_port_rx_dp_hlb_fetch, | |
309 | EF10_STAT_port_rx_dp_hlb_wait, | |
3c36a2ad DP |
310 | EF10_STAT_rx_unicast, |
311 | EF10_STAT_rx_unicast_bytes, | |
312 | EF10_STAT_rx_multicast, | |
313 | EF10_STAT_rx_multicast_bytes, | |
314 | EF10_STAT_rx_broadcast, | |
315 | EF10_STAT_rx_broadcast_bytes, | |
316 | EF10_STAT_rx_bad, | |
317 | EF10_STAT_rx_bad_bytes, | |
318 | EF10_STAT_rx_overflow, | |
319 | EF10_STAT_tx_unicast, | |
320 | EF10_STAT_tx_unicast_bytes, | |
321 | EF10_STAT_tx_multicast, | |
322 | EF10_STAT_tx_multicast_bytes, | |
323 | EF10_STAT_tx_broadcast, | |
324 | EF10_STAT_tx_broadcast_bytes, | |
325 | EF10_STAT_tx_bad, | |
326 | EF10_STAT_tx_bad_bytes, | |
327 | EF10_STAT_tx_overflow, | |
8127d661 BH |
328 | EF10_STAT_COUNT |
329 | }; | |
330 | ||
183233be BH |
331 | /* Maximum number of TX PIO buffers we may allocate to a function. |
332 | * This matches the total number of buffers on each SFC9100-family | |
333 | * controller. | |
334 | */ | |
335 | #define EF10_TX_PIOBUF_COUNT 16 | |
336 | ||
8127d661 BH |
337 | /** |
338 | * struct efx_ef10_nic_data - EF10 architecture NIC state | |
339 | * @mcdi_buf: DMA buffer for MCDI | |
340 | * @warm_boot_count: Last seen MC warm boot count | |
341 | * @vi_base: Absolute index of first VI in this function | |
342 | * @n_allocated_vis: Number of VIs allocated to this function | |
343 | * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot | |
344 | * @must_restore_filters: Flag: filters have yet to be restored after MC reboot | |
183233be BH |
345 | * @n_piobufs: Number of PIO buffers allocated to this function |
346 | * @wc_membase: Base address of write-combining mapping of the memory BAR | |
347 | * @pio_write_base: Base address for writing PIO buffers | |
348 | * @pio_write_vi_base: Relative VI number for @pio_write_base | |
349 | * @piobuf_handle: Handle of each PIO buffer allocated | |
c634700f | 350 | * @piobuf_size: size of a single PIO buffer |
183233be BH |
351 | * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC |
352 | * reboot | |
8127d661 | 353 | * @rx_rss_context: Firmware handle for our RSS context |
267c0157 | 354 | * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared |
8127d661 BH |
355 | * @stats: Hardware statistics |
356 | * @workaround_35388: Flag: firmware supports workaround for bug 35388 | |
46e612b0 | 357 | * @workaround_26807: Flag: firmware supports workaround for bug 26807 |
539de7c5 | 358 | * @workaround_61265: Flag: firmware supports workaround for bug 61265 |
a915ccc9 BH |
359 | * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated |
360 | * after MC reboot | |
8127d661 BH |
361 | * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of |
362 | * %MC_CMD_GET_CAPABILITIES response) | |
ca889a05 BK |
363 | * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of |
364 | * %MC_CMD_GET_CAPABILITIES response) | |
8d9f9dd4 DP |
365 | * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU |
366 | * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU | |
45b2449e | 367 | * @vport_id: The function's vport ID, only relevant for PFs |
6d8aaaf6 | 368 | * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot |
1cd9ecbb | 369 | * @pf_index: The number for this PF, or the parent PF if this is a VF |
3c5eb876 SS |
370 | #ifdef CONFIG_SFC_SRIOV |
371 | * @vf: Pointer to VF data structure | |
372 | #endif | |
34813fe2 AR |
373 | * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero |
374 | * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock. | |
375 | * @vlan_lock: Lock to serialize access to vlan_list. | |
e5fbd977 JC |
376 | * @udp_tunnels: UDP tunnel port numbers and types. |
377 | * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing | |
378 | * @udp_tunnels to hardware and thus the push must be re-done. | |
379 | * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty. | |
8127d661 BH |
380 | */ |
381 | struct efx_ef10_nic_data { | |
382 | struct efx_buffer mcdi_buf; | |
383 | u16 warm_boot_count; | |
384 | unsigned int vi_base; | |
385 | unsigned int n_allocated_vis; | |
386 | bool must_realloc_vis; | |
387 | bool must_restore_filters; | |
183233be BH |
388 | unsigned int n_piobufs; |
389 | void __iomem *wc_membase, *pio_write_base; | |
390 | unsigned int pio_write_vi_base; | |
391 | unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; | |
c634700f | 392 | u16 piobuf_size; |
183233be | 393 | bool must_restore_piobufs; |
8127d661 | 394 | u32 rx_rss_context; |
267c0157 | 395 | bool rx_rss_context_exclusive; |
8127d661 BH |
396 | u64 stats[EF10_STAT_COUNT]; |
397 | bool workaround_35388; | |
46e612b0 | 398 | bool workaround_26807; |
539de7c5 | 399 | bool workaround_61265; |
a915ccc9 | 400 | bool must_check_datapath_caps; |
8127d661 | 401 | u32 datapath_caps; |
ca889a05 | 402 | u32 datapath_caps2; |
8d9f9dd4 DP |
403 | unsigned int rx_dpcpu_fw_id; |
404 | unsigned int tx_dpcpu_fw_id; | |
45b2449e | 405 | unsigned int vport_id; |
6d8aaaf6 | 406 | bool must_probe_vswitching; |
1cd9ecbb | 407 | unsigned int pf_index; |
1d051e00 | 408 | u8 port_id[ETH_ALEN]; |
3c5eb876 | 409 | #ifdef CONFIG_SFC_SRIOV |
88a37de6 | 410 | unsigned int vf_index; |
3c5eb876 SS |
411 | struct ef10_vf *vf; |
412 | #endif | |
413 | u8 vport_mac[ETH_ALEN]; | |
34813fe2 AR |
414 | struct list_head vlan_list; |
415 | struct mutex vlan_lock; | |
e5fbd977 JC |
416 | struct efx_udp_tunnel udp_tunnels[16]; |
417 | bool udp_tunnels_dirty; | |
418 | struct mutex udp_tunnels_lock; | |
8127d661 BH |
419 | }; |
420 | ||
00aef986 | 421 | int efx_init_sriov(void); |
00aef986 | 422 | void efx_fini_sriov(void); |
cd2d5b52 | 423 | |
7c236c43 | 424 | struct ethtool_ts_info; |
ac36baf8 BH |
425 | int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel); |
426 | void efx_ptp_defer_probe_with_channel(struct efx_nic *efx); | |
427 | void efx_ptp_remove(struct efx_nic *efx); | |
433dc9b3 BH |
428 | int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr); |
429 | int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr); | |
00aef986 JP |
430 | void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); |
431 | bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); | |
9ec06595 DP |
432 | int efx_ptp_get_mode(struct efx_nic *efx); |
433 | int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted, | |
434 | unsigned int new_mode); | |
00aef986 JP |
435 | int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); |
436 | void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); | |
99691c4a BH |
437 | size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings); |
438 | size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats); | |
bd9a265d JC |
439 | void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev); |
440 | void __efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
441 | struct sk_buff *skb); | |
442 | static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
443 | struct sk_buff *skb) | |
444 | { | |
445 | if (channel->sync_events_state == SYNC_EVENTS_VALID) | |
446 | __efx_rx_skb_attach_timestamp(channel, skb); | |
447 | } | |
2ea4dc28 AR |
448 | void efx_ptp_start_datapath(struct efx_nic *efx); |
449 | void efx_ptp_stop_datapath(struct efx_nic *efx); | |
7c236c43 | 450 | |
6c8c2513 | 451 | extern const struct efx_nic_type falcon_a1_nic_type; |
452 | extern const struct efx_nic_type falcon_b0_nic_type; | |
453 | extern const struct efx_nic_type siena_a0_nic_type; | |
8127d661 | 454 | extern const struct efx_nic_type efx_hunt_a0_nic_type; |
02246a7f | 455 | extern const struct efx_nic_type efx_hunt_a0_vf_nic_type; |
8ceee660 BH |
456 | |
457 | /************************************************************************** | |
458 | * | |
459 | * Externs | |
460 | * | |
461 | ************************************************************************** | |
462 | */ | |
463 | ||
00aef986 | 464 | int falcon_probe_board(struct efx_nic *efx, u16 revision_info); |
5087b54d | 465 | |
8ceee660 | 466 | /* TX data path */ |
86094f7f BH |
467 | static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) |
468 | { | |
469 | return tx_queue->efx->type->tx_probe(tx_queue); | |
470 | } | |
471 | static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) | |
472 | { | |
473 | tx_queue->efx->type->tx_init(tx_queue); | |
474 | } | |
475 | static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) | |
476 | { | |
477 | tx_queue->efx->type->tx_remove(tx_queue); | |
478 | } | |
479 | static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) | |
480 | { | |
481 | tx_queue->efx->type->tx_write(tx_queue); | |
482 | } | |
8ceee660 BH |
483 | |
484 | /* RX data path */ | |
86094f7f BH |
485 | static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) |
486 | { | |
487 | return rx_queue->efx->type->rx_probe(rx_queue); | |
488 | } | |
489 | static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) | |
490 | { | |
491 | rx_queue->efx->type->rx_init(rx_queue); | |
492 | } | |
493 | static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) | |
494 | { | |
495 | rx_queue->efx->type->rx_remove(rx_queue); | |
496 | } | |
497 | static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
498 | { | |
499 | rx_queue->efx->type->rx_write(rx_queue); | |
500 | } | |
501 | static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) | |
502 | { | |
503 | rx_queue->efx->type->rx_defer_refill(rx_queue); | |
504 | } | |
8ceee660 BH |
505 | |
506 | /* Event data path */ | |
86094f7f BH |
507 | static inline int efx_nic_probe_eventq(struct efx_channel *channel) |
508 | { | |
509 | return channel->efx->type->ev_probe(channel); | |
510 | } | |
261e4d96 | 511 | static inline int efx_nic_init_eventq(struct efx_channel *channel) |
86094f7f | 512 | { |
261e4d96 | 513 | return channel->efx->type->ev_init(channel); |
86094f7f BH |
514 | } |
515 | static inline void efx_nic_fini_eventq(struct efx_channel *channel) | |
516 | { | |
517 | channel->efx->type->ev_fini(channel); | |
518 | } | |
519 | static inline void efx_nic_remove_eventq(struct efx_channel *channel) | |
520 | { | |
521 | channel->efx->type->ev_remove(channel); | |
522 | } | |
523 | static inline int | |
524 | efx_nic_process_eventq(struct efx_channel *channel, int quota) | |
525 | { | |
526 | return channel->efx->type->ev_process(channel, quota); | |
527 | } | |
528 | static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) | |
529 | { | |
530 | channel->efx->type->ev_read_ack(channel); | |
531 | } | |
00aef986 | 532 | void efx_nic_event_test_start(struct efx_channel *channel); |
86094f7f BH |
533 | |
534 | /* Falcon/Siena queue operations */ | |
00aef986 JP |
535 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); |
536 | void efx_farch_tx_init(struct efx_tx_queue *tx_queue); | |
537 | void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); | |
538 | void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); | |
539 | void efx_farch_tx_write(struct efx_tx_queue *tx_queue); | |
e9117e50 BK |
540 | unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue, |
541 | dma_addr_t dma_addr, unsigned int len); | |
00aef986 JP |
542 | int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); |
543 | void efx_farch_rx_init(struct efx_rx_queue *rx_queue); | |
544 | void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); | |
545 | void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); | |
546 | void efx_farch_rx_write(struct efx_rx_queue *rx_queue); | |
547 | void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); | |
548 | int efx_farch_ev_probe(struct efx_channel *channel); | |
549 | int efx_farch_ev_init(struct efx_channel *channel); | |
550 | void efx_farch_ev_fini(struct efx_channel *channel); | |
551 | void efx_farch_ev_remove(struct efx_channel *channel); | |
552 | int efx_farch_ev_process(struct efx_channel *channel, int quota); | |
553 | void efx_farch_ev_read_ack(struct efx_channel *channel); | |
554 | void efx_farch_ev_test_generate(struct efx_channel *channel); | |
86094f7f | 555 | |
add72477 | 556 | /* Falcon/Siena filter operations */ |
00aef986 JP |
557 | int efx_farch_filter_table_probe(struct efx_nic *efx); |
558 | void efx_farch_filter_table_restore(struct efx_nic *efx); | |
559 | void efx_farch_filter_table_remove(struct efx_nic *efx); | |
560 | void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); | |
561 | s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, | |
562 | bool replace); | |
563 | int efx_farch_filter_remove_safe(struct efx_nic *efx, | |
564 | enum efx_filter_priority priority, | |
565 | u32 filter_id); | |
566 | int efx_farch_filter_get_safe(struct efx_nic *efx, | |
567 | enum efx_filter_priority priority, u32 filter_id, | |
568 | struct efx_filter_spec *); | |
fbd79120 BH |
569 | int efx_farch_filter_clear_rx(struct efx_nic *efx, |
570 | enum efx_filter_priority priority); | |
00aef986 JP |
571 | u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, |
572 | enum efx_filter_priority priority); | |
573 | u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); | |
574 | s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, | |
575 | enum efx_filter_priority priority, u32 *buf, | |
576 | u32 size); | |
add72477 | 577 | #ifdef CONFIG_RFS_ACCEL |
00aef986 JP |
578 | s32 efx_farch_filter_rfs_insert(struct efx_nic *efx, |
579 | struct efx_filter_spec *spec); | |
580 | bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, | |
581 | unsigned int index); | |
add72477 | 582 | #endif |
00aef986 | 583 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); |
add72477 | 584 | |
00aef986 | 585 | bool efx_nic_event_present(struct efx_channel *channel); |
8ceee660 | 586 | |
b7f514af BH |
587 | /* Some statistics are computed as A - B where A and B each increase |
588 | * linearly with some hardware counter(s) and the counters are read | |
589 | * asynchronously. If the counters contributing to B are always read | |
590 | * after those contributing to A, the computed value may be lower than | |
591 | * the true value by some variable amount, and may decrease between | |
592 | * subsequent computations. | |
593 | * | |
594 | * We should never allow statistics to decrease or to exceed the true | |
595 | * value. Since the computed value will never be greater than the | |
596 | * true value, we can achieve this by only storing the computed value | |
597 | * when it increases. | |
598 | */ | |
599 | static inline void efx_update_diff_stat(u64 *stat, u64 diff) | |
600 | { | |
601 | if ((s64)(diff - *stat) > 0) | |
602 | *stat = diff; | |
603 | } | |
604 | ||
86094f7f | 605 | /* Interrupts */ |
00aef986 | 606 | int efx_nic_init_interrupt(struct efx_nic *efx); |
942e298e | 607 | int efx_nic_irq_test_start(struct efx_nic *efx); |
00aef986 | 608 | void efx_nic_fini_interrupt(struct efx_nic *efx); |
86094f7f BH |
609 | |
610 | /* Falcon/Siena interrupts */ | |
00aef986 | 611 | void efx_farch_irq_enable_master(struct efx_nic *efx); |
942e298e | 612 | int efx_farch_irq_test_generate(struct efx_nic *efx); |
00aef986 JP |
613 | void efx_farch_irq_disable_master(struct efx_nic *efx); |
614 | irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); | |
615 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); | |
616 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); | |
152b6a62 | 617 | |
eee6f6a9 BH |
618 | static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) |
619 | { | |
dd40781e | 620 | return ACCESS_ONCE(channel->event_test_cpu); |
eee6f6a9 BH |
621 | } |
622 | static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) | |
623 | { | |
624 | return ACCESS_ONCE(efx->last_irq_cpu); | |
625 | } | |
626 | ||
8ceee660 | 627 | /* Global Resources */ |
00aef986 JP |
628 | int efx_nic_flush_queues(struct efx_nic *efx); |
629 | void siena_prepare_flush(struct efx_nic *efx); | |
630 | int efx_farch_fini_dmaq(struct efx_nic *efx); | |
e283546c | 631 | void efx_farch_finish_flr(struct efx_nic *efx); |
00aef986 JP |
632 | void siena_finish_flush(struct efx_nic *efx); |
633 | void falcon_start_nic_stats(struct efx_nic *efx); | |
634 | void falcon_stop_nic_stats(struct efx_nic *efx); | |
635 | int falcon_reset_xaui(struct efx_nic *efx); | |
636 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); | |
637 | void efx_farch_init_common(struct efx_nic *efx); | |
638 | void efx_ef10_handle_drain_event(struct efx_nic *efx); | |
00aef986 | 639 | void efx_farch_rx_push_indir_table(struct efx_nic *efx); |
a707d188 | 640 | void efx_farch_rx_pull_indir_table(struct efx_nic *efx); |
152b6a62 BH |
641 | |
642 | int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, | |
0d19a540 | 643 | unsigned int len, gfp_t gfp_flags); |
152b6a62 | 644 | void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); |
8ceee660 | 645 | |
8c8661e4 | 646 | /* Tests */ |
86094f7f | 647 | struct efx_farch_register_test { |
152b6a62 BH |
648 | unsigned address; |
649 | efx_oword_t mask; | |
650 | }; | |
00aef986 JP |
651 | int efx_farch_test_registers(struct efx_nic *efx, |
652 | const struct efx_farch_register_test *regs, | |
653 | size_t n_regs); | |
8c8661e4 | 654 | |
00aef986 JP |
655 | size_t efx_nic_get_regs_len(struct efx_nic *efx); |
656 | void efx_nic_get_regs(struct efx_nic *efx, void *buf); | |
5b98c1bf | 657 | |
00aef986 JP |
658 | size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, |
659 | const unsigned long *mask, u8 *names); | |
660 | void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, | |
661 | const unsigned long *mask, u64 *stats, | |
662 | const void *dma_buf, bool accumulate); | |
f8f3b5ae | 663 | void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); |
cd0ecc9a | 664 | |
ab0115fc | 665 | #define EFX_MAX_FLUSH_TIME 5000 |
8ceee660 | 666 | |
00aef986 JP |
667 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, |
668 | efx_qword_t *event); | |
8ceee660 | 669 | |
744093c9 | 670 | #endif /* EFX_NIC_H */ |