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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
8ceee660 | 2 | /**************************************************************************** |
f7a6d2c4 | 3 | * Driver for Solarflare network controllers and boards |
8ceee660 | 4 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 5 | * Copyright 2006-2013 Solarflare Communications Inc. |
8ceee660 BH |
6 | */ |
7 | ||
744093c9 BH |
8 | #ifndef EFX_NIC_H |
9 | #define EFX_NIC_H | |
8ceee660 | 10 | |
7c236c43 | 11 | #include <linux/net_tstamp.h> |
5c16a96c | 12 | #include <linux/i2c-algo-bit.h> |
8ceee660 | 13 | #include "net_driver.h" |
177dfcd8 | 14 | #include "efx.h" |
8880f4ec | 15 | #include "mcdi.h" |
8ceee660 | 16 | |
daeda630 | 17 | enum { |
42e6cae1 BK |
18 | /* Revisions 0-2 were Falcon A0, A1 and B0 respectively. |
19 | * They are not supported by this driver but these revision numbers | |
20 | * form part of the ethtool API for register dumping. | |
21 | */ | |
22 | EFX_REV_SIENA_A0 = 3, | |
23 | EFX_REV_HUNT_A0 = 4, | |
8ceee660 BH |
24 | }; |
25 | ||
daeda630 | 26 | static inline int efx_nic_rev(struct efx_nic *efx) |
55668611 | 27 | { |
daeda630 | 28 | return efx->type->revision; |
55668611 | 29 | } |
8ceee660 | 30 | |
00aef986 | 31 | u32 efx_farch_fpga_ver(struct efx_nic *efx); |
152b6a62 | 32 | |
86094f7f BH |
33 | /* Read the current event from the event queue */ |
34 | static inline efx_qword_t *efx_event(struct efx_channel *channel, | |
35 | unsigned int index) | |
36 | { | |
37 | return ((efx_qword_t *) (channel->eventq.buf.addr)) + | |
38 | (index & channel->eventq_mask); | |
39 | } | |
40 | ||
41 | /* See if an event is present | |
42 | * | |
43 | * We check both the high and low dword of the event for all ones. We | |
44 | * wrote all ones when we cleared the event, and no valid event can | |
45 | * have all ones in either its high or low dwords. This approach is | |
46 | * robust against reordering. | |
47 | * | |
48 | * Note that using a single 64-bit comparison is incorrect; even | |
49 | * though the CPU read will be atomic, the DMA write may not be. | |
50 | */ | |
51 | static inline int efx_event_present(efx_qword_t *event) | |
52 | { | |
53 | return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
54 | EFX_DWORD_IS_ALL_ONES(event->dword[1])); | |
55 | } | |
56 | ||
57 | /* Returns a pointer to the specified transmit descriptor in the TX | |
58 | * descriptor queue belonging to the specified channel. | |
59 | */ | |
60 | static inline efx_qword_t * | |
61 | efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) | |
62 | { | |
63 | return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; | |
64 | } | |
65 | ||
70b33fb0 EC |
66 | /* Get partner of a TX queue, seen as part of the same net core queue */ |
67 | static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue) | |
68 | { | |
69 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) | |
70 | return tx_queue - EFX_TXQ_TYPE_OFFLOAD; | |
71 | else | |
72 | return tx_queue + EFX_TXQ_TYPE_OFFLOAD; | |
73 | } | |
74 | ||
75 | /* Report whether this TX queue would be empty for the given write_count. | |
76 | * May return false negative. | |
306a2782 BH |
77 | */ |
78 | static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, | |
79 | unsigned int write_count) | |
80 | { | |
6aa7de05 | 81 | unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count); |
306a2782 BH |
82 | |
83 | if (empty_read_count == 0) | |
84 | return false; | |
85 | ||
86 | return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; | |
87 | } | |
88 | ||
de1deff9 EC |
89 | /* Report whether the NIC considers this TX queue empty, using |
90 | * packet_write_count (the write count recorded for the last completable | |
91 | * doorbell push). May return false negative. EF10 only, which is OK | |
92 | * because only EF10 supports PIO. | |
93 | */ | |
94 | static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue) | |
95 | { | |
96 | EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors); | |
97 | return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count); | |
98 | } | |
99 | ||
70b33fb0 EC |
100 | /* Decide whether we can use TX PIO, ie. write packet data directly into |
101 | * a buffer on the device. This can reduce latency at the expense of | |
102 | * throughput, so we only do this if both hardware and software TX rings | |
103 | * are empty. This also ensures that only one packet at a time can be | |
104 | * using the PIO buffer. | |
105 | */ | |
106 | static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue) | |
306a2782 | 107 | { |
70b33fb0 | 108 | struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue); |
de1deff9 EC |
109 | |
110 | return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) && | |
111 | efx_nic_tx_is_empty(partner); | |
306a2782 BH |
112 | } |
113 | ||
86094f7f BH |
114 | /* Decide whether to push a TX descriptor to the NIC vs merely writing |
115 | * the doorbell. This can reduce latency when we are adding a single | |
116 | * descriptor to an empty queue, but is otherwise pointless. Further, | |
117 | * Falcon and Siena have hardware bugs (SF bug 33851) that may be | |
118 | * triggered if we don't check this. | |
70b33fb0 EC |
119 | * We use the write_count used for the last doorbell push, to get the |
120 | * NIC's view of the tx queue. | |
86094f7f BH |
121 | */ |
122 | static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, | |
123 | unsigned int write_count) | |
124 | { | |
306a2782 | 125 | bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); |
86094f7f BH |
126 | |
127 | tx_queue->empty_read_count = 0; | |
306a2782 | 128 | return was_empty && tx_queue->write_count - write_count == 1; |
86094f7f BH |
129 | } |
130 | ||
131 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
132 | static inline efx_qword_t * | |
133 | efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
134 | { | |
135 | return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; | |
136 | } | |
137 | ||
c1c4f453 BH |
138 | enum { |
139 | PHY_TYPE_NONE = 0, | |
140 | PHY_TYPE_TXC43128 = 1, | |
141 | PHY_TYPE_88E1111 = 2, | |
142 | PHY_TYPE_SFX7101 = 3, | |
143 | PHY_TYPE_QT2022C2 = 4, | |
144 | PHY_TYPE_PM8358 = 6, | |
145 | PHY_TYPE_SFT9001A = 8, | |
146 | PHY_TYPE_QT2025C = 9, | |
147 | PHY_TYPE_SFT9001B = 10, | |
148 | }; | |
149 | ||
5b6262d0 BH |
150 | /* Alignment of PCIe DMA boundaries (4KB) */ |
151 | #define EFX_PAGE_SIZE 4096 | |
152 | /* Size and alignment of buffer table entries (same) */ | |
153 | #define EFX_BUF_SIZE EFX_PAGE_SIZE | |
154 | ||
e4d112e4 EC |
155 | /* NIC-generic software stats */ |
156 | enum { | |
157 | GENERIC_STAT_rx_noskb_drops, | |
158 | GENERIC_STAT_rx_nodesc_trunc, | |
159 | GENERIC_STAT_COUNT | |
160 | }; | |
161 | ||
cd0ecc9a | 162 | enum { |
e4d112e4 | 163 | SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT, |
cd0ecc9a BH |
164 | SIENA_STAT_tx_good_bytes, |
165 | SIENA_STAT_tx_bad_bytes, | |
166 | SIENA_STAT_tx_packets, | |
167 | SIENA_STAT_tx_bad, | |
168 | SIENA_STAT_tx_pause, | |
169 | SIENA_STAT_tx_control, | |
170 | SIENA_STAT_tx_unicast, | |
171 | SIENA_STAT_tx_multicast, | |
172 | SIENA_STAT_tx_broadcast, | |
173 | SIENA_STAT_tx_lt64, | |
174 | SIENA_STAT_tx_64, | |
175 | SIENA_STAT_tx_65_to_127, | |
176 | SIENA_STAT_tx_128_to_255, | |
177 | SIENA_STAT_tx_256_to_511, | |
178 | SIENA_STAT_tx_512_to_1023, | |
179 | SIENA_STAT_tx_1024_to_15xx, | |
180 | SIENA_STAT_tx_15xx_to_jumbo, | |
181 | SIENA_STAT_tx_gtjumbo, | |
182 | SIENA_STAT_tx_collision, | |
183 | SIENA_STAT_tx_single_collision, | |
184 | SIENA_STAT_tx_multiple_collision, | |
185 | SIENA_STAT_tx_excessive_collision, | |
186 | SIENA_STAT_tx_deferred, | |
187 | SIENA_STAT_tx_late_collision, | |
188 | SIENA_STAT_tx_excessive_deferred, | |
189 | SIENA_STAT_tx_non_tcpudp, | |
190 | SIENA_STAT_tx_mac_src_error, | |
191 | SIENA_STAT_tx_ip_src_error, | |
192 | SIENA_STAT_rx_bytes, | |
193 | SIENA_STAT_rx_good_bytes, | |
194 | SIENA_STAT_rx_bad_bytes, | |
195 | SIENA_STAT_rx_packets, | |
196 | SIENA_STAT_rx_good, | |
197 | SIENA_STAT_rx_bad, | |
198 | SIENA_STAT_rx_pause, | |
199 | SIENA_STAT_rx_control, | |
200 | SIENA_STAT_rx_unicast, | |
201 | SIENA_STAT_rx_multicast, | |
202 | SIENA_STAT_rx_broadcast, | |
203 | SIENA_STAT_rx_lt64, | |
204 | SIENA_STAT_rx_64, | |
205 | SIENA_STAT_rx_65_to_127, | |
206 | SIENA_STAT_rx_128_to_255, | |
207 | SIENA_STAT_rx_256_to_511, | |
208 | SIENA_STAT_rx_512_to_1023, | |
209 | SIENA_STAT_rx_1024_to_15xx, | |
210 | SIENA_STAT_rx_15xx_to_jumbo, | |
211 | SIENA_STAT_rx_gtjumbo, | |
212 | SIENA_STAT_rx_bad_gtjumbo, | |
213 | SIENA_STAT_rx_overflow, | |
214 | SIENA_STAT_rx_false_carrier, | |
215 | SIENA_STAT_rx_symbol_error, | |
216 | SIENA_STAT_rx_align_error, | |
217 | SIENA_STAT_rx_length_error, | |
218 | SIENA_STAT_rx_internal_error, | |
219 | SIENA_STAT_rx_nodesc_drop_cnt, | |
220 | SIENA_STAT_COUNT | |
221 | }; | |
222 | ||
8880f4ec BH |
223 | /** |
224 | * struct siena_nic_data - Siena NIC state | |
2dc313ec | 225 | * @efx: Pointer back to main interface structure |
8880f4ec | 226 | * @wol_filter_id: Wake-on-LAN packet filter id |
cd0ecc9a | 227 | * @stats: Hardware statistics |
bf3d0156 | 228 | * @vf: Array of &struct siena_vf objects |
2dc313ec SS |
229 | * @vf_buftbl_base: The zeroth buffer table index used to back VF queues. |
230 | * @vfdi_status: Common VFDI status page to be dmad to VF address space. | |
231 | * @local_addr_list: List of local addresses. Protected by %local_lock. | |
232 | * @local_page_list: List of DMA addressable pages used to broadcast | |
233 | * %local_addr_list. Protected by %local_lock. | |
234 | * @local_lock: Mutex protecting %local_addr_list and %local_page_list. | |
235 | * @peer_work: Work item to broadcast peer addresses to VMs. | |
8880f4ec BH |
236 | */ |
237 | struct siena_nic_data { | |
2dc313ec | 238 | struct efx_nic *efx; |
8880f4ec | 239 | int wol_filter_id; |
cd0ecc9a | 240 | u64 stats[SIENA_STAT_COUNT]; |
2dc313ec | 241 | #ifdef CONFIG_SFC_SRIOV |
bf3d0156 | 242 | struct siena_vf *vf; |
2dc313ec SS |
243 | struct efx_channel *vfdi_channel; |
244 | unsigned vf_buftbl_base; | |
245 | struct efx_buffer vfdi_status; | |
246 | struct list_head local_addr_list; | |
247 | struct list_head local_page_list; | |
248 | struct mutex local_lock; | |
249 | struct work_struct peer_work; | |
250 | #endif | |
8880f4ec BH |
251 | }; |
252 | ||
8127d661 | 253 | enum { |
e80ca013 DP |
254 | EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT, |
255 | EF10_STAT_port_tx_packets, | |
256 | EF10_STAT_port_tx_pause, | |
257 | EF10_STAT_port_tx_control, | |
258 | EF10_STAT_port_tx_unicast, | |
259 | EF10_STAT_port_tx_multicast, | |
260 | EF10_STAT_port_tx_broadcast, | |
261 | EF10_STAT_port_tx_lt64, | |
262 | EF10_STAT_port_tx_64, | |
263 | EF10_STAT_port_tx_65_to_127, | |
264 | EF10_STAT_port_tx_128_to_255, | |
265 | EF10_STAT_port_tx_256_to_511, | |
266 | EF10_STAT_port_tx_512_to_1023, | |
267 | EF10_STAT_port_tx_1024_to_15xx, | |
268 | EF10_STAT_port_tx_15xx_to_jumbo, | |
269 | EF10_STAT_port_rx_bytes, | |
270 | EF10_STAT_port_rx_bytes_minus_good_bytes, | |
271 | EF10_STAT_port_rx_good_bytes, | |
272 | EF10_STAT_port_rx_bad_bytes, | |
273 | EF10_STAT_port_rx_packets, | |
274 | EF10_STAT_port_rx_good, | |
275 | EF10_STAT_port_rx_bad, | |
276 | EF10_STAT_port_rx_pause, | |
277 | EF10_STAT_port_rx_control, | |
278 | EF10_STAT_port_rx_unicast, | |
279 | EF10_STAT_port_rx_multicast, | |
280 | EF10_STAT_port_rx_broadcast, | |
281 | EF10_STAT_port_rx_lt64, | |
282 | EF10_STAT_port_rx_64, | |
283 | EF10_STAT_port_rx_65_to_127, | |
284 | EF10_STAT_port_rx_128_to_255, | |
285 | EF10_STAT_port_rx_256_to_511, | |
286 | EF10_STAT_port_rx_512_to_1023, | |
287 | EF10_STAT_port_rx_1024_to_15xx, | |
288 | EF10_STAT_port_rx_15xx_to_jumbo, | |
289 | EF10_STAT_port_rx_gtjumbo, | |
290 | EF10_STAT_port_rx_bad_gtjumbo, | |
291 | EF10_STAT_port_rx_overflow, | |
292 | EF10_STAT_port_rx_align_error, | |
293 | EF10_STAT_port_rx_length_error, | |
294 | EF10_STAT_port_rx_nodesc_drops, | |
295 | EF10_STAT_port_rx_pm_trunc_bb_overflow, | |
296 | EF10_STAT_port_rx_pm_discard_bb_overflow, | |
297 | EF10_STAT_port_rx_pm_trunc_vfifo_full, | |
298 | EF10_STAT_port_rx_pm_discard_vfifo_full, | |
299 | EF10_STAT_port_rx_pm_trunc_qbb, | |
300 | EF10_STAT_port_rx_pm_discard_qbb, | |
301 | EF10_STAT_port_rx_pm_discard_mapping, | |
302 | EF10_STAT_port_rx_dp_q_disabled_packets, | |
303 | EF10_STAT_port_rx_dp_di_dropped_packets, | |
304 | EF10_STAT_port_rx_dp_streaming_packets, | |
305 | EF10_STAT_port_rx_dp_hlb_fetch, | |
306 | EF10_STAT_port_rx_dp_hlb_wait, | |
3c36a2ad DP |
307 | EF10_STAT_rx_unicast, |
308 | EF10_STAT_rx_unicast_bytes, | |
309 | EF10_STAT_rx_multicast, | |
310 | EF10_STAT_rx_multicast_bytes, | |
311 | EF10_STAT_rx_broadcast, | |
312 | EF10_STAT_rx_broadcast_bytes, | |
313 | EF10_STAT_rx_bad, | |
314 | EF10_STAT_rx_bad_bytes, | |
315 | EF10_STAT_rx_overflow, | |
316 | EF10_STAT_tx_unicast, | |
317 | EF10_STAT_tx_unicast_bytes, | |
318 | EF10_STAT_tx_multicast, | |
319 | EF10_STAT_tx_multicast_bytes, | |
320 | EF10_STAT_tx_broadcast, | |
321 | EF10_STAT_tx_broadcast_bytes, | |
322 | EF10_STAT_tx_bad, | |
323 | EF10_STAT_tx_bad_bytes, | |
324 | EF10_STAT_tx_overflow, | |
f411b54d EC |
325 | EF10_STAT_V1_COUNT, |
326 | EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT, | |
327 | EF10_STAT_fec_corrected_errors, | |
328 | EF10_STAT_fec_corrected_symbols_lane0, | |
329 | EF10_STAT_fec_corrected_symbols_lane1, | |
330 | EF10_STAT_fec_corrected_symbols_lane2, | |
331 | EF10_STAT_fec_corrected_symbols_lane3, | |
2c0b6ee8 BK |
332 | EF10_STAT_ctpio_vi_busy_fallback, |
333 | EF10_STAT_ctpio_long_write_success, | |
334 | EF10_STAT_ctpio_missing_dbell_fail, | |
335 | EF10_STAT_ctpio_overflow_fail, | |
336 | EF10_STAT_ctpio_underflow_fail, | |
337 | EF10_STAT_ctpio_timeout_fail, | |
338 | EF10_STAT_ctpio_noncontig_wr_fail, | |
339 | EF10_STAT_ctpio_frm_clobber_fail, | |
340 | EF10_STAT_ctpio_invalid_wr_fail, | |
341 | EF10_STAT_ctpio_vi_clobber_fallback, | |
342 | EF10_STAT_ctpio_unqualified_fallback, | |
343 | EF10_STAT_ctpio_runt_fallback, | |
344 | EF10_STAT_ctpio_success, | |
345 | EF10_STAT_ctpio_fallback, | |
346 | EF10_STAT_ctpio_poison, | |
347 | EF10_STAT_ctpio_erase, | |
8127d661 BH |
348 | EF10_STAT_COUNT |
349 | }; | |
350 | ||
183233be BH |
351 | /* Maximum number of TX PIO buffers we may allocate to a function. |
352 | * This matches the total number of buffers on each SFC9100-family | |
353 | * controller. | |
354 | */ | |
355 | #define EF10_TX_PIOBUF_COUNT 16 | |
356 | ||
8127d661 BH |
357 | /** |
358 | * struct efx_ef10_nic_data - EF10 architecture NIC state | |
359 | * @mcdi_buf: DMA buffer for MCDI | |
360 | * @warm_boot_count: Last seen MC warm boot count | |
361 | * @vi_base: Absolute index of first VI in this function | |
362 | * @n_allocated_vis: Number of VIs allocated to this function | |
363 | * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot | |
e0a65e3c EC |
364 | * @must_restore_rss_contexts: Flag: RSS contexts have yet to be restored after |
365 | * MC reboot | |
8127d661 | 366 | * @must_restore_filters: Flag: filters have yet to be restored after MC reboot |
183233be BH |
367 | * @n_piobufs: Number of PIO buffers allocated to this function |
368 | * @wc_membase: Base address of write-combining mapping of the memory BAR | |
369 | * @pio_write_base: Base address for writing PIO buffers | |
370 | * @pio_write_vi_base: Relative VI number for @pio_write_base | |
371 | * @piobuf_handle: Handle of each PIO buffer allocated | |
c634700f | 372 | * @piobuf_size: size of a single PIO buffer |
183233be BH |
373 | * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC |
374 | * reboot | |
267c0157 | 375 | * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared |
8127d661 BH |
376 | * @stats: Hardware statistics |
377 | * @workaround_35388: Flag: firmware supports workaround for bug 35388 | |
46e612b0 | 378 | * @workaround_26807: Flag: firmware supports workaround for bug 26807 |
539de7c5 | 379 | * @workaround_61265: Flag: firmware supports workaround for bug 61265 |
a915ccc9 BH |
380 | * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated |
381 | * after MC reboot | |
8127d661 BH |
382 | * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of |
383 | * %MC_CMD_GET_CAPABILITIES response) | |
ca889a05 BK |
384 | * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of |
385 | * %MC_CMD_GET_CAPABILITIES response) | |
8d9f9dd4 DP |
386 | * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU |
387 | * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU | |
45b2449e | 388 | * @vport_id: The function's vport ID, only relevant for PFs |
6d8aaaf6 | 389 | * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot |
1cd9ecbb | 390 | * @pf_index: The number for this PF, or the parent PF if this is a VF |
3c5eb876 SS |
391 | #ifdef CONFIG_SFC_SRIOV |
392 | * @vf: Pointer to VF data structure | |
393 | #endif | |
34813fe2 AR |
394 | * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero |
395 | * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock. | |
396 | * @vlan_lock: Lock to serialize access to vlan_list. | |
e5fbd977 JC |
397 | * @udp_tunnels: UDP tunnel port numbers and types. |
398 | * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing | |
399 | * @udp_tunnels to hardware and thus the push must be re-done. | |
400 | * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty. | |
8127d661 BH |
401 | */ |
402 | struct efx_ef10_nic_data { | |
403 | struct efx_buffer mcdi_buf; | |
404 | u16 warm_boot_count; | |
405 | unsigned int vi_base; | |
406 | unsigned int n_allocated_vis; | |
407 | bool must_realloc_vis; | |
e0a65e3c | 408 | bool must_restore_rss_contexts; |
8127d661 | 409 | bool must_restore_filters; |
183233be BH |
410 | unsigned int n_piobufs; |
411 | void __iomem *wc_membase, *pio_write_base; | |
412 | unsigned int pio_write_vi_base; | |
413 | unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; | |
c634700f | 414 | u16 piobuf_size; |
183233be | 415 | bool must_restore_piobufs; |
267c0157 | 416 | bool rx_rss_context_exclusive; |
8127d661 BH |
417 | u64 stats[EF10_STAT_COUNT]; |
418 | bool workaround_35388; | |
46e612b0 | 419 | bool workaround_26807; |
539de7c5 | 420 | bool workaround_61265; |
a915ccc9 | 421 | bool must_check_datapath_caps; |
8127d661 | 422 | u32 datapath_caps; |
ca889a05 | 423 | u32 datapath_caps2; |
8d9f9dd4 DP |
424 | unsigned int rx_dpcpu_fw_id; |
425 | unsigned int tx_dpcpu_fw_id; | |
45b2449e | 426 | unsigned int vport_id; |
6d8aaaf6 | 427 | bool must_probe_vswitching; |
1cd9ecbb | 428 | unsigned int pf_index; |
1d051e00 | 429 | u8 port_id[ETH_ALEN]; |
3c5eb876 | 430 | #ifdef CONFIG_SFC_SRIOV |
88a37de6 | 431 | unsigned int vf_index; |
3c5eb876 SS |
432 | struct ef10_vf *vf; |
433 | #endif | |
434 | u8 vport_mac[ETH_ALEN]; | |
34813fe2 AR |
435 | struct list_head vlan_list; |
436 | struct mutex vlan_lock; | |
e5fbd977 JC |
437 | struct efx_udp_tunnel udp_tunnels[16]; |
438 | bool udp_tunnels_dirty; | |
439 | struct mutex udp_tunnels_lock; | |
50663fe1 | 440 | u64 licensed_features; |
8127d661 BH |
441 | }; |
442 | ||
00aef986 | 443 | int efx_init_sriov(void); |
00aef986 | 444 | void efx_fini_sriov(void); |
cd2d5b52 | 445 | |
7c236c43 | 446 | struct ethtool_ts_info; |
ac36baf8 BH |
447 | int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel); |
448 | void efx_ptp_defer_probe_with_channel(struct efx_nic *efx); | |
c1d0d339 | 449 | struct efx_channel *efx_ptp_channel(struct efx_nic *efx); |
ac36baf8 | 450 | void efx_ptp_remove(struct efx_nic *efx); |
433dc9b3 BH |
451 | int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr); |
452 | int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr); | |
00aef986 JP |
453 | void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); |
454 | bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); | |
9ec06595 DP |
455 | int efx_ptp_get_mode(struct efx_nic *efx); |
456 | int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted, | |
457 | unsigned int new_mode); | |
00aef986 JP |
458 | int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); |
459 | void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); | |
99691c4a BH |
460 | size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings); |
461 | size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats); | |
bd9a265d JC |
462 | void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev); |
463 | void __efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
464 | struct sk_buff *skb); | |
465 | static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel, | |
466 | struct sk_buff *skb) | |
467 | { | |
468 | if (channel->sync_events_state == SYNC_EVENTS_VALID) | |
469 | __efx_rx_skb_attach_timestamp(channel, skb); | |
470 | } | |
2ea4dc28 AR |
471 | void efx_ptp_start_datapath(struct efx_nic *efx); |
472 | void efx_ptp_stop_datapath(struct efx_nic *efx); | |
9c3afb33 | 473 | bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx); |
b9b603d4 | 474 | ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue); |
7c236c43 | 475 | |
6c8c2513 | 476 | extern const struct efx_nic_type falcon_a1_nic_type; |
477 | extern const struct efx_nic_type falcon_b0_nic_type; | |
478 | extern const struct efx_nic_type siena_a0_nic_type; | |
8127d661 | 479 | extern const struct efx_nic_type efx_hunt_a0_nic_type; |
02246a7f | 480 | extern const struct efx_nic_type efx_hunt_a0_vf_nic_type; |
8ceee660 BH |
481 | |
482 | /************************************************************************** | |
483 | * | |
484 | * Externs | |
485 | * | |
486 | ************************************************************************** | |
487 | */ | |
488 | ||
00aef986 | 489 | int falcon_probe_board(struct efx_nic *efx, u16 revision_info); |
5087b54d | 490 | |
8ceee660 | 491 | /* TX data path */ |
86094f7f BH |
492 | static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) |
493 | { | |
494 | return tx_queue->efx->type->tx_probe(tx_queue); | |
495 | } | |
496 | static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) | |
497 | { | |
498 | tx_queue->efx->type->tx_init(tx_queue); | |
499 | } | |
500 | static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) | |
501 | { | |
502 | tx_queue->efx->type->tx_remove(tx_queue); | |
503 | } | |
504 | static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) | |
505 | { | |
506 | tx_queue->efx->type->tx_write(tx_queue); | |
507 | } | |
8ceee660 BH |
508 | |
509 | /* RX data path */ | |
86094f7f BH |
510 | static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) |
511 | { | |
512 | return rx_queue->efx->type->rx_probe(rx_queue); | |
513 | } | |
514 | static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) | |
515 | { | |
516 | rx_queue->efx->type->rx_init(rx_queue); | |
517 | } | |
518 | static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) | |
519 | { | |
520 | rx_queue->efx->type->rx_remove(rx_queue); | |
521 | } | |
522 | static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
523 | { | |
524 | rx_queue->efx->type->rx_write(rx_queue); | |
525 | } | |
526 | static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) | |
527 | { | |
528 | rx_queue->efx->type->rx_defer_refill(rx_queue); | |
529 | } | |
8ceee660 BH |
530 | |
531 | /* Event data path */ | |
86094f7f BH |
532 | static inline int efx_nic_probe_eventq(struct efx_channel *channel) |
533 | { | |
534 | return channel->efx->type->ev_probe(channel); | |
535 | } | |
261e4d96 | 536 | static inline int efx_nic_init_eventq(struct efx_channel *channel) |
86094f7f | 537 | { |
261e4d96 | 538 | return channel->efx->type->ev_init(channel); |
86094f7f BH |
539 | } |
540 | static inline void efx_nic_fini_eventq(struct efx_channel *channel) | |
541 | { | |
542 | channel->efx->type->ev_fini(channel); | |
543 | } | |
544 | static inline void efx_nic_remove_eventq(struct efx_channel *channel) | |
545 | { | |
546 | channel->efx->type->ev_remove(channel); | |
547 | } | |
548 | static inline int | |
549 | efx_nic_process_eventq(struct efx_channel *channel, int quota) | |
550 | { | |
551 | return channel->efx->type->ev_process(channel, quota); | |
552 | } | |
553 | static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) | |
554 | { | |
555 | channel->efx->type->ev_read_ack(channel); | |
556 | } | |
00aef986 | 557 | void efx_nic_event_test_start(struct efx_channel *channel); |
86094f7f BH |
558 | |
559 | /* Falcon/Siena queue operations */ | |
00aef986 JP |
560 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); |
561 | void efx_farch_tx_init(struct efx_tx_queue *tx_queue); | |
562 | void efx_farch_tx_fini(struct efx_tx_queue *tx_queue); | |
563 | void efx_farch_tx_remove(struct efx_tx_queue *tx_queue); | |
564 | void efx_farch_tx_write(struct efx_tx_queue *tx_queue); | |
e9117e50 BK |
565 | unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue, |
566 | dma_addr_t dma_addr, unsigned int len); | |
00aef986 JP |
567 | int efx_farch_rx_probe(struct efx_rx_queue *rx_queue); |
568 | void efx_farch_rx_init(struct efx_rx_queue *rx_queue); | |
569 | void efx_farch_rx_fini(struct efx_rx_queue *rx_queue); | |
570 | void efx_farch_rx_remove(struct efx_rx_queue *rx_queue); | |
571 | void efx_farch_rx_write(struct efx_rx_queue *rx_queue); | |
572 | void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue); | |
573 | int efx_farch_ev_probe(struct efx_channel *channel); | |
574 | int efx_farch_ev_init(struct efx_channel *channel); | |
575 | void efx_farch_ev_fini(struct efx_channel *channel); | |
576 | void efx_farch_ev_remove(struct efx_channel *channel); | |
577 | int efx_farch_ev_process(struct efx_channel *channel, int quota); | |
578 | void efx_farch_ev_read_ack(struct efx_channel *channel); | |
579 | void efx_farch_ev_test_generate(struct efx_channel *channel); | |
86094f7f | 580 | |
add72477 | 581 | /* Falcon/Siena filter operations */ |
00aef986 JP |
582 | int efx_farch_filter_table_probe(struct efx_nic *efx); |
583 | void efx_farch_filter_table_restore(struct efx_nic *efx); | |
584 | void efx_farch_filter_table_remove(struct efx_nic *efx); | |
585 | void efx_farch_filter_update_rx_scatter(struct efx_nic *efx); | |
586 | s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec, | |
587 | bool replace); | |
588 | int efx_farch_filter_remove_safe(struct efx_nic *efx, | |
589 | enum efx_filter_priority priority, | |
590 | u32 filter_id); | |
591 | int efx_farch_filter_get_safe(struct efx_nic *efx, | |
592 | enum efx_filter_priority priority, u32 filter_id, | |
593 | struct efx_filter_spec *); | |
fbd79120 BH |
594 | int efx_farch_filter_clear_rx(struct efx_nic *efx, |
595 | enum efx_filter_priority priority); | |
00aef986 JP |
596 | u32 efx_farch_filter_count_rx_used(struct efx_nic *efx, |
597 | enum efx_filter_priority priority); | |
598 | u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx); | |
599 | s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx, | |
600 | enum efx_filter_priority priority, u32 *buf, | |
601 | u32 size); | |
add72477 | 602 | #ifdef CONFIG_RFS_ACCEL |
00aef986 JP |
603 | bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, |
604 | unsigned int index); | |
add72477 | 605 | #endif |
00aef986 | 606 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); |
add72477 | 607 | |
00aef986 | 608 | bool efx_nic_event_present(struct efx_channel *channel); |
8ceee660 | 609 | |
b7f514af BH |
610 | /* Some statistics are computed as A - B where A and B each increase |
611 | * linearly with some hardware counter(s) and the counters are read | |
612 | * asynchronously. If the counters contributing to B are always read | |
613 | * after those contributing to A, the computed value may be lower than | |
614 | * the true value by some variable amount, and may decrease between | |
615 | * subsequent computations. | |
616 | * | |
617 | * We should never allow statistics to decrease or to exceed the true | |
618 | * value. Since the computed value will never be greater than the | |
619 | * true value, we can achieve this by only storing the computed value | |
620 | * when it increases. | |
621 | */ | |
622 | static inline void efx_update_diff_stat(u64 *stat, u64 diff) | |
623 | { | |
624 | if ((s64)(diff - *stat) > 0) | |
625 | *stat = diff; | |
626 | } | |
627 | ||
86094f7f | 628 | /* Interrupts */ |
00aef986 | 629 | int efx_nic_init_interrupt(struct efx_nic *efx); |
942e298e | 630 | int efx_nic_irq_test_start(struct efx_nic *efx); |
00aef986 | 631 | void efx_nic_fini_interrupt(struct efx_nic *efx); |
86094f7f BH |
632 | |
633 | /* Falcon/Siena interrupts */ | |
00aef986 | 634 | void efx_farch_irq_enable_master(struct efx_nic *efx); |
942e298e | 635 | int efx_farch_irq_test_generate(struct efx_nic *efx); |
00aef986 JP |
636 | void efx_farch_irq_disable_master(struct efx_nic *efx); |
637 | irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id); | |
638 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); | |
639 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); | |
152b6a62 | 640 | |
eee6f6a9 BH |
641 | static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) |
642 | { | |
6aa7de05 | 643 | return READ_ONCE(channel->event_test_cpu); |
eee6f6a9 BH |
644 | } |
645 | static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) | |
646 | { | |
6aa7de05 | 647 | return READ_ONCE(efx->last_irq_cpu); |
eee6f6a9 BH |
648 | } |
649 | ||
8ceee660 | 650 | /* Global Resources */ |
00aef986 JP |
651 | int efx_nic_flush_queues(struct efx_nic *efx); |
652 | void siena_prepare_flush(struct efx_nic *efx); | |
653 | int efx_farch_fini_dmaq(struct efx_nic *efx); | |
e283546c | 654 | void efx_farch_finish_flr(struct efx_nic *efx); |
00aef986 JP |
655 | void siena_finish_flush(struct efx_nic *efx); |
656 | void falcon_start_nic_stats(struct efx_nic *efx); | |
657 | void falcon_stop_nic_stats(struct efx_nic *efx); | |
658 | int falcon_reset_xaui(struct efx_nic *efx); | |
659 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); | |
660 | void efx_farch_init_common(struct efx_nic *efx); | |
661 | void efx_ef10_handle_drain_event(struct efx_nic *efx); | |
00aef986 | 662 | void efx_farch_rx_push_indir_table(struct efx_nic *efx); |
a707d188 | 663 | void efx_farch_rx_pull_indir_table(struct efx_nic *efx); |
152b6a62 BH |
664 | |
665 | int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, | |
0d19a540 | 666 | unsigned int len, gfp_t gfp_flags); |
152b6a62 | 667 | void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); |
8ceee660 | 668 | |
8c8661e4 | 669 | /* Tests */ |
86094f7f | 670 | struct efx_farch_register_test { |
152b6a62 BH |
671 | unsigned address; |
672 | efx_oword_t mask; | |
673 | }; | |
00aef986 JP |
674 | int efx_farch_test_registers(struct efx_nic *efx, |
675 | const struct efx_farch_register_test *regs, | |
676 | size_t n_regs); | |
8c8661e4 | 677 | |
00aef986 JP |
678 | size_t efx_nic_get_regs_len(struct efx_nic *efx); |
679 | void efx_nic_get_regs(struct efx_nic *efx, void *buf); | |
5b98c1bf | 680 | |
00aef986 JP |
681 | size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, |
682 | const unsigned long *mask, u8 *names); | |
683 | void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, | |
684 | const unsigned long *mask, u64 *stats, | |
685 | const void *dma_buf, bool accumulate); | |
f8f3b5ae | 686 | void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); |
cd0ecc9a | 687 | |
ab0115fc | 688 | #define EFX_MAX_FLUSH_TIME 5000 |
8ceee660 | 689 | |
00aef986 JP |
690 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, |
691 | efx_qword_t *event); | |
8ceee660 | 692 | |
744093c9 | 693 | #endif /* EFX_NIC_H */ |