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sfc: Change efx_nic_type::rx_push_indir_table to push hash key as well
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / sfc / nic.h
CommitLineData
8ceee660 1/****************************************************************************
f7a6d2c4 2 * Driver for Solarflare network controllers and boards
8ceee660 3 * Copyright 2005-2006 Fen Systems Ltd.
f7a6d2c4 4 * Copyright 2006-2013 Solarflare Communications Inc.
8ceee660
BH		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
744093c9
BH		 11#ifndef EFX_NIC_H
12#define EFX_NIC_H
8ceee660 13
7c236c43 14#include <linux/net_tstamp.h>
5c16a96c 15#include <linux/i2c-algo-bit.h>
8ceee660 16#include "net_driver.h"
177dfcd8 17#include "efx.h"
8880f4ec 18#include "mcdi.h"
8ceee660 19
daeda630
BH		 20enum {
21 EFX_REV_FALCON_A0 = 0,
22 EFX_REV_FALCON_A1 = 1,
23 EFX_REV_FALCON_B0 = 2,
8880f4ec 24 EFX_REV_SIENA_A0 = 3,
8127d661 25 EFX_REV_HUNT_A0 = 4,
8ceee660
BH		 26};
27
daeda630 28static inline int efx_nic_rev(struct efx_nic *efx)
55668611 29{
daeda630 30 return efx->type->revision;
55668611 31}
8ceee660 32
00aef986 33u32 efx_farch_fpga_ver(struct efx_nic *efx);
152b6a62
BH		 34
35/* NIC has two interlinked PCI functions for the same port. */
36static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
37{
38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
39}
40
86094f7f
BH		 41/* Read the current event from the event queue */
42static inline efx_qword_t *efx_event(struct efx_channel *channel,
43 unsigned int index)
44{
45 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
46 (index & channel->eventq_mask);
47}
48
49/* See if an event is present
50 *
51 * We check both the high and low dword of the event for all ones. We
52 * wrote all ones when we cleared the event, and no valid event can
53 * have all ones in either its high or low dwords. This approach is
54 * robust against reordering.
55 *
56 * Note that using a single 64-bit comparison is incorrect; even
57 * though the CPU read will be atomic, the DMA write may not be.
58 */
59static inline int efx_event_present(efx_qword_t *event)
60{
61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
62 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
63}
64
65/* Returns a pointer to the specified transmit descriptor in the TX
66 * descriptor queue belonging to the specified channel.
67 */
68static inline efx_qword_t *
69efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
70{
71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
72}
73
306a2782
BH		 74/* Report whether the NIC considers this TX queue empty, given the
75 * write_count used for the last doorbell push. May return false
76 * negative.
77 */
78static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
79 unsigned int write_count)
80{
81 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
82
83 if (empty_read_count == 0)
84 return false;
85
86 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
87}
88
89static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue)
90{
91 return __efx_nic_tx_is_empty(tx_queue, tx_queue->write_count);
92}
93
86094f7f
BH		 94/* Decide whether to push a TX descriptor to the NIC vs merely writing
95 * the doorbell. This can reduce latency when we are adding a single
96 * descriptor to an empty queue, but is otherwise pointless. Further,
97 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
98 * triggered if we don't check this.
99 */
100static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
101 unsigned int write_count)
102{
306a2782 103 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
86094f7f
BH		 104
105 tx_queue->empty_read_count = 0;
306a2782 106 return was_empty && tx_queue->write_count - write_count == 1;
86094f7f
BH		 107}
108
109/* Returns a pointer to the specified descriptor in the RX descriptor queue */
110static inline efx_qword_t *
111efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
112{
113 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
114}
115
c1c4f453
BH		 116enum {
117 PHY_TYPE_NONE = 0,
118 PHY_TYPE_TXC43128 = 1,
119 PHY_TYPE_88E1111 = 2,
120 PHY_TYPE_SFX7101 = 3,
121 PHY_TYPE_QT2022C2 = 4,
122 PHY_TYPE_PM8358 = 6,
123 PHY_TYPE_SFT9001A = 8,
124 PHY_TYPE_QT2025C = 9,
125 PHY_TYPE_SFT9001B = 10,
126};
127
128#define FALCON_XMAC_LOOPBACKS \
129 ((1 << LOOPBACK_XGMII) | \
130 (1 << LOOPBACK_XGXS) | \
131 (1 << LOOPBACK_XAUI))
132
5b6262d0
BH		 133/* Alignment of PCIe DMA boundaries (4KB) */
134#define EFX_PAGE_SIZE 4096
135/* Size and alignment of buffer table entries (same) */
136#define EFX_BUF_SIZE EFX_PAGE_SIZE
137
3759433d 138/**
44838a44
BH		 139 * struct falcon_board_type - board operations and type information
140 * @id: Board type id, as found in NVRAM
3759433d
BH		 141 * @init: Allocate resources and initialise peripheral hardware
142 * @init_phy: Do board-specific PHY initialisation
44838a44 143 * @fini: Shut down hardware and free resources
3759433d
BH		 144 * @set_id_led: Set state of identifying LED or revert to automatic function
145 * @monitor: Board-specific health check function
44838a44
BH		 146 */
147struct falcon_board_type {
148 u8 id;
44838a44
BH		 149 int (*init) (struct efx_nic *nic);
150 void (*init_phy) (struct efx_nic *efx);
151 void (*fini) (struct efx_nic *nic);
152 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
153 int (*monitor) (struct efx_nic *nic);
154};
155
156/**
157 * struct falcon_board - board information
158 * @type: Type of board
159 * @major: Major rev. ('A', 'B' ...)
160 * @minor: Minor rev. (0, 1, ...)
e775fb93
BH		 161 * @i2c_adap: I2C adapter for on-board peripherals
162 * @i2c_data: Data for bit-banging algorithm
3759433d
BH		 163 * @hwmon_client: I2C client for hardware monitor
164 * @ioexp_client: I2C client for power/port control
165 */
166struct falcon_board {
44838a44 167 const struct falcon_board_type *type;
3759433d
BH		 168 int major;
169 int minor;
e775fb93
BH		 170 struct i2c_adapter i2c_adap;
171 struct i2c_algo_bit_data i2c_data;
3759433d
BH		 172 struct i2c_client *hwmon_client, *ioexp_client;
173};
174
45a3fd55
BH		 175/**
176 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
177 * @device_id: Controller's id for the device
178 * @size: Size (in bytes)
179 * @addr_len: Number of address bytes in read/write commands
180 * @munge_address: Flag whether addresses should be munged.
181 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
182 * use bit 3 of the command byte as address bit A8, rather
183 * than having a two-byte address. If this flag is set, then
184 * commands should be munged in this way.
185 * @erase_command: Erase command (or 0 if sector erase not needed).
186 * @erase_size: Erase sector size (in bytes)
187 * Erase commands affect sectors with this size and alignment.
188 * This must be a power of two.
189 * @block_size: Write block size (in bytes).
190 * Write commands are limited to blocks with this size and alignment.
191 */
192struct falcon_spi_device {
193 int device_id;
194 unsigned int size;
195 unsigned int addr_len;
196 unsigned int munge_address:1;
197 u8 erase_command;
198 unsigned int erase_size;
199 unsigned int block_size;
200};
201
202static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
203{
204 return spi->size != 0;
205}
206
cd0ecc9a
BH		 207enum {
208 FALCON_STAT_tx_bytes,
209 FALCON_STAT_tx_packets,
210 FALCON_STAT_tx_pause,
211 FALCON_STAT_tx_control,
212 FALCON_STAT_tx_unicast,
213 FALCON_STAT_tx_multicast,
214 FALCON_STAT_tx_broadcast,
215 FALCON_STAT_tx_lt64,
216 FALCON_STAT_tx_64,
217 FALCON_STAT_tx_65_to_127,
218 FALCON_STAT_tx_128_to_255,
219 FALCON_STAT_tx_256_to_511,
220 FALCON_STAT_tx_512_to_1023,
221 FALCON_STAT_tx_1024_to_15xx,
222 FALCON_STAT_tx_15xx_to_jumbo,
223 FALCON_STAT_tx_gtjumbo,
224 FALCON_STAT_tx_non_tcpudp,
225 FALCON_STAT_tx_mac_src_error,
226 FALCON_STAT_tx_ip_src_error,
227 FALCON_STAT_rx_bytes,
228 FALCON_STAT_rx_good_bytes,
229 FALCON_STAT_rx_bad_bytes,
230 FALCON_STAT_rx_packets,
231 FALCON_STAT_rx_good,
232 FALCON_STAT_rx_bad,
233 FALCON_STAT_rx_pause,
234 FALCON_STAT_rx_control,
235 FALCON_STAT_rx_unicast,
236 FALCON_STAT_rx_multicast,
237 FALCON_STAT_rx_broadcast,
238 FALCON_STAT_rx_lt64,
239 FALCON_STAT_rx_64,
240 FALCON_STAT_rx_65_to_127,
241 FALCON_STAT_rx_128_to_255,
242 FALCON_STAT_rx_256_to_511,
243 FALCON_STAT_rx_512_to_1023,
244 FALCON_STAT_rx_1024_to_15xx,
245 FALCON_STAT_rx_15xx_to_jumbo,
246 FALCON_STAT_rx_gtjumbo,
247 FALCON_STAT_rx_bad_lt64,
248 FALCON_STAT_rx_bad_gtjumbo,
249 FALCON_STAT_rx_overflow,
250 FALCON_STAT_rx_symbol_error,
251 FALCON_STAT_rx_align_error,
252 FALCON_STAT_rx_length_error,
253 FALCON_STAT_rx_internal_error,
254 FALCON_STAT_rx_nodesc_drop_cnt,
255 FALCON_STAT_COUNT
256};
257
5c16a96c
BH		 258/**
259 * struct falcon_nic_data - Falcon NIC state
8986352a 260 * @pci_dev2: Secondary function of Falcon A
3759433d 261 * @board: Board state and functions
cd0ecc9a 262 * @stats: Hardware statistics
55edc6e6
BH		 263 * @stats_disable_count: Nest count for disabling statistics fetches
264 * @stats_pending: Is there a pending DMA of MAC statistics.
265 * @stats_timer: A timer for regularly fetching MAC statistics.
4de92180
BH		 266 * @spi_flash: SPI flash device
267 * @spi_eeprom: SPI EEPROM device
268 * @spi_lock: SPI bus lock
4833f02a 269 * @mdio_lock: MDIO bus lock
cef68bde 270 * @xmac_poll_required: XMAC link state needs polling
5c16a96c
BH		 271 */
272struct falcon_nic_data {
273 struct pci_dev *pci_dev2;
3759433d 274 struct falcon_board board;
cd0ecc9a 275 u64 stats[FALCON_STAT_COUNT];
55edc6e6
BH		 276 unsigned int stats_disable_count;
277 bool stats_pending;
278 struct timer_list stats_timer;
ecd0a6f0
BH		 279 struct falcon_spi_device spi_flash;
280 struct falcon_spi_device spi_eeprom;
4de92180 281 struct mutex spi_lock;
4833f02a 282 struct mutex mdio_lock;
cef68bde 283 bool xmac_poll_required;
5c16a96c
BH		 284};
285
278c0621
BH		 286static inline struct falcon_board *falcon_board(struct efx_nic *efx)
287{
3759433d
BH		 288 struct falcon_nic_data *data = efx->nic_data;
289 return &data->board;
278c0621
BH		 290}
291
cd0ecc9a
BH		 292enum {
293 SIENA_STAT_tx_bytes,
294 SIENA_STAT_tx_good_bytes,
295 SIENA_STAT_tx_bad_bytes,
296 SIENA_STAT_tx_packets,
297 SIENA_STAT_tx_bad,
298 SIENA_STAT_tx_pause,
299 SIENA_STAT_tx_control,
300 SIENA_STAT_tx_unicast,
301 SIENA_STAT_tx_multicast,
302 SIENA_STAT_tx_broadcast,
303 SIENA_STAT_tx_lt64,
304 SIENA_STAT_tx_64,
305 SIENA_STAT_tx_65_to_127,
306 SIENA_STAT_tx_128_to_255,
307 SIENA_STAT_tx_256_to_511,
308 SIENA_STAT_tx_512_to_1023,
309 SIENA_STAT_tx_1024_to_15xx,
310 SIENA_STAT_tx_15xx_to_jumbo,
311 SIENA_STAT_tx_gtjumbo,
312 SIENA_STAT_tx_collision,
313 SIENA_STAT_tx_single_collision,
314 SIENA_STAT_tx_multiple_collision,
315 SIENA_STAT_tx_excessive_collision,
316 SIENA_STAT_tx_deferred,
317 SIENA_STAT_tx_late_collision,
318 SIENA_STAT_tx_excessive_deferred,
319 SIENA_STAT_tx_non_tcpudp,
320 SIENA_STAT_tx_mac_src_error,
321 SIENA_STAT_tx_ip_src_error,
322 SIENA_STAT_rx_bytes,
323 SIENA_STAT_rx_good_bytes,
324 SIENA_STAT_rx_bad_bytes,
325 SIENA_STAT_rx_packets,
326 SIENA_STAT_rx_good,
327 SIENA_STAT_rx_bad,
328 SIENA_STAT_rx_pause,
329 SIENA_STAT_rx_control,
330 SIENA_STAT_rx_unicast,
331 SIENA_STAT_rx_multicast,
332 SIENA_STAT_rx_broadcast,
333 SIENA_STAT_rx_lt64,
334 SIENA_STAT_rx_64,
335 SIENA_STAT_rx_65_to_127,
336 SIENA_STAT_rx_128_to_255,
337 SIENA_STAT_rx_256_to_511,
338 SIENA_STAT_rx_512_to_1023,
339 SIENA_STAT_rx_1024_to_15xx,
340 SIENA_STAT_rx_15xx_to_jumbo,
341 SIENA_STAT_rx_gtjumbo,
342 SIENA_STAT_rx_bad_gtjumbo,
343 SIENA_STAT_rx_overflow,
344 SIENA_STAT_rx_false_carrier,
345 SIENA_STAT_rx_symbol_error,
346 SIENA_STAT_rx_align_error,
347 SIENA_STAT_rx_length_error,
348 SIENA_STAT_rx_internal_error,
349 SIENA_STAT_rx_nodesc_drop_cnt,
350 SIENA_STAT_COUNT
351};
352
8880f4ec
BH		 353/**
354 * struct siena_nic_data - Siena NIC state
8880f4ec 355 * @wol_filter_id: Wake-on-LAN packet filter id
cd0ecc9a 356 * @stats: Hardware statistics
8880f4ec
BH		 357 */
358struct siena_nic_data {
8880f4ec 359 int wol_filter_id;
cd0ecc9a 360 u64 stats[SIENA_STAT_COUNT];
8880f4ec
BH		 361};
362
8127d661
BH		 363enum {
364 EF10_STAT_tx_bytes,
365 EF10_STAT_tx_packets,
366 EF10_STAT_tx_pause,
367 EF10_STAT_tx_control,
368 EF10_STAT_tx_unicast,
369 EF10_STAT_tx_multicast,
370 EF10_STAT_tx_broadcast,
371 EF10_STAT_tx_lt64,
372 EF10_STAT_tx_64,
373 EF10_STAT_tx_65_to_127,
374 EF10_STAT_tx_128_to_255,
375 EF10_STAT_tx_256_to_511,
376 EF10_STAT_tx_512_to_1023,
377 EF10_STAT_tx_1024_to_15xx,
378 EF10_STAT_tx_15xx_to_jumbo,
379 EF10_STAT_rx_bytes,
380 EF10_STAT_rx_bytes_minus_good_bytes,
381 EF10_STAT_rx_good_bytes,
382 EF10_STAT_rx_bad_bytes,
383 EF10_STAT_rx_packets,
384 EF10_STAT_rx_good,
385 EF10_STAT_rx_bad,
386 EF10_STAT_rx_pause,
387 EF10_STAT_rx_control,
388 EF10_STAT_rx_unicast,
389 EF10_STAT_rx_multicast,
390 EF10_STAT_rx_broadcast,
391 EF10_STAT_rx_lt64,
392 EF10_STAT_rx_64,
393 EF10_STAT_rx_65_to_127,
394 EF10_STAT_rx_128_to_255,
395 EF10_STAT_rx_256_to_511,
396 EF10_STAT_rx_512_to_1023,
397 EF10_STAT_rx_1024_to_15xx,
398 EF10_STAT_rx_15xx_to_jumbo,
399 EF10_STAT_rx_gtjumbo,
400 EF10_STAT_rx_bad_gtjumbo,
401 EF10_STAT_rx_overflow,
402 EF10_STAT_rx_align_error,
403 EF10_STAT_rx_length_error,
404 EF10_STAT_rx_nodesc_drops,
568d7a00
EC		 405 EF10_STAT_rx_pm_trunc_bb_overflow,
406 EF10_STAT_rx_pm_discard_bb_overflow,
407 EF10_STAT_rx_pm_trunc_vfifo_full,
408 EF10_STAT_rx_pm_discard_vfifo_full,
409 EF10_STAT_rx_pm_trunc_qbb,
410 EF10_STAT_rx_pm_discard_qbb,
411 EF10_STAT_rx_pm_discard_mapping,
412 EF10_STAT_rx_dp_q_disabled_packets,
413 EF10_STAT_rx_dp_di_dropped_packets,
414 EF10_STAT_rx_dp_streaming_packets,
415 EF10_STAT_rx_dp_emerg_fetch,
416 EF10_STAT_rx_dp_emerg_wait,
8127d661
BH		 417 EF10_STAT_COUNT
418};
419
183233be
BH		 420/* Maximum number of TX PIO buffers we may allocate to a function.
421 * This matches the total number of buffers on each SFC9100-family
422 * controller.
423 */
424#define EF10_TX_PIOBUF_COUNT 16
425
8127d661
BH		 426/**
427 * struct efx_ef10_nic_data - EF10 architecture NIC state
428 * @mcdi_buf: DMA buffer for MCDI
429 * @warm_boot_count: Last seen MC warm boot count
430 * @vi_base: Absolute index of first VI in this function
431 * @n_allocated_vis: Number of VIs allocated to this function
432 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
433 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
183233be
BH		 434 * @n_piobufs: Number of PIO buffers allocated to this function
435 * @wc_membase: Base address of write-combining mapping of the memory BAR
436 * @pio_write_base: Base address for writing PIO buffers
437 * @pio_write_vi_base: Relative VI number for @pio_write_base
438 * @piobuf_handle: Handle of each PIO buffer allocated
439 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
440 * reboot
8127d661
BH		 441 * @rx_rss_context: Firmware handle for our RSS context
442 * @stats: Hardware statistics
443 * @workaround_35388: Flag: firmware supports workaround for bug 35388
a915ccc9
BH		 444 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
445 * after MC reboot
8127d661
BH		 446 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
447 * %MC_CMD_GET_CAPABILITIES response)
448 */
449struct efx_ef10_nic_data {
450 struct efx_buffer mcdi_buf;
451 u16 warm_boot_count;
452 unsigned int vi_base;
453 unsigned int n_allocated_vis;
454 bool must_realloc_vis;
455 bool must_restore_filters;
183233be
BH		 456 unsigned int n_piobufs;
457 void __iomem *wc_membase, *pio_write_base;
458 unsigned int pio_write_vi_base;
459 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
460 bool must_restore_piobufs;
8127d661
BH		 461 u32 rx_rss_context;
462 u64 stats[EF10_STAT_COUNT];
463 bool workaround_35388;
a915ccc9 464 bool must_check_datapath_caps;
8127d661
BH		 465 u32 datapath_caps;
466};
467
cd2d5b52
BH		 468/*
469 * On the SFC9000 family each port is associated with 1 PCI physical
470 * function (PF) handled by sfc and a configurable number of virtual
471 * functions (VFs) that may be handled by some other driver, often in
472 * a VM guest. The queue pointer registers are mapped in both PF and
473 * VF BARs such that an 8K region provides access to a single RX, TX
474 * and event queue (collectively a Virtual Interface, VI or VNIC).
475 *
476 * The PF has access to all 1024 VIs while VFs are mapped to VIs
477 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
478 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
479 * The number of VIs and the VI_SCALE value are configurable but must
480 * be established at boot time by firmware.
481 */
482
483/* Maximum VI_SCALE parameter supported by Siena */
484#define EFX_VI_SCALE_MAX 6
485/* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
486 * so this is the smallest allowed value. */
487#define EFX_VI_BASE 128U
488/* Maximum number of VFs allowed */
489#define EFX_VF_COUNT_MAX 127
490/* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
491#define EFX_MAX_VF_EVQ_SIZE 8192UL
492/* The number of buffer table entries reserved for each VI on a VF */
493#define EFX_VF_BUFTBL_PER_VI \
494 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
495 sizeof(efx_qword_t) / EFX_BUF_SIZE)
496
497#ifdef CONFIG_SFC_SRIOV
498
499static inline bool efx_sriov_wanted(struct efx_nic *efx)
500{
501 return efx->vf_count != 0;
502}
503static inline bool efx_sriov_enabled(struct efx_nic *efx)
504{
505 return efx->vf_init_count != 0;
506}
507static inline unsigned int efx_vf_size(struct efx_nic *efx)
508{
509 return 1 << efx->vi_scale;
510}
511
00aef986
JP		 512int efx_init_sriov(void);
513void efx_sriov_probe(struct efx_nic *efx);
514int efx_sriov_init(struct efx_nic *efx);
515void efx_sriov_mac_address_changed(struct efx_nic *efx);
516void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
517void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
518void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
519void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
520void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
521void efx_sriov_reset(struct efx_nic *efx);
522void efx_sriov_fini(struct efx_nic *efx);
523void efx_fini_sriov(void);
cd2d5b52
BH		 524
525#else
526
527static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
528static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
529static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
530
531static inline int efx_init_sriov(void) { return 0; }
532static inline void efx_sriov_probe(struct efx_nic *efx) {}
533static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
534static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
535static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
536 efx_qword_t *event) {}
537static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
538 efx_qword_t *event) {}
539static inline void efx_sriov_event(struct efx_channel *channel,
540 efx_qword_t *event) {}
541static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
542static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
543static inline void efx_sriov_reset(struct efx_nic *efx) {}
544static inline void efx_sriov_fini(struct efx_nic *efx) {}
545static inline void efx_fini_sriov(void) {}
546
547#endif
548
00aef986
JP		 549int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
550int efx_sriov_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos);
551int efx_sriov_get_vf_config(struct net_device *dev, int vf,
552 struct ifla_vf_info *ivf);
553int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
554 bool spoofchk);
cd2d5b52 555
7c236c43 556struct ethtool_ts_info;
ac36baf8
BH		 557int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
558void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
559void efx_ptp_remove(struct efx_nic *efx);
433dc9b3
BH		 560int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
561int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
00aef986
JP		 562void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
563bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
9ec06595
DP		 564int efx_ptp_get_mode(struct efx_nic *efx);
565int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
566 unsigned int new_mode);
00aef986
JP		 567int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
568void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
bd9a265d
JC		 569void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
570void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
571 struct sk_buff *skb);
572static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
573 struct sk_buff *skb)
574{
575 if (channel->sync_events_state == SYNC_EVENTS_VALID)
576 __efx_rx_skb_attach_timestamp(channel, skb);
577}
2ea4dc28
AR		 578void efx_ptp_start_datapath(struct efx_nic *efx);
579void efx_ptp_stop_datapath(struct efx_nic *efx);
7c236c43 580
6c8c2513 581extern const struct efx_nic_type falcon_a1_nic_type;
582extern const struct efx_nic_type falcon_b0_nic_type;
583extern const struct efx_nic_type siena_a0_nic_type;
8127d661 584extern const struct efx_nic_type efx_hunt_a0_nic_type;
8ceee660
BH		 585
586/**************************************************************************
587 *
588 * Externs
589 *
590 **************************************************************************
591 */
592
00aef986 593int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
5087b54d 594
8ceee660 595/* TX data path */
86094f7f
BH		 596static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
597{
598 return tx_queue->efx->type->tx_probe(tx_queue);
599}
600static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
601{
602 tx_queue->efx->type->tx_init(tx_queue);
603}
604static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
605{
606 tx_queue->efx->type->tx_remove(tx_queue);
607}
608static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
609{
610 tx_queue->efx->type->tx_write(tx_queue);
611}
8ceee660
BH		 612
613/* RX data path */
86094f7f
BH		 614static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
615{
616 return rx_queue->efx->type->rx_probe(rx_queue);
617}
618static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
619{
620 rx_queue->efx->type->rx_init(rx_queue);
621}
622static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
623{
624 rx_queue->efx->type->rx_remove(rx_queue);
625}
626static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
627{
628 rx_queue->efx->type->rx_write(rx_queue);
629}
630static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
631{
632 rx_queue->efx->type->rx_defer_refill(rx_queue);
633}
8ceee660
BH		 634
635/* Event data path */
86094f7f
BH		 636static inline int efx_nic_probe_eventq(struct efx_channel *channel)
637{
638 return channel->efx->type->ev_probe(channel);
639}
261e4d96 640static inline int efx_nic_init_eventq(struct efx_channel *channel)
86094f7f 641{
261e4d96 642 return channel->efx->type->ev_init(channel);
86094f7f
BH		 643}
644static inline void efx_nic_fini_eventq(struct efx_channel *channel)
645{
646 channel->efx->type->ev_fini(channel);
647}
648static inline void efx_nic_remove_eventq(struct efx_channel *channel)
649{
650 channel->efx->type->ev_remove(channel);
651}
652static inline int
653efx_nic_process_eventq(struct efx_channel *channel, int quota)
654{
655 return channel->efx->type->ev_process(channel, quota);
656}
657static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
658{
659 channel->efx->type->ev_read_ack(channel);
660}
00aef986 661void efx_nic_event_test_start(struct efx_channel *channel);
86094f7f
BH		 662
663/* Falcon/Siena queue operations */
00aef986
JP		 664int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
665void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
666void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
667void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
668void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
669int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
670void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
671void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
672void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
673void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
674void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
675int efx_farch_ev_probe(struct efx_channel *channel);
676int efx_farch_ev_init(struct efx_channel *channel);
677void efx_farch_ev_fini(struct efx_channel *channel);
678void efx_farch_ev_remove(struct efx_channel *channel);
679int efx_farch_ev_process(struct efx_channel *channel, int quota);
680void efx_farch_ev_read_ack(struct efx_channel *channel);
681void efx_farch_ev_test_generate(struct efx_channel *channel);
86094f7f 682
add72477 683/* Falcon/Siena filter operations */
00aef986
JP		 684int efx_farch_filter_table_probe(struct efx_nic *efx);
685void efx_farch_filter_table_restore(struct efx_nic *efx);
686void efx_farch_filter_table_remove(struct efx_nic *efx);
687void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
688s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
689 bool replace);
690int efx_farch_filter_remove_safe(struct efx_nic *efx,
691 enum efx_filter_priority priority,
692 u32 filter_id);
693int efx_farch_filter_get_safe(struct efx_nic *efx,
694 enum efx_filter_priority priority, u32 filter_id,
695 struct efx_filter_spec *);
696void efx_farch_filter_clear_rx(struct efx_nic *efx,
697 enum efx_filter_priority priority);
698u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
699 enum efx_filter_priority priority);
700u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
701s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
702 enum efx_filter_priority priority, u32 *buf,
703 u32 size);
add72477 704#ifdef CONFIG_RFS_ACCEL
00aef986
JP		 705s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
706 struct efx_filter_spec *spec);
707bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
708 unsigned int index);
add72477 709#endif
00aef986 710void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
add72477 711
00aef986 712bool efx_nic_event_present(struct efx_channel *channel);
8ceee660 713
b7f514af
BH		 714/* Some statistics are computed as A - B where A and B each increase
715 * linearly with some hardware counter(s) and the counters are read
716 * asynchronously. If the counters contributing to B are always read
717 * after those contributing to A, the computed value may be lower than
718 * the true value by some variable amount, and may decrease between
719 * subsequent computations.
720 *
721 * We should never allow statistics to decrease or to exceed the true
722 * value. Since the computed value will never be greater than the
723 * true value, we can achieve this by only storing the computed value
724 * when it increases.
725 */
726static inline void efx_update_diff_stat(u64 *stat, u64 diff)
727{
728 if ((s64)(diff - *stat) > 0)
729 *stat = diff;
730}
731
86094f7f 732/* Interrupts */
00aef986
JP		 733int efx_nic_init_interrupt(struct efx_nic *efx);
734void efx_nic_irq_test_start(struct efx_nic *efx);
735void efx_nic_fini_interrupt(struct efx_nic *efx);
86094f7f
BH		 736
737/* Falcon/Siena interrupts */
00aef986
JP		 738void efx_farch_irq_enable_master(struct efx_nic *efx);
739void efx_farch_irq_test_generate(struct efx_nic *efx);
740void efx_farch_irq_disable_master(struct efx_nic *efx);
741irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
742irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
743irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
152b6a62 744
eee6f6a9
BH		 745static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
746{
dd40781e 747 return ACCESS_ONCE(channel->event_test_cpu);
eee6f6a9
BH		 748}
749static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
750{
751 return ACCESS_ONCE(efx->last_irq_cpu);
752}
753
8ceee660 754/* Global Resources */
00aef986
JP		 755int efx_nic_flush_queues(struct efx_nic *efx);
756void siena_prepare_flush(struct efx_nic *efx);
757int efx_farch_fini_dmaq(struct efx_nic *efx);
758void siena_finish_flush(struct efx_nic *efx);
759void falcon_start_nic_stats(struct efx_nic *efx);
760void falcon_stop_nic_stats(struct efx_nic *efx);
761int falcon_reset_xaui(struct efx_nic *efx);
762void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
763void efx_farch_init_common(struct efx_nic *efx);
764void efx_ef10_handle_drain_event(struct efx_nic *efx);
00aef986 765void efx_farch_rx_push_indir_table(struct efx_nic *efx);
152b6a62
BH		 766
767int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
0d19a540 768 unsigned int len, gfp_t gfp_flags);
152b6a62 769void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
8ceee660 770
8c8661e4 771/* Tests */
86094f7f 772struct efx_farch_register_test {
152b6a62
BH		 773 unsigned address;
774 efx_oword_t mask;
775};
00aef986
JP		 776int efx_farch_test_registers(struct efx_nic *efx,
777 const struct efx_farch_register_test *regs,
778 size_t n_regs);
8c8661e4 779
00aef986
JP		 780size_t efx_nic_get_regs_len(struct efx_nic *efx);
781void efx_nic_get_regs(struct efx_nic *efx, void *buf);
5b98c1bf 782
00aef986
JP		 783size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
784 const unsigned long *mask, u8 *names);
785void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
786 const unsigned long *mask, u64 *stats,
787 const void *dma_buf, bool accumulate);
f8f3b5ae 788void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
cd0ecc9a 789
ab0115fc 790#define EFX_MAX_FLUSH_TIME 5000
8ceee660 791
00aef986
JP		 792void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
793 efx_qword_t *event);
8ceee660 794
744093c9 795#endif /* EFX_NIC_H */
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