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8ceee660 | 1 | /**************************************************************************** |
f7a6d2c4 | 2 | * Driver for Solarflare network controllers and boards |
8ceee660 | 3 | * Copyright 2005-2006 Fen Systems Ltd. |
f7a6d2c4 | 4 | * Copyright 2005-2013 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
738a8f4b | 15 | #include <linux/ipv6.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
738a8f4b | 17 | #include <net/ipv6.h> |
8ceee660 BH |
18 | #include <linux/if_ether.h> |
19 | #include <linux/highmem.h> | |
20 | #include "net_driver.h" | |
8ceee660 | 21 | #include "efx.h" |
744093c9 | 22 | #include "nic.h" |
8ceee660 | 23 | #include "workarounds.h" |
dfa50be9 | 24 | #include "ef10_regs.h" |
8ceee660 | 25 | |
4d566063 | 26 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
c3940999 TH |
27 | struct efx_tx_buffer *buffer, |
28 | unsigned int *pkts_compl, | |
29 | unsigned int *bytes_compl) | |
8ceee660 BH |
30 | { |
31 | if (buffer->unmap_len) { | |
0e33d870 | 32 | struct device *dma_dev = &tx_queue->efx->pci_dev->dev; |
cc12dac2 BH |
33 | dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len - |
34 | buffer->unmap_len); | |
7668ff9c | 35 | if (buffer->flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
36 | dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len, |
37 | DMA_TO_DEVICE); | |
8ceee660 | 38 | else |
0e33d870 BH |
39 | dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len, |
40 | DMA_TO_DEVICE); | |
8ceee660 | 41 | buffer->unmap_len = 0; |
8ceee660 BH |
42 | } |
43 | ||
7668ff9c | 44 | if (buffer->flags & EFX_TX_BUF_SKB) { |
c3940999 TH |
45 | (*pkts_compl)++; |
46 | (*bytes_compl) += buffer->skb->len; | |
8ceee660 | 47 | dev_kfree_skb_any((struct sk_buff *) buffer->skb); |
62776d03 BH |
48 | netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, |
49 | "TX queue %d transmission id %x complete\n", | |
50 | tx_queue->queue, tx_queue->read_count); | |
f7251a9c BH |
51 | } else if (buffer->flags & EFX_TX_BUF_HEAP) { |
52 | kfree(buffer->heap_buf); | |
8ceee660 | 53 | } |
7668ff9c | 54 | |
f7251a9c BH |
55 | buffer->len = 0; |
56 | buffer->flags = 0; | |
8ceee660 BH |
57 | } |
58 | ||
b9b39b62 | 59 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, |
740847da | 60 | struct sk_buff *skb); |
8ceee660 | 61 | |
63f19884 BH |
62 | static inline unsigned |
63 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
64 | { | |
65 | /* Depending on the NIC revision, we can use descriptor | |
66 | * lengths up to 8K or 8K-1. However, since PCI Express | |
67 | * devices must split read requests at 4K boundaries, there is | |
68 | * little benefit from using descriptors that cross those | |
69 | * boundaries and we keep things simple by not doing so. | |
70 | */ | |
5b6262d0 | 71 | unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1; |
63f19884 BH |
72 | |
73 | /* Work around hardware bug for unaligned buffers. */ | |
74 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
75 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
7e6d06f0 BH |
80 | unsigned int efx_tx_max_skb_descs(struct efx_nic *efx) |
81 | { | |
82 | /* Header and payload descriptor for each output segment, plus | |
83 | * one for every input fragment boundary within a segment | |
84 | */ | |
85 | unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS; | |
86 | ||
dfa50be9 BH |
87 | /* Possibly one more per segment for the alignment workaround, |
88 | * or for option descriptors | |
89 | */ | |
90 | if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0) | |
7e6d06f0 BH |
91 | max_descs += EFX_TSO_MAX_SEGS; |
92 | ||
93 | /* Possibly more for PCIe page boundaries within input fragments */ | |
94 | if (PAGE_SIZE > EFX_PAGE_SIZE) | |
95 | max_descs += max_t(unsigned int, MAX_SKB_FRAGS, | |
96 | DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE)); | |
97 | ||
98 | return max_descs; | |
99 | } | |
100 | ||
14bf718f BH |
101 | /* Get partner of a TX queue, seen as part of the same net core queue */ |
102 | static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue) | |
103 | { | |
104 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) | |
105 | return tx_queue - EFX_TXQ_TYPE_OFFLOAD; | |
106 | else | |
107 | return tx_queue + EFX_TXQ_TYPE_OFFLOAD; | |
108 | } | |
109 | ||
110 | static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1) | |
111 | { | |
112 | /* We need to consider both queues that the net core sees as one */ | |
113 | struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1); | |
114 | struct efx_nic *efx = txq1->efx; | |
115 | unsigned int fill_level; | |
116 | ||
117 | fill_level = max(txq1->insert_count - txq1->old_read_count, | |
118 | txq2->insert_count - txq2->old_read_count); | |
119 | if (likely(fill_level < efx->txq_stop_thresh)) | |
120 | return; | |
121 | ||
122 | /* We used the stale old_read_count above, which gives us a | |
123 | * pessimistic estimate of the fill level (which may even | |
124 | * validly be >= efx->txq_entries). Now try again using | |
125 | * read_count (more likely to be a cache miss). | |
126 | * | |
127 | * If we read read_count and then conditionally stop the | |
128 | * queue, it is possible for the completion path to race with | |
129 | * us and complete all outstanding descriptors in the middle, | |
130 | * after which there will be no more completions to wake it. | |
131 | * Therefore we stop the queue first, then read read_count | |
132 | * (with a memory barrier to ensure the ordering), then | |
133 | * restart the queue if the fill level turns out to be low | |
134 | * enough. | |
135 | */ | |
136 | netif_tx_stop_queue(txq1->core_txq); | |
137 | smp_mb(); | |
138 | txq1->old_read_count = ACCESS_ONCE(txq1->read_count); | |
139 | txq2->old_read_count = ACCESS_ONCE(txq2->read_count); | |
140 | ||
141 | fill_level = max(txq1->insert_count - txq1->old_read_count, | |
142 | txq2->insert_count - txq2->old_read_count); | |
143 | EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries); | |
144 | if (likely(fill_level < efx->txq_stop_thresh)) { | |
145 | smp_mb(); | |
146 | if (likely(!efx->loopback_selftest)) | |
147 | netif_tx_start_queue(txq1->core_txq); | |
148 | } | |
149 | } | |
150 | ||
8ceee660 BH |
151 | /* |
152 | * Add a socket buffer to a TX queue | |
153 | * | |
154 | * This maps all fragments of a socket buffer for DMA and adds them to | |
155 | * the TX queue. The queue's insert pointer will be incremented by | |
156 | * the number of fragments in the socket buffer. | |
157 | * | |
158 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
159 | * the queue's insert pointer will be restored to its original value. | |
160 | * | |
497f5ba3 BH |
161 | * This function is split out from efx_hard_start_xmit to allow the |
162 | * loopback test to direct packets via specific TX queues. | |
163 | * | |
14bf718f | 164 | * Returns NETDEV_TX_OK. |
8ceee660 BH |
165 | * You must hold netif_tx_lock() to call this function. |
166 | */ | |
497f5ba3 | 167 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
8ceee660 BH |
168 | { |
169 | struct efx_nic *efx = tx_queue->efx; | |
0e33d870 | 170 | struct device *dma_dev = &efx->pci_dev->dev; |
8ceee660 BH |
171 | struct efx_tx_buffer *buffer; |
172 | skb_frag_t *fragment; | |
14bf718f | 173 | unsigned int len, unmap_len = 0, insert_ptr; |
8ceee660 BH |
174 | dma_addr_t dma_addr, unmap_addr = 0; |
175 | unsigned int dma_len; | |
7668ff9c | 176 | unsigned short dma_flags; |
14bf718f | 177 | int i = 0; |
8ceee660 BH |
178 | |
179 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
180 | ||
9bc183d7 | 181 | if (skb_shinfo(skb)->gso_size) |
b9b39b62 BH |
182 | return efx_enqueue_skb_tso(tx_queue, skb); |
183 | ||
8ceee660 BH |
184 | /* Get size of the initial fragment */ |
185 | len = skb_headlen(skb); | |
186 | ||
bb145a9e BH |
187 | /* Pad if necessary */ |
188 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
189 | EFX_BUG_ON_PARANOID(skb->data_len); | |
190 | len = 32 + 1; | |
191 | if (skb_pad(skb, len - skb->len)) | |
192 | return NETDEV_TX_OK; | |
193 | } | |
194 | ||
0e33d870 | 195 | /* Map for DMA. Use dma_map_single rather than dma_map_page |
8ceee660 BH |
196 | * since this is more efficient on machines with sparse |
197 | * memory. | |
198 | */ | |
7668ff9c | 199 | dma_flags = EFX_TX_BUF_MAP_SINGLE; |
0e33d870 | 200 | dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE); |
8ceee660 BH |
201 | |
202 | /* Process all fragments */ | |
203 | while (1) { | |
0e33d870 BH |
204 | if (unlikely(dma_mapping_error(dma_dev, dma_addr))) |
205 | goto dma_err; | |
8ceee660 BH |
206 | |
207 | /* Store fields for marking in the per-fragment final | |
208 | * descriptor */ | |
209 | unmap_len = len; | |
210 | unmap_addr = dma_addr; | |
211 | ||
212 | /* Add to TX queue, splitting across DMA boundaries */ | |
213 | do { | |
ecc910f5 | 214 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 215 | buffer = &tx_queue->buffer[insert_ptr]; |
7668ff9c | 216 | EFX_BUG_ON_PARANOID(buffer->flags); |
8ceee660 | 217 | EFX_BUG_ON_PARANOID(buffer->len); |
8ceee660 BH |
218 | EFX_BUG_ON_PARANOID(buffer->unmap_len); |
219 | ||
63f19884 BH |
220 | dma_len = efx_max_tx_len(efx, dma_addr); |
221 | if (likely(dma_len >= len)) | |
8ceee660 BH |
222 | dma_len = len; |
223 | ||
8ceee660 BH |
224 | /* Fill out per descriptor fields */ |
225 | buffer->len = dma_len; | |
226 | buffer->dma_addr = dma_addr; | |
7668ff9c | 227 | buffer->flags = EFX_TX_BUF_CONT; |
8ceee660 BH |
228 | len -= dma_len; |
229 | dma_addr += dma_len; | |
230 | ++tx_queue->insert_count; | |
231 | } while (len); | |
232 | ||
233 | /* Transfer ownership of the unmapping to the final buffer */ | |
7668ff9c | 234 | buffer->flags = EFX_TX_BUF_CONT | dma_flags; |
8ceee660 BH |
235 | buffer->unmap_len = unmap_len; |
236 | unmap_len = 0; | |
237 | ||
238 | /* Get address and size of next fragment */ | |
239 | if (i >= skb_shinfo(skb)->nr_frags) | |
240 | break; | |
241 | fragment = &skb_shinfo(skb)->frags[i]; | |
9e903e08 | 242 | len = skb_frag_size(fragment); |
8ceee660 BH |
243 | i++; |
244 | /* Map for DMA */ | |
7668ff9c | 245 | dma_flags = 0; |
0e33d870 | 246 | dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len, |
5d6bcdfe | 247 | DMA_TO_DEVICE); |
8ceee660 BH |
248 | } |
249 | ||
250 | /* Transfer ownership of the skb to the final buffer */ | |
251 | buffer->skb = skb; | |
7668ff9c | 252 | buffer->flags = EFX_TX_BUF_SKB | dma_flags; |
8ceee660 | 253 | |
c3940999 TH |
254 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
255 | ||
8ceee660 | 256 | /* Pass off to hardware */ |
152b6a62 | 257 | efx_nic_push_buffers(tx_queue); |
8ceee660 | 258 | |
14bf718f BH |
259 | efx_tx_maybe_stop_queue(tx_queue); |
260 | ||
8ceee660 BH |
261 | return NETDEV_TX_OK; |
262 | ||
0e33d870 | 263 | dma_err: |
62776d03 BH |
264 | netif_err(efx, tx_err, efx->net_dev, |
265 | " TX queue %d could not map skb with %d bytes %d " | |
266 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
267 | skb_shinfo(skb)->nr_frags + 1); | |
8ceee660 BH |
268 | |
269 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
9bc183d7 | 270 | dev_kfree_skb_any(skb); |
8ceee660 | 271 | |
8ceee660 BH |
272 | /* Work backwards until we hit the original insert pointer value */ |
273 | while (tx_queue->insert_count != tx_queue->write_count) { | |
c3940999 | 274 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 275 | --tx_queue->insert_count; |
ecc910f5 | 276 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 277 | buffer = &tx_queue->buffer[insert_ptr]; |
c3940999 | 278 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
8ceee660 BH |
279 | } |
280 | ||
281 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 | 282 | if (unmap_len) { |
7668ff9c | 283 | if (dma_flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
284 | dma_unmap_single(dma_dev, unmap_addr, unmap_len, |
285 | DMA_TO_DEVICE); | |
ecbd95c1 | 286 | else |
0e33d870 BH |
287 | dma_unmap_page(dma_dev, unmap_addr, unmap_len, |
288 | DMA_TO_DEVICE); | |
ecbd95c1 | 289 | } |
8ceee660 | 290 | |
14bf718f | 291 | return NETDEV_TX_OK; |
8ceee660 BH |
292 | } |
293 | ||
294 | /* Remove packets from the TX queue | |
295 | * | |
296 | * This removes packets from the TX queue, up to and including the | |
297 | * specified index. | |
298 | */ | |
4d566063 | 299 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
c3940999 TH |
300 | unsigned int index, |
301 | unsigned int *pkts_compl, | |
302 | unsigned int *bytes_compl) | |
8ceee660 BH |
303 | { |
304 | struct efx_nic *efx = tx_queue->efx; | |
305 | unsigned int stop_index, read_ptr; | |
8ceee660 | 306 | |
ecc910f5 SH |
307 | stop_index = (index + 1) & tx_queue->ptr_mask; |
308 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; | |
8ceee660 BH |
309 | |
310 | while (read_ptr != stop_index) { | |
311 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
ba8977bd BH |
312 | |
313 | if (!(buffer->flags & EFX_TX_BUF_OPTION) && | |
314 | unlikely(buffer->len == 0)) { | |
62776d03 BH |
315 | netif_err(efx, tx_err, efx->net_dev, |
316 | "TX queue %d spurious TX completion id %x\n", | |
317 | tx_queue->queue, read_ptr); | |
8ceee660 BH |
318 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
319 | return; | |
320 | } | |
321 | ||
c3940999 | 322 | efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl); |
8ceee660 BH |
323 | |
324 | ++tx_queue->read_count; | |
ecc910f5 | 325 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
8ceee660 BH |
326 | } |
327 | } | |
328 | ||
8ceee660 BH |
329 | /* Initiate a packet transmission. We use one channel per CPU |
330 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
331 | * completion events will be directed back to the CPU that transmitted | |
332 | * the packet, which should be cache-efficient. | |
333 | * | |
334 | * Context: non-blocking. | |
335 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
336 | * OS to free the skb. | |
337 | */ | |
61357325 | 338 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
2d0cc56d | 339 | struct net_device *net_dev) |
8ceee660 | 340 | { |
767e468c | 341 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 | 342 | struct efx_tx_queue *tx_queue; |
94b274bf | 343 | unsigned index, type; |
60ac1065 | 344 | |
e4abce85 | 345 | EFX_WARN_ON_PARANOID(!netif_device_present(net_dev)); |
a7ef5933 | 346 | |
7c236c43 SH |
347 | /* PTP "event" packet */ |
348 | if (unlikely(efx_xmit_with_hwtstamp(skb)) && | |
349 | unlikely(efx_ptp_is_ptp_tx(efx, skb))) { | |
350 | return efx_ptp_tx(efx, skb); | |
351 | } | |
352 | ||
94b274bf BH |
353 | index = skb_get_queue_mapping(skb); |
354 | type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0; | |
355 | if (index >= efx->n_tx_channels) { | |
356 | index -= efx->n_tx_channels; | |
357 | type |= EFX_TXQ_TYPE_HIGHPRI; | |
358 | } | |
359 | tx_queue = efx_get_tx_queue(efx, index, type); | |
60ac1065 | 360 | |
497f5ba3 | 361 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
362 | } |
363 | ||
60031fcc BH |
364 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
365 | { | |
94b274bf BH |
366 | struct efx_nic *efx = tx_queue->efx; |
367 | ||
60031fcc | 368 | /* Must be inverse of queue lookup in efx_hard_start_xmit() */ |
94b274bf BH |
369 | tx_queue->core_txq = |
370 | netdev_get_tx_queue(efx->net_dev, | |
371 | tx_queue->queue / EFX_TXQ_TYPES + | |
372 | ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ? | |
373 | efx->n_tx_channels : 0)); | |
374 | } | |
375 | ||
376 | int efx_setup_tc(struct net_device *net_dev, u8 num_tc) | |
377 | { | |
378 | struct efx_nic *efx = netdev_priv(net_dev); | |
379 | struct efx_channel *channel; | |
380 | struct efx_tx_queue *tx_queue; | |
381 | unsigned tc; | |
382 | int rc; | |
383 | ||
384 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC) | |
385 | return -EINVAL; | |
386 | ||
387 | if (num_tc == net_dev->num_tc) | |
388 | return 0; | |
389 | ||
390 | for (tc = 0; tc < num_tc; tc++) { | |
391 | net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels; | |
392 | net_dev->tc_to_txq[tc].count = efx->n_tx_channels; | |
393 | } | |
394 | ||
395 | if (num_tc > net_dev->num_tc) { | |
396 | /* Initialise high-priority queues as necessary */ | |
397 | efx_for_each_channel(channel, efx) { | |
398 | efx_for_each_possible_channel_tx_queue(tx_queue, | |
399 | channel) { | |
400 | if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI)) | |
401 | continue; | |
402 | if (!tx_queue->buffer) { | |
403 | rc = efx_probe_tx_queue(tx_queue); | |
404 | if (rc) | |
405 | return rc; | |
406 | } | |
407 | if (!tx_queue->initialised) | |
408 | efx_init_tx_queue(tx_queue); | |
409 | efx_init_tx_queue_core_txq(tx_queue); | |
410 | } | |
411 | } | |
412 | } else { | |
413 | /* Reduce number of classes before number of queues */ | |
414 | net_dev->num_tc = num_tc; | |
415 | } | |
416 | ||
417 | rc = netif_set_real_num_tx_queues(net_dev, | |
418 | max_t(int, num_tc, 1) * | |
419 | efx->n_tx_channels); | |
420 | if (rc) | |
421 | return rc; | |
422 | ||
423 | /* Do not destroy high-priority queues when they become | |
424 | * unused. We would have to flush them first, and it is | |
425 | * fairly difficult to flush a subset of TX queues. Leave | |
426 | * it to efx_fini_channels(). | |
427 | */ | |
428 | ||
429 | net_dev->num_tc = num_tc; | |
430 | return 0; | |
60031fcc BH |
431 | } |
432 | ||
8ceee660 BH |
433 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) |
434 | { | |
435 | unsigned fill_level; | |
436 | struct efx_nic *efx = tx_queue->efx; | |
14bf718f | 437 | struct efx_tx_queue *txq2; |
c3940999 | 438 | unsigned int pkts_compl = 0, bytes_compl = 0; |
8ceee660 | 439 | |
ecc910f5 | 440 | EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); |
8ceee660 | 441 | |
c3940999 TH |
442 | efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl); |
443 | netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl); | |
8ceee660 | 444 | |
02e12165 BH |
445 | if (pkts_compl > 1) |
446 | ++tx_queue->merge_events; | |
447 | ||
14bf718f BH |
448 | /* See if we need to restart the netif queue. This memory |
449 | * barrier ensures that we write read_count (inside | |
450 | * efx_dequeue_buffers()) before reading the queue status. | |
451 | */ | |
8ceee660 | 452 | smp_mb(); |
c04bfc6b | 453 | if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && |
9d1aea62 | 454 | likely(efx->port_enabled) && |
e4abce85 | 455 | likely(netif_device_present(efx->net_dev))) { |
14bf718f BH |
456 | txq2 = efx_tx_queue_partner(tx_queue); |
457 | fill_level = max(tx_queue->insert_count - tx_queue->read_count, | |
458 | txq2->insert_count - txq2->read_count); | |
459 | if (fill_level <= efx->txq_wake_thresh) | |
c04bfc6b | 460 | netif_tx_wake_queue(tx_queue->core_txq); |
8ceee660 | 461 | } |
cd38557d BH |
462 | |
463 | /* Check whether the hardware queue is now empty */ | |
464 | if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { | |
465 | tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); | |
466 | if (tx_queue->read_count == tx_queue->old_write_count) { | |
467 | smp_mb(); | |
468 | tx_queue->empty_read_count = | |
469 | tx_queue->read_count | EFX_EMPTY_COUNT_VALID; | |
470 | } | |
471 | } | |
8ceee660 BH |
472 | } |
473 | ||
f7251a9c BH |
474 | /* Size of page-based TSO header buffers. Larger blocks must be |
475 | * allocated from the heap. | |
476 | */ | |
477 | #define TSOH_STD_SIZE 128 | |
478 | #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE) | |
479 | ||
480 | /* At most half the descriptors in the queue at any time will refer to | |
481 | * a TSO header buffer, since they must always be followed by a | |
482 | * payload descriptor referring to an skb. | |
483 | */ | |
484 | static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue) | |
485 | { | |
486 | return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE); | |
487 | } | |
488 | ||
8ceee660 BH |
489 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) |
490 | { | |
491 | struct efx_nic *efx = tx_queue->efx; | |
ecc910f5 | 492 | unsigned int entries; |
7668ff9c | 493 | int rc; |
8ceee660 | 494 | |
ecc910f5 SH |
495 | /* Create the smallest power-of-two aligned ring */ |
496 | entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); | |
497 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
498 | tx_queue->ptr_mask = entries - 1; | |
499 | ||
500 | netif_dbg(efx, probe, efx->net_dev, | |
501 | "creating TX queue %d size %#x mask %#x\n", | |
502 | tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); | |
8ceee660 BH |
503 | |
504 | /* Allocate software ring */ | |
c2e4e25a | 505 | tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer), |
ecc910f5 | 506 | GFP_KERNEL); |
60ac1065 BH |
507 | if (!tx_queue->buffer) |
508 | return -ENOMEM; | |
8ceee660 | 509 | |
f7251a9c BH |
510 | if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) { |
511 | tx_queue->tsoh_page = | |
512 | kcalloc(efx_tsoh_page_count(tx_queue), | |
513 | sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL); | |
514 | if (!tx_queue->tsoh_page) { | |
515 | rc = -ENOMEM; | |
516 | goto fail1; | |
517 | } | |
518 | } | |
519 | ||
8ceee660 | 520 | /* Allocate hardware ring */ |
152b6a62 | 521 | rc = efx_nic_probe_tx(tx_queue); |
8ceee660 | 522 | if (rc) |
f7251a9c | 523 | goto fail2; |
8ceee660 BH |
524 | |
525 | return 0; | |
526 | ||
f7251a9c BH |
527 | fail2: |
528 | kfree(tx_queue->tsoh_page); | |
529 | tx_queue->tsoh_page = NULL; | |
530 | fail1: | |
8ceee660 BH |
531 | kfree(tx_queue->buffer); |
532 | tx_queue->buffer = NULL; | |
8ceee660 BH |
533 | return rc; |
534 | } | |
535 | ||
bc3c90a2 | 536 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 | 537 | { |
62776d03 BH |
538 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
539 | "initialising TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
540 | |
541 | tx_queue->insert_count = 0; | |
542 | tx_queue->write_count = 0; | |
cd38557d | 543 | tx_queue->old_write_count = 0; |
8ceee660 BH |
544 | tx_queue->read_count = 0; |
545 | tx_queue->old_read_count = 0; | |
cd38557d | 546 | tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; |
8ceee660 BH |
547 | |
548 | /* Set up TX descriptor ring */ | |
152b6a62 | 549 | efx_nic_init_tx(tx_queue); |
94b274bf BH |
550 | |
551 | tx_queue->initialised = true; | |
8ceee660 BH |
552 | } |
553 | ||
e42c3d85 | 554 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
555 | { |
556 | struct efx_tx_buffer *buffer; | |
557 | ||
e42c3d85 BH |
558 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
559 | "shutting down TX queue %d\n", tx_queue->queue); | |
560 | ||
8ceee660 BH |
561 | if (!tx_queue->buffer) |
562 | return; | |
563 | ||
564 | /* Free any buffers left in the ring */ | |
565 | while (tx_queue->read_count != tx_queue->write_count) { | |
c3940999 | 566 | unsigned int pkts_compl = 0, bytes_compl = 0; |
ecc910f5 | 567 | buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; |
c3940999 | 568 | efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl); |
8ceee660 BH |
569 | |
570 | ++tx_queue->read_count; | |
571 | } | |
c3940999 | 572 | netdev_tx_reset_queue(tx_queue->core_txq); |
8ceee660 BH |
573 | } |
574 | ||
8ceee660 BH |
575 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) |
576 | { | |
f7251a9c BH |
577 | int i; |
578 | ||
94b274bf BH |
579 | if (!tx_queue->buffer) |
580 | return; | |
581 | ||
62776d03 BH |
582 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
583 | "destroying TX queue %d\n", tx_queue->queue); | |
152b6a62 | 584 | efx_nic_remove_tx(tx_queue); |
8ceee660 | 585 | |
f7251a9c BH |
586 | if (tx_queue->tsoh_page) { |
587 | for (i = 0; i < efx_tsoh_page_count(tx_queue); i++) | |
588 | efx_nic_free_buffer(tx_queue->efx, | |
589 | &tx_queue->tsoh_page[i]); | |
590 | kfree(tx_queue->tsoh_page); | |
591 | tx_queue->tsoh_page = NULL; | |
592 | } | |
593 | ||
8ceee660 BH |
594 | kfree(tx_queue->buffer); |
595 | tx_queue->buffer = NULL; | |
8ceee660 BH |
596 | } |
597 | ||
598 | ||
b9b39b62 BH |
599 | /* Efx TCP segmentation acceleration. |
600 | * | |
601 | * Why? Because by doing it here in the driver we can go significantly | |
602 | * faster than the GSO. | |
603 | * | |
604 | * Requires TX checksum offload support. | |
605 | */ | |
606 | ||
607 | /* Number of bytes inserted at the start of a TSO header buffer, | |
608 | * similar to NET_IP_ALIGN. | |
609 | */ | |
13e9ab11 | 610 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
b9b39b62 BH |
611 | #define TSOH_OFFSET 0 |
612 | #else | |
613 | #define TSOH_OFFSET NET_IP_ALIGN | |
614 | #endif | |
615 | ||
b9b39b62 | 616 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) |
b9b39b62 BH |
617 | |
618 | /** | |
619 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 620 | * @out_len: Remaining length in current segment |
b9b39b62 | 621 | * @seqnum: Current sequence number |
23d9e60b | 622 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 623 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
624 | * @dma_addr: DMA address of current position |
625 | * @in_len: Remaining length in current SKB fragment | |
626 | * @unmap_len: Length of SKB fragment | |
627 | * @unmap_addr: DMA address of SKB fragment | |
7668ff9c | 628 | * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0 |
738a8f4b | 629 | * @protocol: Network protocol (after any VLAN header) |
9714284f BH |
630 | * @ip_off: Offset of IP header |
631 | * @tcp_off: Offset of TCP header | |
23d9e60b | 632 | * @header_len: Number of bytes of header |
53cb13c6 | 633 | * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload |
dfa50be9 BH |
634 | * @header_dma_addr: Header DMA address, when using option descriptors |
635 | * @header_unmap_len: Header DMA mapped length, or 0 if not using option | |
636 | * descriptors | |
b9b39b62 BH |
637 | * |
638 | * The state used during segmentation. It is put into this data structure | |
639 | * just to make it easy to pass into inline functions. | |
640 | */ | |
641 | struct tso_state { | |
23d9e60b BH |
642 | /* Output position */ |
643 | unsigned out_len; | |
b9b39b62 | 644 | unsigned seqnum; |
dfa50be9 | 645 | u16 ipv4_id; |
b9b39b62 BH |
646 | unsigned packet_space; |
647 | ||
23d9e60b BH |
648 | /* Input position */ |
649 | dma_addr_t dma_addr; | |
650 | unsigned in_len; | |
651 | unsigned unmap_len; | |
652 | dma_addr_t unmap_addr; | |
7668ff9c | 653 | unsigned short dma_flags; |
23d9e60b | 654 | |
738a8f4b | 655 | __be16 protocol; |
9714284f BH |
656 | unsigned int ip_off; |
657 | unsigned int tcp_off; | |
23d9e60b | 658 | unsigned header_len; |
53cb13c6 | 659 | unsigned int ip_base_len; |
dfa50be9 BH |
660 | dma_addr_t header_dma_addr; |
661 | unsigned int header_unmap_len; | |
b9b39b62 BH |
662 | }; |
663 | ||
664 | ||
665 | /* | |
666 | * Verify that our various assumptions about sk_buffs and the conditions | |
738a8f4b | 667 | * under which TSO will be attempted hold true. Return the protocol number. |
b9b39b62 | 668 | */ |
738a8f4b | 669 | static __be16 efx_tso_check_protocol(struct sk_buff *skb) |
b9b39b62 | 670 | { |
740847da BH |
671 | __be16 protocol = skb->protocol; |
672 | ||
b9b39b62 | 673 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
674 | protocol); |
675 | if (protocol == htons(ETH_P_8021Q)) { | |
740847da BH |
676 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; |
677 | protocol = veh->h_vlan_encapsulated_proto; | |
740847da BH |
678 | } |
679 | ||
738a8f4b BH |
680 | if (protocol == htons(ETH_P_IP)) { |
681 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); | |
682 | } else { | |
683 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); | |
684 | EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); | |
685 | } | |
b9b39b62 BH |
686 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) |
687 | + (tcp_hdr(skb)->doff << 2u)) > | |
688 | skb_headlen(skb)); | |
738a8f4b BH |
689 | |
690 | return protocol; | |
b9b39b62 BH |
691 | } |
692 | ||
f7251a9c BH |
693 | static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue, |
694 | struct efx_tx_buffer *buffer, unsigned int len) | |
b9b39b62 | 695 | { |
f7251a9c | 696 | u8 *result; |
b9b39b62 | 697 | |
f7251a9c BH |
698 | EFX_BUG_ON_PARANOID(buffer->len); |
699 | EFX_BUG_ON_PARANOID(buffer->flags); | |
700 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
b9b39b62 | 701 | |
f7251a9c BH |
702 | if (likely(len <= TSOH_STD_SIZE - TSOH_OFFSET)) { |
703 | unsigned index = | |
704 | (tx_queue->insert_count & tx_queue->ptr_mask) / 2; | |
705 | struct efx_buffer *page_buf = | |
706 | &tx_queue->tsoh_page[index / TSOH_PER_PAGE]; | |
707 | unsigned offset = | |
708 | TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + TSOH_OFFSET; | |
b9b39b62 | 709 | |
f7251a9c | 710 | if (unlikely(!page_buf->addr) && |
0d19a540 BH |
711 | efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE, |
712 | GFP_ATOMIC)) | |
f7251a9c | 713 | return NULL; |
b9b39b62 | 714 | |
f7251a9c BH |
715 | result = (u8 *)page_buf->addr + offset; |
716 | buffer->dma_addr = page_buf->dma_addr + offset; | |
717 | buffer->flags = EFX_TX_BUF_CONT; | |
718 | } else { | |
719 | tx_queue->tso_long_headers++; | |
b9b39b62 | 720 | |
f7251a9c BH |
721 | buffer->heap_buf = kmalloc(TSOH_OFFSET + len, GFP_ATOMIC); |
722 | if (unlikely(!buffer->heap_buf)) | |
723 | return NULL; | |
724 | result = (u8 *)buffer->heap_buf + TSOH_OFFSET; | |
725 | buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP; | |
b9b39b62 BH |
726 | } |
727 | ||
f7251a9c | 728 | buffer->len = len; |
b9b39b62 | 729 | |
f7251a9c | 730 | return result; |
b9b39b62 BH |
731 | } |
732 | ||
733 | /** | |
734 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
735 | * @tx_queue: Efx TX queue | |
736 | * @dma_addr: DMA address of fragment | |
737 | * @len: Length of fragment | |
ecbd95c1 | 738 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 | 739 | * |
14bf718f | 740 | * Push descriptors onto the TX queue. |
b9b39b62 | 741 | */ |
14bf718f BH |
742 | static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue, |
743 | dma_addr_t dma_addr, unsigned len, | |
744 | struct efx_tx_buffer **final_buffer) | |
b9b39b62 BH |
745 | { |
746 | struct efx_tx_buffer *buffer; | |
747 | struct efx_nic *efx = tx_queue->efx; | |
14bf718f | 748 | unsigned dma_len, insert_ptr; |
b9b39b62 BH |
749 | |
750 | EFX_BUG_ON_PARANOID(len <= 0); | |
751 | ||
b9b39b62 | 752 | while (1) { |
ecc910f5 | 753 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
b9b39b62 BH |
754 | buffer = &tx_queue->buffer[insert_ptr]; |
755 | ++tx_queue->insert_count; | |
756 | ||
757 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
ecc910f5 SH |
758 | tx_queue->read_count >= |
759 | efx->txq_entries); | |
b9b39b62 | 760 | |
b9b39b62 BH |
761 | EFX_BUG_ON_PARANOID(buffer->len); |
762 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
7668ff9c | 763 | EFX_BUG_ON_PARANOID(buffer->flags); |
b9b39b62 BH |
764 | |
765 | buffer->dma_addr = dma_addr; | |
766 | ||
63f19884 | 767 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
768 | |
769 | /* If there is enough space to send then do so */ | |
770 | if (dma_len >= len) | |
771 | break; | |
772 | ||
7668ff9c BH |
773 | buffer->len = dma_len; |
774 | buffer->flags = EFX_TX_BUF_CONT; | |
b9b39b62 BH |
775 | dma_addr += dma_len; |
776 | len -= dma_len; | |
777 | } | |
778 | ||
779 | EFX_BUG_ON_PARANOID(!len); | |
780 | buffer->len = len; | |
ecbd95c1 | 781 | *final_buffer = buffer; |
b9b39b62 BH |
782 | } |
783 | ||
784 | ||
785 | /* | |
786 | * Put a TSO header into the TX queue. | |
787 | * | |
788 | * This is special-cased because we know that it is small enough to fit in | |
789 | * a single fragment, and we know it doesn't cross a page boundary. It | |
790 | * also allows us to not worry about end-of-packet etc. | |
791 | */ | |
f7251a9c BH |
792 | static int efx_tso_put_header(struct efx_tx_queue *tx_queue, |
793 | struct efx_tx_buffer *buffer, u8 *header) | |
b9b39b62 | 794 | { |
f7251a9c BH |
795 | if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) { |
796 | buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev, | |
797 | header, buffer->len, | |
798 | DMA_TO_DEVICE); | |
799 | if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev, | |
800 | buffer->dma_addr))) { | |
801 | kfree(buffer->heap_buf); | |
802 | buffer->len = 0; | |
803 | buffer->flags = 0; | |
804 | return -ENOMEM; | |
805 | } | |
806 | buffer->unmap_len = buffer->len; | |
807 | buffer->flags |= EFX_TX_BUF_MAP_SINGLE; | |
808 | } | |
b9b39b62 BH |
809 | |
810 | ++tx_queue->insert_count; | |
f7251a9c | 811 | return 0; |
b9b39b62 BH |
812 | } |
813 | ||
814 | ||
f7251a9c BH |
815 | /* Remove buffers put into a tx_queue. None of the buffers must have |
816 | * an skb attached. | |
817 | */ | |
b9b39b62 BH |
818 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) |
819 | { | |
820 | struct efx_tx_buffer *buffer; | |
821 | ||
822 | /* Work backwards until we hit the original insert pointer value */ | |
823 | while (tx_queue->insert_count != tx_queue->write_count) { | |
824 | --tx_queue->insert_count; | |
825 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
ecc910f5 | 826 | tx_queue->ptr_mask]; |
f7251a9c | 827 | efx_dequeue_buffer(tx_queue, buffer, NULL, NULL); |
b9b39b62 BH |
828 | } |
829 | } | |
830 | ||
831 | ||
832 | /* Parse the SKB header and initialise state. */ | |
c78c39e6 BH |
833 | static int tso_start(struct tso_state *st, struct efx_nic *efx, |
834 | const struct sk_buff *skb) | |
b9b39b62 | 835 | { |
dfa50be9 BH |
836 | bool use_options = efx_nic_rev(efx) >= EFX_REV_HUNT_A0; |
837 | struct device *dma_dev = &efx->pci_dev->dev; | |
c78c39e6 | 838 | unsigned int header_len, in_len; |
dfa50be9 | 839 | dma_addr_t dma_addr; |
c78c39e6 | 840 | |
9714284f BH |
841 | st->ip_off = skb_network_header(skb) - skb->data; |
842 | st->tcp_off = skb_transport_header(skb) - skb->data; | |
c78c39e6 BH |
843 | header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u); |
844 | in_len = skb_headlen(skb) - header_len; | |
845 | st->header_len = header_len; | |
846 | st->in_len = in_len; | |
53cb13c6 | 847 | if (st->protocol == htons(ETH_P_IP)) { |
9714284f | 848 | st->ip_base_len = st->header_len - st->ip_off; |
738a8f4b | 849 | st->ipv4_id = ntohs(ip_hdr(skb)->id); |
53cb13c6 | 850 | } else { |
9714284f | 851 | st->ip_base_len = st->header_len - st->tcp_off; |
738a8f4b | 852 | st->ipv4_id = 0; |
53cb13c6 | 853 | } |
b9b39b62 BH |
854 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
855 | ||
856 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
857 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
858 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
859 | ||
c78c39e6 BH |
860 | st->out_len = skb->len - header_len; |
861 | ||
dfa50be9 BH |
862 | if (!use_options) { |
863 | st->header_unmap_len = 0; | |
864 | ||
865 | if (likely(in_len == 0)) { | |
866 | st->dma_flags = 0; | |
867 | st->unmap_len = 0; | |
868 | return 0; | |
869 | } | |
870 | ||
871 | dma_addr = dma_map_single(dma_dev, skb->data + header_len, | |
872 | in_len, DMA_TO_DEVICE); | |
873 | st->dma_flags = EFX_TX_BUF_MAP_SINGLE; | |
874 | st->dma_addr = dma_addr; | |
875 | st->unmap_addr = dma_addr; | |
876 | st->unmap_len = in_len; | |
877 | } else { | |
878 | dma_addr = dma_map_single(dma_dev, skb->data, | |
879 | skb_headlen(skb), DMA_TO_DEVICE); | |
880 | st->header_dma_addr = dma_addr; | |
881 | st->header_unmap_len = skb_headlen(skb); | |
c78c39e6 | 882 | st->dma_flags = 0; |
dfa50be9 BH |
883 | st->dma_addr = dma_addr + header_len; |
884 | st->unmap_len = 0; | |
c78c39e6 BH |
885 | } |
886 | ||
dfa50be9 | 887 | return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0; |
b9b39b62 BH |
888 | } |
889 | ||
4d566063 BH |
890 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
891 | skb_frag_t *frag) | |
b9b39b62 | 892 | { |
4a22c4c9 | 893 | st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0, |
9e903e08 | 894 | skb_frag_size(frag), DMA_TO_DEVICE); |
5d6bcdfe | 895 | if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) { |
7668ff9c | 896 | st->dma_flags = 0; |
9e903e08 ED |
897 | st->unmap_len = skb_frag_size(frag); |
898 | st->in_len = skb_frag_size(frag); | |
23d9e60b | 899 | st->dma_addr = st->unmap_addr; |
ecbd95c1 BH |
900 | return 0; |
901 | } | |
902 | return -ENOMEM; | |
903 | } | |
904 | ||
b9b39b62 BH |
905 | |
906 | /** | |
907 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
908 | * @tx_queue: Efx TX queue | |
909 | * @skb: Socket buffer | |
910 | * @st: TSO state | |
911 | * | |
912 | * Form descriptors for the current fragment, until we reach the end | |
14bf718f | 913 | * of fragment or end-of-packet. |
b9b39b62 | 914 | */ |
14bf718f BH |
915 | static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
916 | const struct sk_buff *skb, | |
917 | struct tso_state *st) | |
b9b39b62 | 918 | { |
ecbd95c1 | 919 | struct efx_tx_buffer *buffer; |
14bf718f | 920 | int n; |
b9b39b62 | 921 | |
23d9e60b | 922 | if (st->in_len == 0) |
14bf718f | 923 | return; |
b9b39b62 | 924 | if (st->packet_space == 0) |
14bf718f | 925 | return; |
b9b39b62 | 926 | |
23d9e60b | 927 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
928 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
929 | ||
23d9e60b | 930 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
931 | |
932 | st->packet_space -= n; | |
23d9e60b BH |
933 | st->out_len -= n; |
934 | st->in_len -= n; | |
b9b39b62 | 935 | |
14bf718f | 936 | efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
b9b39b62 | 937 | |
14bf718f BH |
938 | if (st->out_len == 0) { |
939 | /* Transfer ownership of the skb */ | |
940 | buffer->skb = skb; | |
941 | buffer->flags = EFX_TX_BUF_SKB; | |
942 | } else if (st->packet_space != 0) { | |
943 | buffer->flags = EFX_TX_BUF_CONT; | |
944 | } | |
945 | ||
946 | if (st->in_len == 0) { | |
947 | /* Transfer ownership of the DMA mapping */ | |
948 | buffer->unmap_len = st->unmap_len; | |
949 | buffer->flags |= st->dma_flags; | |
950 | st->unmap_len = 0; | |
ecbd95c1 BH |
951 | } |
952 | ||
23d9e60b | 953 | st->dma_addr += n; |
b9b39b62 BH |
954 | } |
955 | ||
956 | ||
957 | /** | |
958 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
959 | * @tx_queue: Efx TX queue | |
960 | * @skb: Socket buffer | |
961 | * @st: TSO state | |
962 | * | |
963 | * Generate a new header and prepare for the new packet. Return 0 on | |
f7251a9c | 964 | * success, or -%ENOMEM if failed to alloc header. |
b9b39b62 | 965 | */ |
4d566063 BH |
966 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
967 | const struct sk_buff *skb, | |
968 | struct tso_state *st) | |
b9b39b62 | 969 | { |
f7251a9c BH |
970 | struct efx_tx_buffer *buffer = |
971 | &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask]; | |
dfa50be9 BH |
972 | bool is_last = st->out_len <= skb_shinfo(skb)->gso_size; |
973 | u8 tcp_flags_clear; | |
b9b39b62 | 974 | |
dfa50be9 | 975 | if (!is_last) { |
53cb13c6 | 976 | st->packet_space = skb_shinfo(skb)->gso_size; |
dfa50be9 | 977 | tcp_flags_clear = 0x09; /* mask out FIN and PSH */ |
b9b39b62 | 978 | } else { |
53cb13c6 | 979 | st->packet_space = st->out_len; |
dfa50be9 | 980 | tcp_flags_clear = 0x00; |
b9b39b62 | 981 | } |
b9b39b62 | 982 | |
dfa50be9 BH |
983 | if (!st->header_unmap_len) { |
984 | /* Allocate and insert a DMA-mapped header buffer. */ | |
985 | struct tcphdr *tsoh_th; | |
986 | unsigned ip_length; | |
987 | u8 *header; | |
988 | int rc; | |
738a8f4b | 989 | |
dfa50be9 BH |
990 | header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len); |
991 | if (!header) | |
992 | return -ENOMEM; | |
738a8f4b | 993 | |
dfa50be9 BH |
994 | tsoh_th = (struct tcphdr *)(header + st->tcp_off); |
995 | ||
996 | /* Copy and update the headers. */ | |
997 | memcpy(header, skb->data, st->header_len); | |
998 | ||
999 | tsoh_th->seq = htonl(st->seqnum); | |
1000 | ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear; | |
1001 | ||
1002 | ip_length = st->ip_base_len + st->packet_space; | |
1003 | ||
1004 | if (st->protocol == htons(ETH_P_IP)) { | |
1005 | struct iphdr *tsoh_iph = | |
1006 | (struct iphdr *)(header + st->ip_off); | |
1007 | ||
1008 | tsoh_iph->tot_len = htons(ip_length); | |
1009 | tsoh_iph->id = htons(st->ipv4_id); | |
1010 | } else { | |
1011 | struct ipv6hdr *tsoh_iph = | |
1012 | (struct ipv6hdr *)(header + st->ip_off); | |
1013 | ||
1014 | tsoh_iph->payload_len = htons(ip_length); | |
1015 | } | |
1016 | ||
1017 | rc = efx_tso_put_header(tx_queue, buffer, header); | |
1018 | if (unlikely(rc)) | |
1019 | return rc; | |
738a8f4b | 1020 | } else { |
dfa50be9 BH |
1021 | /* Send the original headers with a TSO option descriptor |
1022 | * in front | |
1023 | */ | |
1024 | u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear; | |
1025 | ||
1026 | buffer->flags = EFX_TX_BUF_OPTION; | |
1027 | buffer->len = 0; | |
1028 | buffer->unmap_len = 0; | |
1029 | EFX_POPULATE_QWORD_5(buffer->option, | |
1030 | ESF_DZ_TX_DESC_IS_OPT, 1, | |
1031 | ESF_DZ_TX_OPTION_TYPE, | |
1032 | ESE_DZ_TX_OPTION_DESC_TSO, | |
1033 | ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags, | |
1034 | ESF_DZ_TX_TSO_IP_ID, st->ipv4_id, | |
1035 | ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum); | |
1036 | ++tx_queue->insert_count; | |
738a8f4b | 1037 | |
dfa50be9 BH |
1038 | /* We mapped the headers in tso_start(). Unmap them |
1039 | * when the last segment is completed. | |
1040 | */ | |
1041 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
1042 | tx_queue->ptr_mask]; | |
1043 | buffer->dma_addr = st->header_dma_addr; | |
1044 | buffer->len = st->header_len; | |
1045 | if (is_last) { | |
1046 | buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE; | |
1047 | buffer->unmap_len = st->header_unmap_len; | |
1048 | /* Ensure we only unmap them once in case of a | |
1049 | * later DMA mapping error and rollback | |
1050 | */ | |
1051 | st->header_unmap_len = 0; | |
1052 | } else { | |
1053 | buffer->flags = EFX_TX_BUF_CONT; | |
1054 | buffer->unmap_len = 0; | |
1055 | } | |
1056 | ++tx_queue->insert_count; | |
738a8f4b | 1057 | } |
b9b39b62 | 1058 | |
dfa50be9 BH |
1059 | st->seqnum += skb_shinfo(skb)->gso_size; |
1060 | ||
1061 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
1062 | ++st->ipv4_id; | |
f7251a9c | 1063 | |
b9b39b62 BH |
1064 | ++tx_queue->tso_packets; |
1065 | ||
b9b39b62 BH |
1066 | return 0; |
1067 | } | |
1068 | ||
1069 | ||
1070 | /** | |
1071 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1072 | * @tx_queue: Efx TX queue | |
1073 | * @skb: Socket buffer | |
1074 | * | |
1075 | * Context: You must hold netif_tx_lock() to call this function. | |
1076 | * | |
1077 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1078 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
14bf718f | 1079 | * %NETDEV_TX_OK. |
b9b39b62 BH |
1080 | */ |
1081 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1082 | struct sk_buff *skb) |
b9b39b62 | 1083 | { |
ecbd95c1 | 1084 | struct efx_nic *efx = tx_queue->efx; |
14bf718f | 1085 | int frag_i, rc; |
b9b39b62 | 1086 | struct tso_state state; |
b9b39b62 | 1087 | |
738a8f4b BH |
1088 | /* Find the packet protocol and sanity-check it */ |
1089 | state.protocol = efx_tso_check_protocol(skb); | |
b9b39b62 BH |
1090 | |
1091 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
1092 | ||
c78c39e6 BH |
1093 | rc = tso_start(&state, efx, skb); |
1094 | if (rc) | |
1095 | goto mem_err; | |
b9b39b62 | 1096 | |
c78c39e6 | 1097 | if (likely(state.in_len == 0)) { |
b9b39b62 BH |
1098 | /* Grab the first payload fragment. */ |
1099 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1100 | frag_i = 0; | |
ecbd95c1 BH |
1101 | rc = tso_get_fragment(&state, efx, |
1102 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1103 | if (rc) |
1104 | goto mem_err; | |
1105 | } else { | |
c78c39e6 | 1106 | /* Payload starts in the header area. */ |
b9b39b62 BH |
1107 | frag_i = -1; |
1108 | } | |
1109 | ||
1110 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1111 | goto mem_err; | |
1112 | ||
1113 | while (1) { | |
14bf718f | 1114 | tso_fill_packet_with_fragment(tx_queue, skb, &state); |
b9b39b62 BH |
1115 | |
1116 | /* Move onto the next fragment? */ | |
23d9e60b | 1117 | if (state.in_len == 0) { |
b9b39b62 BH |
1118 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1119 | /* End of payload reached. */ | |
1120 | break; | |
ecbd95c1 BH |
1121 | rc = tso_get_fragment(&state, efx, |
1122 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1123 | if (rc) |
1124 | goto mem_err; | |
1125 | } | |
1126 | ||
1127 | /* Start at new packet? */ | |
1128 | if (state.packet_space == 0 && | |
1129 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1130 | goto mem_err; | |
1131 | } | |
1132 | ||
449fa023 ED |
1133 | netdev_tx_sent_queue(tx_queue->core_txq, skb->len); |
1134 | ||
b9b39b62 | 1135 | /* Pass off to hardware */ |
152b6a62 | 1136 | efx_nic_push_buffers(tx_queue); |
b9b39b62 | 1137 | |
14bf718f BH |
1138 | efx_tx_maybe_stop_queue(tx_queue); |
1139 | ||
b9b39b62 BH |
1140 | tx_queue->tso_bursts++; |
1141 | return NETDEV_TX_OK; | |
1142 | ||
1143 | mem_err: | |
62776d03 | 1144 | netif_err(efx, tx_err, efx->net_dev, |
0e33d870 | 1145 | "Out of memory for TSO headers, or DMA mapping error\n"); |
9bc183d7 | 1146 | dev_kfree_skb_any(skb); |
b9b39b62 | 1147 | |
5988b63a | 1148 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b | 1149 | if (state.unmap_len) { |
7668ff9c | 1150 | if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE) |
0e33d870 BH |
1151 | dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr, |
1152 | state.unmap_len, DMA_TO_DEVICE); | |
ecbd95c1 | 1153 | else |
0e33d870 BH |
1154 | dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr, |
1155 | state.unmap_len, DMA_TO_DEVICE); | |
ecbd95c1 | 1156 | } |
5988b63a | 1157 | |
dfa50be9 BH |
1158 | /* Free the header DMA mapping, if using option descriptors */ |
1159 | if (state.header_unmap_len) | |
1160 | dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr, | |
1161 | state.header_unmap_len, DMA_TO_DEVICE); | |
1162 | ||
b9b39b62 | 1163 | efx_enqueue_unwind(tx_queue); |
14bf718f | 1164 | return NETDEV_TX_OK; |
b9b39b62 | 1165 | } |