]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */ |
2 | /* | |
3 | Written/copyright 1997-2001 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | This driver is for the SMC83c170/175 "EPIC" series, as used on the | |
13 | SMC EtherPower II 9432 PCI adapter, and several CardBus cards. | |
14 | ||
15 | The author may be reached as becker@scyld.com, or C/O | |
16 | Scyld Computing Corporation | |
17 | 410 Severn Ave., Suite 210 | |
18 | Annapolis MD 21403 | |
19 | ||
20 | Information and updates available at | |
21 | http://www.scyld.com/network/epic100.html | |
36e1e847 | 22 | [this link no longer provides anything useful -jgarzik] |
1da177e4 LT |
23 | |
24 | --------------------------------------------------------------------- | |
f3b197ac | 25 | |
1da177e4 LT |
26 | */ |
27 | ||
28 | #define DRV_NAME "epic100" | |
d5b20697 AG |
29 | #define DRV_VERSION "2.1" |
30 | #define DRV_RELDATE "Sept 11, 2006" | |
1da177e4 LT |
31 | |
32 | /* The user-configurable values. | |
33 | These may be modified when a driver module is loaded.*/ | |
34 | ||
35 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
36 | ||
37 | /* Used to pass the full-duplex flag, etc. */ | |
38 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
39 | static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
40 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; | |
41 | ||
42 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
43 | Setting to > 1518 effectively disables this feature. */ | |
44 | static int rx_copybreak; | |
45 | ||
46 | /* Operational parameters that are set at compile time. */ | |
47 | ||
48 | /* Keep the ring sizes a power of two for operational efficiency. | |
49 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
50 | Making the Tx ring too large decreases the effectiveness of channel | |
51 | bonding and packet priority. | |
52 | There are no ill effects from too-large receive rings. */ | |
53 | #define TX_RING_SIZE 256 | |
54 | #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */ | |
55 | #define RX_RING_SIZE 256 | |
56 | #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc) | |
57 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc) | |
58 | ||
59 | /* Operational parameters that usually are not changed. */ | |
60 | /* Time in jiffies before concluding the transmitter is hung. */ | |
61 | #define TX_TIMEOUT (2*HZ) | |
62 | ||
63 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
64 | ||
65 | /* Bytes transferred to chip before transmission starts. */ | |
66 | /* Initial threshold, increased on underflow, rounded down to 4 byte units. */ | |
67 | #define TX_FIFO_THRESH 256 | |
68 | #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */ | |
69 | ||
1da177e4 LT |
70 | #include <linux/module.h> |
71 | #include <linux/kernel.h> | |
72 | #include <linux/string.h> | |
73 | #include <linux/timer.h> | |
74 | #include <linux/errno.h> | |
75 | #include <linux/ioport.h> | |
1da177e4 LT |
76 | #include <linux/interrupt.h> |
77 | #include <linux/pci.h> | |
78 | #include <linux/delay.h> | |
79 | #include <linux/netdevice.h> | |
80 | #include <linux/etherdevice.h> | |
81 | #include <linux/skbuff.h> | |
82 | #include <linux/init.h> | |
83 | #include <linux/spinlock.h> | |
84 | #include <linux/ethtool.h> | |
85 | #include <linux/mii.h> | |
86 | #include <linux/crc32.h> | |
87 | #include <linux/bitops.h> | |
88 | #include <asm/io.h> | |
7c0f6ba6 | 89 | #include <linux/uaccess.h> |
9e2d11b9 | 90 | #include <asm/byteorder.h> |
1da177e4 LT |
91 | |
92 | /* These identify the driver base version and may not be removed. */ | |
b0171cdc | 93 | static char version[] = |
3ee307de | 94 | DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>"; |
b0171cdc | 95 | static char version2[] = |
3ee307de | 96 | " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")"; |
1da177e4 LT |
97 | |
98 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
99 | MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver"); | |
100 | MODULE_LICENSE("GPL"); | |
101 | ||
102 | module_param(debug, int, 0); | |
103 | module_param(rx_copybreak, int, 0); | |
104 | module_param_array(options, int, NULL, 0); | |
105 | module_param_array(full_duplex, int, NULL, 0); | |
106 | MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)"); | |
107 | MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex"); | |
108 | MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames"); | |
109 | MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)"); | |
110 | ||
111 | /* | |
112 | Theory of Operation | |
113 | ||
114 | I. Board Compatibility | |
115 | ||
116 | This device driver is designed for the SMC "EPIC/100", the SMC | |
117 | single-chip Ethernet controllers for PCI. This chip is used on | |
118 | the SMC EtherPower II boards. | |
119 | ||
120 | II. Board-specific settings | |
121 | ||
122 | PCI bus devices are configured by the system at boot time, so no jumpers | |
123 | need to be set on the board. The system BIOS will assign the | |
124 | PCI INTA signal to a (preferably otherwise unused) system IRQ line. | |
125 | Note: Kernel versions earlier than 1.3.73 do not support shared PCI | |
126 | interrupt lines. | |
127 | ||
128 | III. Driver operation | |
129 | ||
130 | IIIa. Ring buffers | |
131 | ||
132 | IVb. References | |
133 | ||
631dd1a8 JM |
134 | http://www.smsc.com/media/Downloads_Public/discontinued/83c171.pdf |
135 | http://www.smsc.com/media/Downloads_Public/discontinued/83c175.pdf | |
1da177e4 LT |
136 | http://scyld.com/expert/NWay.html |
137 | http://www.national.com/pf/DP/DP83840A.html | |
138 | ||
139 | IVc. Errata | |
140 | ||
141 | */ | |
142 | ||
143 | ||
1da177e4 LT |
144 | enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 }; |
145 | ||
146 | #define EPIC_TOTAL_SIZE 0x100 | |
147 | #define USE_IO_OPS 1 | |
1da177e4 | 148 | |
aae9bc30 FR |
149 | #ifdef USE_IO_OPS |
150 | #define EPIC_BAR 0 | |
151 | #else | |
152 | #define EPIC_BAR 1 | |
153 | #endif | |
154 | ||
1da177e4 LT |
155 | typedef enum { |
156 | SMSC_83C170_0, | |
157 | SMSC_83C170, | |
158 | SMSC_83C175, | |
159 | } chip_t; | |
160 | ||
161 | ||
162 | struct epic_chip_info { | |
163 | const char *name; | |
1da177e4 LT |
164 | int drv_flags; /* Driver use, intended as capability flags. */ |
165 | }; | |
166 | ||
167 | ||
168 | /* indexed by chip_t */ | |
f71e1309 | 169 | static const struct epic_chip_info pci_id_tbl[] = { |
36e1e847 JG |
170 | { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN }, |
171 | { "SMSC EPIC/100 83c170", TYPE2_INTR }, | |
172 | { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN }, | |
1da177e4 LT |
173 | }; |
174 | ||
175 | ||
9baa3c34 | 176 | static const struct pci_device_id epic_pci_tbl[] = { |
1da177e4 LT |
177 | { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 }, |
178 | { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 }, | |
179 | { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID, | |
180 | PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 }, | |
181 | { 0,} | |
182 | }; | |
183 | MODULE_DEVICE_TABLE (pci, epic_pci_tbl); | |
184 | ||
aae9bc30 FR |
185 | #define ew16(reg, val) iowrite16(val, ioaddr + (reg)) |
186 | #define ew32(reg, val) iowrite32(val, ioaddr + (reg)) | |
187 | #define er8(reg) ioread8(ioaddr + (reg)) | |
188 | #define er16(reg) ioread16(ioaddr + (reg)) | |
189 | #define er32(reg) ioread32(ioaddr + (reg)) | |
1da177e4 LT |
190 | |
191 | /* Offsets to registers, using the (ugh) SMC names. */ | |
192 | enum epic_registers { | |
193 | COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14, | |
194 | PCIBurstCnt=0x18, | |
195 | TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */ | |
196 | MIICtrl=0x30, MIIData=0x34, MIICfg=0x38, | |
197 | LAN0=64, /* MAC address. */ | |
198 | MC0=80, /* Multicast filter table. */ | |
199 | RxCtrl=96, TxCtrl=112, TxSTAT=0x74, | |
200 | PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC, | |
201 | }; | |
202 | ||
203 | /* Interrupt register bits, using my own meaningful names. */ | |
204 | enum IntrStatus { | |
205 | TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000, | |
206 | PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000, | |
207 | RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100, | |
208 | TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010, | |
209 | RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001, | |
210 | }; | |
211 | enum CommandBits { | |
212 | StopRx=1, StartRx=2, TxQueued=4, RxQueued=8, | |
213 | StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80, | |
214 | }; | |
215 | ||
216 | #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */ | |
217 | ||
218 | #define EpicNapiEvent (TxEmpty | TxDone | \ | |
219 | RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull) | |
220 | #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent) | |
221 | ||
f71e1309 | 222 | static const u16 media2miictl[16] = { |
1da177e4 LT |
223 | 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0, |
224 | 0, 0, 0, 0, 0, 0, 0, 0 }; | |
225 | ||
9ebfd492 AV |
226 | /* |
227 | * The EPIC100 Rx and Tx buffer descriptors. Note that these | |
228 | * really ARE host-endian; it's not a misannotation. We tell | |
229 | * the card to byteswap them internally on big-endian hosts - | |
9e2d11b9 | 230 | * look for #ifdef __BIG_ENDIAN in epic_open(). |
9ebfd492 | 231 | */ |
1da177e4 LT |
232 | |
233 | struct epic_tx_desc { | |
234 | u32 txstatus; | |
235 | u32 bufaddr; | |
236 | u32 buflength; | |
237 | u32 next; | |
238 | }; | |
239 | ||
240 | struct epic_rx_desc { | |
241 | u32 rxstatus; | |
242 | u32 bufaddr; | |
243 | u32 buflength; | |
244 | u32 next; | |
245 | }; | |
246 | ||
247 | enum desc_status_bits { | |
248 | DescOwn=0x8000, | |
249 | }; | |
250 | ||
251 | #define PRIV_ALIGN 15 /* Required alignment mask */ | |
252 | struct epic_private { | |
253 | struct epic_rx_desc *rx_ring; | |
254 | struct epic_tx_desc *tx_ring; | |
255 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | |
256 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
257 | /* The addresses of receive-in-place skbuffs. */ | |
258 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
259 | ||
260 | dma_addr_t tx_ring_dma; | |
261 | dma_addr_t rx_ring_dma; | |
262 | ||
263 | /* Ring pointers. */ | |
264 | spinlock_t lock; /* Group with Tx control cache line. */ | |
265 | spinlock_t napi_lock; | |
bea3348e | 266 | struct napi_struct napi; |
1da177e4 LT |
267 | unsigned int cur_tx, dirty_tx; |
268 | ||
269 | unsigned int cur_rx, dirty_rx; | |
270 | u32 irq_mask; | |
271 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
272 | ||
aae9bc30 | 273 | void __iomem *ioaddr; |
1da177e4 LT |
274 | struct pci_dev *pci_dev; /* PCI bus location. */ |
275 | int chip_id, chip_flags; | |
276 | ||
1da177e4 LT |
277 | struct timer_list timer; /* Media selection timer. */ |
278 | int tx_threshold; | |
279 | unsigned char mc_filter[8]; | |
280 | signed char phys[4]; /* MII device addresses. */ | |
281 | u16 advertising; /* NWay media advertisement */ | |
282 | int mii_phy_cnt; | |
4ac0ac84 | 283 | u32 ethtool_ops_nesting; |
1da177e4 LT |
284 | struct mii_if_info mii; |
285 | unsigned int tx_full:1; /* The Tx queue is full. */ | |
286 | unsigned int default_port:4; /* Last dev->if_port value. */ | |
287 | }; | |
288 | ||
289 | static int epic_open(struct net_device *dev); | |
aae9bc30 | 290 | static int read_eeprom(struct epic_private *, int); |
1da177e4 LT |
291 | static int mdio_read(struct net_device *dev, int phy_id, int location); |
292 | static void mdio_write(struct net_device *dev, int phy_id, int loc, int val); | |
293 | static void epic_restart(struct net_device *dev); | |
267146d4 | 294 | static void epic_timer(struct timer_list *t); |
0290bd29 | 295 | static void epic_tx_timeout(struct net_device *dev, unsigned int txqueue); |
1da177e4 | 296 | static void epic_init_ring(struct net_device *dev); |
61357325 SH |
297 | static netdev_tx_t epic_start_xmit(struct sk_buff *skb, |
298 | struct net_device *dev); | |
1da177e4 | 299 | static int epic_rx(struct net_device *dev, int budget); |
bea3348e | 300 | static int epic_poll(struct napi_struct *napi, int budget); |
7d12e780 | 301 | static irqreturn_t epic_interrupt(int irq, void *dev_instance); |
1da177e4 | 302 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
7282d491 | 303 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 LT |
304 | static int epic_close(struct net_device *dev); |
305 | static struct net_device_stats *epic_get_stats(struct net_device *dev); | |
306 | static void set_rx_mode(struct net_device *dev); | |
307 | ||
805524cb SH |
308 | static const struct net_device_ops epic_netdev_ops = { |
309 | .ndo_open = epic_open, | |
310 | .ndo_stop = epic_close, | |
311 | .ndo_start_xmit = epic_start_xmit, | |
312 | .ndo_tx_timeout = epic_tx_timeout, | |
313 | .ndo_get_stats = epic_get_stats, | |
afc4b13d | 314 | .ndo_set_rx_mode = set_rx_mode, |
a7605370 | 315 | .ndo_eth_ioctl = netdev_ioctl, |
805524cb SH |
316 | .ndo_set_mac_address = eth_mac_addr, |
317 | .ndo_validate_addr = eth_validate_addr, | |
318 | }; | |
1da177e4 | 319 | |
1dd06ae8 | 320 | static int epic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 LT |
321 | { |
322 | static int card_idx = -1; | |
aae9bc30 | 323 | void __iomem *ioaddr; |
1da177e4 | 324 | int chip_idx = (int) ent->driver_data; |
1da177e4 LT |
325 | struct net_device *dev; |
326 | struct epic_private *ep; | |
327 | int i, ret, option = 0, duplex = 0; | |
328 | void *ring_space; | |
329 | dma_addr_t ring_dma; | |
330 | ||
331 | /* when built into the kernel, we only print version if device is found */ | |
332 | #ifndef MODULE | |
3ee307de | 333 | pr_info_once("%s%s\n", version, version2); |
1da177e4 | 334 | #endif |
f3b197ac | 335 | |
1da177e4 | 336 | card_idx++; |
f3b197ac | 337 | |
1da177e4 LT |
338 | ret = pci_enable_device(pdev); |
339 | if (ret) | |
340 | goto out; | |
1da177e4 | 341 | |
36e1e847 | 342 | if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) { |
9b91cf9d | 343 | dev_err(&pdev->dev, "no PCI region space\n"); |
1da177e4 LT |
344 | ret = -ENODEV; |
345 | goto err_out_disable; | |
346 | } | |
f3b197ac | 347 | |
1da177e4 LT |
348 | pci_set_master(pdev); |
349 | ||
350 | ret = pci_request_regions(pdev, DRV_NAME); | |
351 | if (ret < 0) | |
352 | goto err_out_disable; | |
353 | ||
354 | ret = -ENOMEM; | |
355 | ||
356 | dev = alloc_etherdev(sizeof (*ep)); | |
41de8d4c | 357 | if (!dev) |
1da177e4 | 358 | goto err_out_free_res; |
41de8d4c | 359 | |
1da177e4 LT |
360 | SET_NETDEV_DEV(dev, &pdev->dev); |
361 | ||
aae9bc30 | 362 | ioaddr = pci_iomap(pdev, EPIC_BAR, 0); |
1da177e4 | 363 | if (!ioaddr) { |
9b91cf9d | 364 | dev_err(&pdev->dev, "ioremap failed\n"); |
1da177e4 LT |
365 | goto err_out_free_netdev; |
366 | } | |
1da177e4 LT |
367 | |
368 | pci_set_drvdata(pdev, dev); | |
4cf1653a | 369 | ep = netdev_priv(dev); |
aae9bc30 | 370 | ep->ioaddr = ioaddr; |
1da177e4 LT |
371 | ep->mii.dev = dev; |
372 | ep->mii.mdio_read = mdio_read; | |
373 | ep->mii.mdio_write = mdio_write; | |
374 | ep->mii.phy_id_mask = 0x1f; | |
375 | ep->mii.reg_num_mask = 0x1f; | |
376 | ||
63692803 CJ |
377 | ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma, |
378 | GFP_KERNEL); | |
1da177e4 LT |
379 | if (!ring_space) |
380 | goto err_out_iounmap; | |
43d620c8 | 381 | ep->tx_ring = ring_space; |
1da177e4 LT |
382 | ep->tx_ring_dma = ring_dma; |
383 | ||
63692803 CJ |
384 | ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma, |
385 | GFP_KERNEL); | |
1da177e4 LT |
386 | if (!ring_space) |
387 | goto err_out_unmap_tx; | |
43d620c8 | 388 | ep->rx_ring = ring_space; |
1da177e4 LT |
389 | ep->rx_ring_dma = ring_dma; |
390 | ||
391 | if (dev->mem_start) { | |
392 | option = dev->mem_start; | |
393 | duplex = (dev->mem_start & 16) ? 1 : 0; | |
394 | } else if (card_idx >= 0 && card_idx < MAX_UNITS) { | |
395 | if (options[card_idx] >= 0) | |
396 | option = options[card_idx]; | |
397 | if (full_duplex[card_idx] >= 0) | |
398 | duplex = full_duplex[card_idx]; | |
399 | } | |
400 | ||
1da177e4 LT |
401 | spin_lock_init(&ep->lock); |
402 | spin_lock_init(&ep->napi_lock); | |
1da177e4 LT |
403 | |
404 | /* Bring the chip out of low-power mode. */ | |
aae9bc30 | 405 | ew32(GENCTL, 0x4200); |
1da177e4 LT |
406 | /* Magic?! If we don't set this bit the MII interface won't work. */ |
407 | /* This magic is documented in SMSC app note 7.15 */ | |
408 | for (i = 16; i > 0; i--) | |
aae9bc30 | 409 | ew32(TEST1, 0x0008); |
1da177e4 LT |
410 | |
411 | /* Turn on the MII transceiver. */ | |
aae9bc30 | 412 | ew32(MIICfg, 0x12); |
1da177e4 | 413 | if (chip_idx == 1) |
aae9bc30 FR |
414 | ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); |
415 | ew32(GENCTL, 0x0200); | |
1da177e4 LT |
416 | |
417 | /* Note: the '175 does not have a serial EEPROM. */ | |
418 | for (i = 0; i < 3; i++) | |
aae9bc30 | 419 | ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(er16(LAN0 + i*4)); |
1da177e4 LT |
420 | |
421 | if (debug > 2) { | |
3ee307de | 422 | dev_dbg(&pdev->dev, "EEPROM contents:\n"); |
1da177e4 | 423 | for (i = 0; i < 64; i++) |
3ee307de | 424 | pr_cont(" %4.4x%s", read_eeprom(ep, i), |
1da177e4 LT |
425 | i % 16 == 15 ? "\n" : ""); |
426 | } | |
427 | ||
428 | ep->pci_dev = pdev; | |
429 | ep->chip_id = chip_idx; | |
430 | ep->chip_flags = pci_id_tbl[chip_idx].drv_flags; | |
f3b197ac | 431 | ep->irq_mask = |
1da177e4 LT |
432 | (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170) |
433 | | CntFull | TxUnderrun | EpicNapiEvent; | |
434 | ||
435 | /* Find the connected MII xcvrs. | |
436 | Doing this in open() would allow detecting external xcvrs later, but | |
437 | takes much time and no cards have external MII. */ | |
438 | { | |
439 | int phy, phy_idx = 0; | |
440 | for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) { | |
441 | int mii_status = mdio_read(dev, phy, MII_BMSR); | |
442 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
443 | ep->phys[phy_idx++] = phy; | |
9b91cf9d | 444 | dev_info(&pdev->dev, |
2e8a538d JG |
445 | "MII transceiver #%d control " |
446 | "%4.4x status %4.4x.\n", | |
447 | phy, mdio_read(dev, phy, 0), mii_status); | |
1da177e4 LT |
448 | } |
449 | } | |
450 | ep->mii_phy_cnt = phy_idx; | |
451 | if (phy_idx != 0) { | |
452 | phy = ep->phys[0]; | |
453 | ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
9b91cf9d | 454 | dev_info(&pdev->dev, |
2e8a538d | 455 | "Autonegotiation advertising %4.4x link " |
1da177e4 | 456 | "partner %4.4x.\n", |
2e8a538d | 457 | ep->mii.advertising, mdio_read(dev, phy, 5)); |
1da177e4 | 458 | } else if ( ! (ep->chip_flags & NO_MII)) { |
9b91cf9d | 459 | dev_warn(&pdev->dev, |
2e8a538d | 460 | "***WARNING***: No MII transceiver found!\n"); |
1da177e4 LT |
461 | /* Use the known PHY address of the EPII. */ |
462 | ep->phys[0] = 3; | |
463 | } | |
464 | ep->mii.phy_id = ep->phys[0]; | |
465 | } | |
466 | ||
467 | /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */ | |
468 | if (ep->chip_flags & MII_PWRDWN) | |
aae9bc30 FR |
469 | ew32(NVCTL, er32(NVCTL) & ~0x483c); |
470 | ew32(GENCTL, 0x0008); | |
1da177e4 LT |
471 | |
472 | /* The lower four bits are the media type. */ | |
473 | if (duplex) { | |
474 | ep->mii.force_media = ep->mii.full_duplex = 1; | |
9b91cf9d | 475 | dev_info(&pdev->dev, "Forced full duplex requested.\n"); |
1da177e4 LT |
476 | } |
477 | dev->if_port = ep->default_port = option; | |
478 | ||
479 | /* The Epic-specific entries in the device structure. */ | |
805524cb | 480 | dev->netdev_ops = &epic_netdev_ops; |
1da177e4 LT |
481 | dev->ethtool_ops = &netdev_ethtool_ops; |
482 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e | 483 | netif_napi_add(dev, &ep->napi, epic_poll, 64); |
1da177e4 LT |
484 | |
485 | ret = register_netdev(dev); | |
486 | if (ret < 0) | |
487 | goto err_out_unmap_rx; | |
488 | ||
3ee307de BB |
489 | netdev_info(dev, "%s at %lx, IRQ %d, %pM\n", |
490 | pci_id_tbl[chip_idx].name, | |
491 | (long)pci_resource_start(pdev, EPIC_BAR), pdev->irq, | |
492 | dev->dev_addr); | |
1da177e4 LT |
493 | |
494 | out: | |
495 | return ret; | |
496 | ||
497 | err_out_unmap_rx: | |
63692803 CJ |
498 | dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, ep->rx_ring, |
499 | ep->rx_ring_dma); | |
1da177e4 | 500 | err_out_unmap_tx: |
63692803 CJ |
501 | dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, ep->tx_ring, |
502 | ep->tx_ring_dma); | |
1da177e4 | 503 | err_out_iounmap: |
aae9bc30 | 504 | pci_iounmap(pdev, ioaddr); |
1da177e4 | 505 | err_out_free_netdev: |
1da177e4 LT |
506 | free_netdev(dev); |
507 | err_out_free_res: | |
508 | pci_release_regions(pdev); | |
509 | err_out_disable: | |
510 | pci_disable_device(pdev); | |
511 | goto out; | |
512 | } | |
f3b197ac | 513 | |
1da177e4 LT |
514 | /* Serial EEPROM section. */ |
515 | ||
516 | /* EEPROM_Ctrl bits. */ | |
517 | #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ | |
518 | #define EE_CS 0x02 /* EEPROM chip select. */ | |
519 | #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */ | |
520 | #define EE_WRITE_0 0x01 | |
521 | #define EE_WRITE_1 0x09 | |
522 | #define EE_DATA_READ 0x10 /* EEPROM chip data out. */ | |
523 | #define EE_ENB (0x0001 | EE_CS) | |
524 | ||
525 | /* Delay between EEPROM clock transitions. | |
526 | This serves to flush the operation to the PCI bus. | |
527 | */ | |
528 | ||
aae9bc30 | 529 | #define eeprom_delay() er32(EECTL) |
1da177e4 LT |
530 | |
531 | /* The EEPROM commands include the alway-set leading bit. */ | |
532 | #define EE_WRITE_CMD (5 << 6) | |
533 | #define EE_READ64_CMD (6 << 6) | |
534 | #define EE_READ256_CMD (6 << 8) | |
535 | #define EE_ERASE_CMD (7 << 6) | |
536 | ||
537 | static void epic_disable_int(struct net_device *dev, struct epic_private *ep) | |
538 | { | |
aae9bc30 | 539 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 | 540 | |
aae9bc30 | 541 | ew32(INTMASK, 0x00000000); |
1da177e4 LT |
542 | } |
543 | ||
aae9bc30 | 544 | static inline void __epic_pci_commit(void __iomem *ioaddr) |
1da177e4 LT |
545 | { |
546 | #ifndef USE_IO_OPS | |
aae9bc30 | 547 | er32(INTMASK); |
1da177e4 LT |
548 | #endif |
549 | } | |
550 | ||
551 | static inline void epic_napi_irq_off(struct net_device *dev, | |
552 | struct epic_private *ep) | |
553 | { | |
aae9bc30 | 554 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 | 555 | |
aae9bc30 | 556 | ew32(INTMASK, ep->irq_mask & ~EpicNapiEvent); |
1da177e4 LT |
557 | __epic_pci_commit(ioaddr); |
558 | } | |
559 | ||
560 | static inline void epic_napi_irq_on(struct net_device *dev, | |
561 | struct epic_private *ep) | |
562 | { | |
aae9bc30 | 563 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
564 | |
565 | /* No need to commit possible posted write */ | |
aae9bc30 | 566 | ew32(INTMASK, ep->irq_mask | EpicNapiEvent); |
1da177e4 LT |
567 | } |
568 | ||
b0171cdc | 569 | static int read_eeprom(struct epic_private *ep, int location) |
1da177e4 | 570 | { |
aae9bc30 | 571 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
572 | int i; |
573 | int retval = 0; | |
1da177e4 | 574 | int read_cmd = location | |
aae9bc30 | 575 | (er32(EECTL) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD); |
1da177e4 | 576 | |
aae9bc30 FR |
577 | ew32(EECTL, EE_ENB & ~EE_CS); |
578 | ew32(EECTL, EE_ENB); | |
1da177e4 LT |
579 | |
580 | /* Shift the read command bits out. */ | |
581 | for (i = 12; i >= 0; i--) { | |
582 | short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0; | |
aae9bc30 | 583 | ew32(EECTL, EE_ENB | dataval); |
1da177e4 | 584 | eeprom_delay(); |
aae9bc30 | 585 | ew32(EECTL, EE_ENB | dataval | EE_SHIFT_CLK); |
1da177e4 LT |
586 | eeprom_delay(); |
587 | } | |
aae9bc30 | 588 | ew32(EECTL, EE_ENB); |
1da177e4 LT |
589 | |
590 | for (i = 16; i > 0; i--) { | |
aae9bc30 | 591 | ew32(EECTL, EE_ENB | EE_SHIFT_CLK); |
1da177e4 | 592 | eeprom_delay(); |
aae9bc30 FR |
593 | retval = (retval << 1) | ((er32(EECTL) & EE_DATA_READ) ? 1 : 0); |
594 | ew32(EECTL, EE_ENB); | |
1da177e4 LT |
595 | eeprom_delay(); |
596 | } | |
597 | ||
598 | /* Terminate the EEPROM access. */ | |
aae9bc30 | 599 | ew32(EECTL, EE_ENB & ~EE_CS); |
1da177e4 LT |
600 | return retval; |
601 | } | |
602 | ||
603 | #define MII_READOP 1 | |
604 | #define MII_WRITEOP 2 | |
605 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
606 | { | |
aae9bc30 FR |
607 | struct epic_private *ep = netdev_priv(dev); |
608 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
609 | int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP; |
610 | int i; | |
611 | ||
aae9bc30 | 612 | ew32(MIICtrl, read_cmd); |
1da177e4 LT |
613 | /* Typical operation takes 25 loops. */ |
614 | for (i = 400; i > 0; i--) { | |
615 | barrier(); | |
aae9bc30 | 616 | if ((er32(MIICtrl) & MII_READOP) == 0) { |
1da177e4 | 617 | /* Work around read failure bug. */ |
8e95a202 | 618 | if (phy_id == 1 && location < 6 && |
aae9bc30 FR |
619 | er16(MIIData) == 0xffff) { |
620 | ew32(MIICtrl, read_cmd); | |
1da177e4 LT |
621 | continue; |
622 | } | |
aae9bc30 | 623 | return er16(MIIData); |
1da177e4 LT |
624 | } |
625 | } | |
626 | return 0xffff; | |
627 | } | |
628 | ||
629 | static void mdio_write(struct net_device *dev, int phy_id, int loc, int value) | |
630 | { | |
aae9bc30 FR |
631 | struct epic_private *ep = netdev_priv(dev); |
632 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
633 | int i; |
634 | ||
aae9bc30 FR |
635 | ew16(MIIData, value); |
636 | ew32(MIICtrl, (phy_id << 9) | (loc << 4) | MII_WRITEOP); | |
f3b197ac | 637 | for (i = 10000; i > 0; i--) { |
1da177e4 | 638 | barrier(); |
aae9bc30 | 639 | if ((er32(MIICtrl) & MII_WRITEOP) == 0) |
1da177e4 LT |
640 | break; |
641 | } | |
1da177e4 LT |
642 | } |
643 | ||
f3b197ac | 644 | |
1da177e4 LT |
645 | static int epic_open(struct net_device *dev) |
646 | { | |
4cf1653a | 647 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 FR |
648 | void __iomem *ioaddr = ep->ioaddr; |
649 | const int irq = ep->pci_dev->irq; | |
650 | int rc, i; | |
1da177e4 LT |
651 | |
652 | /* Soft reset the chip. */ | |
aae9bc30 | 653 | ew32(GENCTL, 0x4001); |
1da177e4 | 654 | |
bea3348e | 655 | napi_enable(&ep->napi); |
aae9bc30 FR |
656 | rc = request_irq(irq, epic_interrupt, IRQF_SHARED, dev->name, dev); |
657 | if (rc) { | |
bea3348e | 658 | napi_disable(&ep->napi); |
aae9bc30 | 659 | return rc; |
bea3348e | 660 | } |
1da177e4 LT |
661 | |
662 | epic_init_ring(dev); | |
663 | ||
aae9bc30 | 664 | ew32(GENCTL, 0x4000); |
1da177e4 LT |
665 | /* This magic is documented in SMSC app note 7.15 */ |
666 | for (i = 16; i > 0; i--) | |
aae9bc30 | 667 | ew32(TEST1, 0x0008); |
1da177e4 LT |
668 | |
669 | /* Pull the chip out of low-power mode, enable interrupts, and set for | |
670 | PCI read multiple. The MIIcfg setting and strange write order are | |
671 | required by the details of which bits are reset and the transceiver | |
672 | wiring on the Ositech CardBus card. | |
673 | */ | |
674 | #if 0 | |
aae9bc30 | 675 | ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12); |
1da177e4 LT |
676 | #endif |
677 | if (ep->chip_flags & MII_PWRDWN) | |
aae9bc30 | 678 | ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); |
1da177e4 | 679 | |
9ebfd492 | 680 | /* Tell the chip to byteswap descriptors on big-endian hosts */ |
9e2d11b9 | 681 | #ifdef __BIG_ENDIAN |
aae9bc30 FR |
682 | ew32(GENCTL, 0x4432 | (RX_FIFO_THRESH << 8)); |
683 | er32(GENCTL); | |
684 | ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8)); | |
1da177e4 | 685 | #else |
aae9bc30 FR |
686 | ew32(GENCTL, 0x4412 | (RX_FIFO_THRESH << 8)); |
687 | er32(GENCTL); | |
688 | ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8)); | |
1da177e4 LT |
689 | #endif |
690 | ||
691 | udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */ | |
f3b197ac | 692 | |
1da177e4 | 693 | for (i = 0; i < 3; i++) |
aae9bc30 | 694 | ew32(LAN0 + i*4, le16_to_cpu(((__le16*)dev->dev_addr)[i])); |
1da177e4 LT |
695 | |
696 | ep->tx_threshold = TX_FIFO_THRESH; | |
aae9bc30 | 697 | ew32(TxThresh, ep->tx_threshold); |
1da177e4 LT |
698 | |
699 | if (media2miictl[dev->if_port & 15]) { | |
700 | if (ep->mii_phy_cnt) | |
701 | mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]); | |
702 | if (dev->if_port == 1) { | |
703 | if (debug > 1) | |
3ee307de BB |
704 | netdev_info(dev, "Using the 10base2 transceiver, MII status %4.4x.\n", |
705 | mdio_read(dev, ep->phys[0], MII_BMSR)); | |
1da177e4 LT |
706 | } |
707 | } else { | |
708 | int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA); | |
709 | if (mii_lpa != 0xffff) { | |
710 | if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL) | |
711 | ep->mii.full_duplex = 1; | |
712 | else if (! (mii_lpa & LPA_LPACK)) | |
713 | mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART); | |
714 | if (debug > 1) | |
3ee307de BB |
715 | netdev_info(dev, "Setting %s-duplex based on MII xcvr %d register read of %4.4x.\n", |
716 | ep->mii.full_duplex ? "full" | |
717 | : "half", | |
718 | ep->phys[0], mii_lpa); | |
1da177e4 LT |
719 | } |
720 | } | |
721 | ||
aae9bc30 FR |
722 | ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79); |
723 | ew32(PRxCDAR, ep->rx_ring_dma); | |
724 | ew32(PTxCDAR, ep->tx_ring_dma); | |
1da177e4 LT |
725 | |
726 | /* Start the chip's Rx process. */ | |
727 | set_rx_mode(dev); | |
aae9bc30 | 728 | ew32(COMMAND, StartRx | RxQueued); |
1da177e4 LT |
729 | |
730 | netif_start_queue(dev); | |
731 | ||
732 | /* Enable interrupts by setting the interrupt mask. */ | |
aae9bc30 FR |
733 | ew32(INTMASK, RxError | RxHeader | EpicNapiEvent | CntFull | |
734 | ((ep->chip_flags & TYPE2_INTR) ? PCIBusErr175 : PCIBusErr170) | | |
735 | TxUnderrun); | |
736 | ||
737 | if (debug > 1) { | |
3ee307de BB |
738 | netdev_dbg(dev, "epic_open() ioaddr %p IRQ %d status %4.4x %s-duplex.\n", |
739 | ioaddr, irq, er32(GENCTL), | |
740 | ep->mii.full_duplex ? "full" : "half"); | |
aae9bc30 | 741 | } |
1da177e4 LT |
742 | |
743 | /* Set the timer to switch to check for link beat and perhaps switch | |
744 | to an alternate media type. */ | |
267146d4 | 745 | timer_setup(&ep->timer, epic_timer, 0); |
1da177e4 | 746 | ep->timer.expires = jiffies + 3*HZ; |
1da177e4 LT |
747 | add_timer(&ep->timer); |
748 | ||
aae9bc30 | 749 | return rc; |
1da177e4 LT |
750 | } |
751 | ||
752 | /* Reset the chip to recover from a PCI transaction error. | |
753 | This may occur at interrupt time. */ | |
754 | static void epic_pause(struct net_device *dev) | |
755 | { | |
aae9bc30 FR |
756 | struct net_device_stats *stats = &dev->stats; |
757 | struct epic_private *ep = netdev_priv(dev); | |
758 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
759 | |
760 | netif_stop_queue (dev); | |
f3b197ac | 761 | |
1da177e4 | 762 | /* Disable interrupts by clearing the interrupt mask. */ |
aae9bc30 | 763 | ew32(INTMASK, 0x00000000); |
1da177e4 | 764 | /* Stop the chip's Tx and Rx DMA processes. */ |
aae9bc30 | 765 | ew16(COMMAND, StopRx | StopTxDMA | StopRxDMA); |
1da177e4 LT |
766 | |
767 | /* Update the error counts. */ | |
aae9bc30 FR |
768 | if (er16(COMMAND) != 0xffff) { |
769 | stats->rx_missed_errors += er8(MPCNT); | |
770 | stats->rx_frame_errors += er8(ALICNT); | |
771 | stats->rx_crc_errors += er8(CRCCNT); | |
1da177e4 LT |
772 | } |
773 | ||
774 | /* Remove the packets on the Rx queue. */ | |
775 | epic_rx(dev, RX_RING_SIZE); | |
776 | } | |
777 | ||
778 | static void epic_restart(struct net_device *dev) | |
779 | { | |
4cf1653a | 780 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 781 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
782 | int i; |
783 | ||
784 | /* Soft reset the chip. */ | |
aae9bc30 | 785 | ew32(GENCTL, 0x4001); |
1da177e4 | 786 | |
3ee307de BB |
787 | netdev_dbg(dev, "Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n", |
788 | ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx); | |
1da177e4 LT |
789 | udelay(1); |
790 | ||
791 | /* This magic is documented in SMSC app note 7.15 */ | |
792 | for (i = 16; i > 0; i--) | |
aae9bc30 | 793 | ew32(TEST1, 0x0008); |
1da177e4 | 794 | |
9e2d11b9 | 795 | #ifdef __BIG_ENDIAN |
aae9bc30 | 796 | ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8)); |
1da177e4 | 797 | #else |
aae9bc30 | 798 | ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8)); |
1da177e4 | 799 | #endif |
aae9bc30 | 800 | ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12); |
1da177e4 | 801 | if (ep->chip_flags & MII_PWRDWN) |
aae9bc30 | 802 | ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); |
1da177e4 LT |
803 | |
804 | for (i = 0; i < 3; i++) | |
aae9bc30 | 805 | ew32(LAN0 + i*4, le16_to_cpu(((__le16*)dev->dev_addr)[i])); |
1da177e4 LT |
806 | |
807 | ep->tx_threshold = TX_FIFO_THRESH; | |
aae9bc30 FR |
808 | ew32(TxThresh, ep->tx_threshold); |
809 | ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79); | |
810 | ew32(PRxCDAR, ep->rx_ring_dma + | |
811 | (ep->cur_rx % RX_RING_SIZE) * sizeof(struct epic_rx_desc)); | |
812 | ew32(PTxCDAR, ep->tx_ring_dma + | |
813 | (ep->dirty_tx % TX_RING_SIZE) * sizeof(struct epic_tx_desc)); | |
1da177e4 LT |
814 | |
815 | /* Start the chip's Rx process. */ | |
816 | set_rx_mode(dev); | |
aae9bc30 | 817 | ew32(COMMAND, StartRx | RxQueued); |
1da177e4 LT |
818 | |
819 | /* Enable interrupts by setting the interrupt mask. */ | |
aae9bc30 FR |
820 | ew32(INTMASK, RxError | RxHeader | EpicNapiEvent | CntFull | |
821 | ((ep->chip_flags & TYPE2_INTR) ? PCIBusErr175 : PCIBusErr170) | | |
822 | TxUnderrun); | |
1da177e4 | 823 | |
3ee307de BB |
824 | netdev_dbg(dev, "epic_restart() done, cmd status %4.4x, ctl %4.4x interrupt %4.4x.\n", |
825 | er32(COMMAND), er32(GENCTL), er32(INTSTAT)); | |
1da177e4 LT |
826 | } |
827 | ||
828 | static void check_media(struct net_device *dev) | |
829 | { | |
4cf1653a | 830 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 831 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
832 | int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0; |
833 | int negotiated = mii_lpa & ep->mii.advertising; | |
834 | int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; | |
835 | ||
836 | if (ep->mii.force_media) | |
837 | return; | |
838 | if (mii_lpa == 0xffff) /* Bogus read */ | |
839 | return; | |
840 | if (ep->mii.full_duplex != duplex) { | |
841 | ep->mii.full_duplex = duplex; | |
3ee307de BB |
842 | netdev_info(dev, "Setting %s-duplex based on MII #%d link partner capability of %4.4x.\n", |
843 | ep->mii.full_duplex ? "full" : "half", | |
844 | ep->phys[0], mii_lpa); | |
aae9bc30 | 845 | ew32(TxCtrl, ep->mii.full_duplex ? 0x7F : 0x79); |
1da177e4 LT |
846 | } |
847 | } | |
848 | ||
267146d4 | 849 | static void epic_timer(struct timer_list *t) |
1da177e4 | 850 | { |
267146d4 KC |
851 | struct epic_private *ep = from_timer(ep, t, timer); |
852 | struct net_device *dev = ep->mii.dev; | |
aae9bc30 | 853 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
854 | int next_tick = 5*HZ; |
855 | ||
856 | if (debug > 3) { | |
3ee307de BB |
857 | netdev_dbg(dev, "Media monitor tick, Tx status %8.8x.\n", |
858 | er32(TxSTAT)); | |
859 | netdev_dbg(dev, "Other registers are IntMask %4.4x IntStatus %4.4x RxStatus %4.4x.\n", | |
860 | er32(INTMASK), er32(INTSTAT), er32(RxSTAT)); | |
1da177e4 LT |
861 | } |
862 | ||
863 | check_media(dev); | |
864 | ||
865 | ep->timer.expires = jiffies + next_tick; | |
866 | add_timer(&ep->timer); | |
867 | } | |
868 | ||
0290bd29 | 869 | static void epic_tx_timeout(struct net_device *dev, unsigned int txqueue) |
1da177e4 | 870 | { |
4cf1653a | 871 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 872 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
873 | |
874 | if (debug > 0) { | |
3ee307de BB |
875 | netdev_warn(dev, "Transmit timeout using MII device, Tx status %4.4x.\n", |
876 | er16(TxSTAT)); | |
1da177e4 | 877 | if (debug > 1) { |
3ee307de BB |
878 | netdev_dbg(dev, "Tx indices: dirty_tx %d, cur_tx %d.\n", |
879 | ep->dirty_tx, ep->cur_tx); | |
1da177e4 LT |
880 | } |
881 | } | |
aae9bc30 | 882 | if (er16(TxSTAT) & 0x10) { /* Tx FIFO underflow. */ |
275defc9 | 883 | dev->stats.tx_fifo_errors++; |
aae9bc30 | 884 | ew32(COMMAND, RestartTx); |
1da177e4 LT |
885 | } else { |
886 | epic_restart(dev); | |
aae9bc30 | 887 | ew32(COMMAND, TxQueued); |
1da177e4 LT |
888 | } |
889 | ||
860e9538 | 890 | netif_trans_update(dev); /* prevent tx timeout */ |
275defc9 | 891 | dev->stats.tx_errors++; |
1da177e4 LT |
892 | if (!ep->tx_full) |
893 | netif_wake_queue(dev); | |
894 | } | |
895 | ||
896 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
897 | static void epic_init_ring(struct net_device *dev) | |
898 | { | |
4cf1653a | 899 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
900 | int i; |
901 | ||
902 | ep->tx_full = 0; | |
903 | ep->dirty_tx = ep->cur_tx = 0; | |
904 | ep->cur_rx = ep->dirty_rx = 0; | |
905 | ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
906 | ||
907 | /* Initialize all Rx descriptors. */ | |
908 | for (i = 0; i < RX_RING_SIZE; i++) { | |
909 | ep->rx_ring[i].rxstatus = 0; | |
9ebfd492 | 910 | ep->rx_ring[i].buflength = ep->rx_buf_sz; |
f3b197ac | 911 | ep->rx_ring[i].next = ep->rx_ring_dma + |
1da177e4 LT |
912 | (i+1)*sizeof(struct epic_rx_desc); |
913 | ep->rx_skbuff[i] = NULL; | |
914 | } | |
915 | /* Mark the last entry as wrapping the ring. */ | |
916 | ep->rx_ring[i-1].next = ep->rx_ring_dma; | |
917 | ||
918 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
919 | for (i = 0; i < RX_RING_SIZE; i++) { | |
dae2e9f4 | 920 | struct sk_buff *skb = netdev_alloc_skb(dev, ep->rx_buf_sz + 2); |
1da177e4 LT |
921 | ep->rx_skbuff[i] = skb; |
922 | if (skb == NULL) | |
923 | break; | |
1da177e4 | 924 | skb_reserve(skb, 2); /* 16 byte align the IP header. */ |
63692803 CJ |
925 | ep->rx_ring[i].bufaddr = dma_map_single(&ep->pci_dev->dev, |
926 | skb->data, | |
927 | ep->rx_buf_sz, | |
928 | DMA_FROM_DEVICE); | |
9ebfd492 | 929 | ep->rx_ring[i].rxstatus = DescOwn; |
1da177e4 LT |
930 | } |
931 | ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
932 | ||
933 | /* The Tx buffer descriptor is filled in as needed, but we | |
934 | do need to clear the ownership bit. */ | |
935 | for (i = 0; i < TX_RING_SIZE; i++) { | |
936 | ep->tx_skbuff[i] = NULL; | |
937 | ep->tx_ring[i].txstatus = 0x0000; | |
f3b197ac | 938 | ep->tx_ring[i].next = ep->tx_ring_dma + |
1da177e4 LT |
939 | (i+1)*sizeof(struct epic_tx_desc); |
940 | } | |
941 | ep->tx_ring[i-1].next = ep->tx_ring_dma; | |
1da177e4 LT |
942 | } |
943 | ||
61357325 | 944 | static netdev_tx_t epic_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 945 | { |
4cf1653a | 946 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 947 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
948 | int entry, free_count; |
949 | u32 ctrl_word; | |
950 | unsigned long flags; | |
f3b197ac | 951 | |
5b057c6b | 952 | if (skb_padto(skb, ETH_ZLEN)) |
6ed10654 | 953 | return NETDEV_TX_OK; |
1da177e4 LT |
954 | |
955 | /* Caution: the write order is important here, set the field with the | |
956 | "ownership" bit last. */ | |
957 | ||
958 | /* Calculate the next Tx descriptor entry. */ | |
959 | spin_lock_irqsave(&ep->lock, flags); | |
960 | free_count = ep->cur_tx - ep->dirty_tx; | |
961 | entry = ep->cur_tx % TX_RING_SIZE; | |
962 | ||
963 | ep->tx_skbuff[entry] = skb; | |
63692803 CJ |
964 | ep->tx_ring[entry].bufaddr = dma_map_single(&ep->pci_dev->dev, |
965 | skb->data, skb->len, | |
966 | DMA_TO_DEVICE); | |
1da177e4 | 967 | if (free_count < TX_QUEUE_LEN/2) {/* Typical path */ |
9ebfd492 | 968 | ctrl_word = 0x100000; /* No interrupt */ |
1da177e4 | 969 | } else if (free_count == TX_QUEUE_LEN/2) { |
9ebfd492 | 970 | ctrl_word = 0x140000; /* Tx-done intr. */ |
1da177e4 | 971 | } else if (free_count < TX_QUEUE_LEN - 1) { |
9ebfd492 | 972 | ctrl_word = 0x100000; /* No Tx-done intr. */ |
1da177e4 LT |
973 | } else { |
974 | /* Leave room for an additional entry. */ | |
9ebfd492 | 975 | ctrl_word = 0x140000; /* Tx-done intr. */ |
1da177e4 LT |
976 | ep->tx_full = 1; |
977 | } | |
9ebfd492 | 978 | ep->tx_ring[entry].buflength = ctrl_word | skb->len; |
1da177e4 LT |
979 | ep->tx_ring[entry].txstatus = |
980 | ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16) | |
9ebfd492 | 981 | | DescOwn; |
1da177e4 LT |
982 | |
983 | ep->cur_tx++; | |
984 | if (ep->tx_full) | |
985 | netif_stop_queue(dev); | |
986 | ||
987 | spin_unlock_irqrestore(&ep->lock, flags); | |
988 | /* Trigger an immediate transmit demand. */ | |
aae9bc30 | 989 | ew32(COMMAND, TxQueued); |
1da177e4 | 990 | |
1da177e4 | 991 | if (debug > 4) |
3ee307de BB |
992 | netdev_dbg(dev, "Queued Tx packet size %d to slot %d, flag %2.2x Tx status %8.8x.\n", |
993 | skb->len, entry, ctrl_word, er32(TxSTAT)); | |
1da177e4 | 994 | |
6ed10654 | 995 | return NETDEV_TX_OK; |
1da177e4 LT |
996 | } |
997 | ||
998 | static void epic_tx_error(struct net_device *dev, struct epic_private *ep, | |
999 | int status) | |
1000 | { | |
275defc9 | 1001 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1002 | |
1003 | #ifndef final_version | |
1004 | /* There was an major error, log it. */ | |
1005 | if (debug > 1) | |
3ee307de BB |
1006 | netdev_dbg(dev, "Transmit error, Tx status %8.8x.\n", |
1007 | status); | |
1da177e4 LT |
1008 | #endif |
1009 | stats->tx_errors++; | |
1010 | if (status & 0x1050) | |
1011 | stats->tx_aborted_errors++; | |
1012 | if (status & 0x0008) | |
1013 | stats->tx_carrier_errors++; | |
1014 | if (status & 0x0040) | |
1015 | stats->tx_window_errors++; | |
1016 | if (status & 0x0010) | |
1017 | stats->tx_fifo_errors++; | |
1018 | } | |
1019 | ||
1020 | static void epic_tx(struct net_device *dev, struct epic_private *ep) | |
1021 | { | |
1022 | unsigned int dirty_tx, cur_tx; | |
1023 | ||
1024 | /* | |
1025 | * Note: if this lock becomes a problem we can narrow the locked | |
1026 | * region at the cost of occasionally grabbing the lock more times. | |
1027 | */ | |
1028 | cur_tx = ep->cur_tx; | |
1029 | for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) { | |
1030 | struct sk_buff *skb; | |
1031 | int entry = dirty_tx % TX_RING_SIZE; | |
9ebfd492 | 1032 | int txstatus = ep->tx_ring[entry].txstatus; |
1da177e4 LT |
1033 | |
1034 | if (txstatus & DescOwn) | |
1035 | break; /* It still hasn't been Txed */ | |
1036 | ||
1037 | if (likely(txstatus & 0x0001)) { | |
275defc9 KV |
1038 | dev->stats.collisions += (txstatus >> 8) & 15; |
1039 | dev->stats.tx_packets++; | |
1040 | dev->stats.tx_bytes += ep->tx_skbuff[entry]->len; | |
1da177e4 LT |
1041 | } else |
1042 | epic_tx_error(dev, ep, txstatus); | |
1043 | ||
1044 | /* Free the original skb. */ | |
1045 | skb = ep->tx_skbuff[entry]; | |
63692803 CJ |
1046 | dma_unmap_single(&ep->pci_dev->dev, |
1047 | ep->tx_ring[entry].bufaddr, skb->len, | |
1048 | DMA_TO_DEVICE); | |
bb6a702c | 1049 | dev_consume_skb_irq(skb); |
1da177e4 LT |
1050 | ep->tx_skbuff[entry] = NULL; |
1051 | } | |
1052 | ||
1053 | #ifndef final_version | |
1054 | if (cur_tx - dirty_tx > TX_RING_SIZE) { | |
3ee307de BB |
1055 | netdev_warn(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d.\n", |
1056 | dirty_tx, cur_tx, ep->tx_full); | |
1da177e4 LT |
1057 | dirty_tx += TX_RING_SIZE; |
1058 | } | |
1059 | #endif | |
1060 | ep->dirty_tx = dirty_tx; | |
1061 | if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) { | |
1062 | /* The ring is no longer full, allow new TX entries. */ | |
1063 | ep->tx_full = 0; | |
1064 | netif_wake_queue(dev); | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1069 | after the Tx thread. */ | |
7d12e780 | 1070 | static irqreturn_t epic_interrupt(int irq, void *dev_instance) |
1da177e4 LT |
1071 | { |
1072 | struct net_device *dev = dev_instance; | |
4cf1653a | 1073 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 1074 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
1075 | unsigned int handled = 0; |
1076 | int status; | |
1077 | ||
aae9bc30 | 1078 | status = er32(INTSTAT); |
1da177e4 | 1079 | /* Acknowledge all of the current interrupt sources ASAP. */ |
aae9bc30 | 1080 | ew32(INTSTAT, status & EpicNormalEvent); |
1da177e4 LT |
1081 | |
1082 | if (debug > 4) { | |
3ee307de BB |
1083 | netdev_dbg(dev, "Interrupt, status=%#8.8x new intstat=%#8.8x.\n", |
1084 | status, er32(INTSTAT)); | |
1da177e4 LT |
1085 | } |
1086 | ||
1087 | if ((status & IntrSummary) == 0) | |
1088 | goto out; | |
1089 | ||
1090 | handled = 1; | |
1091 | ||
1fa8c5f3 | 1092 | if (status & EpicNapiEvent) { |
1da177e4 | 1093 | spin_lock(&ep->napi_lock); |
288379f0 | 1094 | if (napi_schedule_prep(&ep->napi)) { |
1da177e4 | 1095 | epic_napi_irq_off(dev, ep); |
288379f0 | 1096 | __napi_schedule(&ep->napi); |
1fa8c5f3 | 1097 | } |
1da177e4 LT |
1098 | spin_unlock(&ep->napi_lock); |
1099 | } | |
1100 | status &= ~EpicNapiEvent; | |
1101 | ||
1102 | /* Check uncommon events all at once. */ | |
1103 | if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) { | |
aae9bc30 FR |
1104 | struct net_device_stats *stats = &dev->stats; |
1105 | ||
1da177e4 LT |
1106 | if (status == EpicRemoved) |
1107 | goto out; | |
1108 | ||
1109 | /* Always update the error counts to avoid overhead later. */ | |
aae9bc30 FR |
1110 | stats->rx_missed_errors += er8(MPCNT); |
1111 | stats->rx_frame_errors += er8(ALICNT); | |
1112 | stats->rx_crc_errors += er8(CRCCNT); | |
1da177e4 LT |
1113 | |
1114 | if (status & TxUnderrun) { /* Tx FIFO underflow. */ | |
aae9bc30 FR |
1115 | stats->tx_fifo_errors++; |
1116 | ew32(TxThresh, ep->tx_threshold += 128); | |
1da177e4 | 1117 | /* Restart the transmit process. */ |
aae9bc30 | 1118 | ew32(COMMAND, RestartTx); |
1da177e4 LT |
1119 | } |
1120 | if (status & PCIBusErr170) { | |
3ee307de BB |
1121 | netdev_err(dev, "PCI Bus Error! status %4.4x.\n", |
1122 | status); | |
1da177e4 LT |
1123 | epic_pause(dev); |
1124 | epic_restart(dev); | |
1125 | } | |
1126 | /* Clear all error sources. */ | |
aae9bc30 | 1127 | ew32(INTSTAT, status & 0x7f18); |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | out: | |
1131 | if (debug > 3) { | |
3ee307de BB |
1132 | netdev_dbg(dev, "exit interrupt, intr_status=%#4.4x.\n", |
1133 | status); | |
1da177e4 LT |
1134 | } |
1135 | ||
1136 | return IRQ_RETVAL(handled); | |
1137 | } | |
1138 | ||
1139 | static int epic_rx(struct net_device *dev, int budget) | |
1140 | { | |
4cf1653a | 1141 | struct epic_private *ep = netdev_priv(dev); |
1da177e4 LT |
1142 | int entry = ep->cur_rx % RX_RING_SIZE; |
1143 | int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx; | |
1144 | int work_done = 0; | |
1145 | ||
1146 | if (debug > 4) | |
3ee307de | 1147 | netdev_dbg(dev, " In epic_rx(), entry %d %8.8x.\n", entry, |
1da177e4 LT |
1148 | ep->rx_ring[entry].rxstatus); |
1149 | ||
1150 | if (rx_work_limit > budget) | |
1151 | rx_work_limit = budget; | |
1152 | ||
1153 | /* If we own the next entry, it's a new packet. Send it up. */ | |
9ebfd492 AV |
1154 | while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) { |
1155 | int status = ep->rx_ring[entry].rxstatus; | |
1da177e4 LT |
1156 | |
1157 | if (debug > 4) | |
3ee307de BB |
1158 | netdev_dbg(dev, " epic_rx() status was %8.8x.\n", |
1159 | status); | |
1da177e4 LT |
1160 | if (--rx_work_limit < 0) |
1161 | break; | |
1162 | if (status & 0x2006) { | |
1163 | if (debug > 2) | |
3ee307de BB |
1164 | netdev_dbg(dev, "epic_rx() error status was %8.8x.\n", |
1165 | status); | |
1da177e4 | 1166 | if (status & 0x2000) { |
3ee307de BB |
1167 | netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %4.4x!\n", |
1168 | status); | |
275defc9 | 1169 | dev->stats.rx_length_errors++; |
1da177e4 LT |
1170 | } else if (status & 0x0006) |
1171 | /* Rx Frame errors are counted in hardware. */ | |
275defc9 | 1172 | dev->stats.rx_errors++; |
1da177e4 LT |
1173 | } else { |
1174 | /* Malloc up new buffer, compatible with net-2e. */ | |
1175 | /* Omit the four octet CRC from the length. */ | |
1176 | short pkt_len = (status >> 16) - 4; | |
1177 | struct sk_buff *skb; | |
1178 | ||
1179 | if (pkt_len > PKT_BUF_SZ - 4) { | |
3ee307de BB |
1180 | netdev_err(dev, "Oversized Ethernet frame, status %x %d bytes.\n", |
1181 | status, pkt_len); | |
1da177e4 LT |
1182 | pkt_len = 1514; |
1183 | } | |
1184 | /* Check if the packet is long enough to accept without copying | |
1185 | to a minimally-sized skbuff. */ | |
8e95a202 | 1186 | if (pkt_len < rx_copybreak && |
dae2e9f4 | 1187 | (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { |
1da177e4 | 1188 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
63692803 CJ |
1189 | dma_sync_single_for_cpu(&ep->pci_dev->dev, |
1190 | ep->rx_ring[entry].bufaddr, | |
1191 | ep->rx_buf_sz, | |
1192 | DMA_FROM_DEVICE); | |
8c7b7faa | 1193 | skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len); |
1da177e4 | 1194 | skb_put(skb, pkt_len); |
63692803 CJ |
1195 | dma_sync_single_for_device(&ep->pci_dev->dev, |
1196 | ep->rx_ring[entry].bufaddr, | |
1197 | ep->rx_buf_sz, | |
1198 | DMA_FROM_DEVICE); | |
1da177e4 | 1199 | } else { |
63692803 CJ |
1200 | dma_unmap_single(&ep->pci_dev->dev, |
1201 | ep->rx_ring[entry].bufaddr, | |
1202 | ep->rx_buf_sz, | |
1203 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1204 | skb_put(skb = ep->rx_skbuff[entry], pkt_len); |
1205 | ep->rx_skbuff[entry] = NULL; | |
1206 | } | |
1207 | skb->protocol = eth_type_trans(skb, dev); | |
1208 | netif_receive_skb(skb); | |
275defc9 KV |
1209 | dev->stats.rx_packets++; |
1210 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 LT |
1211 | } |
1212 | work_done++; | |
1213 | entry = (++ep->cur_rx) % RX_RING_SIZE; | |
1214 | } | |
1215 | ||
1216 | /* Refill the Rx ring buffers. */ | |
1217 | for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) { | |
1218 | entry = ep->dirty_rx % RX_RING_SIZE; | |
1219 | if (ep->rx_skbuff[entry] == NULL) { | |
1220 | struct sk_buff *skb; | |
dae2e9f4 | 1221 | skb = ep->rx_skbuff[entry] = netdev_alloc_skb(dev, ep->rx_buf_sz + 2); |
1da177e4 LT |
1222 | if (skb == NULL) |
1223 | break; | |
1da177e4 | 1224 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
63692803 CJ |
1225 | ep->rx_ring[entry].bufaddr = dma_map_single(&ep->pci_dev->dev, |
1226 | skb->data, | |
1227 | ep->rx_buf_sz, | |
1228 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1229 | work_done++; |
1230 | } | |
9ebfd492 AV |
1231 | /* AV: shouldn't we add a barrier here? */ |
1232 | ep->rx_ring[entry].rxstatus = DescOwn; | |
1da177e4 LT |
1233 | } |
1234 | return work_done; | |
1235 | } | |
1236 | ||
1237 | static void epic_rx_err(struct net_device *dev, struct epic_private *ep) | |
1238 | { | |
aae9bc30 | 1239 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
1240 | int status; |
1241 | ||
aae9bc30 | 1242 | status = er32(INTSTAT); |
1da177e4 LT |
1243 | |
1244 | if (status == EpicRemoved) | |
1245 | return; | |
1246 | if (status & RxOverflow) /* Missed a Rx frame. */ | |
275defc9 | 1247 | dev->stats.rx_errors++; |
1da177e4 | 1248 | if (status & (RxOverflow | RxFull)) |
aae9bc30 | 1249 | ew16(COMMAND, RxQueued); |
1da177e4 LT |
1250 | } |
1251 | ||
bea3348e | 1252 | static int epic_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1253 | { |
bea3348e SH |
1254 | struct epic_private *ep = container_of(napi, struct epic_private, napi); |
1255 | struct net_device *dev = ep->mii.dev; | |
aae9bc30 | 1256 | void __iomem *ioaddr = ep->ioaddr; |
1fa8c5f3 | 1257 | int work_done; |
1da177e4 LT |
1258 | |
1259 | epic_tx(dev, ep); | |
1260 | ||
1fa8c5f3 | 1261 | work_done = epic_rx(dev, budget); |
1da177e4 LT |
1262 | |
1263 | epic_rx_err(dev, ep); | |
1264 | ||
1fa8c5f3 | 1265 | if (work_done < budget && napi_complete_done(napi, work_done)) { |
1da177e4 | 1266 | unsigned long flags; |
1da177e4 LT |
1267 | |
1268 | spin_lock_irqsave(&ep->napi_lock, flags); | |
1269 | ||
1fa8c5f3 ED |
1270 | ew32(INTSTAT, EpicNapiEvent); |
1271 | epic_napi_irq_on(dev, ep); | |
1da177e4 | 1272 | spin_unlock_irqrestore(&ep->napi_lock, flags); |
1da177e4 LT |
1273 | } |
1274 | ||
bea3348e | 1275 | return work_done; |
1da177e4 LT |
1276 | } |
1277 | ||
1278 | static int epic_close(struct net_device *dev) | |
1279 | { | |
4cf1653a | 1280 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 FR |
1281 | struct pci_dev *pdev = ep->pci_dev; |
1282 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
1283 | struct sk_buff *skb; |
1284 | int i; | |
1285 | ||
1286 | netif_stop_queue(dev); | |
bea3348e | 1287 | napi_disable(&ep->napi); |
1da177e4 LT |
1288 | |
1289 | if (debug > 1) | |
3ee307de BB |
1290 | netdev_dbg(dev, "Shutting down ethercard, status was %2.2x.\n", |
1291 | er32(INTSTAT)); | |
1da177e4 LT |
1292 | |
1293 | del_timer_sync(&ep->timer); | |
1294 | ||
1295 | epic_disable_int(dev, ep); | |
1296 | ||
aae9bc30 | 1297 | free_irq(pdev->irq, dev); |
1da177e4 LT |
1298 | |
1299 | epic_pause(dev); | |
1300 | ||
1301 | /* Free all the skbuffs in the Rx queue. */ | |
1302 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1303 | skb = ep->rx_skbuff[i]; | |
1304 | ep->rx_skbuff[i] = NULL; | |
1305 | ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */ | |
1306 | ep->rx_ring[i].buflength = 0; | |
1307 | if (skb) { | |
63692803 CJ |
1308 | dma_unmap_single(&pdev->dev, ep->rx_ring[i].bufaddr, |
1309 | ep->rx_buf_sz, DMA_FROM_DEVICE); | |
1da177e4 LT |
1310 | dev_kfree_skb(skb); |
1311 | } | |
1312 | ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */ | |
1313 | } | |
1314 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1315 | skb = ep->tx_skbuff[i]; | |
1316 | ep->tx_skbuff[i] = NULL; | |
1317 | if (!skb) | |
1318 | continue; | |
63692803 CJ |
1319 | dma_unmap_single(&pdev->dev, ep->tx_ring[i].bufaddr, skb->len, |
1320 | DMA_TO_DEVICE); | |
1da177e4 LT |
1321 | dev_kfree_skb(skb); |
1322 | } | |
1323 | ||
1324 | /* Green! Leave the chip in low-power mode. */ | |
aae9bc30 | 1325 | ew32(GENCTL, 0x0008); |
1da177e4 LT |
1326 | |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | static struct net_device_stats *epic_get_stats(struct net_device *dev) | |
1331 | { | |
aae9bc30 FR |
1332 | struct epic_private *ep = netdev_priv(dev); |
1333 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
1334 | |
1335 | if (netif_running(dev)) { | |
aae9bc30 FR |
1336 | struct net_device_stats *stats = &dev->stats; |
1337 | ||
1338 | stats->rx_missed_errors += er8(MPCNT); | |
1339 | stats->rx_frame_errors += er8(ALICNT); | |
1340 | stats->rx_crc_errors += er8(CRCCNT); | |
1da177e4 LT |
1341 | } |
1342 | ||
275defc9 | 1343 | return &dev->stats; |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | /* Set or clear the multicast filter for this adaptor. | |
1347 | Note that we only use exclusion around actually queueing the | |
1348 | new frame, not around filling ep->setup_frame. This is non-deterministic | |
1349 | when re-entered but still correct. */ | |
1350 | ||
1351 | static void set_rx_mode(struct net_device *dev) | |
1352 | { | |
4cf1653a | 1353 | struct epic_private *ep = netdev_priv(dev); |
aae9bc30 | 1354 | void __iomem *ioaddr = ep->ioaddr; |
1da177e4 LT |
1355 | unsigned char mc_filter[8]; /* Multicast hash filter */ |
1356 | int i; | |
1357 | ||
1358 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
aae9bc30 | 1359 | ew32(RxCtrl, 0x002c); |
1da177e4 | 1360 | /* Unconditionally log net taps. */ |
1da177e4 | 1361 | memset(mc_filter, 0xff, sizeof(mc_filter)); |
4cd24eaf | 1362 | } else if ((!netdev_mc_empty(dev)) || (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
1363 | /* There is apparently a chip bug, so the multicast filter |
1364 | is never enabled. */ | |
1365 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1366 | memset(mc_filter, 0xff, sizeof(mc_filter)); | |
aae9bc30 | 1367 | ew32(RxCtrl, 0x000c); |
4cd24eaf | 1368 | } else if (netdev_mc_empty(dev)) { |
aae9bc30 | 1369 | ew32(RxCtrl, 0x0004); |
1da177e4 LT |
1370 | return; |
1371 | } else { /* Never executed, for now. */ | |
22bedad3 | 1372 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1373 | |
1374 | memset(mc_filter, 0, sizeof(mc_filter)); | |
22bedad3 | 1375 | netdev_for_each_mc_addr(ha, dev) { |
1da177e4 | 1376 | unsigned int bit_nr = |
22bedad3 | 1377 | ether_crc_le(ETH_ALEN, ha->addr) & 0x3f; |
1da177e4 LT |
1378 | mc_filter[bit_nr >> 3] |= (1 << bit_nr); |
1379 | } | |
1380 | } | |
1381 | /* ToDo: perhaps we need to stop the Tx and Rx process here? */ | |
1382 | if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) { | |
1383 | for (i = 0; i < 4; i++) | |
aae9bc30 | 1384 | ew16(MC0 + i*4, ((u16 *)mc_filter)[i]); |
1da177e4 LT |
1385 | memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter)); |
1386 | } | |
1da177e4 LT |
1387 | } |
1388 | ||
1389 | static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) | |
1390 | { | |
4cf1653a | 1391 | struct epic_private *np = netdev_priv(dev); |
1da177e4 | 1392 | |
68aad78c RJ |
1393 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
1394 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1395 | strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1396 | } |
1397 | ||
60269ae1 PR |
1398 | static int netdev_get_link_ksettings(struct net_device *dev, |
1399 | struct ethtool_link_ksettings *cmd) | |
1da177e4 | 1400 | { |
4cf1653a | 1401 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1402 | |
1403 | spin_lock_irq(&np->lock); | |
82c01a84 | 1404 | mii_ethtool_get_link_ksettings(&np->mii, cmd); |
1da177e4 LT |
1405 | spin_unlock_irq(&np->lock); |
1406 | ||
82c01a84 | 1407 | return 0; |
1da177e4 LT |
1408 | } |
1409 | ||
60269ae1 PR |
1410 | static int netdev_set_link_ksettings(struct net_device *dev, |
1411 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 | 1412 | { |
4cf1653a | 1413 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1414 | int rc; |
1415 | ||
1416 | spin_lock_irq(&np->lock); | |
60269ae1 | 1417 | rc = mii_ethtool_set_link_ksettings(&np->mii, cmd); |
1da177e4 LT |
1418 | spin_unlock_irq(&np->lock); |
1419 | ||
1420 | return rc; | |
1421 | } | |
1422 | ||
1423 | static int netdev_nway_reset(struct net_device *dev) | |
1424 | { | |
4cf1653a | 1425 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1426 | return mii_nway_restart(&np->mii); |
1427 | } | |
1428 | ||
1429 | static u32 netdev_get_link(struct net_device *dev) | |
1430 | { | |
4cf1653a | 1431 | struct epic_private *np = netdev_priv(dev); |
1da177e4 LT |
1432 | return mii_link_ok(&np->mii); |
1433 | } | |
1434 | ||
1435 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1436 | { | |
1437 | return debug; | |
1438 | } | |
1439 | ||
1440 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1441 | { | |
1442 | debug = value; | |
1443 | } | |
1444 | ||
1445 | static int ethtool_begin(struct net_device *dev) | |
1446 | { | |
aae9bc30 FR |
1447 | struct epic_private *ep = netdev_priv(dev); |
1448 | void __iomem *ioaddr = ep->ioaddr; | |
1449 | ||
4ac0ac84 MK |
1450 | if (ep->ethtool_ops_nesting == U32_MAX) |
1451 | return -EBUSY; | |
1da177e4 | 1452 | /* power-up, if interface is down */ |
4ac0ac84 | 1453 | if (!ep->ethtool_ops_nesting++ && !netif_running(dev)) { |
aae9bc30 FR |
1454 | ew32(GENCTL, 0x0200); |
1455 | ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); | |
1da177e4 LT |
1456 | } |
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | static void ethtool_complete(struct net_device *dev) | |
1461 | { | |
aae9bc30 FR |
1462 | struct epic_private *ep = netdev_priv(dev); |
1463 | void __iomem *ioaddr = ep->ioaddr; | |
1464 | ||
1da177e4 | 1465 | /* power-down, if interface is down */ |
4ac0ac84 | 1466 | if (!--ep->ethtool_ops_nesting && !netif_running(dev)) { |
aae9bc30 FR |
1467 | ew32(GENCTL, 0x0008); |
1468 | ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000); | |
1da177e4 LT |
1469 | } |
1470 | } | |
1471 | ||
7282d491 | 1472 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 | 1473 | .get_drvinfo = netdev_get_drvinfo, |
1da177e4 LT |
1474 | .nway_reset = netdev_nway_reset, |
1475 | .get_link = netdev_get_link, | |
1476 | .get_msglevel = netdev_get_msglevel, | |
1477 | .set_msglevel = netdev_set_msglevel, | |
1da177e4 | 1478 | .begin = ethtool_begin, |
60269ae1 PR |
1479 | .complete = ethtool_complete, |
1480 | .get_link_ksettings = netdev_get_link_ksettings, | |
1481 | .set_link_ksettings = netdev_set_link_ksettings, | |
1da177e4 LT |
1482 | }; |
1483 | ||
1484 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1485 | { | |
4cf1653a | 1486 | struct epic_private *np = netdev_priv(dev); |
aae9bc30 | 1487 | void __iomem *ioaddr = np->ioaddr; |
1da177e4 LT |
1488 | struct mii_ioctl_data *data = if_mii(rq); |
1489 | int rc; | |
1490 | ||
1491 | /* power-up, if interface is down */ | |
1492 | if (! netif_running(dev)) { | |
aae9bc30 FR |
1493 | ew32(GENCTL, 0x0200); |
1494 | ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800); | |
1da177e4 LT |
1495 | } |
1496 | ||
1497 | /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */ | |
1498 | spin_lock_irq(&np->lock); | |
1499 | rc = generic_mii_ioctl(&np->mii, data, cmd, NULL); | |
1500 | spin_unlock_irq(&np->lock); | |
1501 | ||
1502 | /* power-down, if interface is down */ | |
1503 | if (! netif_running(dev)) { | |
aae9bc30 FR |
1504 | ew32(GENCTL, 0x0008); |
1505 | ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000); | |
1da177e4 LT |
1506 | } |
1507 | return rc; | |
1508 | } | |
1509 | ||
1510 | ||
b0171cdc | 1511 | static void epic_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
1512 | { |
1513 | struct net_device *dev = pci_get_drvdata(pdev); | |
4cf1653a | 1514 | struct epic_private *ep = netdev_priv(dev); |
f3b197ac | 1515 | |
63692803 CJ |
1516 | dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, ep->tx_ring, |
1517 | ep->tx_ring_dma); | |
1518 | dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, ep->rx_ring, | |
1519 | ep->rx_ring_dma); | |
1da177e4 | 1520 | unregister_netdev(dev); |
aae9bc30 | 1521 | pci_iounmap(pdev, ep->ioaddr); |
1da177e4 LT |
1522 | pci_release_regions(pdev); |
1523 | free_netdev(dev); | |
1524 | pci_disable_device(pdev); | |
1da177e4 LT |
1525 | /* pci_power_off(pdev, -1); */ |
1526 | } | |
1527 | ||
622594f2 | 1528 | static int __maybe_unused epic_suspend(struct device *dev_d) |
1da177e4 | 1529 | { |
622594f2 | 1530 | struct net_device *dev = dev_get_drvdata(dev_d); |
aae9bc30 FR |
1531 | struct epic_private *ep = netdev_priv(dev); |
1532 | void __iomem *ioaddr = ep->ioaddr; | |
1da177e4 LT |
1533 | |
1534 | if (!netif_running(dev)) | |
1535 | return 0; | |
1536 | epic_pause(dev); | |
1537 | /* Put the chip into low-power mode. */ | |
aae9bc30 | 1538 | ew32(GENCTL, 0x0008); |
1da177e4 LT |
1539 | /* pci_power_off(pdev, -1); */ |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | ||
622594f2 | 1544 | static int __maybe_unused epic_resume(struct device *dev_d) |
1da177e4 | 1545 | { |
622594f2 | 1546 | struct net_device *dev = dev_get_drvdata(dev_d); |
1da177e4 LT |
1547 | |
1548 | if (!netif_running(dev)) | |
1549 | return 0; | |
1550 | epic_restart(dev); | |
1551 | /* pci_power_on(pdev); */ | |
1552 | return 0; | |
1553 | } | |
1554 | ||
622594f2 | 1555 | static SIMPLE_DEV_PM_OPS(epic_pm_ops, epic_suspend, epic_resume); |
1da177e4 LT |
1556 | |
1557 | static struct pci_driver epic_driver = { | |
1558 | .name = DRV_NAME, | |
1559 | .id_table = epic_pci_tbl, | |
1560 | .probe = epic_init_one, | |
b0171cdc | 1561 | .remove = epic_remove_one, |
622594f2 | 1562 | .driver.pm = &epic_pm_ops, |
1da177e4 LT |
1563 | }; |
1564 | ||
1565 | ||
1566 | static int __init epic_init (void) | |
1567 | { | |
1568 | /* when a module, this is printed whether or not devices are found in probe */ | |
1569 | #ifdef MODULE | |
3ee307de | 1570 | pr_info("%s%s\n", version, version2); |
1da177e4 LT |
1571 | #endif |
1572 | ||
29917620 | 1573 | return pci_register_driver(&epic_driver); |
1da177e4 LT |
1574 | } |
1575 | ||
1576 | ||
1577 | static void __exit epic_cleanup (void) | |
1578 | { | |
1579 | pci_unregister_driver (&epic_driver); | |
1580 | } | |
1581 | ||
1582 | ||
1583 | module_init(epic_init); | |
1584 | module_exit(epic_cleanup); |