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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / smsc / smc911x.c
CommitLineData
0a0c72c9
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1/*
2 * smc911x.c
3 * This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
4 *
5 * Copyright (C) 2005 Sensoria Corp
6 * Derived from the unified SMC91x driver by Nicolas Pitre
d5498bef 7 * and the smsc911x.c reference driver by SMSC
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8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
0ab75ae8 20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
0a0c72c9
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21 *
22 * Arguments:
23 * watchdog = TX watchdog timeout
24 * tx_fifo_kb = Size of TX FIFO in KB
25 *
26 * History:
27 * 04/16/05 Dustin McIntire Initial version
28 */
29static const char version[] =
30 "smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
31
32/* Debugging options */
33#define ENABLE_SMC_DEBUG_RX 0
34#define ENABLE_SMC_DEBUG_TX 0
35#define ENABLE_SMC_DEBUG_DMA 0
36#define ENABLE_SMC_DEBUG_PKTS 0
37#define ENABLE_SMC_DEBUG_MISC 0
38#define ENABLE_SMC_DEBUG_FUNC 0
39
40#define SMC_DEBUG_RX ((ENABLE_SMC_DEBUG_RX ? 1 : 0) << 0)
41#define SMC_DEBUG_TX ((ENABLE_SMC_DEBUG_TX ? 1 : 0) << 1)
42#define SMC_DEBUG_DMA ((ENABLE_SMC_DEBUG_DMA ? 1 : 0) << 2)
43#define SMC_DEBUG_PKTS ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
44#define SMC_DEBUG_MISC ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
45#define SMC_DEBUG_FUNC ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
46
47#ifndef SMC_DEBUG
48#define SMC_DEBUG ( SMC_DEBUG_RX | \
49 SMC_DEBUG_TX | \
50 SMC_DEBUG_DMA | \
51 SMC_DEBUG_PKTS | \
52 SMC_DEBUG_MISC | \
53 SMC_DEBUG_FUNC \
54 )
55#endif
56
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57#include <linux/module.h>
58#include <linux/kernel.h>
59#include <linux/sched.h>
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60#include <linux/delay.h>
61#include <linux/interrupt.h>
62#include <linux/errno.h>
63#include <linux/ioport.h>
64#include <linux/crc32.h>
65#include <linux/device.h>
66#include <linux/platform_device.h>
67#include <linux/spinlock.h>
68#include <linux/ethtool.h>
69#include <linux/mii.h>
70#include <linux/workqueue.h>
71
72#include <linux/netdevice.h>
73#include <linux/etherdevice.h>
74#include <linux/skbuff.h>
75
76#include <asm/io.h>
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77
78#include "smc911x.h"
79
80/*
81 * Transmit timeout, default 5 seconds.
82 */
83static int watchdog = 5000;
84module_param(watchdog, int, 0400);
85MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
86
87static int tx_fifo_kb=8;
88module_param(tx_fifo_kb, int, 0400);
89MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
90
91MODULE_LICENSE("GPL");
72abb461 92MODULE_ALIAS("platform:smc911x");
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93
94/*
95 * The internal workings of the driver. If you are changing anything
96 * here with the SMC stuff, you should have the datasheet and know
97 * what you are doing.
98 */
99#define CARDNAME "smc911x"
100
101/*
102 * Use power-down feature of the chip
103 */
104#define POWER_DOWN 1
105
0a0c72c9 106#if SMC_DEBUG > 0
dcdf8710 107#define DBG(n, dev, args...) \
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108 do { \
109 if (SMC_DEBUG & (n)) \
dcdf8710 110 netdev_dbg(dev, args); \
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111 } while (0)
112
dcdf8710 113#define PRINTK(dev, args...) netdev_info(dev, args)
0a0c72c9 114#else
dcdf8710
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115#define DBG(n, dev, args...) do { } while (0)
116#define PRINTK(dev, args...) netdev_dbg(dev, args)
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117#endif
118
119#if SMC_DEBUG_PKTS > 0
120static void PRINT_PKT(u_char *buf, int length)
121{
122 int i;
123 int remainder;
124 int lines;
125
126 lines = length / 16;
127 remainder = length % 16;
128
129 for (i = 0; i < lines ; i ++) {
130 int cur;
dcdf8710 131 printk(KERN_DEBUG);
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132 for (cur = 0; cur < 8; cur++) {
133 u_char a, b;
134 a = *buf++;
135 b = *buf++;
dcdf8710 136 pr_cont("%02x%02x ", a, b);
0a0c72c9 137 }
dcdf8710 138 pr_cont("\n");
0a0c72c9 139 }
dcdf8710 140 printk(KERN_DEBUG);
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141 for (i = 0; i < remainder/2 ; i++) {
142 u_char a, b;
143 a = *buf++;
144 b = *buf++;
dcdf8710 145 pr_cont("%02x%02x ", a, b);
0a0c72c9 146 }
dcdf8710 147 pr_cont("\n");
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148}
149#else
150#define PRINT_PKT(x...) do { } while (0)
151#endif
152
153
154/* this enables an interrupt in the interrupt mask register */
699559f8 155#define SMC_ENABLE_INT(lp, x) do { \
0a0c72c9 156 unsigned int __mask; \
699559f8 157 __mask = SMC_GET_INT_EN((lp)); \
0a0c72c9 158 __mask |= (x); \
699559f8 159 SMC_SET_INT_EN((lp), __mask); \
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160} while (0)
161
162/* this disables an interrupt from the interrupt mask register */
699559f8 163#define SMC_DISABLE_INT(lp, x) do { \
0a0c72c9 164 unsigned int __mask; \
699559f8 165 __mask = SMC_GET_INT_EN((lp)); \
0a0c72c9 166 __mask &= ~(x); \
699559f8 167 SMC_SET_INT_EN((lp), __mask); \
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168} while (0)
169
170/*
171 * this does a soft reset on the device
172 */
173static void smc911x_reset(struct net_device *dev)
174{
0a0c72c9 175 struct smc911x_local *lp = netdev_priv(dev);
319edafe 176 unsigned int reg, timeout=0, resets=1, irq_cfg;
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177 unsigned long flags;
178
dcdf8710 179 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
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180
181 /* Take out of PM setting first */
699559f8 182 if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
0a0c72c9 183 /* Write to the bytetest will take out of powerdown */
699559f8 184 SMC_SET_BYTE_TEST(lp, 0);
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185 timeout=10;
186 do {
187 udelay(10);
699559f8 188 reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
db2961c5 189 } while (--timeout && !reg);
0a0c72c9 190 if (timeout == 0) {
dcdf8710 191 PRINTK(dev, "smc911x_reset timeout waiting for PM restore\n");
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192 return;
193 }
194 }
195
196 /* Disable all interrupts */
197 spin_lock_irqsave(&lp->lock, flags);
699559f8 198 SMC_SET_INT_EN(lp, 0);
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199 spin_unlock_irqrestore(&lp->lock, flags);
200
201 while (resets--) {
699559f8 202 SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
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203 timeout=10;
204 do {
205 udelay(10);
699559f8 206 reg = SMC_GET_HW_CFG(lp);
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207 /* If chip indicates reset timeout then try again */
208 if (reg & HW_CFG_SRST_TO_) {
dcdf8710 209 PRINTK(dev, "chip reset timeout, retrying...\n");
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210 resets++;
211 break;
212 }
db2961c5 213 } while (--timeout && (reg & HW_CFG_SRST_));
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214 }
215 if (timeout == 0) {
dcdf8710 216 PRINTK(dev, "smc911x_reset timeout waiting for reset\n");
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217 return;
218 }
219
220 /* make sure EEPROM has finished loading before setting GPIO_CFG */
221 timeout=1000;
46578a69 222 while (--timeout && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_))
0a0c72c9 223 udelay(10);
46578a69 224
0a0c72c9 225 if (timeout == 0){
dcdf8710 226 PRINTK(dev, "smc911x_reset timeout waiting for EEPROM busy\n");
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227 return;
228 }
229
230 /* Initialize interrupts */
699559f8
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231 SMC_SET_INT_EN(lp, 0);
232 SMC_ACK_INT(lp, -1);
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233
234 /* Reset the FIFO level and flow control settings */
699559f8 235 SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
0a0c72c9 236//TODO: Figure out what appropriate pause time is
699559f8
MD
237 SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
238 SMC_SET_AFC_CFG(lp, lp->afc_cfg);
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239
240
241 /* Set to LED outputs */
699559f8 242 SMC_SET_GPIO_CFG(lp, 0x70070000);
0a0c72c9 243
d5498bef 244 /*
0a0c72c9 245 * Deassert IRQ for 1*10us for edge type interrupts
d5498bef 246 * and drive IRQ pin push-pull
0a0c72c9 247 */
319edafe
CM
248 irq_cfg = (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_;
249#ifdef SMC_DYNAMIC_BUS_CONFIG
250 if (lp->cfg.irq_polarity)
251 irq_cfg |= INT_CFG_IRQ_POL_;
252#endif
253 SMC_SET_IRQ_CFG(lp, irq_cfg);
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254
255 /* clear anything saved */
256 if (lp->pending_tx_skb != NULL) {
257 dev_kfree_skb (lp->pending_tx_skb);
258 lp->pending_tx_skb = NULL;
09f75cd7
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259 dev->stats.tx_errors++;
260 dev->stats.tx_aborted_errors++;
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261 }
262}
263
264/*
265 * Enable Interrupts, Receive, and Transmit
266 */
267static void smc911x_enable(struct net_device *dev)
268{
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269 struct smc911x_local *lp = netdev_priv(dev);
270 unsigned mask, cfg, cr;
271 unsigned long flags;
272
dcdf8710 273 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9 274
b891a902
CM
275 spin_lock_irqsave(&lp->lock, flags);
276
699559f8 277 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
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278
279 /* Enable TX */
699559f8 280 cfg = SMC_GET_HW_CFG(lp);
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281 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
282 cfg |= HW_CFG_SF_;
699559f8
MD
283 SMC_SET_HW_CFG(lp, cfg);
284 SMC_SET_FIFO_TDA(lp, 0xFF);
0a0c72c9 285 /* Update TX stats on every 64 packets received or every 1 sec */
699559f8
MD
286 SMC_SET_FIFO_TSL(lp, 64);
287 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
0a0c72c9 288
699559f8 289 SMC_GET_MAC_CR(lp, cr);
0a0c72c9 290 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
699559f8
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291 SMC_SET_MAC_CR(lp, cr);
292 SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
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293
294 /* Add 2 byte padding to start of packets */
699559f8 295 SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
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296
297 /* Turn on receiver and enable RX */
298 if (cr & MAC_CR_RXEN_)
dcdf8710 299 DBG(SMC_DEBUG_RX, dev, "Receiver already enabled\n");
0a0c72c9 300
699559f8 301 SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
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302
303 /* Interrupt on every received packet */
699559f8
MD
304 SMC_SET_FIFO_RSA(lp, 0x01);
305 SMC_SET_FIFO_RSL(lp, 0x00);
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306
307 /* now, enable interrupts */
d5498bef
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308 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
309 INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
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310 INT_EN_PHY_INT_EN_;
311 if (IS_REV_A(lp->revision))
312 mask|=INT_EN_RDFL_EN_;
313 else {
314 mask|=INT_EN_RDFO_EN_;
315 }
699559f8 316 SMC_ENABLE_INT(lp, mask);
b891a902
CM
317
318 spin_unlock_irqrestore(&lp->lock, flags);
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319}
320
321/*
322 * this puts the device in an inactive state
323 */
324static void smc911x_shutdown(struct net_device *dev)
325{
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326 struct smc911x_local *lp = netdev_priv(dev);
327 unsigned cr;
328 unsigned long flags;
329
dcdf8710 330 DBG(SMC_DEBUG_FUNC, dev, "%s: --> %s\n", CARDNAME, __func__);
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331
332 /* Disable IRQ's */
699559f8 333 SMC_SET_INT_EN(lp, 0);
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334
335 /* Turn of Rx and TX */
336 spin_lock_irqsave(&lp->lock, flags);
699559f8 337 SMC_GET_MAC_CR(lp, cr);
0a0c72c9 338 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
699559f8
MD
339 SMC_SET_MAC_CR(lp, cr);
340 SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
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341 spin_unlock_irqrestore(&lp->lock, flags);
342}
343
344static inline void smc911x_drop_pkt(struct net_device *dev)
d5498bef 345{
699559f8 346 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
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347 unsigned int fifo_count, timeout, reg;
348
dcdf8710
BB
349 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, dev, "%s: --> %s\n",
350 CARDNAME, __func__);
699559f8 351 fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
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352 if (fifo_count <= 4) {
353 /* Manually dump the packet data */
354 while (fifo_count--)
699559f8 355 SMC_GET_RX_FIFO(lp);
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356 } else {
357 /* Fast forward through the bad packet */
699559f8 358 SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
0a0c72c9
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359 timeout=50;
360 do {
361 udelay(10);
699559f8 362 reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
db2961c5 363 } while (--timeout && reg);
0a0c72c9 364 if (timeout == 0) {
dcdf8710 365 PRINTK(dev, "timeout waiting for RX fast forward\n");
0a0c72c9
DM
366 }
367 }
368}
369
370/*
371 * This is the procedure to handle the receipt of a packet.
372 * It should be called after checking for packet presence in
d5498bef 373 * the RX status FIFO. It must be called with the spin lock
0a0c72c9
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374 * already held.
375 */
376static inline void smc911x_rcv(struct net_device *dev)
377{
699559f8 378 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
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379 unsigned int pkt_len, status;
380 struct sk_buff *skb;
381 unsigned char *data;
382
dcdf8710
BB
383 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, dev, "--> %s\n",
384 __func__);
699559f8 385 status = SMC_GET_RX_STS_FIFO(lp);
dcdf8710
BB
386 DBG(SMC_DEBUG_RX, dev, "Rx pkt len %d status 0x%08x\n",
387 (status & 0x3fff0000) >> 16, status & 0xc000ffff);
0a0c72c9 388 pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
d5498bef 389 if (status & RX_STS_ES_) {
0a0c72c9 390 /* Deal with a bad packet */
09f75cd7 391 dev->stats.rx_errors++;
d5498bef 392 if (status & RX_STS_CRC_ERR_)
09f75cd7 393 dev->stats.rx_crc_errors++;
0a0c72c9
DM
394 else {
395 if (status & RX_STS_LEN_ERR_)
09f75cd7 396 dev->stats.rx_length_errors++;
d5498bef 397 if (status & RX_STS_MCAST_)
09f75cd7 398 dev->stats.multicast++;
0a0c72c9
DM
399 }
400 /* Remove the bad packet data from the RX FIFO */
401 smc911x_drop_pkt(dev);
402 } else {
403 /* Receive a valid packet */
404 /* Alloc a buffer with extra room for DMA alignment */
dae2e9f4 405 skb = netdev_alloc_skb(dev, pkt_len+32);
0a0c72c9 406 if (unlikely(skb == NULL)) {
dcdf8710 407 PRINTK(dev, "Low memory, rcvd packet dropped.\n");
09f75cd7 408 dev->stats.rx_dropped++;
0a0c72c9
DM
409 smc911x_drop_pkt(dev);
410 return;
411 }
d5498bef 412 /* Align IP header to 32 bits
0a0c72c9 413 * Note that the device is configured to add a 2
d5498bef 414 * byte padding to the packet start, so we really
0a0c72c9
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415 * want to write to the orignal data pointer */
416 data = skb->data;
417 skb_reserve(skb, 2);
418 skb_put(skb,pkt_len-4);
419#ifdef SMC_USE_DMA
420 {
421 unsigned int fifo;
422 /* Lower the FIFO threshold if possible */
699559f8 423 fifo = SMC_GET_FIFO_INT(lp);
0a0c72c9 424 if (fifo & 0xFF) fifo--;
dcdf8710
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425 DBG(SMC_DEBUG_RX, dev, "Setting RX stat FIFO threshold to %d\n",
426 fifo & 0xff);
699559f8 427 SMC_SET_FIFO_INT(lp, fifo);
0a0c72c9 428 /* Setup RX DMA */
699559f8 429 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
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430 lp->rxdma_active = 1;
431 lp->current_rx_skb = skb;
699559f8 432 SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
0a0c72c9
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433 /* Packet processing deferred to DMA RX interrupt */
434 }
435#else
699559f8
MD
436 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
437 SMC_PULL_DATA(lp, data, pkt_len+2+3);
0a0c72c9 438
dcdf8710 439 DBG(SMC_DEBUG_PKTS, dev, "Received packet\n");
0a0c72c9 440 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
0a0c72c9
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441 skb->protocol = eth_type_trans(skb, dev);
442 netif_rx(skb);
09f75cd7
JG
443 dev->stats.rx_packets++;
444 dev->stats.rx_bytes += pkt_len-4;
0a0c72c9
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445#endif
446 }
447}
448
449/*
450 * This is called to actually send a packet to the chip.
451 */
452static void smc911x_hardware_send_pkt(struct net_device *dev)
453{
454 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
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455 struct sk_buff *skb;
456 unsigned int cmdA, cmdB, len;
457 unsigned char *buf;
0a0c72c9 458
dcdf8710 459 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n", __func__);
0a0c72c9
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460 BUG_ON(lp->pending_tx_skb == NULL);
461
462 skb = lp->pending_tx_skb;
463 lp->pending_tx_skb = NULL;
464
d5498bef
JG
465 /* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
466 /* cmdB {31:16] pkt tag [10:0] length */
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467#ifdef SMC_USE_DMA
468 /* 16 byte buffer alignment mode */
469 buf = (char*)((u32)(skb->data) & ~0xF);
d5498bef 470 len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
0a0c72c9
DM
471 cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
472 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
473 skb->len;
474#else
475 buf = (char*)((u32)skb->data & ~0x3);
d5498bef 476 len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
0a0c72c9
DM
477 cmdA = (((u32)skb->data & 0x3) << 16) |
478 TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
479 skb->len;
480#endif
d5498bef 481 /* tag is packet length so we can use this in stats update later */
0a0c72c9 482 cmdB = (skb->len << 16) | (skb->len & 0x7FF);
d5498bef 483
dcdf8710
BB
484 DBG(SMC_DEBUG_TX, dev, "TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
485 len, len, buf, cmdA, cmdB);
699559f8
MD
486 SMC_SET_TX_FIFO(lp, cmdA);
487 SMC_SET_TX_FIFO(lp, cmdB);
0a0c72c9 488
dcdf8710 489 DBG(SMC_DEBUG_PKTS, dev, "Transmitted packet\n");
0a0c72c9
DM
490 PRINT_PKT(buf, len <= 64 ? len : 64);
491
492 /* Send pkt via PIO or DMA */
493#ifdef SMC_USE_DMA
494 lp->current_tx_skb = skb;
699559f8 495 SMC_PUSH_DATA(lp, buf, len);
0a0c72c9
DM
496 /* DMA complete IRQ will free buffer and set jiffies */
497#else
699559f8 498 SMC_PUSH_DATA(lp, buf, len);
0a0c72c9 499 dev->trans_start = jiffies;
70d9d158 500 dev_kfree_skb_irq(skb);
0a0c72c9 501#endif
0a0c72c9
DM
502 if (!lp->tx_throttle) {
503 netif_wake_queue(dev);
504 }
699559f8 505 SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
0a0c72c9
DM
506}
507
508/*
509 * Since I am not sure if I will have enough room in the chip's ram
510 * to store the packet, I call this routine which either sends it
511 * now, or set the card to generates an interrupt when ready
512 * for the packet.
513 */
514static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
515{
516 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
517 unsigned int free;
518 unsigned long flags;
519
dcdf8710
BB
520 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n",
521 __func__);
0a0c72c9 522
b891a902
CM
523 spin_lock_irqsave(&lp->lock, flags);
524
0a0c72c9
DM
525 BUG_ON(lp->pending_tx_skb != NULL);
526
699559f8 527 free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
dcdf8710 528 DBG(SMC_DEBUG_TX, dev, "TX free space %d\n", free);
0a0c72c9
DM
529
530 /* Turn off the flow when running out of space in FIFO */
531 if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
dcdf8710
BB
532 DBG(SMC_DEBUG_TX, dev, "Disabling data flow due to low FIFO space (%d)\n",
533 free);
0a0c72c9 534 /* Reenable when at least 1 packet of size MTU present */
699559f8 535 SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
0a0c72c9
DM
536 lp->tx_throttle = 1;
537 netif_stop_queue(dev);
0a0c72c9
DM
538 }
539
d5498bef 540 /* Drop packets when we run out of space in TX FIFO
0a0c72c9 541 * Account for overhead required for:
d5498bef
JG
542 *
543 * Tx command words 8 bytes
0a0c72c9
DM
544 * Start offset 15 bytes
545 * End padding 15 bytes
d5498bef 546 */
0a0c72c9 547 if (unlikely(free < (skb->len + 8 + 15 + 15))) {
dcdf8710
BB
548 netdev_warn(dev, "No Tx free space %d < %d\n",
549 free, skb->len);
0a0c72c9 550 lp->pending_tx_skb = NULL;
09f75cd7
JG
551 dev->stats.tx_errors++;
552 dev->stats.tx_dropped++;
b891a902 553 spin_unlock_irqrestore(&lp->lock, flags);
d27ab53c 554 dev_kfree_skb_any(skb);
6ed10654 555 return NETDEV_TX_OK;
0a0c72c9 556 }
d5498bef 557
0a0c72c9
DM
558#ifdef SMC_USE_DMA
559 {
560 /* If the DMA is already running then defer this packet Tx until
d5498bef 561 * the DMA IRQ starts it
0a0c72c9 562 */
0a0c72c9 563 if (lp->txdma_active) {
dcdf8710 564 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "Tx DMA running, deferring packet\n");
0a0c72c9
DM
565 lp->pending_tx_skb = skb;
566 netif_stop_queue(dev);
567 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 568 return NETDEV_TX_OK;
0a0c72c9 569 } else {
dcdf8710 570 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "Activating Tx DMA\n");
0a0c72c9
DM
571 lp->txdma_active = 1;
572 }
0a0c72c9
DM
573 }
574#endif
575 lp->pending_tx_skb = skb;
576 smc911x_hardware_send_pkt(dev);
b891a902 577 spin_unlock_irqrestore(&lp->lock, flags);
0a0c72c9 578
6ed10654 579 return NETDEV_TX_OK;
0a0c72c9
DM
580}
581
582/*
583 * This handles a TX status interrupt, which is only called when:
584 * - a TX error occurred, or
585 * - TX of a packet completed.
586 */
587static void smc911x_tx(struct net_device *dev)
588{
0a0c72c9
DM
589 struct smc911x_local *lp = netdev_priv(dev);
590 unsigned int tx_status;
591
dcdf8710
BB
592 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, dev, "--> %s\n",
593 __func__);
0a0c72c9
DM
594
595 /* Collect the TX status */
699559f8 596 while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
dcdf8710
BB
597 DBG(SMC_DEBUG_TX, dev, "Tx stat FIFO used 0x%04x\n",
598 (SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
699559f8 599 tx_status = SMC_GET_TX_STS_FIFO(lp);
09f75cd7
JG
600 dev->stats.tx_packets++;
601 dev->stats.tx_bytes+=tx_status>>16;
dcdf8710
BB
602 DBG(SMC_DEBUG_TX, dev, "Tx FIFO tag 0x%04x status 0x%04x\n",
603 (tx_status & 0xffff0000) >> 16,
604 tx_status & 0x0000ffff);
d5498bef 605 /* count Tx errors, but ignore lost carrier errors when in
0a0c72c9 606 * full-duplex mode */
d5498bef 607 if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
0a0c72c9 608 !(tx_status & 0x00000306))) {
09f75cd7 609 dev->stats.tx_errors++;
0a0c72c9
DM
610 }
611 if (tx_status & TX_STS_MANY_COLL_) {
09f75cd7
JG
612 dev->stats.collisions+=16;
613 dev->stats.tx_aborted_errors++;
0a0c72c9 614 } else {
09f75cd7 615 dev->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
0a0c72c9
DM
616 }
617 /* carrier error only has meaning for half-duplex communication */
d5498bef 618 if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
0a0c72c9 619 !lp->ctl_rfduplx) {
09f75cd7 620 dev->stats.tx_carrier_errors++;
d5498bef 621 }
0a0c72c9 622 if (tx_status & TX_STS_LATE_COLL_) {
09f75cd7
JG
623 dev->stats.collisions++;
624 dev->stats.tx_aborted_errors++;
0a0c72c9
DM
625 }
626 }
627}
628
629
630/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
631/*
632 * Reads a register from the MII Management serial interface
633 */
634
635static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
636{
699559f8 637 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
638 unsigned int phydata;
639
699559f8 640 SMC_GET_MII(lp, phyreg, phyaddr, phydata);
0a0c72c9 641
dcdf8710
BB
642 DBG(SMC_DEBUG_MISC, dev, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
643 __func__, phyaddr, phyreg, phydata);
0a0c72c9
DM
644 return phydata;
645}
646
647
648/*
649 * Writes a register to the MII Management serial interface
650 */
651static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
652 int phydata)
653{
699559f8 654 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9 655
dcdf8710
BB
656 DBG(SMC_DEBUG_MISC, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
657 __func__, phyaddr, phyreg, phydata);
0a0c72c9 658
699559f8 659 SMC_SET_MII(lp, phyreg, phyaddr, phydata);
0a0c72c9
DM
660}
661
662/*
663 * Finds and reports the PHY address (115 and 117 have external
664 * PHY interface 118 has internal only
665 */
666static void smc911x_phy_detect(struct net_device *dev)
667{
0a0c72c9
DM
668 struct smc911x_local *lp = netdev_priv(dev);
669 int phyaddr;
670 unsigned int cfg, id1, id2;
671
dcdf8710 672 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
673
674 lp->phy_type = 0;
675
676 /*
677 * Scan all 32 PHY addresses if necessary, starting at
678 * PHY#1 to PHY#31, and then PHY#0 last.
679 */
680 switch(lp->version) {
c6dcb827
GL
681 case CHIP_9115:
682 case CHIP_9117:
683 case CHIP_9215:
684 case CHIP_9217:
699559f8 685 cfg = SMC_GET_HW_CFG(lp);
0a0c72c9
DM
686 if (cfg & HW_CFG_EXT_PHY_DET_) {
687 cfg &= ~HW_CFG_PHY_CLK_SEL_;
688 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
699559f8 689 SMC_SET_HW_CFG(lp, cfg);
0a0c72c9
DM
690 udelay(10); /* Wait for clocks to stop */
691
692 cfg |= HW_CFG_EXT_PHY_EN_;
699559f8 693 SMC_SET_HW_CFG(lp, cfg);
0a0c72c9
DM
694 udelay(10); /* Wait for clocks to stop */
695
696 cfg &= ~HW_CFG_PHY_CLK_SEL_;
697 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
699559f8 698 SMC_SET_HW_CFG(lp, cfg);
0a0c72c9
DM
699 udelay(10); /* Wait for clocks to stop */
700
701 cfg |= HW_CFG_SMI_SEL_;
699559f8 702 SMC_SET_HW_CFG(lp, cfg);
0a0c72c9
DM
703
704 for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
705
706 /* Read the PHY identifiers */
699559f8
MD
707 SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
708 SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
0a0c72c9
DM
709
710 /* Make sure it is a valid identifier */
d5498bef
JG
711 if (id1 != 0x0000 && id1 != 0xffff &&
712 id1 != 0x8000 && id2 != 0x0000 &&
0a0c72c9
DM
713 id2 != 0xffff && id2 != 0x8000) {
714 /* Save the PHY's address */
715 lp->mii.phy_id = phyaddr & 31;
716 lp->phy_type = id1 << 16 | id2;
717 break;
718 }
719 }
f3073ac7
GL
720 if (phyaddr < 32)
721 /* Found an external PHY */
722 break;
0a0c72c9
DM
723 }
724 default:
725 /* Internal media only */
699559f8
MD
726 SMC_GET_PHY_ID1(lp, 1, id1);
727 SMC_GET_PHY_ID2(lp, 1, id2);
0a0c72c9
DM
728 /* Save the PHY's address */
729 lp->mii.phy_id = 1;
730 lp->phy_type = id1 << 16 | id2;
731 }
732
45dfab68 733 DBG(SMC_DEBUG_MISC, dev, "phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%x\n",
dcdf8710 734 id1, id2, lp->mii.phy_id);
0a0c72c9
DM
735}
736
737/*
738 * Sets the PHY to a configuration as determined by the user.
739 * Called with spin_lock held.
740 */
741static int smc911x_phy_fixed(struct net_device *dev)
742{
743 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
744 int phyaddr = lp->mii.phy_id;
745 int bmcr;
746
dcdf8710 747 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
748
749 /* Enter Link Disable state */
699559f8 750 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
0a0c72c9 751 bmcr |= BMCR_PDOWN;
699559f8 752 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
0a0c72c9
DM
753
754 /*
755 * Set our fixed capabilities
756 * Disable auto-negotiation
757 */
758 bmcr &= ~BMCR_ANENABLE;
759 if (lp->ctl_rfduplx)
760 bmcr |= BMCR_FULLDPLX;
761
762 if (lp->ctl_rspeed == 100)
763 bmcr |= BMCR_SPEED100;
764
765 /* Write our capabilities to the phy control register */
699559f8 766 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
0a0c72c9
DM
767
768 /* Re-Configure the Receive/Phy Control register */
769 bmcr &= ~BMCR_PDOWN;
699559f8 770 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
0a0c72c9
DM
771
772 return 1;
773}
774
49ce9c2c 775/**
0a0c72c9
DM
776 * smc911x_phy_reset - reset the phy
777 * @dev: net device
778 * @phy: phy address
779 *
780 * Issue a software reset for the specified PHY and
781 * wait up to 100ms for the reset to complete. We should
782 * not access the PHY for 50ms after issuing the reset.
783 *
784 * The time to wait appears to be dependent on the PHY.
785 *
786 */
787static int smc911x_phy_reset(struct net_device *dev, int phy)
788{
789 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
790 int timeout;
791 unsigned long flags;
792 unsigned int reg;
793
dcdf8710 794 DBG(SMC_DEBUG_FUNC, dev, "--> %s()\n", __func__);
0a0c72c9
DM
795
796 spin_lock_irqsave(&lp->lock, flags);
699559f8 797 reg = SMC_GET_PMT_CTRL(lp);
0a0c72c9
DM
798 reg &= ~0xfffff030;
799 reg |= PMT_CTRL_PHY_RST_;
699559f8 800 SMC_SET_PMT_CTRL(lp, reg);
0a0c72c9
DM
801 spin_unlock_irqrestore(&lp->lock, flags);
802 for (timeout = 2; timeout; timeout--) {
803 msleep(50);
804 spin_lock_irqsave(&lp->lock, flags);
699559f8 805 reg = SMC_GET_PMT_CTRL(lp);
0a0c72c9
DM
806 spin_unlock_irqrestore(&lp->lock, flags);
807 if (!(reg & PMT_CTRL_PHY_RST_)) {
d5498bef 808 /* extra delay required because the phy may
0a0c72c9 809 * not be completed with its reset
d5498bef 810 * when PHY_BCR_RESET_ is cleared. 256us
0a0c72c9
DM
811 * should suffice, but use 500us to be safe
812 */
813 udelay(500);
814 break;
815 }
816 }
817
818 return reg & PMT_CTRL_PHY_RST_;
819}
820
49ce9c2c 821/**
0a0c72c9
DM
822 * smc911x_phy_powerdown - powerdown phy
823 * @dev: net device
824 * @phy: phy address
825 *
826 * Power down the specified PHY
827 */
828static void smc911x_phy_powerdown(struct net_device *dev, int phy)
829{
699559f8 830 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
831 unsigned int bmcr;
832
833 /* Enter Link Disable state */
699559f8 834 SMC_GET_PHY_BMCR(lp, phy, bmcr);
0a0c72c9 835 bmcr |= BMCR_PDOWN;
699559f8 836 SMC_SET_PHY_BMCR(lp, phy, bmcr);
0a0c72c9
DM
837}
838
49ce9c2c 839/**
0a0c72c9
DM
840 * smc911x_phy_check_media - check the media status and adjust BMCR
841 * @dev: net device
842 * @init: set true for initialisation
843 *
844 * Select duplex mode depending on negotiation state. This
845 * also updates our carrier state.
846 */
847static void smc911x_phy_check_media(struct net_device *dev, int init)
848{
849 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
850 int phyaddr = lp->mii.phy_id;
851 unsigned int bmcr, cr;
852
dcdf8710 853 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
854
855 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
856 /* duplex state has changed */
699559f8
MD
857 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
858 SMC_GET_MAC_CR(lp, cr);
0a0c72c9 859 if (lp->mii.full_duplex) {
dcdf8710 860 DBG(SMC_DEBUG_MISC, dev, "Configuring for full-duplex mode\n");
0a0c72c9
DM
861 bmcr |= BMCR_FULLDPLX;
862 cr |= MAC_CR_RCVOWN_;
863 } else {
dcdf8710 864 DBG(SMC_DEBUG_MISC, dev, "Configuring for half-duplex mode\n");
0a0c72c9
DM
865 bmcr &= ~BMCR_FULLDPLX;
866 cr &= ~MAC_CR_RCVOWN_;
867 }
699559f8
MD
868 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
869 SMC_SET_MAC_CR(lp, cr);
0a0c72c9
DM
870 }
871}
872
873/*
874 * Configures the specified PHY through the MII management interface
875 * using Autonegotiation.
876 * Calls smc911x_phy_fixed() if the user has requested a certain config.
877 * If RPC ANEG bit is set, the media selection is dependent purely on
878 * the selection by the MII (either in the MII BMCR reg or the result
879 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
880 * is controlled by the RPC SPEED and RPC DPLX bits.
881 */
ef8142a5 882static void smc911x_phy_configure(struct work_struct *work)
0a0c72c9 883{
ef8142a5
AM
884 struct smc911x_local *lp = container_of(work, struct smc911x_local,
885 phy_configure);
886 struct net_device *dev = lp->netdev;
0a0c72c9
DM
887 int phyaddr = lp->mii.phy_id;
888 int my_phy_caps; /* My PHY capabilities */
889 int my_ad_caps; /* My Advertised capabilities */
890 int status;
891 unsigned long flags;
892
dcdf8710 893 DBG(SMC_DEBUG_FUNC, dev, "--> %s()\n", __func__);
0a0c72c9
DM
894
895 /*
896 * We should not be called if phy_type is zero.
897 */
898 if (lp->phy_type == 0)
4bb073c0 899 return;
0a0c72c9
DM
900
901 if (smc911x_phy_reset(dev, phyaddr)) {
dcdf8710 902 netdev_info(dev, "PHY reset timed out\n");
4bb073c0 903 return;
0a0c72c9
DM
904 }
905 spin_lock_irqsave(&lp->lock, flags);
906
907 /*
908 * Enable PHY Interrupts (for register 18)
909 * Interrupts listed here are enabled
910 */
699559f8 911 SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
0a0c72c9
DM
912 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
913 PHY_INT_MASK_LINK_DOWN_);
914
915 /* If the user requested no auto neg, then go set his request */
916 if (lp->mii.force_media) {
917 smc911x_phy_fixed(dev);
918 goto smc911x_phy_configure_exit;
919 }
920
921 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
699559f8 922 SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
0a0c72c9 923 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
dcdf8710 924 netdev_info(dev, "Auto negotiation NOT supported\n");
0a0c72c9
DM
925 smc911x_phy_fixed(dev);
926 goto smc911x_phy_configure_exit;
927 }
928
929 /* CSMA capable w/ both pauses */
930 my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
931
932 if (my_phy_caps & BMSR_100BASE4)
933 my_ad_caps |= ADVERTISE_100BASE4;
934 if (my_phy_caps & BMSR_100FULL)
935 my_ad_caps |= ADVERTISE_100FULL;
936 if (my_phy_caps & BMSR_100HALF)
937 my_ad_caps |= ADVERTISE_100HALF;
938 if (my_phy_caps & BMSR_10FULL)
939 my_ad_caps |= ADVERTISE_10FULL;
940 if (my_phy_caps & BMSR_10HALF)
941 my_ad_caps |= ADVERTISE_10HALF;
942
943 /* Disable capabilities not selected by our user */
944 if (lp->ctl_rspeed != 100)
945 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
946
947 if (!lp->ctl_rfduplx)
948 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
949
950 /* Update our Auto-Neg Advertisement Register */
699559f8 951 SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
0a0c72c9
DM
952 lp->mii.advertising = my_ad_caps;
953
954 /*
955 * Read the register back. Without this, it appears that when
956 * auto-negotiation is restarted, sometimes it isn't ready and
957 * the link does not come up.
958 */
959 udelay(10);
699559f8 960 SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
0a0c72c9 961
dcdf8710
BB
962 DBG(SMC_DEBUG_MISC, dev, "phy caps=0x%04x\n", my_phy_caps);
963 DBG(SMC_DEBUG_MISC, dev, "phy advertised caps=0x%04x\n", my_ad_caps);
0a0c72c9
DM
964
965 /* Restart auto-negotiation process in order to advertise my caps */
699559f8 966 SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
0a0c72c9
DM
967
968 smc911x_phy_check_media(dev, 1);
969
970smc911x_phy_configure_exit:
971 spin_unlock_irqrestore(&lp->lock, flags);
0a0c72c9
DM
972}
973
974/*
975 * smc911x_phy_interrupt
976 *
977 * Purpose: Handle interrupts relating to PHY register 18. This is
978 * called from the "hard" interrupt handler under our private spinlock.
979 */
980static void smc911x_phy_interrupt(struct net_device *dev)
981{
982 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
983 int phyaddr = lp->mii.phy_id;
984 int status;
985
dcdf8710 986 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
987
988 if (lp->phy_type == 0)
989 return;
990
991 smc911x_phy_check_media(dev, 0);
992 /* read to clear status bits */
699559f8 993 SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
dcdf8710
BB
994 DBG(SMC_DEBUG_MISC, dev, "PHY interrupt status 0x%04x\n",
995 status & 0xffff);
996 DBG(SMC_DEBUG_MISC, dev, "AFC_CFG 0x%08x\n",
997 SMC_GET_AFC_CFG(lp));
0a0c72c9
DM
998}
999
1000/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1001
1002/*
1003 * This is the main routine of the driver, to handle the device when
1004 * it needs some attention.
1005 */
7d12e780 1006static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
0a0c72c9
DM
1007{
1008 struct net_device *dev = dev_id;
0a0c72c9
DM
1009 struct smc911x_local *lp = netdev_priv(dev);
1010 unsigned int status, mask, timeout;
1011 unsigned int rx_overrun=0, cr, pkts;
1012 unsigned long flags;
1013
dcdf8710 1014 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1015
1016 spin_lock_irqsave(&lp->lock, flags);
1017
1018 /* Spurious interrupt check */
699559f8 1019 if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
0a0c72c9 1020 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
a4d09272 1021 spin_unlock_irqrestore(&lp->lock, flags);
0a0c72c9
DM
1022 return IRQ_NONE;
1023 }
1024
699559f8
MD
1025 mask = SMC_GET_INT_EN(lp);
1026 SMC_SET_INT_EN(lp, 0);
0a0c72c9
DM
1027
1028 /* set a timeout value, so I don't stay here forever */
1029 timeout = 8;
1030
1031
1032 do {
699559f8 1033 status = SMC_GET_INT(lp);
0a0c72c9 1034
dcdf8710
BB
1035 DBG(SMC_DEBUG_MISC, dev, "INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1036 status, mask, status & ~mask);
0a0c72c9
DM
1037
1038 status &= mask;
1039 if (!status)
1040 break;
1041
1042 /* Handle SW interrupt condition */
1043 if (status & INT_STS_SW_INT_) {
699559f8 1044 SMC_ACK_INT(lp, INT_STS_SW_INT_);
0a0c72c9
DM
1045 mask &= ~INT_EN_SW_INT_EN_;
1046 }
1047 /* Handle various error conditions */
1048 if (status & INT_STS_RXE_) {
699559f8 1049 SMC_ACK_INT(lp, INT_STS_RXE_);
09f75cd7 1050 dev->stats.rx_errors++;
d5498bef 1051 }
0a0c72c9 1052 if (status & INT_STS_RXDFH_INT_) {
699559f8
MD
1053 SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
1054 dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
0a0c72c9
DM
1055 }
1056 /* Undocumented interrupt-what is the right thing to do here? */
1057 if (status & INT_STS_RXDF_INT_) {
699559f8 1058 SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
0a0c72c9
DM
1059 }
1060
1061 /* Rx Data FIFO exceeds set level */
1062 if (status & INT_STS_RDFL_) {
1063 if (IS_REV_A(lp->revision)) {
1064 rx_overrun=1;
699559f8 1065 SMC_GET_MAC_CR(lp, cr);
0a0c72c9 1066 cr &= ~MAC_CR_RXEN_;
699559f8 1067 SMC_SET_MAC_CR(lp, cr);
dcdf8710 1068 DBG(SMC_DEBUG_RX, dev, "RX overrun\n");
09f75cd7
JG
1069 dev->stats.rx_errors++;
1070 dev->stats.rx_fifo_errors++;
0a0c72c9 1071 }
699559f8 1072 SMC_ACK_INT(lp, INT_STS_RDFL_);
0a0c72c9
DM
1073 }
1074 if (status & INT_STS_RDFO_) {
1075 if (!IS_REV_A(lp->revision)) {
699559f8 1076 SMC_GET_MAC_CR(lp, cr);
0a0c72c9 1077 cr &= ~MAC_CR_RXEN_;
699559f8 1078 SMC_SET_MAC_CR(lp, cr);
0a0c72c9 1079 rx_overrun=1;
dcdf8710 1080 DBG(SMC_DEBUG_RX, dev, "RX overrun\n");
09f75cd7
JG
1081 dev->stats.rx_errors++;
1082 dev->stats.rx_fifo_errors++;
0a0c72c9 1083 }
699559f8 1084 SMC_ACK_INT(lp, INT_STS_RDFO_);
0a0c72c9
DM
1085 }
1086 /* Handle receive condition */
1087 if ((status & INT_STS_RSFL_) || rx_overrun) {
1088 unsigned int fifo;
dcdf8710 1089 DBG(SMC_DEBUG_RX, dev, "RX irq\n");
699559f8 1090 fifo = SMC_GET_RX_FIFO_INF(lp);
d5498bef 1091 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
dcdf8710
BB
1092 DBG(SMC_DEBUG_RX, dev, "Rx FIFO pkts %d, bytes %d\n",
1093 pkts, fifo & 0xFFFF);
0a0c72c9
DM
1094 if (pkts != 0) {
1095#ifdef SMC_USE_DMA
1096 unsigned int fifo;
1097 if (lp->rxdma_active){
dcdf8710
BB
1098 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev,
1099 "RX DMA active\n");
0a0c72c9 1100 /* The DMA is already running so up the IRQ threshold */
699559f8 1101 fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
0a0c72c9 1102 fifo |= pkts & 0xFF;
dcdf8710
BB
1103 DBG(SMC_DEBUG_RX, dev,
1104 "Setting RX stat FIFO threshold to %d\n",
1105 fifo & 0xff);
699559f8 1106 SMC_SET_FIFO_INT(lp, fifo);
0a0c72c9
DM
1107 } else
1108#endif
1109 smc911x_rcv(dev);
1110 }
699559f8 1111 SMC_ACK_INT(lp, INT_STS_RSFL_);
0a0c72c9
DM
1112 }
1113 /* Handle transmit FIFO available */
1114 if (status & INT_STS_TDFA_) {
dcdf8710 1115 DBG(SMC_DEBUG_TX, dev, "TX data FIFO space available irq\n");
699559f8 1116 SMC_SET_FIFO_TDA(lp, 0xFF);
0a0c72c9
DM
1117 lp->tx_throttle = 0;
1118#ifdef SMC_USE_DMA
1119 if (!lp->txdma_active)
1120#endif
1121 netif_wake_queue(dev);
699559f8 1122 SMC_ACK_INT(lp, INT_STS_TDFA_);
0a0c72c9
DM
1123 }
1124 /* Handle transmit done condition */
1125#if 1
1126 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
dcdf8710
BB
1127 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC, dev,
1128 "Tx stat FIFO limit (%d) /GPT irq\n",
1129 (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
0a0c72c9 1130 smc911x_tx(dev);
699559f8
MD
1131 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1132 SMC_ACK_INT(lp, INT_STS_TSFL_);
1133 SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
0a0c72c9
DM
1134 }
1135#else
1136 if (status & INT_STS_TSFL_) {
dcdf8710 1137 DBG(SMC_DEBUG_TX, dev, "TX status FIFO limit (%d) irq\n", ?);
0a0c72c9 1138 smc911x_tx(dev);
699559f8 1139 SMC_ACK_INT(lp, INT_STS_TSFL_);
0a0c72c9
DM
1140 }
1141
1142 if (status & INT_STS_GPT_INT_) {
dcdf8710
BB
1143 DBG(SMC_DEBUG_RX, dev, "IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1144 SMC_GET_IRQ_CFG(lp),
1145 SMC_GET_FIFO_INT(lp),
1146 SMC_GET_RX_CFG(lp));
1147 DBG(SMC_DEBUG_RX, dev, "Rx Stat FIFO Used 0x%02x Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
1148 (SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
1149 SMC_GET_RX_FIFO_INF(lp) & 0xffff,
1150 SMC_GET_RX_STS_FIFO_PEEK(lp));
699559f8
MD
1151 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1152 SMC_ACK_INT(lp, INT_STS_GPT_INT_);
0a0c72c9
DM
1153 }
1154#endif
1155
3a4fa0a2 1156 /* Handle PHY interrupt condition */
0a0c72c9 1157 if (status & INT_STS_PHY_INT_) {
dcdf8710 1158 DBG(SMC_DEBUG_MISC, dev, "PHY irq\n");
0a0c72c9 1159 smc911x_phy_interrupt(dev);
699559f8 1160 SMC_ACK_INT(lp, INT_STS_PHY_INT_);
0a0c72c9
DM
1161 }
1162 } while (--timeout);
1163
1164 /* restore mask state */
699559f8 1165 SMC_SET_INT_EN(lp, mask);
0a0c72c9 1166
dcdf8710
BB
1167 DBG(SMC_DEBUG_MISC, dev, "Interrupt done (%d loops)\n",
1168 8-timeout);
0a0c72c9
DM
1169
1170 spin_unlock_irqrestore(&lp->lock, flags);
1171
0a0c72c9
DM
1172 return IRQ_HANDLED;
1173}
1174
1175#ifdef SMC_USE_DMA
1176static void
7d12e780 1177smc911x_tx_dma_irq(int dma, void *data)
0a0c72c9
DM
1178{
1179 struct net_device *dev = (struct net_device *)data;
1180 struct smc911x_local *lp = netdev_priv(dev);
1181 struct sk_buff *skb = lp->current_tx_skb;
1182 unsigned long flags;
1183
dcdf8710 1184 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9 1185
dcdf8710 1186 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev, "TX DMA irq handler\n");
0a0c72c9
DM
1187 /* Clear the DMA interrupt sources */
1188 SMC_DMA_ACK_IRQ(dev, dma);
1189 BUG_ON(skb == NULL);
1190 dma_unmap_single(NULL, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
1191 dev->trans_start = jiffies;
1192 dev_kfree_skb_irq(skb);
1193 lp->current_tx_skb = NULL;
1194 if (lp->pending_tx_skb != NULL)
1195 smc911x_hardware_send_pkt(dev);
1196 else {
dcdf8710
BB
1197 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev,
1198 "No pending Tx packets. DMA disabled\n");
0a0c72c9
DM
1199 spin_lock_irqsave(&lp->lock, flags);
1200 lp->txdma_active = 0;
1201 if (!lp->tx_throttle) {
1202 netif_wake_queue(dev);
1203 }
1204 spin_unlock_irqrestore(&lp->lock, flags);
1205 }
1206
dcdf8710
BB
1207 DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, dev,
1208 "TX DMA irq completed\n");
0a0c72c9
DM
1209}
1210static void
7d12e780 1211smc911x_rx_dma_irq(int dma, void *data)
0a0c72c9
DM
1212{
1213 struct net_device *dev = (struct net_device *)data;
0a0c72c9
DM
1214 struct smc911x_local *lp = netdev_priv(dev);
1215 struct sk_buff *skb = lp->current_rx_skb;
1216 unsigned long flags;
1217 unsigned int pkts;
1218
dcdf8710
BB
1219 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
1220 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev, "RX DMA irq handler\n");
0a0c72c9
DM
1221 /* Clear the DMA interrupt sources */
1222 SMC_DMA_ACK_IRQ(dev, dma);
1223 dma_unmap_single(NULL, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
1224 BUG_ON(skb == NULL);
1225 lp->current_rx_skb = NULL;
1226 PRINT_PKT(skb->data, skb->len);
0a0c72c9 1227 skb->protocol = eth_type_trans(skb, dev);
09f75cd7
JG
1228 dev->stats.rx_packets++;
1229 dev->stats.rx_bytes += skb->len;
d30f53ae 1230 netif_rx(skb);
0a0c72c9
DM
1231
1232 spin_lock_irqsave(&lp->lock, flags);
d766a4ed 1233 pkts = (SMC_GET_RX_FIFO_INF(lp) & RX_FIFO_INF_RXSUSED_) >> 16;
0a0c72c9
DM
1234 if (pkts != 0) {
1235 smc911x_rcv(dev);
1236 }else {
1237 lp->rxdma_active = 0;
1238 }
1239 spin_unlock_irqrestore(&lp->lock, flags);
dcdf8710
BB
1240 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, dev,
1241 "RX DMA irq completed. DMA RX FIFO PKTS %d\n",
1242 pkts);
0a0c72c9
DM
1243}
1244#endif /* SMC_USE_DMA */
1245
1246#ifdef CONFIG_NET_POLL_CONTROLLER
1247/*
1248 * Polling receive - used by netconsole and other diagnostic tools
1249 * to allow network i/o with interrupts disabled.
1250 */
1251static void smc911x_poll_controller(struct net_device *dev)
1252{
1253 disable_irq(dev->irq);
9b6d2efe 1254 smc911x_interrupt(dev->irq, dev);
0a0c72c9
DM
1255 enable_irq(dev->irq);
1256}
1257#endif
1258
1259/* Our watchdog timed out. Called by the networking layer */
1260static void smc911x_timeout(struct net_device *dev)
1261{
1262 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1263 int status, mask;
1264 unsigned long flags;
1265
dcdf8710 1266 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1267
1268 spin_lock_irqsave(&lp->lock, flags);
699559f8
MD
1269 status = SMC_GET_INT(lp);
1270 mask = SMC_GET_INT_EN(lp);
0a0c72c9 1271 spin_unlock_irqrestore(&lp->lock, flags);
dcdf8710
BB
1272 DBG(SMC_DEBUG_MISC, dev, "INT 0x%02x MASK 0x%02x\n",
1273 status, mask);
0a0c72c9
DM
1274
1275 /* Dump the current TX FIFO contents and restart */
699559f8
MD
1276 mask = SMC_GET_TX_CFG(lp);
1277 SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
0a0c72c9
DM
1278 /*
1279 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1280 * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
1281 * which calls schedule(). Hence we use a work queue.
1282 */
4bb073c0
DM
1283 if (lp->phy_type != 0)
1284 schedule_work(&lp->phy_configure);
0a0c72c9
DM
1285
1286 /* We can accept TX packets again */
1ae5dc34 1287 dev->trans_start = jiffies; /* prevent tx timeout */
0a0c72c9
DM
1288 netif_wake_queue(dev);
1289}
1290
1291/*
1292 * This routine will, depending on the values passed to it,
1293 * either make it accept multicast packets, go into
1294 * promiscuous mode (for TCPDUMP and cousins) or accept
1295 * a select set of multicast packets
1296 */
1297static void smc911x_set_multicast_list(struct net_device *dev)
1298{
1299 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1300 unsigned int multicast_table[2];
1301 unsigned int mcr, update_multicast = 0;
1302 unsigned long flags;
0a0c72c9 1303
dcdf8710 1304 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1305
1306 spin_lock_irqsave(&lp->lock, flags);
699559f8 1307 SMC_GET_MAC_CR(lp, mcr);
0a0c72c9
DM
1308 spin_unlock_irqrestore(&lp->lock, flags);
1309
1310 if (dev->flags & IFF_PROMISC) {
1311
dcdf8710 1312 DBG(SMC_DEBUG_MISC, dev, "RCR_PRMS\n");
0a0c72c9
DM
1313 mcr |= MAC_CR_PRMS_;
1314 }
1315 /*
1316 * Here, I am setting this to accept all multicast packets.
1317 * I don't need to zero the multicast table, because the flag is
1318 * checked before the table is
1319 */
4cd24eaf 1320 else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
dcdf8710 1321 DBG(SMC_DEBUG_MISC, dev, "RCR_ALMUL\n");
0a0c72c9
DM
1322 mcr |= MAC_CR_MCPAS_;
1323 }
1324
1325 /*
1326 * This sets the internal hardware table to filter out unwanted
1327 * multicast packets before they take up memory.
1328 *
1329 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1330 * address are the offset into the table. If that bit is 1, then the
1331 * multicast packet is accepted. Otherwise, it's dropped silently.
1332 *
1333 * To use the 6 bits as an offset into the table, the high 1 bit is
1334 * the number of the 32 bit register, while the low 5 bits are the bit
1335 * within that register.
1336 */
4cd24eaf 1337 else if (!netdev_mc_empty(dev)) {
22bedad3 1338 struct netdev_hw_addr *ha;
0a0c72c9
DM
1339
1340 /* Set the Hash perfec mode */
1341 mcr |= MAC_CR_HPFILT_;
1342
1343 /* start with a table of all zeros: reject all */
1344 memset(multicast_table, 0, sizeof(multicast_table));
1345
22bedad3 1346 netdev_for_each_mc_addr(ha, dev) {
7b31f7ff 1347 u32 position;
0a0c72c9 1348
7b31f7ff 1349 /* upper 6 bits are used as hash index */
22bedad3 1350 position = ether_crc(ETH_ALEN, ha->addr)>>26;
0a0c72c9 1351
7b31f7ff 1352 multicast_table[position>>5] |= 1 << (position&0x1f);
0a0c72c9
DM
1353 }
1354
1355 /* be sure I get rid of flags I might have set */
1356 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1357
1358 /* now, the table can be loaded into the chipset */
1359 update_multicast = 1;
1360 } else {
dcdf8710 1361 DBG(SMC_DEBUG_MISC, dev, "~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n");
0a0c72c9
DM
1362 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1363
1364 /*
1365 * since I'm disabling all multicast entirely, I need to
1366 * clear the multicast list
1367 */
1368 memset(multicast_table, 0, sizeof(multicast_table));
1369 update_multicast = 1;
1370 }
1371
1372 spin_lock_irqsave(&lp->lock, flags);
699559f8 1373 SMC_SET_MAC_CR(lp, mcr);
0a0c72c9 1374 if (update_multicast) {
dcdf8710
BB
1375 DBG(SMC_DEBUG_MISC, dev,
1376 "update mcast hash table 0x%08x 0x%08x\n",
1377 multicast_table[0], multicast_table[1]);
699559f8
MD
1378 SMC_SET_HASHL(lp, multicast_table[0]);
1379 SMC_SET_HASHH(lp, multicast_table[1]);
0a0c72c9
DM
1380 }
1381 spin_unlock_irqrestore(&lp->lock, flags);
1382}
1383
1384
1385/*
1386 * Open and Initialize the board
1387 *
1388 * Set up everything, reset the card, etc..
1389 */
1390static int
1391smc911x_open(struct net_device *dev)
1392{
ef8142a5
AM
1393 struct smc911x_local *lp = netdev_priv(dev);
1394
dcdf8710 1395 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9 1396
0a0c72c9
DM
1397 /* reset the hardware */
1398 smc911x_reset(dev);
1399
1400 /* Configure the PHY, initialize the link state */
ef8142a5 1401 smc911x_phy_configure(&lp->phy_configure);
0a0c72c9
DM
1402
1403 /* Turn on Tx + Rx */
1404 smc911x_enable(dev);
1405
1406 netif_start_queue(dev);
1407
1408 return 0;
1409}
1410
1411/*
1412 * smc911x_close
1413 *
1414 * this makes the board clean up everything that it can
1415 * and not talk to the outside world. Caused by
1416 * an 'ifconfig ethX down'
1417 */
1418static int smc911x_close(struct net_device *dev)
1419{
1420 struct smc911x_local *lp = netdev_priv(dev);
1421
dcdf8710 1422 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1423
1424 netif_stop_queue(dev);
1425 netif_carrier_off(dev);
1426
1427 /* clear everything */
1428 smc911x_shutdown(dev);
1429
1430 if (lp->phy_type != 0) {
1431 /* We need to ensure that no calls to
1432 * smc911x_phy_configure are pending.
0a0c72c9 1433 */
4bb073c0 1434 cancel_work_sync(&lp->phy_configure);
0a0c72c9
DM
1435 smc911x_phy_powerdown(dev, lp->mii.phy_id);
1436 }
1437
1438 if (lp->pending_tx_skb) {
1439 dev_kfree_skb(lp->pending_tx_skb);
1440 lp->pending_tx_skb = NULL;
1441 }
1442
1443 return 0;
1444}
1445
0a0c72c9
DM
1446/*
1447 * Ethtool support
1448 */
1449static int
1450smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1451{
1452 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1453 int ret, status;
1454 unsigned long flags;
1455
dcdf8710 1456 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1457 cmd->maxtxpkt = 1;
1458 cmd->maxrxpkt = 1;
1459
1460 if (lp->phy_type != 0) {
1461 spin_lock_irqsave(&lp->lock, flags);
1462 ret = mii_ethtool_gset(&lp->mii, cmd);
1463 spin_unlock_irqrestore(&lp->lock, flags);
1464 } else {
1465 cmd->supported = SUPPORTED_10baseT_Half |
1466 SUPPORTED_10baseT_Full |
1467 SUPPORTED_TP | SUPPORTED_AUI;
1468
1469 if (lp->ctl_rspeed == 10)
70739497 1470 ethtool_cmd_speed_set(cmd, SPEED_10);
0a0c72c9 1471 else if (lp->ctl_rspeed == 100)
70739497 1472 ethtool_cmd_speed_set(cmd, SPEED_100);
0a0c72c9
DM
1473
1474 cmd->autoneg = AUTONEG_DISABLE;
1475 if (lp->mii.phy_id==1)
1476 cmd->transceiver = XCVR_INTERNAL;
1477 else
1478 cmd->transceiver = XCVR_EXTERNAL;
1479 cmd->port = 0;
699559f8 1480 SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
d5498bef
JG
1481 cmd->duplex =
1482 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
0a0c72c9
DM
1483 DUPLEX_FULL : DUPLEX_HALF;
1484 ret = 0;
1485 }
1486
1487 return ret;
1488}
1489
1490static int
1491smc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1492{
1493 struct smc911x_local *lp = netdev_priv(dev);
1494 int ret;
1495 unsigned long flags;
1496
1497 if (lp->phy_type != 0) {
1498 spin_lock_irqsave(&lp->lock, flags);
1499 ret = mii_ethtool_sset(&lp->mii, cmd);
1500 spin_unlock_irqrestore(&lp->lock, flags);
1501 } else {
1502 if (cmd->autoneg != AUTONEG_DISABLE ||
1503 cmd->speed != SPEED_10 ||
1504 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1505 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1506 return -EINVAL;
1507
1508 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1509
1510 ret = 0;
1511 }
1512
1513 return ret;
1514}
1515
1516static void
1517smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1518{
7826d43f
JP
1519 strlcpy(info->driver, CARDNAME, sizeof(info->driver));
1520 strlcpy(info->version, version, sizeof(info->version));
1521 strlcpy(info->bus_info, dev_name(dev->dev.parent),
1522 sizeof(info->bus_info));
0a0c72c9
DM
1523}
1524
1525static int smc911x_ethtool_nwayreset(struct net_device *dev)
1526{
1527 struct smc911x_local *lp = netdev_priv(dev);
1528 int ret = -EINVAL;
1529 unsigned long flags;
1530
1531 if (lp->phy_type != 0) {
1532 spin_lock_irqsave(&lp->lock, flags);
1533 ret = mii_nway_restart(&lp->mii);
1534 spin_unlock_irqrestore(&lp->lock, flags);
1535 }
1536
1537 return ret;
1538}
1539
1540static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
1541{
1542 struct smc911x_local *lp = netdev_priv(dev);
1543 return lp->msg_enable;
1544}
1545
1546static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1547{
1548 struct smc911x_local *lp = netdev_priv(dev);
1549 lp->msg_enable = level;
1550}
1551
1552static int smc911x_ethtool_getregslen(struct net_device *dev)
1553{
1554 /* System regs + MAC regs + PHY regs */
d5498bef
JG
1555 return (((E2P_CMD - ID_REV)/4 + 1) +
1556 (WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
0a0c72c9
DM
1557}
1558
d5498bef 1559static void smc911x_ethtool_getregs(struct net_device *dev,
0a0c72c9
DM
1560 struct ethtool_regs* regs, void *buf)
1561{
0a0c72c9
DM
1562 struct smc911x_local *lp = netdev_priv(dev);
1563 unsigned long flags;
1564 u32 reg,i,j=0;
1565 u32 *data = (u32*)buf;
1566
1567 regs->version = lp->version;
1568 for(i=ID_REV;i<=E2P_CMD;i+=4) {
699559f8 1569 data[j++] = SMC_inl(lp, i);
0a0c72c9
DM
1570 }
1571 for(i=MAC_CR;i<=WUCSR;i++) {
1572 spin_lock_irqsave(&lp->lock, flags);
699559f8 1573 SMC_GET_MAC_CSR(lp, i, reg);
0a0c72c9 1574 spin_unlock_irqrestore(&lp->lock, flags);
d5498bef 1575 data[j++] = reg;
0a0c72c9
DM
1576 }
1577 for(i=0;i<=31;i++) {
1578 spin_lock_irqsave(&lp->lock, flags);
699559f8 1579 SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
0a0c72c9 1580 spin_unlock_irqrestore(&lp->lock, flags);
d5498bef 1581 data[j++] = reg & 0xFFFF;
0a0c72c9
DM
1582 }
1583}
1584
1585static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1586{
699559f8 1587 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1588 unsigned int timeout;
1589 int e2p_cmd;
1590
699559f8 1591 e2p_cmd = SMC_GET_E2P_CMD(lp);
0a0c72c9
DM
1592 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1593 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
dcdf8710
BB
1594 PRINTK(dev, "%s timeout waiting for EEPROM to respond\n",
1595 __func__);
0a0c72c9 1596 return -EFAULT;
d5498bef 1597 }
0a0c72c9 1598 mdelay(1);
699559f8 1599 e2p_cmd = SMC_GET_E2P_CMD(lp);
0a0c72c9
DM
1600 }
1601 if (timeout == 0) {
dcdf8710
BB
1602 PRINTK(dev, "%s timeout waiting for EEPROM CMD not busy\n",
1603 __func__);
0a0c72c9
DM
1604 return -ETIMEDOUT;
1605 }
1606 return 0;
1607}
1608
d5498bef 1609static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
0a0c72c9
DM
1610 int cmd, int addr)
1611{
699559f8 1612 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1613 int ret;
1614
d5498bef 1615 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9 1616 return ret;
699559f8 1617 SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
d5498bef 1618 ((cmd) & (0x7<<28)) |
0a0c72c9
DM
1619 ((addr) & 0xFF));
1620 return 0;
1621}
1622
d5498bef 1623static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
0a0c72c9
DM
1624 u8 *data)
1625{
699559f8 1626 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1627 int ret;
1628
d5498bef 1629 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9 1630 return ret;
699559f8 1631 *data = SMC_GET_E2P_DATA(lp);
0a0c72c9
DM
1632 return 0;
1633}
1634
d5498bef 1635static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
0a0c72c9
DM
1636 u8 data)
1637{
699559f8 1638 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1639 int ret;
1640
d5498bef 1641 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
0a0c72c9 1642 return ret;
699559f8 1643 SMC_SET_E2P_DATA(lp, data);
0a0c72c9
DM
1644 return 0;
1645}
1646
d5498bef 1647static int smc911x_ethtool_geteeprom(struct net_device *dev,
0a0c72c9
DM
1648 struct ethtool_eeprom *eeprom, u8 *data)
1649{
1650 u8 eebuf[SMC911X_EEPROM_LEN];
1651 int i, ret;
1652
1653 for(i=0;i<SMC911X_EEPROM_LEN;i++) {
1654 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
1655 return ret;
1656 if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
1657 return ret;
1658 }
1659 memcpy(data, eebuf+eeprom->offset, eeprom->len);
d5498bef 1660 return 0;
0a0c72c9
DM
1661}
1662
d5498bef 1663static int smc911x_ethtool_seteeprom(struct net_device *dev,
0a0c72c9
DM
1664 struct ethtool_eeprom *eeprom, u8 *data)
1665{
1666 int i, ret;
1667
1668 /* Enable erase */
1669 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
1670 return ret;
1671 for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
1672 /* erase byte */
1673 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
1674 return ret;
1675 /* write byte */
1676 if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
1677 return ret;
1678 if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
1679 return ret;
1680 }
1681 return 0;
1682}
1683
1684static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
1685{
1686 return SMC911X_EEPROM_LEN;
1687}
1688
7282d491 1689static const struct ethtool_ops smc911x_ethtool_ops = {
0a0c72c9
DM
1690 .get_settings = smc911x_ethtool_getsettings,
1691 .set_settings = smc911x_ethtool_setsettings,
1692 .get_drvinfo = smc911x_ethtool_getdrvinfo,
1693 .get_msglevel = smc911x_ethtool_getmsglevel,
1694 .set_msglevel = smc911x_ethtool_setmsglevel,
1695 .nway_reset = smc911x_ethtool_nwayreset,
1696 .get_link = ethtool_op_get_link,
1697 .get_regs_len = smc911x_ethtool_getregslen,
1698 .get_regs = smc911x_ethtool_getregs,
1699 .get_eeprom_len = smc911x_ethtool_geteeprom_len,
1700 .get_eeprom = smc911x_ethtool_geteeprom,
1701 .set_eeprom = smc911x_ethtool_seteeprom,
1702};
1703
1704/*
1705 * smc911x_findirq
1706 *
1707 * This routine has a simple purpose -- make the SMC chip generate an
1708 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1709 */
9f1e13db 1710static int smc911x_findirq(struct net_device *dev)
0a0c72c9 1711{
699559f8 1712 struct smc911x_local *lp = netdev_priv(dev);
0a0c72c9
DM
1713 int timeout = 20;
1714 unsigned long cookie;
1715
dcdf8710 1716 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1717
1718 cookie = probe_irq_on();
1719
1720 /*
1721 * Force a SW interrupt
1722 */
1723
699559f8 1724 SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
0a0c72c9
DM
1725
1726 /*
1727 * Wait until positive that the interrupt has been generated
1728 */
1729 do {
1730 int int_status;
1731 udelay(10);
699559f8 1732 int_status = SMC_GET_INT_EN(lp);
0a0c72c9
DM
1733 if (int_status & INT_EN_SW_INT_EN_)
1734 break; /* got the interrupt */
1735 } while (--timeout);
1736
1737 /*
1738 * there is really nothing that I can do here if timeout fails,
1739 * as autoirq_report will return a 0 anyway, which is what I
1740 * want in this case. Plus, the clean up is needed in both
1741 * cases.
1742 */
1743
1744 /* and disable all interrupts again */
699559f8 1745 SMC_SET_INT_EN(lp, 0);
0a0c72c9
DM
1746
1747 /* and return what I found */
1748 return probe_irq_off(cookie);
1749}
1750
ec4e0cff
AB
1751static const struct net_device_ops smc911x_netdev_ops = {
1752 .ndo_open = smc911x_open,
1753 .ndo_stop = smc911x_close,
1754 .ndo_start_xmit = smc911x_hard_start_xmit,
1755 .ndo_tx_timeout = smc911x_timeout,
afc4b13d 1756 .ndo_set_rx_mode = smc911x_set_multicast_list,
ec4e0cff
AB
1757 .ndo_change_mtu = eth_change_mtu,
1758 .ndo_validate_addr = eth_validate_addr,
1759 .ndo_set_mac_address = eth_mac_addr,
1760#ifdef CONFIG_NET_POLL_CONTROLLER
1761 .ndo_poll_controller = smc911x_poll_controller,
1762#endif
1763};
1764
0a0c72c9
DM
1765/*
1766 * Function: smc911x_probe(unsigned long ioaddr)
1767 *
1768 * Purpose:
1769 * Tests to see if a given ioaddr points to an SMC911x chip.
1770 * Returns a 0 on success
1771 *
1772 * Algorithm:
1773 * (1) see if the endian word is OK
1774 * (1) see if I recognize the chip ID in the appropriate register
1775 *
1776 * Here I do typical initialization tasks.
1777 *
1778 * o Initialize the structure if needed
1779 * o print out my vanity message if not done so already
1780 * o print out what type of hardware is detected
1781 * o print out the ethernet address
1782 * o find the IRQ
1783 * o set up my private data
1784 * o configure the dev structure with my subroutines
1785 * o actually GRAB the irq.
1786 * o GRAB the region
1787 */
9f1e13db 1788static int smc911x_probe(struct net_device *dev)
0a0c72c9
DM
1789{
1790 struct smc911x_local *lp = netdev_priv(dev);
1791 int i, retval;
1792 unsigned int val, chip_id, revision;
1793 const char *version_string;
12c03f59 1794 unsigned long irq_flags;
0a0c72c9 1795
dcdf8710 1796 DBG(SMC_DEBUG_FUNC, dev, "--> %s\n", __func__);
0a0c72c9
DM
1797
1798 /* First, see if the endian word is recognized */
699559f8 1799 val = SMC_GET_BYTE_TEST(lp);
dcdf8710
BB
1800 DBG(SMC_DEBUG_MISC, dev, "%s: endian probe returned 0x%04x\n",
1801 CARDNAME, val);
0a0c72c9 1802 if (val != 0x87654321) {
dcdf8710 1803 netdev_err(dev, "Invalid chip endian 0x%08x\n", val);
0a0c72c9
DM
1804 retval = -ENODEV;
1805 goto err_out;
1806 }
1807
1808 /*
1809 * check if the revision register is something that I
1810 * recognize. These might need to be added to later,
1811 * as future revisions could be added.
1812 */
699559f8 1813 chip_id = SMC_GET_PN(lp);
dcdf8710
BB
1814 DBG(SMC_DEBUG_MISC, dev, "%s: id probe returned 0x%04x\n",
1815 CARDNAME, chip_id);
0a0c72c9
DM
1816 for(i=0;chip_ids[i].id != 0; i++) {
1817 if (chip_ids[i].id == chip_id) break;
1818 }
1819 if (!chip_ids[i].id) {
dcdf8710 1820 netdev_err(dev, "Unknown chip ID %04x\n", chip_id);
0a0c72c9
DM
1821 retval = -ENODEV;
1822 goto err_out;
1823 }
1824 version_string = chip_ids[i].name;
1825
699559f8 1826 revision = SMC_GET_REV(lp);
dcdf8710 1827 DBG(SMC_DEBUG_MISC, dev, "%s: revision = 0x%04x\n", CARDNAME, revision);
0a0c72c9
DM
1828
1829 /* At this point I'll assume that the chip is an SMC911x. */
dcdf8710
BB
1830 DBG(SMC_DEBUG_MISC, dev, "%s: Found a %s\n",
1831 CARDNAME, chip_ids[i].name);
0a0c72c9
DM
1832
1833 /* Validate the TX FIFO size requested */
1834 if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
dcdf8710
BB
1835 netdev_err(dev, "Invalid TX FIFO size requested %d\n",
1836 tx_fifo_kb);
0a0c72c9
DM
1837 retval = -EINVAL;
1838 goto err_out;
1839 }
d5498bef 1840
0a0c72c9 1841 /* fill in some of the fields */
0a0c72c9
DM
1842 lp->version = chip_ids[i].id;
1843 lp->revision = revision;
1844 lp->tx_fifo_kb = tx_fifo_kb;
1845 /* Reverse calculate the RX FIFO size from the TX */
1846 lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
1847 lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
1848
1849 /* Set the automatic flow control values */
1850 switch(lp->tx_fifo_kb) {
d5498bef 1851 /*
0a0c72c9
DM
1852 * AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
1853 * AFC_LO is AFC_HI/2
1854 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1855 */
1856 case 2:/* 13440 Rx Data Fifo Size */
1857 lp->afc_cfg=0x008C46AF;break;
1858 case 3:/* 12480 Rx Data Fifo Size */
1859 lp->afc_cfg=0x0082419F;break;
1860 case 4:/* 11520 Rx Data Fifo Size */
1861 lp->afc_cfg=0x00783C9F;break;
1862 case 5:/* 10560 Rx Data Fifo Size */
1863 lp->afc_cfg=0x006E374F;break;
1864 case 6:/* 9600 Rx Data Fifo Size */
1865 lp->afc_cfg=0x0064328F;break;
1866 case 7:/* 8640 Rx Data Fifo Size */
1867 lp->afc_cfg=0x005A2D7F;break;
1868 case 8:/* 7680 Rx Data Fifo Size */
1869 lp->afc_cfg=0x0050287F;break;
1870 case 9:/* 6720 Rx Data Fifo Size */
1871 lp->afc_cfg=0x0046236F;break;
1872 case 10:/* 5760 Rx Data Fifo Size */
1873 lp->afc_cfg=0x003C1E6F;break;
1874 case 11:/* 4800 Rx Data Fifo Size */
1875 lp->afc_cfg=0x0032195F;break;
d5498bef 1876 /*
0a0c72c9
DM
1877 * AFC_HI is ~1520 bytes less than RX Data Fifo Size
1878 * AFC_LO is AFC_HI/2
1879 * BACK_DUR is about 5uS*(AFC_LO) rounded down
1880 */
1881 case 12:/* 3840 Rx Data Fifo Size */
1882 lp->afc_cfg=0x0024124F;break;
1883 case 13:/* 2880 Rx Data Fifo Size */
1884 lp->afc_cfg=0x0015073F;break;
1885 case 14:/* 1920 Rx Data Fifo Size */
1886 lp->afc_cfg=0x0006032F;break;
1887 default:
dcdf8710 1888 PRINTK(dev, "ERROR -- no AFC_CFG setting found");
0a0c72c9
DM
1889 break;
1890 }
1891
dcdf8710
BB
1892 DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX, dev,
1893 "%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
1894 lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
0a0c72c9
DM
1895
1896 spin_lock_init(&lp->lock);
1897
1898 /* Get the MAC address */
699559f8 1899 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
0a0c72c9
DM
1900
1901 /* now, reset the chip, and put it into a known state */
1902 smc911x_reset(dev);
1903
1904 /*
1905 * If dev->irq is 0, then the device has to be banged on to see
1906 * what the IRQ is.
1907 *
1908 * Specifying an IRQ is done with the assumption that the user knows
1909 * what (s)he is doing. No checking is done!!!!
1910 */
1911 if (dev->irq < 1) {
1912 int trials;
1913
1914 trials = 3;
1915 while (trials--) {
699559f8 1916 dev->irq = smc911x_findirq(dev);
0a0c72c9
DM
1917 if (dev->irq)
1918 break;
1919 /* kick the card and try again */
1920 smc911x_reset(dev);
1921 }
1922 }
1923 if (dev->irq == 0) {
dcdf8710 1924 netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
0a0c72c9
DM
1925 retval = -ENODEV;
1926 goto err_out;
1927 }
1928 dev->irq = irq_canonicalize(dev->irq);
1929
ec4e0cff 1930 dev->netdev_ops = &smc911x_netdev_ops;
0a0c72c9 1931 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
0a0c72c9 1932 dev->ethtool_ops = &smc911x_ethtool_ops;
0a0c72c9 1933
ef8142a5 1934 INIT_WORK(&lp->phy_configure, smc911x_phy_configure);
0a0c72c9
DM
1935 lp->mii.phy_id_mask = 0x1f;
1936 lp->mii.reg_num_mask = 0x1f;
1937 lp->mii.force_media = 0;
1938 lp->mii.full_duplex = 0;
1939 lp->mii.dev = dev;
1940 lp->mii.mdio_read = smc911x_phy_read;
1941 lp->mii.mdio_write = smc911x_phy_write;
1942
1943 /*
1944 * Locate the phy, if any.
1945 */
1946 smc911x_phy_detect(dev);
1947
1948 /* Set default parameters */
1949 lp->msg_enable = NETIF_MSG_LINK;
1950 lp->ctl_rfduplx = 1;
1951 lp->ctl_rspeed = 100;
1952
12c03f59
MD
1953#ifdef SMC_DYNAMIC_BUS_CONFIG
1954 irq_flags = lp->cfg.irq_flags;
1955#else
1956 irq_flags = IRQF_SHARED | SMC_IRQ_SENSE;
1957#endif
1958
0a0c72c9 1959 /* Grab the IRQ */
a0607fd3 1960 retval = request_irq(dev->irq, smc911x_interrupt,
12c03f59 1961 irq_flags, dev->name, dev);
0a0c72c9
DM
1962 if (retval)
1963 goto err_out;
1964
0a0c72c9
DM
1965#ifdef SMC_USE_DMA
1966 lp->rxdma = SMC_DMA_REQUEST(dev, smc911x_rx_dma_irq);
1967 lp->txdma = SMC_DMA_REQUEST(dev, smc911x_tx_dma_irq);
1968 lp->rxdma_active = 0;
1969 lp->txdma_active = 0;
1970 dev->dma = lp->rxdma;
1971#endif
1972
1973 retval = register_netdev(dev);
1974 if (retval == 0) {
1975 /* now, print out the card info, in a short format.. */
dcdf8710
BB
1976 netdev_info(dev, "%s (rev %d) at %#lx IRQ %d",
1977 version_string, lp->revision,
1978 dev->base_addr, dev->irq);
0a0c72c9
DM
1979
1980#ifdef SMC_USE_DMA
1981 if (lp->rxdma != -1)
dcdf8710 1982 pr_cont(" RXDMA %d", lp->rxdma);
0a0c72c9
DM
1983
1984 if (lp->txdma != -1)
dcdf8710 1985 pr_cont(" TXDMA %d", lp->txdma);
0a0c72c9 1986#endif
dcdf8710 1987 pr_cont("\n");
0a0c72c9 1988 if (!is_valid_ether_addr(dev->dev_addr)) {
dcdf8710 1989 netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n");
0a0c72c9
DM
1990 } else {
1991 /* Print the Ethernet address */
dcdf8710
BB
1992 netdev_info(dev, "Ethernet addr: %pM\n",
1993 dev->dev_addr);
0a0c72c9
DM
1994 }
1995
1996 if (lp->phy_type == 0) {
dcdf8710 1997 PRINTK(dev, "No PHY found\n");
0a0c72c9 1998 } else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
dcdf8710 1999 PRINTK(dev, "LAN911x Internal PHY\n");
0a0c72c9 2000 } else {
dcdf8710 2001 PRINTK(dev, "External PHY 0x%08x\n", lp->phy_type);
0a0c72c9
DM
2002 }
2003 }
d5498bef 2004
0a0c72c9
DM
2005err_out:
2006#ifdef SMC_USE_DMA
2007 if (retval) {
2008 if (lp->rxdma != -1) {
2009 SMC_DMA_FREE(dev, lp->rxdma);
2010 }
2011 if (lp->txdma != -1) {
2012 SMC_DMA_FREE(dev, lp->txdma);
2013 }
2014 }
2015#endif
2016 return retval;
2017}
2018
2019/*
dcdf8710 2020 * smc911x_drv_probe(void)
0a0c72c9
DM
2021 *
2022 * Output:
2023 * 0 --> there is a device
2024 * anything else, error
2025 */
9f1e13db 2026static int smc911x_drv_probe(struct platform_device *pdev)
0a0c72c9
DM
2027{
2028 struct net_device *ndev;
2029 struct resource *res;
ef8142a5 2030 struct smc911x_local *lp;
6b80778d 2031 void __iomem *addr;
0a0c72c9
DM
2032 int ret;
2033
dcdf8710 2034 /* ndev is not valid yet, so avoid passing it in. */
b39d66a8 2035 DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
0a0c72c9
DM
2036 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2037 if (!res) {
2038 ret = -ENODEV;
2039 goto out;
2040 }
2041
2042 /*
2043 * Request the regions.
2044 */
2045 if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
2046 ret = -EBUSY;
2047 goto out;
2048 }
2049
2050 ndev = alloc_etherdev(sizeof(struct smc911x_local));
2051 if (!ndev) {
0a0c72c9
DM
2052 ret = -ENOMEM;
2053 goto release_1;
2054 }
0a0c72c9
DM
2055 SET_NETDEV_DEV(ndev, &pdev->dev);
2056
2057 ndev->dma = (unsigned char)-1;
2058 ndev->irq = platform_get_irq(pdev, 0);
ef8142a5
AM
2059 lp = netdev_priv(ndev);
2060 lp->netdev = ndev;
12c03f59 2061#ifdef SMC_DYNAMIC_BUS_CONFIG
a316084c 2062 {
c82e5e57 2063 struct smc911x_platdata *pd = dev_get_platdata(&pdev->dev);
a316084c
AM
2064 if (!pd) {
2065 ret = -EINVAL;
2066 goto release_both;
2067 }
2068 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
12c03f59 2069 }
12c03f59 2070#endif
0a0c72c9
DM
2071
2072 addr = ioremap(res->start, SMC911X_IO_EXTENT);
2073 if (!addr) {
2074 ret = -ENOMEM;
2075 goto release_both;
2076 }
2077
2078 platform_set_drvdata(pdev, ndev);
699559f8
MD
2079 lp->base = addr;
2080 ndev->base_addr = res->start;
2081 ret = smc911x_probe(ndev);
0a0c72c9 2082 if (ret != 0) {
0a0c72c9
DM
2083 iounmap(addr);
2084release_both:
2085 free_netdev(ndev);
2086release_1:
2087 release_mem_region(res->start, SMC911X_IO_EXTENT);
2088out:
dcdf8710 2089 pr_info("%s: not found (%d).\n", CARDNAME, ret);
0a0c72c9
DM
2090 }
2091#ifdef SMC_USE_DMA
2092 else {
0a0c72c9
DM
2093 lp->physaddr = res->start;
2094 lp->dev = &pdev->dev;
2095 }
2096#endif
2097
2098 return ret;
2099}
2100
9f1e13db 2101static int smc911x_drv_remove(struct platform_device *pdev)
0a0c72c9
DM
2102{
2103 struct net_device *ndev = platform_get_drvdata(pdev);
699559f8 2104 struct smc911x_local *lp = netdev_priv(ndev);
0a0c72c9
DM
2105 struct resource *res;
2106
dcdf8710 2107 DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
0a0c72c9
DM
2108
2109 unregister_netdev(ndev);
2110
2111 free_irq(ndev->irq, ndev);
2112
2113#ifdef SMC_USE_DMA
2114 {
0a0c72c9
DM
2115 if (lp->rxdma != -1) {
2116 SMC_DMA_FREE(dev, lp->rxdma);
2117 }
2118 if (lp->txdma != -1) {
2119 SMC_DMA_FREE(dev, lp->txdma);
2120 }
2121 }
2122#endif
699559f8 2123 iounmap(lp->base);
0a0c72c9
DM
2124 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2125 release_mem_region(res->start, SMC911X_IO_EXTENT);
2126
2127 free_netdev(ndev);
2128 return 0;
2129}
2130
2131static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2132{
2133 struct net_device *ndev = platform_get_drvdata(dev);
699559f8 2134 struct smc911x_local *lp = netdev_priv(ndev);
0a0c72c9 2135
dcdf8710 2136 DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
0a0c72c9
DM
2137 if (ndev) {
2138 if (netif_running(ndev)) {
2139 netif_device_detach(ndev);
2140 smc911x_shutdown(ndev);
2141#if POWER_DOWN
2142 /* Set D2 - Energy detect only setting */
699559f8 2143 SMC_SET_PMT_CTRL(lp, 2<<12);
0a0c72c9
DM
2144#endif
2145 }
2146 }
2147 return 0;
2148}
2149
2150static int smc911x_drv_resume(struct platform_device *dev)
2151{
2152 struct net_device *ndev = platform_get_drvdata(dev);
2153
dcdf8710 2154 DBG(SMC_DEBUG_FUNC, ndev, "--> %s\n", __func__);
0a0c72c9
DM
2155 if (ndev) {
2156 struct smc911x_local *lp = netdev_priv(ndev);
2157
2158 if (netif_running(ndev)) {
2159 smc911x_reset(ndev);
0a0c72c9 2160 if (lp->phy_type != 0)
ef8142a5 2161 smc911x_phy_configure(&lp->phy_configure);
347c8d83 2162 smc911x_enable(ndev);
0a0c72c9
DM
2163 netif_device_attach(ndev);
2164 }
2165 }
2166 return 0;
2167}
2168
2169static struct platform_driver smc911x_driver = {
2170 .probe = smc911x_drv_probe,
9f1e13db 2171 .remove = smc911x_drv_remove,
0a0c72c9
DM
2172 .suspend = smc911x_drv_suspend,
2173 .resume = smc911x_drv_resume,
2174 .driver = {
2175 .name = CARDNAME,
72abb461 2176 .owner = THIS_MODULE,
0a0c72c9
DM
2177 },
2178};
d5498bef 2179
db62f684 2180module_platform_driver(smc911x_driver);