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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * smc91x.c | |
3 | * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. | |
4 | * | |
5 | * Copyright (C) 1996 by Erik Stahlman | |
6 | * Copyright (C) 2001 Standard Microsystems Corporation | |
7 | * Developed by Simple Network Magic Corporation | |
8 | * Copyright (C) 2003 Monta Vista Software, Inc. | |
9 | * Unified SMC91x driver by Nicolas Pitre | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
23 | * |
24 | * Arguments: | |
25 | * io = for the base address | |
26 | * irq = for the IRQ | |
27 | * nowait = 0 for normal wait states, 1 eliminates additional wait states | |
28 | * | |
29 | * original author: | |
30 | * Erik Stahlman <erik@vt.edu> | |
31 | * | |
32 | * hardware multicast code: | |
33 | * Peter Cammaert <pc@denkart.be> | |
34 | * | |
35 | * contributors: | |
36 | * Daris A Nevil <dnevil@snmc.com> | |
2f82af08 | 37 | * Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
38 | * Russell King <rmk@arm.linux.org.uk> |
39 | * | |
40 | * History: | |
41 | * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet | |
42 | * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" | |
43 | * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 | |
44 | * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 | |
45 | * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 | |
46 | * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support | |
47 | * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, | |
48 | * more bus abstraction, big cleanup, etc. | |
49 | * 29/09/03 Russell King - add driver model support | |
50 | * - ethtool support | |
51 | * - convert to use generic MII interface | |
52 | * - add link up/down notification | |
53 | * - don't try to handle full negotiation in | |
54 | * smc_phy_configure | |
55 | * - clean up (and fix stack overrun) in PHY | |
56 | * MII read/write functions | |
57 | * 22/09/04 Nicolas Pitre big update (see commit log for details) | |
58 | */ | |
59 | static const char version[] = | |
6389aa45 | 60 | "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>"; |
1da177e4 LT |
61 | |
62 | /* Debugging level */ | |
63 | #ifndef SMC_DEBUG | |
64 | #define SMC_DEBUG 0 | |
65 | #endif | |
66 | ||
67 | ||
1da177e4 LT |
68 | #include <linux/module.h> |
69 | #include <linux/kernel.h> | |
70 | #include <linux/sched.h> | |
1da177e4 LT |
71 | #include <linux/delay.h> |
72 | #include <linux/interrupt.h> | |
476c32c4 | 73 | #include <linux/irq.h> |
1da177e4 LT |
74 | #include <linux/errno.h> |
75 | #include <linux/ioport.h> | |
76 | #include <linux/crc32.h> | |
d052d1be | 77 | #include <linux/platform_device.h> |
1da177e4 LT |
78 | #include <linux/spinlock.h> |
79 | #include <linux/ethtool.h> | |
80 | #include <linux/mii.h> | |
81 | #include <linux/workqueue.h> | |
682a1694 | 82 | #include <linux/of.h> |
3f823c15 | 83 | #include <linux/of_device.h> |
7d2911c4 | 84 | #include <linux/of_gpio.h> |
1da177e4 LT |
85 | |
86 | #include <linux/netdevice.h> | |
87 | #include <linux/etherdevice.h> | |
88 | #include <linux/skbuff.h> | |
89 | ||
90 | #include <asm/io.h> | |
1da177e4 LT |
91 | |
92 | #include "smc91x.h" | |
93 | ||
1da177e4 LT |
94 | #ifndef SMC_NOWAIT |
95 | # define SMC_NOWAIT 0 | |
96 | #endif | |
97 | static int nowait = SMC_NOWAIT; | |
98 | module_param(nowait, int, 0400); | |
99 | MODULE_PARM_DESC(nowait, "set to 1 for no wait state"); | |
100 | ||
101 | /* | |
102 | * Transmit timeout, default 5 seconds. | |
103 | */ | |
ea937560 | 104 | static int watchdog = 1000; |
1da177e4 LT |
105 | module_param(watchdog, int, 0400); |
106 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
107 | ||
108 | MODULE_LICENSE("GPL"); | |
72abb461 | 109 | MODULE_ALIAS("platform:smc91x"); |
1da177e4 LT |
110 | |
111 | /* | |
112 | * The internal workings of the driver. If you are changing anything | |
113 | * here with the SMC stuff, you should have the datasheet and know | |
114 | * what you are doing. | |
115 | */ | |
116 | #define CARDNAME "smc91x" | |
117 | ||
118 | /* | |
119 | * Use power-down feature of the chip | |
120 | */ | |
121 | #define POWER_DOWN 1 | |
122 | ||
123 | /* | |
124 | * Wait time for memory to be free. This probably shouldn't be | |
125 | * tuned that much, as waiting for this means nothing else happens | |
126 | * in the system | |
127 | */ | |
128 | #define MEMORY_WAIT_TIME 16 | |
129 | ||
5d0571d9 NP |
130 | /* |
131 | * The maximum number of processing loops allowed for each call to the | |
6aa20a22 | 132 | * IRQ handler. |
5d0571d9 NP |
133 | */ |
134 | #define MAX_IRQ_LOOPS 8 | |
135 | ||
1da177e4 LT |
136 | /* |
137 | * This selects whether TX packets are sent one by one to the SMC91x internal | |
138 | * memory and throttled until transmission completes. This may prevent | |
139 | * RX overruns a litle by keeping much of the memory free for RX packets | |
140 | * but to the expense of reduced TX throughput and increased IRQ overhead. | |
141 | * Note this is not a cure for a too slow data bus or too high IRQ latency. | |
142 | */ | |
143 | #define THROTTLE_TX_PKTS 0 | |
144 | ||
145 | /* | |
146 | * The MII clock high/low times. 2x this number gives the MII clock period | |
147 | * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!) | |
148 | */ | |
149 | #define MII_DELAY 1 | |
150 | ||
a450a685 ZSL |
151 | #define DBG(n, dev, fmt, ...) \ |
152 | do { \ | |
153 | if (SMC_DEBUG >= (n)) \ | |
154 | netdev_dbg(dev, fmt, ##__VA_ARGS__); \ | |
1da177e4 LT |
155 | } while (0) |
156 | ||
a450a685 ZSL |
157 | #define PRINTK(dev, fmt, ...) \ |
158 | do { \ | |
159 | if (SMC_DEBUG > 0) \ | |
160 | netdev_info(dev, fmt, ##__VA_ARGS__); \ | |
161 | else \ | |
162 | netdev_dbg(dev, fmt, ##__VA_ARGS__); \ | |
163 | } while (0) | |
1da177e4 LT |
164 | |
165 | #if SMC_DEBUG > 3 | |
166 | static void PRINT_PKT(u_char *buf, int length) | |
167 | { | |
168 | int i; | |
169 | int remainder; | |
170 | int lines; | |
171 | ||
172 | lines = length / 16; | |
173 | remainder = length % 16; | |
174 | ||
175 | for (i = 0; i < lines ; i ++) { | |
176 | int cur; | |
6389aa45 | 177 | printk(KERN_DEBUG); |
1da177e4 LT |
178 | for (cur = 0; cur < 8; cur++) { |
179 | u_char a, b; | |
180 | a = *buf++; | |
181 | b = *buf++; | |
6389aa45 | 182 | pr_cont("%02x%02x ", a, b); |
1da177e4 | 183 | } |
6389aa45 | 184 | pr_cont("\n"); |
1da177e4 | 185 | } |
6389aa45 | 186 | printk(KERN_DEBUG); |
1da177e4 LT |
187 | for (i = 0; i < remainder/2 ; i++) { |
188 | u_char a, b; | |
189 | a = *buf++; | |
190 | b = *buf++; | |
6389aa45 | 191 | pr_cont("%02x%02x ", a, b); |
1da177e4 | 192 | } |
6389aa45 | 193 | pr_cont("\n"); |
1da177e4 LT |
194 | } |
195 | #else | |
a450a685 | 196 | static inline void PRINT_PKT(u_char *buf, int length) { } |
1da177e4 LT |
197 | #endif |
198 | ||
199 | ||
200 | /* this enables an interrupt in the interrupt mask register */ | |
cfdfa865 | 201 | #define SMC_ENABLE_INT(lp, x) do { \ |
1da177e4 | 202 | unsigned char mask; \ |
8ff499e4 DD |
203 | unsigned long smc_enable_flags; \ |
204 | spin_lock_irqsave(&lp->lock, smc_enable_flags); \ | |
cfdfa865 | 205 | mask = SMC_GET_INT_MASK(lp); \ |
1da177e4 | 206 | mask |= (x); \ |
cfdfa865 | 207 | SMC_SET_INT_MASK(lp, mask); \ |
8ff499e4 | 208 | spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \ |
1da177e4 LT |
209 | } while (0) |
210 | ||
211 | /* this disables an interrupt from the interrupt mask register */ | |
cfdfa865 | 212 | #define SMC_DISABLE_INT(lp, x) do { \ |
1da177e4 | 213 | unsigned char mask; \ |
8ff499e4 DD |
214 | unsigned long smc_disable_flags; \ |
215 | spin_lock_irqsave(&lp->lock, smc_disable_flags); \ | |
cfdfa865 | 216 | mask = SMC_GET_INT_MASK(lp); \ |
1da177e4 | 217 | mask &= ~(x); \ |
cfdfa865 | 218 | SMC_SET_INT_MASK(lp, mask); \ |
8ff499e4 | 219 | spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \ |
1da177e4 LT |
220 | } while (0) |
221 | ||
222 | /* | |
223 | * Wait while MMU is busy. This is usually in the order of a few nanosecs | |
224 | * if at all, but let's avoid deadlocking the system if the hardware | |
225 | * decides to go south. | |
226 | */ | |
cfdfa865 MD |
227 | #define SMC_WAIT_MMU_BUSY(lp) do { \ |
228 | if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ | |
1da177e4 | 229 | unsigned long timeout = jiffies + 2; \ |
cfdfa865 | 230 | while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ |
1da177e4 | 231 | if (time_after(jiffies, timeout)) { \ |
6389aa45 BB |
232 | netdev_dbg(dev, "timeout %s line %d\n", \ |
233 | __FILE__, __LINE__); \ | |
1da177e4 LT |
234 | break; \ |
235 | } \ | |
236 | cpu_relax(); \ | |
237 | } \ | |
238 | } \ | |
239 | } while (0) | |
240 | ||
241 | ||
242 | /* | |
243 | * this does a soft reset on the device | |
244 | */ | |
245 | static void smc_reset(struct net_device *dev) | |
246 | { | |
247 | struct smc_local *lp = netdev_priv(dev); | |
248 | void __iomem *ioaddr = lp->base; | |
249 | unsigned int ctl, cfg; | |
be83668a | 250 | struct sk_buff *pending_skb; |
1da177e4 | 251 | |
6389aa45 | 252 | DBG(2, dev, "%s\n", __func__); |
1da177e4 | 253 | |
be83668a | 254 | /* Disable all interrupts, block TX tasklet */ |
76cb4fe7 | 255 | spin_lock_irq(&lp->lock); |
cfdfa865 MD |
256 | SMC_SELECT_BANK(lp, 2); |
257 | SMC_SET_INT_MASK(lp, 0); | |
be83668a NP |
258 | pending_skb = lp->pending_tx_skb; |
259 | lp->pending_tx_skb = NULL; | |
76cb4fe7 | 260 | spin_unlock_irq(&lp->lock); |
1da177e4 | 261 | |
be83668a NP |
262 | /* free any pending tx skb */ |
263 | if (pending_skb) { | |
264 | dev_kfree_skb(pending_skb); | |
09f75cd7 JG |
265 | dev->stats.tx_errors++; |
266 | dev->stats.tx_aborted_errors++; | |
be83668a NP |
267 | } |
268 | ||
1da177e4 LT |
269 | /* |
270 | * This resets the registers mostly to defaults, but doesn't | |
271 | * affect EEPROM. That seems unnecessary | |
272 | */ | |
cfdfa865 MD |
273 | SMC_SELECT_BANK(lp, 0); |
274 | SMC_SET_RCR(lp, RCR_SOFTRST); | |
1da177e4 LT |
275 | |
276 | /* | |
277 | * Setup the Configuration Register | |
278 | * This is necessary because the CONFIG_REG is not affected | |
279 | * by a soft reset | |
280 | */ | |
cfdfa865 | 281 | SMC_SELECT_BANK(lp, 1); |
1da177e4 LT |
282 | |
283 | cfg = CONFIG_DEFAULT; | |
284 | ||
285 | /* | |
286 | * Setup for fast accesses if requested. If the card/system | |
287 | * can't handle it then there will be no recovery except for | |
288 | * a hard reset or power cycle | |
289 | */ | |
c4f0e767 | 290 | if (lp->cfg.flags & SMC91X_NOWAIT) |
1da177e4 LT |
291 | cfg |= CONFIG_NO_WAIT; |
292 | ||
293 | /* | |
294 | * Release from possible power-down state | |
295 | * Configuration register is not affected by Soft Reset | |
296 | */ | |
297 | cfg |= CONFIG_EPH_POWER_EN; | |
298 | ||
cfdfa865 | 299 | SMC_SET_CONFIG(lp, cfg); |
1da177e4 LT |
300 | |
301 | /* this should pause enough for the chip to be happy */ | |
302 | /* | |
303 | * elaborate? What does the chip _need_? --jgarzik | |
304 | * | |
305 | * This seems to be undocumented, but something the original | |
306 | * driver(s) have always done. Suspect undocumented timing | |
307 | * info/determined empirically. --rmk | |
308 | */ | |
309 | udelay(1); | |
310 | ||
311 | /* Disable transmit and receive functionality */ | |
cfdfa865 MD |
312 | SMC_SELECT_BANK(lp, 0); |
313 | SMC_SET_RCR(lp, RCR_CLEAR); | |
314 | SMC_SET_TCR(lp, TCR_CLEAR); | |
1da177e4 | 315 | |
cfdfa865 MD |
316 | SMC_SELECT_BANK(lp, 1); |
317 | ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE; | |
1da177e4 LT |
318 | |
319 | /* | |
320 | * Set the control register to automatically release successfully | |
321 | * transmitted packets, to make the best use out of our limited | |
322 | * memory | |
323 | */ | |
324 | if(!THROTTLE_TX_PKTS) | |
325 | ctl |= CTL_AUTO_RELEASE; | |
326 | else | |
327 | ctl &= ~CTL_AUTO_RELEASE; | |
cfdfa865 | 328 | SMC_SET_CTL(lp, ctl); |
1da177e4 LT |
329 | |
330 | /* Reset the MMU */ | |
cfdfa865 MD |
331 | SMC_SELECT_BANK(lp, 2); |
332 | SMC_SET_MMU_CMD(lp, MC_RESET); | |
333 | SMC_WAIT_MMU_BUSY(lp); | |
1da177e4 LT |
334 | } |
335 | ||
336 | /* | |
337 | * Enable Interrupts, Receive, and Transmit | |
338 | */ | |
339 | static void smc_enable(struct net_device *dev) | |
340 | { | |
341 | struct smc_local *lp = netdev_priv(dev); | |
342 | void __iomem *ioaddr = lp->base; | |
343 | int mask; | |
344 | ||
6389aa45 | 345 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
346 | |
347 | /* see the header file for options in TCR/RCR DEFAULT */ | |
cfdfa865 MD |
348 | SMC_SELECT_BANK(lp, 0); |
349 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
350 | SMC_SET_RCR(lp, lp->rcr_cur_mode); | |
1da177e4 | 351 | |
cfdfa865 MD |
352 | SMC_SELECT_BANK(lp, 1); |
353 | SMC_SET_MAC_ADDR(lp, dev->dev_addr); | |
1da177e4 LT |
354 | |
355 | /* now, enable interrupts */ | |
356 | mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; | |
357 | if (lp->version >= (CHIP_91100 << 4)) | |
358 | mask |= IM_MDINT; | |
cfdfa865 MD |
359 | SMC_SELECT_BANK(lp, 2); |
360 | SMC_SET_INT_MASK(lp, mask); | |
1da177e4 LT |
361 | |
362 | /* | |
363 | * From this point the register bank must _NOT_ be switched away | |
364 | * to something else than bank 2 without proper locking against | |
365 | * races with any tasklet or interrupt handlers until smc_shutdown() | |
366 | * or smc_reset() is called. | |
367 | */ | |
368 | } | |
369 | ||
370 | /* | |
371 | * this puts the device in an inactive state | |
372 | */ | |
373 | static void smc_shutdown(struct net_device *dev) | |
374 | { | |
375 | struct smc_local *lp = netdev_priv(dev); | |
376 | void __iomem *ioaddr = lp->base; | |
be83668a | 377 | struct sk_buff *pending_skb; |
1da177e4 | 378 | |
6389aa45 | 379 | DBG(2, dev, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
380 | |
381 | /* no more interrupts for me */ | |
76cb4fe7 | 382 | spin_lock_irq(&lp->lock); |
cfdfa865 MD |
383 | SMC_SELECT_BANK(lp, 2); |
384 | SMC_SET_INT_MASK(lp, 0); | |
be83668a NP |
385 | pending_skb = lp->pending_tx_skb; |
386 | lp->pending_tx_skb = NULL; | |
76cb4fe7 | 387 | spin_unlock_irq(&lp->lock); |
be83668a NP |
388 | if (pending_skb) |
389 | dev_kfree_skb(pending_skb); | |
1da177e4 LT |
390 | |
391 | /* and tell the card to stay away from that nasty outside world */ | |
cfdfa865 MD |
392 | SMC_SELECT_BANK(lp, 0); |
393 | SMC_SET_RCR(lp, RCR_CLEAR); | |
394 | SMC_SET_TCR(lp, TCR_CLEAR); | |
1da177e4 LT |
395 | |
396 | #ifdef POWER_DOWN | |
397 | /* finally, shut the chip down */ | |
cfdfa865 MD |
398 | SMC_SELECT_BANK(lp, 1); |
399 | SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); | |
1da177e4 LT |
400 | #endif |
401 | } | |
402 | ||
403 | /* | |
404 | * This is the procedure to handle the receipt of a packet. | |
405 | */ | |
406 | static inline void smc_rcv(struct net_device *dev) | |
407 | { | |
408 | struct smc_local *lp = netdev_priv(dev); | |
409 | void __iomem *ioaddr = lp->base; | |
410 | unsigned int packet_number, status, packet_len; | |
411 | ||
6389aa45 | 412 | DBG(3, dev, "%s\n", __func__); |
1da177e4 | 413 | |
cfdfa865 | 414 | packet_number = SMC_GET_RXFIFO(lp); |
1da177e4 | 415 | if (unlikely(packet_number & RXFIFO_REMPTY)) { |
6389aa45 | 416 | PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); |
1da177e4 LT |
417 | return; |
418 | } | |
419 | ||
420 | /* read from start of packet */ | |
cfdfa865 | 421 | SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC); |
1da177e4 LT |
422 | |
423 | /* First two words are status and packet length */ | |
cfdfa865 | 424 | SMC_GET_PKT_HDR(lp, status, packet_len); |
1da177e4 | 425 | packet_len &= 0x07ff; /* mask off top bits */ |
6389aa45 BB |
426 | DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", |
427 | packet_number, status, packet_len, packet_len); | |
1da177e4 LT |
428 | |
429 | back: | |
430 | if (unlikely(packet_len < 6 || status & RS_ERRORS)) { | |
431 | if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { | |
432 | /* accept VLAN packets */ | |
433 | status &= ~RS_TOOLONG; | |
434 | goto back; | |
435 | } | |
436 | if (packet_len < 6) { | |
437 | /* bloody hardware */ | |
6389aa45 BB |
438 | netdev_err(dev, "fubar (rxlen %u status %x\n", |
439 | packet_len, status); | |
1da177e4 LT |
440 | status |= RS_TOOSHORT; |
441 | } | |
cfdfa865 MD |
442 | SMC_WAIT_MMU_BUSY(lp); |
443 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
09f75cd7 | 444 | dev->stats.rx_errors++; |
1da177e4 | 445 | if (status & RS_ALGNERR) |
09f75cd7 | 446 | dev->stats.rx_frame_errors++; |
1da177e4 | 447 | if (status & (RS_TOOSHORT | RS_TOOLONG)) |
09f75cd7 | 448 | dev->stats.rx_length_errors++; |
1da177e4 | 449 | if (status & RS_BADCRC) |
09f75cd7 | 450 | dev->stats.rx_crc_errors++; |
1da177e4 LT |
451 | } else { |
452 | struct sk_buff *skb; | |
453 | unsigned char *data; | |
454 | unsigned int data_len; | |
455 | ||
456 | /* set multicast stats */ | |
457 | if (status & RS_MULTICAST) | |
09f75cd7 | 458 | dev->stats.multicast++; |
1da177e4 LT |
459 | |
460 | /* | |
461 | * Actual payload is packet_len - 6 (or 5 if odd byte). | |
462 | * We want skb_reserve(2) and the final ctrl word | |
463 | * (2 bytes, possibly containing the payload odd byte). | |
464 | * Furthermore, we add 2 bytes to allow rounding up to | |
465 | * multiple of 4 bytes on 32 bit buses. | |
466 | * Hence packet_len - 6 + 2 + 2 + 2. | |
467 | */ | |
dae2e9f4 | 468 | skb = netdev_alloc_skb(dev, packet_len); |
1da177e4 | 469 | if (unlikely(skb == NULL)) { |
cfdfa865 MD |
470 | SMC_WAIT_MMU_BUSY(lp); |
471 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
09f75cd7 | 472 | dev->stats.rx_dropped++; |
1da177e4 LT |
473 | return; |
474 | } | |
475 | ||
476 | /* Align IP header to 32 bits */ | |
477 | skb_reserve(skb, 2); | |
478 | ||
479 | /* BUG: the LAN91C111 rev A never sets this bit. Force it. */ | |
480 | if (lp->version == 0x90) | |
481 | status |= RS_ODDFRAME; | |
482 | ||
483 | /* | |
484 | * If odd length: packet_len - 5, | |
485 | * otherwise packet_len - 6. | |
486 | * With the trailing ctrl byte it's packet_len - 4. | |
487 | */ | |
488 | data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); | |
489 | data = skb_put(skb, data_len); | |
cfdfa865 | 490 | SMC_PULL_DATA(lp, data, packet_len - 4); |
1da177e4 | 491 | |
cfdfa865 MD |
492 | SMC_WAIT_MMU_BUSY(lp); |
493 | SMC_SET_MMU_CMD(lp, MC_RELEASE); | |
1da177e4 LT |
494 | |
495 | PRINT_PKT(data, packet_len - 4); | |
496 | ||
1da177e4 LT |
497 | skb->protocol = eth_type_trans(skb, dev); |
498 | netif_rx(skb); | |
09f75cd7 JG |
499 | dev->stats.rx_packets++; |
500 | dev->stats.rx_bytes += data_len; | |
1da177e4 LT |
501 | } |
502 | } | |
503 | ||
504 | #ifdef CONFIG_SMP | |
505 | /* | |
506 | * On SMP we have the following problem: | |
507 | * | |
508 | * A = smc_hardware_send_pkt() | |
509 | * B = smc_hard_start_xmit() | |
510 | * C = smc_interrupt() | |
511 | * | |
512 | * A and B can never be executed simultaneously. However, at least on UP, | |
513 | * it is possible (and even desirable) for C to interrupt execution of | |
514 | * A or B in order to have better RX reliability and avoid overruns. | |
515 | * C, just like A and B, must have exclusive access to the chip and | |
516 | * each of them must lock against any other concurrent access. | |
517 | * Unfortunately this is not possible to have C suspend execution of A or | |
518 | * B taking place on another CPU. On UP this is no an issue since A and B | |
519 | * are run from softirq context and C from hard IRQ context, and there is | |
520 | * no other CPU where concurrent access can happen. | |
521 | * If ever there is a way to force at least B and C to always be executed | |
522 | * on the same CPU then we could use read/write locks to protect against | |
523 | * any other concurrent access and C would always interrupt B. But life | |
524 | * isn't that easy in a SMP world... | |
525 | */ | |
8ff499e4 | 526 | #define smc_special_trylock(lock, flags) \ |
1da177e4 LT |
527 | ({ \ |
528 | int __ret; \ | |
8ff499e4 | 529 | local_irq_save(flags); \ |
1da177e4 LT |
530 | __ret = spin_trylock(lock); \ |
531 | if (!__ret) \ | |
8ff499e4 | 532 | local_irq_restore(flags); \ |
1da177e4 LT |
533 | __ret; \ |
534 | }) | |
0b4f2928 | 535 | #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) |
8ff499e4 | 536 | #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) |
1da177e4 | 537 | #else |
fd0775bf MF |
538 | #define smc_special_trylock(lock, flags) (flags == flags) |
539 | #define smc_special_lock(lock, flags) do { flags = 0; } while (0) | |
540 | #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) | |
1da177e4 LT |
541 | #endif |
542 | ||
543 | /* | |
544 | * This is called to actually send a packet to the chip. | |
545 | */ | |
546 | static void smc_hardware_send_pkt(unsigned long data) | |
547 | { | |
548 | struct net_device *dev = (struct net_device *)data; | |
549 | struct smc_local *lp = netdev_priv(dev); | |
550 | void __iomem *ioaddr = lp->base; | |
551 | struct sk_buff *skb; | |
552 | unsigned int packet_no, len; | |
553 | unsigned char *buf; | |
8ff499e4 | 554 | unsigned long flags; |
1da177e4 | 555 | |
6389aa45 | 556 | DBG(3, dev, "%s\n", __func__); |
1da177e4 | 557 | |
8ff499e4 | 558 | if (!smc_special_trylock(&lp->lock, flags)) { |
1da177e4 LT |
559 | netif_stop_queue(dev); |
560 | tasklet_schedule(&lp->tx_task); | |
561 | return; | |
562 | } | |
563 | ||
564 | skb = lp->pending_tx_skb; | |
be83668a | 565 | if (unlikely(!skb)) { |
8ff499e4 | 566 | smc_special_unlock(&lp->lock, flags); |
be83668a NP |
567 | return; |
568 | } | |
1da177e4 | 569 | lp->pending_tx_skb = NULL; |
be83668a | 570 | |
cfdfa865 | 571 | packet_no = SMC_GET_AR(lp); |
1da177e4 | 572 | if (unlikely(packet_no & AR_FAILED)) { |
6389aa45 | 573 | netdev_err(dev, "Memory allocation failed.\n"); |
09f75cd7 JG |
574 | dev->stats.tx_errors++; |
575 | dev->stats.tx_fifo_errors++; | |
8ff499e4 | 576 | smc_special_unlock(&lp->lock, flags); |
1da177e4 LT |
577 | goto done; |
578 | } | |
579 | ||
580 | /* point to the beginning of the packet */ | |
cfdfa865 MD |
581 | SMC_SET_PN(lp, packet_no); |
582 | SMC_SET_PTR(lp, PTR_AUTOINC); | |
1da177e4 LT |
583 | |
584 | buf = skb->data; | |
585 | len = skb->len; | |
6389aa45 BB |
586 | DBG(2, dev, "TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n", |
587 | packet_no, len, len, buf); | |
1da177e4 LT |
588 | PRINT_PKT(buf, len); |
589 | ||
590 | /* | |
591 | * Send the packet length (+6 for status words, length, and ctl. | |
592 | * The card will pad to 64 bytes with zeroes if packet is too small. | |
593 | */ | |
cfdfa865 | 594 | SMC_PUT_PKT_HDR(lp, 0, len + 6); |
1da177e4 LT |
595 | |
596 | /* send the actual data */ | |
cfdfa865 | 597 | SMC_PUSH_DATA(lp, buf, len & ~1); |
1da177e4 LT |
598 | |
599 | /* Send final ctl word with the last byte if there is one */ | |
cfdfa865 | 600 | SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp)); |
1da177e4 LT |
601 | |
602 | /* | |
ea937560 NP |
603 | * If THROTTLE_TX_PKTS is set, we stop the queue here. This will |
604 | * have the effect of having at most one packet queued for TX | |
605 | * in the chip's memory at all time. | |
606 | * | |
607 | * If THROTTLE_TX_PKTS is not set then the queue is stopped only | |
608 | * when memory allocation (MC_ALLOC) does not succeed right away. | |
1da177e4 | 609 | */ |
ea937560 | 610 | if (THROTTLE_TX_PKTS) |
1da177e4 LT |
611 | netif_stop_queue(dev); |
612 | ||
613 | /* queue the packet for TX */ | |
cfdfa865 | 614 | SMC_SET_MMU_CMD(lp, MC_ENQUEUE); |
8ff499e4 | 615 | smc_special_unlock(&lp->lock, flags); |
1da177e4 LT |
616 | |
617 | dev->trans_start = jiffies; | |
09f75cd7 JG |
618 | dev->stats.tx_packets++; |
619 | dev->stats.tx_bytes += len; | |
1da177e4 | 620 | |
cfdfa865 | 621 | SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT); |
1da177e4 LT |
622 | |
623 | done: if (!THROTTLE_TX_PKTS) | |
624 | netif_wake_queue(dev); | |
625 | ||
4b61fe26 | 626 | dev_consume_skb_any(skb); |
1da177e4 LT |
627 | } |
628 | ||
629 | /* | |
630 | * Since I am not sure if I will have enough room in the chip's ram | |
631 | * to store the packet, I call this routine which either sends it | |
632 | * now, or set the card to generates an interrupt when ready | |
633 | * for the packet. | |
634 | */ | |
635 | static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
636 | { | |
637 | struct smc_local *lp = netdev_priv(dev); | |
638 | void __iomem *ioaddr = lp->base; | |
639 | unsigned int numPages, poll_count, status; | |
8ff499e4 | 640 | unsigned long flags; |
1da177e4 | 641 | |
6389aa45 | 642 | DBG(3, dev, "%s\n", __func__); |
1da177e4 LT |
643 | |
644 | BUG_ON(lp->pending_tx_skb != NULL); | |
1da177e4 LT |
645 | |
646 | /* | |
647 | * The MMU wants the number of pages to be the number of 256 bytes | |
648 | * 'pages', minus 1 (since a packet can't ever have 0 pages :)) | |
649 | * | |
650 | * The 91C111 ignores the size bits, but earlier models don't. | |
651 | * | |
652 | * Pkt size for allocating is data length +6 (for additional status | |
653 | * words, length and ctl) | |
654 | * | |
655 | * If odd size then last byte is included in ctl word. | |
656 | */ | |
657 | numPages = ((skb->len & ~1) + (6 - 1)) >> 8; | |
658 | if (unlikely(numPages > 7)) { | |
6389aa45 | 659 | netdev_warn(dev, "Far too big packet error.\n"); |
09f75cd7 JG |
660 | dev->stats.tx_errors++; |
661 | dev->stats.tx_dropped++; | |
4b61fe26 | 662 | dev_kfree_skb_any(skb); |
6ed10654 | 663 | return NETDEV_TX_OK; |
1da177e4 LT |
664 | } |
665 | ||
8ff499e4 | 666 | smc_special_lock(&lp->lock, flags); |
1da177e4 LT |
667 | |
668 | /* now, try to allocate the memory */ | |
cfdfa865 | 669 | SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages); |
1da177e4 LT |
670 | |
671 | /* | |
672 | * Poll the chip for a short amount of time in case the | |
673 | * allocation succeeds quickly. | |
674 | */ | |
675 | poll_count = MEMORY_WAIT_TIME; | |
676 | do { | |
cfdfa865 | 677 | status = SMC_GET_INT(lp); |
1da177e4 | 678 | if (status & IM_ALLOC_INT) { |
cfdfa865 | 679 | SMC_ACK_INT(lp, IM_ALLOC_INT); |
1da177e4 LT |
680 | break; |
681 | } | |
682 | } while (--poll_count); | |
683 | ||
8ff499e4 | 684 | smc_special_unlock(&lp->lock, flags); |
1da177e4 | 685 | |
be83668a | 686 | lp->pending_tx_skb = skb; |
1da177e4 LT |
687 | if (!poll_count) { |
688 | /* oh well, wait until the chip finds memory later */ | |
689 | netif_stop_queue(dev); | |
6389aa45 | 690 | DBG(2, dev, "TX memory allocation deferred.\n"); |
cfdfa865 | 691 | SMC_ENABLE_INT(lp, IM_ALLOC_INT); |
1da177e4 LT |
692 | } else { |
693 | /* | |
694 | * Allocation succeeded: push packet to the chip's own memory | |
695 | * immediately. | |
6aa20a22 | 696 | */ |
1da177e4 LT |
697 | smc_hardware_send_pkt((unsigned long)dev); |
698 | } | |
699 | ||
6ed10654 | 700 | return NETDEV_TX_OK; |
1da177e4 LT |
701 | } |
702 | ||
703 | /* | |
704 | * This handles a TX interrupt, which is only called when: | |
705 | * - a TX error occurred, or | |
706 | * - CTL_AUTO_RELEASE is not set and TX of a packet completed. | |
707 | */ | |
708 | static void smc_tx(struct net_device *dev) | |
709 | { | |
710 | struct smc_local *lp = netdev_priv(dev); | |
711 | void __iomem *ioaddr = lp->base; | |
712 | unsigned int saved_packet, packet_no, tx_status, pkt_len; | |
713 | ||
6389aa45 | 714 | DBG(3, dev, "%s\n", __func__); |
1da177e4 LT |
715 | |
716 | /* If the TX FIFO is empty then nothing to do */ | |
cfdfa865 | 717 | packet_no = SMC_GET_TXFIFO(lp); |
1da177e4 | 718 | if (unlikely(packet_no & TXFIFO_TEMPTY)) { |
6389aa45 | 719 | PRINTK(dev, "smc_tx with nothing on FIFO.\n"); |
1da177e4 LT |
720 | return; |
721 | } | |
722 | ||
723 | /* select packet to read from */ | |
cfdfa865 MD |
724 | saved_packet = SMC_GET_PN(lp); |
725 | SMC_SET_PN(lp, packet_no); | |
1da177e4 LT |
726 | |
727 | /* read the first word (status word) from this packet */ | |
cfdfa865 MD |
728 | SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ); |
729 | SMC_GET_PKT_HDR(lp, tx_status, pkt_len); | |
6389aa45 BB |
730 | DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n", |
731 | tx_status, packet_no); | |
1da177e4 | 732 | |
8de90115 | 733 | if (!(tx_status & ES_TX_SUC)) |
09f75cd7 | 734 | dev->stats.tx_errors++; |
8de90115 NP |
735 | |
736 | if (tx_status & ES_LOSTCARR) | |
09f75cd7 | 737 | dev->stats.tx_carrier_errors++; |
1da177e4 | 738 | |
8de90115 | 739 | if (tx_status & (ES_LATCOL | ES_16COL)) { |
6389aa45 | 740 | PRINTK(dev, "%s occurred on last xmit\n", |
8de90115 NP |
741 | (tx_status & ES_LATCOL) ? |
742 | "late collision" : "too many collisions"); | |
09f75cd7 JG |
743 | dev->stats.tx_window_errors++; |
744 | if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) { | |
6389aa45 | 745 | netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n"); |
1da177e4 LT |
746 | } |
747 | } | |
748 | ||
749 | /* kill the packet */ | |
cfdfa865 MD |
750 | SMC_WAIT_MMU_BUSY(lp); |
751 | SMC_SET_MMU_CMD(lp, MC_FREEPKT); | |
1da177e4 LT |
752 | |
753 | /* Don't restore Packet Number Reg until busy bit is cleared */ | |
cfdfa865 MD |
754 | SMC_WAIT_MMU_BUSY(lp); |
755 | SMC_SET_PN(lp, saved_packet); | |
1da177e4 LT |
756 | |
757 | /* re-enable transmit */ | |
cfdfa865 MD |
758 | SMC_SELECT_BANK(lp, 0); |
759 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
760 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
761 | } |
762 | ||
763 | ||
764 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
765 | ||
766 | static void smc_mii_out(struct net_device *dev, unsigned int val, int bits) | |
767 | { | |
768 | struct smc_local *lp = netdev_priv(dev); | |
769 | void __iomem *ioaddr = lp->base; | |
770 | unsigned int mii_reg, mask; | |
771 | ||
cfdfa865 | 772 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
1da177e4 LT |
773 | mii_reg |= MII_MDOE; |
774 | ||
775 | for (mask = 1 << (bits - 1); mask; mask >>= 1) { | |
776 | if (val & mask) | |
777 | mii_reg |= MII_MDO; | |
778 | else | |
779 | mii_reg &= ~MII_MDO; | |
780 | ||
cfdfa865 | 781 | SMC_SET_MII(lp, mii_reg); |
1da177e4 | 782 | udelay(MII_DELAY); |
cfdfa865 | 783 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
1da177e4 LT |
784 | udelay(MII_DELAY); |
785 | } | |
786 | } | |
787 | ||
788 | static unsigned int smc_mii_in(struct net_device *dev, int bits) | |
789 | { | |
790 | struct smc_local *lp = netdev_priv(dev); | |
791 | void __iomem *ioaddr = lp->base; | |
792 | unsigned int mii_reg, mask, val; | |
793 | ||
cfdfa865 MD |
794 | mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO); |
795 | SMC_SET_MII(lp, mii_reg); | |
1da177e4 LT |
796 | |
797 | for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { | |
cfdfa865 | 798 | if (SMC_GET_MII(lp) & MII_MDI) |
1da177e4 LT |
799 | val |= mask; |
800 | ||
cfdfa865 | 801 | SMC_SET_MII(lp, mii_reg); |
1da177e4 | 802 | udelay(MII_DELAY); |
cfdfa865 | 803 | SMC_SET_MII(lp, mii_reg | MII_MCLK); |
1da177e4 LT |
804 | udelay(MII_DELAY); |
805 | } | |
806 | ||
807 | return val; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Reads a register from the MII Management serial interface | |
812 | */ | |
813 | static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) | |
814 | { | |
815 | struct smc_local *lp = netdev_priv(dev); | |
816 | void __iomem *ioaddr = lp->base; | |
817 | unsigned int phydata; | |
818 | ||
cfdfa865 | 819 | SMC_SELECT_BANK(lp, 3); |
1da177e4 LT |
820 | |
821 | /* Idle - 32 ones */ | |
822 | smc_mii_out(dev, 0xffffffff, 32); | |
823 | ||
824 | /* Start code (01) + read (10) + phyaddr + phyreg */ | |
825 | smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); | |
826 | ||
827 | /* Turnaround (2bits) + phydata */ | |
828 | phydata = smc_mii_in(dev, 18); | |
829 | ||
830 | /* Return to idle state */ | |
cfdfa865 | 831 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
1da177e4 | 832 | |
6389aa45 BB |
833 | DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", |
834 | __func__, phyaddr, phyreg, phydata); | |
1da177e4 | 835 | |
cfdfa865 | 836 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
837 | return phydata; |
838 | } | |
839 | ||
840 | /* | |
841 | * Writes a register to the MII Management serial interface | |
842 | */ | |
843 | static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, | |
844 | int phydata) | |
845 | { | |
846 | struct smc_local *lp = netdev_priv(dev); | |
847 | void __iomem *ioaddr = lp->base; | |
848 | ||
cfdfa865 | 849 | SMC_SELECT_BANK(lp, 3); |
1da177e4 LT |
850 | |
851 | /* Idle - 32 ones */ | |
852 | smc_mii_out(dev, 0xffffffff, 32); | |
853 | ||
854 | /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */ | |
855 | smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); | |
856 | ||
857 | /* Return to idle state */ | |
cfdfa865 | 858 | SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO)); |
1da177e4 | 859 | |
6389aa45 BB |
860 | DBG(3, dev, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", |
861 | __func__, phyaddr, phyreg, phydata); | |
1da177e4 | 862 | |
cfdfa865 | 863 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
864 | } |
865 | ||
866 | /* | |
867 | * Finds and reports the PHY address | |
868 | */ | |
869 | static void smc_phy_detect(struct net_device *dev) | |
870 | { | |
871 | struct smc_local *lp = netdev_priv(dev); | |
872 | int phyaddr; | |
873 | ||
6389aa45 | 874 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
875 | |
876 | lp->phy_type = 0; | |
877 | ||
878 | /* | |
879 | * Scan all 32 PHY addresses if necessary, starting at | |
880 | * PHY#1 to PHY#31, and then PHY#0 last. | |
881 | */ | |
882 | for (phyaddr = 1; phyaddr < 33; ++phyaddr) { | |
883 | unsigned int id1, id2; | |
884 | ||
885 | /* Read the PHY identifiers */ | |
886 | id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1); | |
887 | id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2); | |
888 | ||
6389aa45 BB |
889 | DBG(3, dev, "phy_id1=0x%x, phy_id2=0x%x\n", |
890 | id1, id2); | |
1da177e4 LT |
891 | |
892 | /* Make sure it is a valid identifier */ | |
893 | if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 && | |
894 | id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { | |
895 | /* Save the PHY's address */ | |
896 | lp->mii.phy_id = phyaddr & 31; | |
897 | lp->phy_type = id1 << 16 | id2; | |
898 | break; | |
899 | } | |
900 | } | |
901 | } | |
902 | ||
903 | /* | |
904 | * Sets the PHY to a configuration as determined by the user | |
905 | */ | |
906 | static int smc_phy_fixed(struct net_device *dev) | |
907 | { | |
908 | struct smc_local *lp = netdev_priv(dev); | |
909 | void __iomem *ioaddr = lp->base; | |
910 | int phyaddr = lp->mii.phy_id; | |
911 | int bmcr, cfg1; | |
912 | ||
6389aa45 | 913 | DBG(3, dev, "%s\n", __func__); |
1da177e4 LT |
914 | |
915 | /* Enter Link Disable state */ | |
916 | cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG); | |
917 | cfg1 |= PHY_CFG1_LNKDIS; | |
918 | smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1); | |
919 | ||
920 | /* | |
921 | * Set our fixed capabilities | |
922 | * Disable auto-negotiation | |
923 | */ | |
924 | bmcr = 0; | |
925 | ||
926 | if (lp->ctl_rfduplx) | |
927 | bmcr |= BMCR_FULLDPLX; | |
928 | ||
929 | if (lp->ctl_rspeed == 100) | |
930 | bmcr |= BMCR_SPEED100; | |
931 | ||
932 | /* Write our capabilities to the phy control register */ | |
933 | smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); | |
934 | ||
935 | /* Re-Configure the Receive/Phy Control register */ | |
cfdfa865 MD |
936 | SMC_SELECT_BANK(lp, 0); |
937 | SMC_SET_RPC(lp, lp->rpc_cur_mode); | |
938 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
939 | |
940 | return 1; | |
941 | } | |
942 | ||
49ce9c2c | 943 | /** |
1da177e4 LT |
944 | * smc_phy_reset - reset the phy |
945 | * @dev: net device | |
946 | * @phy: phy address | |
947 | * | |
948 | * Issue a software reset for the specified PHY and | |
949 | * wait up to 100ms for the reset to complete. We should | |
950 | * not access the PHY for 50ms after issuing the reset. | |
951 | * | |
952 | * The time to wait appears to be dependent on the PHY. | |
953 | * | |
954 | * Must be called with lp->lock locked. | |
955 | */ | |
956 | static int smc_phy_reset(struct net_device *dev, int phy) | |
957 | { | |
958 | struct smc_local *lp = netdev_priv(dev); | |
959 | unsigned int bmcr; | |
960 | int timeout; | |
961 | ||
962 | smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET); | |
963 | ||
964 | for (timeout = 2; timeout; timeout--) { | |
965 | spin_unlock_irq(&lp->lock); | |
966 | msleep(50); | |
967 | spin_lock_irq(&lp->lock); | |
968 | ||
969 | bmcr = smc_phy_read(dev, phy, MII_BMCR); | |
970 | if (!(bmcr & BMCR_RESET)) | |
971 | break; | |
972 | } | |
973 | ||
974 | return bmcr & BMCR_RESET; | |
975 | } | |
976 | ||
49ce9c2c | 977 | /** |
1da177e4 LT |
978 | * smc_phy_powerdown - powerdown phy |
979 | * @dev: net device | |
980 | * | |
981 | * Power down the specified PHY | |
982 | */ | |
983 | static void smc_phy_powerdown(struct net_device *dev) | |
984 | { | |
985 | struct smc_local *lp = netdev_priv(dev); | |
986 | unsigned int bmcr; | |
987 | int phy = lp->mii.phy_id; | |
988 | ||
989 | if (lp->phy_type == 0) | |
990 | return; | |
991 | ||
992 | /* We need to ensure that no calls to smc_phy_configure are | |
993 | pending. | |
1da177e4 | 994 | */ |
4bb073c0 | 995 | cancel_work_sync(&lp->phy_configure); |
1da177e4 LT |
996 | |
997 | bmcr = smc_phy_read(dev, phy, MII_BMCR); | |
998 | smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN); | |
999 | } | |
1000 | ||
49ce9c2c | 1001 | /** |
1da177e4 LT |
1002 | * smc_phy_check_media - check the media status and adjust TCR |
1003 | * @dev: net device | |
1004 | * @init: set true for initialisation | |
1005 | * | |
1006 | * Select duplex mode depending on negotiation state. This | |
1007 | * also updates our carrier state. | |
1008 | */ | |
1009 | static void smc_phy_check_media(struct net_device *dev, int init) | |
1010 | { | |
1011 | struct smc_local *lp = netdev_priv(dev); | |
1012 | void __iomem *ioaddr = lp->base; | |
1013 | ||
1014 | if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { | |
1015 | /* duplex state has changed */ | |
1016 | if (lp->mii.full_duplex) { | |
1017 | lp->tcr_cur_mode |= TCR_SWFDUP; | |
1018 | } else { | |
1019 | lp->tcr_cur_mode &= ~TCR_SWFDUP; | |
1020 | } | |
1021 | ||
cfdfa865 MD |
1022 | SMC_SELECT_BANK(lp, 0); |
1023 | SMC_SET_TCR(lp, lp->tcr_cur_mode); | |
1da177e4 LT |
1024 | } |
1025 | } | |
1026 | ||
1027 | /* | |
1028 | * Configures the specified PHY through the MII management interface | |
1029 | * using Autonegotiation. | |
1030 | * Calls smc_phy_fixed() if the user has requested a certain config. | |
1031 | * If RPC ANEG bit is set, the media selection is dependent purely on | |
1032 | * the selection by the MII (either in the MII BMCR reg or the result | |
1033 | * of autonegotiation.) If the RPC ANEG bit is cleared, the selection | |
1034 | * is controlled by the RPC SPEED and RPC DPLX bits. | |
1035 | */ | |
6d5aefb8 | 1036 | static void smc_phy_configure(struct work_struct *work) |
1da177e4 | 1037 | { |
6d5aefb8 DH |
1038 | struct smc_local *lp = |
1039 | container_of(work, struct smc_local, phy_configure); | |
1040 | struct net_device *dev = lp->dev; | |
1da177e4 LT |
1041 | void __iomem *ioaddr = lp->base; |
1042 | int phyaddr = lp->mii.phy_id; | |
1043 | int my_phy_caps; /* My PHY capabilities */ | |
1044 | int my_ad_caps; /* My Advertised capabilities */ | |
1045 | int status; | |
1046 | ||
6389aa45 | 1047 | DBG(3, dev, "smc_program_phy()\n"); |
1da177e4 LT |
1048 | |
1049 | spin_lock_irq(&lp->lock); | |
1050 | ||
1051 | /* | |
1052 | * We should not be called if phy_type is zero. | |
1053 | */ | |
1054 | if (lp->phy_type == 0) | |
1055 | goto smc_phy_configure_exit; | |
1056 | ||
1057 | if (smc_phy_reset(dev, phyaddr)) { | |
6389aa45 | 1058 | netdev_info(dev, "PHY reset timed out\n"); |
1da177e4 LT |
1059 | goto smc_phy_configure_exit; |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Enable PHY Interrupts (for register 18) | |
1064 | * Interrupts listed here are disabled | |
1065 | */ | |
1066 | smc_phy_write(dev, phyaddr, PHY_MASK_REG, | |
1067 | PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD | | |
1068 | PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB | | |
1069 | PHY_INT_SPDDET | PHY_INT_DPLXDET); | |
1070 | ||
1071 | /* Configure the Receive/Phy Control register */ | |
cfdfa865 MD |
1072 | SMC_SELECT_BANK(lp, 0); |
1073 | SMC_SET_RPC(lp, lp->rpc_cur_mode); | |
1da177e4 LT |
1074 | |
1075 | /* If the user requested no auto neg, then go set his request */ | |
1076 | if (lp->mii.force_media) { | |
1077 | smc_phy_fixed(dev); | |
1078 | goto smc_phy_configure_exit; | |
1079 | } | |
1080 | ||
1081 | /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ | |
1082 | my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR); | |
1083 | ||
1084 | if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { | |
6389aa45 | 1085 | netdev_info(dev, "Auto negotiation NOT supported\n"); |
1da177e4 LT |
1086 | smc_phy_fixed(dev); |
1087 | goto smc_phy_configure_exit; | |
1088 | } | |
1089 | ||
1090 | my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */ | |
1091 | ||
1092 | if (my_phy_caps & BMSR_100BASE4) | |
1093 | my_ad_caps |= ADVERTISE_100BASE4; | |
1094 | if (my_phy_caps & BMSR_100FULL) | |
1095 | my_ad_caps |= ADVERTISE_100FULL; | |
1096 | if (my_phy_caps & BMSR_100HALF) | |
1097 | my_ad_caps |= ADVERTISE_100HALF; | |
1098 | if (my_phy_caps & BMSR_10FULL) | |
1099 | my_ad_caps |= ADVERTISE_10FULL; | |
1100 | if (my_phy_caps & BMSR_10HALF) | |
1101 | my_ad_caps |= ADVERTISE_10HALF; | |
1102 | ||
1103 | /* Disable capabilities not selected by our user */ | |
1104 | if (lp->ctl_rspeed != 100) | |
1105 | my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF); | |
1106 | ||
1107 | if (!lp->ctl_rfduplx) | |
1108 | my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); | |
1109 | ||
1110 | /* Update our Auto-Neg Advertisement Register */ | |
1111 | smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps); | |
1112 | lp->mii.advertising = my_ad_caps; | |
1113 | ||
1114 | /* | |
1115 | * Read the register back. Without this, it appears that when | |
1116 | * auto-negotiation is restarted, sometimes it isn't ready and | |
1117 | * the link does not come up. | |
1118 | */ | |
1119 | status = smc_phy_read(dev, phyaddr, MII_ADVERTISE); | |
1120 | ||
6389aa45 BB |
1121 | DBG(2, dev, "phy caps=%x\n", my_phy_caps); |
1122 | DBG(2, dev, "phy advertised caps=%x\n", my_ad_caps); | |
1da177e4 LT |
1123 | |
1124 | /* Restart auto-negotiation process in order to advertise my caps */ | |
1125 | smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); | |
1126 | ||
1127 | smc_phy_check_media(dev, 1); | |
1128 | ||
1129 | smc_phy_configure_exit: | |
cfdfa865 | 1130 | SMC_SELECT_BANK(lp, 2); |
1da177e4 | 1131 | spin_unlock_irq(&lp->lock); |
1da177e4 LT |
1132 | } |
1133 | ||
1134 | /* | |
1135 | * smc_phy_interrupt | |
1136 | * | |
1137 | * Purpose: Handle interrupts relating to PHY register 18. This is | |
1138 | * called from the "hard" interrupt handler under our private spinlock. | |
1139 | */ | |
1140 | static void smc_phy_interrupt(struct net_device *dev) | |
1141 | { | |
1142 | struct smc_local *lp = netdev_priv(dev); | |
1143 | int phyaddr = lp->mii.phy_id; | |
1144 | int phy18; | |
1145 | ||
6389aa45 | 1146 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
1147 | |
1148 | if (lp->phy_type == 0) | |
1149 | return; | |
1150 | ||
1151 | for(;;) { | |
1152 | smc_phy_check_media(dev, 0); | |
1153 | ||
1154 | /* Read PHY Register 18, Status Output */ | |
1155 | phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG); | |
1156 | if ((phy18 & PHY_INT_INT) == 0) | |
1157 | break; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ | |
1162 | ||
1163 | static void smc_10bt_check_media(struct net_device *dev, int init) | |
1164 | { | |
1165 | struct smc_local *lp = netdev_priv(dev); | |
1166 | void __iomem *ioaddr = lp->base; | |
1167 | unsigned int old_carrier, new_carrier; | |
1168 | ||
1169 | old_carrier = netif_carrier_ok(dev) ? 1 : 0; | |
1170 | ||
cfdfa865 MD |
1171 | SMC_SELECT_BANK(lp, 0); |
1172 | new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0; | |
1173 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1174 | |
1175 | if (init || (old_carrier != new_carrier)) { | |
1176 | if (!new_carrier) { | |
1177 | netif_carrier_off(dev); | |
1178 | } else { | |
1179 | netif_carrier_on(dev); | |
1180 | } | |
1181 | if (netif_msg_link(lp)) | |
6389aa45 BB |
1182 | netdev_info(dev, "link %s\n", |
1183 | new_carrier ? "up" : "down"); | |
1da177e4 LT |
1184 | } |
1185 | } | |
1186 | ||
1187 | static void smc_eph_interrupt(struct net_device *dev) | |
1188 | { | |
1189 | struct smc_local *lp = netdev_priv(dev); | |
1190 | void __iomem *ioaddr = lp->base; | |
1191 | unsigned int ctl; | |
1192 | ||
1193 | smc_10bt_check_media(dev, 0); | |
1194 | ||
cfdfa865 MD |
1195 | SMC_SELECT_BANK(lp, 1); |
1196 | ctl = SMC_GET_CTL(lp); | |
1197 | SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE); | |
1198 | SMC_SET_CTL(lp, ctl); | |
1199 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1200 | } |
1201 | ||
1202 | /* | |
1203 | * This is the main routine of the driver, to handle the device when | |
1204 | * it needs some attention. | |
1205 | */ | |
7d12e780 | 1206 | static irqreturn_t smc_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1207 | { |
1208 | struct net_device *dev = dev_id; | |
1209 | struct smc_local *lp = netdev_priv(dev); | |
1210 | void __iomem *ioaddr = lp->base; | |
1211 | int status, mask, timeout, card_stats; | |
1212 | int saved_pointer; | |
1213 | ||
6389aa45 | 1214 | DBG(3, dev, "%s\n", __func__); |
1da177e4 LT |
1215 | |
1216 | spin_lock(&lp->lock); | |
1217 | ||
1218 | /* A preamble may be used when there is a potential race | |
1219 | * between the interruptible transmit functions and this | |
1220 | * ISR. */ | |
1221 | SMC_INTERRUPT_PREAMBLE; | |
1222 | ||
cfdfa865 MD |
1223 | saved_pointer = SMC_GET_PTR(lp); |
1224 | mask = SMC_GET_INT_MASK(lp); | |
1225 | SMC_SET_INT_MASK(lp, 0); | |
1da177e4 LT |
1226 | |
1227 | /* set a timeout value, so I don't stay here forever */ | |
5d0571d9 | 1228 | timeout = MAX_IRQ_LOOPS; |
1da177e4 LT |
1229 | |
1230 | do { | |
cfdfa865 | 1231 | status = SMC_GET_INT(lp); |
1da177e4 | 1232 | |
6389aa45 BB |
1233 | DBG(2, dev, "INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", |
1234 | status, mask, | |
1235 | ({ int meminfo; SMC_SELECT_BANK(lp, 0); | |
1236 | meminfo = SMC_GET_MIR(lp); | |
1237 | SMC_SELECT_BANK(lp, 2); meminfo; }), | |
1238 | SMC_GET_FIFO(lp)); | |
1da177e4 LT |
1239 | |
1240 | status &= mask; | |
1241 | if (!status) | |
1242 | break; | |
1243 | ||
ea937560 NP |
1244 | if (status & IM_TX_INT) { |
1245 | /* do this before RX as it will free memory quickly */ | |
6389aa45 | 1246 | DBG(3, dev, "TX int\n"); |
1da177e4 | 1247 | smc_tx(dev); |
cfdfa865 | 1248 | SMC_ACK_INT(lp, IM_TX_INT); |
1da177e4 LT |
1249 | if (THROTTLE_TX_PKTS) |
1250 | netif_wake_queue(dev); | |
ea937560 | 1251 | } else if (status & IM_RCV_INT) { |
6389aa45 | 1252 | DBG(3, dev, "RX irq\n"); |
ea937560 | 1253 | smc_rcv(dev); |
1da177e4 | 1254 | } else if (status & IM_ALLOC_INT) { |
6389aa45 | 1255 | DBG(3, dev, "Allocation irq\n"); |
1da177e4 LT |
1256 | tasklet_hi_schedule(&lp->tx_task); |
1257 | mask &= ~IM_ALLOC_INT; | |
1258 | } else if (status & IM_TX_EMPTY_INT) { | |
6389aa45 | 1259 | DBG(3, dev, "TX empty\n"); |
1da177e4 LT |
1260 | mask &= ~IM_TX_EMPTY_INT; |
1261 | ||
1262 | /* update stats */ | |
cfdfa865 MD |
1263 | SMC_SELECT_BANK(lp, 0); |
1264 | card_stats = SMC_GET_COUNTER(lp); | |
1265 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 LT |
1266 | |
1267 | /* single collisions */ | |
09f75cd7 | 1268 | dev->stats.collisions += card_stats & 0xF; |
1da177e4 LT |
1269 | card_stats >>= 4; |
1270 | ||
1271 | /* multiple collisions */ | |
09f75cd7 | 1272 | dev->stats.collisions += card_stats & 0xF; |
1da177e4 | 1273 | } else if (status & IM_RX_OVRN_INT) { |
6389aa45 BB |
1274 | DBG(1, dev, "RX overrun (EPH_ST 0x%04x)\n", |
1275 | ({ int eph_st; SMC_SELECT_BANK(lp, 0); | |
1276 | eph_st = SMC_GET_EPH_STATUS(lp); | |
1277 | SMC_SELECT_BANK(lp, 2); eph_st; })); | |
cfdfa865 | 1278 | SMC_ACK_INT(lp, IM_RX_OVRN_INT); |
09f75cd7 JG |
1279 | dev->stats.rx_errors++; |
1280 | dev->stats.rx_fifo_errors++; | |
1da177e4 LT |
1281 | } else if (status & IM_EPH_INT) { |
1282 | smc_eph_interrupt(dev); | |
1283 | } else if (status & IM_MDINT) { | |
cfdfa865 | 1284 | SMC_ACK_INT(lp, IM_MDINT); |
1da177e4 LT |
1285 | smc_phy_interrupt(dev); |
1286 | } else if (status & IM_ERCV_INT) { | |
cfdfa865 | 1287 | SMC_ACK_INT(lp, IM_ERCV_INT); |
6389aa45 | 1288 | PRINTK(dev, "UNSUPPORTED: ERCV INTERRUPT\n"); |
1da177e4 LT |
1289 | } |
1290 | } while (--timeout); | |
1291 | ||
1292 | /* restore register states */ | |
cfdfa865 MD |
1293 | SMC_SET_PTR(lp, saved_pointer); |
1294 | SMC_SET_INT_MASK(lp, mask); | |
1da177e4 LT |
1295 | spin_unlock(&lp->lock); |
1296 | ||
c500cb26 | 1297 | #ifndef CONFIG_NET_POLL_CONTROLLER |
5d0571d9 | 1298 | if (timeout == MAX_IRQ_LOOPS) |
6389aa45 BB |
1299 | PRINTK(dev, "spurious interrupt (mask = 0x%02x)\n", |
1300 | mask); | |
c500cb26 | 1301 | #endif |
6389aa45 BB |
1302 | DBG(3, dev, "Interrupt done (%d loops)\n", |
1303 | MAX_IRQ_LOOPS - timeout); | |
1da177e4 LT |
1304 | |
1305 | /* | |
1306 | * We return IRQ_HANDLED unconditionally here even if there was | |
1307 | * nothing to do. There is a possibility that a packet might | |
1308 | * get enqueued into the chip right after TX_EMPTY_INT is raised | |
1309 | * but just before the CPU acknowledges the IRQ. | |
1310 | * Better take an unneeded IRQ in some occasions than complexifying | |
1311 | * the code for all cases. | |
1312 | */ | |
1313 | return IRQ_HANDLED; | |
1314 | } | |
1315 | ||
1316 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1317 | /* | |
1318 | * Polling receive - used by netconsole and other diagnostic tools | |
1319 | * to allow network i/o with interrupts disabled. | |
1320 | */ | |
1321 | static void smc_poll_controller(struct net_device *dev) | |
1322 | { | |
1323 | disable_irq(dev->irq); | |
9c8e7f5c | 1324 | smc_interrupt(dev->irq, dev); |
1da177e4 LT |
1325 | enable_irq(dev->irq); |
1326 | } | |
1327 | #endif | |
1328 | ||
1329 | /* Our watchdog timed out. Called by the networking layer */ | |
1330 | static void smc_timeout(struct net_device *dev) | |
1331 | { | |
1332 | struct smc_local *lp = netdev_priv(dev); | |
1333 | void __iomem *ioaddr = lp->base; | |
8de90115 | 1334 | int status, mask, eph_st, meminfo, fifo; |
1da177e4 | 1335 | |
6389aa45 | 1336 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
1337 | |
1338 | spin_lock_irq(&lp->lock); | |
cfdfa865 MD |
1339 | status = SMC_GET_INT(lp); |
1340 | mask = SMC_GET_INT_MASK(lp); | |
1341 | fifo = SMC_GET_FIFO(lp); | |
1342 | SMC_SELECT_BANK(lp, 0); | |
1343 | eph_st = SMC_GET_EPH_STATUS(lp); | |
1344 | meminfo = SMC_GET_MIR(lp); | |
1345 | SMC_SELECT_BANK(lp, 2); | |
1da177e4 | 1346 | spin_unlock_irq(&lp->lock); |
6389aa45 BB |
1347 | PRINTK(dev, "TX timeout (INT 0x%02x INTMASK 0x%02x MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", |
1348 | status, mask, meminfo, fifo, eph_st); | |
1da177e4 LT |
1349 | |
1350 | smc_reset(dev); | |
1351 | smc_enable(dev); | |
1352 | ||
1353 | /* | |
1354 | * Reconfiguring the PHY doesn't seem like a bad idea here, but | |
1355 | * smc_phy_configure() calls msleep() which calls schedule_timeout() | |
1356 | * which calls schedule(). Hence we use a work queue. | |
1357 | */ | |
4bb073c0 DM |
1358 | if (lp->phy_type != 0) |
1359 | schedule_work(&lp->phy_configure); | |
1da177e4 LT |
1360 | |
1361 | /* We can accept TX packets again */ | |
1ae5dc34 | 1362 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
1363 | netif_wake_queue(dev); |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * This routine will, depending on the values passed to it, | |
1368 | * either make it accept multicast packets, go into | |
1369 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1370 | * a select set of multicast packets | |
1371 | */ | |
1372 | static void smc_set_multicast_list(struct net_device *dev) | |
1373 | { | |
1374 | struct smc_local *lp = netdev_priv(dev); | |
1375 | void __iomem *ioaddr = lp->base; | |
1376 | unsigned char multicast_table[8]; | |
1377 | int update_multicast = 0; | |
1378 | ||
6389aa45 | 1379 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
1380 | |
1381 | if (dev->flags & IFF_PROMISC) { | |
6389aa45 | 1382 | DBG(2, dev, "RCR_PRMS\n"); |
1da177e4 LT |
1383 | lp->rcr_cur_mode |= RCR_PRMS; |
1384 | } | |
1385 | ||
1386 | /* BUG? I never disable promiscuous mode if multicasting was turned on. | |
1387 | Now, I turn off promiscuous mode, but I don't do anything to multicasting | |
1388 | when promiscuous mode is turned on. | |
1389 | */ | |
1390 | ||
1391 | /* | |
1392 | * Here, I am setting this to accept all multicast packets. | |
1393 | * I don't need to zero the multicast table, because the flag is | |
1394 | * checked before the table is | |
1395 | */ | |
4cd24eaf | 1396 | else if (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) { |
6389aa45 | 1397 | DBG(2, dev, "RCR_ALMUL\n"); |
1da177e4 LT |
1398 | lp->rcr_cur_mode |= RCR_ALMUL; |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * This sets the internal hardware table to filter out unwanted | |
1403 | * multicast packets before they take up memory. | |
1404 | * | |
1405 | * The SMC chip uses a hash table where the high 6 bits of the CRC of | |
1406 | * address are the offset into the table. If that bit is 1, then the | |
1407 | * multicast packet is accepted. Otherwise, it's dropped silently. | |
1408 | * | |
1409 | * To use the 6 bits as an offset into the table, the high 3 bits are | |
1410 | * the number of the 8 bit register, while the low 3 bits are the bit | |
1411 | * within that register. | |
1412 | */ | |
4cd24eaf | 1413 | else if (!netdev_mc_empty(dev)) { |
22bedad3 | 1414 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1415 | |
1416 | /* table for flipping the order of 3 bits */ | |
1417 | static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7}; | |
1418 | ||
1419 | /* start with a table of all zeros: reject all */ | |
1420 | memset(multicast_table, 0, sizeof(multicast_table)); | |
1421 | ||
22bedad3 | 1422 | netdev_for_each_mc_addr(ha, dev) { |
1da177e4 LT |
1423 | int position; |
1424 | ||
1da177e4 | 1425 | /* only use the low order bits */ |
22bedad3 | 1426 | position = crc32_le(~0, ha->addr, 6) & 0x3f; |
1da177e4 LT |
1427 | |
1428 | /* do some messy swapping to put the bit in the right spot */ | |
1429 | multicast_table[invert3[position&7]] |= | |
1430 | (1<<invert3[(position>>3)&7]); | |
1431 | } | |
1432 | ||
1433 | /* be sure I get rid of flags I might have set */ | |
1434 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); | |
1435 | ||
1436 | /* now, the table can be loaded into the chipset */ | |
1437 | update_multicast = 1; | |
1438 | } else { | |
6389aa45 | 1439 | DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n"); |
1da177e4 LT |
1440 | lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL); |
1441 | ||
1442 | /* | |
1443 | * since I'm disabling all multicast entirely, I need to | |
1444 | * clear the multicast list | |
1445 | */ | |
1446 | memset(multicast_table, 0, sizeof(multicast_table)); | |
1447 | update_multicast = 1; | |
1448 | } | |
1449 | ||
1450 | spin_lock_irq(&lp->lock); | |
cfdfa865 MD |
1451 | SMC_SELECT_BANK(lp, 0); |
1452 | SMC_SET_RCR(lp, lp->rcr_cur_mode); | |
1da177e4 | 1453 | if (update_multicast) { |
cfdfa865 MD |
1454 | SMC_SELECT_BANK(lp, 3); |
1455 | SMC_SET_MCAST(lp, multicast_table); | |
1da177e4 | 1456 | } |
cfdfa865 | 1457 | SMC_SELECT_BANK(lp, 2); |
1da177e4 LT |
1458 | spin_unlock_irq(&lp->lock); |
1459 | } | |
1460 | ||
1461 | ||
1462 | /* | |
1463 | * Open and Initialize the board | |
1464 | * | |
1465 | * Set up everything, reset the card, etc.. | |
1466 | */ | |
1467 | static int | |
1468 | smc_open(struct net_device *dev) | |
1469 | { | |
1470 | struct smc_local *lp = netdev_priv(dev); | |
1471 | ||
6389aa45 | 1472 | DBG(2, dev, "%s\n", __func__); |
1da177e4 | 1473 | |
1da177e4 LT |
1474 | /* Setup the default Register Modes */ |
1475 | lp->tcr_cur_mode = TCR_DEFAULT; | |
1476 | lp->rcr_cur_mode = RCR_DEFAULT; | |
b0dbcf51 RK |
1477 | lp->rpc_cur_mode = RPC_DEFAULT | |
1478 | lp->cfg.leda << RPC_LSXA_SHFT | | |
1479 | lp->cfg.ledb << RPC_LSXB_SHFT; | |
1da177e4 LT |
1480 | |
1481 | /* | |
1482 | * If we are not using a MII interface, we need to | |
1483 | * monitor our own carrier signal to detect faults. | |
1484 | */ | |
1485 | if (lp->phy_type == 0) | |
1486 | lp->tcr_cur_mode |= TCR_MON_CSN; | |
1487 | ||
1488 | /* reset the hardware */ | |
1489 | smc_reset(dev); | |
1490 | smc_enable(dev); | |
1491 | ||
1492 | /* Configure the PHY, initialize the link state */ | |
1493 | if (lp->phy_type != 0) | |
6d5aefb8 | 1494 | smc_phy_configure(&lp->phy_configure); |
1da177e4 LT |
1495 | else { |
1496 | spin_lock_irq(&lp->lock); | |
1497 | smc_10bt_check_media(dev, 1); | |
1498 | spin_unlock_irq(&lp->lock); | |
1499 | } | |
1500 | ||
1501 | netif_start_queue(dev); | |
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | /* | |
1506 | * smc_close | |
1507 | * | |
1508 | * this makes the board clean up everything that it can | |
1509 | * and not talk to the outside world. Caused by | |
1510 | * an 'ifconfig ethX down' | |
1511 | */ | |
1512 | static int smc_close(struct net_device *dev) | |
1513 | { | |
1514 | struct smc_local *lp = netdev_priv(dev); | |
1515 | ||
6389aa45 | 1516 | DBG(2, dev, "%s\n", __func__); |
1da177e4 LT |
1517 | |
1518 | netif_stop_queue(dev); | |
1519 | netif_carrier_off(dev); | |
1520 | ||
1521 | /* clear everything */ | |
1522 | smc_shutdown(dev); | |
be83668a | 1523 | tasklet_kill(&lp->tx_task); |
1da177e4 | 1524 | smc_phy_powerdown(dev); |
1da177e4 LT |
1525 | return 0; |
1526 | } | |
1527 | ||
1da177e4 LT |
1528 | /* |
1529 | * Ethtool support | |
1530 | */ | |
1531 | static int | |
1532 | smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1533 | { | |
1534 | struct smc_local *lp = netdev_priv(dev); | |
1535 | int ret; | |
1536 | ||
1537 | cmd->maxtxpkt = 1; | |
1538 | cmd->maxrxpkt = 1; | |
1539 | ||
1540 | if (lp->phy_type != 0) { | |
1541 | spin_lock_irq(&lp->lock); | |
1542 | ret = mii_ethtool_gset(&lp->mii, cmd); | |
1543 | spin_unlock_irq(&lp->lock); | |
1544 | } else { | |
1545 | cmd->supported = SUPPORTED_10baseT_Half | | |
1546 | SUPPORTED_10baseT_Full | | |
1547 | SUPPORTED_TP | SUPPORTED_AUI; | |
1548 | ||
1549 | if (lp->ctl_rspeed == 10) | |
70739497 | 1550 | ethtool_cmd_speed_set(cmd, SPEED_10); |
1da177e4 | 1551 | else if (lp->ctl_rspeed == 100) |
70739497 | 1552 | ethtool_cmd_speed_set(cmd, SPEED_100); |
1da177e4 LT |
1553 | |
1554 | cmd->autoneg = AUTONEG_DISABLE; | |
1555 | cmd->transceiver = XCVR_INTERNAL; | |
1556 | cmd->port = 0; | |
1557 | cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF; | |
1558 | ||
1559 | ret = 0; | |
1560 | } | |
1561 | ||
1562 | return ret; | |
1563 | } | |
1564 | ||
1565 | static int | |
1566 | smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1567 | { | |
1568 | struct smc_local *lp = netdev_priv(dev); | |
1569 | int ret; | |
1570 | ||
1571 | if (lp->phy_type != 0) { | |
1572 | spin_lock_irq(&lp->lock); | |
1573 | ret = mii_ethtool_sset(&lp->mii, cmd); | |
1574 | spin_unlock_irq(&lp->lock); | |
1575 | } else { | |
1576 | if (cmd->autoneg != AUTONEG_DISABLE || | |
1577 | cmd->speed != SPEED_10 || | |
1578 | (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) || | |
1579 | (cmd->port != PORT_TP && cmd->port != PORT_AUI)) | |
1580 | return -EINVAL; | |
1581 | ||
1582 | // lp->port = cmd->port; | |
1583 | lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL; | |
1584 | ||
1585 | // if (netif_running(dev)) | |
1586 | // smc_set_port(dev); | |
1587 | ||
1588 | ret = 0; | |
1589 | } | |
1590 | ||
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | static void | |
1595 | smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1596 | { | |
7826d43f JP |
1597 | strlcpy(info->driver, CARDNAME, sizeof(info->driver)); |
1598 | strlcpy(info->version, version, sizeof(info->version)); | |
1599 | strlcpy(info->bus_info, dev_name(dev->dev.parent), | |
1600 | sizeof(info->bus_info)); | |
1da177e4 LT |
1601 | } |
1602 | ||
1603 | static int smc_ethtool_nwayreset(struct net_device *dev) | |
1604 | { | |
1605 | struct smc_local *lp = netdev_priv(dev); | |
1606 | int ret = -EINVAL; | |
1607 | ||
1608 | if (lp->phy_type != 0) { | |
1609 | spin_lock_irq(&lp->lock); | |
1610 | ret = mii_nway_restart(&lp->mii); | |
1611 | spin_unlock_irq(&lp->lock); | |
1612 | } | |
1613 | ||
1614 | return ret; | |
1615 | } | |
1616 | ||
1617 | static u32 smc_ethtool_getmsglevel(struct net_device *dev) | |
1618 | { | |
1619 | struct smc_local *lp = netdev_priv(dev); | |
1620 | return lp->msg_enable; | |
1621 | } | |
1622 | ||
1623 | static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1624 | { | |
1625 | struct smc_local *lp = netdev_priv(dev); | |
1626 | lp->msg_enable = level; | |
1627 | } | |
1628 | ||
357fe2c6 VS |
1629 | static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word) |
1630 | { | |
1631 | u16 ctl; | |
1632 | struct smc_local *lp = netdev_priv(dev); | |
1633 | void __iomem *ioaddr = lp->base; | |
1634 | ||
1635 | spin_lock_irq(&lp->lock); | |
1636 | /* load word into GP register */ | |
1637 | SMC_SELECT_BANK(lp, 1); | |
1638 | SMC_SET_GP(lp, word); | |
1639 | /* set the address to put the data in EEPROM */ | |
1640 | SMC_SELECT_BANK(lp, 2); | |
1641 | SMC_SET_PTR(lp, addr); | |
1642 | /* tell it to write */ | |
1643 | SMC_SELECT_BANK(lp, 1); | |
1644 | ctl = SMC_GET_CTL(lp); | |
1645 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); | |
1646 | /* wait for it to finish */ | |
1647 | do { | |
1648 | udelay(1); | |
1649 | } while (SMC_GET_CTL(lp) & CTL_STORE); | |
1650 | /* clean up */ | |
1651 | SMC_SET_CTL(lp, ctl); | |
1652 | SMC_SELECT_BANK(lp, 2); | |
1653 | spin_unlock_irq(&lp->lock); | |
1654 | return 0; | |
1655 | } | |
1656 | ||
1657 | static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word) | |
1658 | { | |
1659 | u16 ctl; | |
1660 | struct smc_local *lp = netdev_priv(dev); | |
1661 | void __iomem *ioaddr = lp->base; | |
1662 | ||
1663 | spin_lock_irq(&lp->lock); | |
1664 | /* set the EEPROM address to get the data from */ | |
1665 | SMC_SELECT_BANK(lp, 2); | |
1666 | SMC_SET_PTR(lp, addr | PTR_READ); | |
1667 | /* tell it to load */ | |
1668 | SMC_SELECT_BANK(lp, 1); | |
1669 | SMC_SET_GP(lp, 0xffff); /* init to known */ | |
1670 | ctl = SMC_GET_CTL(lp); | |
1671 | SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); | |
1672 | /* wait for it to finish */ | |
1673 | do { | |
1674 | udelay(1); | |
1675 | } while (SMC_GET_CTL(lp) & CTL_RELOAD); | |
1676 | /* read word from GP register */ | |
1677 | *word = SMC_GET_GP(lp); | |
1678 | /* clean up */ | |
1679 | SMC_SET_CTL(lp, ctl); | |
1680 | SMC_SELECT_BANK(lp, 2); | |
1681 | spin_unlock_irq(&lp->lock); | |
1682 | return 0; | |
1683 | } | |
1684 | ||
1685 | static int smc_ethtool_geteeprom_len(struct net_device *dev) | |
1686 | { | |
1687 | return 0x23 * 2; | |
1688 | } | |
1689 | ||
1690 | static int smc_ethtool_geteeprom(struct net_device *dev, | |
1691 | struct ethtool_eeprom *eeprom, u8 *data) | |
1692 | { | |
1693 | int i; | |
1694 | int imax; | |
1695 | ||
6389aa45 | 1696 | DBG(1, dev, "Reading %d bytes at %d(0x%x)\n", |
357fe2c6 VS |
1697 | eeprom->len, eeprom->offset, eeprom->offset); |
1698 | imax = smc_ethtool_geteeprom_len(dev); | |
1699 | for (i = 0; i < eeprom->len; i += 2) { | |
1700 | int ret; | |
1701 | u16 wbuf; | |
1702 | int offset = i + eeprom->offset; | |
1703 | if (offset > imax) | |
1704 | break; | |
1705 | ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf); | |
1706 | if (ret != 0) | |
1707 | return ret; | |
6389aa45 | 1708 | DBG(2, dev, "Read 0x%x from 0x%x\n", wbuf, offset >> 1); |
357fe2c6 VS |
1709 | data[i] = (wbuf >> 8) & 0xff; |
1710 | data[i+1] = wbuf & 0xff; | |
1711 | } | |
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | static int smc_ethtool_seteeprom(struct net_device *dev, | |
1716 | struct ethtool_eeprom *eeprom, u8 *data) | |
1717 | { | |
1718 | int i; | |
1719 | int imax; | |
1720 | ||
6389aa45 BB |
1721 | DBG(1, dev, "Writing %d bytes to %d(0x%x)\n", |
1722 | eeprom->len, eeprom->offset, eeprom->offset); | |
357fe2c6 VS |
1723 | imax = smc_ethtool_geteeprom_len(dev); |
1724 | for (i = 0; i < eeprom->len; i += 2) { | |
1725 | int ret; | |
1726 | u16 wbuf; | |
1727 | int offset = i + eeprom->offset; | |
1728 | if (offset > imax) | |
1729 | break; | |
1730 | wbuf = (data[i] << 8) | data[i + 1]; | |
6389aa45 | 1731 | DBG(2, dev, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1); |
357fe2c6 VS |
1732 | ret = smc_write_eeprom_word(dev, offset >> 1, wbuf); |
1733 | if (ret != 0) | |
1734 | return ret; | |
1735 | } | |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | ||
7282d491 | 1740 | static const struct ethtool_ops smc_ethtool_ops = { |
1da177e4 LT |
1741 | .get_settings = smc_ethtool_getsettings, |
1742 | .set_settings = smc_ethtool_setsettings, | |
1743 | .get_drvinfo = smc_ethtool_getdrvinfo, | |
1744 | ||
1745 | .get_msglevel = smc_ethtool_getmsglevel, | |
1746 | .set_msglevel = smc_ethtool_setmsglevel, | |
1747 | .nway_reset = smc_ethtool_nwayreset, | |
1748 | .get_link = ethtool_op_get_link, | |
357fe2c6 VS |
1749 | .get_eeprom_len = smc_ethtool_geteeprom_len, |
1750 | .get_eeprom = smc_ethtool_geteeprom, | |
1751 | .set_eeprom = smc_ethtool_seteeprom, | |
1da177e4 LT |
1752 | }; |
1753 | ||
a528079e MD |
1754 | static const struct net_device_ops smc_netdev_ops = { |
1755 | .ndo_open = smc_open, | |
1756 | .ndo_stop = smc_close, | |
1757 | .ndo_start_xmit = smc_hard_start_xmit, | |
1758 | .ndo_tx_timeout = smc_timeout, | |
afc4b13d | 1759 | .ndo_set_rx_mode = smc_set_multicast_list, |
635ecaa7 | 1760 | .ndo_change_mtu = eth_change_mtu, |
a528079e MD |
1761 | .ndo_validate_addr = eth_validate_addr, |
1762 | .ndo_set_mac_address = eth_mac_addr, | |
1763 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1764 | .ndo_poll_controller = smc_poll_controller, | |
1765 | #endif | |
1766 | }; | |
1767 | ||
1da177e4 LT |
1768 | /* |
1769 | * smc_findirq | |
1770 | * | |
1771 | * This routine has a simple purpose -- make the SMC chip generate an | |
1772 | * interrupt, so an auto-detect routine can detect it, and find the IRQ, | |
1773 | */ | |
1774 | /* | |
1775 | * does this still work? | |
1776 | * | |
1777 | * I just deleted auto_irq.c, since it was never built... | |
1778 | * --jgarzik | |
1779 | */ | |
1e48fea4 | 1780 | static int smc_findirq(struct smc_local *lp) |
1da177e4 | 1781 | { |
cfdfa865 | 1782 | void __iomem *ioaddr = lp->base; |
1da177e4 LT |
1783 | int timeout = 20; |
1784 | unsigned long cookie; | |
1785 | ||
702b3468 | 1786 | DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
1787 | |
1788 | cookie = probe_irq_on(); | |
1789 | ||
1790 | /* | |
1791 | * What I try to do here is trigger an ALLOC_INT. This is done | |
1792 | * by allocating a small chunk of memory, which will give an interrupt | |
1793 | * when done. | |
1794 | */ | |
1795 | /* enable ALLOCation interrupts ONLY */ | |
cfdfa865 MD |
1796 | SMC_SELECT_BANK(lp, 2); |
1797 | SMC_SET_INT_MASK(lp, IM_ALLOC_INT); | |
1da177e4 LT |
1798 | |
1799 | /* | |
1800 | * Allocate 512 bytes of memory. Note that the chip was just | |
1801 | * reset so all the memory is available | |
1802 | */ | |
cfdfa865 | 1803 | SMC_SET_MMU_CMD(lp, MC_ALLOC | 1); |
1da177e4 LT |
1804 | |
1805 | /* | |
1806 | * Wait until positive that the interrupt has been generated | |
1807 | */ | |
1808 | do { | |
1809 | int int_status; | |
1810 | udelay(10); | |
cfdfa865 | 1811 | int_status = SMC_GET_INT(lp); |
1da177e4 LT |
1812 | if (int_status & IM_ALLOC_INT) |
1813 | break; /* got the interrupt */ | |
1814 | } while (--timeout); | |
1815 | ||
1816 | /* | |
1817 | * there is really nothing that I can do here if timeout fails, | |
1818 | * as autoirq_report will return a 0 anyway, which is what I | |
1819 | * want in this case. Plus, the clean up is needed in both | |
1820 | * cases. | |
1821 | */ | |
1822 | ||
1823 | /* and disable all interrupts again */ | |
cfdfa865 | 1824 | SMC_SET_INT_MASK(lp, 0); |
1da177e4 LT |
1825 | |
1826 | /* and return what I found */ | |
1827 | return probe_irq_off(cookie); | |
1828 | } | |
1829 | ||
1830 | /* | |
1831 | * Function: smc_probe(unsigned long ioaddr) | |
1832 | * | |
1833 | * Purpose: | |
1834 | * Tests to see if a given ioaddr points to an SMC91x chip. | |
1835 | * Returns a 0 on success | |
1836 | * | |
1837 | * Algorithm: | |
1838 | * (1) see if the high byte of BANK_SELECT is 0x33 | |
1839 | * (2) compare the ioaddr with the base register's address | |
1840 | * (3) see if I recognize the chip ID in the appropriate register | |
1841 | * | |
1842 | * Here I do typical initialization tasks. | |
1843 | * | |
1844 | * o Initialize the structure if needed | |
1845 | * o print out my vanity message if not done so already | |
1846 | * o print out what type of hardware is detected | |
1847 | * o print out the ethernet address | |
1848 | * o find the IRQ | |
1849 | * o set up my private data | |
1850 | * o configure the dev structure with my subroutines | |
1851 | * o actually GRAB the irq. | |
1852 | * o GRAB the region | |
1853 | */ | |
1e48fea4 | 1854 | static int smc_probe(struct net_device *dev, void __iomem *ioaddr, |
1dd06ae8 | 1855 | unsigned long irq_flags) |
1da177e4 LT |
1856 | { |
1857 | struct smc_local *lp = netdev_priv(dev); | |
0795af57 | 1858 | int retval; |
1da177e4 LT |
1859 | unsigned int val, revision_register; |
1860 | const char *version_string; | |
1861 | ||
6389aa45 | 1862 | DBG(2, dev, "%s: %s\n", CARDNAME, __func__); |
1da177e4 LT |
1863 | |
1864 | /* First, see if the high byte is 0x33 */ | |
cfdfa865 | 1865 | val = SMC_CURRENT_BANK(lp); |
6389aa45 BB |
1866 | DBG(2, dev, "%s: bank signature probe returned 0x%04x\n", |
1867 | CARDNAME, val); | |
1da177e4 LT |
1868 | if ((val & 0xFF00) != 0x3300) { |
1869 | if ((val & 0xFF) == 0x33) { | |
6389aa45 BB |
1870 | netdev_warn(dev, |
1871 | "%s: Detected possible byte-swapped interface at IOADDR %p\n", | |
1872 | CARDNAME, ioaddr); | |
1da177e4 LT |
1873 | } |
1874 | retval = -ENODEV; | |
1875 | goto err_out; | |
1876 | } | |
1877 | ||
1878 | /* | |
1879 | * The above MIGHT indicate a device, but I need to write to | |
1880 | * further test this. | |
1881 | */ | |
cfdfa865 MD |
1882 | SMC_SELECT_BANK(lp, 0); |
1883 | val = SMC_CURRENT_BANK(lp); | |
1da177e4 LT |
1884 | if ((val & 0xFF00) != 0x3300) { |
1885 | retval = -ENODEV; | |
1886 | goto err_out; | |
1887 | } | |
1888 | ||
1889 | /* | |
1890 | * well, we've already written once, so hopefully another | |
1891 | * time won't hurt. This time, I need to switch the bank | |
1892 | * register to bank 1, so I can access the base address | |
1893 | * register | |
1894 | */ | |
cfdfa865 MD |
1895 | SMC_SELECT_BANK(lp, 1); |
1896 | val = SMC_GET_BASE(lp); | |
1da177e4 | 1897 | val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; |
6bc21eed | 1898 | if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { |
6389aa45 BB |
1899 | netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n", |
1900 | CARDNAME, ioaddr, val); | |
1da177e4 LT |
1901 | } |
1902 | ||
1903 | /* | |
1904 | * check if the revision register is something that I | |
1905 | * recognize. These might need to be added to later, | |
1906 | * as future revisions could be added. | |
1907 | */ | |
cfdfa865 MD |
1908 | SMC_SELECT_BANK(lp, 3); |
1909 | revision_register = SMC_GET_REV(lp); | |
6389aa45 | 1910 | DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register); |
1da177e4 LT |
1911 | version_string = chip_ids[ (revision_register >> 4) & 0xF]; |
1912 | if (!version_string || (revision_register & 0xff00) != 0x3300) { | |
1913 | /* I don't recognize this chip, so... */ | |
6389aa45 BB |
1914 | netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n", |
1915 | CARDNAME, ioaddr, revision_register); | |
1da177e4 LT |
1916 | |
1917 | retval = -ENODEV; | |
1918 | goto err_out; | |
1919 | } | |
1920 | ||
1921 | /* At this point I'll assume that the chip is an SMC91x. */ | |
6389aa45 | 1922 | pr_info_once("%s\n", version); |
1da177e4 LT |
1923 | |
1924 | /* fill in some of the fields */ | |
1925 | dev->base_addr = (unsigned long)ioaddr; | |
1926 | lp->base = ioaddr; | |
1927 | lp->version = revision_register & 0xff; | |
1928 | spin_lock_init(&lp->lock); | |
1929 | ||
1930 | /* Get the MAC address */ | |
cfdfa865 MD |
1931 | SMC_SELECT_BANK(lp, 1); |
1932 | SMC_GET_MAC_ADDR(lp, dev->dev_addr); | |
1da177e4 LT |
1933 | |
1934 | /* now, reset the chip, and put it into a known state */ | |
1935 | smc_reset(dev); | |
1936 | ||
1937 | /* | |
1938 | * If dev->irq is 0, then the device has to be banged on to see | |
1939 | * what the IRQ is. | |
6389aa45 | 1940 | * |
1da177e4 LT |
1941 | * This banging doesn't always detect the IRQ, for unknown reasons. |
1942 | * a workaround is to reset the chip and try again. | |
1943 | * | |
1944 | * Interestingly, the DOS packet driver *SETS* the IRQ on the card to | |
1945 | * be what is requested on the command line. I don't do that, mostly | |
1946 | * because the card that I have uses a non-standard method of accessing | |
1947 | * the IRQs, and because this _should_ work in most configurations. | |
1948 | * | |
1949 | * Specifying an IRQ is done with the assumption that the user knows | |
1950 | * what (s)he is doing. No checking is done!!!! | |
1951 | */ | |
1952 | if (dev->irq < 1) { | |
1953 | int trials; | |
1954 | ||
1955 | trials = 3; | |
1956 | while (trials--) { | |
cfdfa865 | 1957 | dev->irq = smc_findirq(lp); |
1da177e4 LT |
1958 | if (dev->irq) |
1959 | break; | |
1960 | /* kick the card and try again */ | |
1961 | smc_reset(dev); | |
1962 | } | |
1963 | } | |
1964 | if (dev->irq == 0) { | |
6389aa45 | 1965 | netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n"); |
1da177e4 LT |
1966 | retval = -ENODEV; |
1967 | goto err_out; | |
1968 | } | |
1969 | dev->irq = irq_canonicalize(dev->irq); | |
1970 | ||
1da177e4 | 1971 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
a528079e | 1972 | dev->netdev_ops = &smc_netdev_ops; |
1da177e4 | 1973 | dev->ethtool_ops = &smc_ethtool_ops; |
1da177e4 LT |
1974 | |
1975 | tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev); | |
6d5aefb8 DH |
1976 | INIT_WORK(&lp->phy_configure, smc_phy_configure); |
1977 | lp->dev = dev; | |
1da177e4 LT |
1978 | lp->mii.phy_id_mask = 0x1f; |
1979 | lp->mii.reg_num_mask = 0x1f; | |
1980 | lp->mii.force_media = 0; | |
1981 | lp->mii.full_duplex = 0; | |
1982 | lp->mii.dev = dev; | |
1983 | lp->mii.mdio_read = smc_phy_read; | |
1984 | lp->mii.mdio_write = smc_phy_write; | |
1985 | ||
1986 | /* | |
1987 | * Locate the phy, if any. | |
1988 | */ | |
1989 | if (lp->version >= (CHIP_91100 << 4)) | |
1990 | smc_phy_detect(dev); | |
1991 | ||
99e1baf8 NP |
1992 | /* then shut everything down to save power */ |
1993 | smc_shutdown(dev); | |
1994 | smc_phy_powerdown(dev); | |
1995 | ||
1da177e4 LT |
1996 | /* Set default parameters */ |
1997 | lp->msg_enable = NETIF_MSG_LINK; | |
1998 | lp->ctl_rfduplx = 0; | |
1999 | lp->ctl_rspeed = 10; | |
2000 | ||
2001 | if (lp->version >= (CHIP_91100 << 4)) { | |
2002 | lp->ctl_rfduplx = 1; | |
2003 | lp->ctl_rspeed = 100; | |
2004 | } | |
2005 | ||
2006 | /* Grab the IRQ */ | |
a0607fd3 | 2007 | retval = request_irq(dev->irq, smc_interrupt, irq_flags, dev->name, dev); |
1da177e4 LT |
2008 | if (retval) |
2009 | goto err_out; | |
2010 | ||
52256c0e EM |
2011 | #ifdef CONFIG_ARCH_PXA |
2012 | # ifdef SMC_USE_PXA_DMA | |
2013 | lp->cfg.flags |= SMC91X_USE_DMA; | |
2014 | # endif | |
2015 | if (lp->cfg.flags & SMC91X_USE_DMA) { | |
1da177e4 LT |
2016 | int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW, |
2017 | smc_pxa_dma_irq, NULL); | |
2018 | if (dma >= 0) | |
2019 | dev->dma = dma; | |
2020 | } | |
2021 | #endif | |
2022 | ||
2023 | retval = register_netdev(dev); | |
2024 | if (retval == 0) { | |
2025 | /* now, print out the card info, in a short format.. */ | |
6389aa45 BB |
2026 | netdev_info(dev, "%s (rev %d) at %p IRQ %d", |
2027 | version_string, revision_register & 0x0f, | |
2028 | lp->base, dev->irq); | |
1da177e4 LT |
2029 | |
2030 | if (dev->dma != (unsigned char)-1) | |
6389aa45 | 2031 | pr_cont(" DMA %d", dev->dma); |
1da177e4 | 2032 | |
6389aa45 | 2033 | pr_cont("%s%s\n", |
d6bc372e | 2034 | lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "", |
1da177e4 LT |
2035 | THROTTLE_TX_PKTS ? " [throttle_tx]" : ""); |
2036 | ||
2037 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
6389aa45 | 2038 | netdev_warn(dev, "Invalid ethernet MAC address. Please set using ifconfig\n"); |
1da177e4 LT |
2039 | } else { |
2040 | /* Print the Ethernet address */ | |
6389aa45 BB |
2041 | netdev_info(dev, "Ethernet addr: %pM\n", |
2042 | dev->dev_addr); | |
1da177e4 LT |
2043 | } |
2044 | ||
2045 | if (lp->phy_type == 0) { | |
6389aa45 | 2046 | PRINTK(dev, "No PHY found\n"); |
1da177e4 | 2047 | } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) { |
6389aa45 | 2048 | PRINTK(dev, "PHY LAN83C183 (LAN91C111 Internal)\n"); |
1da177e4 | 2049 | } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) { |
6389aa45 | 2050 | PRINTK(dev, "PHY LAN83C180\n"); |
1da177e4 LT |
2051 | } |
2052 | } | |
2053 | ||
2054 | err_out: | |
52256c0e | 2055 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
2056 | if (retval && dev->dma != (unsigned char)-1) |
2057 | pxa_free_dma(dev->dma); | |
2058 | #endif | |
2059 | return retval; | |
2060 | } | |
2061 | ||
2062 | static int smc_enable_device(struct platform_device *pdev) | |
2063 | { | |
3e947943 MD |
2064 | struct net_device *ndev = platform_get_drvdata(pdev); |
2065 | struct smc_local *lp = netdev_priv(ndev); | |
1da177e4 LT |
2066 | unsigned long flags; |
2067 | unsigned char ecor, ecsr; | |
2068 | void __iomem *addr; | |
2069 | struct resource * res; | |
2070 | ||
2071 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
2072 | if (!res) | |
2073 | return 0; | |
2074 | ||
2075 | /* | |
2076 | * Map the attribute space. This is overkill, but clean. | |
2077 | */ | |
2078 | addr = ioremap(res->start, ATTRIB_SIZE); | |
2079 | if (!addr) | |
2080 | return -ENOMEM; | |
2081 | ||
2082 | /* | |
2083 | * Reset the device. We must disable IRQs around this | |
2084 | * since a reset causes the IRQ line become active. | |
2085 | */ | |
2086 | local_irq_save(flags); | |
2087 | ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; | |
2088 | writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); | |
2089 | readb(addr + (ECOR << SMC_IO_SHIFT)); | |
2090 | ||
2091 | /* | |
2092 | * Wait 100us for the chip to reset. | |
2093 | */ | |
2094 | udelay(100); | |
2095 | ||
2096 | /* | |
2097 | * The device will ignore all writes to the enable bit while | |
2098 | * reset is asserted, even if the reset bit is cleared in the | |
2099 | * same write. Must clear reset first, then enable the device. | |
2100 | */ | |
2101 | writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); | |
2102 | writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); | |
2103 | ||
2104 | /* | |
2105 | * Set the appropriate byte/word mode. | |
2106 | */ | |
2107 | ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; | |
3e947943 | 2108 | if (!SMC_16BIT(lp)) |
09779c6d | 2109 | ecsr |= ECSR_IOIS8; |
1da177e4 LT |
2110 | writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); |
2111 | local_irq_restore(flags); | |
2112 | ||
2113 | iounmap(addr); | |
2114 | ||
2115 | /* | |
2116 | * Wait for the chip to wake up. We could poll the control | |
2117 | * register in the main register space, but that isn't mapped | |
2118 | * yet. We know this is going to take 750us. | |
2119 | */ | |
2120 | msleep(1); | |
2121 | ||
2122 | return 0; | |
2123 | } | |
2124 | ||
15919886 EM |
2125 | static int smc_request_attrib(struct platform_device *pdev, |
2126 | struct net_device *ndev) | |
1da177e4 LT |
2127 | { |
2128 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
55c8eb6c | 2129 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
1da177e4 LT |
2130 | |
2131 | if (!res) | |
2132 | return 0; | |
2133 | ||
2134 | if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME)) | |
2135 | return -EBUSY; | |
2136 | ||
2137 | return 0; | |
2138 | } | |
2139 | ||
15919886 EM |
2140 | static void smc_release_attrib(struct platform_device *pdev, |
2141 | struct net_device *ndev) | |
1da177e4 LT |
2142 | { |
2143 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); | |
55c8eb6c | 2144 | struct smc_local *lp __maybe_unused = netdev_priv(ndev); |
1da177e4 LT |
2145 | |
2146 | if (res) | |
2147 | release_mem_region(res->start, ATTRIB_SIZE); | |
2148 | } | |
2149 | ||
09779c6d | 2150 | static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev) |
1da177e4 | 2151 | { |
09779c6d NP |
2152 | if (SMC_CAN_USE_DATACS) { |
2153 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); | |
2154 | struct smc_local *lp = netdev_priv(ndev); | |
1da177e4 | 2155 | |
09779c6d NP |
2156 | if (!res) |
2157 | return; | |
1da177e4 | 2158 | |
09779c6d | 2159 | if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) { |
6389aa45 BB |
2160 | netdev_info(ndev, "%s: failed to request datacs memory region.\n", |
2161 | CARDNAME); | |
09779c6d NP |
2162 | return; |
2163 | } | |
1da177e4 | 2164 | |
09779c6d NP |
2165 | lp->datacs = ioremap(res->start, SMC_DATA_EXTENT); |
2166 | } | |
1da177e4 LT |
2167 | } |
2168 | ||
2169 | static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev) | |
2170 | { | |
09779c6d NP |
2171 | if (SMC_CAN_USE_DATACS) { |
2172 | struct smc_local *lp = netdev_priv(ndev); | |
2173 | struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32"); | |
1da177e4 | 2174 | |
09779c6d NP |
2175 | if (lp->datacs) |
2176 | iounmap(lp->datacs); | |
1da177e4 | 2177 | |
09779c6d | 2178 | lp->datacs = NULL; |
1da177e4 | 2179 | |
09779c6d NP |
2180 | if (res) |
2181 | release_mem_region(res->start, SMC_DATA_EXTENT); | |
2182 | } | |
1da177e4 | 2183 | } |
1da177e4 | 2184 | |
3f823c15 TL |
2185 | #if IS_BUILTIN(CONFIG_OF) |
2186 | static const struct of_device_id smc91x_match[] = { | |
2187 | { .compatible = "smsc,lan91c94", }, | |
2188 | { .compatible = "smsc,lan91c111", }, | |
2189 | {}, | |
2190 | }; | |
2191 | MODULE_DEVICE_TABLE(of, smc91x_match); | |
7d2911c4 TL |
2192 | |
2193 | /** | |
2194 | * of_try_set_control_gpio - configure a gpio if it exists | |
2195 | */ | |
2196 | static int try_toggle_control_gpio(struct device *dev, | |
2197 | struct gpio_desc **desc, | |
2198 | const char *name, int index, | |
2199 | int value, unsigned int nsdelay) | |
2200 | { | |
2201 | struct gpio_desc *gpio = *desc; | |
2202 | int res; | |
2203 | ||
2204 | gpio = devm_gpiod_get_index(dev, name, index); | |
2205 | if (IS_ERR(gpio)) { | |
2206 | if (PTR_ERR(gpio) == -ENOENT) { | |
2207 | *desc = NULL; | |
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | return PTR_ERR(gpio); | |
2212 | } | |
2213 | res = gpiod_direction_output(gpio, !value); | |
2214 | if (res) { | |
2215 | dev_err(dev, "unable to toggle gpio %s: %i\n", name, res); | |
2216 | devm_gpiod_put(dev, gpio); | |
2217 | gpio = NULL; | |
2218 | return res; | |
2219 | } | |
2220 | if (nsdelay) | |
2221 | usleep_range(nsdelay, 2 * nsdelay); | |
2222 | gpiod_set_value_cansleep(gpio, value); | |
2223 | *desc = gpio; | |
2224 | ||
2225 | return 0; | |
2226 | } | |
3f823c15 TL |
2227 | #endif |
2228 | ||
1da177e4 LT |
2229 | /* |
2230 | * smc_init(void) | |
2231 | * Input parameters: | |
2232 | * dev->base_addr == 0, try to find all possible locations | |
2233 | * dev->base_addr > 0x1ff, this is the address to check | |
2234 | * dev->base_addr == <anything else>, return failure code | |
2235 | * | |
2236 | * Output: | |
2237 | * 0 --> there is a device | |
2238 | * anything else, error | |
2239 | */ | |
1e48fea4 | 2240 | static int smc_drv_probe(struct platform_device *pdev) |
1da177e4 | 2241 | { |
f64deaca | 2242 | struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); |
3f823c15 | 2243 | const struct of_device_id *match = NULL; |
3e947943 | 2244 | struct smc_local *lp; |
1da177e4 | 2245 | struct net_device *ndev; |
e7b3dc7e | 2246 | struct resource *res, *ires; |
1da177e4 | 2247 | unsigned int __iomem *addr; |
d280eadc | 2248 | unsigned long irq_flags = SMC_IRQ_FLAGS; |
1da177e4 LT |
2249 | int ret; |
2250 | ||
1da177e4 LT |
2251 | ndev = alloc_etherdev(sizeof(struct smc_local)); |
2252 | if (!ndev) { | |
1da177e4 | 2253 | ret = -ENOMEM; |
15919886 | 2254 | goto out; |
1da177e4 | 2255 | } |
3ae5eaec | 2256 | SET_NETDEV_DEV(ndev, &pdev->dev); |
1da177e4 | 2257 | |
3e947943 MD |
2258 | /* get configuration from platform data, only allow use of |
2259 | * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set. | |
2260 | */ | |
2261 | ||
2262 | lp = netdev_priv(ndev); | |
3f823c15 | 2263 | lp->cfg.flags = 0; |
3e947943 | 2264 | |
15919886 | 2265 | if (pd) { |
3e947943 | 2266 | memcpy(&lp->cfg, pd, sizeof(lp->cfg)); |
15919886 | 2267 | lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags); |
3f823c15 TL |
2268 | } |
2269 | ||
2270 | #if IS_BUILTIN(CONFIG_OF) | |
2271 | match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); | |
2272 | if (match) { | |
2273 | struct device_node *np = pdev->dev.of_node; | |
2274 | u32 val; | |
2275 | ||
7d2911c4 TL |
2276 | /* Optional pwrdwn GPIO configured? */ |
2277 | ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, | |
2278 | "power", 0, 0, 100); | |
2279 | if (ret) | |
2280 | return ret; | |
2281 | ||
2282 | /* | |
2283 | * Optional reset GPIO configured? Minimum 100 ns reset needed | |
2284 | * according to LAN91C96 datasheet page 14. | |
2285 | */ | |
2286 | ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, | |
2287 | "reset", 0, 0, 100); | |
2288 | if (ret) | |
2289 | return ret; | |
2290 | ||
2291 | /* | |
2292 | * Need to wait for optional EEPROM to load, max 750 us according | |
2293 | * to LAN91C96 datasheet page 55. | |
2294 | */ | |
2295 | if (lp->reset_gpio) | |
2296 | usleep_range(750, 1000); | |
2297 | ||
3f823c15 TL |
2298 | /* Combination of IO widths supported, default to 16-bit */ |
2299 | if (!of_property_read_u32(np, "reg-io-width", &val)) { | |
2300 | if (val & 1) | |
2301 | lp->cfg.flags |= SMC91X_USE_8BIT; | |
2302 | if ((val == 0) || (val & 2)) | |
2303 | lp->cfg.flags |= SMC91X_USE_16BIT; | |
2304 | if (val & 4) | |
2305 | lp->cfg.flags |= SMC91X_USE_32BIT; | |
2306 | } else { | |
2307 | lp->cfg.flags |= SMC91X_USE_16BIT; | |
2308 | } | |
2309 | } | |
2310 | #endif | |
2311 | ||
2312 | if (!pd && !match) { | |
fa6d3be0 EM |
2313 | lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0; |
2314 | lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0; | |
2315 | lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0; | |
c4f0e767 | 2316 | lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0; |
3e947943 MD |
2317 | } |
2318 | ||
b0dbcf51 RK |
2319 | if (!lp->cfg.leda && !lp->cfg.ledb) { |
2320 | lp->cfg.leda = RPC_LSA_DEFAULT; | |
2321 | lp->cfg.ledb = RPC_LSB_DEFAULT; | |
2322 | } | |
2323 | ||
1da177e4 | 2324 | ndev->dma = (unsigned char)-1; |
e7b3dc7e | 2325 | |
15919886 EM |
2326 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); |
2327 | if (!res) | |
2328 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2329 | if (!res) { | |
2330 | ret = -ENODEV; | |
2331 | goto out_free_netdev; | |
2332 | } | |
2333 | ||
2334 | ||
2335 | if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) { | |
2336 | ret = -EBUSY; | |
2337 | goto out_free_netdev; | |
2338 | } | |
2339 | ||
e7b3dc7e RK |
2340 | ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2341 | if (!ires) { | |
48944738 | 2342 | ret = -ENODEV; |
15919886 | 2343 | goto out_release_io; |
48944738 | 2344 | } |
1da177e4 | 2345 | |
e7b3dc7e | 2346 | ndev->irq = ires->start; |
d280eadc | 2347 | |
d5ccd67b | 2348 | if (irq_flags == -1 || ires->flags & IRQF_TRIGGER_MASK) |
d280eadc | 2349 | irq_flags = ires->flags & IRQF_TRIGGER_MASK; |
e7b3dc7e | 2350 | |
15919886 | 2351 | ret = smc_request_attrib(pdev, ndev); |
1da177e4 | 2352 | if (ret) |
15919886 | 2353 | goto out_release_io; |
1da177e4 | 2354 | #if defined(CONFIG_SA1100_ASSABET) |
6ad1b614 | 2355 | neponset_ncr_set(NCR_ENET_OSC_EN); |
1da177e4 | 2356 | #endif |
3e947943 | 2357 | platform_set_drvdata(pdev, ndev); |
1da177e4 LT |
2358 | ret = smc_enable_device(pdev); |
2359 | if (ret) | |
2360 | goto out_release_attrib; | |
2361 | ||
2362 | addr = ioremap(res->start, SMC_IO_EXTENT); | |
2363 | if (!addr) { | |
2364 | ret = -ENOMEM; | |
2365 | goto out_release_attrib; | |
2366 | } | |
2367 | ||
52256c0e | 2368 | #ifdef CONFIG_ARCH_PXA |
073ac8fd | 2369 | { |
1da177e4 | 2370 | struct smc_local *lp = netdev_priv(ndev); |
073ac8fd | 2371 | lp->device = &pdev->dev; |
1da177e4 LT |
2372 | lp->physaddr = res->start; |
2373 | } | |
2374 | #endif | |
2375 | ||
d280eadc | 2376 | ret = smc_probe(ndev, addr, irq_flags); |
073ac8fd RK |
2377 | if (ret != 0) |
2378 | goto out_iounmap; | |
2379 | ||
1da177e4 LT |
2380 | smc_request_datacs(pdev, ndev); |
2381 | ||
2382 | return 0; | |
2383 | ||
2384 | out_iounmap: | |
1da177e4 LT |
2385 | iounmap(addr); |
2386 | out_release_attrib: | |
15919886 | 2387 | smc_release_attrib(pdev, ndev); |
1da177e4 LT |
2388 | out_release_io: |
2389 | release_mem_region(res->start, SMC_IO_EXTENT); | |
15919886 EM |
2390 | out_free_netdev: |
2391 | free_netdev(ndev); | |
1da177e4 | 2392 | out: |
6389aa45 | 2393 | pr_info("%s: not found (%d).\n", CARDNAME, ret); |
1da177e4 LT |
2394 | |
2395 | return ret; | |
2396 | } | |
2397 | ||
1e48fea4 | 2398 | static int smc_drv_remove(struct platform_device *pdev) |
1da177e4 | 2399 | { |
3ae5eaec | 2400 | struct net_device *ndev = platform_get_drvdata(pdev); |
1da177e4 LT |
2401 | struct smc_local *lp = netdev_priv(ndev); |
2402 | struct resource *res; | |
2403 | ||
1da177e4 LT |
2404 | unregister_netdev(ndev); |
2405 | ||
2406 | free_irq(ndev->irq, ndev); | |
2407 | ||
52256c0e | 2408 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
2409 | if (ndev->dma != (unsigned char)-1) |
2410 | pxa_free_dma(ndev->dma); | |
2411 | #endif | |
2412 | iounmap(lp->base); | |
2413 | ||
2414 | smc_release_datacs(pdev,ndev); | |
15919886 | 2415 | smc_release_attrib(pdev,ndev); |
1da177e4 LT |
2416 | |
2417 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); | |
2418 | if (!res) | |
6fc30db5 | 2419 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1da177e4 LT |
2420 | release_mem_region(res->start, SMC_IO_EXTENT); |
2421 | ||
2422 | free_netdev(ndev); | |
2423 | ||
2424 | return 0; | |
2425 | } | |
2426 | ||
9f950f72 | 2427 | static int smc_drv_suspend(struct device *dev) |
1da177e4 | 2428 | { |
9f950f72 KH |
2429 | struct platform_device *pdev = to_platform_device(dev); |
2430 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1da177e4 | 2431 | |
9480e307 | 2432 | if (ndev) { |
1da177e4 LT |
2433 | if (netif_running(ndev)) { |
2434 | netif_device_detach(ndev); | |
2435 | smc_shutdown(ndev); | |
2436 | smc_phy_powerdown(ndev); | |
2437 | } | |
2438 | } | |
2439 | return 0; | |
2440 | } | |
2441 | ||
9f950f72 | 2442 | static int smc_drv_resume(struct device *dev) |
1da177e4 | 2443 | { |
9f950f72 KH |
2444 | struct platform_device *pdev = to_platform_device(dev); |
2445 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1da177e4 | 2446 | |
9480e307 | 2447 | if (ndev) { |
1da177e4 | 2448 | struct smc_local *lp = netdev_priv(ndev); |
5fc34413 | 2449 | smc_enable_device(pdev); |
1da177e4 LT |
2450 | if (netif_running(ndev)) { |
2451 | smc_reset(ndev); | |
2452 | smc_enable(ndev); | |
2453 | if (lp->phy_type != 0) | |
6d5aefb8 | 2454 | smc_phy_configure(&lp->phy_configure); |
1da177e4 LT |
2455 | netif_device_attach(ndev); |
2456 | } | |
2457 | } | |
2458 | return 0; | |
2459 | } | |
2460 | ||
9f950f72 KH |
2461 | static struct dev_pm_ops smc_drv_pm_ops = { |
2462 | .suspend = smc_drv_suspend, | |
2463 | .resume = smc_drv_resume, | |
2464 | }; | |
2465 | ||
3ae5eaec | 2466 | static struct platform_driver smc_driver = { |
1da177e4 | 2467 | .probe = smc_drv_probe, |
1e48fea4 | 2468 | .remove = smc_drv_remove, |
3ae5eaec RK |
2469 | .driver = { |
2470 | .name = CARDNAME, | |
72abb461 | 2471 | .owner = THIS_MODULE, |
9f950f72 | 2472 | .pm = &smc_drv_pm_ops, |
89ce376c | 2473 | .of_match_table = of_match_ptr(smc91x_match), |
3ae5eaec | 2474 | }, |
1da177e4 LT |
2475 | }; |
2476 | ||
db62f684 | 2477 | module_platform_driver(smc_driver); |