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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
0ab75ae8 | 21 | . along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
22 | . |
23 | . Information contained in this file was obtained from the LAN91C111 | |
24 | . manual from SMC. To get a copy, if you really want one, you can find | |
25 | . information under www.smsc.com. | |
26 | . | |
27 | . Authors | |
28 | . Erik Stahlman <erik@vt.edu> | |
29 | . Daris A Nevil <dnevil@snmc.com> | |
2f82af08 | 30 | . Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
31 | . |
32 | ---------------------------------------------------------------------------*/ | |
33 | #ifndef _SMC91X_H_ | |
34 | #define _SMC91X_H_ | |
35 | ||
d24c8f24 | 36 | #include <linux/dmaengine.h> |
3e947943 | 37 | #include <linux/smc91x.h> |
1da177e4 | 38 | |
2fb04fdf RK |
39 | /* |
40 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
41 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
42 | */ | |
43 | #define SMC_outw_b(x, a, r) \ | |
44 | do { \ | |
45 | unsigned int __val16 = (x); \ | |
46 | unsigned int __reg = (r); \ | |
47 | SMC_outb(__val16, a, __reg); \ | |
48 | SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \ | |
49 | } while (0) | |
50 | ||
51 | #define SMC_inw_b(a, r) \ | |
52 | ({ \ | |
53 | unsigned int __val16; \ | |
54 | unsigned int __reg = r; \ | |
55 | __val16 = SMC_inb(a, __reg); \ | |
56 | __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
57 | __val16; \ | |
58 | }) | |
59 | ||
1da177e4 LT |
60 | /* |
61 | * Define your architecture specific bus configuration parameters here. | |
62 | */ | |
63 | ||
b70661c7 | 64 | #if defined(CONFIG_ARM) |
1da177e4 | 65 | |
25c07e2c RJ |
66 | #include <asm/mach-types.h> |
67 | ||
38fd6c38 EM |
68 | /* Now the bus width is specified in the platform data |
69 | * pretend here to support all I/O access types | |
70 | */ | |
71 | #define SMC_CAN_USE_8BIT 1 | |
1da177e4 | 72 | #define SMC_CAN_USE_16BIT 1 |
38fd6c38 | 73 | #define SMC_CAN_USE_32BIT 1 |
1da177e4 LT |
74 | #define SMC_NOWAIT 1 |
75 | ||
3aed74cd | 76 | #define SMC_IO_SHIFT (lp->io_shift) |
1da177e4 | 77 | |
38fd6c38 | 78 | #define SMC_inb(a, r) readb((a) + (r)) |
2fb04fdf RK |
79 | #define SMC_inw(a, r) \ |
80 | ({ \ | |
81 | unsigned int __smc_r = r; \ | |
82 | SMC_16BIT(lp) ? readw((a) + __smc_r) : \ | |
83 | SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \ | |
84 | ({ BUG(); 0; }); \ | |
85 | }) | |
86 | ||
38fd6c38 EM |
87 | #define SMC_inl(a, r) readl((a) + (r)) |
88 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
d09d747a | 89 | #define SMC_outw(lp, v, a, r) \ |
2fb04fdf RK |
90 | do { \ |
91 | unsigned int __v = v, __smc_r = r; \ | |
92 | if (SMC_16BIT(lp)) \ | |
d09d747a | 93 | __SMC_outw(lp, __v, a, __smc_r); \ |
2fb04fdf RK |
94 | else if (SMC_8BIT(lp)) \ |
95 | SMC_outw_b(__v, a, __smc_r); \ | |
96 | else \ | |
97 | BUG(); \ | |
98 | } while (0) | |
99 | ||
38fd6c38 | 100 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) |
2fb04fdf RK |
101 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, l) |
102 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l) | |
1da177e4 LT |
103 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
104 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
38fd6c38 EM |
105 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
106 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 107 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 108 | |
38fd6c38 | 109 | /* We actually can't write halfwords properly if not word aligned */ |
d09d747a RJ |
110 | static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg, |
111 | bool use_align4_workaround) | |
38fd6c38 | 112 | { |
d09d747a | 113 | if (use_align4_workaround) { |
1da177e4 LT |
114 | unsigned int v = val << 16; |
115 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
116 | writel(v, ioaddr + (reg & ~2)); | |
117 | } else { | |
118 | writew(val, ioaddr + reg); | |
119 | } | |
120 | } | |
121 | ||
d09d747a RJ |
122 | #define __SMC_outw(lp, v, a, r) \ |
123 | _SMC_outw_align4((v), (a), (r), \ | |
124 | IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) && \ | |
125 | (lp)->cfg.pxa_u16_align4) | |
126 | ||
127 | ||
1da177e4 LT |
128 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
129 | ||
130 | #define SMC_CAN_USE_8BIT 0 | |
131 | #define SMC_CAN_USE_16BIT 1 | |
132 | #define SMC_CAN_USE_32BIT 0 | |
133 | ||
134 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
135 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
136 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
137 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
d09d747a | 138 | #define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000) |
1da177e4 LT |
139 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) |
140 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
141 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
142 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
143 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
144 | ||
9ded96f2 | 145 | #define SMC_IRQ_FLAGS (0) |
1da177e4 | 146 | |
1da177e4 LT |
147 | #elif defined(CONFIG_M32R) |
148 | ||
149 | #define SMC_CAN_USE_8BIT 0 | |
150 | #define SMC_CAN_USE_16BIT 1 | |
151 | #define SMC_CAN_USE_32BIT 0 | |
152 | ||
59dc76a4 | 153 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
154 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
155 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
d09d747a | 156 | #define SMC_outw(lp, v, a, r) outw(v, ((u32)a) + (r)) |
f3ac9fbf HT |
157 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) |
158 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 159 | |
9ded96f2 | 160 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
161 | |
162 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
163 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
164 | ||
b920de1b DH |
165 | #elif defined(CONFIG_MN10300) |
166 | ||
167 | /* | |
168 | * MN10300/AM33 configuration | |
169 | */ | |
170 | ||
2f2a2132 | 171 | #include <unit/smc91111.h> |
b920de1b | 172 | |
6321b54a MS |
173 | #elif defined(CONFIG_ATARI) |
174 | ||
175 | #define SMC_CAN_USE_8BIT 1 | |
176 | #define SMC_CAN_USE_16BIT 1 | |
177 | #define SMC_CAN_USE_32BIT 1 | |
178 | #define SMC_NOWAIT 1 | |
179 | ||
180 | #define SMC_inb(a, r) readb((a) + (r)) | |
181 | #define SMC_inw(a, r) readw((a) + (r)) | |
182 | #define SMC_inl(a, r) readl((a) + (r)) | |
183 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
d09d747a | 184 | #define SMC_outw(lp, v, a, r) writew(v, (a) + (r)) |
6321b54a MS |
185 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) |
186 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
187 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
188 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
189 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
190 | ||
191 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
192 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
193 | ||
717ea4b3 GU |
194 | #elif defined(CONFIG_COLDFIRE) |
195 | ||
196 | #define SMC_CAN_USE_8BIT 0 | |
197 | #define SMC_CAN_USE_16BIT 1 | |
198 | #define SMC_CAN_USE_32BIT 0 | |
199 | #define SMC_NOWAIT 1 | |
200 | ||
201 | static inline void mcf_insw(void *a, unsigned char *p, int l) | |
202 | { | |
203 | u16 *wp = (u16 *) p; | |
204 | while (l-- > 0) | |
205 | *wp++ = readw(a); | |
206 | } | |
207 | ||
208 | static inline void mcf_outsw(void *a, unsigned char *p, int l) | |
209 | { | |
210 | u16 *wp = (u16 *) p; | |
211 | while (l-- > 0) | |
212 | writew(*wp++, a); | |
213 | } | |
214 | ||
215 | #define SMC_inw(a, r) _swapw(readw((a) + (r))) | |
d09d747a | 216 | #define SMC_outw(lp, v, a, r) writew(_swapw(v), (a) + (r)) |
717ea4b3 GU |
217 | #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) |
218 | #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) | |
219 | ||
cf68ca1e | 220 | #define SMC_IRQ_FLAGS 0 |
717ea4b3 | 221 | |
f147d0b3 YS |
222 | #elif defined(CONFIG_H8300) |
223 | #define SMC_CAN_USE_8BIT 1 | |
224 | #define SMC_CAN_USE_16BIT 0 | |
225 | #define SMC_CAN_USE_32BIT 0 | |
226 | #define SMC_NOWAIT 0 | |
227 | ||
228 | #define SMC_inb(a, r) ioread8((a) + (r)) | |
229 | #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) | |
230 | #define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l) | |
231 | #define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l) | |
232 | ||
1da177e4 LT |
233 | #else |
234 | ||
b920de1b DH |
235 | /* |
236 | * Default configuration | |
237 | */ | |
238 | ||
1da177e4 LT |
239 | #define SMC_CAN_USE_8BIT 1 |
240 | #define SMC_CAN_USE_16BIT 1 | |
241 | #define SMC_CAN_USE_32BIT 1 | |
242 | #define SMC_NOWAIT 1 | |
243 | ||
d1c5ea33 MD |
244 | #define SMC_IO_SHIFT (lp->io_shift) |
245 | ||
4ba73aa1 WD |
246 | #define SMC_inb(a, r) ioread8((a) + (r)) |
247 | #define SMC_inw(a, r) ioread16((a) + (r)) | |
248 | #define SMC_inl(a, r) ioread32((a) + (r)) | |
249 | #define SMC_outb(v, a, r) iowrite8(v, (a) + (r)) | |
d09d747a | 250 | #define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r)) |
4ba73aa1 WD |
251 | #define SMC_outl(v, a, r) iowrite32(v, (a) + (r)) |
252 | #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l) | |
253 | #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l) | |
254 | #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l) | |
255 | #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l) | |
1da177e4 LT |
256 | |
257 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
258 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
259 | ||
260 | #endif | |
261 | ||
073ac8fd RK |
262 | |
263 | /* store this information for the driver.. */ | |
264 | struct smc_local { | |
265 | /* | |
266 | * If I have to wait until memory is available to send a | |
267 | * packet, I will store the skbuff here, until I get the | |
268 | * desired memory. Then, I'll send it out and free it. | |
269 | */ | |
270 | struct sk_buff *pending_tx_skb; | |
271 | struct tasklet_struct tx_task; | |
272 | ||
7d2911c4 TL |
273 | struct gpio_desc *power_gpio; |
274 | struct gpio_desc *reset_gpio; | |
275 | ||
073ac8fd RK |
276 | /* version/revision of the SMC91x chip */ |
277 | int version; | |
278 | ||
279 | /* Contains the current active transmission mode */ | |
280 | int tcr_cur_mode; | |
281 | ||
282 | /* Contains the current active receive mode */ | |
283 | int rcr_cur_mode; | |
284 | ||
285 | /* Contains the current active receive/phy mode */ | |
286 | int rpc_cur_mode; | |
287 | int ctl_rfduplx; | |
288 | int ctl_rspeed; | |
289 | ||
290 | u32 msg_enable; | |
291 | u32 phy_type; | |
292 | struct mii_if_info mii; | |
293 | ||
294 | /* work queue */ | |
295 | struct work_struct phy_configure; | |
296 | struct net_device *dev; | |
297 | int work_pending; | |
298 | ||
299 | spinlock_t lock; | |
300 | ||
52256c0e | 301 | #ifdef CONFIG_ARCH_PXA |
073ac8fd RK |
302 | /* DMA needs the physical address of the chip */ |
303 | u_long physaddr; | |
304 | struct device *device; | |
305 | #endif | |
d24c8f24 | 306 | struct dma_chan *dma_chan; |
073ac8fd RK |
307 | void __iomem *base; |
308 | void __iomem *datacs; | |
3e947943 | 309 | |
15919886 EM |
310 | /* the low address lines on some platforms aren't connected... */ |
311 | int io_shift; | |
d09d747a RJ |
312 | /* on some platforms a u16 write must be 4-bytes aligned */ |
313 | bool half_word_align4; | |
15919886 | 314 | |
3e947943 | 315 | struct smc91x_platdata cfg; |
073ac8fd RK |
316 | }; |
317 | ||
fa6d3be0 EM |
318 | #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) |
319 | #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) | |
320 | #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) | |
073ac8fd | 321 | |
52256c0e | 322 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
323 | /* |
324 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
325 | * always happening in irq context so no need to worry about races. TX is | |
326 | * different and probably not worth it for that reason, and not as critical | |
327 | * as RX which can overrun memory and lose packets. | |
328 | */ | |
329 | #include <linux/dma-mapping.h> | |
d24c8f24 | 330 | #include <linux/dma/pxa-dma.h> |
1da177e4 LT |
331 | |
332 | #ifdef SMC_insl | |
333 | #undef SMC_insl | |
334 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 335 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
d24c8f24 RJ |
336 | static inline void |
337 | smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len) | |
338 | { | |
339 | dma_addr_t dmabuf; | |
340 | struct dma_async_tx_descriptor *tx; | |
341 | dma_cookie_t cookie; | |
342 | enum dma_status status; | |
343 | struct dma_tx_state state; | |
344 | ||
345 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); | |
346 | tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len, | |
347 | DMA_DEV_TO_MEM, 0); | |
348 | if (tx) { | |
349 | cookie = dmaengine_submit(tx); | |
350 | dma_async_issue_pending(lp->dma_chan); | |
351 | do { | |
352 | status = dmaengine_tx_status(lp->dma_chan, cookie, | |
353 | &state); | |
354 | cpu_relax(); | |
355 | } while (status != DMA_COMPLETE && status != DMA_ERROR && | |
356 | state.residue); | |
357 | dmaengine_terminate_all(lp->dma_chan); | |
358 | } | |
359 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); | |
360 | } | |
361 | ||
1da177e4 | 362 | static inline void |
073ac8fd | 363 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
364 | u_char *buf, int len) |
365 | { | |
d24c8f24 RJ |
366 | struct dma_slave_config config; |
367 | int ret; | |
1da177e4 LT |
368 | |
369 | /* fallback if no DMA available */ | |
d24c8f24 | 370 | if (!lp->dma_chan) { |
1da177e4 LT |
371 | readsl(ioaddr + reg, buf, len); |
372 | return; | |
373 | } | |
374 | ||
375 | /* 64 bit alignment is required for memory to memory DMA */ | |
376 | if ((long)buf & 4) { | |
377 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
378 | buf += 4; | |
379 | len--; | |
380 | } | |
381 | ||
d24c8f24 RJ |
382 | memset(&config, 0, sizeof(config)); |
383 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
384 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
385 | config.src_addr = lp->physaddr + reg; | |
386 | config.dst_addr = lp->physaddr + reg; | |
387 | config.src_maxburst = 32; | |
388 | config.dst_maxburst = 32; | |
389 | ret = dmaengine_slave_config(lp->dma_chan, &config); | |
390 | if (ret) { | |
391 | dev_err(lp->device, "dma channel configuration failed: %d\n", | |
392 | ret); | |
393 | return; | |
394 | } | |
395 | ||
1da177e4 | 396 | len *= 4; |
d24c8f24 | 397 | smc_pxa_dma_inpump(lp, buf, len); |
1da177e4 LT |
398 | } |
399 | #endif | |
400 | ||
401 | #ifdef SMC_insw | |
402 | #undef SMC_insw | |
403 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 404 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 405 | static inline void |
073ac8fd | 406 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
407 | u_char *buf, int len) |
408 | { | |
d24c8f24 RJ |
409 | struct dma_slave_config config; |
410 | int ret; | |
1da177e4 LT |
411 | |
412 | /* fallback if no DMA available */ | |
d24c8f24 | 413 | if (!lp->dma_chan) { |
1da177e4 LT |
414 | readsw(ioaddr + reg, buf, len); |
415 | return; | |
416 | } | |
417 | ||
418 | /* 64 bit alignment is required for memory to memory DMA */ | |
419 | while ((long)buf & 6) { | |
420 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
421 | buf += 2; | |
422 | len--; | |
423 | } | |
424 | ||
d24c8f24 RJ |
425 | memset(&config, 0, sizeof(config)); |
426 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
427 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
428 | config.src_addr = lp->physaddr + reg; | |
429 | config.dst_addr = lp->physaddr + reg; | |
430 | config.src_maxburst = 32; | |
431 | config.dst_maxburst = 32; | |
432 | ret = dmaengine_slave_config(lp->dma_chan, &config); | |
433 | if (ret) { | |
434 | dev_err(lp->device, "dma channel configuration failed: %d\n", | |
435 | ret); | |
436 | return; | |
437 | } | |
438 | ||
1da177e4 | 439 | len *= 2; |
d24c8f24 | 440 | smc_pxa_dma_inpump(lp, buf, len); |
1da177e4 LT |
441 | } |
442 | #endif | |
443 | ||
52256c0e | 444 | #endif /* CONFIG_ARCH_PXA */ |
1da177e4 LT |
445 | |
446 | ||
09779c6d NP |
447 | /* |
448 | * Everything a particular hardware setup needs should have been defined | |
449 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
450 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
451 | * use of them. | |
452 | */ | |
453 | ||
454 | #if ! SMC_CAN_USE_32BIT | |
455 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
456 | #define SMC_outl(x, ioaddr, reg) BUG() | |
457 | #define SMC_insl(a, r, p, l) BUG() | |
458 | #define SMC_outsl(a, r, p, l) BUG() | |
459 | #endif | |
460 | ||
461 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
462 | #define SMC_insl(a, r, p, l) BUG() | |
463 | #define SMC_outsl(a, r, p, l) BUG() | |
464 | #endif | |
465 | ||
466 | #if ! SMC_CAN_USE_16BIT | |
467 | ||
d09d747a | 468 | #define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg) |
2fb04fdf | 469 | #define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg) |
09779c6d NP |
470 | #define SMC_insw(a, r, p, l) BUG() |
471 | #define SMC_outsw(a, r, p, l) BUG() | |
472 | ||
473 | #endif | |
474 | ||
475 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
476 | #define SMC_insw(a, r, p, l) BUG() | |
477 | #define SMC_outsw(a, r, p, l) BUG() | |
478 | #endif | |
479 | ||
480 | #if ! SMC_CAN_USE_8BIT | |
daa7ee8d | 481 | #undef SMC_inb |
09779c6d | 482 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) |
daa7ee8d | 483 | #undef SMC_outb |
09779c6d NP |
484 | #define SMC_outb(x, ioaddr, reg) BUG() |
485 | #define SMC_insb(a, r, p, l) BUG() | |
486 | #define SMC_outsb(a, r, p, l) BUG() | |
487 | #endif | |
488 | ||
489 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
490 | #define SMC_insb(a, r, p, l) BUG() | |
491 | #define SMC_outsb(a, r, p, l) BUG() | |
492 | #endif | |
493 | ||
494 | #ifndef SMC_CAN_USE_DATACS | |
495 | #define SMC_CAN_USE_DATACS 0 | |
496 | #endif | |
497 | ||
1da177e4 LT |
498 | #ifndef SMC_IO_SHIFT |
499 | #define SMC_IO_SHIFT 0 | |
500 | #endif | |
09779c6d NP |
501 | |
502 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 503 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
504 | #endif |
505 | ||
506 | #ifndef SMC_INTERRUPT_PREAMBLE | |
507 | #define SMC_INTERRUPT_PREAMBLE | |
508 | #endif | |
509 | ||
510 | ||
511 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
512 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
513 | #define SMC_DATA_EXTENT (4) | |
514 | ||
515 | /* | |
516 | . Bank Select Register: | |
517 | . | |
518 | . yyyy yyyy 0000 00xx | |
519 | . xx = bank number | |
520 | . yyyy yyyy = 0x33, for identification purposes. | |
521 | */ | |
522 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
523 | ||
524 | ||
525 | // Transmit Control Register | |
526 | /* BANK 0 */ | |
cfdfa865 | 527 | #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) |
1da177e4 LT |
528 | #define TCR_ENABLE 0x0001 // When 1 we can transmit |
529 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
530 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
531 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
532 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
533 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
534 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
535 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
536 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
537 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
538 | ||
539 | #define TCR_CLEAR 0 /* do NOTHING */ | |
540 | /* the default settings for the TCR register : */ | |
541 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
542 | ||
543 | ||
544 | // EPH Status Register | |
545 | /* BANK 0 */ | |
cfdfa865 | 546 | #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) |
1da177e4 LT |
547 | #define ES_TX_SUC 0x0001 // Last TX was successful |
548 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
549 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
550 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
551 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
552 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
553 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
554 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
555 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
556 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
557 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
558 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
559 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
560 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
561 | ||
562 | ||
563 | // Receive Control Register | |
564 | /* BANK 0 */ | |
cfdfa865 | 565 | #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) |
1da177e4 LT |
566 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted |
567 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
568 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
569 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
570 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
571 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
572 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
573 | #define RCR_SOFTRST 0x8000 // resets the chip | |
574 | ||
575 | /* the normal settings for the RCR register : */ | |
576 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
577 | #define RCR_CLEAR 0x0 // set it to a base state | |
578 | ||
579 | ||
580 | // Counter Register | |
581 | /* BANK 0 */ | |
cfdfa865 | 582 | #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) |
1da177e4 LT |
583 | |
584 | ||
585 | // Memory Information Register | |
586 | /* BANK 0 */ | |
cfdfa865 | 587 | #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) |
1da177e4 LT |
588 | |
589 | ||
590 | // Receive/Phy Control Register | |
591 | /* BANK 0 */ | |
cfdfa865 | 592 | #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) |
1da177e4 LT |
593 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. |
594 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
595 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
596 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
597 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
1da177e4 LT |
598 | |
599 | #ifndef RPC_LSA_DEFAULT | |
600 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
601 | #endif | |
602 | #ifndef RPC_LSB_DEFAULT | |
603 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
604 | #endif | |
605 | ||
b0dbcf51 | 606 | #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) |
1da177e4 LT |
607 | |
608 | ||
609 | /* Bank 0 0x0C is reserved */ | |
610 | ||
611 | // Bank Select Register | |
612 | /* All Banks */ | |
613 | #define BSR_REG 0x000E | |
614 | ||
615 | ||
616 | // Configuration Reg | |
617 | /* BANK 1 */ | |
cfdfa865 | 618 | #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) |
1da177e4 LT |
619 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy |
620 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
621 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
622 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
623 | ||
624 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
625 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
626 | ||
627 | ||
628 | // Base Address Register | |
629 | /* BANK 1 */ | |
cfdfa865 | 630 | #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) |
1da177e4 LT |
631 | |
632 | ||
633 | // Individual Address Registers | |
634 | /* BANK 1 */ | |
cfdfa865 MD |
635 | #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) |
636 | #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) | |
637 | #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) | |
1da177e4 LT |
638 | |
639 | ||
640 | // General Purpose Register | |
641 | /* BANK 1 */ | |
cfdfa865 | 642 | #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) |
1da177e4 LT |
643 | |
644 | ||
645 | // Control Register | |
646 | /* BANK 1 */ | |
cfdfa865 | 647 | #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) |
1da177e4 LT |
648 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received |
649 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
650 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
651 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
652 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
653 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
654 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
655 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
656 | ||
657 | ||
658 | // MMU Command Register | |
659 | /* BANK 2 */ | |
cfdfa865 | 660 | #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) |
1da177e4 LT |
661 | #define MC_BUSY 1 // When 1 the last release has not completed |
662 | #define MC_NOP (0<<5) // No Op | |
663 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
664 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
665 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
666 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
667 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
668 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
669 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
670 | ||
671 | ||
672 | // Packet Number Register | |
673 | /* BANK 2 */ | |
cfdfa865 | 674 | #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) |
1da177e4 LT |
675 | |
676 | ||
677 | // Allocation Result Register | |
678 | /* BANK 2 */ | |
cfdfa865 | 679 | #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) |
1da177e4 LT |
680 | #define AR_FAILED 0x80 // Alocation Failed |
681 | ||
682 | ||
683 | // TX FIFO Ports Register | |
684 | /* BANK 2 */ | |
cfdfa865 | 685 | #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
686 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty |
687 | ||
688 | // RX FIFO Ports Register | |
689 | /* BANK 2 */ | |
cfdfa865 | 690 | #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) |
1da177e4 LT |
691 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty |
692 | ||
cfdfa865 | 693 | #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
694 | |
695 | // Pointer Register | |
696 | /* BANK 2 */ | |
cfdfa865 | 697 | #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) |
1da177e4 LT |
698 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area |
699 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
700 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
701 | ||
702 | ||
703 | // Data Register | |
704 | /* BANK 2 */ | |
cfdfa865 | 705 | #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) |
1da177e4 LT |
706 | |
707 | ||
708 | // Interrupt Status/Acknowledge Register | |
709 | /* BANK 2 */ | |
cfdfa865 | 710 | #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) |
1da177e4 LT |
711 | |
712 | ||
713 | // Interrupt Mask Register | |
714 | /* BANK 2 */ | |
cfdfa865 | 715 | #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) |
1da177e4 LT |
716 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt |
717 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
718 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
719 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
720 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
721 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
722 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
723 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
724 | ||
725 | ||
726 | // Multicast Table Registers | |
727 | /* BANK 3 */ | |
cfdfa865 MD |
728 | #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) |
729 | #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) | |
730 | #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) | |
731 | #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) | |
1da177e4 LT |
732 | |
733 | ||
734 | // Management Interface Register (MII) | |
735 | /* BANK 3 */ | |
cfdfa865 | 736 | #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) |
1da177e4 LT |
737 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup |
738 | #define MII_MDOE 0x0008 // MII Output Enable | |
739 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
740 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
741 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
742 | ||
743 | ||
744 | // Revision Register | |
745 | /* BANK 3 */ | |
746 | /* ( hi: chip id low: rev # ) */ | |
cfdfa865 | 747 | #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) |
1da177e4 LT |
748 | |
749 | ||
750 | // Early RCV Register | |
751 | /* BANK 3 */ | |
752 | /* this is NOT on SMC9192 */ | |
cfdfa865 | 753 | #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) |
1da177e4 LT |
754 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received |
755 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
756 | ||
757 | ||
758 | // External Register | |
759 | /* BANK 7 */ | |
cfdfa865 | 760 | #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) |
1da177e4 LT |
761 | |
762 | ||
763 | #define CHIP_9192 3 | |
764 | #define CHIP_9194 4 | |
765 | #define CHIP_9195 5 | |
766 | #define CHIP_9196 6 | |
767 | #define CHIP_91100 7 | |
768 | #define CHIP_91100FD 8 | |
769 | #define CHIP_91111FD 9 | |
770 | ||
771 | static const char * chip_ids[ 16 ] = { | |
772 | NULL, NULL, NULL, | |
773 | /* 3 */ "SMC91C90/91C92", | |
774 | /* 4 */ "SMC91C94", | |
775 | /* 5 */ "SMC91C95", | |
776 | /* 6 */ "SMC91C96", | |
777 | /* 7 */ "SMC91C100", | |
778 | /* 8 */ "SMC91C100FD", | |
779 | /* 9 */ "SMC91C11xFD", | |
780 | NULL, NULL, NULL, | |
781 | NULL, NULL, NULL}; | |
782 | ||
783 | ||
1da177e4 LT |
784 | /* |
785 | . Receive status bits | |
786 | */ | |
787 | #define RS_ALGNERR 0x8000 | |
788 | #define RS_BRODCAST 0x4000 | |
789 | #define RS_BADCRC 0x2000 | |
790 | #define RS_ODDFRAME 0x1000 | |
791 | #define RS_TOOLONG 0x0800 | |
792 | #define RS_TOOSHORT 0x0400 | |
793 | #define RS_MULTICAST 0x0001 | |
794 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
795 | ||
796 | ||
797 | /* | |
798 | * PHY IDs | |
799 | * LAN83C183 == LAN91C111 Internal PHY | |
800 | */ | |
801 | #define PHY_LAN83C183 0x0016f840 | |
802 | #define PHY_LAN83C180 0x02821c50 | |
803 | ||
804 | /* | |
805 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
806 | * | |
807 | * Generic PHY registers can be found in <linux/mii.h> | |
808 | * | |
809 | * These phy registers are specific to our on-board phy. | |
810 | */ | |
811 | ||
812 | // PHY Configuration Register 1 | |
813 | #define PHY_CFG1_REG 0x10 | |
814 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
815 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
816 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
817 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
818 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
819 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
820 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
821 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
822 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
823 | #define PHY_CFG1_TLVL_MASK 0x003C | |
824 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
825 | ||
826 | ||
827 | // PHY Configuration Register 2 | |
828 | #define PHY_CFG2_REG 0x11 | |
829 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
830 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
831 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
832 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
833 | ||
834 | // PHY Status Output (and Interrupt status) Register | |
835 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
836 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
837 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
838 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
839 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
840 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
841 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
842 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
843 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
844 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
845 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
846 | ||
847 | // PHY Interrupt/Status Mask Register | |
848 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
849 | // Uses the same bit definitions as PHY_INT_REG | |
850 | ||
851 | ||
852 | /* | |
853 | * SMC91C96 ethernet config and status registers. | |
854 | * These are in the "attribute" space. | |
855 | */ | |
856 | #define ECOR 0x8000 | |
857 | #define ECOR_RESET 0x80 | |
858 | #define ECOR_LEVEL_IRQ 0x40 | |
859 | #define ECOR_WR_ATTRIB 0x04 | |
860 | #define ECOR_ENABLE 0x01 | |
861 | ||
862 | #define ECSR 0x8002 | |
863 | #define ECSR_IOIS8 0x20 | |
864 | #define ECSR_PWRDWN 0x04 | |
865 | #define ECSR_INT 0x02 | |
866 | ||
867 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
868 | ||
869 | ||
870 | /* | |
871 | * Macros to abstract register access according to the data bus | |
872 | * capabilities. Please use those and not the in/out primitives. | |
873 | * Note: the following macros do *not* select the bank -- this must | |
874 | * be done separately as needed in the main code. The SMC_REG() macro | |
875 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
876 | * |
877 | * Note: despite inline functions being safer, everything leading to this | |
878 | * should preferably be macros to let BUG() display the line number in | |
879 | * the core source code since we're interested in the top call site | |
880 | * not in any inline function location. | |
1da177e4 LT |
881 | */ |
882 | ||
883 | #if SMC_DEBUG > 0 | |
cfdfa865 | 884 | #define SMC_REG(lp, reg, bank) \ |
1da177e4 | 885 | ({ \ |
cfdfa865 | 886 | int __b = SMC_CURRENT_BANK(lp); \ |
1da177e4 | 887 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ |
6389aa45 BB |
888 | pr_err("%s: bank reg screwed (0x%04x)\n", \ |
889 | CARDNAME, __b); \ | |
1da177e4 LT |
890 | BUG(); \ |
891 | } \ | |
892 | reg<<SMC_IO_SHIFT; \ | |
893 | }) | |
894 | #else | |
cfdfa865 | 895 | #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) |
1da177e4 LT |
896 | #endif |
897 | ||
09779c6d NP |
898 | /* |
899 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
900 | * aligned to a 32 bit boundary. I tell you that does exist! | |
901 | * Fortunately the affected register accesses can be easily worked around | |
25985edc | 902 | * since we can write zeroes to the preceding 16 bits without adverse |
09779c6d NP |
903 | * effects and use a 32-bit access. |
904 | * | |
905 | * Enforce it on any 32-bit capable setup for now. | |
906 | */ | |
3e947943 | 907 | #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) |
09779c6d | 908 | |
cfdfa865 | 909 | #define SMC_GET_PN(lp) \ |
3e947943 | 910 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ |
cfdfa865 | 911 | : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) |
09779c6d | 912 | |
cfdfa865 | 913 | #define SMC_SET_PN(lp, x) \ |
09779c6d | 914 | do { \ |
3e947943 | 915 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 916 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ |
3e947943 | 917 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 918 | SMC_outb(x, ioaddr, PN_REG(lp)); \ |
09779c6d | 919 | else \ |
d09d747a | 920 | SMC_outw(lp, x, ioaddr, PN_REG(lp)); \ |
09779c6d NP |
921 | } while (0) |
922 | ||
cfdfa865 | 923 | #define SMC_GET_AR(lp) \ |
3e947943 | 924 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ |
cfdfa865 | 925 | : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) |
09779c6d | 926 | |
cfdfa865 | 927 | #define SMC_GET_TXFIFO(lp) \ |
3e947943 | 928 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ |
cfdfa865 | 929 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) |
09779c6d | 930 | |
cfdfa865 | 931 | #define SMC_GET_RXFIFO(lp) \ |
3e947943 | 932 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ |
cfdfa865 | 933 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) |
09779c6d | 934 | |
cfdfa865 | 935 | #define SMC_GET_INT(lp) \ |
3e947943 | 936 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ |
cfdfa865 | 937 | : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) |
09779c6d | 938 | |
cfdfa865 | 939 | #define SMC_ACK_INT(lp, x) \ |
1da177e4 | 940 | do { \ |
3e947943 | 941 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 942 | SMC_outb(x, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
943 | else { \ |
944 | unsigned long __flags; \ | |
945 | int __mask; \ | |
946 | local_irq_save(__flags); \ | |
cfdfa865 | 947 | __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ |
d09d747a | 948 | SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \ |
09779c6d NP |
949 | local_irq_restore(__flags); \ |
950 | } \ | |
951 | } while (0) | |
952 | ||
cfdfa865 | 953 | #define SMC_GET_INT_MASK(lp) \ |
3e947943 | 954 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ |
cfdfa865 | 955 | : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) |
09779c6d | 956 | |
cfdfa865 | 957 | #define SMC_SET_INT_MASK(lp, x) \ |
09779c6d | 958 | do { \ |
3e947943 | 959 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 960 | SMC_outb(x, ioaddr, IM_REG(lp)); \ |
09779c6d | 961 | else \ |
d09d747a | 962 | SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
963 | } while (0) |
964 | ||
cfdfa865 | 965 | #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) |
09779c6d | 966 | |
cfdfa865 | 967 | #define SMC_SELECT_BANK(lp, x) \ |
09779c6d | 968 | do { \ |
3e947943 | 969 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
09779c6d NP |
970 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ |
971 | else \ | |
d09d747a | 972 | SMC_outw(lp, x, ioaddr, BANK_SELECT); \ |
09779c6d NP |
973 | } while (0) |
974 | ||
cfdfa865 | 975 | #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) |
09779c6d | 976 | |
d09d747a | 977 | #define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp)) |
09779c6d | 978 | |
cfdfa865 | 979 | #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) |
09779c6d | 980 | |
d09d747a | 981 | #define SMC_SET_CONFIG(lp, x) SMC_outw(lp, x, ioaddr, CONFIG_REG(lp)) |
09779c6d | 982 | |
cfdfa865 | 983 | #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) |
09779c6d | 984 | |
cfdfa865 | 985 | #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) |
09779c6d | 986 | |
d09d747a | 987 | #define SMC_SET_CTL(lp, x) SMC_outw(lp, x, ioaddr, CTL_REG(lp)) |
09779c6d | 988 | |
cfdfa865 | 989 | #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) |
09779c6d | 990 | |
357fe2c6 VS |
991 | #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) |
992 | ||
993 | #define SMC_SET_GP(lp, x) \ | |
994 | do { \ | |
995 | if (SMC_MUST_ALIGN_WRITE(lp)) \ | |
996 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \ | |
997 | else \ | |
d09d747a | 998 | SMC_outw(lp, x, ioaddr, GP_REG(lp)); \ |
357fe2c6 VS |
999 | } while (0) |
1000 | ||
d09d747a | 1001 | #define SMC_SET_MII(lp, x) SMC_outw(lp, x, ioaddr, MII_REG(lp)) |
09779c6d | 1002 | |
cfdfa865 | 1003 | #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) |
09779c6d | 1004 | |
d09d747a | 1005 | #define SMC_SET_MIR(lp, x) SMC_outw(lp, x, ioaddr, MIR_REG(lp)) |
09779c6d | 1006 | |
cfdfa865 | 1007 | #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1008 | |
d09d747a | 1009 | #define SMC_SET_MMU_CMD(lp, x) SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1010 | |
d09d747a | 1011 | #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) |
09779c6d | 1012 | |
cfdfa865 | 1013 | #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) |
09779c6d | 1014 | |
cfdfa865 | 1015 | #define SMC_SET_PTR(lp, x) \ |
09779c6d | 1016 | do { \ |
3e947943 | 1017 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1018 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ |
09779c6d | 1019 | else \ |
d09d747a | 1020 | SMC_outw(lp, x, ioaddr, PTR_REG(lp)); \ |
1da177e4 | 1021 | } while (0) |
1da177e4 | 1022 | |
cfdfa865 | 1023 | #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) |
09779c6d | 1024 | |
cfdfa865 | 1025 | #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) |
09779c6d | 1026 | |
d09d747a | 1027 | #define SMC_SET_RCR(lp, x) SMC_outw(lp, x, ioaddr, RCR_REG(lp)) |
09779c6d | 1028 | |
cfdfa865 | 1029 | #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) |
09779c6d | 1030 | |
cfdfa865 | 1031 | #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) |
09779c6d | 1032 | |
cfdfa865 | 1033 | #define SMC_SET_RPC(lp, x) \ |
09779c6d | 1034 | do { \ |
3e947943 | 1035 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1036 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ |
09779c6d | 1037 | else \ |
d09d747a | 1038 | SMC_outw(lp, x, ioaddr, RPC_REG(lp)); \ |
09779c6d NP |
1039 | } while (0) |
1040 | ||
cfdfa865 | 1041 | #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) |
09779c6d | 1042 | |
d09d747a | 1043 | #define SMC_SET_TCR(lp, x) SMC_outw(lp, x, ioaddr, TCR_REG(lp)) |
1da177e4 LT |
1044 | |
1045 | #ifndef SMC_GET_MAC_ADDR | |
cfdfa865 | 1046 | #define SMC_GET_MAC_ADDR(lp, addr) \ |
1da177e4 LT |
1047 | do { \ |
1048 | unsigned int __v; \ | |
cfdfa865 | 1049 | __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ |
1da177e4 | 1050 | addr[0] = __v; addr[1] = __v >> 8; \ |
cfdfa865 | 1051 | __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ |
1da177e4 | 1052 | addr[2] = __v; addr[3] = __v >> 8; \ |
cfdfa865 | 1053 | __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ |
1da177e4 LT |
1054 | addr[4] = __v; addr[5] = __v >> 8; \ |
1055 | } while (0) | |
1056 | #endif | |
1057 | ||
cfdfa865 | 1058 | #define SMC_SET_MAC_ADDR(lp, addr) \ |
1da177e4 | 1059 | do { \ |
d09d747a RJ |
1060 | SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ |
1061 | SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ | |
1062 | SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ | |
1da177e4 LT |
1063 | } while (0) |
1064 | ||
cfdfa865 | 1065 | #define SMC_SET_MCAST(lp, x) \ |
1da177e4 LT |
1066 | do { \ |
1067 | const unsigned char *mt = (x); \ | |
d09d747a RJ |
1068 | SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ |
1069 | SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ | |
1070 | SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ | |
1071 | SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ | |
1da177e4 LT |
1072 | } while (0) |
1073 | ||
cfdfa865 | 1074 | #define SMC_PUT_PKT_HDR(lp, status, length) \ |
1da177e4 | 1075 | do { \ |
3e947943 | 1076 | if (SMC_32BIT(lp)) \ |
cfdfa865 MD |
1077 | SMC_outl((status) | (length)<<16, ioaddr, \ |
1078 | DATA_REG(lp)); \ | |
09779c6d | 1079 | else { \ |
d09d747a RJ |
1080 | SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \ |
1081 | SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \ | |
09779c6d | 1082 | } \ |
1da177e4 | 1083 | } while (0) |
1da177e4 | 1084 | |
cfdfa865 | 1085 | #define SMC_GET_PKT_HDR(lp, status, length) \ |
1da177e4 | 1086 | do { \ |
3e947943 | 1087 | if (SMC_32BIT(lp)) { \ |
cfdfa865 | 1088 | unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ |
09779c6d NP |
1089 | (status) = __val & 0xffff; \ |
1090 | (length) = __val >> 16; \ | |
1091 | } else { \ | |
cfdfa865 MD |
1092 | (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ |
1093 | (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ | |
1da177e4 LT |
1094 | } \ |
1095 | } while (0) | |
1da177e4 | 1096 | |
cfdfa865 | 1097 | #define SMC_PUSH_DATA(lp, p, l) \ |
1da177e4 | 1098 | do { \ |
3e947943 | 1099 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1100 | void *__ptr = (p); \ |
1101 | int __len = (l); \ | |
fbd81976 | 1102 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1103 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1104 | __len -= 2; \ | |
e9e4ea74 | 1105 | SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ |
09779c6d NP |
1106 | __ptr += 2; \ |
1107 | } \ | |
1108 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1109 | __ioaddr = lp->datacs; \ | |
cfdfa865 | 1110 | SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
09779c6d NP |
1111 | if (__len & 2) { \ |
1112 | __ptr += (__len & ~3); \ | |
e9e4ea74 | 1113 | SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \ |
09779c6d | 1114 | } \ |
3e947943 | 1115 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1116 | SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1117 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1118 | SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ |
1da177e4 | 1119 | } while (0) |
1da177e4 | 1120 | |
cfdfa865 | 1121 | #define SMC_PULL_DATA(lp, p, l) \ |
09779c6d | 1122 | do { \ |
3e947943 | 1123 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1124 | void *__ptr = (p); \ |
1125 | int __len = (l); \ | |
fbd81976 | 1126 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1127 | if ((unsigned long)__ptr & 2) { \ |
1128 | /* \ | |
1129 | * We want 32bit alignment here. \ | |
1130 | * Since some buses perform a full \ | |
1131 | * 32bit fetch even for 16bit data \ | |
1132 | * we can't use SMC_inw() here. \ | |
1133 | * Back both source (on-chip) and \ | |
1134 | * destination pointers of 2 bytes. \ | |
1135 | * This is possible since the call to \ | |
1136 | * SMC_GET_PKT_HDR() already advanced \ | |
1137 | * the source pointer of 4 bytes, and \ | |
1138 | * the skb_reserve(skb, 2) advanced \ | |
1139 | * the destination pointer of 2 bytes. \ | |
1140 | */ \ | |
1141 | __ptr -= 2; \ | |
1142 | __len += 2; \ | |
cfdfa865 MD |
1143 | SMC_SET_PTR(lp, \ |
1144 | 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
09779c6d NP |
1145 | } \ |
1146 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1147 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1148 | __len += 2; \ |
cfdfa865 | 1149 | SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
3e947943 | 1150 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1151 | SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1152 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1153 | SMC_insb(ioaddr, DATA_REG(lp), p, l); \ |
09779c6d | 1154 | } while (0) |
1da177e4 LT |
1155 | |
1156 | #endif /* _SMC91X_H_ */ |