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fd9abb3d SG |
1 | /*************************************************************************** |
2 | * | |
3 | * Copyright (C) 2004-2008 SMSC | |
4 | * Copyright (C) 2005-2008 ARM | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
fd9abb3d SG |
18 | * |
19 | *************************************************************************** | |
20 | * Rewritten, heavily based on smsc911x simple driver by SMSC. | |
21 | * Partly uses io macros from smc91x.c by Nicolas Pitre | |
22 | * | |
23 | * Supported devices: | |
24 | * LAN9115, LAN9116, LAN9117, LAN9118 | |
25 | * LAN9215, LAN9216, LAN9217, LAN9218 | |
26 | * LAN9210, LAN9211 | |
27 | * LAN9220, LAN9221 | |
28c21379 | 28 | * LAN89218 |
fd9abb3d SG |
29 | * |
30 | */ | |
31 | ||
dffc6b24 JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
fd9abb3d | 34 | #include <linux/crc32.h> |
b6c23019 | 35 | #include <linux/clk.h> |
fd9abb3d SG |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/init.h> | |
a6b7a407 | 41 | #include <linux/interrupt.h> |
fd9abb3d SG |
42 | #include <linux/ioport.h> |
43 | #include <linux/kernel.h> | |
44 | #include <linux/module.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/platform_device.h> | |
c7e963f6 | 47 | #include <linux/regulator/consumer.h> |
fd9abb3d | 48 | #include <linux/sched.h> |
fd9abb3d | 49 | #include <linux/timer.h> |
fd9abb3d SG |
50 | #include <linux/bug.h> |
51 | #include <linux/bitops.h> | |
52 | #include <linux/irq.h> | |
53 | #include <linux/io.h> | |
833cc67c | 54 | #include <linux/swab.h> |
fd9abb3d SG |
55 | #include <linux/phy.h> |
56 | #include <linux/smsc911x.h> | |
6cb87823 | 57 | #include <linux/device.h> |
79f88ee9 SG |
58 | #include <linux/of.h> |
59 | #include <linux/of_device.h> | |
60 | #include <linux/of_gpio.h> | |
61 | #include <linux/of_net.h> | |
0b50dc4f | 62 | #include <linux/acpi.h> |
3a611e26 | 63 | #include <linux/pm_runtime.h> |
0b50dc4f | 64 | #include <linux/property.h> |
3a611e26 | 65 | |
fd9abb3d SG |
66 | #include "smsc911x.h" |
67 | ||
68 | #define SMSC_CHIPNAME "smsc911x" | |
69 | #define SMSC_MDIONAME "smsc911x-mdio" | |
70 | #define SMSC_DRV_VERSION "2008-10-21" | |
71 | ||
72 | MODULE_LICENSE("GPL"); | |
73 | MODULE_VERSION(SMSC_DRV_VERSION); | |
62038e4a | 74 | MODULE_ALIAS("platform:smsc911x"); |
fd9abb3d SG |
75 | |
76 | #if USE_DEBUG > 0 | |
77 | static int debug = 16; | |
78 | #else | |
79 | static int debug = 3; | |
80 | #endif | |
81 | ||
82 | module_param(debug, int, 0); | |
83 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
84 | ||
c326de88 MP |
85 | struct smsc911x_data; |
86 | ||
87 | struct smsc911x_ops { | |
88 | u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); | |
89 | void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); | |
90 | void (*rx_readfifo)(struct smsc911x_data *pdata, | |
91 | unsigned int *buf, unsigned int wordcount); | |
92 | void (*tx_writefifo)(struct smsc911x_data *pdata, | |
93 | unsigned int *buf, unsigned int wordcount); | |
94 | }; | |
95 | ||
c7e963f6 RM |
96 | #define SMSC911X_NUM_SUPPLIES 2 |
97 | ||
fd9abb3d SG |
98 | struct smsc911x_data { |
99 | void __iomem *ioaddr; | |
100 | ||
101 | unsigned int idrev; | |
102 | ||
103 | /* used to decide which workarounds apply */ | |
104 | unsigned int generation; | |
105 | ||
106 | /* device configuration (copied from platform_data during probe) */ | |
2107fb8b | 107 | struct smsc911x_platform_config config; |
fd9abb3d SG |
108 | |
109 | /* This needs to be acquired before calling any of below: | |
110 | * smsc911x_mac_read(), smsc911x_mac_write() | |
111 | */ | |
112 | spinlock_t mac_lock; | |
113 | ||
492c5d94 | 114 | /* spinlock to ensure register accesses are serialised */ |
fd9abb3d | 115 | spinlock_t dev_lock; |
fd9abb3d | 116 | |
fd9abb3d | 117 | struct mii_bus *mii_bus; |
fd9abb3d SG |
118 | unsigned int using_extphy; |
119 | int last_duplex; | |
120 | int last_carrier; | |
121 | ||
122 | u32 msg_enable; | |
123 | unsigned int gpio_setting; | |
124 | unsigned int gpio_orig_setting; | |
125 | struct net_device *dev; | |
126 | struct napi_struct napi; | |
127 | ||
128 | unsigned int software_irq_signal; | |
129 | ||
130 | #ifdef USE_PHY_WORK_AROUND | |
131 | #define MIN_PACKET_SIZE (64) | |
132 | char loopback_tx_pkt[MIN_PACKET_SIZE]; | |
133 | char loopback_rx_pkt[MIN_PACKET_SIZE]; | |
134 | unsigned int resetcount; | |
135 | #endif | |
136 | ||
137 | /* Members for Multicast filter workaround */ | |
138 | unsigned int multicast_update_pending; | |
139 | unsigned int set_bits_mask; | |
140 | unsigned int clear_bits_mask; | |
141 | unsigned int hashhi; | |
142 | unsigned int hashlo; | |
c326de88 MP |
143 | |
144 | /* register access functions */ | |
145 | const struct smsc911x_ops *ops; | |
c7e963f6 RM |
146 | |
147 | /* regulators */ | |
148 | struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES]; | |
b6c23019 LJ |
149 | |
150 | /* clock */ | |
151 | struct clk *clk; | |
fd9abb3d SG |
152 | }; |
153 | ||
c326de88 MP |
154 | /* Easy access to information */ |
155 | #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) | |
156 | ||
492c5d94 | 157 | static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
fd9abb3d | 158 | { |
2107fb8b SG |
159 | if (pdata->config.flags & SMSC911X_USE_32BIT) |
160 | return readl(pdata->ioaddr + reg); | |
161 | ||
492c5d94 CM |
162 | if (pdata->config.flags & SMSC911X_USE_16BIT) |
163 | return ((readw(pdata->ioaddr + reg) & 0xFFFF) | | |
2107fb8b | 164 | ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); |
fd9abb3d | 165 | |
2107fb8b | 166 | BUG(); |
702403af | 167 | return 0; |
fd9abb3d SG |
168 | } |
169 | ||
c326de88 MP |
170 | static inline u32 |
171 | __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) | |
172 | { | |
173 | if (pdata->config.flags & SMSC911X_USE_32BIT) | |
174 | return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); | |
175 | ||
176 | if (pdata->config.flags & SMSC911X_USE_16BIT) | |
177 | return (readw(pdata->ioaddr + | |
178 | __smsc_shift(pdata, reg)) & 0xFFFF) | | |
179 | ((readw(pdata->ioaddr + | |
180 | __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); | |
181 | ||
182 | BUG(); | |
183 | return 0; | |
184 | } | |
185 | ||
492c5d94 CM |
186 | static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) |
187 | { | |
188 | u32 data; | |
189 | unsigned long flags; | |
190 | ||
191 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 192 | data = pdata->ops->reg_read(pdata, reg); |
492c5d94 CM |
193 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
194 | ||
195 | return data; | |
196 | } | |
197 | ||
198 | static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, | |
199 | u32 val) | |
fd9abb3d | 200 | { |
2107fb8b SG |
201 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
202 | writel(val, pdata->ioaddr + reg); | |
203 | return; | |
204 | } | |
205 | ||
206 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
2107fb8b SG |
207 | writew(val & 0xFFFF, pdata->ioaddr + reg); |
208 | writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); | |
2107fb8b SG |
209 | return; |
210 | } | |
fd9abb3d | 211 | |
2107fb8b | 212 | BUG(); |
fd9abb3d SG |
213 | } |
214 | ||
c326de88 MP |
215 | static inline void |
216 | __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) | |
217 | { | |
218 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
219 | writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); | |
220 | return; | |
221 | } | |
222 | ||
223 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
224 | writew(val & 0xFFFF, | |
225 | pdata->ioaddr + __smsc_shift(pdata, reg)); | |
226 | writew((val >> 16) & 0xFFFF, | |
227 | pdata->ioaddr + __smsc_shift(pdata, reg + 2)); | |
228 | return; | |
229 | } | |
230 | ||
231 | BUG(); | |
232 | } | |
233 | ||
492c5d94 CM |
234 | static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, |
235 | u32 val) | |
236 | { | |
237 | unsigned long flags; | |
238 | ||
239 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
c326de88 | 240 | pdata->ops->reg_write(pdata, reg, val); |
492c5d94 CM |
241 | spin_unlock_irqrestore(&pdata->dev_lock, flags); |
242 | } | |
243 | ||
fd9abb3d SG |
244 | /* Writes a packet to the TX_DATA_FIFO */ |
245 | static inline void | |
246 | smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf, | |
247 | unsigned int wordcount) | |
248 | { | |
492c5d94 CM |
249 | unsigned long flags; |
250 | ||
251 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
252 | ||
833cc67c MD |
253 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
254 | while (wordcount--) | |
492c5d94 CM |
255 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, |
256 | swab32(*buf++)); | |
257 | goto out; | |
833cc67c MD |
258 | } |
259 | ||
2107fb8b | 260 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 261 | iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount); |
492c5d94 | 262 | goto out; |
2107fb8b SG |
263 | } |
264 | ||
265 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
266 | while (wordcount--) | |
492c5d94 CM |
267 | __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++); |
268 | goto out; | |
2107fb8b SG |
269 | } |
270 | ||
271 | BUG(); | |
492c5d94 CM |
272 | out: |
273 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
fd9abb3d SG |
274 | } |
275 | ||
c326de88 MP |
276 | /* Writes a packet to the TX_DATA_FIFO - shifted version */ |
277 | static inline void | |
278 | smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
279 | unsigned int wordcount) | |
280 | { | |
281 | unsigned long flags; | |
282 | ||
283 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
284 | ||
285 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
286 | while (wordcount--) | |
287 | __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO, | |
288 | swab32(*buf++)); | |
289 | goto out; | |
290 | } | |
291 | ||
292 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 293 | iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
294 | TX_DATA_FIFO), buf, wordcount); |
295 | goto out; | |
296 | } | |
297 | ||
298 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
299 | while (wordcount--) | |
300 | __smsc911x_reg_write_shift(pdata, | |
301 | TX_DATA_FIFO, *buf++); | |
302 | goto out; | |
303 | } | |
304 | ||
305 | BUG(); | |
306 | out: | |
307 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
308 | } | |
309 | ||
fd9abb3d SG |
310 | /* Reads a packet out of the RX_DATA_FIFO */ |
311 | static inline void | |
312 | smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf, | |
313 | unsigned int wordcount) | |
314 | { | |
492c5d94 CM |
315 | unsigned long flags; |
316 | ||
317 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
318 | ||
833cc67c MD |
319 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { |
320 | while (wordcount--) | |
492c5d94 CM |
321 | *buf++ = swab32(__smsc911x_reg_read(pdata, |
322 | RX_DATA_FIFO)); | |
323 | goto out; | |
833cc67c MD |
324 | } |
325 | ||
2107fb8b | 326 | if (pdata->config.flags & SMSC911X_USE_32BIT) { |
2925f6c0 | 327 | ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount); |
492c5d94 | 328 | goto out; |
2107fb8b | 329 | } |
fd9abb3d | 330 | |
2107fb8b SG |
331 | if (pdata->config.flags & SMSC911X_USE_16BIT) { |
332 | while (wordcount--) | |
492c5d94 CM |
333 | *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO); |
334 | goto out; | |
2107fb8b SG |
335 | } |
336 | ||
337 | BUG(); | |
492c5d94 CM |
338 | out: |
339 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
2107fb8b | 340 | } |
fd9abb3d | 341 | |
c326de88 MP |
342 | /* Reads a packet out of the RX_DATA_FIFO - shifted version */ |
343 | static inline void | |
344 | smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf, | |
345 | unsigned int wordcount) | |
346 | { | |
347 | unsigned long flags; | |
348 | ||
349 | spin_lock_irqsave(&pdata->dev_lock, flags); | |
350 | ||
351 | if (pdata->config.flags & SMSC911X_SWAP_FIFO) { | |
352 | while (wordcount--) | |
353 | *buf++ = swab32(__smsc911x_reg_read_shift(pdata, | |
354 | RX_DATA_FIFO)); | |
355 | goto out; | |
356 | } | |
357 | ||
358 | if (pdata->config.flags & SMSC911X_USE_32BIT) { | |
2925f6c0 | 359 | ioread32_rep(pdata->ioaddr + __smsc_shift(pdata, |
c326de88 MP |
360 | RX_DATA_FIFO), buf, wordcount); |
361 | goto out; | |
362 | } | |
363 | ||
364 | if (pdata->config.flags & SMSC911X_USE_16BIT) { | |
365 | while (wordcount--) | |
366 | *buf++ = __smsc911x_reg_read_shift(pdata, | |
367 | RX_DATA_FIFO); | |
368 | goto out; | |
369 | } | |
370 | ||
371 | BUG(); | |
372 | out: | |
373 | spin_unlock_irqrestore(&pdata->dev_lock, flags); | |
374 | } | |
375 | ||
c7e963f6 | 376 | /* |
b6c23019 | 377 | * enable regulator and clock resources. |
c7e963f6 RM |
378 | */ |
379 | static int smsc911x_enable_resources(struct platform_device *pdev) | |
380 | { | |
381 | struct net_device *ndev = platform_get_drvdata(pdev); | |
382 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
383 | int ret = 0; | |
384 | ||
385 | ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies), | |
386 | pdata->supplies); | |
387 | if (ret) | |
388 | netdev_err(ndev, "failed to enable regulators %d\n", | |
389 | ret); | |
b6c23019 LJ |
390 | |
391 | if (!IS_ERR(pdata->clk)) { | |
392 | ret = clk_prepare_enable(pdata->clk); | |
393 | if (ret < 0) | |
394 | netdev_err(ndev, "failed to enable clock %d\n", ret); | |
395 | } | |
396 | ||
c7e963f6 RM |
397 | return ret; |
398 | } | |
399 | ||
400 | /* | |
401 | * disable resources, currently just regulators. | |
402 | */ | |
403 | static int smsc911x_disable_resources(struct platform_device *pdev) | |
404 | { | |
405 | struct net_device *ndev = platform_get_drvdata(pdev); | |
406 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
407 | int ret = 0; | |
408 | ||
409 | ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies), | |
410 | pdata->supplies); | |
b6c23019 LJ |
411 | |
412 | if (!IS_ERR(pdata->clk)) | |
413 | clk_disable_unprepare(pdata->clk); | |
414 | ||
c7e963f6 RM |
415 | return ret; |
416 | } | |
417 | ||
418 | /* | |
419 | * Request resources, currently just regulators. | |
420 | * | |
421 | * The SMSC911x has two power pins: vddvario and vdd33a, in designs where | |
422 | * these are not always-on we need to request regulators to be turned on | |
423 | * before we can try to access the device registers. | |
424 | */ | |
425 | static int smsc911x_request_resources(struct platform_device *pdev) | |
426 | { | |
427 | struct net_device *ndev = platform_get_drvdata(pdev); | |
428 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
429 | int ret = 0; | |
430 | ||
431 | /* Request regulators */ | |
432 | pdata->supplies[0].supply = "vdd33a"; | |
433 | pdata->supplies[1].supply = "vddvario"; | |
434 | ret = regulator_bulk_get(&pdev->dev, | |
435 | ARRAY_SIZE(pdata->supplies), | |
436 | pdata->supplies); | |
437 | if (ret) | |
438 | netdev_err(ndev, "couldn't get regulators %d\n", | |
439 | ret); | |
b6c23019 LJ |
440 | |
441 | /* Request clock */ | |
442 | pdata->clk = clk_get(&pdev->dev, NULL); | |
443 | if (IS_ERR(pdata->clk)) | |
1e87af97 FE |
444 | dev_dbg(&pdev->dev, "couldn't get clock %li\n", |
445 | PTR_ERR(pdata->clk)); | |
b6c23019 | 446 | |
c7e963f6 RM |
447 | return ret; |
448 | } | |
449 | ||
450 | /* | |
451 | * Free resources, currently just regulators. | |
452 | * | |
453 | */ | |
454 | static void smsc911x_free_resources(struct platform_device *pdev) | |
455 | { | |
456 | struct net_device *ndev = platform_get_drvdata(pdev); | |
457 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
458 | ||
459 | /* Free regulators */ | |
460 | regulator_bulk_free(ARRAY_SIZE(pdata->supplies), | |
461 | pdata->supplies); | |
b6c23019 LJ |
462 | |
463 | /* Free clock */ | |
464 | if (!IS_ERR(pdata->clk)) { | |
465 | clk_put(pdata->clk); | |
466 | pdata->clk = NULL; | |
467 | } | |
c7e963f6 RM |
468 | } |
469 | ||
fd9abb3d SG |
470 | /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read |
471 | * and smsc911x_mac_write, so assumes mac_lock is held */ | |
472 | static int smsc911x_mac_complete(struct smsc911x_data *pdata) | |
473 | { | |
474 | int i; | |
475 | u32 val; | |
476 | ||
477 | SMSC_ASSERT_MAC_LOCK(pdata); | |
478 | ||
479 | for (i = 0; i < 40; i++) { | |
480 | val = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
481 | if (!(val & MAC_CSR_CMD_CSR_BUSY_)) | |
482 | return 0; | |
483 | } | |
dffc6b24 JP |
484 | SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. " |
485 | "MAC_CSR_CMD: 0x%08X", val); | |
fd9abb3d SG |
486 | return -EIO; |
487 | } | |
488 | ||
489 | /* Fetches a MAC register value. Assumes mac_lock is acquired */ | |
490 | static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset) | |
491 | { | |
492 | unsigned int temp; | |
493 | ||
494 | SMSC_ASSERT_MAC_LOCK(pdata); | |
495 | ||
496 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
497 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 | 498 | SMSC_WARN(pdata, hw, "MAC busy at entry"); |
fd9abb3d SG |
499 | return 0xFFFFFFFF; |
500 | } | |
501 | ||
502 | /* Send the MAC cmd */ | |
503 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
504 | MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); | |
505 | ||
506 | /* Workaround for hardware read-after-write restriction */ | |
507 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
508 | ||
509 | /* Wait for the read to complete */ | |
510 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
511 | return smsc911x_reg_read(pdata, MAC_CSR_DATA); | |
512 | ||
dffc6b24 | 513 | SMSC_WARN(pdata, hw, "MAC busy after read"); |
fd9abb3d SG |
514 | return 0xFFFFFFFF; |
515 | } | |
516 | ||
517 | /* Set a mac register, mac_lock must be acquired before calling */ | |
518 | static void smsc911x_mac_write(struct smsc911x_data *pdata, | |
519 | unsigned int offset, u32 val) | |
520 | { | |
521 | unsigned int temp; | |
522 | ||
523 | SMSC_ASSERT_MAC_LOCK(pdata); | |
524 | ||
525 | temp = smsc911x_reg_read(pdata, MAC_CSR_CMD); | |
526 | if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) { | |
dffc6b24 JP |
527 | SMSC_WARN(pdata, hw, |
528 | "smsc911x_mac_write failed, MAC busy at entry"); | |
fd9abb3d SG |
529 | return; |
530 | } | |
531 | ||
532 | /* Send data to write */ | |
533 | smsc911x_reg_write(pdata, MAC_CSR_DATA, val); | |
534 | ||
535 | /* Write the actual data */ | |
536 | smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) | | |
537 | MAC_CSR_CMD_CSR_BUSY_)); | |
538 | ||
539 | /* Workaround for hardware read-after-write restriction */ | |
540 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
541 | ||
542 | /* Wait for the write to complete */ | |
543 | if (likely(smsc911x_mac_complete(pdata) == 0)) | |
544 | return; | |
545 | ||
dffc6b24 | 546 | SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write"); |
fd9abb3d SG |
547 | } |
548 | ||
549 | /* Get a phy register */ | |
550 | static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx) | |
551 | { | |
552 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
553 | unsigned long flags; | |
554 | unsigned int addr; | |
555 | int i, reg; | |
556 | ||
557 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
558 | ||
559 | /* Confirm MII not busy */ | |
560 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 561 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???"); |
fd9abb3d SG |
562 | reg = -EIO; |
563 | goto out; | |
564 | } | |
565 | ||
566 | /* Set the address, index & direction (read from PHY) */ | |
567 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6); | |
568 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
569 | ||
570 | /* Wait for read to complete w/ timeout */ | |
571 | for (i = 0; i < 100; i++) | |
572 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
573 | reg = smsc911x_mac_read(pdata, MII_DATA); | |
574 | goto out; | |
575 | } | |
576 | ||
dffc6b24 | 577 | SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish"); |
fd9abb3d SG |
578 | reg = -EIO; |
579 | ||
580 | out: | |
581 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
582 | return reg; | |
583 | } | |
584 | ||
585 | /* Set a phy register */ | |
586 | static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
587 | u16 val) | |
588 | { | |
589 | struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv; | |
590 | unsigned long flags; | |
591 | unsigned int addr; | |
592 | int i, reg; | |
593 | ||
594 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
595 | ||
596 | /* Confirm MII not busy */ | |
597 | if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
dffc6b24 | 598 | SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???"); |
fd9abb3d SG |
599 | reg = -EIO; |
600 | goto out; | |
601 | } | |
602 | ||
603 | /* Put the data to write in the MAC */ | |
604 | smsc911x_mac_write(pdata, MII_DATA, val); | |
605 | ||
606 | /* Set the address, index & direction (write to PHY) */ | |
607 | addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | | |
608 | MII_ACC_MII_WRITE_; | |
609 | smsc911x_mac_write(pdata, MII_ACC, addr); | |
610 | ||
611 | /* Wait for write to complete w/ timeout */ | |
612 | for (i = 0; i < 100; i++) | |
613 | if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) { | |
614 | reg = 0; | |
615 | goto out; | |
616 | } | |
617 | ||
dffc6b24 | 618 | SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish"); |
fd9abb3d SG |
619 | reg = -EIO; |
620 | ||
621 | out: | |
622 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
623 | return reg; | |
624 | } | |
625 | ||
d23f028a SG |
626 | /* Switch to external phy. Assumes tx and rx are stopped. */ |
627 | static void smsc911x_phy_enable_external(struct smsc911x_data *pdata) | |
fd9abb3d SG |
628 | { |
629 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
630 | ||
d23f028a SG |
631 | /* Disable phy clocks to the MAC */ |
632 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
633 | hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; | |
634 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
635 | udelay(10); /* Enough time for clocks to stop */ | |
fd9abb3d | 636 | |
d23f028a SG |
637 | /* Switch to external phy */ |
638 | hwcfg |= HW_CFG_EXT_PHY_EN_; | |
639 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
fd9abb3d | 640 | |
d23f028a SG |
641 | /* Enable phy clocks to the MAC */ |
642 | hwcfg &= (~HW_CFG_PHY_CLK_SEL_); | |
643 | hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; | |
644 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
645 | udelay(10); /* Enough time for clocks to restart */ | |
fd9abb3d | 646 | |
d23f028a SG |
647 | hwcfg |= HW_CFG_SMI_SEL_; |
648 | smsc911x_reg_write(pdata, HW_CFG, hwcfg); | |
649 | } | |
fd9abb3d | 650 | |
d23f028a SG |
651 | /* Autodetects and enables external phy if present on supported chips. |
652 | * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY | |
653 | * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */ | |
654 | static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata) | |
655 | { | |
656 | unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG); | |
fd9abb3d | 657 | |
d23f028a | 658 | if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) { |
dffc6b24 | 659 | SMSC_TRACE(pdata, hw, "Forcing internal PHY"); |
d23f028a SG |
660 | pdata->using_extphy = 0; |
661 | } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) { | |
dffc6b24 | 662 | SMSC_TRACE(pdata, hw, "Forcing external PHY"); |
d23f028a SG |
663 | smsc911x_phy_enable_external(pdata); |
664 | pdata->using_extphy = 1; | |
665 | } else if (hwcfg & HW_CFG_EXT_PHY_DET_) { | |
dffc6b24 JP |
666 | SMSC_TRACE(pdata, hw, |
667 | "HW_CFG EXT_PHY_DET set, using external PHY"); | |
d23f028a | 668 | smsc911x_phy_enable_external(pdata); |
fd9abb3d SG |
669 | pdata->using_extphy = 1; |
670 | } else { | |
dffc6b24 JP |
671 | SMSC_TRACE(pdata, hw, |
672 | "HW_CFG EXT_PHY_DET clear, using internal PHY"); | |
d23f028a | 673 | pdata->using_extphy = 0; |
fd9abb3d | 674 | } |
fd9abb3d SG |
675 | } |
676 | ||
677 | /* Fetches a tx status out of the status fifo */ | |
678 | static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata) | |
679 | { | |
680 | unsigned int result = | |
681 | smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_; | |
682 | ||
683 | if (result != 0) | |
684 | result = smsc911x_reg_read(pdata, TX_STATUS_FIFO); | |
685 | ||
686 | return result; | |
687 | } | |
688 | ||
689 | /* Fetches the next rx status */ | |
690 | static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata) | |
691 | { | |
692 | unsigned int result = | |
693 | smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_; | |
694 | ||
695 | if (result != 0) | |
696 | result = smsc911x_reg_read(pdata, RX_STATUS_FIFO); | |
697 | ||
698 | return result; | |
699 | } | |
700 | ||
701 | #ifdef USE_PHY_WORK_AROUND | |
702 | static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata) | |
703 | { | |
704 | unsigned int tries; | |
705 | u32 wrsz; | |
706 | u32 rdsz; | |
707 | ulong bufp; | |
708 | ||
709 | for (tries = 0; tries < 10; tries++) { | |
710 | unsigned int txcmd_a; | |
711 | unsigned int txcmd_b; | |
712 | unsigned int status; | |
713 | unsigned int pktlength; | |
714 | unsigned int i; | |
715 | ||
716 | /* Zero-out rx packet memory */ | |
717 | memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE); | |
718 | ||
719 | /* Write tx packet to 118 */ | |
720 | txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16; | |
721 | txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
722 | txcmd_a |= MIN_PACKET_SIZE; | |
723 | ||
724 | txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE; | |
725 | ||
726 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a); | |
727 | smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b); | |
728 | ||
729 | bufp = (ulong)pdata->loopback_tx_pkt & (~0x3); | |
730 | wrsz = MIN_PACKET_SIZE + 3; | |
731 | wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3); | |
732 | wrsz >>= 2; | |
733 | ||
c326de88 | 734 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d SG |
735 | |
736 | /* Wait till transmit is done */ | |
737 | i = 60; | |
738 | do { | |
739 | udelay(5); | |
740 | status = smsc911x_tx_get_txstatus(pdata); | |
741 | } while ((i--) && (!status)); | |
742 | ||
743 | if (!status) { | |
dffc6b24 JP |
744 | SMSC_WARN(pdata, hw, |
745 | "Failed to transmit during loopback test"); | |
fd9abb3d SG |
746 | continue; |
747 | } | |
748 | if (status & TX_STS_ES_) { | |
dffc6b24 JP |
749 | SMSC_WARN(pdata, hw, |
750 | "Transmit encountered errors during loopback test"); | |
fd9abb3d SG |
751 | continue; |
752 | } | |
753 | ||
754 | /* Wait till receive is done */ | |
755 | i = 60; | |
756 | do { | |
757 | udelay(5); | |
758 | status = smsc911x_rx_get_rxstatus(pdata); | |
759 | } while ((i--) && (!status)); | |
760 | ||
761 | if (!status) { | |
dffc6b24 JP |
762 | SMSC_WARN(pdata, hw, |
763 | "Failed to receive during loopback test"); | |
fd9abb3d SG |
764 | continue; |
765 | } | |
766 | if (status & RX_STS_ES_) { | |
dffc6b24 JP |
767 | SMSC_WARN(pdata, hw, |
768 | "Receive encountered errors during loopback test"); | |
fd9abb3d SG |
769 | continue; |
770 | } | |
771 | ||
772 | pktlength = ((status & 0x3FFF0000UL) >> 16); | |
773 | bufp = (ulong)pdata->loopback_rx_pkt; | |
774 | rdsz = pktlength + 3; | |
775 | rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3); | |
776 | rdsz >>= 2; | |
777 | ||
c326de88 | 778 | pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz); |
fd9abb3d SG |
779 | |
780 | if (pktlength != (MIN_PACKET_SIZE + 4)) { | |
dffc6b24 JP |
781 | SMSC_WARN(pdata, hw, "Unexpected packet size " |
782 | "during loop back test, size=%d, will retry", | |
783 | pktlength); | |
fd9abb3d SG |
784 | } else { |
785 | unsigned int j; | |
786 | int mismatch = 0; | |
787 | for (j = 0; j < MIN_PACKET_SIZE; j++) { | |
788 | if (pdata->loopback_tx_pkt[j] | |
789 | != pdata->loopback_rx_pkt[j]) { | |
790 | mismatch = 1; | |
791 | break; | |
792 | } | |
793 | } | |
794 | if (!mismatch) { | |
dffc6b24 | 795 | SMSC_TRACE(pdata, hw, "Successfully verified " |
fd9abb3d SG |
796 | "loopback packet"); |
797 | return 0; | |
798 | } else { | |
dffc6b24 JP |
799 | SMSC_WARN(pdata, hw, "Data mismatch " |
800 | "during loop back test, will retry"); | |
fd9abb3d SG |
801 | } |
802 | } | |
803 | } | |
804 | ||
805 | return -EIO; | |
806 | } | |
807 | ||
808 | static int smsc911x_phy_reset(struct smsc911x_data *pdata) | |
809 | { | |
fd9abb3d SG |
810 | unsigned int temp; |
811 | unsigned int i = 100000; | |
812 | ||
cd998ecd PF |
813 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
814 | smsc911x_reg_write(pdata, PMT_CTRL, temp | PMT_CTRL_PHY_RST_); | |
fd9abb3d SG |
815 | do { |
816 | msleep(1); | |
cd998ecd PF |
817 | temp = smsc911x_reg_read(pdata, PMT_CTRL); |
818 | } while ((i--) && (temp & PMT_CTRL_PHY_RST_)); | |
fd9abb3d | 819 | |
cd998ecd | 820 | if (unlikely(temp & PMT_CTRL_PHY_RST_)) { |
dffc6b24 | 821 | SMSC_WARN(pdata, hw, "PHY reset failed to complete"); |
fd9abb3d SG |
822 | return -EIO; |
823 | } | |
824 | /* Extra delay required because the phy may not be completed with | |
825 | * its reset when BMCR_RESET is cleared. Specs say 256 uS is | |
826 | * enough delay but using 1ms here to be safe */ | |
827 | msleep(1); | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static int smsc911x_phy_loopbacktest(struct net_device *dev) | |
833 | { | |
834 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 835 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
836 | int result = -EIO; |
837 | unsigned int i, val; | |
838 | unsigned long flags; | |
839 | ||
840 | /* Initialise tx packet using broadcast destination address */ | |
c7bf7169 | 841 | eth_broadcast_addr(pdata->loopback_tx_pkt); |
fd9abb3d SG |
842 | |
843 | /* Use incrementing source address */ | |
844 | for (i = 6; i < 12; i++) | |
845 | pdata->loopback_tx_pkt[i] = (char)i; | |
846 | ||
847 | /* Set length type field */ | |
848 | pdata->loopback_tx_pkt[12] = 0x00; | |
849 | pdata->loopback_tx_pkt[13] = 0x00; | |
850 | ||
851 | for (i = 14; i < MIN_PACKET_SIZE; i++) | |
852 | pdata->loopback_tx_pkt[i] = (char)i; | |
853 | ||
854 | val = smsc911x_reg_read(pdata, HW_CFG); | |
855 | val &= HW_CFG_TX_FIF_SZ_; | |
856 | val |= HW_CFG_SF_; | |
857 | smsc911x_reg_write(pdata, HW_CFG, val); | |
858 | ||
859 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
860 | smsc911x_reg_write(pdata, RX_CFG, | |
861 | (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8); | |
862 | ||
863 | for (i = 0; i < 10; i++) { | |
864 | /* Set PHY to 10/FD, no ANEG, and loopback mode */ | |
e5a03bfd AL |
865 | smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, |
866 | MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX); | |
fd9abb3d SG |
867 | |
868 | /* Enable MAC tx/rx, FD */ | |
869 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
870 | smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_ | |
871 | | MAC_CR_TXEN_ | MAC_CR_RXEN_); | |
872 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
873 | ||
874 | if (smsc911x_phy_check_loopbackpkt(pdata) == 0) { | |
875 | result = 0; | |
876 | break; | |
877 | } | |
878 | pdata->resetcount++; | |
879 | ||
880 | /* Disable MAC rx */ | |
881 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
882 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
883 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
884 | ||
885 | smsc911x_phy_reset(pdata); | |
886 | } | |
887 | ||
888 | /* Disable MAC */ | |
889 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
890 | smsc911x_mac_write(pdata, MAC_CR, 0); | |
891 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
892 | ||
893 | /* Cancel PHY loopback mode */ | |
e5a03bfd | 894 | smsc911x_mii_write(phy_dev->mdio.bus, phy_dev->mdio.addr, MII_BMCR, 0); |
fd9abb3d SG |
895 | |
896 | smsc911x_reg_write(pdata, TX_CFG, 0); | |
897 | smsc911x_reg_write(pdata, RX_CFG, 0); | |
898 | ||
899 | return result; | |
900 | } | |
901 | #endif /* USE_PHY_WORK_AROUND */ | |
902 | ||
fd9abb3d SG |
903 | static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata) |
904 | { | |
f788e322 PR |
905 | struct net_device *ndev = pdata->dev; |
906 | struct phy_device *phy_dev = ndev->phydev; | |
fd9abb3d SG |
907 | u32 afc = smsc911x_reg_read(pdata, AFC_CFG); |
908 | u32 flow; | |
909 | unsigned long flags; | |
910 | ||
911 | if (phy_dev->duplex == DUPLEX_FULL) { | |
912 | u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); | |
913 | u16 rmtadv = phy_read(phy_dev, MII_LPA); | |
bc02ff95 | 914 | u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
fd9abb3d SG |
915 | |
916 | if (cap & FLOW_CTRL_RX) | |
917 | flow = 0xFFFF0002; | |
918 | else | |
919 | flow = 0; | |
920 | ||
921 | if (cap & FLOW_CTRL_TX) | |
922 | afc |= 0xF; | |
923 | else | |
924 | afc &= ~0xF; | |
925 | ||
dffc6b24 JP |
926 | SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s", |
927 | (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), | |
928 | (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); | |
fd9abb3d | 929 | } else { |
dffc6b24 | 930 | SMSC_TRACE(pdata, hw, "half duplex"); |
fd9abb3d SG |
931 | flow = 0; |
932 | afc |= 0xF; | |
933 | } | |
934 | ||
935 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
936 | smsc911x_mac_write(pdata, FLOW, flow); | |
937 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
938 | ||
939 | smsc911x_reg_write(pdata, AFC_CFG, afc); | |
940 | } | |
941 | ||
942 | /* Update link mode if anything has changed. Called periodically when the | |
943 | * PHY is in polling mode, even if nothing has changed. */ | |
944 | static void smsc911x_phy_adjust_link(struct net_device *dev) | |
945 | { | |
946 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 947 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
948 | unsigned long flags; |
949 | int carrier; | |
950 | ||
951 | if (phy_dev->duplex != pdata->last_duplex) { | |
952 | unsigned int mac_cr; | |
dffc6b24 | 953 | SMSC_TRACE(pdata, hw, "duplex state has changed"); |
fd9abb3d SG |
954 | |
955 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
956 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
957 | if (phy_dev->duplex) { | |
dffc6b24 JP |
958 | SMSC_TRACE(pdata, hw, |
959 | "configuring for full duplex mode"); | |
fd9abb3d SG |
960 | mac_cr |= MAC_CR_FDPX_; |
961 | } else { | |
dffc6b24 JP |
962 | SMSC_TRACE(pdata, hw, |
963 | "configuring for half duplex mode"); | |
fd9abb3d SG |
964 | mac_cr &= ~MAC_CR_FDPX_; |
965 | } | |
966 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
967 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
968 | ||
969 | smsc911x_phy_update_flowcontrol(pdata); | |
970 | pdata->last_duplex = phy_dev->duplex; | |
971 | } | |
972 | ||
973 | carrier = netif_carrier_ok(dev); | |
974 | if (carrier != pdata->last_carrier) { | |
dffc6b24 | 975 | SMSC_TRACE(pdata, hw, "carrier state has changed"); |
fd9abb3d | 976 | if (carrier) { |
dffc6b24 | 977 | SMSC_TRACE(pdata, hw, "configuring for carrier OK"); |
fd9abb3d SG |
978 | if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) && |
979 | (!pdata->using_extphy)) { | |
88393161 | 980 | /* Restore original GPIO configuration */ |
fd9abb3d SG |
981 | pdata->gpio_setting = pdata->gpio_orig_setting; |
982 | smsc911x_reg_write(pdata, GPIO_CFG, | |
983 | pdata->gpio_setting); | |
984 | } | |
985 | } else { | |
dffc6b24 | 986 | SMSC_TRACE(pdata, hw, "configuring for no carrier"); |
fd9abb3d SG |
987 | /* Check global setting that LED1 |
988 | * usage is 10/100 indicator */ | |
989 | pdata->gpio_setting = smsc911x_reg_read(pdata, | |
990 | GPIO_CFG); | |
8e95a202 JP |
991 | if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) && |
992 | (!pdata->using_extphy)) { | |
fd9abb3d | 993 | /* Force 10/100 LED off, after saving |
88393161 | 994 | * original GPIO configuration */ |
fd9abb3d SG |
995 | pdata->gpio_orig_setting = pdata->gpio_setting; |
996 | ||
997 | pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_; | |
998 | pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_ | |
999 | | GPIO_CFG_GPIODIR0_ | |
1000 | | GPIO_CFG_GPIOD0_); | |
1001 | smsc911x_reg_write(pdata, GPIO_CFG, | |
1002 | pdata->gpio_setting); | |
1003 | } | |
1004 | } | |
1005 | pdata->last_carrier = carrier; | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | static int smsc911x_mii_probe(struct net_device *dev) | |
1010 | { | |
1011 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1012 | struct phy_device *phydev = NULL; | |
e4a474f8 | 1013 | int ret; |
fd9abb3d SG |
1014 | |
1015 | /* find the first phy */ | |
e4a474f8 | 1016 | phydev = phy_find_first(pdata->mii_bus); |
fd9abb3d | 1017 | if (!phydev) { |
dffc6b24 | 1018 | netdev_err(dev, "no PHY found\n"); |
fd9abb3d SG |
1019 | return -ENODEV; |
1020 | } | |
1021 | ||
dffc6b24 | 1022 | SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X", |
e5a03bfd | 1023 | phydev->mdio.addr, phydev->phy_id); |
e4a474f8 | 1024 | |
f9a8f83b FF |
1025 | ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link, |
1026 | pdata->config.phy_interface); | |
fd9abb3d | 1027 | |
e4a474f8 | 1028 | if (ret) { |
dffc6b24 | 1029 | netdev_err(dev, "Could not attach to PHY\n"); |
e4a474f8 | 1030 | return ret; |
fd9abb3d SG |
1031 | } |
1032 | ||
2220943a | 1033 | phy_attached_info(phydev); |
fd9abb3d SG |
1034 | |
1035 | /* mask with MAC supported features */ | |
1036 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
1037 | SUPPORTED_Asym_Pause); | |
1038 | phydev->advertising = phydev->supported; | |
1039 | ||
fd9abb3d SG |
1040 | pdata->last_duplex = -1; |
1041 | pdata->last_carrier = -1; | |
1042 | ||
1043 | #ifdef USE_PHY_WORK_AROUND | |
1044 | if (smsc911x_phy_loopbacktest(dev) < 0) { | |
dffc6b24 | 1045 | SMSC_WARN(pdata, hw, "Failed Loop Back Test"); |
b43c142f | 1046 | phy_disconnect(phydev); |
fd9abb3d SG |
1047 | return -ENODEV; |
1048 | } | |
dffc6b24 | 1049 | SMSC_TRACE(pdata, hw, "Passed Loop Back Test"); |
fd9abb3d SG |
1050 | #endif /* USE_PHY_WORK_AROUND */ |
1051 | ||
dffc6b24 | 1052 | SMSC_TRACE(pdata, hw, "phy initialised successfully"); |
fd9abb3d SG |
1053 | return 0; |
1054 | } | |
1055 | ||
8489ec1f | 1056 | static int smsc911x_mii_init(struct platform_device *pdev, |
1dd06ae8 | 1057 | struct net_device *dev) |
fd9abb3d SG |
1058 | { |
1059 | struct smsc911x_data *pdata = netdev_priv(dev); | |
e7f4dc35 | 1060 | int err = -ENXIO; |
fd9abb3d SG |
1061 | |
1062 | pdata->mii_bus = mdiobus_alloc(); | |
1063 | if (!pdata->mii_bus) { | |
1064 | err = -ENOMEM; | |
1065 | goto err_out_1; | |
1066 | } | |
1067 | ||
1068 | pdata->mii_bus->name = SMSC_MDIONAME; | |
09ef0789 FF |
1069 | snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1070 | pdev->name, pdev->id); | |
fd9abb3d SG |
1071 | pdata->mii_bus->priv = pdata; |
1072 | pdata->mii_bus->read = smsc911x_mii_read; | |
1073 | pdata->mii_bus->write = smsc911x_mii_write; | |
fd9abb3d SG |
1074 | |
1075 | pdata->mii_bus->parent = &pdev->dev; | |
fd9abb3d | 1076 | |
fd9abb3d SG |
1077 | switch (pdata->idrev & 0xFFFF0000) { |
1078 | case 0x01170000: | |
1079 | case 0x01150000: | |
1080 | case 0x117A0000: | |
1081 | case 0x115A0000: | |
1082 | /* External PHY supported, try to autodetect */ | |
d23f028a | 1083 | smsc911x_phy_initialise_external(pdata); |
fd9abb3d SG |
1084 | break; |
1085 | default: | |
dffc6b24 JP |
1086 | SMSC_TRACE(pdata, hw, "External PHY is not supported, " |
1087 | "using internal PHY"); | |
d23f028a | 1088 | pdata->using_extphy = 0; |
fd9abb3d SG |
1089 | break; |
1090 | } | |
1091 | ||
1092 | if (!pdata->using_extphy) { | |
1093 | /* Mask all PHYs except ID 1 (internal) */ | |
1094 | pdata->mii_bus->phy_mask = ~(1 << 1); | |
1095 | } | |
1096 | ||
1097 | if (mdiobus_register(pdata->mii_bus)) { | |
dffc6b24 | 1098 | SMSC_WARN(pdata, probe, "Error registering mii bus"); |
fd9abb3d SG |
1099 | goto err_out_free_bus_2; |
1100 | } | |
1101 | ||
fd9abb3d SG |
1102 | return 0; |
1103 | ||
fd9abb3d SG |
1104 | err_out_free_bus_2: |
1105 | mdiobus_free(pdata->mii_bus); | |
1106 | err_out_1: | |
1107 | return err; | |
1108 | } | |
1109 | ||
1110 | /* Gets the number of tx statuses in the fifo */ | |
1111 | static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata) | |
1112 | { | |
1113 | return (smsc911x_reg_read(pdata, TX_FIFO_INF) | |
1114 | & TX_FIFO_INF_TSUSED_) >> 16; | |
1115 | } | |
1116 | ||
1117 | /* Reads tx statuses and increments counters where necessary */ | |
1118 | static void smsc911x_tx_update_txcounters(struct net_device *dev) | |
1119 | { | |
1120 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1121 | unsigned int tx_stat; | |
1122 | ||
1123 | while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) { | |
1124 | if (unlikely(tx_stat & 0x80000000)) { | |
1125 | /* In this driver the packet tag is used as the packet | |
1126 | * length. Since a packet length can never reach the | |
1127 | * size of 0x8000, this bit is reserved. It is worth | |
1128 | * noting that the "reserved bit" in the warning above | |
1129 | * does not reference a hardware defined reserved bit | |
1130 | * but rather a driver defined one. | |
1131 | */ | |
dffc6b24 | 1132 | SMSC_WARN(pdata, hw, "Packet tag reserved bit is high"); |
fd9abb3d | 1133 | } else { |
785b6f97 | 1134 | if (unlikely(tx_stat & TX_STS_ES_)) { |
fd9abb3d SG |
1135 | dev->stats.tx_errors++; |
1136 | } else { | |
1137 | dev->stats.tx_packets++; | |
1138 | dev->stats.tx_bytes += (tx_stat >> 16); | |
1139 | } | |
785b6f97 | 1140 | if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) { |
fd9abb3d SG |
1141 | dev->stats.collisions += 16; |
1142 | dev->stats.tx_aborted_errors += 1; | |
1143 | } else { | |
1144 | dev->stats.collisions += | |
1145 | ((tx_stat >> 3) & 0xF); | |
1146 | } | |
785b6f97 | 1147 | if (unlikely(tx_stat & TX_STS_LOST_CARRIER_)) |
fd9abb3d | 1148 | dev->stats.tx_carrier_errors += 1; |
785b6f97 | 1149 | if (unlikely(tx_stat & TX_STS_LATE_COL_)) { |
fd9abb3d SG |
1150 | dev->stats.collisions++; |
1151 | dev->stats.tx_aborted_errors++; | |
1152 | } | |
1153 | } | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | /* Increments the Rx error counters */ | |
1158 | static void | |
1159 | smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat) | |
1160 | { | |
1161 | int crc_err = 0; | |
1162 | ||
785b6f97 | 1163 | if (unlikely(rxstat & RX_STS_ES_)) { |
fd9abb3d | 1164 | dev->stats.rx_errors++; |
785b6f97 | 1165 | if (unlikely(rxstat & RX_STS_CRC_ERR_)) { |
fd9abb3d SG |
1166 | dev->stats.rx_crc_errors++; |
1167 | crc_err = 1; | |
1168 | } | |
1169 | } | |
1170 | if (likely(!crc_err)) { | |
785b6f97 SG |
1171 | if (unlikely((rxstat & RX_STS_FRAME_TYPE_) && |
1172 | (rxstat & RX_STS_LENGTH_ERR_))) | |
fd9abb3d | 1173 | dev->stats.rx_length_errors++; |
fd9abb3d SG |
1174 | if (rxstat & RX_STS_MCAST_) |
1175 | dev->stats.multicast++; | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | /* Quickly dumps bad packets */ | |
1180 | static void | |
3c5e979b | 1181 | smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords) |
fd9abb3d | 1182 | { |
fd9abb3d SG |
1183 | if (likely(pktwords >= 4)) { |
1184 | unsigned int timeout = 500; | |
1185 | unsigned int val; | |
1186 | smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_); | |
1187 | do { | |
1188 | udelay(1); | |
1189 | val = smsc911x_reg_read(pdata, RX_DP_CTRL); | |
8dacd548 | 1190 | } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout); |
fd9abb3d SG |
1191 | |
1192 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1193 | SMSC_WARN(pdata, hw, "Timed out waiting for " |
1194 | "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val); | |
fd9abb3d SG |
1195 | } else { |
1196 | unsigned int temp; | |
1197 | while (pktwords--) | |
1198 | temp = smsc911x_reg_read(pdata, RX_DATA_FIFO); | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | /* NAPI poll function */ | |
1203 | static int smsc911x_poll(struct napi_struct *napi, int budget) | |
1204 | { | |
1205 | struct smsc911x_data *pdata = | |
1206 | container_of(napi, struct smsc911x_data, napi); | |
1207 | struct net_device *dev = pdata->dev; | |
1208 | int npackets = 0; | |
1209 | ||
f88c5b98 | 1210 | while (npackets < budget) { |
fd9abb3d SG |
1211 | unsigned int pktlength; |
1212 | unsigned int pktwords; | |
1213 | struct sk_buff *skb; | |
1214 | unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata); | |
1215 | ||
1216 | if (!rxstat) { | |
1217 | unsigned int temp; | |
1218 | /* We processed all packets available. Tell NAPI it can | |
1219 | * stop polling then re-enable rx interrupts */ | |
1220 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_); | |
288379f0 | 1221 | napi_complete(napi); |
fd9abb3d SG |
1222 | temp = smsc911x_reg_read(pdata, INT_EN); |
1223 | temp |= INT_EN_RSFL_EN_; | |
1224 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1225 | break; | |
1226 | } | |
1227 | ||
1228 | /* Count packet for NAPI scheduling, even if it has an error. | |
1229 | * Error packets still require cycles to discard */ | |
1230 | npackets++; | |
1231 | ||
1232 | pktlength = ((rxstat & 0x3FFF0000) >> 16); | |
1233 | pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2; | |
1234 | smsc911x_rx_counterrors(dev, rxstat); | |
1235 | ||
1236 | if (unlikely(rxstat & RX_STS_ES_)) { | |
dffc6b24 JP |
1237 | SMSC_WARN(pdata, rx_err, |
1238 | "Discarding packet with error bit set"); | |
fd9abb3d SG |
1239 | /* Packet has an error, discard it and continue with |
1240 | * the next */ | |
1241 | smsc911x_rx_fastforward(pdata, pktwords); | |
1242 | dev->stats.rx_dropped++; | |
1243 | continue; | |
1244 | } | |
1245 | ||
3c5e979b | 1246 | skb = netdev_alloc_skb(dev, pktwords << 2); |
fd9abb3d | 1247 | if (unlikely(!skb)) { |
dffc6b24 JP |
1248 | SMSC_WARN(pdata, rx_err, |
1249 | "Unable to allocate skb for rx packet"); | |
fd9abb3d SG |
1250 | /* Drop the packet and stop this polling iteration */ |
1251 | smsc911x_rx_fastforward(pdata, pktwords); | |
1252 | dev->stats.rx_dropped++; | |
1253 | break; | |
1254 | } | |
1255 | ||
3c5e979b WD |
1256 | pdata->ops->rx_readfifo(pdata, |
1257 | (unsigned int *)skb->data, pktwords); | |
fd9abb3d SG |
1258 | |
1259 | /* Align IP on 16B boundary */ | |
1260 | skb_reserve(skb, NET_IP_ALIGN); | |
1261 | skb_put(skb, pktlength - 4); | |
fd9abb3d | 1262 | skb->protocol = eth_type_trans(skb, dev); |
bc8acf2c | 1263 | skb_checksum_none_assert(skb); |
fd9abb3d SG |
1264 | netif_receive_skb(skb); |
1265 | ||
1266 | /* Update counters */ | |
1267 | dev->stats.rx_packets++; | |
1268 | dev->stats.rx_bytes += (pktlength - 4); | |
fd9abb3d SG |
1269 | } |
1270 | ||
1271 | /* Return total received packets */ | |
1272 | return npackets; | |
1273 | } | |
1274 | ||
1275 | /* Returns hash bit number for given MAC address | |
1276 | * Example: | |
1277 | * 01 00 5E 00 00 01 -> returns bit number 31 */ | |
1278 | static unsigned int smsc911x_hash(char addr[ETH_ALEN]) | |
1279 | { | |
1280 | return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; | |
1281 | } | |
1282 | ||
1283 | static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata) | |
1284 | { | |
1285 | /* Performs the multicast & mac_cr update. This is called when | |
1286 | * safe on the current hardware, and with the mac_lock held */ | |
1287 | unsigned int mac_cr; | |
1288 | ||
1289 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1290 | ||
1291 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1292 | mac_cr |= pdata->set_bits_mask; | |
1293 | mac_cr &= ~(pdata->clear_bits_mask); | |
1294 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1295 | smsc911x_mac_write(pdata, HASHH, pdata->hashhi); | |
1296 | smsc911x_mac_write(pdata, HASHL, pdata->hashlo); | |
dffc6b24 JP |
1297 | SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X", |
1298 | mac_cr, pdata->hashhi, pdata->hashlo); | |
fd9abb3d SG |
1299 | } |
1300 | ||
1301 | static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata) | |
1302 | { | |
1303 | unsigned int mac_cr; | |
1304 | ||
1305 | /* This function is only called for older LAN911x devices | |
1306 | * (revA or revB), where MAC_CR, HASHH and HASHL should not | |
1307 | * be modified during Rx - newer devices immediately update the | |
1308 | * registers. | |
1309 | * | |
1310 | * This is called from interrupt context */ | |
1311 | ||
1312 | spin_lock(&pdata->mac_lock); | |
1313 | ||
1314 | /* Check Rx has stopped */ | |
1315 | if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_) | |
dffc6b24 | 1316 | SMSC_WARN(pdata, drv, "Rx not stopped"); |
fd9abb3d SG |
1317 | |
1318 | /* Perform the update - safe to do now Rx has stopped */ | |
1319 | smsc911x_rx_multicast_update(pdata); | |
1320 | ||
1321 | /* Re-enable Rx */ | |
1322 | mac_cr = smsc911x_mac_read(pdata, MAC_CR); | |
1323 | mac_cr |= MAC_CR_RXEN_; | |
1324 | smsc911x_mac_write(pdata, MAC_CR, mac_cr); | |
1325 | ||
1326 | pdata->multicast_update_pending = 0; | |
1327 | ||
1328 | spin_unlock(&pdata->mac_lock); | |
1329 | } | |
1330 | ||
ccf899a2 EBS |
1331 | static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata) |
1332 | { | |
f788e322 PR |
1333 | struct net_device *ndev = pdata->dev; |
1334 | struct phy_device *phy_dev = ndev->phydev; | |
ccf899a2 EBS |
1335 | int rc = 0; |
1336 | ||
f788e322 | 1337 | if (!phy_dev) |
ccf899a2 EBS |
1338 | return rc; |
1339 | ||
1340 | /* If the internal PHY is in General Power-Down mode, all, except the | |
1341 | * management interface, is powered-down and stays in that condition as | |
1342 | * long as Phy register bit 0.11 is HIGH. | |
1343 | * | |
1344 | * In that case, clear the bit 0.11, so the PHY powers up and we can | |
1345 | * access to the phy registers. | |
1346 | */ | |
f788e322 | 1347 | rc = phy_read(phy_dev, MII_BMCR); |
ccf899a2 EBS |
1348 | if (rc < 0) { |
1349 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1350 | return rc; | |
1351 | } | |
1352 | ||
1353 | /* If the PHY general power-down bit is not set is not necessary to | |
1354 | * disable the general power down-mode. | |
1355 | */ | |
1356 | if (rc & BMCR_PDOWN) { | |
f788e322 | 1357 | rc = phy_write(phy_dev, MII_BMCR, rc & ~BMCR_PDOWN); |
ccf899a2 EBS |
1358 | if (rc < 0) { |
1359 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1360 | return rc; | |
1361 | } | |
1362 | ||
1363 | usleep_range(1000, 1500); | |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
6386994e JMC |
1369 | static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata) |
1370 | { | |
f788e322 PR |
1371 | struct net_device *ndev = pdata->dev; |
1372 | struct phy_device *phy_dev = ndev->phydev; | |
6386994e JMC |
1373 | int rc = 0; |
1374 | ||
f788e322 | 1375 | if (!phy_dev) |
6386994e JMC |
1376 | return rc; |
1377 | ||
f788e322 | 1378 | rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS); |
6386994e JMC |
1379 | |
1380 | if (rc < 0) { | |
1381 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1382 | return rc; | |
1383 | } | |
1384 | ||
242bcd5b AK |
1385 | /* Only disable if energy detect mode is already enabled */ |
1386 | if (rc & MII_LAN83C185_EDPWRDOWN) { | |
6386994e | 1387 | /* Disable energy detect mode for this SMSC Transceivers */ |
f788e322 | 1388 | rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS, |
6386994e JMC |
1389 | rc & (~MII_LAN83C185_EDPWRDOWN)); |
1390 | ||
1391 | if (rc < 0) { | |
1392 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1393 | return rc; | |
1394 | } | |
6ff53fd3 AK |
1395 | /* Allow PHY to wakeup */ |
1396 | mdelay(2); | |
6386994e JMC |
1397 | } |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata) | |
1403 | { | |
f788e322 PR |
1404 | struct net_device *ndev = pdata->dev; |
1405 | struct phy_device *phy_dev = ndev->phydev; | |
6386994e JMC |
1406 | int rc = 0; |
1407 | ||
f788e322 | 1408 | if (!phy_dev) |
6386994e JMC |
1409 | return rc; |
1410 | ||
f788e322 | 1411 | rc = phy_read(phy_dev, MII_LAN83C185_CTRL_STATUS); |
6386994e JMC |
1412 | |
1413 | if (rc < 0) { | |
1414 | SMSC_WARN(pdata, drv, "Failed reading PHY control reg"); | |
1415 | return rc; | |
1416 | } | |
1417 | ||
1418 | /* Only enable if energy detect mode is already disabled */ | |
1419 | if (!(rc & MII_LAN83C185_EDPWRDOWN)) { | |
6386994e | 1420 | /* Enable energy detect mode for this SMSC Transceivers */ |
f788e322 | 1421 | rc = phy_write(phy_dev, MII_LAN83C185_CTRL_STATUS, |
6386994e JMC |
1422 | rc | MII_LAN83C185_EDPWRDOWN); |
1423 | ||
1424 | if (rc < 0) { | |
1425 | SMSC_WARN(pdata, drv, "Failed writing PHY control reg"); | |
1426 | return rc; | |
1427 | } | |
6386994e JMC |
1428 | } |
1429 | return 0; | |
1430 | } | |
1431 | ||
fd9abb3d SG |
1432 | static int smsc911x_soft_reset(struct smsc911x_data *pdata) |
1433 | { | |
1434 | unsigned int timeout; | |
1435 | unsigned int temp; | |
6386994e JMC |
1436 | int ret; |
1437 | ||
ccf899a2 EBS |
1438 | /* |
1439 | * Make sure to power-up the PHY chip before doing a reset, otherwise | |
1440 | * the reset fails. | |
1441 | */ | |
1442 | ret = smsc911x_phy_general_power_up(pdata); | |
1443 | if (ret) { | |
1444 | SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip"); | |
1445 | return ret; | |
1446 | } | |
1447 | ||
6386994e JMC |
1448 | /* |
1449 | * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that | |
1450 | * are initialized in a Energy Detect Power-Down mode that prevents | |
1451 | * the MAC chip to be software reseted. So we have to wakeup the PHY | |
1452 | * before. | |
1453 | */ | |
1454 | if (pdata->generation == 4) { | |
1455 | ret = smsc911x_phy_disable_energy_detect(pdata); | |
1456 | ||
1457 | if (ret) { | |
1458 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1459 | return ret; | |
1460 | } | |
1461 | } | |
fd9abb3d SG |
1462 | |
1463 | /* Reset the LAN911x */ | |
1464 | smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); | |
1465 | timeout = 10; | |
1466 | do { | |
1467 | udelay(10); | |
1468 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1469 | } while ((--timeout) && (temp & HW_CFG_SRST_)); | |
1470 | ||
1471 | if (unlikely(temp & HW_CFG_SRST_)) { | |
dffc6b24 | 1472 | SMSC_WARN(pdata, drv, "Failed to complete reset"); |
fd9abb3d SG |
1473 | return -EIO; |
1474 | } | |
6386994e JMC |
1475 | |
1476 | if (pdata->generation == 4) { | |
1477 | ret = smsc911x_phy_enable_energy_detect(pdata); | |
1478 | ||
1479 | if (ret) { | |
1480 | SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip"); | |
1481 | return ret; | |
1482 | } | |
1483 | } | |
1484 | ||
fd9abb3d SG |
1485 | return 0; |
1486 | } | |
1487 | ||
1488 | /* Sets the device MAC address to dev_addr, called with mac_lock held */ | |
1489 | static void | |
225ddf49 | 1490 | smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6]) |
fd9abb3d SG |
1491 | { |
1492 | u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; | |
1493 | u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | | |
1494 | (dev_addr[1] << 8) | dev_addr[0]; | |
1495 | ||
1496 | SMSC_ASSERT_MAC_LOCK(pdata); | |
1497 | ||
1498 | smsc911x_mac_write(pdata, ADDRH, mac_high16); | |
1499 | smsc911x_mac_write(pdata, ADDRL, mac_low32); | |
1500 | } | |
1501 | ||
8e27628e MB |
1502 | static void smsc911x_disable_irq_chip(struct net_device *dev) |
1503 | { | |
1504 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1505 | ||
1506 | smsc911x_reg_write(pdata, INT_EN, 0); | |
1507 | smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF); | |
1508 | } | |
1509 | ||
a85f00c3 JL |
1510 | static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id) |
1511 | { | |
1512 | struct net_device *dev = dev_id; | |
1513 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1514 | u32 intsts = smsc911x_reg_read(pdata, INT_STS); | |
1515 | u32 inten = smsc911x_reg_read(pdata, INT_EN); | |
1516 | int serviced = IRQ_NONE; | |
1517 | u32 temp; | |
1518 | ||
1519 | if (unlikely(intsts & inten & INT_STS_SW_INT_)) { | |
1520 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1521 | temp &= (~INT_EN_SW_INT_EN_); | |
1522 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1523 | smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_); | |
1524 | pdata->software_irq_signal = 1; | |
1525 | smp_wmb(); | |
1526 | serviced = IRQ_HANDLED; | |
1527 | } | |
1528 | ||
1529 | if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) { | |
1530 | /* Called when there is a multicast update scheduled and | |
1531 | * it is now safe to complete the update */ | |
1532 | SMSC_TRACE(pdata, intr, "RX Stop interrupt"); | |
1533 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_); | |
1534 | if (pdata->multicast_update_pending) | |
1535 | smsc911x_rx_multicast_update_workaround(pdata); | |
1536 | serviced = IRQ_HANDLED; | |
1537 | } | |
1538 | ||
1539 | if (intsts & inten & INT_STS_TDFA_) { | |
1540 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1541 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1542 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1543 | smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_); | |
1544 | netif_wake_queue(dev); | |
1545 | serviced = IRQ_HANDLED; | |
1546 | } | |
1547 | ||
1548 | if (unlikely(intsts & inten & INT_STS_RXE_)) { | |
1549 | SMSC_TRACE(pdata, intr, "RX Error interrupt"); | |
1550 | smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_); | |
1551 | serviced = IRQ_HANDLED; | |
1552 | } | |
1553 | ||
1554 | if (likely(intsts & inten & INT_STS_RSFL_)) { | |
1555 | if (likely(napi_schedule_prep(&pdata->napi))) { | |
1556 | /* Disable Rx interrupts */ | |
1557 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1558 | temp &= (~INT_EN_RSFL_EN_); | |
1559 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1560 | /* Schedule a NAPI poll */ | |
1561 | __napi_schedule(&pdata->napi); | |
1562 | } else { | |
1563 | SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed"); | |
1564 | } | |
1565 | serviced = IRQ_HANDLED; | |
1566 | } | |
1567 | ||
1568 | return serviced; | |
1569 | } | |
1570 | ||
fd9abb3d SG |
1571 | static int smsc911x_open(struct net_device *dev) |
1572 | { | |
1573 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1574 | unsigned int timeout; | |
1575 | unsigned int temp; | |
1576 | unsigned int intcfg; | |
1358bd5a | 1577 | int retval; |
f252974e | 1578 | int irq_flags; |
fd9abb3d | 1579 | |
aea95dd5 | 1580 | /* find and start the given phy */ |
f788e322 | 1581 | if (!dev->phydev) { |
aea95dd5 JL |
1582 | retval = smsc911x_mii_probe(dev); |
1583 | if (retval < 0) { | |
1584 | SMSC_WARN(pdata, probe, "Error starting phy"); | |
1585 | goto out; | |
1586 | } | |
fd9abb3d SG |
1587 | } |
1588 | ||
fd9abb3d | 1589 | /* Reset the LAN911x */ |
1358bd5a JL |
1590 | retval = smsc911x_soft_reset(pdata); |
1591 | if (retval) { | |
dffc6b24 | 1592 | SMSC_WARN(pdata, hw, "soft reset failed"); |
aea95dd5 | 1593 | goto mii_free_out; |
fd9abb3d SG |
1594 | } |
1595 | ||
1596 | smsc911x_reg_write(pdata, HW_CFG, 0x00050000); | |
1597 | smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740); | |
1598 | ||
f277e65e GW |
1599 | /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */ |
1600 | spin_lock_irq(&pdata->mac_lock); | |
1601 | smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q); | |
1602 | spin_unlock_irq(&pdata->mac_lock); | |
1603 | ||
fd9abb3d SG |
1604 | /* Make sure EEPROM has finished loading before setting GPIO_CFG */ |
1605 | timeout = 50; | |
f7efb6cc SG |
1606 | while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) && |
1607 | --timeout) { | |
fd9abb3d SG |
1608 | udelay(10); |
1609 | } | |
1610 | ||
1611 | if (unlikely(timeout == 0)) | |
dffc6b24 JP |
1612 | SMSC_WARN(pdata, ifup, |
1613 | "Timed out waiting for EEPROM busy bit to clear"); | |
fd9abb3d SG |
1614 | |
1615 | smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000); | |
1616 | ||
1617 | /* The soft reset above cleared the device's MAC address, | |
1618 | * restore it from local copy (set in probe) */ | |
1619 | spin_lock_irq(&pdata->mac_lock); | |
225ddf49 | 1620 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
fd9abb3d SG |
1621 | spin_unlock_irq(&pdata->mac_lock); |
1622 | ||
1623 | /* Initialise irqs, but leave all sources disabled */ | |
8e27628e | 1624 | smsc911x_disable_irq_chip(dev); |
fd9abb3d SG |
1625 | |
1626 | /* Set interrupt deassertion to 100uS */ | |
1627 | intcfg = ((10 << 24) | INT_CFG_IRQ_EN_); | |
1628 | ||
2107fb8b | 1629 | if (pdata->config.irq_polarity) { |
dffc6b24 | 1630 | SMSC_TRACE(pdata, ifup, "irq polarity: active high"); |
fd9abb3d SG |
1631 | intcfg |= INT_CFG_IRQ_POL_; |
1632 | } else { | |
dffc6b24 | 1633 | SMSC_TRACE(pdata, ifup, "irq polarity: active low"); |
fd9abb3d SG |
1634 | } |
1635 | ||
2107fb8b | 1636 | if (pdata->config.irq_type) { |
dffc6b24 | 1637 | SMSC_TRACE(pdata, ifup, "irq type: push-pull"); |
fd9abb3d SG |
1638 | intcfg |= INT_CFG_IRQ_TYPE_; |
1639 | } else { | |
dffc6b24 | 1640 | SMSC_TRACE(pdata, ifup, "irq type: open drain"); |
fd9abb3d SG |
1641 | } |
1642 | ||
1643 | smsc911x_reg_write(pdata, INT_CFG, intcfg); | |
1644 | ||
dffc6b24 | 1645 | SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq); |
fd9abb3d SG |
1646 | pdata->software_irq_signal = 0; |
1647 | smp_wmb(); | |
1648 | ||
f252974e JL |
1649 | irq_flags = irq_get_trigger_type(dev->irq); |
1650 | retval = request_irq(dev->irq, smsc911x_irqhandler, | |
1651 | irq_flags | IRQF_SHARED, dev->name, dev); | |
1652 | if (retval) { | |
1653 | SMSC_WARN(pdata, probe, | |
1654 | "Unable to claim requested irq: %d", dev->irq); | |
1655 | goto mii_free_out; | |
1656 | } | |
1657 | ||
fd9abb3d SG |
1658 | temp = smsc911x_reg_read(pdata, INT_EN); |
1659 | temp |= INT_EN_SW_INT_EN_; | |
1660 | smsc911x_reg_write(pdata, INT_EN, temp); | |
1661 | ||
1662 | timeout = 1000; | |
1663 | while (timeout--) { | |
1664 | if (pdata->software_irq_signal) | |
1665 | break; | |
1666 | msleep(1); | |
1667 | } | |
1668 | ||
1669 | if (!pdata->software_irq_signal) { | |
dffc6b24 JP |
1670 | netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n", |
1671 | dev->irq); | |
1358bd5a | 1672 | retval = -ENODEV; |
f252974e | 1673 | goto irq_stop_out; |
fd9abb3d | 1674 | } |
dffc6b24 JP |
1675 | SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d", |
1676 | dev->irq); | |
fd9abb3d | 1677 | |
dffc6b24 JP |
1678 | netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
1679 | (unsigned long)pdata->ioaddr, dev->irq); | |
fd9abb3d | 1680 | |
44c1d6f9 SG |
1681 | /* Reset the last known duplex and carrier */ |
1682 | pdata->last_duplex = -1; | |
1683 | pdata->last_carrier = -1; | |
1684 | ||
fd9abb3d | 1685 | /* Bring the PHY up */ |
f788e322 | 1686 | phy_start(dev->phydev); |
fd9abb3d SG |
1687 | |
1688 | temp = smsc911x_reg_read(pdata, HW_CFG); | |
1689 | /* Preserve TX FIFO size and external PHY configuration */ | |
1690 | temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF); | |
1691 | temp |= HW_CFG_SF_; | |
1692 | smsc911x_reg_write(pdata, HW_CFG, temp); | |
1693 | ||
1694 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1695 | temp |= FIFO_INT_TX_AVAIL_LEVEL_; | |
1696 | temp &= ~(FIFO_INT_RX_STS_LEVEL_); | |
1697 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1698 | ||
1699 | /* set RX Data offset to 2 bytes for alignment */ | |
3c5e979b | 1700 | smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8)); |
fd9abb3d SG |
1701 | |
1702 | /* enable NAPI polling before enabling RX interrupts */ | |
1703 | napi_enable(&pdata->napi); | |
1704 | ||
1705 | temp = smsc911x_reg_read(pdata, INT_EN); | |
1373c0fd | 1706 | temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_); |
fd9abb3d SG |
1707 | smsc911x_reg_write(pdata, INT_EN, temp); |
1708 | ||
1709 | spin_lock_irq(&pdata->mac_lock); | |
1710 | temp = smsc911x_mac_read(pdata, MAC_CR); | |
1711 | temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); | |
1712 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1713 | spin_unlock_irq(&pdata->mac_lock); | |
1714 | ||
1715 | smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_); | |
1716 | ||
1717 | netif_start_queue(dev); | |
1718 | return 0; | |
aea95dd5 | 1719 | |
f252974e JL |
1720 | irq_stop_out: |
1721 | free_irq(dev->irq, dev); | |
aea95dd5 JL |
1722 | mii_free_out: |
1723 | phy_disconnect(dev->phydev); | |
1724 | dev->phydev = NULL; | |
1358bd5a JL |
1725 | out: |
1726 | return retval; | |
fd9abb3d SG |
1727 | } |
1728 | ||
1729 | /* Entry point for stopping the interface */ | |
1730 | static int smsc911x_stop(struct net_device *dev) | |
1731 | { | |
1732 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1733 | unsigned int temp; | |
1734 | ||
fd9abb3d SG |
1735 | /* Disable all device interrupts */ |
1736 | temp = smsc911x_reg_read(pdata, INT_CFG); | |
1737 | temp &= ~INT_CFG_IRQ_EN_; | |
1738 | smsc911x_reg_write(pdata, INT_CFG, temp); | |
1739 | ||
1740 | /* Stop Tx and Rx polling */ | |
1741 | netif_stop_queue(dev); | |
1742 | napi_disable(&pdata->napi); | |
1743 | ||
1744 | /* At this point all Rx and Tx activity is stopped */ | |
1745 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1746 | smsc911x_tx_update_txcounters(dev); | |
1747 | ||
f252974e JL |
1748 | free_irq(dev->irq, dev); |
1749 | ||
fd9abb3d | 1750 | /* Bring the PHY down */ |
aea95dd5 | 1751 | if (dev->phydev) { |
f788e322 | 1752 | phy_stop(dev->phydev); |
aea95dd5 JL |
1753 | phy_disconnect(dev->phydev); |
1754 | dev->phydev = NULL; | |
1755 | } | |
1756 | netif_carrier_off(dev); | |
fd9abb3d | 1757 | |
dffc6b24 | 1758 | SMSC_TRACE(pdata, ifdown, "Interface stopped"); |
fd9abb3d SG |
1759 | return 0; |
1760 | } | |
1761 | ||
1762 | /* Entry point for transmitting a packet */ | |
1763 | static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1764 | { | |
1765 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1766 | unsigned int freespace; | |
1767 | unsigned int tx_cmd_a; | |
1768 | unsigned int tx_cmd_b; | |
1769 | unsigned int temp; | |
1770 | u32 wrsz; | |
1771 | ulong bufp; | |
1772 | ||
1773 | freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_; | |
1774 | ||
1775 | if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD)) | |
dffc6b24 JP |
1776 | SMSC_WARN(pdata, tx_err, |
1777 | "Tx data fifo low, space available: %d", freespace); | |
fd9abb3d SG |
1778 | |
1779 | /* Word alignment adjustment */ | |
1780 | tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16; | |
1781 | tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; | |
1782 | tx_cmd_a |= (unsigned int)skb->len; | |
1783 | ||
1784 | tx_cmd_b = ((unsigned int)skb->len) << 16; | |
1785 | tx_cmd_b |= (unsigned int)skb->len; | |
1786 | ||
1787 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a); | |
1788 | smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b); | |
1789 | ||
1790 | bufp = (ulong)skb->data & (~0x3); | |
1791 | wrsz = (u32)skb->len + 3; | |
1792 | wrsz += (u32)((ulong)skb->data & 0x3); | |
1793 | wrsz >>= 2; | |
1794 | ||
c326de88 | 1795 | pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz); |
fd9abb3d | 1796 | freespace -= (skb->len + 32); |
8c0069ae | 1797 | skb_tx_timestamp(skb); |
89a9eb63 | 1798 | dev_consume_skb_any(skb); |
fd9abb3d SG |
1799 | |
1800 | if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30)) | |
1801 | smsc911x_tx_update_txcounters(dev); | |
1802 | ||
1803 | if (freespace < TX_FIFO_LOW_THRESHOLD) { | |
1804 | netif_stop_queue(dev); | |
1805 | temp = smsc911x_reg_read(pdata, FIFO_INT); | |
1806 | temp &= 0x00FFFFFF; | |
1807 | temp |= 0x32000000; | |
1808 | smsc911x_reg_write(pdata, FIFO_INT, temp); | |
1809 | } | |
1810 | ||
1811 | return NETDEV_TX_OK; | |
1812 | } | |
1813 | ||
1814 | /* Entry point for getting status counters */ | |
1815 | static struct net_device_stats *smsc911x_get_stats(struct net_device *dev) | |
1816 | { | |
1817 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1818 | smsc911x_tx_update_txcounters(dev); | |
1819 | dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP); | |
1820 | return &dev->stats; | |
1821 | } | |
1822 | ||
1823 | /* Entry point for setting addressing modes */ | |
1824 | static void smsc911x_set_multicast_list(struct net_device *dev) | |
1825 | { | |
1826 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1827 | unsigned long flags; | |
1828 | ||
1829 | if (dev->flags & IFF_PROMISC) { | |
1830 | /* Enabling promiscuous mode */ | |
1831 | pdata->set_bits_mask = MAC_CR_PRMS_; | |
1832 | pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1833 | pdata->hashhi = 0; | |
1834 | pdata->hashlo = 0; | |
1835 | } else if (dev->flags & IFF_ALLMULTI) { | |
1836 | /* Enabling all multicast mode */ | |
1837 | pdata->set_bits_mask = MAC_CR_MCPAS_; | |
1838 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); | |
1839 | pdata->hashhi = 0; | |
1840 | pdata->hashlo = 0; | |
4cd24eaf | 1841 | } else if (!netdev_mc_empty(dev)) { |
fd9abb3d SG |
1842 | /* Enabling specific multicast addresses */ |
1843 | unsigned int hash_high = 0; | |
1844 | unsigned int hash_low = 0; | |
22bedad3 | 1845 | struct netdev_hw_addr *ha; |
fd9abb3d SG |
1846 | |
1847 | pdata->set_bits_mask = MAC_CR_HPFILT_; | |
1848 | pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); | |
1849 | ||
22bedad3 JP |
1850 | netdev_for_each_mc_addr(ha, dev) { |
1851 | unsigned int bitnum = smsc911x_hash(ha->addr); | |
2a0d18f9 JP |
1852 | unsigned int mask = 0x01 << (bitnum & 0x1F); |
1853 | ||
1854 | if (bitnum & 0x20) | |
1855 | hash_high |= mask; | |
1856 | else | |
1857 | hash_low |= mask; | |
fd9abb3d | 1858 | } |
fd9abb3d SG |
1859 | |
1860 | pdata->hashhi = hash_high; | |
1861 | pdata->hashlo = hash_low; | |
1862 | } else { | |
1863 | /* Enabling local MAC address only */ | |
1864 | pdata->set_bits_mask = 0; | |
1865 | pdata->clear_bits_mask = | |
1866 | (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); | |
1867 | pdata->hashhi = 0; | |
1868 | pdata->hashlo = 0; | |
1869 | } | |
1870 | ||
1871 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1872 | ||
1873 | if (pdata->generation <= 1) { | |
1874 | /* Older hardware revision - cannot change these flags while | |
1875 | * receiving data */ | |
1876 | if (!pdata->multicast_update_pending) { | |
1877 | unsigned int temp; | |
dffc6b24 | 1878 | SMSC_TRACE(pdata, hw, "scheduling mcast update"); |
fd9abb3d SG |
1879 | pdata->multicast_update_pending = 1; |
1880 | ||
1881 | /* Request the hardware to stop, then perform the | |
1882 | * update when we get an RX_STOP interrupt */ | |
fd9abb3d SG |
1883 | temp = smsc911x_mac_read(pdata, MAC_CR); |
1884 | temp &= ~(MAC_CR_RXEN_); | |
1885 | smsc911x_mac_write(pdata, MAC_CR, temp); | |
1886 | } else { | |
1887 | /* There is another update pending, this should now | |
1888 | * use the newer values */ | |
1889 | } | |
1890 | } else { | |
1891 | /* Newer hardware revision - can write immediately */ | |
1892 | smsc911x_rx_multicast_update(pdata); | |
1893 | } | |
1894 | ||
1895 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1896 | } | |
1897 | ||
fd9abb3d | 1898 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1757ab2f | 1899 | static void smsc911x_poll_controller(struct net_device *dev) |
fd9abb3d SG |
1900 | { |
1901 | disable_irq(dev->irq); | |
1902 | smsc911x_irqhandler(0, dev); | |
1903 | enable_irq(dev->irq); | |
1904 | } | |
1905 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1906 | ||
225ddf49 SG |
1907 | static int smsc911x_set_mac_address(struct net_device *dev, void *p) |
1908 | { | |
1909 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1910 | struct sockaddr *addr = p; | |
1911 | ||
1912 | /* On older hardware revisions we cannot change the mac address | |
1913 | * registers while receiving data. Newer devices can safely change | |
1914 | * this at any time. */ | |
1915 | if (pdata->generation <= 1 && netif_running(dev)) | |
1916 | return -EBUSY; | |
1917 | ||
1918 | if (!is_valid_ether_addr(addr->sa_data)) | |
1919 | return -EADDRNOTAVAIL; | |
1920 | ||
1921 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
1922 | ||
1923 | spin_lock_irq(&pdata->mac_lock); | |
1924 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); | |
1925 | spin_unlock_irq(&pdata->mac_lock); | |
1926 | ||
dffc6b24 | 1927 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
225ddf49 SG |
1928 | |
1929 | return 0; | |
1930 | } | |
1931 | ||
fd9abb3d SG |
1932 | /* Standard ioctls for mii-tool */ |
1933 | static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1934 | { | |
f788e322 | 1935 | if (!netif_running(dev) || !dev->phydev) |
fd9abb3d SG |
1936 | return -EINVAL; |
1937 | ||
f788e322 | 1938 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
fd9abb3d SG |
1939 | } |
1940 | ||
fd9abb3d SG |
1941 | static void smsc911x_ethtool_getdrvinfo(struct net_device *dev, |
1942 | struct ethtool_drvinfo *info) | |
1943 | { | |
1944 | strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver)); | |
1945 | strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version)); | |
db1d7bf7 | 1946 | strlcpy(info->bus_info, dev_name(dev->dev.parent), |
fd9abb3d SG |
1947 | sizeof(info->bus_info)); |
1948 | } | |
1949 | ||
1950 | static int smsc911x_ethtool_nwayreset(struct net_device *dev) | |
1951 | { | |
f788e322 | 1952 | return phy_start_aneg(dev->phydev); |
fd9abb3d SG |
1953 | } |
1954 | ||
1955 | static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev) | |
1956 | { | |
1957 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1958 | return pdata->msg_enable; | |
1959 | } | |
1960 | ||
1961 | static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level) | |
1962 | { | |
1963 | struct smsc911x_data *pdata = netdev_priv(dev); | |
1964 | pdata->msg_enable = level; | |
1965 | } | |
1966 | ||
1967 | static int smsc911x_ethtool_getregslen(struct net_device *dev) | |
1968 | { | |
1969 | return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) * | |
1970 | sizeof(u32); | |
1971 | } | |
1972 | ||
1973 | static void | |
1974 | smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, | |
1975 | void *buf) | |
1976 | { | |
1977 | struct smsc911x_data *pdata = netdev_priv(dev); | |
f788e322 | 1978 | struct phy_device *phy_dev = dev->phydev; |
fd9abb3d SG |
1979 | unsigned long flags; |
1980 | unsigned int i; | |
1981 | unsigned int j = 0; | |
1982 | u32 *data = buf; | |
1983 | ||
1984 | regs->version = pdata->idrev; | |
1985 | for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32))) | |
1986 | data[j++] = smsc911x_reg_read(pdata, i); | |
1987 | ||
1988 | for (i = MAC_CR; i <= WUCSR; i++) { | |
1989 | spin_lock_irqsave(&pdata->mac_lock, flags); | |
1990 | data[j++] = smsc911x_mac_read(pdata, i); | |
1991 | spin_unlock_irqrestore(&pdata->mac_lock, flags); | |
1992 | } | |
1993 | ||
1994 | for (i = 0; i <= 31; i++) | |
e5a03bfd AL |
1995 | data[j++] = smsc911x_mii_read(phy_dev->mdio.bus, |
1996 | phy_dev->mdio.addr, i); | |
fd9abb3d SG |
1997 | } |
1998 | ||
1999 | static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata) | |
2000 | { | |
2001 | unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG); | |
2002 | temp &= ~GPIO_CFG_EEPR_EN_; | |
2003 | smsc911x_reg_write(pdata, GPIO_CFG, temp); | |
2004 | msleep(1); | |
2005 | } | |
2006 | ||
2007 | static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op) | |
2008 | { | |
2009 | int timeout = 100; | |
2010 | u32 e2cmd; | |
2011 | ||
dffc6b24 | 2012 | SMSC_TRACE(pdata, drv, "op 0x%08x", op); |
fd9abb3d | 2013 | if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) { |
dffc6b24 | 2014 | SMSC_WARN(pdata, drv, "Busy at start"); |
fd9abb3d SG |
2015 | return -EBUSY; |
2016 | } | |
2017 | ||
2018 | e2cmd = op | E2P_CMD_EPC_BUSY_; | |
2019 | smsc911x_reg_write(pdata, E2P_CMD, e2cmd); | |
2020 | ||
2021 | do { | |
2022 | msleep(1); | |
2023 | e2cmd = smsc911x_reg_read(pdata, E2P_CMD); | |
2cf0dbed | 2024 | } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); |
fd9abb3d SG |
2025 | |
2026 | if (!timeout) { | |
dffc6b24 | 2027 | SMSC_TRACE(pdata, drv, "TIMED OUT"); |
fd9abb3d SG |
2028 | return -EAGAIN; |
2029 | } | |
2030 | ||
2031 | if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { | |
1c01a80c | 2032 | SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation"); |
fd9abb3d SG |
2033 | return -EINVAL; |
2034 | } | |
2035 | ||
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata, | |
2040 | u8 address, u8 *data) | |
2041 | { | |
2042 | u32 op = E2P_CMD_EPC_CMD_READ_ | address; | |
2043 | int ret; | |
2044 | ||
dffc6b24 | 2045 | SMSC_TRACE(pdata, drv, "address 0x%x", address); |
fd9abb3d SG |
2046 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2047 | ||
2048 | if (!ret) | |
2049 | data[address] = smsc911x_reg_read(pdata, E2P_DATA); | |
2050 | ||
2051 | return ret; | |
2052 | } | |
2053 | ||
2054 | static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, | |
2055 | u8 address, u8 data) | |
2056 | { | |
2057 | u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; | |
58add9fc | 2058 | u32 temp; |
fd9abb3d SG |
2059 | int ret; |
2060 | ||
dffc6b24 | 2061 | SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data); |
fd9abb3d SG |
2062 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2063 | ||
2064 | if (!ret) { | |
2065 | op = E2P_CMD_EPC_CMD_WRITE_ | address; | |
2066 | smsc911x_reg_write(pdata, E2P_DATA, (u32)data); | |
58add9fc SG |
2067 | |
2068 | /* Workaround for hardware read-after-write restriction */ | |
2069 | temp = smsc911x_reg_read(pdata, BYTE_TEST); | |
2070 | ||
fd9abb3d SG |
2071 | ret = smsc911x_eeprom_send_cmd(pdata, op); |
2072 | } | |
2073 | ||
2074 | return ret; | |
2075 | } | |
2076 | ||
2077 | static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev) | |
2078 | { | |
2079 | return SMSC911X_EEPROM_SIZE; | |
2080 | } | |
2081 | ||
2082 | static int smsc911x_ethtool_get_eeprom(struct net_device *dev, | |
2083 | struct ethtool_eeprom *eeprom, u8 *data) | |
2084 | { | |
2085 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2086 | u8 eeprom_data[SMSC911X_EEPROM_SIZE]; | |
2087 | int len; | |
2088 | int i; | |
2089 | ||
2090 | smsc911x_eeprom_enable_access(pdata); | |
2091 | ||
2092 | len = min(eeprom->len, SMSC911X_EEPROM_SIZE); | |
2093 | for (i = 0; i < len; i++) { | |
2094 | int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data); | |
2095 | if (ret < 0) { | |
2096 | eeprom->len = 0; | |
2097 | return ret; | |
2098 | } | |
2099 | } | |
2100 | ||
2101 | memcpy(data, &eeprom_data[eeprom->offset], len); | |
2102 | eeprom->len = len; | |
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | static int smsc911x_ethtool_set_eeprom(struct net_device *dev, | |
2107 | struct ethtool_eeprom *eeprom, u8 *data) | |
2108 | { | |
2109 | int ret; | |
2110 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2111 | ||
2112 | smsc911x_eeprom_enable_access(pdata); | |
2113 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_); | |
2114 | ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data); | |
2115 | smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_); | |
2116 | ||
2117 | /* Single byte write, according to man page */ | |
2118 | eeprom->len = 1; | |
2119 | ||
2120 | return ret; | |
2121 | } | |
2122 | ||
cb5b04fe | 2123 | static const struct ethtool_ops smsc911x_ethtool_ops = { |
fd9abb3d SG |
2124 | .get_link = ethtool_op_get_link, |
2125 | .get_drvinfo = smsc911x_ethtool_getdrvinfo, | |
2126 | .nway_reset = smsc911x_ethtool_nwayreset, | |
2127 | .get_msglevel = smsc911x_ethtool_getmsglevel, | |
2128 | .set_msglevel = smsc911x_ethtool_setmsglevel, | |
2129 | .get_regs_len = smsc911x_ethtool_getregslen, | |
2130 | .get_regs = smsc911x_ethtool_getregs, | |
2131 | .get_eeprom_len = smsc911x_ethtool_get_eeprom_len, | |
2132 | .get_eeprom = smsc911x_ethtool_get_eeprom, | |
2133 | .set_eeprom = smsc911x_ethtool_set_eeprom, | |
b5d1d256 | 2134 | .get_ts_info = ethtool_op_get_ts_info, |
2c087409 PR |
2135 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
2136 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
fd9abb3d SG |
2137 | }; |
2138 | ||
631b7568 SG |
2139 | static const struct net_device_ops smsc911x_netdev_ops = { |
2140 | .ndo_open = smsc911x_open, | |
2141 | .ndo_stop = smsc911x_stop, | |
2142 | .ndo_start_xmit = smsc911x_hard_start_xmit, | |
2143 | .ndo_get_stats = smsc911x_get_stats, | |
afc4b13d | 2144 | .ndo_set_rx_mode = smsc911x_set_multicast_list, |
631b7568 | 2145 | .ndo_do_ioctl = smsc911x_do_ioctl, |
635ecaa7 | 2146 | .ndo_change_mtu = eth_change_mtu, |
631b7568 | 2147 | .ndo_validate_addr = eth_validate_addr, |
225ddf49 | 2148 | .ndo_set_mac_address = smsc911x_set_mac_address, |
631b7568 SG |
2149 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2150 | .ndo_poll_controller = smsc911x_poll_controller, | |
2151 | #endif | |
2152 | }; | |
2153 | ||
31f45747 | 2154 | /* copies the current mac address from hardware to dev->dev_addr */ |
8489ec1f | 2155 | static void smsc911x_read_mac_address(struct net_device *dev) |
31f45747 SG |
2156 | { |
2157 | struct smsc911x_data *pdata = netdev_priv(dev); | |
2158 | u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH); | |
2159 | u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL); | |
2160 | ||
2161 | dev->dev_addr[0] = (u8)(mac_low32); | |
2162 | dev->dev_addr[1] = (u8)(mac_low32 >> 8); | |
2163 | dev->dev_addr[2] = (u8)(mac_low32 >> 16); | |
2164 | dev->dev_addr[3] = (u8)(mac_low32 >> 24); | |
2165 | dev->dev_addr[4] = (u8)(mac_high16); | |
2166 | dev->dev_addr[5] = (u8)(mac_high16 >> 8); | |
2167 | } | |
2168 | ||
fd9abb3d | 2169 | /* Initializing private device structures, only called from probe */ |
8489ec1f | 2170 | static int smsc911x_init(struct net_device *dev) |
fd9abb3d SG |
2171 | { |
2172 | struct smsc911x_data *pdata = netdev_priv(dev); | |
769ce4c9 | 2173 | unsigned int byte_test, mask; |
3ac3546e | 2174 | unsigned int to = 100; |
fd9abb3d | 2175 | |
dffc6b24 JP |
2176 | SMSC_TRACE(pdata, probe, "Driver Parameters:"); |
2177 | SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX", | |
2178 | (unsigned long)pdata->ioaddr); | |
2179 | SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq); | |
2180 | SMSC_TRACE(pdata, probe, "PHY will be autodetected."); | |
fd9abb3d | 2181 | |
fd9abb3d | 2182 | spin_lock_init(&pdata->dev_lock); |
35a67edf | 2183 | spin_lock_init(&pdata->mac_lock); |
fd9abb3d | 2184 | |
6fed9592 | 2185 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2186 | SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000"); |
fd9abb3d SG |
2187 | return -ENODEV; |
2188 | } | |
2189 | ||
3ac3546e RM |
2190 | /* |
2191 | * poll the READY bit in PMT_CTRL. Any other access to the device is | |
2192 | * forbidden while this bit isn't set. Try for 100ms | |
769ce4c9 KP |
2193 | * |
2194 | * Note that this test is done before the WORD_SWAP register is | |
2195 | * programmed. So in some configurations the READY bit is at 16 before | |
2196 | * WORD_SWAP is written to. This issue is worked around by waiting | |
2197 | * until either bit 0 or bit 16 gets set in PMT_CTRL. | |
2198 | * | |
2199 | * SMSC has confirmed that checking bit 16 (marked as reserved in | |
2200 | * the datasheet) is fine since these bits "will either never be set | |
2201 | * or can only go high after READY does (so also indicate the device | |
2202 | * is ready)". | |
3ac3546e | 2203 | */ |
769ce4c9 KP |
2204 | |
2205 | mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_); | |
2206 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to) | |
3ac3546e | 2207 | udelay(1000); |
769ce4c9 | 2208 | |
3ac3546e | 2209 | if (to == 0) { |
b1a04a62 | 2210 | netdev_err(dev, "Device not READY in 100ms aborting\n"); |
3ac3546e RM |
2211 | return -ENODEV; |
2212 | } | |
2213 | ||
fd9abb3d SG |
2214 | /* Check byte ordering */ |
2215 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
dffc6b24 | 2216 | SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2217 | if (byte_test == 0x43218765) { |
dffc6b24 JP |
2218 | SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, " |
2219 | "applying WORD_SWAP"); | |
fd9abb3d SG |
2220 | smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff); |
2221 | ||
2222 | /* 1 dummy read of BYTE_TEST is needed after a write to | |
2223 | * WORD_SWAP before its contents are valid */ | |
2224 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2225 | ||
2226 | byte_test = smsc911x_reg_read(pdata, BYTE_TEST); | |
2227 | } | |
2228 | ||
2229 | if (byte_test != 0x87654321) { | |
dffc6b24 | 2230 | SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test); |
fd9abb3d | 2231 | if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) { |
dffc6b24 JP |
2232 | SMSC_WARN(pdata, probe, |
2233 | "top 16 bits equal to bottom 16 bits"); | |
2234 | SMSC_TRACE(pdata, probe, | |
2235 | "This may mean the chip is set " | |
2236 | "for 32 bit while the bus is reading 16 bit"); | |
fd9abb3d SG |
2237 | } |
2238 | return -ENODEV; | |
2239 | } | |
2240 | ||
2241 | /* Default generation to zero (all workarounds apply) */ | |
2242 | pdata->generation = 0; | |
2243 | ||
2244 | pdata->idrev = smsc911x_reg_read(pdata, ID_REV); | |
2245 | switch (pdata->idrev & 0xFFFF0000) { | |
2246 | case 0x01180000: | |
2247 | case 0x01170000: | |
2248 | case 0x01160000: | |
2249 | case 0x01150000: | |
28c21379 | 2250 | case 0x218A0000: |
fd9abb3d SG |
2251 | /* LAN911[5678] family */ |
2252 | pdata->generation = pdata->idrev & 0x0000FFFF; | |
2253 | break; | |
2254 | ||
2255 | case 0x118A0000: | |
2256 | case 0x117A0000: | |
2257 | case 0x116A0000: | |
2258 | case 0x115A0000: | |
2259 | /* LAN921[5678] family */ | |
2260 | pdata->generation = 3; | |
2261 | break; | |
2262 | ||
2263 | case 0x92100000: | |
2264 | case 0x92110000: | |
2265 | case 0x92200000: | |
2266 | case 0x92210000: | |
2267 | /* LAN9210/LAN9211/LAN9220/LAN9221 */ | |
2268 | pdata->generation = 4; | |
2269 | break; | |
2270 | ||
2271 | default: | |
dffc6b24 JP |
2272 | SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X", |
2273 | pdata->idrev); | |
fd9abb3d SG |
2274 | return -ENODEV; |
2275 | } | |
2276 | ||
dffc6b24 JP |
2277 | SMSC_TRACE(pdata, probe, |
2278 | "LAN911x identified, idrev: 0x%08X, generation: %d", | |
2279 | pdata->idrev, pdata->generation); | |
fd9abb3d SG |
2280 | |
2281 | if (pdata->generation == 0) | |
dffc6b24 JP |
2282 | SMSC_WARN(pdata, probe, |
2283 | "This driver is not intended for this chip revision"); | |
fd9abb3d | 2284 | |
31f45747 SG |
2285 | /* workaround for platforms without an eeprom, where the mac address |
2286 | * is stored elsewhere and set by the bootloader. This saves the | |
2287 | * mac address before resetting the device */ | |
35a67edf EBS |
2288 | if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) { |
2289 | spin_lock_irq(&pdata->mac_lock); | |
31f45747 | 2290 | smsc911x_read_mac_address(dev); |
35a67edf EBS |
2291 | spin_unlock_irq(&pdata->mac_lock); |
2292 | } | |
31f45747 | 2293 | |
fd9abb3d | 2294 | /* Reset the LAN911x */ |
cd998ecd | 2295 | if (smsc911x_phy_reset(pdata) || smsc911x_soft_reset(pdata)) |
fd9abb3d SG |
2296 | return -ENODEV; |
2297 | ||
fd9abb3d | 2298 | dev->flags |= IFF_MULTICAST; |
fd9abb3d | 2299 | netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT); |
631b7568 | 2300 | dev->netdev_ops = &smsc911x_netdev_ops; |
fd9abb3d SG |
2301 | dev->ethtool_ops = &smsc911x_ethtool_ops; |
2302 | ||
fd9abb3d SG |
2303 | return 0; |
2304 | } | |
2305 | ||
8489ec1f | 2306 | static int smsc911x_drv_remove(struct platform_device *pdev) |
fd9abb3d SG |
2307 | { |
2308 | struct net_device *dev; | |
2309 | struct smsc911x_data *pdata; | |
2310 | struct resource *res; | |
2311 | ||
2312 | dev = platform_get_drvdata(pdev); | |
2313 | BUG_ON(!dev); | |
2314 | pdata = netdev_priv(dev); | |
2315 | BUG_ON(!pdata); | |
2316 | BUG_ON(!pdata->ioaddr); | |
aea95dd5 | 2317 | WARN_ON(dev->phydev); |
fd9abb3d | 2318 | |
dffc6b24 | 2319 | SMSC_TRACE(pdata, ifdown, "Stopping driver"); |
fd9abb3d | 2320 | |
fd9abb3d SG |
2321 | mdiobus_unregister(pdata->mii_bus); |
2322 | mdiobus_free(pdata->mii_bus); | |
2323 | ||
fd9abb3d | 2324 | unregister_netdev(dev); |
fd9abb3d SG |
2325 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2326 | "smsc911x-memory"); | |
2327 | if (!res) | |
d4522739 | 2328 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
fd9abb3d | 2329 | |
39424539 | 2330 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2331 | |
2332 | iounmap(pdata->ioaddr); | |
2333 | ||
c7e963f6 RM |
2334 | (void)smsc911x_disable_resources(pdev); |
2335 | smsc911x_free_resources(pdev); | |
2336 | ||
fd9abb3d SG |
2337 | free_netdev(dev); |
2338 | ||
3a611e26 GU |
2339 | pm_runtime_put(&pdev->dev); |
2340 | pm_runtime_disable(&pdev->dev); | |
2341 | ||
fd9abb3d SG |
2342 | return 0; |
2343 | } | |
2344 | ||
c326de88 MP |
2345 | /* standard register acces */ |
2346 | static const struct smsc911x_ops standard_smsc911x_ops = { | |
2347 | .reg_read = __smsc911x_reg_read, | |
2348 | .reg_write = __smsc911x_reg_write, | |
2349 | .rx_readfifo = smsc911x_rx_readfifo, | |
2350 | .tx_writefifo = smsc911x_tx_writefifo, | |
2351 | }; | |
2352 | ||
2353 | /* shifted register access */ | |
2354 | static const struct smsc911x_ops shifted_smsc911x_ops = { | |
2355 | .reg_read = __smsc911x_reg_read_shift, | |
2356 | .reg_write = __smsc911x_reg_write_shift, | |
2357 | .rx_readfifo = smsc911x_rx_readfifo_shift, | |
2358 | .tx_writefifo = smsc911x_tx_writefifo_shift, | |
2359 | }; | |
2360 | ||
0b50dc4f JL |
2361 | static int smsc911x_probe_config(struct smsc911x_platform_config *config, |
2362 | struct device *dev) | |
79f88ee9 | 2363 | { |
62ee783b | 2364 | int phy_interface; |
79f88ee9 | 2365 | u32 width = 0; |
31cb5c9e | 2366 | int err; |
79f88ee9 | 2367 | |
62ee783b GR |
2368 | phy_interface = device_get_phy_mode(dev); |
2369 | if (phy_interface < 0) | |
31cb5c9e | 2370 | phy_interface = PHY_INTERFACE_MODE_NA; |
62ee783b | 2371 | config->phy_interface = phy_interface; |
79f88ee9 | 2372 | |
0b50dc4f | 2373 | device_get_mac_address(dev, config->mac, ETH_ALEN); |
79f88ee9 | 2374 | |
31cb5c9e GR |
2375 | err = device_property_read_u32(dev, "reg-io-width", &width); |
2376 | if (err == -ENXIO) | |
2377 | return err; | |
2378 | if (!err && width == 4) | |
79f88ee9 | 2379 | config->flags |= SMSC911X_USE_32BIT; |
f26cd41a DM |
2380 | else |
2381 | config->flags |= SMSC911X_USE_16BIT; | |
79f88ee9 | 2382 | |
31cb5c9e GR |
2383 | device_property_read_u32(dev, "reg-shift", &config->shift); |
2384 | ||
0b50dc4f | 2385 | if (device_property_present(dev, "smsc,irq-active-high")) |
79f88ee9 SG |
2386 | config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH; |
2387 | ||
0b50dc4f | 2388 | if (device_property_present(dev, "smsc,irq-push-pull")) |
79f88ee9 SG |
2389 | config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL; |
2390 | ||
0b50dc4f | 2391 | if (device_property_present(dev, "smsc,force-internal-phy")) |
79f88ee9 SG |
2392 | config->flags |= SMSC911X_FORCE_INTERNAL_PHY; |
2393 | ||
0b50dc4f | 2394 | if (device_property_present(dev, "smsc,force-external-phy")) |
79f88ee9 SG |
2395 | config->flags |= SMSC911X_FORCE_EXTERNAL_PHY; |
2396 | ||
0b50dc4f | 2397 | if (device_property_present(dev, "smsc,save-mac-address")) |
79f88ee9 SG |
2398 | config->flags |= SMSC911X_SAVE_MAC_ADDRESS; |
2399 | ||
2400 | return 0; | |
2401 | } | |
79f88ee9 | 2402 | |
8489ec1f | 2403 | static int smsc911x_drv_probe(struct platform_device *pdev) |
fd9abb3d SG |
2404 | { |
2405 | struct net_device *dev; | |
2406 | struct smsc911x_data *pdata; | |
495c765d | 2407 | struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev); |
965b2aa7 | 2408 | struct resource *res; |
f252974e | 2409 | int res_size, irq; |
fd9abb3d | 2410 | int retval; |
fd9abb3d | 2411 | |
fd9abb3d SG |
2412 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
2413 | "smsc911x-memory"); | |
2414 | if (!res) | |
2415 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2416 | if (!res) { | |
dffc6b24 | 2417 | pr_warn("Could not allocate resource\n"); |
fd9abb3d SG |
2418 | retval = -ENODEV; |
2419 | goto out_0; | |
2420 | } | |
39424539 | 2421 | res_size = resource_size(res); |
fd9abb3d | 2422 | |
965b2aa7 | 2423 | irq = platform_get_irq(pdev, 0); |
f892a84c TL |
2424 | if (irq == -EPROBE_DEFER) { |
2425 | retval = -EPROBE_DEFER; | |
2426 | goto out_0; | |
2427 | } else if (irq <= 0) { | |
dffc6b24 | 2428 | pr_warn("Could not allocate irq resource\n"); |
61307ed8 SG |
2429 | retval = -ENODEV; |
2430 | goto out_0; | |
2431 | } | |
2432 | ||
fd9abb3d SG |
2433 | if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) { |
2434 | retval = -EBUSY; | |
2435 | goto out_0; | |
2436 | } | |
2437 | ||
2438 | dev = alloc_etherdev(sizeof(struct smsc911x_data)); | |
2439 | if (!dev) { | |
fd9abb3d SG |
2440 | retval = -ENOMEM; |
2441 | goto out_release_io_1; | |
2442 | } | |
2443 | ||
2444 | SET_NETDEV_DEV(dev, &pdev->dev); | |
2445 | ||
2446 | pdata = netdev_priv(dev); | |
965b2aa7 | 2447 | dev->irq = irq; |
fd9abb3d SG |
2448 | pdata->ioaddr = ioremap_nocache(res->start, res_size); |
2449 | ||
fd9abb3d SG |
2450 | pdata->dev = dev; |
2451 | pdata->msg_enable = ((1 << debug) - 1); | |
2452 | ||
c7e963f6 RM |
2453 | platform_set_drvdata(pdev, dev); |
2454 | ||
2455 | retval = smsc911x_request_resources(pdev); | |
2456 | if (retval) | |
2e1d4a06 | 2457 | goto out_request_resources_fail; |
c7e963f6 RM |
2458 | |
2459 | retval = smsc911x_enable_resources(pdev); | |
2460 | if (retval) | |
2e1d4a06 | 2461 | goto out_enable_resources_fail; |
c7e963f6 | 2462 | |
fd9abb3d | 2463 | if (pdata->ioaddr == NULL) { |
dffc6b24 | 2464 | SMSC_WARN(pdata, probe, "Error smsc911x base address invalid"); |
fd9abb3d | 2465 | retval = -ENOMEM; |
c7e963f6 | 2466 | goto out_disable_resources; |
fd9abb3d SG |
2467 | } |
2468 | ||
0b50dc4f | 2469 | retval = smsc911x_probe_config(&pdata->config, &pdev->dev); |
79f88ee9 SG |
2470 | if (retval && config) { |
2471 | /* copy config parameters across to pdata */ | |
2472 | memcpy(&pdata->config, config, sizeof(pdata->config)); | |
2473 | retval = 0; | |
2474 | } | |
2475 | ||
2476 | if (retval) { | |
2477 | SMSC_WARN(pdata, probe, "Error smsc911x config not found"); | |
c7e963f6 | 2478 | goto out_disable_resources; |
79f88ee9 SG |
2479 | } |
2480 | ||
c326de88 MP |
2481 | /* assume standard, non-shifted, access to HW registers */ |
2482 | pdata->ops = &standard_smsc911x_ops; | |
2483 | /* apply the right access if shifting is needed */ | |
79f88ee9 | 2484 | if (pdata->config.shift) |
c326de88 MP |
2485 | pdata->ops = &shifted_smsc911x_ops; |
2486 | ||
3a611e26 GU |
2487 | pm_runtime_enable(&pdev->dev); |
2488 | pm_runtime_get_sync(&pdev->dev); | |
2489 | ||
fd9abb3d SG |
2490 | retval = smsc911x_init(dev); |
2491 | if (retval < 0) | |
c7e963f6 | 2492 | goto out_disable_resources; |
fd9abb3d | 2493 | |
31f6f291 BK |
2494 | netif_carrier_off(dev); |
2495 | ||
aea95dd5 JL |
2496 | retval = smsc911x_mii_init(pdev, dev); |
2497 | if (retval) { | |
2498 | SMSC_WARN(pdata, probe, "Error %i initialising mii", retval); | |
f252974e | 2499 | goto out_disable_resources; |
aea95dd5 JL |
2500 | } |
2501 | ||
fd9abb3d SG |
2502 | retval = register_netdev(dev); |
2503 | if (retval) { | |
dffc6b24 | 2504 | SMSC_WARN(pdata, probe, "Error %i registering device", retval); |
f252974e | 2505 | goto out_disable_resources; |
fd9abb3d | 2506 | } else { |
dffc6b24 JP |
2507 | SMSC_TRACE(pdata, probe, |
2508 | "Network interface: \"%s\"", dev->name); | |
fd9abb3d SG |
2509 | } |
2510 | ||
fd9abb3d SG |
2511 | spin_lock_irq(&pdata->mac_lock); |
2512 | ||
2513 | /* Check if mac address has been specified when bringing interface up */ | |
2514 | if (is_valid_ether_addr(dev->dev_addr)) { | |
225ddf49 | 2515 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 JP |
2516 | SMSC_TRACE(pdata, probe, |
2517 | "MAC Address is specified by configuration"); | |
aace4959 | 2518 | } else if (is_valid_ether_addr(pdata->config.mac)) { |
d458cdf7 | 2519 | memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN); |
dffc6b24 JP |
2520 | SMSC_TRACE(pdata, probe, |
2521 | "MAC Address specified by platform data"); | |
fd9abb3d SG |
2522 | } else { |
2523 | /* Try reading mac address from device. if EEPROM is present | |
2524 | * it will already have been set */ | |
62747cd2 | 2525 | smsc_get_mac(dev); |
fd9abb3d SG |
2526 | |
2527 | if (is_valid_ether_addr(dev->dev_addr)) { | |
2528 | /* eeprom values are valid so use them */ | |
dffc6b24 JP |
2529 | SMSC_TRACE(pdata, probe, |
2530 | "Mac Address is read from LAN911x EEPROM"); | |
fd9abb3d SG |
2531 | } else { |
2532 | /* eeprom values are invalid, generate random MAC */ | |
7ce5d222 | 2533 | eth_hw_addr_random(dev); |
225ddf49 | 2534 | smsc911x_set_hw_mac_address(pdata, dev->dev_addr); |
dffc6b24 | 2535 | SMSC_TRACE(pdata, probe, |
7efd26d0 | 2536 | "MAC Address is set to eth_random_addr"); |
fd9abb3d SG |
2537 | } |
2538 | } | |
2539 | ||
2540 | spin_unlock_irq(&pdata->mac_lock); | |
2541 | ||
dffc6b24 | 2542 | netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr); |
fd9abb3d SG |
2543 | |
2544 | return 0; | |
2545 | ||
c7e963f6 | 2546 | out_disable_resources: |
3a611e26 GU |
2547 | pm_runtime_put(&pdev->dev); |
2548 | pm_runtime_disable(&pdev->dev); | |
c7e963f6 | 2549 | (void)smsc911x_disable_resources(pdev); |
2e1d4a06 | 2550 | out_enable_resources_fail: |
c7e963f6 | 2551 | smsc911x_free_resources(pdev); |
2e1d4a06 | 2552 | out_request_resources_fail: |
fd9abb3d | 2553 | iounmap(pdata->ioaddr); |
fd9abb3d SG |
2554 | free_netdev(dev); |
2555 | out_release_io_1: | |
39424539 | 2556 | release_mem_region(res->start, resource_size(res)); |
fd9abb3d SG |
2557 | out_0: |
2558 | return retval; | |
2559 | } | |
2560 | ||
b6907b0c DM |
2561 | #ifdef CONFIG_PM |
2562 | /* This implementation assumes the devices remains powered on its VDDVARIO | |
2563 | * pins during suspend. */ | |
2564 | ||
6cb87823 DM |
2565 | /* TODO: implement freeze/thaw callbacks for hibernation.*/ |
2566 | ||
2567 | static int smsc911x_suspend(struct device *dev) | |
b6907b0c | 2568 | { |
6cb87823 DM |
2569 | struct net_device *ndev = dev_get_drvdata(dev); |
2570 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2571 | |
2572 | /* enable wake on LAN, energy detection and the external PME | |
2573 | * signal. */ | |
2574 | smsc911x_reg_write(pdata, PMT_CTRL, | |
2575 | PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ | | |
2576 | PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_); | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
6cb87823 | 2581 | static int smsc911x_resume(struct device *dev) |
b6907b0c | 2582 | { |
6cb87823 DM |
2583 | struct net_device *ndev = dev_get_drvdata(dev); |
2584 | struct smsc911x_data *pdata = netdev_priv(ndev); | |
b6907b0c DM |
2585 | unsigned int to = 100; |
2586 | ||
2587 | /* Note 3.11 from the datasheet: | |
2588 | * "When the LAN9220 is in a power saving state, a write of any | |
2589 | * data to the BYTE_TEST register will wake-up the device." | |
2590 | */ | |
2591 | smsc911x_reg_write(pdata, BYTE_TEST, 0); | |
2592 | ||
2593 | /* poll the READY bit in PMT_CTRL. Any other access to the device is | |
2594 | * forbidden while this bit isn't set. Try for 100ms and return -EIO | |
2595 | * if it failed. */ | |
2596 | while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to) | |
2597 | udelay(1000); | |
2598 | ||
2599 | return (to == 0) ? -EIO : 0; | |
2600 | } | |
2601 | ||
47145210 | 2602 | static const struct dev_pm_ops smsc911x_pm_ops = { |
6cb87823 DM |
2603 | .suspend = smsc911x_suspend, |
2604 | .resume = smsc911x_resume, | |
2605 | }; | |
2606 | ||
2607 | #define SMSC911X_PM_OPS (&smsc911x_pm_ops) | |
2608 | ||
b6907b0c | 2609 | #else |
6cb87823 | 2610 | #define SMSC911X_PM_OPS NULL |
b6907b0c DM |
2611 | #endif |
2612 | ||
d62fdf8b | 2613 | #ifdef CONFIG_OF |
79f88ee9 SG |
2614 | static const struct of_device_id smsc911x_dt_ids[] = { |
2615 | { .compatible = "smsc,lan9115", }, | |
2616 | { /* sentinel */ } | |
2617 | }; | |
2618 | MODULE_DEVICE_TABLE(of, smsc911x_dt_ids); | |
d62fdf8b | 2619 | #endif |
79f88ee9 | 2620 | |
0b50dc4f JL |
2621 | static const struct acpi_device_id smsc911x_acpi_match[] = { |
2622 | { "ARMH9118", 0 }, | |
2623 | { } | |
2624 | }; | |
2625 | MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match); | |
2626 | ||
fd9abb3d SG |
2627 | static struct platform_driver smsc911x_driver = { |
2628 | .probe = smsc911x_drv_probe, | |
8489ec1f | 2629 | .remove = smsc911x_drv_remove, |
fd9abb3d | 2630 | .driver = { |
6cb87823 | 2631 | .name = SMSC_CHIPNAME, |
6cb87823 | 2632 | .pm = SMSC911X_PM_OPS, |
d62fdf8b | 2633 | .of_match_table = of_match_ptr(smsc911x_dt_ids), |
0b50dc4f | 2634 | .acpi_match_table = ACPI_PTR(smsc911x_acpi_match), |
fd9abb3d SG |
2635 | }, |
2636 | }; | |
2637 | ||
2638 | /* Entry point for loading the module */ | |
2639 | static int __init smsc911x_init_module(void) | |
2640 | { | |
62747cd2 | 2641 | SMSC_INITIALIZE(); |
fd9abb3d SG |
2642 | return platform_driver_register(&smsc911x_driver); |
2643 | } | |
2644 | ||
2645 | /* entry point for unloading the module */ | |
2646 | static void __exit smsc911x_cleanup_module(void) | |
2647 | { | |
2648 | platform_driver_unregister(&smsc911x_driver); | |
2649 | } | |
2650 | ||
2651 | module_init(smsc911x_init_module); | |
2652 | module_exit(smsc911x_cleanup_module); |