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4fa9c49f | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
286a8372 GC |
2 | /******************************************************************************* |
3 | Header File to describe Normal/enhanced descriptor functions used for RING | |
4 | and CHAINED modes. | |
5 | ||
6 | Copyright(C) 2011 STMicroelectronics Ltd | |
7 | ||
8 | It defines all the functions used to handle the normal/enhanced | |
9 | descriptors in case of the DMA is configured to work in chained or | |
10 | in ring mode. | |
11 | ||
286a8372 GC |
12 | |
13 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
14 | *******************************************************************************/ | |
15 | ||
bd4242df RK |
16 | #ifndef __DESC_COM_H__ |
17 | #define __DESC_COM_H__ | |
18 | ||
4a7d666a GC |
19 | /* Specific functions used for Ring mode */ |
20 | ||
21 | /* Enhanced descriptors */ | |
583e6361 AK |
22 | static inline void ehn_desc_rx_set_on_ring(struct dma_desc *p, int end, |
23 | int bfsize) | |
286a8372 | 24 | { |
583e6361 AK |
25 | if (bfsize == BUF_SIZE_16KiB) |
26 | p->des1 |= cpu_to_le32((BUF_SIZE_8KiB | |
27 | << ERDES1_BUFFER2_SIZE_SHIFT) | |
28 | & ERDES1_BUFFER2_SIZE_MASK); | |
286a8372 | 29 | |
286a8372 | 30 | if (end) |
f8be0d78 | 31 | p->des1 |= cpu_to_le32(ERDES1_END_RING); |
286a8372 GC |
32 | } |
33 | ||
293e4365 | 34 | static inline void enh_desc_end_tx_desc_on_ring(struct dma_desc *p, int end) |
286a8372 | 35 | { |
293e4365 | 36 | if (end) |
f8be0d78 | 37 | p->des0 |= cpu_to_le32(ETDES0_END_RING); |
293e4365 | 38 | else |
f8be0d78 | 39 | p->des0 &= cpu_to_le32(~ETDES0_END_RING); |
286a8372 GC |
40 | } |
41 | ||
4a7d666a | 42 | static inline void enh_set_tx_desc_len_on_ring(struct dma_desc *p, int len) |
286a8372 GC |
43 | { |
44 | if (unlikely(len > BUF_SIZE_4KiB)) { | |
f8be0d78 MW |
45 | p->des1 |= cpu_to_le32((((len - BUF_SIZE_4KiB) |
46 | << ETDES1_BUFFER2_SIZE_SHIFT) | |
293e4365 | 47 | & ETDES1_BUFFER2_SIZE_MASK) | (BUF_SIZE_4KiB |
f8be0d78 | 48 | & ETDES1_BUFFER1_SIZE_MASK)); |
286a8372 | 49 | } else |
f8be0d78 | 50 | p->des1 |= cpu_to_le32((len & ETDES1_BUFFER1_SIZE_MASK)); |
286a8372 GC |
51 | } |
52 | ||
4a7d666a | 53 | /* Normal descriptors */ |
583e6361 | 54 | static inline void ndesc_rx_set_on_ring(struct dma_desc *p, int end, int bfsize) |
286a8372 | 55 | { |
583e6361 AK |
56 | if (bfsize >= BUF_SIZE_2KiB) { |
57 | int bfsize2; | |
58 | ||
59 | bfsize2 = min(bfsize - BUF_SIZE_2KiB + 1, BUF_SIZE_2KiB - 1); | |
60 | p->des1 |= cpu_to_le32((bfsize2 << RDES1_BUFFER2_SIZE_SHIFT) | |
61 | & RDES1_BUFFER2_SIZE_MASK); | |
62 | } | |
286a8372 | 63 | |
286a8372 | 64 | if (end) |
f8be0d78 | 65 | p->des1 |= cpu_to_le32(RDES1_END_RING); |
286a8372 GC |
66 | } |
67 | ||
293e4365 | 68 | static inline void ndesc_end_tx_desc_on_ring(struct dma_desc *p, int end) |
286a8372 | 69 | { |
293e4365 | 70 | if (end) |
f8be0d78 | 71 | p->des1 |= cpu_to_le32(TDES1_END_RING); |
293e4365 | 72 | else |
f8be0d78 | 73 | p->des1 &= cpu_to_le32(~TDES1_END_RING); |
286a8372 GC |
74 | } |
75 | ||
4a7d666a | 76 | static inline void norm_set_tx_desc_len_on_ring(struct dma_desc *p, int len) |
286a8372 GC |
77 | { |
78 | if (unlikely(len > BUF_SIZE_2KiB)) { | |
293e4365 GC |
79 | unsigned int buffer1 = (BUF_SIZE_2KiB - 1) |
80 | & TDES1_BUFFER1_SIZE_MASK; | |
f8be0d78 MW |
81 | p->des1 |= cpu_to_le32((((len - buffer1) |
82 | << TDES1_BUFFER2_SIZE_SHIFT) | |
83 | & TDES1_BUFFER2_SIZE_MASK) | buffer1); | |
286a8372 | 84 | } else |
f8be0d78 | 85 | p->des1 |= cpu_to_le32((len & TDES1_BUFFER1_SIZE_MASK)); |
286a8372 GC |
86 | } |
87 | ||
4a7d666a | 88 | /* Specific functions used for Chain mode */ |
286a8372 | 89 | |
4a7d666a | 90 | /* Enhanced descriptors */ |
293e4365 | 91 | static inline void ehn_desc_rx_set_on_chain(struct dma_desc *p) |
286a8372 | 92 | { |
f8be0d78 | 93 | p->des1 |= cpu_to_le32(ERDES1_SECOND_ADDRESS_CHAINED); |
286a8372 GC |
94 | } |
95 | ||
293e4365 | 96 | static inline void enh_desc_end_tx_desc_on_chain(struct dma_desc *p) |
286a8372 | 97 | { |
f8be0d78 | 98 | p->des0 |= cpu_to_le32(ETDES0_SECOND_ADDRESS_CHAINED); |
286a8372 GC |
99 | } |
100 | ||
4a7d666a | 101 | static inline void enh_set_tx_desc_len_on_chain(struct dma_desc *p, int len) |
286a8372 | 102 | { |
f8be0d78 | 103 | p->des1 |= cpu_to_le32(len & ETDES1_BUFFER1_SIZE_MASK); |
286a8372 GC |
104 | } |
105 | ||
4a7d666a GC |
106 | /* Normal descriptors */ |
107 | static inline void ndesc_rx_set_on_chain(struct dma_desc *p, int end) | |
286a8372 | 108 | { |
f8be0d78 | 109 | p->des1 |= cpu_to_le32(RDES1_SECOND_ADDRESS_CHAINED); |
286a8372 GC |
110 | } |
111 | ||
293e4365 | 112 | static inline void ndesc_tx_set_on_chain(struct dma_desc *p) |
286a8372 | 113 | { |
f8be0d78 | 114 | p->des1 |= cpu_to_le32(TDES1_SECOND_ADDRESS_CHAINED); |
286a8372 GC |
115 | } |
116 | ||
4a7d666a | 117 | static inline void norm_set_tx_desc_len_on_chain(struct dma_desc *p, int len) |
286a8372 | 118 | { |
f8be0d78 | 119 | p->des1 |= cpu_to_le32(len & TDES1_BUFFER1_SIZE_MASK); |
286a8372 | 120 | } |
bd4242df | 121 | #endif /* __DESC_COM_H__ */ |