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58da0cfa VW |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2020, Intel Corporation | |
3 | */ | |
4 | ||
5 | #include <linux/clk-provider.h> | |
6 | #include <linux/pci.h> | |
7 | #include <linux/dmi.h> | |
b9663b7c | 8 | #include "dwmac-intel.h" |
b4c5f83a | 9 | #include "dwmac4.h" |
58da0cfa VW |
10 | #include "stmmac.h" |
11 | ||
b9663b7c VW |
12 | struct intel_priv_data { |
13 | int mdio_adhoc_addr; /* mdio address for serdes & etc */ | |
14 | }; | |
15 | ||
58da0cfa VW |
16 | /* This struct is used to associate PCI Function of MAC controller on a board, |
17 | * discovered via DMI, with the address of PHY connected to the MAC. The | |
18 | * negative value of the address means that MAC controller is not connected | |
19 | * with PHY. | |
20 | */ | |
21 | struct stmmac_pci_func_data { | |
22 | unsigned int func; | |
23 | int phy_addr; | |
24 | }; | |
25 | ||
26 | struct stmmac_pci_dmi_data { | |
27 | const struct stmmac_pci_func_data *func; | |
28 | size_t nfuncs; | |
29 | }; | |
30 | ||
31 | struct stmmac_pci_info { | |
32 | int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); | |
33 | }; | |
34 | ||
35 | static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, | |
36 | const struct dmi_system_id *dmi_list) | |
37 | { | |
38 | const struct stmmac_pci_func_data *func_data; | |
39 | const struct stmmac_pci_dmi_data *dmi_data; | |
40 | const struct dmi_system_id *dmi_id; | |
41 | int func = PCI_FUNC(pdev->devfn); | |
42 | size_t n; | |
43 | ||
44 | dmi_id = dmi_first_match(dmi_list); | |
45 | if (!dmi_id) | |
46 | return -ENODEV; | |
47 | ||
48 | dmi_data = dmi_id->driver_data; | |
49 | func_data = dmi_data->func; | |
50 | ||
51 | for (n = 0; n < dmi_data->nfuncs; n++, func_data++) | |
52 | if (func_data->func == func) | |
53 | return func_data->phy_addr; | |
54 | ||
55 | return -ENODEV; | |
56 | } | |
57 | ||
b9663b7c VW |
58 | static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr, |
59 | int phyreg, u32 mask, u32 val) | |
60 | { | |
61 | unsigned int retries = 10; | |
62 | int val_rd; | |
63 | ||
64 | do { | |
65 | val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); | |
66 | if ((val_rd & mask) == (val & mask)) | |
67 | return 0; | |
68 | udelay(POLL_DELAY_US); | |
69 | } while (--retries); | |
70 | ||
71 | return -ETIMEDOUT; | |
72 | } | |
73 | ||
74 | static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) | |
75 | { | |
76 | struct intel_priv_data *intel_priv = priv_data; | |
77 | struct stmmac_priv *priv = netdev_priv(ndev); | |
78 | int serdes_phy_addr = 0; | |
79 | u32 data = 0; | |
80 | ||
81 | if (!intel_priv->mdio_adhoc_addr) | |
82 | return 0; | |
83 | ||
84 | serdes_phy_addr = intel_priv->mdio_adhoc_addr; | |
85 | ||
86 | /* assert clk_req */ | |
ccacb703 | 87 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c | 88 | data |= SERDES_PLL_CLK; |
ccacb703 | 89 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
90 | |
91 | /* check for clk_ack assertion */ | |
92 | data = serdes_status_poll(priv, serdes_phy_addr, | |
93 | SERDES_GSR0, | |
94 | SERDES_PLL_CLK, | |
95 | SERDES_PLL_CLK); | |
96 | ||
97 | if (data) { | |
98 | dev_err(priv->device, "Serdes PLL clk request timeout\n"); | |
99 | return data; | |
100 | } | |
101 | ||
102 | /* assert lane reset */ | |
ccacb703 | 103 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c | 104 | data |= SERDES_RST; |
ccacb703 | 105 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
106 | |
107 | /* check for assert lane reset reflection */ | |
108 | data = serdes_status_poll(priv, serdes_phy_addr, | |
109 | SERDES_GSR0, | |
110 | SERDES_RST, | |
111 | SERDES_RST); | |
112 | ||
113 | if (data) { | |
114 | dev_err(priv->device, "Serdes assert lane reset timeout\n"); | |
115 | return data; | |
116 | } | |
117 | ||
118 | /* move power state to P0 */ | |
ccacb703 | 119 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c VW |
120 | |
121 | data &= ~SERDES_PWR_ST_MASK; | |
122 | data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT; | |
123 | ||
ccacb703 | 124 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
125 | |
126 | /* Check for P0 state */ | |
127 | data = serdes_status_poll(priv, serdes_phy_addr, | |
128 | SERDES_GSR0, | |
129 | SERDES_PWR_ST_MASK, | |
130 | SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT); | |
131 | ||
132 | if (data) { | |
133 | dev_err(priv->device, "Serdes power state P0 timeout.\n"); | |
134 | return data; | |
135 | } | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) | |
141 | { | |
142 | struct intel_priv_data *intel_priv = intel_data; | |
143 | struct stmmac_priv *priv = netdev_priv(ndev); | |
144 | int serdes_phy_addr = 0; | |
145 | u32 data = 0; | |
146 | ||
147 | if (!intel_priv->mdio_adhoc_addr) | |
148 | return; | |
149 | ||
150 | serdes_phy_addr = intel_priv->mdio_adhoc_addr; | |
151 | ||
152 | /* move power state to P3 */ | |
ccacb703 | 153 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c VW |
154 | |
155 | data &= ~SERDES_PWR_ST_MASK; | |
156 | data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT; | |
157 | ||
ccacb703 | 158 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
159 | |
160 | /* Check for P3 state */ | |
161 | data = serdes_status_poll(priv, serdes_phy_addr, | |
162 | SERDES_GSR0, | |
163 | SERDES_PWR_ST_MASK, | |
164 | SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT); | |
165 | ||
166 | if (data) { | |
167 | dev_err(priv->device, "Serdes power state P3 timeout\n"); | |
168 | return; | |
169 | } | |
170 | ||
171 | /* de-assert clk_req */ | |
ccacb703 | 172 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c | 173 | data &= ~SERDES_PLL_CLK; |
ccacb703 | 174 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
175 | |
176 | /* check for clk_ack de-assert */ | |
177 | data = serdes_status_poll(priv, serdes_phy_addr, | |
178 | SERDES_GSR0, | |
179 | SERDES_PLL_CLK, | |
180 | (u32)~SERDES_PLL_CLK); | |
181 | ||
182 | if (data) { | |
183 | dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); | |
184 | return; | |
185 | } | |
186 | ||
187 | /* de-assert lane reset */ | |
ccacb703 | 188 | data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); |
b9663b7c | 189 | data &= ~SERDES_RST; |
ccacb703 | 190 | mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); |
b9663b7c VW |
191 | |
192 | /* check for de-assert lane reset reflection */ | |
193 | data = serdes_status_poll(priv, serdes_phy_addr, | |
194 | SERDES_GSR0, | |
195 | SERDES_RST, | |
196 | (u32)~SERDES_RST); | |
197 | ||
198 | if (data) { | |
199 | dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); | |
200 | return; | |
201 | } | |
202 | } | |
203 | ||
58da0cfa VW |
204 | static void common_default_data(struct plat_stmmacenet_data *plat) |
205 | { | |
206 | plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ | |
207 | plat->has_gmac = 1; | |
208 | plat->force_sf_dma_mode = 1; | |
209 | ||
210 | plat->mdio_bus_data->needs_reset = true; | |
211 | ||
212 | /* Set default value for multicast hash bins */ | |
213 | plat->multicast_filter_bins = HASH_TABLE_SIZE; | |
214 | ||
215 | /* Set default value for unicast filter entries */ | |
216 | plat->unicast_filter_entries = 1; | |
217 | ||
218 | /* Set the maxmtu to a default of JUMBO_LEN */ | |
219 | plat->maxmtu = JUMBO_LEN; | |
220 | ||
221 | /* Set default number of RX and TX queues to use */ | |
222 | plat->tx_queues_to_use = 1; | |
223 | plat->rx_queues_to_use = 1; | |
224 | ||
225 | /* Disable Priority config by default */ | |
226 | plat->tx_queues_cfg[0].use_prio = false; | |
227 | plat->rx_queues_cfg[0].use_prio = false; | |
228 | ||
229 | /* Disable RX queues routing by default */ | |
230 | plat->rx_queues_cfg[0].pkt_route = 0x0; | |
231 | } | |
232 | ||
233 | static int intel_mgbe_common_data(struct pci_dev *pdev, | |
234 | struct plat_stmmacenet_data *plat) | |
235 | { | |
09f012e6 | 236 | int ret; |
58da0cfa VW |
237 | int i; |
238 | ||
bff6f1db | 239 | plat->phy_addr = -1; |
58da0cfa VW |
240 | plat->clk_csr = 5; |
241 | plat->has_gmac = 0; | |
242 | plat->has_gmac4 = 1; | |
243 | plat->force_sf_dma_mode = 0; | |
244 | plat->tso_en = 1; | |
245 | ||
246 | plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; | |
247 | ||
248 | for (i = 0; i < plat->rx_queues_to_use; i++) { | |
249 | plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; | |
250 | plat->rx_queues_cfg[i].chan = i; | |
251 | ||
252 | /* Disable Priority config by default */ | |
253 | plat->rx_queues_cfg[i].use_prio = false; | |
254 | ||
255 | /* Disable RX queues routing by default */ | |
256 | plat->rx_queues_cfg[i].pkt_route = 0x0; | |
257 | } | |
258 | ||
259 | for (i = 0; i < plat->tx_queues_to_use; i++) { | |
260 | plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; | |
261 | ||
262 | /* Disable Priority config by default */ | |
263 | plat->tx_queues_cfg[i].use_prio = false; | |
264 | } | |
265 | ||
266 | /* FIFO size is 4096 bytes for 1 tx/rx queue */ | |
267 | plat->tx_fifo_size = plat->tx_queues_to_use * 4096; | |
268 | plat->rx_fifo_size = plat->rx_queues_to_use * 4096; | |
269 | ||
270 | plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; | |
271 | plat->tx_queues_cfg[0].weight = 0x09; | |
272 | plat->tx_queues_cfg[1].weight = 0x0A; | |
273 | plat->tx_queues_cfg[2].weight = 0x0B; | |
274 | plat->tx_queues_cfg[3].weight = 0x0C; | |
275 | plat->tx_queues_cfg[4].weight = 0x0D; | |
276 | plat->tx_queues_cfg[5].weight = 0x0E; | |
277 | plat->tx_queues_cfg[6].weight = 0x0F; | |
278 | plat->tx_queues_cfg[7].weight = 0x10; | |
279 | ||
280 | plat->dma_cfg->pbl = 32; | |
281 | plat->dma_cfg->pblx8 = true; | |
282 | plat->dma_cfg->fixed_burst = 0; | |
283 | plat->dma_cfg->mixed_burst = 0; | |
284 | plat->dma_cfg->aal = 0; | |
285 | ||
286 | plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), | |
287 | GFP_KERNEL); | |
288 | if (!plat->axi) | |
289 | return -ENOMEM; | |
290 | ||
291 | plat->axi->axi_lpi_en = 0; | |
292 | plat->axi->axi_xit_frm = 0; | |
293 | plat->axi->axi_wr_osr_lmt = 1; | |
294 | plat->axi->axi_rd_osr_lmt = 1; | |
295 | plat->axi->axi_blen[0] = 4; | |
296 | plat->axi->axi_blen[1] = 8; | |
297 | plat->axi->axi_blen[2] = 16; | |
298 | ||
299 | plat->ptp_max_adj = plat->clk_ptp_rate; | |
b4c5f83a | 300 | plat->eee_usecs_rate = plat->clk_ptp_rate; |
58da0cfa VW |
301 | |
302 | /* Set system clock */ | |
303 | plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, | |
304 | "stmmac-clk", NULL, 0, | |
305 | plat->clk_ptp_rate); | |
306 | ||
307 | if (IS_ERR(plat->stmmac_clk)) { | |
308 | dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); | |
309 | plat->stmmac_clk = NULL; | |
310 | } | |
09f012e6 AS |
311 | |
312 | ret = clk_prepare_enable(plat->stmmac_clk); | |
313 | if (ret) { | |
314 | clk_unregister_fixed_rate(plat->stmmac_clk); | |
315 | return ret; | |
316 | } | |
58da0cfa VW |
317 | |
318 | /* Set default value for multicast hash bins */ | |
319 | plat->multicast_filter_bins = HASH_TABLE_SIZE; | |
320 | ||
321 | /* Set default value for unicast filter entries */ | |
322 | plat->unicast_filter_entries = 1; | |
323 | ||
324 | /* Set the maxmtu to a default of JUMBO_LEN */ | |
325 | plat->maxmtu = JUMBO_LEN; | |
326 | ||
e0f9956a CKT |
327 | plat->vlan_fail_q_en = true; |
328 | ||
329 | /* Use the last Rx queue */ | |
330 | plat->vlan_fail_q = plat->rx_queues_to_use - 1; | |
331 | ||
58da0cfa VW |
332 | return 0; |
333 | } | |
334 | ||
335 | static int ehl_common_data(struct pci_dev *pdev, | |
336 | struct plat_stmmacenet_data *plat) | |
337 | { | |
58da0cfa VW |
338 | plat->rx_queues_to_use = 8; |
339 | plat->tx_queues_to_use = 8; | |
340 | plat->clk_ptp_rate = 200000000; | |
58da0cfa | 341 | |
d5383b03 | 342 | return intel_mgbe_common_data(pdev, plat); |
58da0cfa VW |
343 | } |
344 | ||
345 | static int ehl_sgmii_data(struct pci_dev *pdev, | |
346 | struct plat_stmmacenet_data *plat) | |
347 | { | |
348 | plat->bus_id = 1; | |
58da0cfa VW |
349 | plat->phy_interface = PHY_INTERFACE_MODE_SGMII; |
350 | ||
b9663b7c VW |
351 | plat->serdes_powerup = intel_serdes_powerup; |
352 | plat->serdes_powerdown = intel_serdes_powerdown; | |
353 | ||
58da0cfa VW |
354 | return ehl_common_data(pdev, plat); |
355 | } | |
356 | ||
ccacb703 | 357 | static struct stmmac_pci_info ehl_sgmii1g_info = { |
58da0cfa VW |
358 | .setup = ehl_sgmii_data, |
359 | }; | |
360 | ||
361 | static int ehl_rgmii_data(struct pci_dev *pdev, | |
362 | struct plat_stmmacenet_data *plat) | |
363 | { | |
364 | plat->bus_id = 1; | |
58da0cfa VW |
365 | plat->phy_interface = PHY_INTERFACE_MODE_RGMII; |
366 | ||
367 | return ehl_common_data(pdev, plat); | |
368 | } | |
369 | ||
ccacb703 | 370 | static struct stmmac_pci_info ehl_rgmii1g_info = { |
58da0cfa VW |
371 | .setup = ehl_rgmii_data, |
372 | }; | |
373 | ||
67c08ac4 VW |
374 | static int ehl_pse0_common_data(struct pci_dev *pdev, |
375 | struct plat_stmmacenet_data *plat) | |
376 | { | |
377 | plat->bus_id = 2; | |
7cfc4486 | 378 | plat->addr64 = 32; |
67c08ac4 VW |
379 | return ehl_common_data(pdev, plat); |
380 | } | |
381 | ||
382 | static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, | |
383 | struct plat_stmmacenet_data *plat) | |
384 | { | |
385 | plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; | |
386 | return ehl_pse0_common_data(pdev, plat); | |
387 | } | |
388 | ||
ccacb703 | 389 | static struct stmmac_pci_info ehl_pse0_rgmii1g_info = { |
67c08ac4 VW |
390 | .setup = ehl_pse0_rgmii1g_data, |
391 | }; | |
392 | ||
393 | static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, | |
394 | struct plat_stmmacenet_data *plat) | |
395 | { | |
396 | plat->phy_interface = PHY_INTERFACE_MODE_SGMII; | |
b9663b7c VW |
397 | plat->serdes_powerup = intel_serdes_powerup; |
398 | plat->serdes_powerdown = intel_serdes_powerdown; | |
67c08ac4 VW |
399 | return ehl_pse0_common_data(pdev, plat); |
400 | } | |
401 | ||
ccacb703 | 402 | static struct stmmac_pci_info ehl_pse0_sgmii1g_info = { |
67c08ac4 VW |
403 | .setup = ehl_pse0_sgmii1g_data, |
404 | }; | |
405 | ||
406 | static int ehl_pse1_common_data(struct pci_dev *pdev, | |
407 | struct plat_stmmacenet_data *plat) | |
408 | { | |
409 | plat->bus_id = 3; | |
7cfc4486 | 410 | plat->addr64 = 32; |
67c08ac4 VW |
411 | return ehl_common_data(pdev, plat); |
412 | } | |
413 | ||
414 | static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, | |
415 | struct plat_stmmacenet_data *plat) | |
416 | { | |
417 | plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; | |
418 | return ehl_pse1_common_data(pdev, plat); | |
419 | } | |
420 | ||
ccacb703 | 421 | static struct stmmac_pci_info ehl_pse1_rgmii1g_info = { |
67c08ac4 VW |
422 | .setup = ehl_pse1_rgmii1g_data, |
423 | }; | |
424 | ||
425 | static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, | |
426 | struct plat_stmmacenet_data *plat) | |
427 | { | |
428 | plat->phy_interface = PHY_INTERFACE_MODE_SGMII; | |
b9663b7c VW |
429 | plat->serdes_powerup = intel_serdes_powerup; |
430 | plat->serdes_powerdown = intel_serdes_powerdown; | |
67c08ac4 VW |
431 | return ehl_pse1_common_data(pdev, plat); |
432 | } | |
433 | ||
ccacb703 | 434 | static struct stmmac_pci_info ehl_pse1_sgmii1g_info = { |
67c08ac4 VW |
435 | .setup = ehl_pse1_sgmii1g_data, |
436 | }; | |
437 | ||
58da0cfa VW |
438 | static int tgl_common_data(struct pci_dev *pdev, |
439 | struct plat_stmmacenet_data *plat) | |
440 | { | |
58da0cfa VW |
441 | plat->rx_queues_to_use = 6; |
442 | plat->tx_queues_to_use = 4; | |
443 | plat->clk_ptp_rate = 200000000; | |
58da0cfa | 444 | |
d5383b03 | 445 | return intel_mgbe_common_data(pdev, plat); |
58da0cfa VW |
446 | } |
447 | ||
448 | static int tgl_sgmii_data(struct pci_dev *pdev, | |
449 | struct plat_stmmacenet_data *plat) | |
450 | { | |
451 | plat->bus_id = 1; | |
58da0cfa | 452 | plat->phy_interface = PHY_INTERFACE_MODE_SGMII; |
b9663b7c VW |
453 | plat->serdes_powerup = intel_serdes_powerup; |
454 | plat->serdes_powerdown = intel_serdes_powerdown; | |
58da0cfa VW |
455 | return tgl_common_data(pdev, plat); |
456 | } | |
457 | ||
ccacb703 | 458 | static struct stmmac_pci_info tgl_sgmii1g_info = { |
58da0cfa VW |
459 | .setup = tgl_sgmii_data, |
460 | }; | |
461 | ||
462 | static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { | |
463 | { | |
464 | .func = 6, | |
465 | .phy_addr = 1, | |
466 | }, | |
467 | }; | |
468 | ||
469 | static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { | |
470 | .func = galileo_stmmac_func_data, | |
471 | .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), | |
472 | }; | |
473 | ||
474 | static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { | |
475 | { | |
476 | .func = 6, | |
477 | .phy_addr = 1, | |
478 | }, | |
479 | { | |
480 | .func = 7, | |
481 | .phy_addr = 1, | |
482 | }, | |
483 | }; | |
484 | ||
485 | static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { | |
486 | .func = iot2040_stmmac_func_data, | |
487 | .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), | |
488 | }; | |
489 | ||
490 | static const struct dmi_system_id quark_pci_dmi[] = { | |
491 | { | |
492 | .matches = { | |
493 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), | |
494 | }, | |
495 | .driver_data = (void *)&galileo_stmmac_dmi_data, | |
496 | }, | |
497 | { | |
498 | .matches = { | |
499 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), | |
500 | }, | |
501 | .driver_data = (void *)&galileo_stmmac_dmi_data, | |
502 | }, | |
503 | /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. | |
504 | * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which | |
505 | * has only one pci network device while other asset tags are | |
506 | * for IOT2040 which has two. | |
507 | */ | |
508 | { | |
509 | .matches = { | |
510 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), | |
511 | DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, | |
512 | "6ES7647-0AA00-0YA2"), | |
513 | }, | |
514 | .driver_data = (void *)&galileo_stmmac_dmi_data, | |
515 | }, | |
516 | { | |
517 | .matches = { | |
518 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), | |
519 | }, | |
520 | .driver_data = (void *)&iot2040_stmmac_dmi_data, | |
521 | }, | |
522 | {} | |
523 | }; | |
524 | ||
525 | static int quark_default_data(struct pci_dev *pdev, | |
526 | struct plat_stmmacenet_data *plat) | |
527 | { | |
528 | int ret; | |
529 | ||
530 | /* Set common default data first */ | |
531 | common_default_data(plat); | |
532 | ||
533 | /* Refuse to load the driver and register net device if MAC controller | |
534 | * does not connect to any PHY interface. | |
535 | */ | |
536 | ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); | |
537 | if (ret < 0) { | |
538 | /* Return error to the caller on DMI enabled boards. */ | |
539 | if (dmi_get_system_info(DMI_BOARD_NAME)) | |
540 | return ret; | |
541 | ||
542 | /* Galileo boards with old firmware don't support DMI. We always | |
543 | * use 1 here as PHY address, so at least the first found MAC | |
544 | * controller would be probed. | |
545 | */ | |
546 | ret = 1; | |
547 | } | |
548 | ||
549 | plat->bus_id = pci_dev_id(pdev); | |
550 | plat->phy_addr = ret; | |
551 | plat->phy_interface = PHY_INTERFACE_MODE_RMII; | |
552 | ||
553 | plat->dma_cfg->pbl = 16; | |
554 | plat->dma_cfg->pblx8 = true; | |
555 | plat->dma_cfg->fixed_burst = 1; | |
556 | /* AXI (TODO) */ | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
ccacb703 | 561 | static const struct stmmac_pci_info quark_info = { |
58da0cfa VW |
562 | .setup = quark_default_data, |
563 | }; | |
564 | ||
565 | /** | |
566 | * intel_eth_pci_probe | |
567 | * | |
568 | * @pdev: pci device pointer | |
569 | * @id: pointer to table of device id/id's. | |
570 | * | |
571 | * Description: This probing function gets called for all PCI devices which | |
572 | * match the ID table and are not "owned" by other driver yet. This function | |
573 | * gets passed a "struct pci_dev *" for each device whose entry in the ID table | |
574 | * matches the device. The probe functions returns zero when the driver choose | |
575 | * to take "ownership" of the device or an error code(-ve no) otherwise. | |
576 | */ | |
577 | static int intel_eth_pci_probe(struct pci_dev *pdev, | |
578 | const struct pci_device_id *id) | |
579 | { | |
580 | struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; | |
b9663b7c | 581 | struct intel_priv_data *intel_priv; |
58da0cfa VW |
582 | struct plat_stmmacenet_data *plat; |
583 | struct stmmac_resources res; | |
58da0cfa VW |
584 | int ret; |
585 | ||
ccacb703 | 586 | intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); |
b9663b7c VW |
587 | if (!intel_priv) |
588 | return -ENOMEM; | |
589 | ||
58da0cfa VW |
590 | plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); |
591 | if (!plat) | |
592 | return -ENOMEM; | |
593 | ||
594 | plat->mdio_bus_data = devm_kzalloc(&pdev->dev, | |
595 | sizeof(*plat->mdio_bus_data), | |
596 | GFP_KERNEL); | |
597 | if (!plat->mdio_bus_data) | |
598 | return -ENOMEM; | |
599 | ||
600 | plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), | |
601 | GFP_KERNEL); | |
602 | if (!plat->dma_cfg) | |
603 | return -ENOMEM; | |
604 | ||
605 | /* Enable pci device */ | |
606 | ret = pci_enable_device(pdev); | |
607 | if (ret) { | |
608 | dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", | |
609 | __func__); | |
610 | return ret; | |
611 | } | |
612 | ||
e578f043 AS |
613 | ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); |
614 | if (ret) | |
615 | return ret; | |
58da0cfa VW |
616 | |
617 | pci_set_master(pdev); | |
618 | ||
b9663b7c VW |
619 | plat->bsp_priv = intel_priv; |
620 | intel_priv->mdio_adhoc_addr = 0x15; | |
621 | ||
58da0cfa VW |
622 | ret = info->setup(pdev, plat); |
623 | if (ret) | |
624 | return ret; | |
625 | ||
52c1f794 AS |
626 | ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
627 | if (ret < 0) | |
628 | return ret; | |
58da0cfa VW |
629 | |
630 | memset(&res, 0, sizeof(res)); | |
e578f043 | 631 | res.addr = pcim_iomap_table(pdev)[0]; |
52c1f794 AS |
632 | res.wol_irq = pci_irq_vector(pdev, 0); |
633 | res.irq = pci_irq_vector(pdev, 0); | |
58da0cfa | 634 | |
785ff20b WVK |
635 | if (plat->eee_usecs_rate > 0) { |
636 | u32 tx_lpi_usec; | |
637 | ||
638 | tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; | |
639 | writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER); | |
640 | } | |
641 | ||
09f012e6 AS |
642 | ret = stmmac_dvr_probe(&pdev->dev, plat, &res); |
643 | if (ret) { | |
52c1f794 | 644 | pci_free_irq_vectors(pdev); |
09f012e6 AS |
645 | clk_disable_unprepare(plat->stmmac_clk); |
646 | clk_unregister_fixed_rate(plat->stmmac_clk); | |
647 | } | |
648 | ||
649 | return ret; | |
58da0cfa VW |
650 | } |
651 | ||
652 | /** | |
653 | * intel_eth_pci_remove | |
654 | * | |
655 | * @pdev: platform device pointer | |
656 | * Description: this function calls the main to free the net resources | |
657 | * and releases the PCI resources. | |
658 | */ | |
659 | static void intel_eth_pci_remove(struct pci_dev *pdev) | |
660 | { | |
661 | struct net_device *ndev = dev_get_drvdata(&pdev->dev); | |
662 | struct stmmac_priv *priv = netdev_priv(ndev); | |
58da0cfa VW |
663 | |
664 | stmmac_dvr_remove(&pdev->dev); | |
665 | ||
52c1f794 AS |
666 | pci_free_irq_vectors(pdev); |
667 | ||
09f012e6 | 668 | clk_unregister_fixed_rate(priv->plat->stmmac_clk); |
58da0cfa | 669 | |
e578f043 | 670 | pcim_iounmap_regions(pdev, BIT(0)); |
58da0cfa VW |
671 | |
672 | pci_disable_device(pdev); | |
673 | } | |
674 | ||
675 | static int __maybe_unused intel_eth_pci_suspend(struct device *dev) | |
676 | { | |
677 | struct pci_dev *pdev = to_pci_dev(dev); | |
678 | int ret; | |
679 | ||
680 | ret = stmmac_suspend(dev); | |
681 | if (ret) | |
682 | return ret; | |
683 | ||
684 | ret = pci_save_state(pdev); | |
685 | if (ret) | |
686 | return ret; | |
687 | ||
688 | pci_disable_device(pdev); | |
689 | pci_wake_from_d3(pdev, true); | |
690 | return 0; | |
691 | } | |
692 | ||
693 | static int __maybe_unused intel_eth_pci_resume(struct device *dev) | |
694 | { | |
695 | struct pci_dev *pdev = to_pci_dev(dev); | |
696 | int ret; | |
697 | ||
698 | pci_restore_state(pdev); | |
699 | pci_set_power_state(pdev, PCI_D0); | |
700 | ||
701 | ret = pci_enable_device(pdev); | |
702 | if (ret) | |
703 | return ret; | |
704 | ||
705 | pci_set_master(pdev); | |
706 | ||
707 | return stmmac_resume(dev); | |
708 | } | |
709 | ||
710 | static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, | |
711 | intel_eth_pci_resume); | |
712 | ||
d63439f5 VW |
713 | #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 |
714 | #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 | |
715 | #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 | |
716 | #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 | |
67c08ac4 VW |
717 | /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC |
718 | * which are named PSE0 and PSE1 | |
719 | */ | |
d63439f5 VW |
720 | #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 |
721 | #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 | |
722 | #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 | |
723 | #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 | |
724 | #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 | |
725 | #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 | |
8450e23f NAAT |
726 | #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac |
727 | #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2 | |
d63439f5 | 728 | #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac |
58da0cfa VW |
729 | |
730 | static const struct pci_device_id intel_eth_pci_id_table[] = { | |
ccacb703 AS |
731 | { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) }, |
732 | { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) }, | |
733 | { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) }, | |
734 | { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) }, | |
735 | { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) }, | |
736 | { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) }, | |
737 | { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) }, | |
738 | { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) }, | |
739 | { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) }, | |
740 | { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) }, | |
741 | { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) }, | |
8450e23f NAAT |
742 | { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) }, |
743 | { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) }, | |
58da0cfa VW |
744 | {} |
745 | }; | |
58da0cfa VW |
746 | MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); |
747 | ||
748 | static struct pci_driver intel_eth_pci_driver = { | |
749 | .name = "intel-eth-pci", | |
750 | .id_table = intel_eth_pci_id_table, | |
751 | .probe = intel_eth_pci_probe, | |
752 | .remove = intel_eth_pci_remove, | |
753 | .driver = { | |
754 | .pm = &intel_eth_pm_ops, | |
755 | }, | |
756 | }; | |
757 | ||
758 | module_pci_driver(intel_eth_pci_driver); | |
759 | ||
760 | MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); | |
761 | MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); | |
762 | MODULE_LICENSE("GPL v2"); |