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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
7ad269ea RC |
2 | /** |
3 | * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer | |
4 | * | |
5 | * Copyright (C) 2014 Chen-Zhi (Roger Chen) | |
6 | * | |
7 | * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> | |
7ad269ea RC |
8 | */ |
9 | ||
10 | #include <linux/stmmac.h> | |
11 | #include <linux/bitops.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/phy.h> | |
14 | #include <linux/of_net.h> | |
15 | #include <linux/gpio.h> | |
e0fb4013 | 16 | #include <linux/module.h> |
7ad269ea RC |
17 | #include <linux/of_gpio.h> |
18 | #include <linux/of_device.h> | |
e0fb4013 | 19 | #include <linux/platform_device.h> |
7ad269ea RC |
20 | #include <linux/regulator/consumer.h> |
21 | #include <linux/delay.h> | |
22 | #include <linux/mfd/syscon.h> | |
23 | #include <linux/regmap.h> | |
2c896fb0 | 24 | #include <linux/pm_runtime.h> |
7ad269ea | 25 | |
e0fb4013 JE |
26 | #include "stmmac_platform.h" |
27 | ||
0fb98db1 HS |
28 | struct rk_priv_data; |
29 | struct rk_gmac_ops { | |
30 | void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, | |
31 | int tx_delay, int rx_delay); | |
32 | void (*set_to_rmii)(struct rk_priv_data *bsp_priv); | |
33 | void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); | |
34 | void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); | |
fecd4d7e | 35 | void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); |
0fb98db1 HS |
36 | }; |
37 | ||
7ad269ea RC |
38 | struct rk_priv_data { |
39 | struct platform_device *pdev; | |
40 | int phy_iface; | |
2e12f536 | 41 | struct regulator *regulator; |
229666c1 | 42 | bool suspended; |
92c2588f | 43 | const struct rk_gmac_ops *ops; |
7ad269ea RC |
44 | |
45 | bool clk_enabled; | |
46 | bool clock_input; | |
fecd4d7e | 47 | bool integrated_phy; |
7ad269ea RC |
48 | |
49 | struct clk *clk_mac; | |
7ad269ea RC |
50 | struct clk *gmac_clkin; |
51 | struct clk *mac_clk_rx; | |
52 | struct clk *mac_clk_tx; | |
53 | struct clk *clk_mac_ref; | |
54 | struct clk *clk_mac_refout; | |
23c94d63 | 55 | struct clk *clk_mac_speed; |
7ad269ea RC |
56 | struct clk *aclk_mac; |
57 | struct clk *pclk_mac; | |
fecd4d7e DW |
58 | struct clk *clk_phy; |
59 | ||
60 | struct reset_control *phy_reset; | |
7ad269ea RC |
61 | |
62 | int tx_delay; | |
63 | int rx_delay; | |
64 | ||
65 | struct regmap *grf; | |
66 | }; | |
67 | ||
68 | #define HIWORD_UPDATE(val, mask, shift) \ | |
69 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
70 | ||
71 | #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) | |
72 | #define GRF_CLR_BIT(nr) (BIT(nr+16)) | |
73 | ||
eaf70ad1 WE |
74 | #define DELAY_ENABLE(soc, tx, rx) \ |
75 | (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ | |
76 | ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) | |
77 | ||
23c94d63 DW |
78 | #define PX30_GRF_GMAC_CON1 0x0904 |
79 | ||
80 | /* PX30_GRF_GMAC_CON1 */ | |
81 | #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ | |
82 | GRF_BIT(6)) | |
83 | #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) | |
84 | #define PX30_GMAC_SPEED_100M GRF_BIT(2) | |
85 | ||
86 | static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) | |
87 | { | |
88 | struct device *dev = &bsp_priv->pdev->dev; | |
89 | ||
90 | if (IS_ERR(bsp_priv->grf)) { | |
91 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
92 | return; | |
93 | } | |
94 | ||
95 | regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, | |
96 | PX30_GMAC_PHY_INTF_SEL_RMII); | |
97 | } | |
98 | ||
99 | static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
100 | { | |
101 | struct device *dev = &bsp_priv->pdev->dev; | |
102 | int ret; | |
103 | ||
104 | if (IS_ERR(bsp_priv->clk_mac_speed)) { | |
105 | dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); | |
106 | return; | |
107 | } | |
108 | ||
109 | if (speed == 10) { | |
110 | regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, | |
111 | PX30_GMAC_SPEED_10M); | |
112 | ||
113 | ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000); | |
114 | if (ret) | |
115 | dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n", | |
116 | __func__, ret); | |
117 | } else if (speed == 100) { | |
118 | regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, | |
119 | PX30_GMAC_SPEED_100M); | |
120 | ||
121 | ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000); | |
122 | if (ret) | |
123 | dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n", | |
124 | __func__, ret); | |
125 | ||
126 | } else { | |
127 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
128 | } | |
129 | } | |
130 | ||
131 | static const struct rk_gmac_ops px30_ops = { | |
132 | .set_to_rmii = px30_set_to_rmii, | |
133 | .set_rmii_speed = px30_set_rmii_speed, | |
134 | }; | |
135 | ||
05946876 DW |
136 | #define RK3128_GRF_MAC_CON0 0x0168 |
137 | #define RK3128_GRF_MAC_CON1 0x016c | |
138 | ||
139 | /* RK3128_GRF_MAC_CON0 */ | |
140 | #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) | |
141 | #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) | |
142 | #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) | |
143 | #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) | |
144 | #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) | |
145 | #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
146 | ||
147 | /* RK3128_GRF_MAC_CON1 */ | |
148 | #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ | |
149 | (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) | |
150 | #define RK3128_GMAC_PHY_INTF_SEL_RMII \ | |
151 | (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) | |
152 | #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) | |
153 | #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) | |
154 | #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) | |
155 | #define RK3128_GMAC_SPEED_100M GRF_BIT(10) | |
156 | #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) | |
157 | #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) | |
158 | #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) | |
159 | #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) | |
160 | #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) | |
161 | #define RK3128_GMAC_RMII_MODE GRF_BIT(14) | |
162 | #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) | |
163 | ||
164 | static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, | |
165 | int tx_delay, int rx_delay) | |
166 | { | |
167 | struct device *dev = &bsp_priv->pdev->dev; | |
168 | ||
169 | if (IS_ERR(bsp_priv->grf)) { | |
170 | dev_err(dev, "Missing rockchip,grf property\n"); | |
171 | return; | |
172 | } | |
173 | ||
174 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
175 | RK3128_GMAC_PHY_INTF_SEL_RGMII | | |
176 | RK3128_GMAC_RMII_MODE_CLR); | |
177 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, | |
178 | DELAY_ENABLE(RK3128, tx_delay, rx_delay) | | |
179 | RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | | |
180 | RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
181 | } | |
182 | ||
183 | static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) | |
184 | { | |
185 | struct device *dev = &bsp_priv->pdev->dev; | |
186 | ||
187 | if (IS_ERR(bsp_priv->grf)) { | |
188 | dev_err(dev, "Missing rockchip,grf property\n"); | |
189 | return; | |
190 | } | |
191 | ||
192 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
193 | RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); | |
194 | } | |
195 | ||
196 | static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
197 | { | |
198 | struct device *dev = &bsp_priv->pdev->dev; | |
199 | ||
200 | if (IS_ERR(bsp_priv->grf)) { | |
201 | dev_err(dev, "Missing rockchip,grf property\n"); | |
202 | return; | |
203 | } | |
204 | ||
205 | if (speed == 10) | |
206 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
207 | RK3128_GMAC_CLK_2_5M); | |
208 | else if (speed == 100) | |
209 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
210 | RK3128_GMAC_CLK_25M); | |
211 | else if (speed == 1000) | |
212 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
213 | RK3128_GMAC_CLK_125M); | |
214 | else | |
215 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
216 | } | |
217 | ||
218 | static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
219 | { | |
220 | struct device *dev = &bsp_priv->pdev->dev; | |
221 | ||
222 | if (IS_ERR(bsp_priv->grf)) { | |
223 | dev_err(dev, "Missing rockchip,grf property\n"); | |
224 | return; | |
225 | } | |
226 | ||
227 | if (speed == 10) { | |
228 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
229 | RK3128_GMAC_RMII_CLK_2_5M | | |
230 | RK3128_GMAC_SPEED_10M); | |
231 | } else if (speed == 100) { | |
232 | regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, | |
233 | RK3128_GMAC_RMII_CLK_25M | | |
234 | RK3128_GMAC_SPEED_100M); | |
235 | } else { | |
236 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
237 | } | |
238 | } | |
239 | ||
240 | static const struct rk_gmac_ops rk3128_ops = { | |
241 | .set_to_rgmii = rk3128_set_to_rgmii, | |
242 | .set_to_rmii = rk3128_set_to_rmii, | |
243 | .set_rgmii_speed = rk3128_set_rgmii_speed, | |
244 | .set_rmii_speed = rk3128_set_rmii_speed, | |
245 | }; | |
246 | ||
e7ffd812 XZ |
247 | #define RK3228_GRF_MAC_CON0 0x0900 |
248 | #define RK3228_GRF_MAC_CON1 0x0904 | |
249 | ||
6fa12c78 DW |
250 | #define RK3228_GRF_CON_MUX 0x50 |
251 | ||
e7ffd812 XZ |
252 | /* RK3228_GRF_MAC_CON0 */ |
253 | #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) | |
254 | #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
255 | ||
256 | /* RK3228_GRF_MAC_CON1 */ | |
257 | #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ | |
258 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) | |
259 | #define RK3228_GMAC_PHY_INTF_SEL_RMII \ | |
260 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) | |
261 | #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) | |
262 | #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) | |
263 | #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) | |
264 | #define RK3228_GMAC_SPEED_100M GRF_BIT(2) | |
265 | #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) | |
266 | #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) | |
267 | #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) | |
268 | #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) | |
269 | #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) | |
270 | #define RK3228_GMAC_RMII_MODE GRF_BIT(10) | |
271 | #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) | |
272 | #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) | |
273 | #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) | |
274 | #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) | |
275 | #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) | |
276 | ||
6fa12c78 DW |
277 | /* RK3228_GRF_COM_MUX */ |
278 | #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) | |
279 | ||
e7ffd812 XZ |
280 | static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, |
281 | int tx_delay, int rx_delay) | |
282 | { | |
283 | struct device *dev = &bsp_priv->pdev->dev; | |
284 | ||
285 | if (IS_ERR(bsp_priv->grf)) { | |
286 | dev_err(dev, "Missing rockchip,grf property\n"); | |
287 | return; | |
288 | } | |
289 | ||
290 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
291 | RK3228_GMAC_PHY_INTF_SEL_RGMII | | |
292 | RK3228_GMAC_RMII_MODE_CLR | | |
eaf70ad1 | 293 | DELAY_ENABLE(RK3228, tx_delay, rx_delay)); |
e7ffd812 XZ |
294 | |
295 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, | |
296 | RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | | |
297 | RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
298 | } | |
299 | ||
300 | static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) | |
301 | { | |
302 | struct device *dev = &bsp_priv->pdev->dev; | |
303 | ||
304 | if (IS_ERR(bsp_priv->grf)) { | |
305 | dev_err(dev, "Missing rockchip,grf property\n"); | |
306 | return; | |
307 | } | |
308 | ||
309 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
310 | RK3228_GMAC_PHY_INTF_SEL_RMII | | |
311 | RK3228_GMAC_RMII_MODE); | |
312 | ||
313 | /* set MAC to RMII mode */ | |
314 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); | |
315 | } | |
316 | ||
317 | static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
318 | { | |
319 | struct device *dev = &bsp_priv->pdev->dev; | |
320 | ||
321 | if (IS_ERR(bsp_priv->grf)) { | |
322 | dev_err(dev, "Missing rockchip,grf property\n"); | |
323 | return; | |
324 | } | |
325 | ||
326 | if (speed == 10) | |
327 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
328 | RK3228_GMAC_CLK_2_5M); | |
329 | else if (speed == 100) | |
330 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
331 | RK3228_GMAC_CLK_25M); | |
332 | else if (speed == 1000) | |
333 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
334 | RK3228_GMAC_CLK_125M); | |
335 | else | |
336 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
337 | } | |
338 | ||
339 | static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
340 | { | |
341 | struct device *dev = &bsp_priv->pdev->dev; | |
342 | ||
343 | if (IS_ERR(bsp_priv->grf)) { | |
344 | dev_err(dev, "Missing rockchip,grf property\n"); | |
345 | return; | |
346 | } | |
347 | ||
348 | if (speed == 10) | |
349 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
350 | RK3228_GMAC_RMII_CLK_2_5M | | |
351 | RK3228_GMAC_SPEED_10M); | |
352 | else if (speed == 100) | |
353 | regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, | |
354 | RK3228_GMAC_RMII_CLK_25M | | |
355 | RK3228_GMAC_SPEED_100M); | |
356 | else | |
357 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
358 | } | |
359 | ||
6fa12c78 DW |
360 | static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) |
361 | { | |
362 | regmap_write(priv->grf, RK3228_GRF_CON_MUX, | |
363 | RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); | |
364 | } | |
365 | ||
e7ffd812 XZ |
366 | static const struct rk_gmac_ops rk3228_ops = { |
367 | .set_to_rgmii = rk3228_set_to_rgmii, | |
368 | .set_to_rmii = rk3228_set_to_rmii, | |
369 | .set_rgmii_speed = rk3228_set_rgmii_speed, | |
370 | .set_rmii_speed = rk3228_set_rmii_speed, | |
6fa12c78 | 371 | .integrated_phy_powerup = rk3228_integrated_phy_powerup, |
e7ffd812 XZ |
372 | }; |
373 | ||
7ad269ea RC |
374 | #define RK3288_GRF_SOC_CON1 0x0248 |
375 | #define RK3288_GRF_SOC_CON3 0x0250 | |
7ad269ea RC |
376 | |
377 | /*RK3288_GRF_SOC_CON1*/ | |
0fb98db1 HS |
378 | #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ |
379 | GRF_CLR_BIT(8)) | |
380 | #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ | |
381 | GRF_BIT(8)) | |
382 | #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) | |
383 | #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) | |
384 | #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) | |
385 | #define RK3288_GMAC_SPEED_100M GRF_BIT(10) | |
386 | #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) | |
387 | #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) | |
388 | #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) | |
389 | #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) | |
390 | #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) | |
391 | #define RK3288_GMAC_RMII_MODE GRF_BIT(14) | |
392 | #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) | |
7ad269ea RC |
393 | |
394 | /*RK3288_GRF_SOC_CON3*/ | |
0fb98db1 HS |
395 | #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) |
396 | #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) | |
397 | #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) | |
398 | #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) | |
399 | #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) | |
400 | #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
401 | ||
402 | static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, | |
403 | int tx_delay, int rx_delay) | |
7ad269ea RC |
404 | { |
405 | struct device *dev = &bsp_priv->pdev->dev; | |
406 | ||
407 | if (IS_ERR(bsp_priv->grf)) { | |
d42202dc | 408 | dev_err(dev, "Missing rockchip,grf property\n"); |
7ad269ea RC |
409 | return; |
410 | } | |
411 | ||
412 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, | |
0fb98db1 HS |
413 | RK3288_GMAC_PHY_INTF_SEL_RGMII | |
414 | RK3288_GMAC_RMII_MODE_CLR); | |
7ad269ea | 415 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, |
eaf70ad1 | 416 | DELAY_ENABLE(RK3288, tx_delay, rx_delay) | |
0fb98db1 HS |
417 | RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | |
418 | RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
7ad269ea RC |
419 | } |
420 | ||
0fb98db1 | 421 | static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) |
7ad269ea RC |
422 | { |
423 | struct device *dev = &bsp_priv->pdev->dev; | |
424 | ||
425 | if (IS_ERR(bsp_priv->grf)) { | |
d42202dc | 426 | dev_err(dev, "Missing rockchip,grf property\n"); |
7ad269ea RC |
427 | return; |
428 | } | |
429 | ||
430 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, | |
0fb98db1 | 431 | RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); |
7ad269ea RC |
432 | } |
433 | ||
0fb98db1 | 434 | static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
7ad269ea RC |
435 | { |
436 | struct device *dev = &bsp_priv->pdev->dev; | |
437 | ||
438 | if (IS_ERR(bsp_priv->grf)) { | |
d42202dc | 439 | dev_err(dev, "Missing rockchip,grf property\n"); |
7ad269ea RC |
440 | return; |
441 | } | |
442 | ||
443 | if (speed == 10) | |
0fb98db1 HS |
444 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
445 | RK3288_GMAC_CLK_2_5M); | |
7ad269ea | 446 | else if (speed == 100) |
0fb98db1 HS |
447 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
448 | RK3288_GMAC_CLK_25M); | |
7ad269ea | 449 | else if (speed == 1000) |
0fb98db1 HS |
450 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, |
451 | RK3288_GMAC_CLK_125M); | |
7ad269ea RC |
452 | else |
453 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
454 | } | |
455 | ||
0fb98db1 | 456 | static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
7ad269ea RC |
457 | { |
458 | struct device *dev = &bsp_priv->pdev->dev; | |
459 | ||
460 | if (IS_ERR(bsp_priv->grf)) { | |
d42202dc | 461 | dev_err(dev, "Missing rockchip,grf property\n"); |
7ad269ea RC |
462 | return; |
463 | } | |
464 | ||
465 | if (speed == 10) { | |
466 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, | |
0fb98db1 HS |
467 | RK3288_GMAC_RMII_CLK_2_5M | |
468 | RK3288_GMAC_SPEED_10M); | |
7ad269ea RC |
469 | } else if (speed == 100) { |
470 | regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, | |
0fb98db1 HS |
471 | RK3288_GMAC_RMII_CLK_25M | |
472 | RK3288_GMAC_SPEED_100M); | |
7ad269ea RC |
473 | } else { |
474 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
475 | } | |
476 | } | |
477 | ||
92c2588f | 478 | static const struct rk_gmac_ops rk3288_ops = { |
0fb98db1 HS |
479 | .set_to_rgmii = rk3288_set_to_rgmii, |
480 | .set_to_rmii = rk3288_set_to_rmii, | |
481 | .set_rgmii_speed = rk3288_set_rgmii_speed, | |
482 | .set_rmii_speed = rk3288_set_rmii_speed, | |
483 | }; | |
484 | ||
d4ff816e | 485 | #define RK3328_GRF_MAC_CON0 0x0900 |
486 | #define RK3328_GRF_MAC_CON1 0x0904 | |
8bdf63bd DW |
487 | #define RK3328_GRF_MAC_CON2 0x0908 |
488 | #define RK3328_GRF_MACPHY_CON1 0xb04 | |
d4ff816e | 489 | |
490 | /* RK3328_GRF_MAC_CON0 */ | |
491 | #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) | |
492 | #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
493 | ||
494 | /* RK3328_GRF_MAC_CON1 */ | |
495 | #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ | |
496 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) | |
497 | #define RK3328_GMAC_PHY_INTF_SEL_RMII \ | |
498 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) | |
499 | #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) | |
500 | #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) | |
501 | #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) | |
502 | #define RK3328_GMAC_SPEED_100M GRF_BIT(2) | |
503 | #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) | |
504 | #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) | |
505 | #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) | |
506 | #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) | |
507 | #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) | |
508 | #define RK3328_GMAC_RMII_MODE GRF_BIT(9) | |
509 | #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) | |
510 | #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) | |
511 | #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) | |
512 | #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) | |
513 | #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) | |
514 | ||
8bdf63bd DW |
515 | /* RK3328_GRF_MACPHY_CON1 */ |
516 | #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) | |
517 | ||
d4ff816e | 518 | static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, |
519 | int tx_delay, int rx_delay) | |
520 | { | |
521 | struct device *dev = &bsp_priv->pdev->dev; | |
522 | ||
523 | if (IS_ERR(bsp_priv->grf)) { | |
524 | dev_err(dev, "Missing rockchip,grf property\n"); | |
525 | return; | |
526 | } | |
527 | ||
528 | regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, | |
529 | RK3328_GMAC_PHY_INTF_SEL_RGMII | | |
530 | RK3328_GMAC_RMII_MODE_CLR | | |
531 | RK3328_GMAC_RXCLK_DLY_ENABLE | | |
532 | RK3328_GMAC_TXCLK_DLY_ENABLE); | |
533 | ||
534 | regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0, | |
535 | RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | | |
536 | RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
537 | } | |
538 | ||
539 | static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) | |
540 | { | |
541 | struct device *dev = &bsp_priv->pdev->dev; | |
8bdf63bd | 542 | unsigned int reg; |
d4ff816e | 543 | |
544 | if (IS_ERR(bsp_priv->grf)) { | |
545 | dev_err(dev, "Missing rockchip,grf property\n"); | |
546 | return; | |
547 | } | |
548 | ||
8bdf63bd DW |
549 | reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : |
550 | RK3328_GRF_MAC_CON1; | |
551 | ||
552 | regmap_write(bsp_priv->grf, reg, | |
d4ff816e | 553 | RK3328_GMAC_PHY_INTF_SEL_RMII | |
554 | RK3328_GMAC_RMII_MODE); | |
d4ff816e | 555 | } |
556 | ||
557 | static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
558 | { | |
559 | struct device *dev = &bsp_priv->pdev->dev; | |
560 | ||
561 | if (IS_ERR(bsp_priv->grf)) { | |
562 | dev_err(dev, "Missing rockchip,grf property\n"); | |
563 | return; | |
564 | } | |
565 | ||
566 | if (speed == 10) | |
567 | regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, | |
568 | RK3328_GMAC_CLK_2_5M); | |
569 | else if (speed == 100) | |
570 | regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, | |
571 | RK3328_GMAC_CLK_25M); | |
572 | else if (speed == 1000) | |
573 | regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, | |
574 | RK3328_GMAC_CLK_125M); | |
575 | else | |
576 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
577 | } | |
578 | ||
579 | static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
580 | { | |
581 | struct device *dev = &bsp_priv->pdev->dev; | |
8bdf63bd | 582 | unsigned int reg; |
d4ff816e | 583 | |
584 | if (IS_ERR(bsp_priv->grf)) { | |
585 | dev_err(dev, "Missing rockchip,grf property\n"); | |
586 | return; | |
587 | } | |
588 | ||
8bdf63bd DW |
589 | reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : |
590 | RK3328_GRF_MAC_CON1; | |
591 | ||
d4ff816e | 592 | if (speed == 10) |
8bdf63bd | 593 | regmap_write(bsp_priv->grf, reg, |
d4ff816e | 594 | RK3328_GMAC_RMII_CLK_2_5M | |
595 | RK3328_GMAC_SPEED_10M); | |
596 | else if (speed == 100) | |
8bdf63bd | 597 | regmap_write(bsp_priv->grf, reg, |
d4ff816e | 598 | RK3328_GMAC_RMII_CLK_25M | |
599 | RK3328_GMAC_SPEED_100M); | |
600 | else | |
601 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
602 | } | |
603 | ||
8bdf63bd DW |
604 | static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) |
605 | { | |
606 | regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, | |
607 | RK3328_MACPHY_RMII_MODE); | |
608 | } | |
609 | ||
d4ff816e | 610 | static const struct rk_gmac_ops rk3328_ops = { |
611 | .set_to_rgmii = rk3328_set_to_rgmii, | |
612 | .set_to_rmii = rk3328_set_to_rmii, | |
613 | .set_rgmii_speed = rk3328_set_rgmii_speed, | |
614 | .set_rmii_speed = rk3328_set_rmii_speed, | |
8bdf63bd | 615 | .integrated_phy_powerup = rk3328_integrated_phy_powerup, |
d4ff816e | 616 | }; |
617 | ||
ba289af8 RC |
618 | #define RK3366_GRF_SOC_CON6 0x0418 |
619 | #define RK3366_GRF_SOC_CON7 0x041c | |
620 | ||
621 | /* RK3366_GRF_SOC_CON6 */ | |
622 | #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ | |
623 | GRF_CLR_BIT(11)) | |
624 | #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ | |
625 | GRF_BIT(11)) | |
626 | #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) | |
627 | #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) | |
628 | #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) | |
629 | #define RK3366_GMAC_SPEED_100M GRF_BIT(7) | |
630 | #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) | |
631 | #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) | |
632 | #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) | |
633 | #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) | |
634 | #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) | |
635 | #define RK3366_GMAC_RMII_MODE GRF_BIT(6) | |
636 | #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) | |
637 | ||
638 | /* RK3366_GRF_SOC_CON7 */ | |
639 | #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) | |
640 | #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) | |
641 | #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) | |
642 | #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) | |
643 | #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) | |
644 | #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
645 | ||
646 | static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, | |
647 | int tx_delay, int rx_delay) | |
648 | { | |
649 | struct device *dev = &bsp_priv->pdev->dev; | |
650 | ||
651 | if (IS_ERR(bsp_priv->grf)) { | |
652 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
653 | return; | |
654 | } | |
655 | ||
656 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
657 | RK3366_GMAC_PHY_INTF_SEL_RGMII | | |
658 | RK3366_GMAC_RMII_MODE_CLR); | |
659 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, | |
eaf70ad1 | 660 | DELAY_ENABLE(RK3366, tx_delay, rx_delay) | |
ba289af8 RC |
661 | RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | |
662 | RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
663 | } | |
664 | ||
665 | static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) | |
666 | { | |
667 | struct device *dev = &bsp_priv->pdev->dev; | |
668 | ||
669 | if (IS_ERR(bsp_priv->grf)) { | |
670 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
671 | return; | |
672 | } | |
673 | ||
674 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
675 | RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); | |
676 | } | |
677 | ||
678 | static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
679 | { | |
680 | struct device *dev = &bsp_priv->pdev->dev; | |
681 | ||
682 | if (IS_ERR(bsp_priv->grf)) { | |
683 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
684 | return; | |
685 | } | |
686 | ||
687 | if (speed == 10) | |
688 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
689 | RK3366_GMAC_CLK_2_5M); | |
690 | else if (speed == 100) | |
691 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
692 | RK3366_GMAC_CLK_25M); | |
693 | else if (speed == 1000) | |
694 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
695 | RK3366_GMAC_CLK_125M); | |
696 | else | |
697 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
698 | } | |
699 | ||
700 | static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
701 | { | |
702 | struct device *dev = &bsp_priv->pdev->dev; | |
703 | ||
704 | if (IS_ERR(bsp_priv->grf)) { | |
705 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
706 | return; | |
707 | } | |
708 | ||
709 | if (speed == 10) { | |
710 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
711 | RK3366_GMAC_RMII_CLK_2_5M | | |
712 | RK3366_GMAC_SPEED_10M); | |
713 | } else if (speed == 100) { | |
714 | regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, | |
715 | RK3366_GMAC_RMII_CLK_25M | | |
716 | RK3366_GMAC_SPEED_100M); | |
717 | } else { | |
718 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
719 | } | |
720 | } | |
721 | ||
722 | static const struct rk_gmac_ops rk3366_ops = { | |
723 | .set_to_rgmii = rk3366_set_to_rgmii, | |
724 | .set_to_rmii = rk3366_set_to_rmii, | |
725 | .set_rgmii_speed = rk3366_set_rgmii_speed, | |
726 | .set_rmii_speed = rk3366_set_rmii_speed, | |
727 | }; | |
728 | ||
df558854 HS |
729 | #define RK3368_GRF_SOC_CON15 0x043c |
730 | #define RK3368_GRF_SOC_CON16 0x0440 | |
731 | ||
732 | /* RK3368_GRF_SOC_CON15 */ | |
733 | #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ | |
734 | GRF_CLR_BIT(11)) | |
735 | #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ | |
736 | GRF_BIT(11)) | |
737 | #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) | |
738 | #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) | |
739 | #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) | |
740 | #define RK3368_GMAC_SPEED_100M GRF_BIT(7) | |
741 | #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) | |
742 | #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) | |
743 | #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) | |
744 | #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) | |
745 | #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) | |
746 | #define RK3368_GMAC_RMII_MODE GRF_BIT(6) | |
747 | #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) | |
748 | ||
749 | /* RK3368_GRF_SOC_CON16 */ | |
750 | #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) | |
751 | #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) | |
752 | #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) | |
753 | #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) | |
754 | #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) | |
755 | #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
756 | ||
757 | static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, | |
758 | int tx_delay, int rx_delay) | |
759 | { | |
760 | struct device *dev = &bsp_priv->pdev->dev; | |
761 | ||
762 | if (IS_ERR(bsp_priv->grf)) { | |
763 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
764 | return; | |
765 | } | |
766 | ||
767 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
768 | RK3368_GMAC_PHY_INTF_SEL_RGMII | | |
769 | RK3368_GMAC_RMII_MODE_CLR); | |
770 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, | |
eaf70ad1 | 771 | DELAY_ENABLE(RK3368, tx_delay, rx_delay) | |
df558854 HS |
772 | RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | |
773 | RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
774 | } | |
775 | ||
776 | static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) | |
777 | { | |
778 | struct device *dev = &bsp_priv->pdev->dev; | |
779 | ||
780 | if (IS_ERR(bsp_priv->grf)) { | |
781 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
782 | return; | |
783 | } | |
784 | ||
785 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
786 | RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); | |
787 | } | |
788 | ||
789 | static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
790 | { | |
791 | struct device *dev = &bsp_priv->pdev->dev; | |
792 | ||
793 | if (IS_ERR(bsp_priv->grf)) { | |
794 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
795 | return; | |
796 | } | |
797 | ||
798 | if (speed == 10) | |
799 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
800 | RK3368_GMAC_CLK_2_5M); | |
801 | else if (speed == 100) | |
802 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
803 | RK3368_GMAC_CLK_25M); | |
804 | else if (speed == 1000) | |
805 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
806 | RK3368_GMAC_CLK_125M); | |
807 | else | |
808 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
809 | } | |
810 | ||
811 | static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
812 | { | |
813 | struct device *dev = &bsp_priv->pdev->dev; | |
814 | ||
815 | if (IS_ERR(bsp_priv->grf)) { | |
816 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
817 | return; | |
818 | } | |
819 | ||
820 | if (speed == 10) { | |
821 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
822 | RK3368_GMAC_RMII_CLK_2_5M | | |
823 | RK3368_GMAC_SPEED_10M); | |
824 | } else if (speed == 100) { | |
825 | regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, | |
826 | RK3368_GMAC_RMII_CLK_25M | | |
827 | RK3368_GMAC_SPEED_100M); | |
828 | } else { | |
829 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
830 | } | |
831 | } | |
832 | ||
92c2588f | 833 | static const struct rk_gmac_ops rk3368_ops = { |
df558854 HS |
834 | .set_to_rgmii = rk3368_set_to_rgmii, |
835 | .set_to_rmii = rk3368_set_to_rmii, | |
836 | .set_rgmii_speed = rk3368_set_rgmii_speed, | |
837 | .set_rmii_speed = rk3368_set_rmii_speed, | |
838 | }; | |
839 | ||
ba289af8 RC |
840 | #define RK3399_GRF_SOC_CON5 0xc214 |
841 | #define RK3399_GRF_SOC_CON6 0xc218 | |
842 | ||
843 | /* RK3399_GRF_SOC_CON5 */ | |
844 | #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ | |
845 | GRF_CLR_BIT(11)) | |
846 | #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ | |
847 | GRF_BIT(11)) | |
848 | #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) | |
849 | #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) | |
850 | #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) | |
851 | #define RK3399_GMAC_SPEED_100M GRF_BIT(7) | |
852 | #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) | |
853 | #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) | |
854 | #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) | |
855 | #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) | |
856 | #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) | |
857 | #define RK3399_GMAC_RMII_MODE GRF_BIT(6) | |
858 | #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) | |
859 | ||
860 | /* RK3399_GRF_SOC_CON6 */ | |
861 | #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) | |
862 | #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) | |
863 | #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) | |
864 | #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) | |
865 | #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) | |
866 | #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) | |
867 | ||
868 | static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, | |
869 | int tx_delay, int rx_delay) | |
870 | { | |
871 | struct device *dev = &bsp_priv->pdev->dev; | |
872 | ||
873 | if (IS_ERR(bsp_priv->grf)) { | |
874 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
875 | return; | |
876 | } | |
877 | ||
878 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
879 | RK3399_GMAC_PHY_INTF_SEL_RGMII | | |
880 | RK3399_GMAC_RMII_MODE_CLR); | |
881 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, | |
eaf70ad1 | 882 | DELAY_ENABLE(RK3399, tx_delay, rx_delay) | |
ba289af8 RC |
883 | RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | |
884 | RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); | |
885 | } | |
886 | ||
887 | static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) | |
888 | { | |
889 | struct device *dev = &bsp_priv->pdev->dev; | |
890 | ||
891 | if (IS_ERR(bsp_priv->grf)) { | |
892 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
893 | return; | |
894 | } | |
895 | ||
896 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
897 | RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); | |
898 | } | |
899 | ||
900 | static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
901 | { | |
902 | struct device *dev = &bsp_priv->pdev->dev; | |
903 | ||
904 | if (IS_ERR(bsp_priv->grf)) { | |
905 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
906 | return; | |
907 | } | |
908 | ||
909 | if (speed == 10) | |
910 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
911 | RK3399_GMAC_CLK_2_5M); | |
912 | else if (speed == 100) | |
913 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
914 | RK3399_GMAC_CLK_25M); | |
915 | else if (speed == 1000) | |
916 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
917 | RK3399_GMAC_CLK_125M); | |
918 | else | |
919 | dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); | |
920 | } | |
921 | ||
922 | static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
923 | { | |
924 | struct device *dev = &bsp_priv->pdev->dev; | |
925 | ||
926 | if (IS_ERR(bsp_priv->grf)) { | |
927 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
928 | return; | |
929 | } | |
930 | ||
931 | if (speed == 10) { | |
932 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
933 | RK3399_GMAC_RMII_CLK_2_5M | | |
934 | RK3399_GMAC_SPEED_10M); | |
935 | } else if (speed == 100) { | |
936 | regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, | |
937 | RK3399_GMAC_RMII_CLK_25M | | |
938 | RK3399_GMAC_SPEED_100M); | |
939 | } else { | |
940 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
941 | } | |
942 | } | |
943 | ||
944 | static const struct rk_gmac_ops rk3399_ops = { | |
945 | .set_to_rgmii = rk3399_set_to_rgmii, | |
946 | .set_to_rmii = rk3399_set_to_rmii, | |
947 | .set_rgmii_speed = rk3399_set_rgmii_speed, | |
948 | .set_rmii_speed = rk3399_set_rmii_speed, | |
949 | }; | |
950 | ||
89c9c163 DW |
951 | #define RV1108_GRF_GMAC_CON0 0X0900 |
952 | ||
953 | /* RV1108_GRF_GMAC_CON0 */ | |
954 | #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ | |
955 | GRF_BIT(6)) | |
956 | #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) | |
957 | #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) | |
958 | #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) | |
959 | #define RV1108_GMAC_SPEED_100M GRF_BIT(2) | |
960 | #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) | |
961 | #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) | |
962 | ||
963 | static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) | |
964 | { | |
965 | struct device *dev = &bsp_priv->pdev->dev; | |
966 | ||
967 | if (IS_ERR(bsp_priv->grf)) { | |
968 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
969 | return; | |
970 | } | |
971 | ||
972 | regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, | |
973 | RV1108_GMAC_PHY_INTF_SEL_RMII); | |
974 | } | |
975 | ||
976 | static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) | |
977 | { | |
978 | struct device *dev = &bsp_priv->pdev->dev; | |
979 | ||
980 | if (IS_ERR(bsp_priv->grf)) { | |
981 | dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); | |
982 | return; | |
983 | } | |
984 | ||
985 | if (speed == 10) { | |
986 | regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, | |
987 | RV1108_GMAC_RMII_CLK_2_5M | | |
988 | RV1108_GMAC_SPEED_10M); | |
989 | } else if (speed == 100) { | |
990 | regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, | |
991 | RV1108_GMAC_RMII_CLK_25M | | |
992 | RV1108_GMAC_SPEED_100M); | |
993 | } else { | |
994 | dev_err(dev, "unknown speed value for RMII! speed=%d", speed); | |
995 | } | |
996 | } | |
997 | ||
998 | static const struct rk_gmac_ops rv1108_ops = { | |
999 | .set_to_rmii = rv1108_set_to_rmii, | |
1000 | .set_rmii_speed = rv1108_set_rmii_speed, | |
1001 | }; | |
1002 | ||
fecd4d7e DW |
1003 | #define RK_GRF_MACPHY_CON0 0xb00 |
1004 | #define RK_GRF_MACPHY_CON1 0xb04 | |
1005 | #define RK_GRF_MACPHY_CON2 0xb08 | |
1006 | #define RK_GRF_MACPHY_CON3 0xb0c | |
1007 | ||
1008 | #define RK_MACPHY_ENABLE GRF_BIT(0) | |
1009 | #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) | |
1010 | #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) | |
1011 | #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) | |
1012 | #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) | |
1013 | #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) | |
1014 | ||
1015 | static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) | |
1016 | { | |
1017 | if (priv->ops->integrated_phy_powerup) | |
1018 | priv->ops->integrated_phy_powerup(priv); | |
1019 | ||
1020 | regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); | |
1021 | regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); | |
1022 | ||
1023 | regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); | |
1024 | regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); | |
1025 | ||
1026 | if (priv->phy_reset) { | |
1027 | /* PHY needs to be disabled before trying to reset it */ | |
1028 | regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); | |
1029 | if (priv->phy_reset) | |
1030 | reset_control_assert(priv->phy_reset); | |
1031 | usleep_range(10, 20); | |
1032 | if (priv->phy_reset) | |
1033 | reset_control_deassert(priv->phy_reset); | |
1034 | usleep_range(10, 20); | |
1035 | regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); | |
1036 | msleep(30); | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) | |
7ad269ea | 1041 | { |
fecd4d7e DW |
1042 | regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); |
1043 | if (priv->phy_reset) | |
1044 | reset_control_assert(priv->phy_reset); | |
1045 | } | |
1046 | ||
1047 | static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) | |
1048 | { | |
1049 | struct rk_priv_data *bsp_priv = plat->bsp_priv; | |
7ad269ea | 1050 | struct device *dev = &bsp_priv->pdev->dev; |
fecd4d7e | 1051 | int ret; |
7ad269ea RC |
1052 | |
1053 | bsp_priv->clk_enabled = false; | |
1054 | ||
1055 | bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); | |
1056 | if (IS_ERR(bsp_priv->mac_clk_rx)) | |
d42202dc RP |
1057 | dev_err(dev, "cannot get clock %s\n", |
1058 | "mac_clk_rx"); | |
7ad269ea RC |
1059 | |
1060 | bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); | |
1061 | if (IS_ERR(bsp_priv->mac_clk_tx)) | |
d42202dc RP |
1062 | dev_err(dev, "cannot get clock %s\n", |
1063 | "mac_clk_tx"); | |
7ad269ea RC |
1064 | |
1065 | bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); | |
1066 | if (IS_ERR(bsp_priv->aclk_mac)) | |
d42202dc RP |
1067 | dev_err(dev, "cannot get clock %s\n", |
1068 | "aclk_mac"); | |
7ad269ea RC |
1069 | |
1070 | bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); | |
1071 | if (IS_ERR(bsp_priv->pclk_mac)) | |
d42202dc RP |
1072 | dev_err(dev, "cannot get clock %s\n", |
1073 | "pclk_mac"); | |
7ad269ea RC |
1074 | |
1075 | bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); | |
1076 | if (IS_ERR(bsp_priv->clk_mac)) | |
d42202dc RP |
1077 | dev_err(dev, "cannot get clock %s\n", |
1078 | "stmmaceth"); | |
7ad269ea RC |
1079 | |
1080 | if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { | |
1081 | bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); | |
1082 | if (IS_ERR(bsp_priv->clk_mac_ref)) | |
d42202dc RP |
1083 | dev_err(dev, "cannot get clock %s\n", |
1084 | "clk_mac_ref"); | |
7ad269ea RC |
1085 | |
1086 | if (!bsp_priv->clock_input) { | |
1087 | bsp_priv->clk_mac_refout = | |
1088 | devm_clk_get(dev, "clk_mac_refout"); | |
1089 | if (IS_ERR(bsp_priv->clk_mac_refout)) | |
d42202dc RP |
1090 | dev_err(dev, "cannot get clock %s\n", |
1091 | "clk_mac_refout"); | |
7ad269ea RC |
1092 | } |
1093 | } | |
1094 | ||
23c94d63 DW |
1095 | bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed"); |
1096 | if (IS_ERR(bsp_priv->clk_mac_speed)) | |
1097 | dev_err(dev, "cannot get clock %s\n", "clk_mac_speed"); | |
1098 | ||
7ad269ea | 1099 | if (bsp_priv->clock_input) { |
d42202dc | 1100 | dev_info(dev, "clock input from PHY\n"); |
7ad269ea RC |
1101 | } else { |
1102 | if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) | |
c48fa33c | 1103 | clk_set_rate(bsp_priv->clk_mac, 50000000); |
7ad269ea RC |
1104 | } |
1105 | ||
fecd4d7e DW |
1106 | if (plat->phy_node && bsp_priv->integrated_phy) { |
1107 | bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0); | |
1108 | if (IS_ERR(bsp_priv->clk_phy)) { | |
1109 | ret = PTR_ERR(bsp_priv->clk_phy); | |
1110 | dev_err(dev, "Cannot get PHY clock: %d\n", ret); | |
1111 | return -EINVAL; | |
1112 | } | |
1113 | clk_set_rate(bsp_priv->clk_phy, 50000000); | |
1114 | } | |
1115 | ||
7ad269ea RC |
1116 | return 0; |
1117 | } | |
1118 | ||
1119 | static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) | |
1120 | { | |
428ad1bc | 1121 | int phy_iface = bsp_priv->phy_iface; |
7ad269ea RC |
1122 | |
1123 | if (enable) { | |
1124 | if (!bsp_priv->clk_enabled) { | |
1125 | if (phy_iface == PHY_INTERFACE_MODE_RMII) { | |
1126 | if (!IS_ERR(bsp_priv->mac_clk_rx)) | |
1127 | clk_prepare_enable( | |
1128 | bsp_priv->mac_clk_rx); | |
1129 | ||
1130 | if (!IS_ERR(bsp_priv->clk_mac_ref)) | |
1131 | clk_prepare_enable( | |
1132 | bsp_priv->clk_mac_ref); | |
1133 | ||
1134 | if (!IS_ERR(bsp_priv->clk_mac_refout)) | |
1135 | clk_prepare_enable( | |
1136 | bsp_priv->clk_mac_refout); | |
1137 | } | |
1138 | ||
fecd4d7e DW |
1139 | if (!IS_ERR(bsp_priv->clk_phy)) |
1140 | clk_prepare_enable(bsp_priv->clk_phy); | |
1141 | ||
7ad269ea RC |
1142 | if (!IS_ERR(bsp_priv->aclk_mac)) |
1143 | clk_prepare_enable(bsp_priv->aclk_mac); | |
1144 | ||
1145 | if (!IS_ERR(bsp_priv->pclk_mac)) | |
1146 | clk_prepare_enable(bsp_priv->pclk_mac); | |
1147 | ||
1148 | if (!IS_ERR(bsp_priv->mac_clk_tx)) | |
1149 | clk_prepare_enable(bsp_priv->mac_clk_tx); | |
1150 | ||
23c94d63 DW |
1151 | if (!IS_ERR(bsp_priv->clk_mac_speed)) |
1152 | clk_prepare_enable(bsp_priv->clk_mac_speed); | |
1153 | ||
7ad269ea RC |
1154 | /** |
1155 | * if (!IS_ERR(bsp_priv->clk_mac)) | |
1156 | * clk_prepare_enable(bsp_priv->clk_mac); | |
1157 | */ | |
1158 | mdelay(5); | |
1159 | bsp_priv->clk_enabled = true; | |
1160 | } | |
1161 | } else { | |
1162 | if (bsp_priv->clk_enabled) { | |
1163 | if (phy_iface == PHY_INTERFACE_MODE_RMII) { | |
93120eba | 1164 | clk_disable_unprepare(bsp_priv->mac_clk_rx); |
7ad269ea | 1165 | |
93120eba | 1166 | clk_disable_unprepare(bsp_priv->clk_mac_ref); |
7ad269ea | 1167 | |
93120eba | 1168 | clk_disable_unprepare(bsp_priv->clk_mac_refout); |
7ad269ea RC |
1169 | } |
1170 | ||
93120eba | 1171 | clk_disable_unprepare(bsp_priv->clk_phy); |
fecd4d7e | 1172 | |
93120eba | 1173 | clk_disable_unprepare(bsp_priv->aclk_mac); |
7ad269ea | 1174 | |
93120eba | 1175 | clk_disable_unprepare(bsp_priv->pclk_mac); |
7ad269ea | 1176 | |
93120eba | 1177 | clk_disable_unprepare(bsp_priv->mac_clk_tx); |
23c94d63 DW |
1178 | |
1179 | clk_disable_unprepare(bsp_priv->clk_mac_speed); | |
7ad269ea RC |
1180 | /** |
1181 | * if (!IS_ERR(bsp_priv->clk_mac)) | |
1182 | * clk_disable_unprepare(bsp_priv->clk_mac); | |
1183 | */ | |
1184 | bsp_priv->clk_enabled = false; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) | |
1192 | { | |
2e12f536 | 1193 | struct regulator *ldo = bsp_priv->regulator; |
7ad269ea RC |
1194 | int ret; |
1195 | struct device *dev = &bsp_priv->pdev->dev; | |
1196 | ||
2e12f536 | 1197 | if (!ldo) { |
d42202dc | 1198 | dev_err(dev, "no regulator found\n"); |
7ad269ea RC |
1199 | return -1; |
1200 | } | |
1201 | ||
2e12f536 RP |
1202 | if (enable) { |
1203 | ret = regulator_enable(ldo); | |
1204 | if (ret) | |
d42202dc | 1205 | dev_err(dev, "fail to enable phy-supply\n"); |
7ad269ea | 1206 | } else { |
2e12f536 RP |
1207 | ret = regulator_disable(ldo); |
1208 | if (ret) | |
d42202dc | 1209 | dev_err(dev, "fail to disable phy-supply\n"); |
7ad269ea RC |
1210 | } |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
0fb98db1 | 1215 | static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, |
fecd4d7e | 1216 | struct plat_stmmacenet_data *plat, |
92c2588f | 1217 | const struct rk_gmac_ops *ops) |
7ad269ea RC |
1218 | { |
1219 | struct rk_priv_data *bsp_priv; | |
1220 | struct device *dev = &pdev->dev; | |
1221 | int ret; | |
1222 | const char *strings = NULL; | |
1223 | int value; | |
1224 | ||
1225 | bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); | |
1226 | if (!bsp_priv) | |
1227 | return ERR_PTR(-ENOMEM); | |
1228 | ||
1229 | bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); | |
0fb98db1 | 1230 | bsp_priv->ops = ops; |
7ad269ea | 1231 | |
2e12f536 RP |
1232 | bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); |
1233 | if (IS_ERR(bsp_priv->regulator)) { | |
1234 | if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { | |
1235 | dev_err(dev, "phy regulator is not available yet, deferred probing\n"); | |
1236 | return ERR_PTR(-EPROBE_DEFER); | |
1237 | } | |
1238 | dev_err(dev, "no regulator found\n"); | |
1239 | bsp_priv->regulator = NULL; | |
7ad269ea RC |
1240 | } |
1241 | ||
1242 | ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); | |
1243 | if (ret) { | |
d42202dc | 1244 | dev_err(dev, "Can not read property: clock_in_out.\n"); |
7ad269ea RC |
1245 | bsp_priv->clock_input = true; |
1246 | } else { | |
d42202dc RP |
1247 | dev_info(dev, "clock input or output? (%s).\n", |
1248 | strings); | |
7ad269ea RC |
1249 | if (!strcmp(strings, "input")) |
1250 | bsp_priv->clock_input = true; | |
1251 | else | |
1252 | bsp_priv->clock_input = false; | |
1253 | } | |
1254 | ||
1255 | ret = of_property_read_u32(dev->of_node, "tx_delay", &value); | |
1256 | if (ret) { | |
1257 | bsp_priv->tx_delay = 0x30; | |
d42202dc RP |
1258 | dev_err(dev, "Can not read property: tx_delay."); |
1259 | dev_err(dev, "set tx_delay to 0x%x\n", | |
1260 | bsp_priv->tx_delay); | |
7ad269ea | 1261 | } else { |
d42202dc | 1262 | dev_info(dev, "TX delay(0x%x).\n", value); |
7ad269ea RC |
1263 | bsp_priv->tx_delay = value; |
1264 | } | |
1265 | ||
1266 | ret = of_property_read_u32(dev->of_node, "rx_delay", &value); | |
1267 | if (ret) { | |
1268 | bsp_priv->rx_delay = 0x10; | |
d42202dc RP |
1269 | dev_err(dev, "Can not read property: rx_delay."); |
1270 | dev_err(dev, "set rx_delay to 0x%x\n", | |
1271 | bsp_priv->rx_delay); | |
7ad269ea | 1272 | } else { |
d42202dc | 1273 | dev_info(dev, "RX delay(0x%x).\n", value); |
7ad269ea RC |
1274 | bsp_priv->rx_delay = value; |
1275 | } | |
1276 | ||
1277 | bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1278 | "rockchip,grf"); | |
7ad269ea | 1279 | |
fecd4d7e DW |
1280 | if (plat->phy_node) { |
1281 | bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, | |
1282 | "phy-is-integrated"); | |
1283 | if (bsp_priv->integrated_phy) { | |
1284 | bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL); | |
1285 | if (IS_ERR(bsp_priv->phy_reset)) { | |
1286 | dev_err(&pdev->dev, "No PHY reset control found.\n"); | |
1287 | bsp_priv->phy_reset = NULL; | |
1288 | } | |
1289 | } | |
1290 | } | |
1291 | dev_info(dev, "integrated PHY? (%s).\n", | |
1292 | bsp_priv->integrated_phy ? "yes" : "no"); | |
1293 | ||
1294 | bsp_priv->pdev = pdev; | |
45383f52 RC |
1295 | |
1296 | return bsp_priv; | |
1297 | } | |
1298 | ||
1299 | static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) | |
1300 | { | |
1301 | int ret; | |
1302 | struct device *dev = &bsp_priv->pdev->dev; | |
1303 | ||
f217bfde HS |
1304 | ret = gmac_clk_enable(bsp_priv, true); |
1305 | if (ret) | |
1306 | return ret; | |
1307 | ||
7ad269ea | 1308 | /*rmii or rgmii*/ |
eaf70ad1 WE |
1309 | switch (bsp_priv->phy_iface) { |
1310 | case PHY_INTERFACE_MODE_RGMII: | |
d42202dc | 1311 | dev_info(dev, "init for RGMII\n"); |
0fb98db1 HS |
1312 | bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, |
1313 | bsp_priv->rx_delay); | |
eaf70ad1 WE |
1314 | break; |
1315 | case PHY_INTERFACE_MODE_RGMII_ID: | |
1316 | dev_info(dev, "init for RGMII_ID\n"); | |
1317 | bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); | |
1318 | break; | |
1319 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
1320 | dev_info(dev, "init for RGMII_RXID\n"); | |
1321 | bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); | |
1322 | break; | |
1323 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
1324 | dev_info(dev, "init for RGMII_TXID\n"); | |
1325 | bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); | |
1326 | break; | |
1327 | case PHY_INTERFACE_MODE_RMII: | |
d42202dc | 1328 | dev_info(dev, "init for RMII\n"); |
0fb98db1 | 1329 | bsp_priv->ops->set_to_rmii(bsp_priv); |
eaf70ad1 WE |
1330 | break; |
1331 | default: | |
d42202dc | 1332 | dev_err(dev, "NO interface defined!\n"); |
7ad269ea RC |
1333 | } |
1334 | ||
7ad269ea | 1335 | ret = phy_power_on(bsp_priv, true); |
c69c29a1 AK |
1336 | if (ret) { |
1337 | gmac_clk_enable(bsp_priv, false); | |
7ad269ea | 1338 | return ret; |
c69c29a1 | 1339 | } |
7ad269ea | 1340 | |
2c896fb0 DW |
1341 | pm_runtime_enable(dev); |
1342 | pm_runtime_get_sync(dev); | |
1343 | ||
fecd4d7e DW |
1344 | if (bsp_priv->integrated_phy) |
1345 | rk_gmac_integrated_phy_powerup(bsp_priv); | |
1346 | ||
7ad269ea RC |
1347 | return 0; |
1348 | } | |
1349 | ||
229666c1 | 1350 | static void rk_gmac_powerdown(struct rk_priv_data *gmac) |
7ad269ea | 1351 | { |
2c896fb0 DW |
1352 | struct device *dev = &gmac->pdev->dev; |
1353 | ||
fecd4d7e DW |
1354 | if (gmac->integrated_phy) |
1355 | rk_gmac_integrated_phy_powerdown(gmac); | |
1356 | ||
2c896fb0 DW |
1357 | pm_runtime_put_sync(dev); |
1358 | pm_runtime_disable(dev); | |
1359 | ||
7ad269ea RC |
1360 | phy_power_on(gmac, false); |
1361 | gmac_clk_enable(gmac, false); | |
1362 | } | |
1363 | ||
1364 | static void rk_fix_speed(void *priv, unsigned int speed) | |
1365 | { | |
1366 | struct rk_priv_data *bsp_priv = priv; | |
1367 | struct device *dev = &bsp_priv->pdev->dev; | |
1368 | ||
eaf70ad1 WE |
1369 | switch (bsp_priv->phy_iface) { |
1370 | case PHY_INTERFACE_MODE_RGMII: | |
1371 | case PHY_INTERFACE_MODE_RGMII_ID: | |
1372 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
1373 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
0fb98db1 | 1374 | bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); |
eaf70ad1 WE |
1375 | break; |
1376 | case PHY_INTERFACE_MODE_RMII: | |
0fb98db1 | 1377 | bsp_priv->ops->set_rmii_speed(bsp_priv, speed); |
eaf70ad1 WE |
1378 | break; |
1379 | default: | |
7ad269ea | 1380 | dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); |
eaf70ad1 | 1381 | } |
7ad269ea RC |
1382 | } |
1383 | ||
27ffefd2 JE |
1384 | static int rk_gmac_probe(struct platform_device *pdev) |
1385 | { | |
1386 | struct plat_stmmacenet_data *plat_dat; | |
1387 | struct stmmac_resources stmmac_res; | |
f529f182 | 1388 | const struct rk_gmac_ops *data; |
27ffefd2 JE |
1389 | int ret; |
1390 | ||
149adedd JE |
1391 | data = of_device_get_match_data(&pdev->dev); |
1392 | if (!data) { | |
1393 | dev_err(&pdev->dev, "no of match data provided\n"); | |
1394 | return -EINVAL; | |
1395 | } | |
1396 | ||
27ffefd2 JE |
1397 | ret = stmmac_get_platform_resources(pdev, &stmmac_res); |
1398 | if (ret) | |
1399 | return ret; | |
1400 | ||
1401 | plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); | |
1402 | if (IS_ERR(plat_dat)) | |
1403 | return PTR_ERR(plat_dat); | |
1404 | ||
1405 | plat_dat->has_gmac = true; | |
27ffefd2 JE |
1406 | plat_dat->fix_mac_speed = rk_fix_speed; |
1407 | ||
fecd4d7e | 1408 | plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data); |
d2ed0a77 JH |
1409 | if (IS_ERR(plat_dat->bsp_priv)) { |
1410 | ret = PTR_ERR(plat_dat->bsp_priv); | |
1411 | goto err_remove_config_dt; | |
1412 | } | |
27ffefd2 | 1413 | |
fecd4d7e DW |
1414 | ret = rk_gmac_clk_init(plat_dat); |
1415 | if (ret) | |
1416 | return ret; | |
1417 | ||
07a5e769 | 1418 | ret = rk_gmac_powerup(plat_dat->bsp_priv); |
27ffefd2 | 1419 | if (ret) |
d2ed0a77 | 1420 | goto err_remove_config_dt; |
27ffefd2 | 1421 | |
2d222656 JH |
1422 | ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); |
1423 | if (ret) | |
2745529a | 1424 | goto err_gmac_powerdown; |
27ffefd2 | 1425 | |
2d222656 JH |
1426 | return 0; |
1427 | ||
2745529a DM |
1428 | err_gmac_powerdown: |
1429 | rk_gmac_powerdown(plat_dat->bsp_priv); | |
d2ed0a77 JH |
1430 | err_remove_config_dt: |
1431 | stmmac_remove_config_dt(pdev, plat_dat); | |
2d222656 JH |
1432 | |
1433 | return ret; | |
27ffefd2 JE |
1434 | } |
1435 | ||
0de8c4c9 JE |
1436 | static int rk_gmac_remove(struct platform_device *pdev) |
1437 | { | |
1438 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev); | |
1439 | int ret = stmmac_dvr_remove(&pdev->dev); | |
1440 | ||
1441 | rk_gmac_powerdown(bsp_priv); | |
1442 | ||
1443 | return ret; | |
1444 | } | |
1445 | ||
5619468a JE |
1446 | #ifdef CONFIG_PM_SLEEP |
1447 | static int rk_gmac_suspend(struct device *dev) | |
1448 | { | |
1449 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); | |
1450 | int ret = stmmac_suspend(dev); | |
1451 | ||
1452 | /* Keep the PHY up if we use Wake-on-Lan. */ | |
1453 | if (!device_may_wakeup(dev)) { | |
1454 | rk_gmac_powerdown(bsp_priv); | |
1455 | bsp_priv->suspended = true; | |
1456 | } | |
1457 | ||
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | static int rk_gmac_resume(struct device *dev) | |
1462 | { | |
1463 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); | |
1464 | ||
1465 | /* The PHY was up for Wake-on-Lan. */ | |
1466 | if (bsp_priv->suspended) { | |
1467 | rk_gmac_powerup(bsp_priv); | |
1468 | bsp_priv->suspended = false; | |
1469 | } | |
1470 | ||
1471 | return stmmac_resume(dev); | |
1472 | } | |
1473 | #endif /* CONFIG_PM_SLEEP */ | |
1474 | ||
1475 | static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); | |
1476 | ||
e0fb4013 | 1477 | static const struct of_device_id rk_gmac_dwmac_match[] = { |
23c94d63 | 1478 | { .compatible = "rockchip,px30-gmac", .data = &px30_ops }, |
05946876 | 1479 | { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops }, |
e7ffd812 | 1480 | { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops }, |
f529f182 | 1481 | { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops }, |
d4ff816e | 1482 | { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops }, |
ba289af8 | 1483 | { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops }, |
f529f182 | 1484 | { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops }, |
ba289af8 | 1485 | { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops }, |
89c9c163 | 1486 | { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops }, |
e0fb4013 JE |
1487 | { } |
1488 | }; | |
1489 | MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); | |
1490 | ||
1491 | static struct platform_driver rk_gmac_dwmac_driver = { | |
27ffefd2 | 1492 | .probe = rk_gmac_probe, |
0de8c4c9 | 1493 | .remove = rk_gmac_remove, |
e0fb4013 JE |
1494 | .driver = { |
1495 | .name = "rk_gmac-dwmac", | |
5619468a | 1496 | .pm = &rk_gmac_pm_ops, |
e0fb4013 JE |
1497 | .of_match_table = rk_gmac_dwmac_match, |
1498 | }, | |
1499 | }; | |
1500 | module_platform_driver(rk_gmac_dwmac_driver); | |
1501 | ||
1502 | MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>"); | |
1503 | MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer"); | |
1504 | MODULE_LICENSE("GPL"); |