[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-socfpga.c

/* Copyright Altera Corporation (C) 2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2,
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adopted from dwmac-sti.c
 */

#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/stmmac.h>

#include "stmmac.h"
#include "stmmac_platform.h"

#include "altr_tse_pcs.h"

#define SGMII_ADAPTER_CTRL_REG                          0x00
#define SGMII_ADAPTER_DISABLE                           0x0001

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010

#define SYSMGR_FPGAGRP_MODULE_REG  0x00000028
#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004

#define EMAC_SPLITTER_CTRL_REG			0x0
#define EMAC_SPLITTER_CTRL_SPEED_MASK		0x3
#define EMAC_SPLITTER_CTRL_SPEED_10		0x2
#define EMAC_SPLITTER_CTRL_SPEED_100		0x3
#define EMAC_SPLITTER_CTRL_SPEED_1000		0x0

struct socfpga_dwmac {
	int	interface;
	u32	reg_offset;
	u32	reg_shift;
	struct	device *dev;
	struct regmap *sys_mgr_base_addr;
	struct reset_control *stmmac_rst;
	void __iomem *splitter_base;
	bool f2h_ptp_ref_clk;
	struct tse_pcs pcs;
};

static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
{
	struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
	void __iomem *splitter_base = dwmac->splitter_base;
	void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
	void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
	struct device *dev = dwmac->dev;
	struct net_device *ndev = dev_get_drvdata(dev);
	struct phy_device *phy_dev = ndev->phydev;
	u32 val;

	if ((tse_pcs_base) && (sgmii_adapter_base))
		writew(SGMII_ADAPTER_DISABLE,
		       sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);

	if (splitter_base) {
		val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
		val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;

		switch (speed) {
		case 1000:
			val |= EMAC_SPLITTER_CTRL_SPEED_1000;
			break;
		case 100:
			val |= EMAC_SPLITTER_CTRL_SPEED_100;
			break;
		case 10:
			val |= EMAC_SPLITTER_CTRL_SPEED_10;
			break;
		default:
			return;
		}
		writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
	}

	if (tse_pcs_base && sgmii_adapter_base)
		tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
}

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct regmap *sys_mgr_base_addr;
	u32 reg_offset, reg_shift;
	int ret, index;
	struct device_node *np_splitter = NULL;
	struct device_node *np_sgmii_adapter = NULL;
	struct resource res_splitter;
	struct resource res_tse_pcs;
	struct resource res_sgmii_adapter;

	dwmac->interface = of_get_phy_mode(np);

	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	if (IS_ERR(sys_mgr_base_addr)) {
		dev_info(dev, "No sysmgr-syscon node found\n");
		return PTR_ERR(sys_mgr_base_addr);
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	if (ret) {
		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	if (ret) {
		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
		return -EINVAL;
	}

	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");

	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
	if (np_splitter) {
		ret = of_address_to_resource(np_splitter, 0, &res_splitter);
		of_node_put(np_splitter);
		if (ret) {
			dev_info(dev, "Missing emac splitter address\n");
			return -EINVAL;
		}

		dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
		if (IS_ERR(dwmac->splitter_base)) {
			dev_info(dev, "Failed to mapping emac splitter\n");
			return PTR_ERR(dwmac->splitter_base);
		}
	}

	np_sgmii_adapter = of_parse_phandle(np,
					    "altr,gmii-to-sgmii-converter", 0);
	if (np_sgmii_adapter) {
		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "hps_emac_interface_splitter_avalon_slave");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_splitter)) {
				dev_err(dev,
					"%s: ERROR: missing emac splitter address\n",
					__func__);
				ret = -EINVAL;
				goto err_node_put;
			}

			dwmac->splitter_base =
			    devm_ioremap_resource(dev, &res_splitter);

			if (IS_ERR(dwmac->splitter_base)) {
				ret = PTR_ERR(dwmac->splitter_base);
				goto err_node_put;
			}
		}

		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "gmii_to_sgmii_adapter_avalon_slave");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_sgmii_adapter)) {
				dev_err(dev,
					"%s: ERROR: failed mapping adapter\n",
					__func__);
				ret = -EINVAL;
				goto err_node_put;
			}

			dwmac->pcs.sgmii_adapter_base =
			    devm_ioremap_resource(dev, &res_sgmii_adapter);

			if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
				ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base);
				goto err_node_put;
			}
		}

		index = of_property_match_string(np_sgmii_adapter, "reg-names",
						 "eth_tse_control_port");

		if (index >= 0) {
			if (of_address_to_resource(np_sgmii_adapter, index,
						   &res_tse_pcs)) {
				dev_err(dev,
					"%s: ERROR: failed mapping tse control port\n",
					__func__);
				ret = -EINVAL;
				goto err_node_put;
			}

			dwmac->pcs.tse_pcs_base =
			    devm_ioremap_resource(dev, &res_tse_pcs);

			if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
				ret = PTR_ERR(dwmac->pcs.tse_pcs_base);
				goto err_node_put;
			}
		}
	}
	dwmac->reg_offset = reg_offset;
	dwmac->reg_shift = reg_shift;
	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	dwmac->dev = dev;
	of_node_put(np_sgmii_adapter);

	return 0;

err_node_put:
	of_node_put(np_sgmii_adapter);
	return ret;
}

static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
{
	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	int phymode = dwmac->interface;
	u32 reg_offset = dwmac->reg_offset;
	u32 reg_shift = dwmac->reg_shift;
	u32 ctrl, val, module;

	switch (phymode) {
	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
		break;
	case PHY_INTERFACE_MODE_MII:
	case PHY_INTERFACE_MODE_GMII:
	case PHY_INTERFACE_MODE_SGMII:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
		break;
	default:
		dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
		return -EINVAL;
	}

	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	 * is the actual phy mode on phy hardware, but phy interface from
	 * EMAC core is GMII.
	 */
	if (dwmac->splitter_base)
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;

	/* Assert reset to the enet controller before changing the phy mode */
	if (dwmac->stmmac_rst)
		reset_control_assert(dwmac->stmmac_rst);

	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	ctrl |= val << reg_shift;

	if (dwmac->f2h_ptp_ref_clk) {
		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
		regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			    &module);
		module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
		regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
			     module);
	} else {
		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
	}

	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

	/* Deassert reset for the phy configuration to be sampled by
	 * the enet controller, and operation to start in requested mode
	 */
	if (dwmac->stmmac_rst)
		reset_control_deassert(dwmac->stmmac_rst);
	if (phymode == PHY_INTERFACE_MODE_SGMII) {
		if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
			dev_err(dwmac->dev, "Unable to initialize TSE PCS");
			return -EINVAL;
		}
	}

	return 0;
}

static int socfpga_dwmac_probe(struct platform_device *pdev)
{
	struct plat_stmmacenet_data *plat_dat;
	struct stmmac_resources stmmac_res;
	struct device		*dev = &pdev->dev;
	int			ret;
	struct socfpga_dwmac	*dwmac;
	struct net_device	*ndev;
	struct stmmac_priv	*stpriv;

	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	if (ret)
		return ret;

	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	if (IS_ERR(plat_dat))
		return PTR_ERR(plat_dat);

	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
	if (!dwmac) {
		ret = -ENOMEM;
		goto err_remove_config_dt;
	}

	ret = socfpga_dwmac_parse_data(dwmac, dev);
	if (ret) {
		dev_err(dev, "Unable to parse OF data\n");
		goto err_remove_config_dt;
	}

	plat_dat->bsp_priv = dwmac;
	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;

	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
	if (ret)
		goto err_remove_config_dt;

	ndev = platform_get_drvdata(pdev);
	stpriv = netdev_priv(ndev);

	/* The socfpga driver needs to control the stmmac reset to set the phy
	 * mode. Create a copy of the core reset handle so it can be used by
	 * the driver later.
	 */
	dwmac->stmmac_rst = stpriv->stmmac_rst;

	ret = socfpga_dwmac_set_phy_mode(dwmac);
	if (ret)
		goto err_dvr_remove;

	return 0;

err_dvr_remove:
	stmmac_dvr_remove(&pdev->dev);
err_remove_config_dt:
	stmmac_remove_config_dt(pdev, plat_dat);

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int socfpga_dwmac_resume(struct device *dev)
{
	struct net_device *ndev = dev_get_drvdata(dev);
	struct stmmac_priv *priv = netdev_priv(ndev);

	socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);

	/* Before the enet controller is suspended, the phy is suspended.
	 * This causes the phy clock to be gated. The enet controller is
	 * resumed before the phy, so the clock is still gated "off" when
	 * the enet controller is resumed. This code makes sure the phy
	 * is "resumed" before reinitializing the enet controller since
	 * the enet controller depends on an active phy clock to complete
	 * a DMA reset. A DMA reset will "time out" if executed
	 * with no phy clock input on the Synopsys enet controller.
	 * Verified through Synopsys Case #8000711656.
	 *
	 * Note that the phy clock is also gated when the phy is isolated.
	 * Phy "suspend" and "isolate" controls are located in phy basic
	 * control register 0, and can be modified by the phy driver
	 * framework.
	 */
	if (priv->phydev)
		phy_resume(priv->phydev);

	return stmmac_resume(dev);
}
#endif /* CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
					       socfpga_dwmac_resume);

static const struct of_device_id socfpga_dwmac_match[] = {
	{ .compatible = "altr,socfpga-stmmac" },
	{ }
};
MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);

static struct platform_driver socfpga_dwmac_driver = {
	.probe  = socfpga_dwmac_probe,
	.remove = stmmac_pltfr_remove,
	.driver = {
		.name           = "socfpga-dwmac",
		.pm		= &socfpga_dwmac_pm_ops,
		.of_match_table = socfpga_dwmac_match,
	},
};
module_platform_driver(socfpga_dwmac_driver);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
801d233b DN	1	/* Copyright Altera Corporation (C) 2014. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License, version 2,
	5	* as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	14	*
	15	* Adopted from dwmac-sti.c
	16	*/
	17
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/of.h>
b4834c86	20	#include <linux/of_address.h>
801d233b DN	21	#include <linux/of_net.h>
	22	#include <linux/phy.h>
	23	#include <linux/regmap.h>
2d871aa0	24	#include <linux/reset.h>
801d233b	25	#include <linux/stmmac.h>
f10f9fb2	26
2d871aa0	27	#include "stmmac.h"
f10f9fb2	28	#include "stmmac_platform.h"
801d233b	29
fb3bbdb8 THL	30	#include "altr_tse_pcs.h"
	31
	32	#define SGMII_ADAPTER_CTRL_REG 0x00
	33	#define SGMII_ADAPTER_DISABLE 0x0001
	34
801d233b DN	35	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
	36	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
	37	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
	38	#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
	39	#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
43569814	40	#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
801d233b	41
734e00fa PR	42	#define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
	43	#define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
	44
b4834c86 LFT	45	#define EMAC_SPLITTER_CTRL_REG 0x0
	46	#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
	47	#define EMAC_SPLITTER_CTRL_SPEED_10 0x2
	48	#define EMAC_SPLITTER_CTRL_SPEED_100 0x3
	49	#define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
	50
801d233b DN	51	struct socfpga_dwmac {
	52	int interface;
	53	u32 reg_offset;
	54	u32 reg_shift;
	55	struct device *dev;
	56	struct regmap *sys_mgr_base_addr;
70cb136f	57	struct reset_control *stmmac_rst;
b4834c86	58	void __iomem *splitter_base;
43569814	59	bool f2h_ptp_ref_clk;
fb3bbdb8	60	struct tse_pcs pcs;
801d233b DN	61	};
801d233b DN	62
b4834c86 LFT	63	static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
	64	{
	65	struct socfpga_dwmac dwmac = (struct socfpga_dwmac )priv;
	66	void __iomem *splitter_base = dwmac->splitter_base;
fb3bbdb8 THL	67	void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
	68	void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
	69	struct device *dev = dwmac->dev;
	70	struct net_device *ndev = dev_get_drvdata(dev);
	71	struct phy_device *phy_dev = ndev->phydev;
b4834c86 LFT	72	u32 val;
b4834c86 LFT	73
fb3bbdb8 THL	74	if ((tse_pcs_base) && (sgmii_adapter_base))
	75	writew(SGMII_ADAPTER_DISABLE,
	76	sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
	77
	78	if (splitter_base) {
	79	val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
	80	val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
	81
	82	switch (speed) {
	83	case 1000:
	84	val \|= EMAC_SPLITTER_CTRL_SPEED_1000;
	85	break;
	86	case 100:
	87	val \|= EMAC_SPLITTER_CTRL_SPEED_100;
	88	break;
	89	case 10:
	90	val \|= EMAC_SPLITTER_CTRL_SPEED_10;
	91	break;
	92	default:
	93	return;
	94	}
	95	writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
b4834c86 LFT	96	}
b4834c86 LFT	97
fb3bbdb8 THL	98	if (tse_pcs_base && sgmii_adapter_base)
fb3bbdb8 THL	99	tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
b4834c86 LFT	100	}
b4834c86 LFT	101
801d233b DN	102	static int socfpga_dwmac_parse_data(struct socfpga_dwmac dwmac, struct device dev)
	103	{
	104	struct device_node *np = dev->of_node;
	105	struct regmap *sys_mgr_base_addr;
	106	u32 reg_offset, reg_shift;
fb3bbdb8 THL	107	int ret, index;
	108	struct device_node *np_splitter = NULL;
	109	struct device_node *np_sgmii_adapter = NULL;
b4834c86	110	struct resource res_splitter;
fb3bbdb8 THL	111	struct resource res_tse_pcs;
fb3bbdb8 THL	112	struct resource res_sgmii_adapter;
801d233b DN	113
	114	dwmac->interface = of_get_phy_mode(np);
	115
	116	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	117	if (IS_ERR(sys_mgr_base_addr)) {
	118	dev_info(dev, "No sysmgr-syscon node found\n");
	119	return PTR_ERR(sys_mgr_base_addr);
	120	}
	121
	122	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	123	if (ret) {
	124	dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
	125	return -EINVAL;
	126	}
	127
	128	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	129	if (ret) {
	130	dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
	131	return -EINVAL;
	132	}
	133
43569814 PR	134	dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
43569814 PR	135
b4834c86 LFT	136	np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
b4834c86 LFT	137	if (np_splitter) {
f7113b3a PC	138	ret = of_address_to_resource(np_splitter, 0, &res_splitter);
	139	of_node_put(np_splitter);
	140	if (ret) {
b4834c86 LFT	141	dev_info(dev, "Missing emac splitter address\n");
	142	return -EINVAL;
	143	}
	144
dace1b54	145	dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
f19f916d	146	if (IS_ERR(dwmac->splitter_base)) {
b4834c86	147	dev_info(dev, "Failed to mapping emac splitter\n");
f19f916d	148	return PTR_ERR(dwmac->splitter_base);
b4834c86 LFT	149	}
	150	}
	151
fb3bbdb8 THL	152	np_sgmii_adapter = of_parse_phandle(np,
	153	"altr,gmii-to-sgmii-converter", 0);
	154	if (np_sgmii_adapter) {
	155	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	156	"hps_emac_interface_splitter_avalon_slave");
	157
	158	if (index >= 0) {
	159	if (of_address_to_resource(np_sgmii_adapter, index,
	160	&res_splitter)) {
	161	dev_err(dev,
	162	"%s: ERROR: missing emac splitter address\n",
	163	__func__);
f7113b3a PC	164	ret = -EINVAL;
f7113b3a PC	165	goto err_node_put;
fb3bbdb8 THL	166	}
	167
	168	dwmac->splitter_base =
	169	devm_ioremap_resource(dev, &res_splitter);
	170
f7113b3a PC	171	if (IS_ERR(dwmac->splitter_base)) {
	172	ret = PTR_ERR(dwmac->splitter_base);
	173	goto err_node_put;
	174	}
fb3bbdb8 THL	175	}
	176
	177	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	178	"gmii_to_sgmii_adapter_avalon_slave");
	179
	180	if (index >= 0) {
	181	if (of_address_to_resource(np_sgmii_adapter, index,
	182	&res_sgmii_adapter)) {
	183	dev_err(dev,
	184	"%s: ERROR: failed mapping adapter\n",
	185	__func__);
f7113b3a PC	186	ret = -EINVAL;
f7113b3a PC	187	goto err_node_put;
fb3bbdb8 THL	188	}
	189
	190	dwmac->pcs.sgmii_adapter_base =
	191	devm_ioremap_resource(dev, &res_sgmii_adapter);
	192
f7113b3a PC	193	if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
	194	ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base);
	195	goto err_node_put;
	196	}
fb3bbdb8 THL	197	}
	198
	199	index = of_property_match_string(np_sgmii_adapter, "reg-names",
	200	"eth_tse_control_port");
	201
	202	if (index >= 0) {
	203	if (of_address_to_resource(np_sgmii_adapter, index,
	204	&res_tse_pcs)) {
	205	dev_err(dev,
	206	"%s: ERROR: failed mapping tse control port\n",
	207	__func__);
f7113b3a PC	208	ret = -EINVAL;
f7113b3a PC	209	goto err_node_put;
fb3bbdb8 THL	210	}
	211
	212	dwmac->pcs.tse_pcs_base =
	213	devm_ioremap_resource(dev, &res_tse_pcs);
	214
f7113b3a PC	215	if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
	216	ret = PTR_ERR(dwmac->pcs.tse_pcs_base);
	217	goto err_node_put;
	218	}
fb3bbdb8 THL	219	}
fb3bbdb8 THL	220	}
801d233b DN	221	dwmac->reg_offset = reg_offset;
	222	dwmac->reg_shift = reg_shift;
	223	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	224	dwmac->dev = dev;
f7113b3a	225	of_node_put(np_sgmii_adapter);
801d233b DN	226
801d233b DN	227	return 0;
f7113b3a PC	228
	229	err_node_put:
	230	of_node_put(np_sgmii_adapter);
	231	return ret;
801d233b DN	232	}
801d233b DN	233
0f400a87	234	static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
801d233b DN	235	{
	236	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	237	int phymode = dwmac->interface;
	238	u32 reg_offset = dwmac->reg_offset;
	239	u32 reg_shift = dwmac->reg_shift;
734e00fa	240	u32 ctrl, val, module;
801d233b DN	241
	242	switch (phymode) {
	243	case PHY_INTERFACE_MODE_RGMII:
b4834c86	244	case PHY_INTERFACE_MODE_RGMII_ID:
801d233b DN	245	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
	246	break;
	247	case PHY_INTERFACE_MODE_MII:
	248	case PHY_INTERFACE_MODE_GMII:
fb3bbdb8	249	case PHY_INTERFACE_MODE_SGMII:
801d233b DN	250	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	251	break;
	252	default:
	253	dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
	254	return -EINVAL;
	255	}
	256
b4834c86 LFT	257	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	258	* is the actual phy mode on phy hardware, but phy interface from
	259	* EMAC core is GMII.
	260	*/
	261	if (dwmac->splitter_base)
	262	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	263
70cb136f JE	264	/* Assert reset to the enet controller before changing the phy mode */
	265	if (dwmac->stmmac_rst)
	266	reset_control_assert(dwmac->stmmac_rst);
	267
801d233b DN	268	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	269	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	270	ctrl \|= val << reg_shift;
	271
734e00fa	272	if (dwmac->f2h_ptp_ref_clk) {
43569814	273	ctrl \|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
734e00fa PR	274	regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	275	&module);
	276	module \|= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
	277	regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
	278	module);
	279	} else {
43569814	280	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
734e00fa	281	}
43569814	282
801d233b	283	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
734e00fa	284
70cb136f JE	285	/* Deassert reset for the phy configuration to be sampled by
	286	* the enet controller, and operation to start in requested mode
	287	*/
	288	if (dwmac->stmmac_rst)
	289	reset_control_deassert(dwmac->stmmac_rst);
fb3bbdb8 THL	290	if (phymode == PHY_INTERFACE_MODE_SGMII) {
	291	if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
	292	dev_err(dwmac->dev, "Unable to initialize TSE PCS");
	293	return -EINVAL;
	294	}
	295	}
70cb136f	296
801d233b DN	297	return 0;
	298	}
	299
8880b6c8	300	static int socfpga_dwmac_probe(struct platform_device *pdev)
82732789	301	{
8880b6c8 JE	302	struct plat_stmmacenet_data *plat_dat;
8880b6c8 JE	303	struct stmmac_resources stmmac_res;
82732789 JE	304	struct device *dev = &pdev->dev;
	305	int ret;
	306	struct socfpga_dwmac *dwmac;
50ac64cf JH	307	struct net_device *ndev;
50ac64cf JH	308	struct stmmac_priv *stpriv;
82732789	309
8880b6c8 JE	310	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
	311	if (ret)
	312	return ret;
	313
	314	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
	315	if (IS_ERR(plat_dat))
	316	return PTR_ERR(plat_dat);
	317
82732789	318	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
d2ed0a77 JH	319	if (!dwmac) {
	320	ret = -ENOMEM;
	321	goto err_remove_config_dt;
	322	}
82732789 JE	323
	324	ret = socfpga_dwmac_parse_data(dwmac, dev);
	325	if (ret) {
	326	dev_err(dev, "Unable to parse OF data\n");
d2ed0a77	327	goto err_remove_config_dt;
82732789 JE	328	}
82732789 JE	329
8880b6c8	330	plat_dat->bsp_priv = dwmac;
8880b6c8	331	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
82732789	332
3c201b5a	333	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
50ac64cf	334	if (ret)
d2ed0a77	335	goto err_remove_config_dt;
fb3bbdb8	336
50ac64cf JH	337	ndev = platform_get_drvdata(pdev);
50ac64cf JH	338	stpriv = netdev_priv(ndev);
70cb136f	339
50ac64cf JH	340	/* The socfpga driver needs to control the stmmac reset to set the phy
	341	* mode. Create a copy of the core reset handle so it can be used by
	342	* the driver later.
	343	*/
	344	dwmac->stmmac_rst = stpriv->stmmac_rst;
70cb136f	345
50ac64cf JH	346	ret = socfpga_dwmac_set_phy_mode(dwmac);
	347	if (ret)
	348	goto err_dvr_remove;
	349
	350	return 0;
	351
	352	err_dvr_remove:
	353	stmmac_dvr_remove(&pdev->dev);
d2ed0a77 JH	354	err_remove_config_dt:
d2ed0a77 JH	355	stmmac_remove_config_dt(pdev, plat_dat);
8880b6c8	356
3c201b5a	357	return ret;
8880b6c8	358	}
c7c52ae7	359
56868dee JE	360	#ifdef CONFIG_PM_SLEEP
	361	static int socfpga_dwmac_resume(struct device *dev)
	362	{
56868dee JE	363	struct net_device *ndev = dev_get_drvdata(dev);
	364	struct stmmac_priv *priv = netdev_priv(ndev);
	365
0f400a87	366	socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
56868dee	367
53737247 JE	368	/* Before the enet controller is suspended, the phy is suspended.
	369	* This causes the phy clock to be gated. The enet controller is
	370	* resumed before the phy, so the clock is still gated "off" when
	371	* the enet controller is resumed. This code makes sure the phy
	372	* is "resumed" before reinitializing the enet controller since
	373	* the enet controller depends on an active phy clock to complete
	374	* a DMA reset. A DMA reset will "time out" if executed
	375	* with no phy clock input on the Synopsys enet controller.
	376	* Verified through Synopsys Case #8000711656.
	377	*
	378	* Note that the phy clock is also gated when the phy is isolated.
	379	* Phy "suspend" and "isolate" controls are located in phy basic
	380	* control register 0, and can be modified by the phy driver
	381	* framework.
	382	*/
	383	if (priv->phydev)
	384	phy_resume(priv->phydev);
	385
56868dee JE	386	return stmmac_resume(dev);
	387	}
	388	#endif /* CONFIG_PM_SLEEP */
	389
bfca2eba JE	390	static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
bfca2eba JE	391	socfpga_dwmac_resume);
56868dee	392
c7c52ae7	393	static const struct of_device_id socfpga_dwmac_match[] = {
8880b6c8	394	{ .compatible = "altr,socfpga-stmmac" },
c7c52ae7 JE	395	{ }
	396	};
	397	MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
	398
	399	static struct platform_driver socfpga_dwmac_driver = {
8880b6c8	400	.probe = socfpga_dwmac_probe,
c7c52ae7 JE	401	.remove = stmmac_pltfr_remove,
	402	.driver = {
	403	.name = "socfpga-dwmac",
56868dee	404	.pm = &socfpga_dwmac_pm_ops,
c7c52ae7 JE	405	.of_match_table = socfpga_dwmac_match,
	406	},
	407	};
	408	module_platform_driver(socfpga_dwmac_driver);
	409
	410	MODULE_LICENSE("GPL v2");