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9f93ac8d LC |
1 | /* |
2 | * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer | |
3 | * | |
4 | * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/iopoll.h> | |
634db83b | 20 | #include <linux/mdio-mux.h> |
9f93ac8d LC |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_mdio.h> | |
25 | #include <linux/of_net.h> | |
26 | #include <linux/phy.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/regulator/consumer.h> | |
29 | #include <linux/regmap.h> | |
30 | #include <linux/stmmac.h> | |
31 | ||
32 | #include "stmmac.h" | |
33 | #include "stmmac_platform.h" | |
34 | ||
35 | /* General notes on dwmac-sun8i: | |
36 | * Locking: no locking is necessary in this file because all necessary locking | |
37 | * is done in the "stmmac files" | |
38 | */ | |
39 | ||
40 | /* struct emac_variant - Descrive dwmac-sun8i hardware variant | |
41 | * @default_syscon_value: The default value of the EMAC register in syscon | |
42 | * This value is used for disabling properly EMAC | |
43 | * and used as a good starting value in case of the | |
44 | * boot process(uboot) leave some stuff. | |
634db83b | 45 | * @soc_has_internal_phy: Does the MAC embed an internal PHY |
9f93ac8d LC |
46 | * @support_mii: Does the MAC handle MII |
47 | * @support_rmii: Does the MAC handle RMII | |
48 | * @support_rgmii: Does the MAC handle RGMII | |
49 | */ | |
50 | struct emac_variant { | |
51 | u32 default_syscon_value; | |
634db83b | 52 | bool soc_has_internal_phy; |
9f93ac8d LC |
53 | bool support_mii; |
54 | bool support_rmii; | |
55 | bool support_rgmii; | |
56 | }; | |
57 | ||
58 | /* struct sunxi_priv_data - hold all sunxi private data | |
59 | * @tx_clk: reference to MAC TX clock | |
60 | * @ephy_clk: reference to the optional EPHY clock for the internal PHY | |
61 | * @regulator: reference to the optional regulator | |
62 | * @rst_ephy: reference to the optional EPHY reset for the internal PHY | |
63 | * @variant: reference to the current board variant | |
64 | * @regmap: regmap for using the syscon | |
634db83b CL |
65 | * @internal_phy_powered: Does the internal PHY is enabled |
66 | * @mux_handle: Internal pointer used by mdio-mux lib | |
9f93ac8d LC |
67 | */ |
68 | struct sunxi_priv_data { | |
69 | struct clk *tx_clk; | |
70 | struct clk *ephy_clk; | |
71 | struct regulator *regulator; | |
72 | struct reset_control *rst_ephy; | |
73 | const struct emac_variant *variant; | |
74 | struct regmap *regmap; | |
634db83b CL |
75 | bool internal_phy_powered; |
76 | void *mux_handle; | |
9f93ac8d LC |
77 | }; |
78 | ||
79 | static const struct emac_variant emac_variant_h3 = { | |
80 | .default_syscon_value = 0x58000, | |
634db83b | 81 | .soc_has_internal_phy = true, |
9f93ac8d LC |
82 | .support_mii = true, |
83 | .support_rmii = true, | |
84 | .support_rgmii = true | |
85 | }; | |
86 | ||
57fde47d IZ |
87 | static const struct emac_variant emac_variant_v3s = { |
88 | .default_syscon_value = 0x38000, | |
634db83b | 89 | .soc_has_internal_phy = true, |
57fde47d IZ |
90 | .support_mii = true |
91 | }; | |
92 | ||
9f93ac8d LC |
93 | static const struct emac_variant emac_variant_a83t = { |
94 | .default_syscon_value = 0, | |
634db83b | 95 | .soc_has_internal_phy = false, |
9f93ac8d LC |
96 | .support_mii = true, |
97 | .support_rgmii = true | |
98 | }; | |
99 | ||
100 | static const struct emac_variant emac_variant_a64 = { | |
101 | .default_syscon_value = 0, | |
634db83b | 102 | .soc_has_internal_phy = false, |
9f93ac8d LC |
103 | .support_mii = true, |
104 | .support_rmii = true, | |
105 | .support_rgmii = true | |
106 | }; | |
107 | ||
108 | #define EMAC_BASIC_CTL0 0x00 | |
109 | #define EMAC_BASIC_CTL1 0x04 | |
110 | #define EMAC_INT_STA 0x08 | |
111 | #define EMAC_INT_EN 0x0C | |
112 | #define EMAC_TX_CTL0 0x10 | |
113 | #define EMAC_TX_CTL1 0x14 | |
114 | #define EMAC_TX_FLOW_CTL 0x1C | |
115 | #define EMAC_TX_DESC_LIST 0x20 | |
116 | #define EMAC_RX_CTL0 0x24 | |
117 | #define EMAC_RX_CTL1 0x28 | |
118 | #define EMAC_RX_DESC_LIST 0x34 | |
119 | #define EMAC_RX_FRM_FLT 0x38 | |
120 | #define EMAC_MDIO_CMD 0x48 | |
121 | #define EMAC_MDIO_DATA 0x4C | |
122 | #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) | |
123 | #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) | |
124 | #define EMAC_TX_DMA_STA 0xB0 | |
125 | #define EMAC_TX_CUR_DESC 0xB4 | |
126 | #define EMAC_TX_CUR_BUF 0xB8 | |
127 | #define EMAC_RX_DMA_STA 0xC0 | |
128 | #define EMAC_RX_CUR_DESC 0xC4 | |
129 | #define EMAC_RX_CUR_BUF 0xC8 | |
130 | ||
131 | /* Use in EMAC_BASIC_CTL0 */ | |
132 | #define EMAC_DUPLEX_FULL BIT(0) | |
133 | #define EMAC_LOOPBACK BIT(1) | |
134 | #define EMAC_SPEED_1000 0 | |
135 | #define EMAC_SPEED_100 (0x03 << 2) | |
136 | #define EMAC_SPEED_10 (0x02 << 2) | |
137 | ||
138 | /* Use in EMAC_BASIC_CTL1 */ | |
139 | #define EMAC_BURSTLEN_SHIFT 24 | |
140 | ||
141 | /* Used in EMAC_RX_FRM_FLT */ | |
142 | #define EMAC_FRM_FLT_RXALL BIT(0) | |
143 | #define EMAC_FRM_FLT_CTL BIT(13) | |
144 | #define EMAC_FRM_FLT_MULTICAST BIT(16) | |
145 | ||
146 | /* Used in RX_CTL1*/ | |
147 | #define EMAC_RX_MD BIT(1) | |
148 | #define EMAC_RX_TH_MASK GENMASK(4, 5) | |
149 | #define EMAC_RX_TH_32 0 | |
150 | #define EMAC_RX_TH_64 (0x1 << 4) | |
151 | #define EMAC_RX_TH_96 (0x2 << 4) | |
152 | #define EMAC_RX_TH_128 (0x3 << 4) | |
153 | #define EMAC_RX_DMA_EN BIT(30) | |
154 | #define EMAC_RX_DMA_START BIT(31) | |
155 | ||
156 | /* Used in TX_CTL1*/ | |
157 | #define EMAC_TX_MD BIT(1) | |
158 | #define EMAC_TX_NEXT_FRM BIT(2) | |
159 | #define EMAC_TX_TH_MASK GENMASK(8, 10) | |
160 | #define EMAC_TX_TH_64 0 | |
161 | #define EMAC_TX_TH_128 (0x1 << 8) | |
162 | #define EMAC_TX_TH_192 (0x2 << 8) | |
163 | #define EMAC_TX_TH_256 (0x3 << 8) | |
164 | #define EMAC_TX_DMA_EN BIT(30) | |
165 | #define EMAC_TX_DMA_START BIT(31) | |
166 | ||
167 | /* Used in RX_CTL0 */ | |
168 | #define EMAC_RX_RECEIVER_EN BIT(31) | |
169 | #define EMAC_RX_DO_CRC BIT(27) | |
170 | #define EMAC_RX_FLOW_CTL_EN BIT(16) | |
171 | ||
172 | /* Used in TX_CTL0 */ | |
173 | #define EMAC_TX_TRANSMITTER_EN BIT(31) | |
174 | ||
175 | /* Used in EMAC_TX_FLOW_CTL */ | |
176 | #define EMAC_TX_FLOW_CTL_EN BIT(0) | |
177 | ||
178 | /* Used in EMAC_INT_STA */ | |
179 | #define EMAC_TX_INT BIT(0) | |
180 | #define EMAC_TX_DMA_STOP_INT BIT(1) | |
181 | #define EMAC_TX_BUF_UA_INT BIT(2) | |
182 | #define EMAC_TX_TIMEOUT_INT BIT(3) | |
183 | #define EMAC_TX_UNDERFLOW_INT BIT(4) | |
184 | #define EMAC_TX_EARLY_INT BIT(5) | |
185 | #define EMAC_RX_INT BIT(8) | |
186 | #define EMAC_RX_BUF_UA_INT BIT(9) | |
187 | #define EMAC_RX_DMA_STOP_INT BIT(10) | |
188 | #define EMAC_RX_TIMEOUT_INT BIT(11) | |
189 | #define EMAC_RX_OVERFLOW_INT BIT(12) | |
190 | #define EMAC_RX_EARLY_INT BIT(13) | |
191 | #define EMAC_RGMII_STA_INT BIT(16) | |
192 | ||
193 | #define MAC_ADDR_TYPE_DST BIT(31) | |
194 | ||
195 | /* H3 specific bits for EPHY */ | |
196 | #define H3_EPHY_ADDR_SHIFT 20 | |
1450ba8a | 197 | #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ |
9f93ac8d LC |
198 | #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ |
199 | #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ | |
200 | #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ | |
634db83b CL |
201 | #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) |
202 | #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 | |
203 | #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 | |
9f93ac8d LC |
204 | |
205 | /* H3/A64 specific bits */ | |
206 | #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ | |
207 | ||
208 | /* Generic system control EMAC_CLK bits */ | |
209 | #define SYSCON_ETXDC_MASK GENMASK(2, 0) | |
210 | #define SYSCON_ETXDC_SHIFT 10 | |
211 | #define SYSCON_ERXDC_MASK GENMASK(4, 0) | |
212 | #define SYSCON_ERXDC_SHIFT 5 | |
213 | /* EMAC PHY Interface Type */ | |
214 | #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ | |
215 | #define SYSCON_ETCS_MASK GENMASK(1, 0) | |
216 | #define SYSCON_ETCS_MII 0x0 | |
217 | #define SYSCON_ETCS_EXT_GMII 0x1 | |
218 | #define SYSCON_ETCS_INT_GMII 0x2 | |
219 | #define SYSCON_EMAC_REG 0x30 | |
220 | ||
221 | /* sun8i_dwmac_dma_reset() - reset the EMAC | |
222 | * Called from stmmac via stmmac_dma_ops->reset | |
223 | */ | |
224 | static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) | |
225 | { | |
226 | writel(0, ioaddr + EMAC_RX_CTL1); | |
227 | writel(0, ioaddr + EMAC_TX_CTL1); | |
228 | writel(0, ioaddr + EMAC_RX_FRM_FLT); | |
229 | writel(0, ioaddr + EMAC_RX_DESC_LIST); | |
230 | writel(0, ioaddr + EMAC_TX_DESC_LIST); | |
231 | writel(0, ioaddr + EMAC_INT_EN); | |
232 | writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); | |
233 | return 0; | |
234 | } | |
235 | ||
236 | /* sun8i_dwmac_dma_init() - initialize the EMAC | |
237 | * Called from stmmac via stmmac_dma_ops->init | |
238 | */ | |
239 | static void sun8i_dwmac_dma_init(void __iomem *ioaddr, | |
240 | struct stmmac_dma_cfg *dma_cfg, | |
241 | u32 dma_tx, u32 dma_rx, int atds) | |
242 | { | |
243 | /* Write TX and RX descriptors address */ | |
244 | writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST); | |
245 | writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST); | |
246 | ||
247 | writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); | |
248 | writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); | |
249 | } | |
250 | ||
251 | /* sun8i_dwmac_dump_regs() - Dump EMAC address space | |
252 | * Called from stmmac_dma_ops->dump_regs | |
253 | * Used for ethtool | |
254 | */ | |
255 | static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) | |
256 | { | |
257 | int i; | |
258 | ||
259 | for (i = 0; i < 0xC8; i += 4) { | |
260 | if (i == 0x32 || i == 0x3C) | |
261 | continue; | |
262 | reg_space[i / 4] = readl(ioaddr + i); | |
263 | } | |
264 | } | |
265 | ||
266 | /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space | |
267 | * Called from stmmac_ops->dump_regs | |
268 | * Used for ethtool | |
269 | */ | |
270 | static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, | |
271 | u32 *reg_space) | |
272 | { | |
273 | int i; | |
274 | void __iomem *ioaddr = hw->pcsr; | |
275 | ||
276 | for (i = 0; i < 0xC8; i += 4) { | |
277 | if (i == 0x32 || i == 0x3C) | |
278 | continue; | |
279 | reg_space[i / 4] = readl(ioaddr + i); | |
280 | } | |
281 | } | |
282 | ||
283 | static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) | |
284 | { | |
285 | writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); | |
286 | } | |
287 | ||
288 | static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) | |
289 | { | |
290 | writel(0, ioaddr + EMAC_INT_EN); | |
291 | } | |
292 | ||
293 | static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) | |
294 | { | |
295 | u32 v; | |
296 | ||
297 | v = readl(ioaddr + EMAC_TX_CTL1); | |
298 | v |= EMAC_TX_DMA_START; | |
299 | v |= EMAC_TX_DMA_EN; | |
300 | writel(v, ioaddr + EMAC_TX_CTL1); | |
301 | } | |
302 | ||
303 | static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) | |
304 | { | |
305 | u32 v; | |
306 | ||
307 | v = readl(ioaddr + EMAC_TX_CTL1); | |
308 | v |= EMAC_TX_DMA_START; | |
309 | v |= EMAC_TX_DMA_EN; | |
310 | writel(v, ioaddr + EMAC_TX_CTL1); | |
311 | } | |
312 | ||
313 | static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) | |
314 | { | |
315 | u32 v; | |
316 | ||
317 | v = readl(ioaddr + EMAC_TX_CTL1); | |
318 | v &= ~EMAC_TX_DMA_EN; | |
319 | writel(v, ioaddr + EMAC_TX_CTL1); | |
320 | } | |
321 | ||
322 | static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) | |
323 | { | |
324 | u32 v; | |
325 | ||
326 | v = readl(ioaddr + EMAC_RX_CTL1); | |
327 | v |= EMAC_RX_DMA_START; | |
328 | v |= EMAC_RX_DMA_EN; | |
329 | writel(v, ioaddr + EMAC_RX_CTL1); | |
330 | } | |
331 | ||
332 | static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) | |
333 | { | |
334 | u32 v; | |
335 | ||
336 | v = readl(ioaddr + EMAC_RX_CTL1); | |
337 | v &= ~EMAC_RX_DMA_EN; | |
338 | writel(v, ioaddr + EMAC_RX_CTL1); | |
339 | } | |
340 | ||
341 | static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, | |
342 | struct stmmac_extra_stats *x, u32 chan) | |
343 | { | |
344 | u32 v; | |
345 | int ret = 0; | |
346 | ||
347 | v = readl(ioaddr + EMAC_INT_STA); | |
348 | ||
349 | if (v & EMAC_TX_INT) { | |
350 | ret |= handle_tx; | |
351 | x->tx_normal_irq_n++; | |
352 | } | |
353 | ||
354 | if (v & EMAC_TX_DMA_STOP_INT) | |
355 | x->tx_process_stopped_irq++; | |
356 | ||
357 | if (v & EMAC_TX_BUF_UA_INT) | |
358 | x->tx_process_stopped_irq++; | |
359 | ||
360 | if (v & EMAC_TX_TIMEOUT_INT) | |
361 | ret |= tx_hard_error; | |
362 | ||
363 | if (v & EMAC_TX_UNDERFLOW_INT) { | |
364 | ret |= tx_hard_error; | |
365 | x->tx_undeflow_irq++; | |
366 | } | |
367 | ||
368 | if (v & EMAC_TX_EARLY_INT) | |
369 | x->tx_early_irq++; | |
370 | ||
371 | if (v & EMAC_RX_INT) { | |
372 | ret |= handle_rx; | |
373 | x->rx_normal_irq_n++; | |
374 | } | |
375 | ||
376 | if (v & EMAC_RX_BUF_UA_INT) | |
377 | x->rx_buf_unav_irq++; | |
378 | ||
379 | if (v & EMAC_RX_DMA_STOP_INT) | |
380 | x->rx_process_stopped_irq++; | |
381 | ||
382 | if (v & EMAC_RX_TIMEOUT_INT) | |
383 | ret |= tx_hard_error; | |
384 | ||
385 | if (v & EMAC_RX_OVERFLOW_INT) { | |
386 | ret |= tx_hard_error; | |
387 | x->rx_overflow_irq++; | |
388 | } | |
389 | ||
390 | if (v & EMAC_RX_EARLY_INT) | |
391 | x->rx_early_irq++; | |
392 | ||
393 | if (v & EMAC_RGMII_STA_INT) | |
394 | x->irq_rgmii_n++; | |
395 | ||
396 | writel(v, ioaddr + EMAC_INT_STA); | |
397 | ||
398 | return ret; | |
399 | } | |
400 | ||
401 | static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode, | |
402 | int rxmode, int rxfifosz) | |
403 | { | |
404 | u32 v; | |
405 | ||
406 | v = readl(ioaddr + EMAC_TX_CTL1); | |
407 | if (txmode == SF_DMA_MODE) { | |
408 | v |= EMAC_TX_MD; | |
409 | /* Undocumented bit (called TX_NEXT_FRM in BSP), the original | |
410 | * comment is | |
411 | * "Operating on second frame increase the performance | |
412 | * especially when transmit store-and-forward is used." | |
413 | */ | |
414 | v |= EMAC_TX_NEXT_FRM; | |
415 | } else { | |
416 | v &= ~EMAC_TX_MD; | |
417 | v &= ~EMAC_TX_TH_MASK; | |
418 | if (txmode < 64) | |
419 | v |= EMAC_TX_TH_64; | |
420 | else if (txmode < 128) | |
421 | v |= EMAC_TX_TH_128; | |
422 | else if (txmode < 192) | |
423 | v |= EMAC_TX_TH_192; | |
424 | else if (txmode < 256) | |
425 | v |= EMAC_TX_TH_256; | |
426 | } | |
427 | writel(v, ioaddr + EMAC_TX_CTL1); | |
428 | ||
429 | v = readl(ioaddr + EMAC_RX_CTL1); | |
430 | if (rxmode == SF_DMA_MODE) { | |
431 | v |= EMAC_RX_MD; | |
432 | } else { | |
433 | v &= ~EMAC_RX_MD; | |
434 | v &= ~EMAC_RX_TH_MASK; | |
435 | if (rxmode < 32) | |
436 | v |= EMAC_RX_TH_32; | |
437 | else if (rxmode < 64) | |
438 | v |= EMAC_RX_TH_64; | |
439 | else if (rxmode < 96) | |
440 | v |= EMAC_RX_TH_96; | |
441 | else if (rxmode < 128) | |
442 | v |= EMAC_RX_TH_128; | |
443 | } | |
444 | writel(v, ioaddr + EMAC_RX_CTL1); | |
445 | } | |
446 | ||
447 | static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { | |
448 | .reset = sun8i_dwmac_dma_reset, | |
449 | .init = sun8i_dwmac_dma_init, | |
450 | .dump_regs = sun8i_dwmac_dump_regs, | |
451 | .dma_mode = sun8i_dwmac_dma_operation_mode, | |
452 | .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, | |
453 | .enable_dma_irq = sun8i_dwmac_enable_dma_irq, | |
454 | .disable_dma_irq = sun8i_dwmac_disable_dma_irq, | |
455 | .start_tx = sun8i_dwmac_dma_start_tx, | |
456 | .stop_tx = sun8i_dwmac_dma_stop_tx, | |
457 | .start_rx = sun8i_dwmac_dma_start_rx, | |
458 | .stop_rx = sun8i_dwmac_dma_stop_rx, | |
459 | .dma_interrupt = sun8i_dwmac_dma_interrupt, | |
460 | }; | |
461 | ||
462 | static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) | |
463 | { | |
464 | struct sunxi_priv_data *gmac = priv; | |
465 | int ret; | |
466 | ||
467 | if (gmac->regulator) { | |
468 | ret = regulator_enable(gmac->regulator); | |
469 | if (ret) { | |
470 | dev_err(&pdev->dev, "Fail to enable regulator\n"); | |
471 | return ret; | |
472 | } | |
473 | } | |
474 | ||
475 | ret = clk_prepare_enable(gmac->tx_clk); | |
476 | if (ret) { | |
477 | if (gmac->regulator) | |
478 | regulator_disable(gmac->regulator); | |
479 | dev_err(&pdev->dev, "Could not enable AHB clock\n"); | |
480 | return ret; | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu) | |
487 | { | |
488 | void __iomem *ioaddr = hw->pcsr; | |
489 | u32 v; | |
490 | ||
491 | v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ | |
492 | writel(v, ioaddr + EMAC_BASIC_CTL1); | |
493 | } | |
494 | ||
495 | static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) | |
496 | { | |
497 | u32 t, r; | |
498 | ||
499 | t = readl(ioaddr + EMAC_TX_CTL0); | |
500 | r = readl(ioaddr + EMAC_RX_CTL0); | |
501 | if (enable) { | |
502 | t |= EMAC_TX_TRANSMITTER_EN; | |
503 | r |= EMAC_RX_RECEIVER_EN; | |
504 | } else { | |
505 | t &= ~EMAC_TX_TRANSMITTER_EN; | |
506 | r &= ~EMAC_RX_RECEIVER_EN; | |
507 | } | |
508 | writel(t, ioaddr + EMAC_TX_CTL0); | |
509 | writel(r, ioaddr + EMAC_RX_CTL0); | |
510 | } | |
511 | ||
512 | /* Set MAC address at slot reg_n | |
513 | * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST | |
514 | * If addr is NULL, clear the slot | |
515 | */ | |
516 | static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, | |
517 | unsigned char *addr, | |
518 | unsigned int reg_n) | |
519 | { | |
520 | void __iomem *ioaddr = hw->pcsr; | |
521 | u32 v; | |
522 | ||
523 | if (!addr) { | |
524 | writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); | |
525 | return; | |
526 | } | |
527 | ||
528 | stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), | |
529 | EMAC_MACADDR_LO(reg_n)); | |
530 | if (reg_n > 0) { | |
531 | v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); | |
532 | v |= MAC_ADDR_TYPE_DST; | |
533 | writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); | |
534 | } | |
535 | } | |
536 | ||
537 | static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, | |
538 | unsigned char *addr, | |
539 | unsigned int reg_n) | |
540 | { | |
541 | void __iomem *ioaddr = hw->pcsr; | |
542 | ||
543 | stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), | |
544 | EMAC_MACADDR_LO(reg_n)); | |
545 | } | |
546 | ||
547 | /* caution this function must return non 0 to work */ | |
548 | static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) | |
549 | { | |
550 | void __iomem *ioaddr = hw->pcsr; | |
551 | u32 v; | |
552 | ||
553 | v = readl(ioaddr + EMAC_RX_CTL0); | |
554 | v |= EMAC_RX_DO_CRC; | |
555 | writel(v, ioaddr + EMAC_RX_CTL0); | |
556 | ||
557 | return 1; | |
558 | } | |
559 | ||
560 | static void sun8i_dwmac_set_filter(struct mac_device_info *hw, | |
561 | struct net_device *dev) | |
562 | { | |
563 | void __iomem *ioaddr = hw->pcsr; | |
564 | u32 v; | |
565 | int i = 1; | |
566 | struct netdev_hw_addr *ha; | |
567 | int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; | |
568 | ||
569 | v = EMAC_FRM_FLT_CTL; | |
570 | ||
571 | if (dev->flags & IFF_PROMISC) { | |
572 | v = EMAC_FRM_FLT_RXALL; | |
573 | } else if (dev->flags & IFF_ALLMULTI) { | |
574 | v |= EMAC_FRM_FLT_MULTICAST; | |
575 | } else if (macaddrs <= hw->unicast_filter_entries) { | |
576 | if (!netdev_mc_empty(dev)) { | |
577 | netdev_for_each_mc_addr(ha, dev) { | |
578 | sun8i_dwmac_set_umac_addr(hw, ha->addr, i); | |
579 | i++; | |
580 | } | |
581 | } | |
582 | if (!netdev_uc_empty(dev)) { | |
583 | netdev_for_each_uc_addr(ha, dev) { | |
584 | sun8i_dwmac_set_umac_addr(hw, ha->addr, i); | |
585 | i++; | |
586 | } | |
587 | } | |
588 | } else { | |
589 | netdev_info(dev, "Too many address, switching to promiscuous\n"); | |
590 | v = EMAC_FRM_FLT_RXALL; | |
591 | } | |
592 | ||
593 | /* Disable unused address filter slots */ | |
594 | while (i < hw->unicast_filter_entries) | |
595 | sun8i_dwmac_set_umac_addr(hw, NULL, i++); | |
596 | ||
597 | writel(v, ioaddr + EMAC_RX_FRM_FLT); | |
598 | } | |
599 | ||
600 | static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, | |
601 | unsigned int duplex, unsigned int fc, | |
602 | unsigned int pause_time, u32 tx_cnt) | |
603 | { | |
604 | void __iomem *ioaddr = hw->pcsr; | |
605 | u32 v; | |
606 | ||
607 | v = readl(ioaddr + EMAC_RX_CTL0); | |
608 | if (fc == FLOW_AUTO) | |
609 | v |= EMAC_RX_FLOW_CTL_EN; | |
610 | else | |
611 | v &= ~EMAC_RX_FLOW_CTL_EN; | |
612 | writel(v, ioaddr + EMAC_RX_CTL0); | |
613 | ||
614 | v = readl(ioaddr + EMAC_TX_FLOW_CTL); | |
615 | if (fc == FLOW_AUTO) | |
616 | v |= EMAC_TX_FLOW_CTL_EN; | |
617 | else | |
618 | v &= ~EMAC_TX_FLOW_CTL_EN; | |
619 | writel(v, ioaddr + EMAC_TX_FLOW_CTL); | |
620 | } | |
621 | ||
622 | static int sun8i_dwmac_reset(struct stmmac_priv *priv) | |
623 | { | |
624 | u32 v; | |
625 | int err; | |
626 | ||
627 | v = readl(priv->ioaddr + EMAC_BASIC_CTL1); | |
628 | writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); | |
629 | ||
630 | /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) | |
631 | * need more if no cable plugged. 100ms seems OK | |
632 | */ | |
633 | err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, | |
634 | !(v & 0x01), 100, 100000); | |
635 | ||
636 | if (err) { | |
637 | dev_err(priv->device, "EMAC reset timeout\n"); | |
638 | return -EFAULT; | |
639 | } | |
640 | return 0; | |
641 | } | |
642 | ||
634db83b CL |
643 | /* Search in mdio-mux node for internal PHY node and get its clk/reset */ |
644 | static int get_ephy_nodes(struct stmmac_priv *priv) | |
645 | { | |
646 | struct sunxi_priv_data *gmac = priv->plat->bsp_priv; | |
647 | struct device_node *mdio_mux, *iphynode; | |
648 | struct device_node *mdio_internal; | |
649 | int ret; | |
650 | ||
651 | mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); | |
652 | if (!mdio_mux) { | |
653 | dev_err(priv->device, "Cannot get mdio-mux node\n"); | |
654 | return -ENODEV; | |
655 | } | |
656 | ||
657 | mdio_internal = of_find_compatible_node(mdio_mux, NULL, | |
658 | "allwinner,sun8i-h3-mdio-internal"); | |
659 | if (!mdio_internal) { | |
660 | dev_err(priv->device, "Cannot get internal_mdio node\n"); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | /* Seek for internal PHY */ | |
665 | for_each_child_of_node(mdio_internal, iphynode) { | |
666 | gmac->ephy_clk = of_clk_get(iphynode, 0); | |
667 | if (IS_ERR(gmac->ephy_clk)) | |
668 | continue; | |
669 | gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); | |
670 | if (IS_ERR(gmac->rst_ephy)) { | |
671 | ret = PTR_ERR(gmac->rst_ephy); | |
672 | if (ret == -EPROBE_DEFER) | |
673 | return ret; | |
674 | continue; | |
675 | } | |
676 | dev_info(priv->device, "Found internal PHY node\n"); | |
677 | return 0; | |
678 | } | |
679 | return -ENODEV; | |
680 | } | |
681 | ||
682 | static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) | |
683 | { | |
684 | struct sunxi_priv_data *gmac = priv->plat->bsp_priv; | |
685 | int ret; | |
686 | ||
687 | if (gmac->internal_phy_powered) { | |
688 | dev_warn(priv->device, "Internal PHY already powered\n"); | |
689 | return 0; | |
690 | } | |
691 | ||
692 | dev_info(priv->device, "Powering internal PHY\n"); | |
693 | ret = clk_prepare_enable(gmac->ephy_clk); | |
694 | if (ret) { | |
695 | dev_err(priv->device, "Cannot enable internal PHY\n"); | |
696 | return ret; | |
697 | } | |
698 | ||
699 | /* Make sure the EPHY is properly reseted, as U-Boot may leave | |
700 | * it at deasserted state, and thus it may fail to reset EMAC. | |
701 | */ | |
702 | reset_control_assert(gmac->rst_ephy); | |
703 | ||
704 | ret = reset_control_deassert(gmac->rst_ephy); | |
705 | if (ret) { | |
706 | dev_err(priv->device, "Cannot deassert internal phy\n"); | |
707 | clk_disable_unprepare(gmac->ephy_clk); | |
708 | return ret; | |
709 | } | |
710 | ||
711 | gmac->internal_phy_powered = true; | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) | |
717 | { | |
718 | if (!gmac->internal_phy_powered) | |
719 | return 0; | |
720 | ||
721 | clk_disable_unprepare(gmac->ephy_clk); | |
722 | reset_control_assert(gmac->rst_ephy); | |
723 | gmac->internal_phy_powered = false; | |
724 | return 0; | |
725 | } | |
726 | ||
727 | /* MDIO multiplexing switch function | |
728 | * This function is called by the mdio-mux layer when it thinks the mdio bus | |
729 | * multiplexer needs to switch. | |
730 | * 'current_child' is the current value of the mux register | |
731 | * 'desired_child' is the value of the 'reg' property of the target child MDIO | |
732 | * node. | |
733 | * The first time this function is called, current_child == -1. | |
734 | * If current_child == desired_child, then the mux is already set to the | |
735 | * correct bus. | |
736 | */ | |
737 | static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, | |
738 | void *data) | |
739 | { | |
740 | struct stmmac_priv *priv = data; | |
741 | struct sunxi_priv_data *gmac = priv->plat->bsp_priv; | |
742 | u32 reg, val; | |
743 | int ret = 0; | |
744 | bool need_power_ephy = false; | |
745 | ||
746 | if (current_child ^ desired_child) { | |
747 | regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); | |
748 | switch (desired_child) { | |
749 | case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: | |
750 | dev_info(priv->device, "Switch mux to internal PHY"); | |
751 | val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; | |
752 | ||
753 | need_power_ephy = true; | |
754 | break; | |
755 | case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: | |
756 | dev_info(priv->device, "Switch mux to external PHY"); | |
757 | val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; | |
758 | need_power_ephy = false; | |
759 | break; | |
760 | default: | |
761 | dev_err(priv->device, "Invalid child ID %x\n", | |
762 | desired_child); | |
763 | return -EINVAL; | |
764 | } | |
765 | regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); | |
766 | if (need_power_ephy) { | |
767 | ret = sun8i_dwmac_power_internal_phy(priv); | |
768 | if (ret) | |
769 | return ret; | |
770 | } else { | |
771 | sun8i_dwmac_unpower_internal_phy(gmac); | |
772 | } | |
773 | /* After changing syscon value, the MAC need reset or it will | |
774 | * use the last value (and so the last PHY set). | |
775 | */ | |
776 | ret = sun8i_dwmac_reset(priv); | |
777 | } | |
778 | return ret; | |
779 | } | |
780 | ||
781 | static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) | |
782 | { | |
783 | int ret; | |
784 | struct device_node *mdio_mux; | |
785 | struct sunxi_priv_data *gmac = priv->plat->bsp_priv; | |
786 | ||
787 | mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); | |
788 | if (!mdio_mux) | |
789 | return -ENODEV; | |
790 | ||
791 | ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, | |
792 | &gmac->mux_handle, priv, priv->mii); | |
793 | return ret; | |
794 | } | |
795 | ||
9f93ac8d LC |
796 | static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) |
797 | { | |
798 | struct sunxi_priv_data *gmac = priv->plat->bsp_priv; | |
799 | struct device_node *node = priv->device->of_node; | |
d93b07f8 | 800 | int ret; |
9f93ac8d LC |
801 | u32 reg, val; |
802 | ||
803 | regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val); | |
804 | reg = gmac->variant->default_syscon_value; | |
805 | if (reg != val) | |
806 | dev_warn(priv->device, | |
807 | "Current syscon value is not the default %x (expect %x)\n", | |
808 | val, reg); | |
809 | ||
634db83b | 810 | if (gmac->variant->soc_has_internal_phy) { |
1c08ac0c | 811 | if (of_property_read_bool(node, "allwinner,leds-active-low")) |
634db83b CL |
812 | reg |= H3_EPHY_LED_POL; |
813 | else | |
814 | reg &= ~H3_EPHY_LED_POL; | |
815 | ||
816 | /* Force EPHY xtal frequency to 24MHz. */ | |
817 | reg |= H3_EPHY_CLK_SEL; | |
818 | ||
819 | ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); | |
820 | if (ret < 0) { | |
821 | dev_err(priv->device, "Could not parse MDIO addr\n"); | |
822 | return ret; | |
9f93ac8d | 823 | } |
634db83b CL |
824 | /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY |
825 | * address. No need to mask it again. | |
826 | */ | |
827 | reg |= 1 << H3_EPHY_ADDR_SHIFT; | |
9f93ac8d LC |
828 | } |
829 | ||
830 | if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { | |
831 | if (val % 100) { | |
832 | dev_err(priv->device, "tx-delay must be a multiple of 100\n"); | |
833 | return -EINVAL; | |
834 | } | |
835 | val /= 100; | |
836 | dev_dbg(priv->device, "set tx-delay to %x\n", val); | |
837 | if (val <= SYSCON_ETXDC_MASK) { | |
838 | reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT); | |
839 | reg |= (val << SYSCON_ETXDC_SHIFT); | |
840 | } else { | |
841 | dev_err(priv->device, "Invalid TX clock delay: %d\n", | |
842 | val); | |
843 | return -EINVAL; | |
844 | } | |
845 | } | |
846 | ||
847 | if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { | |
848 | if (val % 100) { | |
849 | dev_err(priv->device, "rx-delay must be a multiple of 100\n"); | |
850 | return -EINVAL; | |
851 | } | |
852 | val /= 100; | |
853 | dev_dbg(priv->device, "set rx-delay to %x\n", val); | |
854 | if (val <= SYSCON_ERXDC_MASK) { | |
855 | reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT); | |
856 | reg |= (val << SYSCON_ERXDC_SHIFT); | |
857 | } else { | |
858 | dev_err(priv->device, "Invalid RX clock delay: %d\n", | |
859 | val); | |
860 | return -EINVAL; | |
861 | } | |
862 | } | |
863 | ||
864 | /* Clear interface mode bits */ | |
865 | reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); | |
866 | if (gmac->variant->support_rmii) | |
867 | reg &= ~SYSCON_RMII_EN; | |
868 | ||
d93b07f8 | 869 | switch (priv->plat->interface) { |
9f93ac8d LC |
870 | case PHY_INTERFACE_MODE_MII: |
871 | /* default */ | |
872 | break; | |
873 | case PHY_INTERFACE_MODE_RGMII: | |
874 | reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; | |
875 | break; | |
876 | case PHY_INTERFACE_MODE_RMII: | |
877 | reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; | |
878 | break; | |
879 | default: | |
880 | dev_err(priv->device, "Unsupported interface mode: %s", | |
881 | phy_modes(priv->plat->interface)); | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
885 | regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) | |
891 | { | |
892 | u32 reg = gmac->variant->default_syscon_value; | |
893 | ||
894 | regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); | |
895 | } | |
896 | ||
634db83b | 897 | static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) |
9f93ac8d | 898 | { |
634db83b | 899 | struct sunxi_priv_data *gmac = priv; |
2f878491 | 900 | |
634db83b CL |
901 | if (gmac->variant->soc_has_internal_phy) { |
902 | /* sun8i_dwmac_exit could be called with mdiomux uninit */ | |
903 | if (gmac->mux_handle) | |
904 | mdio_mux_uninit(gmac->mux_handle); | |
905 | if (gmac->internal_phy_powered) | |
906 | sun8i_dwmac_unpower_internal_phy(gmac); | |
9f93ac8d LC |
907 | } |
908 | ||
9f93ac8d | 909 | sun8i_dwmac_unset_syscon(gmac); |
9f93ac8d | 910 | |
634db83b | 911 | reset_control_put(gmac->rst_ephy); |
9f93ac8d LC |
912 | |
913 | clk_disable_unprepare(gmac->tx_clk); | |
914 | ||
915 | if (gmac->regulator) | |
916 | regulator_disable(gmac->regulator); | |
917 | } | |
918 | ||
919 | static const struct stmmac_ops sun8i_dwmac_ops = { | |
920 | .core_init = sun8i_dwmac_core_init, | |
921 | .set_mac = sun8i_dwmac_set_mac, | |
922 | .dump_regs = sun8i_dwmac_dump_mac_regs, | |
923 | .rx_ipc = sun8i_dwmac_rx_ipc_enable, | |
924 | .set_filter = sun8i_dwmac_set_filter, | |
925 | .flow_ctrl = sun8i_dwmac_flow_ctrl, | |
926 | .set_umac_addr = sun8i_dwmac_set_umac_addr, | |
927 | .get_umac_addr = sun8i_dwmac_get_umac_addr, | |
928 | }; | |
929 | ||
930 | static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) | |
931 | { | |
932 | struct mac_device_info *mac; | |
933 | struct stmmac_priv *priv = ppriv; | |
934 | int ret; | |
935 | ||
936 | mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); | |
937 | if (!mac) | |
938 | return NULL; | |
939 | ||
634db83b | 940 | ret = sun8i_dwmac_set_syscon(priv); |
9f93ac8d LC |
941 | if (ret) |
942 | return NULL; | |
943 | ||
944 | mac->pcsr = priv->ioaddr; | |
945 | mac->mac = &sun8i_dwmac_ops; | |
946 | mac->dma = &sun8i_dwmac_dma_ops; | |
947 | ||
948 | /* The loopback bit seems to be re-set when link change | |
949 | * Simply mask it each time | |
950 | * Speed 10/100/1000 are set in BIT(2)/BIT(3) | |
951 | */ | |
952 | mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; | |
953 | mac->link.speed10 = EMAC_SPEED_10; | |
954 | mac->link.speed100 = EMAC_SPEED_100; | |
955 | mac->link.speed1000 = EMAC_SPEED_1000; | |
956 | mac->link.duplex = EMAC_DUPLEX_FULL; | |
957 | mac->mii.addr = EMAC_MDIO_CMD; | |
958 | mac->mii.data = EMAC_MDIO_DATA; | |
959 | mac->mii.reg_shift = 4; | |
960 | mac->mii.reg_mask = GENMASK(8, 4); | |
961 | mac->mii.addr_shift = 12; | |
962 | mac->mii.addr_mask = GENMASK(16, 12); | |
963 | mac->mii.clk_csr_shift = 20; | |
964 | mac->mii.clk_csr_mask = GENMASK(22, 20); | |
965 | mac->unicast_filter_entries = 8; | |
966 | ||
967 | /* Synopsys Id is not available */ | |
968 | priv->synopsys_id = 0; | |
969 | ||
970 | return mac; | |
971 | } | |
972 | ||
973 | static int sun8i_dwmac_probe(struct platform_device *pdev) | |
974 | { | |
975 | struct plat_stmmacenet_data *plat_dat; | |
976 | struct stmmac_resources stmmac_res; | |
977 | struct sunxi_priv_data *gmac; | |
978 | struct device *dev = &pdev->dev; | |
979 | int ret; | |
634db83b CL |
980 | struct stmmac_priv *priv; |
981 | struct net_device *ndev; | |
9f93ac8d LC |
982 | |
983 | ret = stmmac_get_platform_resources(pdev, &stmmac_res); | |
984 | if (ret) | |
985 | return ret; | |
986 | ||
987 | plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); | |
988 | if (IS_ERR(plat_dat)) | |
989 | return PTR_ERR(plat_dat); | |
990 | ||
991 | gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); | |
992 | if (!gmac) | |
993 | return -ENOMEM; | |
994 | ||
995 | gmac->variant = of_device_get_match_data(&pdev->dev); | |
996 | if (!gmac->variant) { | |
997 | dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
1001 | gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); | |
1002 | if (IS_ERR(gmac->tx_clk)) { | |
1003 | dev_err(dev, "Could not get TX clock\n"); | |
1004 | return PTR_ERR(gmac->tx_clk); | |
1005 | } | |
1006 | ||
1007 | /* Optional regulator for PHY */ | |
1008 | gmac->regulator = devm_regulator_get_optional(dev, "phy"); | |
1009 | if (IS_ERR(gmac->regulator)) { | |
1010 | if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) | |
1011 | return -EPROBE_DEFER; | |
1012 | dev_info(dev, "No regulator found\n"); | |
1013 | gmac->regulator = NULL; | |
1014 | } | |
1015 | ||
1016 | gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
1017 | "syscon"); | |
1018 | if (IS_ERR(gmac->regmap)) { | |
1019 | ret = PTR_ERR(gmac->regmap); | |
1020 | dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); | |
1021 | return ret; | |
1022 | } | |
1023 | ||
1024 | plat_dat->interface = of_get_phy_mode(dev->of_node); | |
9f93ac8d LC |
1025 | |
1026 | /* platform data specifying hardware features and callbacks. | |
1027 | * hardware features were copied from Allwinner drivers. | |
1028 | */ | |
1029 | plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; | |
1030 | plat_dat->tx_coe = 1; | |
1031 | plat_dat->has_sun8i = true; | |
1032 | plat_dat->bsp_priv = gmac; | |
1033 | plat_dat->init = sun8i_dwmac_init; | |
1034 | plat_dat->exit = sun8i_dwmac_exit; | |
1035 | plat_dat->setup = sun8i_dwmac_setup; | |
1036 | ||
1037 | ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); | |
1038 | if (ret) | |
1039 | return ret; | |
1040 | ||
1041 | ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); | |
1042 | if (ret) | |
634db83b CL |
1043 | goto dwmac_exit; |
1044 | ||
1045 | ndev = dev_get_drvdata(&pdev->dev); | |
1046 | priv = netdev_priv(ndev); | |
1047 | /* The mux must be registered after parent MDIO | |
1048 | * so after stmmac_dvr_probe() | |
1049 | */ | |
1050 | if (gmac->variant->soc_has_internal_phy) { | |
1051 | ret = get_ephy_nodes(priv); | |
1052 | if (ret) | |
1053 | goto dwmac_exit; | |
1054 | ret = sun8i_dwmac_register_mdio_mux(priv); | |
1055 | if (ret) { | |
1056 | dev_err(&pdev->dev, "Failed to register mux\n"); | |
1057 | goto dwmac_mux; | |
1058 | } | |
1059 | } else { | |
1060 | ret = sun8i_dwmac_reset(priv); | |
1061 | if (ret) | |
1062 | goto dwmac_exit; | |
1063 | } | |
9f93ac8d LC |
1064 | |
1065 | return ret; | |
634db83b CL |
1066 | dwmac_mux: |
1067 | sun8i_dwmac_unset_syscon(gmac); | |
1068 | dwmac_exit: | |
1069 | sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); | |
1070 | return ret; | |
9f93ac8d LC |
1071 | } |
1072 | ||
1073 | static const struct of_device_id sun8i_dwmac_match[] = { | |
a8ff8ccb CL |
1074 | { .compatible = "allwinner,sun8i-h3-emac", |
1075 | .data = &emac_variant_h3 }, | |
1076 | { .compatible = "allwinner,sun8i-v3s-emac", | |
1077 | .data = &emac_variant_v3s }, | |
1078 | { .compatible = "allwinner,sun8i-a83t-emac", | |
1079 | .data = &emac_variant_a83t }, | |
1080 | { .compatible = "allwinner,sun50i-a64-emac", | |
1081 | .data = &emac_variant_a64 }, | |
9f93ac8d LC |
1082 | { } |
1083 | }; | |
1084 | MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); | |
1085 | ||
1086 | static struct platform_driver sun8i_dwmac_driver = { | |
1087 | .probe = sun8i_dwmac_probe, | |
1088 | .remove = stmmac_pltfr_remove, | |
1089 | .driver = { | |
1090 | .name = "dwmac-sun8i", | |
1091 | .pm = &stmmac_pltfr_pm_ops, | |
1092 | .of_match_table = sun8i_dwmac_match, | |
1093 | }, | |
1094 | }; | |
1095 | module_platform_driver(sun8i_dwmac_driver); | |
1096 | ||
1097 | MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); | |
1098 | MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); | |
1099 | MODULE_LICENSE("GPL"); |