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Merge tag 'mlx5-updates-2017-06-27' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-sun8i.c
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9f93ac8d
LC		 1/*
2 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
3 *
4 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/mfd/syscon.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/of_mdio.h>
24#include <linux/of_net.h>
25#include <linux/phy.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include <linux/regmap.h>
29#include <linux/stmmac.h>
30
31#include "stmmac.h"
32#include "stmmac_platform.h"
33
34/* General notes on dwmac-sun8i:
35 * Locking: no locking is necessary in this file because all necessary locking
36 * is done in the "stmmac files"
37 */
38
39/* struct emac_variant - Descrive dwmac-sun8i hardware variant
40 * @default_syscon_value: The default value of the EMAC register in syscon
41 * This value is used for disabling properly EMAC
42 * and used as a good starting value in case of the
43 * boot process(uboot) leave some stuff.
44 * @internal_phy: Does the MAC embed an internal PHY
45 * @support_mii: Does the MAC handle MII
46 * @support_rmii: Does the MAC handle RMII
47 * @support_rgmii: Does the MAC handle RGMII
48 */
49struct emac_variant {
50 u32 default_syscon_value;
51 int internal_phy;
52 bool support_mii;
53 bool support_rmii;
54 bool support_rgmii;
55};
56
57/* struct sunxi_priv_data - hold all sunxi private data
58 * @tx_clk: reference to MAC TX clock
59 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
60 * @regulator: reference to the optional regulator
61 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
62 * @variant: reference to the current board variant
63 * @regmap: regmap for using the syscon
64 * @use_internal_phy: Does the current PHY choice imply using the internal PHY
65 */
66struct sunxi_priv_data {
67 struct clk *tx_clk;
68 struct clk *ephy_clk;
69 struct regulator *regulator;
70 struct reset_control *rst_ephy;
71 const struct emac_variant *variant;
72 struct regmap *regmap;
73 bool use_internal_phy;
74};
75
76static const struct emac_variant emac_variant_h3 = {
77 .default_syscon_value = 0x58000,
78 .internal_phy = PHY_INTERFACE_MODE_MII,
79 .support_mii = true,
80 .support_rmii = true,
81 .support_rgmii = true
82};
83
57fde47d
IZ		 84static const struct emac_variant emac_variant_v3s = {
85 .default_syscon_value = 0x38000,
86 .internal_phy = PHY_INTERFACE_MODE_MII,
87 .support_mii = true
88};
89
9f93ac8d
LC		 90static const struct emac_variant emac_variant_a83t = {
91 .default_syscon_value = 0,
92 .internal_phy = 0,
93 .support_mii = true,
94 .support_rgmii = true
95};
96
97static const struct emac_variant emac_variant_a64 = {
98 .default_syscon_value = 0,
99 .internal_phy = 0,
100 .support_mii = true,
101 .support_rmii = true,
102 .support_rgmii = true
103};
104
105#define EMAC_BASIC_CTL0 0x00
106#define EMAC_BASIC_CTL1 0x04
107#define EMAC_INT_STA 0x08
108#define EMAC_INT_EN 0x0C
109#define EMAC_TX_CTL0 0x10
110#define EMAC_TX_CTL1 0x14
111#define EMAC_TX_FLOW_CTL 0x1C
112#define EMAC_TX_DESC_LIST 0x20
113#define EMAC_RX_CTL0 0x24
114#define EMAC_RX_CTL1 0x28
115#define EMAC_RX_DESC_LIST 0x34
116#define EMAC_RX_FRM_FLT 0x38
117#define EMAC_MDIO_CMD 0x48
118#define EMAC_MDIO_DATA 0x4C
119#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
120#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
121#define EMAC_TX_DMA_STA 0xB0
122#define EMAC_TX_CUR_DESC 0xB4
123#define EMAC_TX_CUR_BUF 0xB8
124#define EMAC_RX_DMA_STA 0xC0
125#define EMAC_RX_CUR_DESC 0xC4
126#define EMAC_RX_CUR_BUF 0xC8
127
128/* Use in EMAC_BASIC_CTL0 */
129#define EMAC_DUPLEX_FULL BIT(0)
130#define EMAC_LOOPBACK BIT(1)
131#define EMAC_SPEED_1000 0
132#define EMAC_SPEED_100 (0x03 << 2)
133#define EMAC_SPEED_10 (0x02 << 2)
134
135/* Use in EMAC_BASIC_CTL1 */
136#define EMAC_BURSTLEN_SHIFT 24
137
138/* Used in EMAC_RX_FRM_FLT */
139#define EMAC_FRM_FLT_RXALL BIT(0)
140#define EMAC_FRM_FLT_CTL BIT(13)
141#define EMAC_FRM_FLT_MULTICAST BIT(16)
142
143/* Used in RX_CTL1*/
144#define EMAC_RX_MD BIT(1)
145#define EMAC_RX_TH_MASK GENMASK(4, 5)
146#define EMAC_RX_TH_32 0
147#define EMAC_RX_TH_64 (0x1 << 4)
148#define EMAC_RX_TH_96 (0x2 << 4)
149#define EMAC_RX_TH_128 (0x3 << 4)
150#define EMAC_RX_DMA_EN BIT(30)
151#define EMAC_RX_DMA_START BIT(31)
152
153/* Used in TX_CTL1*/
154#define EMAC_TX_MD BIT(1)
155#define EMAC_TX_NEXT_FRM BIT(2)
156#define EMAC_TX_TH_MASK GENMASK(8, 10)
157#define EMAC_TX_TH_64 0
158#define EMAC_TX_TH_128 (0x1 << 8)
159#define EMAC_TX_TH_192 (0x2 << 8)
160#define EMAC_TX_TH_256 (0x3 << 8)
161#define EMAC_TX_DMA_EN BIT(30)
162#define EMAC_TX_DMA_START BIT(31)
163
164/* Used in RX_CTL0 */
165#define EMAC_RX_RECEIVER_EN BIT(31)
166#define EMAC_RX_DO_CRC BIT(27)
167#define EMAC_RX_FLOW_CTL_EN BIT(16)
168
169/* Used in TX_CTL0 */
170#define EMAC_TX_TRANSMITTER_EN BIT(31)
171
172/* Used in EMAC_TX_FLOW_CTL */
173#define EMAC_TX_FLOW_CTL_EN BIT(0)
174
175/* Used in EMAC_INT_STA */
176#define EMAC_TX_INT BIT(0)
177#define EMAC_TX_DMA_STOP_INT BIT(1)
178#define EMAC_TX_BUF_UA_INT BIT(2)
179#define EMAC_TX_TIMEOUT_INT BIT(3)
180#define EMAC_TX_UNDERFLOW_INT BIT(4)
181#define EMAC_TX_EARLY_INT BIT(5)
182#define EMAC_RX_INT BIT(8)
183#define EMAC_RX_BUF_UA_INT BIT(9)
184#define EMAC_RX_DMA_STOP_INT BIT(10)
185#define EMAC_RX_TIMEOUT_INT BIT(11)
186#define EMAC_RX_OVERFLOW_INT BIT(12)
187#define EMAC_RX_EARLY_INT BIT(13)
188#define EMAC_RGMII_STA_INT BIT(16)
189
190#define MAC_ADDR_TYPE_DST BIT(31)
191
192/* H3 specific bits for EPHY */
193#define H3_EPHY_ADDR_SHIFT 20
1450ba8a 194#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
9f93ac8d
LC		 195#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
196#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
197#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
198
199/* H3/A64 specific bits */
200#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
201
202/* Generic system control EMAC_CLK bits */
203#define SYSCON_ETXDC_MASK GENMASK(2, 0)
204#define SYSCON_ETXDC_SHIFT 10
205#define SYSCON_ERXDC_MASK GENMASK(4, 0)
206#define SYSCON_ERXDC_SHIFT 5
207/* EMAC PHY Interface Type */
208#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
209#define SYSCON_ETCS_MASK GENMASK(1, 0)
210#define SYSCON_ETCS_MII 0x0
211#define SYSCON_ETCS_EXT_GMII 0x1
212#define SYSCON_ETCS_INT_GMII 0x2
213#define SYSCON_EMAC_REG 0x30
214
215/* sun8i_dwmac_dma_reset() - reset the EMAC
216 * Called from stmmac via stmmac_dma_ops->reset
217 */
218static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
219{
220 writel(0, ioaddr + EMAC_RX_CTL1);
221 writel(0, ioaddr + EMAC_TX_CTL1);
222 writel(0, ioaddr + EMAC_RX_FRM_FLT);
223 writel(0, ioaddr + EMAC_RX_DESC_LIST);
224 writel(0, ioaddr + EMAC_TX_DESC_LIST);
225 writel(0, ioaddr + EMAC_INT_EN);
226 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
227 return 0;
228}
229
230/* sun8i_dwmac_dma_init() - initialize the EMAC
231 * Called from stmmac via stmmac_dma_ops->init
232 */
233static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
234 struct stmmac_dma_cfg *dma_cfg,
235 u32 dma_tx, u32 dma_rx, int atds)
236{
237 /* Write TX and RX descriptors address */
238 writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
239 writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
240
241 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
242 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
243}
244
245/* sun8i_dwmac_dump_regs() - Dump EMAC address space
246 * Called from stmmac_dma_ops->dump_regs
247 * Used for ethtool
248 */
249static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
250{
251 int i;
252
253 for (i = 0; i < 0xC8; i += 4) {
254 if (i == 0x32 || i == 0x3C)
255 continue;
256 reg_space[i / 4] = readl(ioaddr + i);
257 }
258}
259
260/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
261 * Called from stmmac_ops->dump_regs
262 * Used for ethtool
263 */
264static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
265 u32 *reg_space)
266{
267 int i;
268 void __iomem *ioaddr = hw->pcsr;
269
270 for (i = 0; i < 0xC8; i += 4) {
271 if (i == 0x32 || i == 0x3C)
272 continue;
273 reg_space[i / 4] = readl(ioaddr + i);
274 }
275}
276
277static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
278{
279 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
280}
281
282static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
283{
284 writel(0, ioaddr + EMAC_INT_EN);
285}
286
287static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
288{
289 u32 v;
290
291 v = readl(ioaddr + EMAC_TX_CTL1);
292 v |= EMAC_TX_DMA_START;
293 v |= EMAC_TX_DMA_EN;
294 writel(v, ioaddr + EMAC_TX_CTL1);
295}
296
297static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
298{
299 u32 v;
300
301 v = readl(ioaddr + EMAC_TX_CTL1);
302 v |= EMAC_TX_DMA_START;
303 v |= EMAC_TX_DMA_EN;
304 writel(v, ioaddr + EMAC_TX_CTL1);
305}
306
307static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
308{
309 u32 v;
310
311 v = readl(ioaddr + EMAC_TX_CTL1);
312 v &= ~EMAC_TX_DMA_EN;
313 writel(v, ioaddr + EMAC_TX_CTL1);
314}
315
316static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
317{
318 u32 v;
319
320 v = readl(ioaddr + EMAC_RX_CTL1);
321 v |= EMAC_RX_DMA_START;
322 v |= EMAC_RX_DMA_EN;
323 writel(v, ioaddr + EMAC_RX_CTL1);
324}
325
326static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
327{
328 u32 v;
329
330 v = readl(ioaddr + EMAC_RX_CTL1);
331 v &= ~EMAC_RX_DMA_EN;
332 writel(v, ioaddr + EMAC_RX_CTL1);
333}
334
335static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
336 struct stmmac_extra_stats *x, u32 chan)
337{
338 u32 v;
339 int ret = 0;
340
341 v = readl(ioaddr + EMAC_INT_STA);
342
343 if (v & EMAC_TX_INT) {
344 ret |= handle_tx;
345 x->tx_normal_irq_n++;
346 }
347
348 if (v & EMAC_TX_DMA_STOP_INT)
349 x->tx_process_stopped_irq++;
350
351 if (v & EMAC_TX_BUF_UA_INT)
352 x->tx_process_stopped_irq++;
353
354 if (v & EMAC_TX_TIMEOUT_INT)
355 ret |= tx_hard_error;
356
357 if (v & EMAC_TX_UNDERFLOW_INT) {
358 ret |= tx_hard_error;
359 x->tx_undeflow_irq++;
360 }
361
362 if (v & EMAC_TX_EARLY_INT)
363 x->tx_early_irq++;
364
365 if (v & EMAC_RX_INT) {
366 ret |= handle_rx;
367 x->rx_normal_irq_n++;
368 }
369
370 if (v & EMAC_RX_BUF_UA_INT)
371 x->rx_buf_unav_irq++;
372
373 if (v & EMAC_RX_DMA_STOP_INT)
374 x->rx_process_stopped_irq++;
375
376 if (v & EMAC_RX_TIMEOUT_INT)
377 ret |= tx_hard_error;
378
379 if (v & EMAC_RX_OVERFLOW_INT) {
380 ret |= tx_hard_error;
381 x->rx_overflow_irq++;
382 }
383
384 if (v & EMAC_RX_EARLY_INT)
385 x->rx_early_irq++;
386
387 if (v & EMAC_RGMII_STA_INT)
388 x->irq_rgmii_n++;
389
390 writel(v, ioaddr + EMAC_INT_STA);
391
392 return ret;
393}
394
395static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
396 int rxmode, int rxfifosz)
397{
398 u32 v;
399
400 v = readl(ioaddr + EMAC_TX_CTL1);
401 if (txmode == SF_DMA_MODE) {
402 v |= EMAC_TX_MD;
403 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
404 * comment is
405 * "Operating on second frame increase the performance
406 * especially when transmit store-and-forward is used."
407 */
408 v |= EMAC_TX_NEXT_FRM;
409 } else {
410 v &= ~EMAC_TX_MD;
411 v &= ~EMAC_TX_TH_MASK;
412 if (txmode < 64)
413 v |= EMAC_TX_TH_64;
414 else if (txmode < 128)
415 v |= EMAC_TX_TH_128;
416 else if (txmode < 192)
417 v |= EMAC_TX_TH_192;
418 else if (txmode < 256)
419 v |= EMAC_TX_TH_256;
420 }
421 writel(v, ioaddr + EMAC_TX_CTL1);
422
423 v = readl(ioaddr + EMAC_RX_CTL1);
424 if (rxmode == SF_DMA_MODE) {
425 v |= EMAC_RX_MD;
426 } else {
427 v &= ~EMAC_RX_MD;
428 v &= ~EMAC_RX_TH_MASK;
429 if (rxmode < 32)
430 v |= EMAC_RX_TH_32;
431 else if (rxmode < 64)
432 v |= EMAC_RX_TH_64;
433 else if (rxmode < 96)
434 v |= EMAC_RX_TH_96;
435 else if (rxmode < 128)
436 v |= EMAC_RX_TH_128;
437 }
438 writel(v, ioaddr + EMAC_RX_CTL1);
439}
440
441static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
442 .reset = sun8i_dwmac_dma_reset,
443 .init = sun8i_dwmac_dma_init,
444 .dump_regs = sun8i_dwmac_dump_regs,
445 .dma_mode = sun8i_dwmac_dma_operation_mode,
446 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
447 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
448 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
449 .start_tx = sun8i_dwmac_dma_start_tx,
450 .stop_tx = sun8i_dwmac_dma_stop_tx,
451 .start_rx = sun8i_dwmac_dma_start_rx,
452 .stop_rx = sun8i_dwmac_dma_stop_rx,
453 .dma_interrupt = sun8i_dwmac_dma_interrupt,
454};
455
456static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
457{
458 struct sunxi_priv_data *gmac = priv;
459 int ret;
460
461 if (gmac->regulator) {
462 ret = regulator_enable(gmac->regulator);
463 if (ret) {
464 dev_err(&pdev->dev, "Fail to enable regulator\n");
465 return ret;
466 }
467 }
468
469 ret = clk_prepare_enable(gmac->tx_clk);
470 if (ret) {
471 if (gmac->regulator)
472 regulator_disable(gmac->regulator);
473 dev_err(&pdev->dev, "Could not enable AHB clock\n");
474 return ret;
475 }
476
477 return 0;
478}
479
480static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
481{
482 void __iomem *ioaddr = hw->pcsr;
483 u32 v;
484
485 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
486 writel(v, ioaddr + EMAC_BASIC_CTL1);
487}
488
489static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
490{
491 u32 t, r;
492
493 t = readl(ioaddr + EMAC_TX_CTL0);
494 r = readl(ioaddr + EMAC_RX_CTL0);
495 if (enable) {
496 t |= EMAC_TX_TRANSMITTER_EN;
497 r |= EMAC_RX_RECEIVER_EN;
498 } else {
499 t &= ~EMAC_TX_TRANSMITTER_EN;
500 r &= ~EMAC_RX_RECEIVER_EN;
501 }
502 writel(t, ioaddr + EMAC_TX_CTL0);
503 writel(r, ioaddr + EMAC_RX_CTL0);
504}
505
506/* Set MAC address at slot reg_n
507 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
508 * If addr is NULL, clear the slot
509 */
510static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
511 unsigned char *addr,
512 unsigned int reg_n)
513{
514 void __iomem *ioaddr = hw->pcsr;
515 u32 v;
516
517 if (!addr) {
518 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
519 return;
520 }
521
522 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
523 EMAC_MACADDR_LO(reg_n));
524 if (reg_n > 0) {
525 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
526 v |= MAC_ADDR_TYPE_DST;
527 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
528 }
529}
530
531static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
532 unsigned char *addr,
533 unsigned int reg_n)
534{
535 void __iomem *ioaddr = hw->pcsr;
536
537 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
538 EMAC_MACADDR_LO(reg_n));
539}
540
541/* caution this function must return non 0 to work */
542static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
543{
544 void __iomem *ioaddr = hw->pcsr;
545 u32 v;
546
547 v = readl(ioaddr + EMAC_RX_CTL0);
548 v |= EMAC_RX_DO_CRC;
549 writel(v, ioaddr + EMAC_RX_CTL0);
550
551 return 1;
552}
553
554static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
555 struct net_device *dev)
556{
557 void __iomem *ioaddr = hw->pcsr;
558 u32 v;
559 int i = 1;
560 struct netdev_hw_addr *ha;
561 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
562
563 v = EMAC_FRM_FLT_CTL;
564
565 if (dev->flags & IFF_PROMISC) {
566 v = EMAC_FRM_FLT_RXALL;
567 } else if (dev->flags & IFF_ALLMULTI) {
568 v |= EMAC_FRM_FLT_MULTICAST;
569 } else if (macaddrs <= hw->unicast_filter_entries) {
570 if (!netdev_mc_empty(dev)) {
571 netdev_for_each_mc_addr(ha, dev) {
572 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
573 i++;
574 }
575 }
576 if (!netdev_uc_empty(dev)) {
577 netdev_for_each_uc_addr(ha, dev) {
578 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
579 i++;
580 }
581 }
582 } else {
583 netdev_info(dev, "Too many address, switching to promiscuous\n");
584 v = EMAC_FRM_FLT_RXALL;
585 }
586
587 /* Disable unused address filter slots */
588 while (i < hw->unicast_filter_entries)
589 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
590
591 writel(v, ioaddr + EMAC_RX_FRM_FLT);
592}
593
594static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
595 unsigned int duplex, unsigned int fc,
596 unsigned int pause_time, u32 tx_cnt)
597{
598 void __iomem *ioaddr = hw->pcsr;
599 u32 v;
600
601 v = readl(ioaddr + EMAC_RX_CTL0);
602 if (fc == FLOW_AUTO)
603 v |= EMAC_RX_FLOW_CTL_EN;
604 else
605 v &= ~EMAC_RX_FLOW_CTL_EN;
606 writel(v, ioaddr + EMAC_RX_CTL0);
607
608 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
609 if (fc == FLOW_AUTO)
610 v |= EMAC_TX_FLOW_CTL_EN;
611 else
612 v &= ~EMAC_TX_FLOW_CTL_EN;
613 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
614}
615
616static int sun8i_dwmac_reset(struct stmmac_priv *priv)
617{
618 u32 v;
619 int err;
620
621 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
622 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
623
624 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
625 * need more if no cable plugged. 100ms seems OK
626 */
627 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
628 !(v & 0x01), 100, 100000);
629
630 if (err) {
631 dev_err(priv->device, "EMAC reset timeout\n");
632 return -EFAULT;
633 }
634 return 0;
635}
636
637static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
638{
639 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
640 struct device_node *node = priv->device->of_node;
1c2fa5f8 641 int ret, phy_interface;
9f93ac8d
LC		 642 u32 reg, val;
643
644 regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
645 reg = gmac->variant->default_syscon_value;
646 if (reg != val)
647 dev_warn(priv->device,
648 "Current syscon value is not the default %x (expect %x)\n",
649 val, reg);
650
651 if (gmac->variant->internal_phy) {
652 if (!gmac->use_internal_phy) {
653 /* switch to external PHY interface */
654 reg &= ~H3_EPHY_SELECT;
655 } else {
656 reg |= H3_EPHY_SELECT;
657 reg &= ~H3_EPHY_SHUTDOWN;
658 dev_dbg(priv->device, "Select internal_phy %x\n", reg);
659
660 if (of_property_read_bool(priv->plat->phy_node,
661 "allwinner,leds-active-low"))
662 reg |= H3_EPHY_LED_POL;
663 else
664 reg &= ~H3_EPHY_LED_POL;
665
1450ba8a
IZ		 666 /* Force EPHY xtal frequency to 24MHz. */
667 reg |= H3_EPHY_CLK_SEL;
668
9f93ac8d
LC		 669 ret = of_mdio_parse_addr(priv->device,
670 priv->plat->phy_node);
671 if (ret < 0) {
672 dev_err(priv->device, "Could not parse MDIO addr\n");
673 return ret;
674 }
675 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
676 * address. No need to mask it again.
677 */
678 reg |= ret << H3_EPHY_ADDR_SHIFT;
679 }
680 }
681
682 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
683 if (val % 100) {
684 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
685 return -EINVAL;
686 }
687 val /= 100;
688 dev_dbg(priv->device, "set tx-delay to %x\n", val);
689 if (val <= SYSCON_ETXDC_MASK) {
690 reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
691 reg |= (val << SYSCON_ETXDC_SHIFT);
692 } else {
693 dev_err(priv->device, "Invalid TX clock delay: %d\n",
694 val);
695 return -EINVAL;
696 }
697 }
698
699 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
700 if (val % 100) {
701 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
702 return -EINVAL;
703 }
704 val /= 100;
705 dev_dbg(priv->device, "set rx-delay to %x\n", val);
706 if (val <= SYSCON_ERXDC_MASK) {
707 reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
708 reg |= (val << SYSCON_ERXDC_SHIFT);
709 } else {
710 dev_err(priv->device, "Invalid RX clock delay: %d\n",
711 val);
712 return -EINVAL;
713 }
714 }
715
716 /* Clear interface mode bits */
717 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
718 if (gmac->variant->support_rmii)
719 reg &= ~SYSCON_RMII_EN;
720
1c2fa5f8
LC		 721 phy_interface = priv->plat->interface;
722 /* if PHY is internal, select the mode (xMII) used by the SoC */
723 if (gmac->use_internal_phy)
724 phy_interface = gmac->variant->internal_phy;
725 switch (phy_interface) {
9f93ac8d
LC		 726 case PHY_INTERFACE_MODE_MII:
727 /* default */
728 break;
729 case PHY_INTERFACE_MODE_RGMII:
730 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
731 break;
732 case PHY_INTERFACE_MODE_RMII:
733 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
734 break;
735 default:
736 dev_err(priv->device, "Unsupported interface mode: %s",
737 phy_modes(priv->plat->interface));
738 return -EINVAL;
739 }
740
741 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
742
743 return 0;
744}
745
746static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
747{
748 u32 reg = gmac->variant->default_syscon_value;
749
750 regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
751}
752
753static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
754{
755 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
756 int ret;
757
758 if (!gmac->use_internal_phy)
759 return 0;
760
761 ret = clk_prepare_enable(gmac->ephy_clk);
762 if (ret) {
763 dev_err(priv->device, "Cannot enable ephy\n");
764 return ret;
765 }
766
2f878491
IZ		 767 /* Make sure the EPHY is properly reseted, as U-Boot may leave
768 * it at deasserted state, and thus it may fail to reset EMAC.
769 */
770 reset_control_assert(gmac->rst_ephy);
771
9f93ac8d
LC		 772 ret = reset_control_deassert(gmac->rst_ephy);
773 if (ret) {
774 dev_err(priv->device, "Cannot deassert ephy\n");
775 clk_disable_unprepare(gmac->ephy_clk);
776 return ret;
777 }
778
779 return 0;
780}
781
782static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
783{
784 if (!gmac->use_internal_phy)
785 return 0;
786
787 clk_disable_unprepare(gmac->ephy_clk);
788 reset_control_assert(gmac->rst_ephy);
789 return 0;
790}
791
792/* sun8i_power_phy() - Activate the PHY:
793 * In case of error, no need to call sun8i_unpower_phy(),
794 * it will be called anyway by sun8i_dwmac_exit()
795 */
796static int sun8i_power_phy(struct stmmac_priv *priv)
797{
798 int ret;
799
800 ret = sun8i_dwmac_power_internal_phy(priv);
801 if (ret)
802 return ret;
803
804 ret = sun8i_dwmac_set_syscon(priv);
805 if (ret)
806 return ret;
807
808 /* After changing syscon value, the MAC need reset or it will use
809 * the last value (and so the last PHY set.
810 */
811 ret = sun8i_dwmac_reset(priv);
812 if (ret)
813 return ret;
814 return 0;
815}
816
817static void sun8i_unpower_phy(struct sunxi_priv_data *gmac)
818{
819 sun8i_dwmac_unset_syscon(gmac);
820 sun8i_dwmac_unpower_internal_phy(gmac);
821}
822
823static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
824{
825 struct sunxi_priv_data *gmac = priv;
826
827 sun8i_unpower_phy(gmac);
828
829 clk_disable_unprepare(gmac->tx_clk);
830
831 if (gmac->regulator)
832 regulator_disable(gmac->regulator);
833}
834
835static const struct stmmac_ops sun8i_dwmac_ops = {
836 .core_init = sun8i_dwmac_core_init,
837 .set_mac = sun8i_dwmac_set_mac,
838 .dump_regs = sun8i_dwmac_dump_mac_regs,
839 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
840 .set_filter = sun8i_dwmac_set_filter,
841 .flow_ctrl = sun8i_dwmac_flow_ctrl,
842 .set_umac_addr = sun8i_dwmac_set_umac_addr,
843 .get_umac_addr = sun8i_dwmac_get_umac_addr,
844};
845
846static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
847{
848 struct mac_device_info *mac;
849 struct stmmac_priv *priv = ppriv;
850 int ret;
851
852 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
853 if (!mac)
854 return NULL;
855
856 ret = sun8i_power_phy(priv);
857 if (ret)
858 return NULL;
859
860 mac->pcsr = priv->ioaddr;
861 mac->mac = &sun8i_dwmac_ops;
862 mac->dma = &sun8i_dwmac_dma_ops;
863
864 /* The loopback bit seems to be re-set when link change
865 * Simply mask it each time
866 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
867 */
868 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
869 mac->link.speed10 = EMAC_SPEED_10;
870 mac->link.speed100 = EMAC_SPEED_100;
871 mac->link.speed1000 = EMAC_SPEED_1000;
872 mac->link.duplex = EMAC_DUPLEX_FULL;
873 mac->mii.addr = EMAC_MDIO_CMD;
874 mac->mii.data = EMAC_MDIO_DATA;
875 mac->mii.reg_shift = 4;
876 mac->mii.reg_mask = GENMASK(8, 4);
877 mac->mii.addr_shift = 12;
878 mac->mii.addr_mask = GENMASK(16, 12);
879 mac->mii.clk_csr_shift = 20;
880 mac->mii.clk_csr_mask = GENMASK(22, 20);
881 mac->unicast_filter_entries = 8;
882
883 /* Synopsys Id is not available */
884 priv->synopsys_id = 0;
885
886 return mac;
887}
888
889static int sun8i_dwmac_probe(struct platform_device *pdev)
890{
891 struct plat_stmmacenet_data *plat_dat;
892 struct stmmac_resources stmmac_res;
893 struct sunxi_priv_data *gmac;
894 struct device *dev = &pdev->dev;
895 int ret;
896
897 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
898 if (ret)
899 return ret;
900
901 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
902 if (IS_ERR(plat_dat))
903 return PTR_ERR(plat_dat);
904
905 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
906 if (!gmac)
907 return -ENOMEM;
908
909 gmac->variant = of_device_get_match_data(&pdev->dev);
910 if (!gmac->variant) {
911 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
912 return -EINVAL;
913 }
914
915 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
916 if (IS_ERR(gmac->tx_clk)) {
917 dev_err(dev, "Could not get TX clock\n");
918 return PTR_ERR(gmac->tx_clk);
919 }
920
921 /* Optional regulator for PHY */
922 gmac->regulator = devm_regulator_get_optional(dev, "phy");
923 if (IS_ERR(gmac->regulator)) {
924 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
925 return -EPROBE_DEFER;
926 dev_info(dev, "No regulator found\n");
927 gmac->regulator = NULL;
928 }
929
930 gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
931 "syscon");
932 if (IS_ERR(gmac->regmap)) {
933 ret = PTR_ERR(gmac->regmap);
934 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
935 return ret;
936 }
937
938 plat_dat->interface = of_get_phy_mode(dev->of_node);
1c2fa5f8 939 if (plat_dat->interface == PHY_INTERFACE_MODE_INTERNAL) {
9f93ac8d
LC		 940 dev_info(&pdev->dev, "Will use internal PHY\n");
941 gmac->use_internal_phy = true;
942 gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
943 if (IS_ERR(gmac->ephy_clk)) {
944 ret = PTR_ERR(gmac->ephy_clk);
945 dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret);
946 return -EINVAL;
947 }
948
949 gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
950 if (IS_ERR(gmac->rst_ephy)) {
951 ret = PTR_ERR(gmac->rst_ephy);
952 if (ret == -EPROBE_DEFER)
953 return ret;
954 dev_err(&pdev->dev, "No EPHY reset control found %d\n",
955 ret);
956 return -EINVAL;
957 }
958 } else {
959 dev_info(&pdev->dev, "Will use external PHY\n");
960 gmac->use_internal_phy = false;
961 }
962
963 /* platform data specifying hardware features and callbacks.
964 * hardware features were copied from Allwinner drivers.
965 */
966 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
967 plat_dat->tx_coe = 1;
968 plat_dat->has_sun8i = true;
969 plat_dat->bsp_priv = gmac;
970 plat_dat->init = sun8i_dwmac_init;
971 plat_dat->exit = sun8i_dwmac_exit;
972 plat_dat->setup = sun8i_dwmac_setup;
973
974 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
975 if (ret)
976 return ret;
977
978 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
979 if (ret)
980 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
981
982 return ret;
983}
984
985static const struct of_device_id sun8i_dwmac_match[] = {
986 { .compatible = "allwinner,sun8i-h3-emac",
987 .data = &emac_variant_h3 },
57fde47d
IZ		 988 { .compatible = "allwinner,sun8i-v3s-emac",
989 .data = &emac_variant_v3s },
9f93ac8d
LC		 990 { .compatible = "allwinner,sun8i-a83t-emac",
991 .data = &emac_variant_a83t },
992 { .compatible = "allwinner,sun50i-a64-emac",
993 .data = &emac_variant_a64 },
994 { }
995};
996MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
997
998static struct platform_driver sun8i_dwmac_driver = {
999 .probe = sun8i_dwmac_probe,
1000 .remove = stmmac_pltfr_remove,
1001 .driver = {
1002 .name = "dwmac-sun8i",
1003 .pm = &stmmac_pltfr_pm_ops,
1004 .of_match_table = sun8i_dwmac_match,
1005 },
1006};
1007module_platform_driver(sun8i_dwmac_driver);
1008
1009MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1010MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1011MODULE_LICENSE("GPL");
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