[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / stmicro / stmmac / dwmac100_dma.c

/*******************************************************************************
  This is the driver for the MAC 10/100 on-chip Ethernet controller
  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.

  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  this code.

  This contains the functions to handle the dma.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <asm/io.h>
#include "dwmac100.h"
#include "dwmac_dma.h"

static void dwmac100_dma_init(void __iomem *ioaddr,
			      struct stmmac_dma_cfg *dma_cfg,
			      u32 dma_tx, u32 dma_rx, int atds)
{
	/* Enable Application Access by writing to DMA CSR0 */
	writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
	       ioaddr + DMA_BUS_MODE);

	/* Mask interrupts by writing to CSR7 */
	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

	/* RX/TX descriptor base addr lists must be written into
	 * DMA CSR3 and CSR4, respectively
	 */
	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
}

/* Store and Forward capability is not used at all.
 *
 * The transmit threshold can be programmed by setting the TTC bits in the DMA
 * control register.
 */
static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
					int rxmode, int rxfifosz)
{
	u32 csr6 = readl(ioaddr + DMA_CONTROL);

	if (txmode <= 32)
		csr6 |= DMA_CONTROL_TTC_32;
	else if (txmode <= 64)
		csr6 |= DMA_CONTROL_TTC_64;
	else
		csr6 |= DMA_CONTROL_TTC_128;

	writel(csr6, ioaddr + DMA_CONTROL);
}

static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
{
	int i;

	for (i = 0; i < 9; i++)
		reg_space[DMA_BUS_MODE / 4 + i] =
			readl(ioaddr + DMA_BUS_MODE + i * 4);

	reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
		readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
	reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
		readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
}

/* DMA controller has two counters to track the number of the missed frames. */
static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
				       void __iomem *ioaddr)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);

	if (unlikely(csr8)) {
		if (csr8 & DMA_MISSED_FRAME_OVE) {
			stats->rx_over_errors += 0x800;
			x->rx_overflow_cntr += 0x800;
		} else {
			unsigned int ove_cntr;
			ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
			stats->rx_over_errors += ove_cntr;
			x->rx_overflow_cntr += ove_cntr;
		}

		if (csr8 & DMA_MISSED_FRAME_OVE_M) {
			stats->rx_missed_errors += 0xffff;
			x->rx_missed_cntr += 0xffff;
		} else {
			unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
			stats->rx_missed_errors += miss_f;
			x->rx_missed_cntr += miss_f;
		}
	}
}

const struct stmmac_dma_ops dwmac100_dma_ops = {
	.reset = dwmac_dma_reset,
	.init = dwmac100_dma_init,
	.dump_regs = dwmac100_dump_dma_regs,
	.dma_mode = dwmac100_dma_operation_mode,
	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
	.enable_dma_transmission = dwmac_enable_dma_transmission,
	.enable_dma_irq = dwmac_enable_dma_irq,
	.disable_dma_irq = dwmac_disable_dma_irq,
	.start_tx = dwmac_dma_start_tx,
	.stop_tx = dwmac_dma_stop_tx,
	.start_rx = dwmac_dma_start_rx,
	.stop_rx = dwmac_dma_stop_rx,
	.dma_interrupt = dwmac_dma_interrupt,
};
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	This is the driver for the MAC 10/100 on-chip Ethernet controller
	3	currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
	4
	5	DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
	6	this code.
	7
56b106ae	8	This contains the functions to handle the dma.
3c32be63	9
47dd7a54 GC	10	Copyright (C) 2007-2009 STMicroelectronics Ltd
	11
	12	This program is free software; you can redistribute it and/or modify it
	13	under the terms and conditions of the GNU General Public License,
	14	version 2, as published by the Free Software Foundation.
	15
	16	This program is distributed in the hope it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	more details.
	20
47dd7a54 GC	21	The full GNU General Public License is included in this distribution in
	22	the file called "COPYING".
	23
	24	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	25	*******************************************************************************/
	26
b7f080cf	27	#include <asm/io.h>
7e848ae1	28	#include "dwmac100.h"
aec7ff27	29	#include "dwmac_dma.h"
47dd7a54	30
50ca903a NC	31	static void dwmac100_dma_init(void __iomem *ioaddr,
	32	struct stmmac_dma_cfg *dma_cfg,
	33	u32 dma_tx, u32 dma_rx, int atds)
47dd7a54	34	{
47dd7a54	35	/* Enable Application Access by writing to DMA CSR0 */
50ca903a	36	writel(DMA_BUS_MODE_DEFAULT \| (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
ceb69499	37	ioaddr + DMA_BUS_MODE);
47dd7a54 GC	38
	39	/* Mask interrupts by writing to CSR7 */
	40	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
	41
ceb69499 GC	42	/* RX/TX descriptor base addr lists must be written into
	43	* DMA CSR3 and CSR4, respectively
	44	*/
47dd7a54 GC	45	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
47dd7a54 GC	46	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
47dd7a54 GC	47	}
47dd7a54 GC	48
ceb69499 GC	49	/* Store and Forward capability is not used at all.
	50	*
	51	* The transmit threshold can be programmed by setting the TTC bits in the DMA
	52	* control register.
	53	*/
ad01b7d4	54	static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode,
f88203a2	55	int rxmode, int rxfifosz)
47dd7a54 GC	56	{
	57	u32 csr6 = readl(ioaddr + DMA_CONTROL);
	58
	59	if (txmode <= 32)
	60	csr6 \|= DMA_CONTROL_TTC_32;
	61	else if (txmode <= 64)
	62	csr6 \|= DMA_CONTROL_TTC_64;
	63	else
	64	csr6 \|= DMA_CONTROL_TTC_128;
	65
	66	writel(csr6, ioaddr + DMA_CONTROL);
47dd7a54 GC	67	}
47dd7a54 GC	68
fbf68229	69	static void dwmac100_dump_dma_regs(void __iomem ioaddr, u32 reg_space)
47dd7a54 GC	70	{
	71	int i;
	72
47dd7a54	73	for (i = 0; i < 9; i++)
fbf68229 LC	74	reg_space[DMA_BUS_MODE / 4 + i] =
fbf68229 LC	75	readl(ioaddr + DMA_BUS_MODE + i * 4);
83d7af64	76
fbf68229 LC	77	reg_space[DMA_CUR_TX_BUF_ADDR / 4] =
	78	readl(ioaddr + DMA_CUR_TX_BUF_ADDR);
	79	reg_space[DMA_CUR_RX_BUF_ADDR / 4] =
	80	readl(ioaddr + DMA_CUR_RX_BUF_ADDR);
47dd7a54 GC	81	}
47dd7a54 GC	82
ceb69499	83	/* DMA controller has two counters to track the number of the missed frames. */
3c32be63	84	static void dwmac100_dma_diagnostic_fr(void data, struct stmmac_extra_stats x,
ad01b7d4	85	void __iomem *ioaddr)
47dd7a54 GC	86	{
	87	struct net_device_stats stats = (struct net_device_stats )data;
	88	u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
	89
	90	if (unlikely(csr8)) {
	91	if (csr8 & DMA_MISSED_FRAME_OVE) {
	92	stats->rx_over_errors += 0x800;
	93	x->rx_overflow_cntr += 0x800;
	94	} else {
	95	unsigned int ove_cntr;
	96	ove_cntr = ((csr8 & DMA_MISSED_FRAME_OVE_CNTR) >> 17);
	97	stats->rx_over_errors += ove_cntr;
	98	x->rx_overflow_cntr += ove_cntr;
	99	}
	100
	101	if (csr8 & DMA_MISSED_FRAME_OVE_M) {
	102	stats->rx_missed_errors += 0xffff;
	103	x->rx_missed_cntr += 0xffff;
	104	} else {
	105	unsigned int miss_f = (csr8 & DMA_MISSED_FRAME_M_CNTR);
	106	stats->rx_missed_errors += miss_f;
	107	x->rx_missed_cntr += miss_f;
	108	}
	109	}
47dd7a54 GC	110	}
47dd7a54 GC	111
cadb7924	112	const struct stmmac_dma_ops dwmac100_dma_ops = {
495db273	113	.reset = dwmac_dma_reset,
7e848ae1 GC	114	.init = dwmac100_dma_init,
	115	.dump_regs = dwmac100_dump_dma_regs,
	116	.dma_mode = dwmac100_dma_operation_mode,
	117	.dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
aec7ff27 GC	118	.enable_dma_transmission = dwmac_enable_dma_transmission,
	119	.enable_dma_irq = dwmac_enable_dma_irq,
	120	.disable_dma_irq = dwmac_disable_dma_irq,
	121	.start_tx = dwmac_dma_start_tx,
	122	.stop_tx = dwmac_dma_stop_tx,
	123	.start_rx = dwmac_dma_start_rx,
	124	.stop_rx = dwmac_dma_stop_rx,
	125	.dma_interrupt = dwmac_dma_interrupt,
db98a0b0	126	};