[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_core.c

/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.00  has been used for developing this code.
 *
 * This only implements the mac core functions for this chip.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/crc32.h>
#include <linux/slab.h>
#include <linux/ethtool.h>
#include <linux/io.h>
#include "stmmac_pcs.h"
#include "dwmac4.h"

static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_CONFIG);

	value |= GMAC_CORE_INIT;

	if (mtu > 1500)
		value |= GMAC_CONFIG_2K;
	if (mtu > 2000)
		value |= GMAC_CONFIG_JE;

	if (hw->ps) {
		value |= GMAC_CONFIG_TE;

		if (hw->ps == SPEED_1000) {
			value &= ~GMAC_CONFIG_PS;
		} else {
			value |= GMAC_CONFIG_PS;

			if (hw->ps == SPEED_10)
				value &= ~GMAC_CONFIG_FES;
			else
				value |= GMAC_CONFIG_FES;
		}
	}

	writel(value, ioaddr + GMAC_CONFIG);

	/* Mask GMAC interrupts */
	value = GMAC_INT_DEFAULT_MASK;
	if (hw->pmt)
		value |= GMAC_INT_PMT_EN;
	if (hw->pcs)
		value |= GMAC_PCS_IRQ_DEFAULT;

	writel(value, ioaddr + GMAC_INT_EN);
}

static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);

	value &= GMAC_RX_QUEUE_CLEAR(queue);
	value |= GMAC_RX_AV_QUEUE_ENABLE(queue);

	writel(value, ioaddr + GMAC_RXQ_CTRL0);
}

static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
					  u32 rx_alg)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MTL_OPERATION_MODE);

	value &= ~MTL_OPERATION_RAA;
	switch (rx_alg) {
	case MTL_RX_ALGORITHM_SP:
		value |= MTL_OPERATION_RAA_SP;
		break;
	case MTL_RX_ALGORITHM_WSP:
		value |= MTL_OPERATION_RAA_WSP;
		break;
	default:
		break;
	}

	writel(value, ioaddr + MTL_OPERATION_MODE);
}

static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
					  u32 tx_alg)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MTL_OPERATION_MODE);

	value &= ~MTL_OPERATION_SCHALG_MASK;
	switch (tx_alg) {
	case MTL_TX_ALGORITHM_WRR:
		value |= MTL_OPERATION_SCHALG_WRR;
		break;
	case MTL_TX_ALGORITHM_WFQ:
		value |= MTL_OPERATION_SCHALG_WFQ;
		break;
	case MTL_TX_ALGORITHM_DWRR:
		value |= MTL_OPERATION_SCHALG_DWRR;
		break;
	case MTL_TX_ALGORITHM_SP:
		value |= MTL_OPERATION_SCHALG_SP;
		break;
	default:
		break;
	}
}

static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
{
	void __iomem *ioaddr = hw->pcsr;
	int i;

	for (i = 0; i < GMAC_REG_NUM; i++)
		reg_space[i] = readl(ioaddr + i * 4);
}

static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_CONFIG);

	if (hw->rx_csum)
		value |= GMAC_CONFIG_IPC;
	else
		value &= ~GMAC_CONFIG_IPC;

	writel(value, ioaddr + GMAC_CONFIG);

	value = readl(ioaddr + GMAC_CONFIG);

	return !!(value & GMAC_CONFIG_IPC);
}

static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
{
	void __iomem *ioaddr = hw->pcsr;
	unsigned int pmt = 0;

	if (mode & WAKE_MAGIC) {
		pr_debug("GMAC: WOL Magic frame\n");
		pmt |= power_down | magic_pkt_en;
	}
	if (mode & WAKE_UCAST) {
		pr_debug("GMAC: WOL on global unicast\n");
		pmt |= power_down | global_unicast | wake_up_frame_en;
	}

	writel(pmt, ioaddr + GMAC_PMT);
}

static void dwmac4_set_umac_addr(struct mac_device_info *hw,
				 unsigned char *addr, unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;

	stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				   GMAC_ADDR_LOW(reg_n));
}

static void dwmac4_get_umac_addr(struct mac_device_info *hw,
				 unsigned char *addr, unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;

	stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				   GMAC_ADDR_LOW(reg_n));
}

static void dwmac4_set_eee_mode(struct mac_device_info *hw,
				bool en_tx_lpi_clockgating)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	/* Enable the link status receive on RGMII, SGMII ore SMII
	 * receive path and instruct the transmit to enter in LPI
	 * state.
	 */
	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;

	if (en_tx_lpi_clockgating)
		value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	if (link)
		value |= GMAC4_LPI_CTRL_STATUS_PLS;
	else
		value &= ~GMAC4_LPI_CTRL_STATUS_PLS;

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
{
	void __iomem *ioaddr = hw->pcsr;
	int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);

	/* Program the timers in the LPI timer control register:
	 * LS: minimum time (ms) for which the link
	 *  status from PHY should be ok before transmitting
	 *  the LPI pattern.
	 * TW: minimum time (us) for which the core waits
	 *  after it has stopped transmitting the LPI pattern.
	 */
	writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
}

static void dwmac4_set_filter(struct mac_device_info *hw,
			      struct net_device *dev)
{
	void __iomem *ioaddr = (void __iomem *)dev->base_addr;
	unsigned int value = 0;

	if (dev->flags & IFF_PROMISC) {
		value = GMAC_PACKET_FILTER_PR;
	} else if ((dev->flags & IFF_ALLMULTI) ||
			(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
		/* Pass all multi */
		value = GMAC_PACKET_FILTER_PM;
		/* Set the 64 bits of the HASH tab. To be updated if taller
		 * hash table is used
		 */
		writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
		writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
	} else if (!netdev_mc_empty(dev)) {
		u32 mc_filter[2];
		struct netdev_hw_addr *ha;

		/* Hash filter for multicast */
		value = GMAC_PACKET_FILTER_HMC;

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the content of the Hash Table Reg 0 and 1.
			 */
			int bit_nr =
				(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
			/* The most significant bit determines the register
			 * to use while the other 5 bits determines the bit
			 * within the selected register
			 */
			mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
		}
		writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
		writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
	}

	/* Handle multiple unicast addresses */
	if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
		/* Switch to promiscuous mode if more than 128 addrs
		 * are required
		 */
		value |= GMAC_PACKET_FILTER_PR;
	} else if (!netdev_uc_empty(dev)) {
		int reg = 1;
		struct netdev_hw_addr *ha;

		netdev_for_each_uc_addr(ha, dev) {
			dwmac4_set_umac_addr(hw, ha->addr, reg);
			reg++;
		}
	}

	writel(value, ioaddr + GMAC_PACKET_FILTER);
}

static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
			     unsigned int fc, unsigned int pause_time)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 channel = STMMAC_CHAN0;	/* FIXME */
	unsigned int flow = 0;

	pr_debug("GMAC Flow-Control:\n");
	if (fc & FLOW_RX) {
		pr_debug("\tReceive Flow-Control ON\n");
		flow |= GMAC_RX_FLOW_CTRL_RFE;
		writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
	}
	if (fc & FLOW_TX) {
		pr_debug("\tTransmit Flow-Control ON\n");
		flow |= GMAC_TX_FLOW_CTRL_TFE;
		writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));

		if (duplex) {
			pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
			flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
			writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
		}
	}
}

static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
			    bool loopback)
{
	dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
}

static void dwmac4_rane(void __iomem *ioaddr, bool restart)
{
	dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
}

static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
{
	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
}

/* RGMII or SMII interface */
static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
{
	u32 status;

	status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
	x->irq_rgmii_n++;

	/* Check the link status */
	if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
		int speed_value;

		x->pcs_link = 1;

		speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
			       GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
		if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
			x->pcs_speed = SPEED_1000;
		else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
			x->pcs_speed = SPEED_100;
		else
			x->pcs_speed = SPEED_10;

		x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);

		pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
			x->pcs_duplex ? "Full" : "Half");
	} else {
		x->pcs_link = 0;
		pr_info("Link is Down\n");
	}
}

static int dwmac4_irq_status(struct mac_device_info *hw,
			     struct stmmac_extra_stats *x)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 mtl_int_qx_status;
	u32 intr_status;
	int ret = 0;

	intr_status = readl(ioaddr + GMAC_INT_STATUS);

	/* Not used events (e.g. MMC interrupts) are not handled. */
	if ((intr_status & mmc_tx_irq))
		x->mmc_tx_irq_n++;
	if (unlikely(intr_status & mmc_rx_irq))
		x->mmc_rx_irq_n++;
	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
		x->mmc_rx_csum_offload_irq_n++;
	/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
	if (unlikely(intr_status & pmt_irq)) {
		readl(ioaddr + GMAC_PMT);
		x->irq_receive_pmt_irq_n++;
	}

	mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
	/* Check MTL Interrupt: Currently only one queue is used: Q0. */
	if (mtl_int_qx_status & MTL_INT_Q0) {
		/* read Queue 0 Interrupt status */
		u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));

		if (status & MTL_RX_OVERFLOW_INT) {
			/*  clear Interrupt */
			writel(status | MTL_RX_OVERFLOW_INT,
			       ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
			ret = CORE_IRQ_MTL_RX_OVERFLOW;
		}
	}

	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
	if (intr_status & PCS_RGSMIIIS_IRQ)
		dwmac4_phystatus(ioaddr, x);

	return ret;
}

static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
{
	u32 value;

	/*  Currently only channel 0 is supported */
	value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));

	if (value & MTL_DEBUG_TXSTSFSTS)
		x->mtl_tx_status_fifo_full++;
	if (value & MTL_DEBUG_TXFSTS)
		x->mtl_tx_fifo_not_empty++;
	if (value & MTL_DEBUG_TWCSTS)
		x->mmtl_fifo_ctrl++;
	if (value & MTL_DEBUG_TRCSTS_MASK) {
		u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
			     >> MTL_DEBUG_TRCSTS_SHIFT;
		if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
			x->mtl_tx_fifo_read_ctrl_write++;
		else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
			x->mtl_tx_fifo_read_ctrl_wait++;
		else if (trcsts == MTL_DEBUG_TRCSTS_READ)
			x->mtl_tx_fifo_read_ctrl_read++;
		else
			x->mtl_tx_fifo_read_ctrl_idle++;
	}
	if (value & MTL_DEBUG_TXPAUSED)
		x->mac_tx_in_pause++;

	value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));

	if (value & MTL_DEBUG_RXFSTS_MASK) {
		u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
			     >> MTL_DEBUG_RRCSTS_SHIFT;

		if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
			x->mtl_rx_fifo_fill_level_full++;
		else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
			x->mtl_rx_fifo_fill_above_thresh++;
		else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
			x->mtl_rx_fifo_fill_below_thresh++;
		else
			x->mtl_rx_fifo_fill_level_empty++;
	}
	if (value & MTL_DEBUG_RRCSTS_MASK) {
		u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
			     MTL_DEBUG_RRCSTS_SHIFT;

		if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
			x->mtl_rx_fifo_read_ctrl_flush++;
		else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
			x->mtl_rx_fifo_read_ctrl_read_data++;
		else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
			x->mtl_rx_fifo_read_ctrl_status++;
		else
			x->mtl_rx_fifo_read_ctrl_idle++;
	}
	if (value & MTL_DEBUG_RWCSTS)
		x->mtl_rx_fifo_ctrl_active++;

	/* GMAC debug */
	value = readl(ioaddr + GMAC_DEBUG);

	if (value & GMAC_DEBUG_TFCSTS_MASK) {
		u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
			      >> GMAC_DEBUG_TFCSTS_SHIFT;

		if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
			x->mac_tx_frame_ctrl_xfer++;
		else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
			x->mac_tx_frame_ctrl_pause++;
		else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
			x->mac_tx_frame_ctrl_wait++;
		else
			x->mac_tx_frame_ctrl_idle++;
	}
	if (value & GMAC_DEBUG_TPESTS)
		x->mac_gmii_tx_proto_engine++;
	if (value & GMAC_DEBUG_RFCFCSTS_MASK)
		x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
					    >> GMAC_DEBUG_RFCFCSTS_SHIFT;
	if (value & GMAC_DEBUG_RPESTS)
		x->mac_gmii_rx_proto_engine++;
}

static const struct stmmac_ops dwmac4_ops = {
	.core_init = dwmac4_core_init,
	.rx_ipc = dwmac4_rx_ipc_enable,
	.rx_queue_enable = dwmac4_rx_queue_enable,
	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
	.dump_regs = dwmac4_dump_regs,
	.host_irq_status = dwmac4_irq_status,
	.flow_ctrl = dwmac4_flow_ctrl,
	.pmt = dwmac4_pmt,
	.set_umac_addr = dwmac4_set_umac_addr,
	.get_umac_addr = dwmac4_get_umac_addr,
	.set_eee_mode = dwmac4_set_eee_mode,
	.reset_eee_mode = dwmac4_reset_eee_mode,
	.set_eee_timer = dwmac4_set_eee_timer,
	.set_eee_pls = dwmac4_set_eee_pls,
	.pcs_ctrl_ane = dwmac4_ctrl_ane,
	.pcs_rane = dwmac4_rane,
	.pcs_get_adv_lp = dwmac4_get_adv_lp,
	.debug = dwmac4_debug,
	.set_filter = dwmac4_set_filter,
};

struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
				     int perfect_uc_entries, int *synopsys_id)
{
	struct mac_device_info *mac;
	u32 hwid = readl(ioaddr + GMAC_VERSION);

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	if (!mac)
		return NULL;

	mac->pcsr = ioaddr;
	mac->multicast_filter_bins = mcbins;
	mac->unicast_filter_entries = perfect_uc_entries;
	mac->mcast_bits_log2 = 0;

	if (mac->multicast_filter_bins)
		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);

	mac->mac = &dwmac4_ops;

	mac->link.port = GMAC_CONFIG_PS;
	mac->link.duplex = GMAC_CONFIG_DM;
	mac->link.speed = GMAC_CONFIG_FES;
	mac->mii.addr = GMAC_MDIO_ADDR;
	mac->mii.data = GMAC_MDIO_DATA;
	mac->mii.addr_shift = 21;
	mac->mii.addr_mask = GENMASK(25, 21);
	mac->mii.reg_shift = 16;
	mac->mii.reg_mask = GENMASK(20, 16);
	mac->mii.clk_csr_shift = 8;
	mac->mii.clk_csr_mask = GENMASK(11, 8);

	/* Get and dump the chip ID */
	*synopsys_id = stmmac_get_synopsys_id(hwid);

	if (*synopsys_id > DWMAC_CORE_4_00)
		mac->dma = &dwmac410_dma_ops;
	else
		mac->dma = &dwmac4_dma_ops;

	return mac;
}
Commit	Line	Data
477286b5 AT	1	/*
	2	* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	3	* DWC Ether MAC version 4.00 has been used for developing this code.
	4	*
	5	* This only implements the mac core functions for this chip.
	6	*
	7	* Copyright (C) 2015 STMicroelectronics Ltd
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2, as published by the Free Software Foundation.
	12	*
	13	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	14	*/
	15
	16	#include <linux/crc32.h>
	17	#include <linux/slab.h>
	18	#include <linux/ethtool.h>
	19	#include <linux/io.h>
70523e63	20	#include "stmmac_pcs.h"
477286b5 AT	21	#include "dwmac4.h"
	22
	23	static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
	24	{
	25	void __iomem *ioaddr = hw->pcsr;
	26	u32 value = readl(ioaddr + GMAC_CONFIG);
	27
	28	value \|= GMAC_CORE_INIT;
	29
	30	if (mtu > 1500)
	31	value \|= GMAC_CONFIG_2K;
	32	if (mtu > 2000)
	33	value \|= GMAC_CONFIG_JE;
	34
02e57b9d GC	35	if (hw->ps) {
	36	value \|= GMAC_CONFIG_TE;
	37
	38	if (hw->ps == SPEED_1000) {
	39	value &= ~GMAC_CONFIG_PS;
	40	} else {
	41	value \|= GMAC_CONFIG_PS;
	42
	43	if (hw->ps == SPEED_10)
	44	value &= ~GMAC_CONFIG_FES;
	45	else
	46	value \|= GMAC_CONFIG_FES;
	47	}
	48	}
	49
477286b5 AT	50	writel(value, ioaddr + GMAC_CONFIG);
	51
	52	/* Mask GMAC interrupts */
3fe5cadb GC	53	value = GMAC_INT_DEFAULT_MASK;
	54	if (hw->pmt)
	55	value \|= GMAC_INT_PMT_EN;
	56	if (hw->pcs)
	57	value \|= GMAC_PCS_IRQ_DEFAULT;
	58
	59	writel(value, ioaddr + GMAC_INT_EN);
477286b5 AT	60	}
477286b5 AT	61
9eb12474	62	static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
	63	{
	64	void __iomem *ioaddr = hw->pcsr;
	65	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
	66
	67	value &= GMAC_RX_QUEUE_CLEAR(queue);
	68	value \|= GMAC_RX_AV_QUEUE_ENABLE(queue);
	69
	70	writel(value, ioaddr + GMAC_RXQ_CTRL0);
	71	}
	72
d0a9c9f9 JP	73	static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
	74	u32 rx_alg)
	75	{
	76	void __iomem *ioaddr = hw->pcsr;
	77	u32 value = readl(ioaddr + MTL_OPERATION_MODE);
	78
	79	value &= ~MTL_OPERATION_RAA;
	80	switch (rx_alg) {
	81	case MTL_RX_ALGORITHM_SP:
	82	value \|= MTL_OPERATION_RAA_SP;
	83	break;
	84	case MTL_RX_ALGORITHM_WSP:
	85	value \|= MTL_OPERATION_RAA_WSP;
	86	break;
	87	default:
	88	break;
	89	}
	90
	91	writel(value, ioaddr + MTL_OPERATION_MODE);
	92	}
	93
	94	static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
	95	u32 tx_alg)
	96	{
	97	void __iomem *ioaddr = hw->pcsr;
	98	u32 value = readl(ioaddr + MTL_OPERATION_MODE);
	99
	100	value &= ~MTL_OPERATION_SCHALG_MASK;
	101	switch (tx_alg) {
	102	case MTL_TX_ALGORITHM_WRR:
	103	value \|= MTL_OPERATION_SCHALG_WRR;
	104	break;
	105	case MTL_TX_ALGORITHM_WFQ:
	106	value \|= MTL_OPERATION_SCHALG_WFQ;
	107	break;
	108	case MTL_TX_ALGORITHM_DWRR:
	109	value \|= MTL_OPERATION_SCHALG_DWRR;
	110	break;
	111	case MTL_TX_ALGORITHM_SP:
	112	value \|= MTL_OPERATION_SCHALG_SP;
	113	break;
	114	default:
	115	break;
	116	}
	117	}
	118
fbf68229	119	static void dwmac4_dump_regs(struct mac_device_info hw, u32 reg_space)
477286b5 AT	120	{
	121	void __iomem *ioaddr = hw->pcsr;
	122	int i;
	123
fbf68229 LC	124	for (i = 0; i < GMAC_REG_NUM; i++)
fbf68229 LC	125	reg_space[i] = readl(ioaddr + i * 4);
477286b5 AT	126	}
	127
	128	static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
	129	{
	130	void __iomem *ioaddr = hw->pcsr;
	131	u32 value = readl(ioaddr + GMAC_CONFIG);
	132
	133	if (hw->rx_csum)
	134	value \|= GMAC_CONFIG_IPC;
	135	else
	136	value &= ~GMAC_CONFIG_IPC;
	137
	138	writel(value, ioaddr + GMAC_CONFIG);
	139
	140	value = readl(ioaddr + GMAC_CONFIG);
	141
	142	return !!(value & GMAC_CONFIG_IPC);
	143	}
	144
	145	static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
	146	{
	147	void __iomem *ioaddr = hw->pcsr;
	148	unsigned int pmt = 0;
	149
	150	if (mode & WAKE_MAGIC) {
	151	pr_debug("GMAC: WOL Magic frame\n");
	152	pmt \|= power_down \| magic_pkt_en;
	153	}
	154	if (mode & WAKE_UCAST) {
	155	pr_debug("GMAC: WOL on global unicast\n");
19cd1203	156	pmt \|= power_down \| global_unicast \| wake_up_frame_en;
477286b5 AT	157	}
	158
	159	writel(pmt, ioaddr + GMAC_PMT);
	160	}
	161
	162	static void dwmac4_set_umac_addr(struct mac_device_info *hw,
	163	unsigned char *addr, unsigned int reg_n)
	164	{
	165	void __iomem *ioaddr = hw->pcsr;
	166
	167	stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	168	GMAC_ADDR_LOW(reg_n));
	169	}
	170
	171	static void dwmac4_get_umac_addr(struct mac_device_info *hw,
	172	unsigned char *addr, unsigned int reg_n)
	173	{
	174	void __iomem *ioaddr = hw->pcsr;
	175
	176	stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	177	GMAC_ADDR_LOW(reg_n));
	178	}
	179
b4b7b772	180	static void dwmac4_set_eee_mode(struct mac_device_info *hw,
b4b7b772	181	bool en_tx_lpi_clockgating)
afbb1674	182	{
	183	void __iomem *ioaddr = hw->pcsr;
	184	u32 value;
	185
	186	/* Enable the link status receive on RGMII, SGMII ore SMII
	187	* receive path and instruct the transmit to enter in LPI
	188	* state.
	189	*/
	190	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	191	value \|= GMAC4_LPI_CTRL_STATUS_LPIEN \| GMAC4_LPI_CTRL_STATUS_LPITXA;
	192
b4b7b772	193	if (en_tx_lpi_clockgating)
	194	value \|= GMAC4_LPI_CTRL_STATUS_LPITCSE;
	195
afbb1674	196	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	197	}
	198
	199	static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
	200	{
	201	void __iomem *ioaddr = hw->pcsr;
	202	u32 value;
	203
	204	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	205	value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN \| GMAC4_LPI_CTRL_STATUS_LPITXA);
	206	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	207	}
	208
	209	static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
	210	{
	211	void __iomem *ioaddr = hw->pcsr;
	212	u32 value;
	213
	214	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	215
	216	if (link)
	217	value \|= GMAC4_LPI_CTRL_STATUS_PLS;
	218	else
	219	value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
	220
	221	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	222	}
	223
	224	static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
	225	{
	226	void __iomem *ioaddr = hw->pcsr;
f4ec6064	227	int value = ((tw & 0xffff)) \| ((ls & 0x3ff) << 16);
afbb1674	228
	229	/* Program the timers in the LPI timer control register:
	230	* LS: minimum time (ms) for which the link
	231	* status from PHY should be ok before transmitting
	232	* the LPI pattern.
	233	* TW: minimum time (us) for which the core waits
	234	* after it has stopped transmitting the LPI pattern.
	235	*/
	236	writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
	237	}
	238
477286b5 AT	239	static void dwmac4_set_filter(struct mac_device_info *hw,
	240	struct net_device *dev)
	241	{
	242	void __iomem ioaddr = (void __iomem )dev->base_addr;
	243	unsigned int value = 0;
	244
	245	if (dev->flags & IFF_PROMISC) {
	246	value = GMAC_PACKET_FILTER_PR;
	247	} else if ((dev->flags & IFF_ALLMULTI) \|\|
	248	(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
	249	/* Pass all multi */
	250	value = GMAC_PACKET_FILTER_PM;
	251	/* Set the 64 bits of the HASH tab. To be updated if taller
	252	* hash table is used
	253	*/
	254	writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
	255	writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
	256	} else if (!netdev_mc_empty(dev)) {
	257	u32 mc_filter[2];
	258	struct netdev_hw_addr *ha;
	259
	260	/* Hash filter for multicast */
	261	value = GMAC_PACKET_FILTER_HMC;
	262
	263	memset(mc_filter, 0, sizeof(mc_filter));
	264	netdev_for_each_mc_addr(ha, dev) {
	265	/* The upper 6 bits of the calculated CRC are used to
	266	* index the content of the Hash Table Reg 0 and 1.
	267	*/
	268	int bit_nr =
	269	(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
	270	/* The most significant bit determines the register
	271	* to use while the other 5 bits determines the bit
	272	* within the selected register
	273	*/
	274	mc_filter[bit_nr >> 5] \|= (1 << (bit_nr & 0x1F));
	275	}
	276	writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
	277	writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
	278	}
	279
	280	/* Handle multiple unicast addresses */
	281	if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
	282	/* Switch to promiscuous mode if more than 128 addrs
	283	* are required
	284	*/
	285	value \|= GMAC_PACKET_FILTER_PR;
	286	} else if (!netdev_uc_empty(dev)) {
	287	int reg = 1;
	288	struct netdev_hw_addr *ha;
	289
	290	netdev_for_each_uc_addr(ha, dev) {
ca8bdaf1	291	dwmac4_set_umac_addr(hw, ha->addr, reg);
477286b5 AT	292	reg++;
	293	}
	294	}
	295
	296	writel(value, ioaddr + GMAC_PACKET_FILTER);
	297	}
	298
	299	static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
	300	unsigned int fc, unsigned int pause_time)
	301	{
	302	void __iomem *ioaddr = hw->pcsr;
	303	u32 channel = STMMAC_CHAN0; /* FIXME */
	304	unsigned int flow = 0;
	305
	306	pr_debug("GMAC Flow-Control:\n");
	307	if (fc & FLOW_RX) {
	308	pr_debug("\tReceive Flow-Control ON\n");
	309	flow \|= GMAC_RX_FLOW_CTRL_RFE;
	310	writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
	311	}
	312	if (fc & FLOW_TX) {
	313	pr_debug("\tTransmit Flow-Control ON\n");
	314	flow \|= GMAC_TX_FLOW_CTRL_TFE;
	315	writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
	316
	317	if (duplex) {
	318	pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
	319	flow \|= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
	320	writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
	321	}
	322	}
	323	}
	324
70523e63 GC	325	static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
70523e63 GC	326	bool loopback)
477286b5	327	{
70523e63 GC	328	dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
70523e63 GC	329	}
477286b5	330
70523e63 GC	331	static void dwmac4_rane(void __iomem *ioaddr, bool restart)
	332	{
	333	dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
	334	}
477286b5	335
70523e63 GC	336	static void dwmac4_get_adv_lp(void __iomem ioaddr, struct rgmii_adv adv)
	337	{
	338	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
477286b5 AT	339	}
477286b5 AT	340
70523e63 GC	341	/* RGMII or SMII interface */
70523e63 GC	342	static void dwmac4_phystatus(void __iomem ioaddr, struct stmmac_extra_stats x)
477286b5	343	{
70523e63	344	u32 status;
477286b5	345
70523e63 GC	346	status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
70523e63 GC	347	x->irq_rgmii_n++;
477286b5	348
70523e63 GC	349	/* Check the link status */
	350	if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
	351	int speed_value;
477286b5	352
70523e63	353	x->pcs_link = 1;
477286b5	354
70523e63 GC	355	speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
	356	GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
	357	if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
	358	x->pcs_speed = SPEED_1000;
	359	else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
	360	x->pcs_speed = SPEED_100;
	361	else
	362	x->pcs_speed = SPEED_10;
	363
	364	x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
477286b5	365
70523e63 GC	366	pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
	367	x->pcs_duplex ? "Full" : "Half");
	368	} else {
	369	x->pcs_link = 0;
	370	pr_info("Link is Down\n");
	371	}
477286b5 AT	372	}
	373
	374	static int dwmac4_irq_status(struct mac_device_info *hw,
	375	struct stmmac_extra_stats *x)
	376	{
	377	void __iomem *ioaddr = hw->pcsr;
	378	u32 mtl_int_qx_status;
	379	u32 intr_status;
	380	int ret = 0;
	381
	382	intr_status = readl(ioaddr + GMAC_INT_STATUS);
	383
	384	/* Not used events (e.g. MMC interrupts) are not handled. */
	385	if ((intr_status & mmc_tx_irq))
	386	x->mmc_tx_irq_n++;
	387	if (unlikely(intr_status & mmc_rx_irq))
	388	x->mmc_rx_irq_n++;
	389	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
	390	x->mmc_rx_csum_offload_irq_n++;
	391	/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
	392	if (unlikely(intr_status & pmt_irq)) {
	393	readl(ioaddr + GMAC_PMT);
	394	x->irq_receive_pmt_irq_n++;
	395	}
	396
477286b5 AT	397	mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
	398	/* Check MTL Interrupt: Currently only one queue is used: Q0. */
	399	if (mtl_int_qx_status & MTL_INT_Q0) {
	400	/* read Queue 0 Interrupt status */
	401	u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
	402
	403	if (status & MTL_RX_OVERFLOW_INT) {
	404	/* clear Interrupt */
	405	writel(status \| MTL_RX_OVERFLOW_INT,
	406	ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
	407	ret = CORE_IRQ_MTL_RX_OVERFLOW;
	408	}
	409	}
	410
70523e63 GC	411	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
	412	if (intr_status & PCS_RGSMIIIS_IRQ)
	413	dwmac4_phystatus(ioaddr, x);
	414
477286b5 AT	415	return ret;
	416	}
	417
	418	static void dwmac4_debug(void __iomem ioaddr, struct stmmac_extra_stats x)
	419	{
	420	u32 value;
	421
	422	/* Currently only channel 0 is supported */
	423	value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));
	424
	425	if (value & MTL_DEBUG_TXSTSFSTS)
	426	x->mtl_tx_status_fifo_full++;
	427	if (value & MTL_DEBUG_TXFSTS)
	428	x->mtl_tx_fifo_not_empty++;
	429	if (value & MTL_DEBUG_TWCSTS)
	430	x->mmtl_fifo_ctrl++;
	431	if (value & MTL_DEBUG_TRCSTS_MASK) {
	432	u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
	433	>> MTL_DEBUG_TRCSTS_SHIFT;
	434	if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
	435	x->mtl_tx_fifo_read_ctrl_write++;
	436	else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
	437	x->mtl_tx_fifo_read_ctrl_wait++;
	438	else if (trcsts == MTL_DEBUG_TRCSTS_READ)
	439	x->mtl_tx_fifo_read_ctrl_read++;
	440	else
	441	x->mtl_tx_fifo_read_ctrl_idle++;
	442	}
	443	if (value & MTL_DEBUG_TXPAUSED)
	444	x->mac_tx_in_pause++;
	445
	446	value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));
	447
	448	if (value & MTL_DEBUG_RXFSTS_MASK) {
	449	u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
	450	>> MTL_DEBUG_RRCSTS_SHIFT;
	451
	452	if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
	453	x->mtl_rx_fifo_fill_level_full++;
	454	else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
	455	x->mtl_rx_fifo_fill_above_thresh++;
	456	else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
	457	x->mtl_rx_fifo_fill_below_thresh++;
	458	else
	459	x->mtl_rx_fifo_fill_level_empty++;
	460	}
	461	if (value & MTL_DEBUG_RRCSTS_MASK) {
	462	u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
	463	MTL_DEBUG_RRCSTS_SHIFT;
	464
	465	if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
	466	x->mtl_rx_fifo_read_ctrl_flush++;
	467	else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
	468	x->mtl_rx_fifo_read_ctrl_read_data++;
	469	else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
	470	x->mtl_rx_fifo_read_ctrl_status++;
	471	else
	472	x->mtl_rx_fifo_read_ctrl_idle++;
	473	}
	474	if (value & MTL_DEBUG_RWCSTS)
	475	x->mtl_rx_fifo_ctrl_active++;
	476
	477	/* GMAC debug */
	478	value = readl(ioaddr + GMAC_DEBUG);
479
480	if (value & GMAC_DEBUG_TFCSTS_MASK) {
481	u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
482	>> GMAC_DEBUG_TFCSTS_SHIFT;
483
484	if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
485	x->mac_tx_frame_ctrl_xfer++;
486	else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
487	x->mac_tx_frame_ctrl_pause++;
488	else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
489	x->mac_tx_frame_ctrl_wait++;
490	else
491	x->mac_tx_frame_ctrl_idle++;
492	}
493	if (value & GMAC_DEBUG_TPESTS)
494	x->mac_gmii_tx_proto_engine++;
495	if (value & GMAC_DEBUG_RFCFCSTS_MASK)
496	x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
497	>> GMAC_DEBUG_RFCFCSTS_SHIFT;
498	if (value & GMAC_DEBUG_RPESTS)
499	x->mac_gmii_rx_proto_engine++;
500	}
501
502	static const struct stmmac_ops dwmac4_ops = {
503	.core_init = dwmac4_core_init,
504	.rx_ipc = dwmac4_rx_ipc_enable,
9eb12474	505	.rx_queue_enable = dwmac4_rx_queue_enable,
d0a9c9f9 JP	506	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
d0a9c9f9 JP	507	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
477286b5 AT	508	.dump_regs = dwmac4_dump_regs,
	509	.host_irq_status = dwmac4_irq_status,
	510	.flow_ctrl = dwmac4_flow_ctrl,
	511	.pmt = dwmac4_pmt,
	512	.set_umac_addr = dwmac4_set_umac_addr,
	513	.get_umac_addr = dwmac4_get_umac_addr,
afbb1674	514	.set_eee_mode = dwmac4_set_eee_mode,
	515	.reset_eee_mode = dwmac4_reset_eee_mode,
	516	.set_eee_timer = dwmac4_set_eee_timer,
	517	.set_eee_pls = dwmac4_set_eee_pls,
70523e63 GC	518	.pcs_ctrl_ane = dwmac4_ctrl_ane,
	519	.pcs_rane = dwmac4_rane,
	520	.pcs_get_adv_lp = dwmac4_get_adv_lp,
477286b5 AT	521	.debug = dwmac4_debug,
	522	.set_filter = dwmac4_set_filter,
	523	};
	524
	525	struct mac_device_info dwmac4_setup(void __iomem ioaddr, int mcbins,
	526	int perfect_uc_entries, int *synopsys_id)
	527	{
	528	struct mac_device_info *mac;
	529	u32 hwid = readl(ioaddr + GMAC_VERSION);
	530
	531	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	532	if (!mac)
	533	return NULL;
	534
	535	mac->pcsr = ioaddr;
	536	mac->multicast_filter_bins = mcbins;
	537	mac->unicast_filter_entries = perfect_uc_entries;
	538	mac->mcast_bits_log2 = 0;
	539
	540	if (mac->multicast_filter_bins)
	541	mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
	542
	543	mac->mac = &dwmac4_ops;
	544
	545	mac->link.port = GMAC_CONFIG_PS;
	546	mac->link.duplex = GMAC_CONFIG_DM;
	547	mac->link.speed = GMAC_CONFIG_FES;
	548	mac->mii.addr = GMAC_MDIO_ADDR;
	549	mac->mii.data = GMAC_MDIO_DATA;
b91dce4c LC	550	mac->mii.addr_shift = 21;
	551	mac->mii.addr_mask = GENMASK(25, 21);
	552	mac->mii.reg_shift = 16;
	553	mac->mii.reg_mask = GENMASK(20, 16);
	554	mac->mii.clk_csr_shift = 8;
	555	mac->mii.clk_csr_mask = GENMASK(11, 8);
477286b5 AT	556
	557	/* Get and dump the chip ID */
	558	*synopsys_id = stmmac_get_synopsys_id(hwid);
	559
	560	if (*synopsys_id > DWMAC_CORE_4_00)
	561	mac->dma = &dwmac410_dma_ops;
	562	else
	563	mac->dma = &dwmac4_dma_ops;
	564
	565	return mac;
	566	}