[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_core.c

/*
 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
 * DWC Ether MAC version 4.00  has been used for developing this code.
 *
 * This only implements the mac core functions for this chip.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/crc32.h>
#include <linux/slab.h>
#include <linux/ethtool.h>
#include <linux/io.h>
#include "stmmac_pcs.h"
#include "dwmac4.h"

static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_CONFIG);

	value |= GMAC_CORE_INIT;

	if (mtu > 1500)
		value |= GMAC_CONFIG_2K;
	if (mtu > 2000)
		value |= GMAC_CONFIG_JE;

	if (hw->ps) {
		value |= GMAC_CONFIG_TE;

		if (hw->ps == SPEED_1000) {
			value &= ~GMAC_CONFIG_PS;
		} else {
			value |= GMAC_CONFIG_PS;

			if (hw->ps == SPEED_10)
				value &= ~GMAC_CONFIG_FES;
			else
				value |= GMAC_CONFIG_FES;
		}
	}

	writel(value, ioaddr + GMAC_CONFIG);

	/* Mask GMAC interrupts */
	value = GMAC_INT_DEFAULT_MASK;
	if (hw->pmt)
		value |= GMAC_INT_PMT_EN;
	if (hw->pcs)
		value |= GMAC_PCS_IRQ_DEFAULT;

	writel(value, ioaddr + GMAC_INT_EN);
}

static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
				   u8 mode, u32 queue)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);

	value &= GMAC_RX_QUEUE_CLEAR(queue);
	if (mode == MTL_RX_AVB)
		value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
	else if (mode == MTL_RX_DCB)
		value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);

	writel(value, ioaddr + GMAC_RXQ_CTRL0);
}

static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
					  u32 rx_alg)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MTL_OPERATION_MODE);

	value &= ~MTL_OPERATION_RAA;
	switch (rx_alg) {
	case MTL_RX_ALGORITHM_SP:
		value |= MTL_OPERATION_RAA_SP;
		break;
	case MTL_RX_ALGORITHM_WSP:
		value |= MTL_OPERATION_RAA_WSP;
		break;
	default:
		break;
	}

	writel(value, ioaddr + MTL_OPERATION_MODE);
}

static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
					  u32 tx_alg)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MTL_OPERATION_MODE);

	value &= ~MTL_OPERATION_SCHALG_MASK;
	switch (tx_alg) {
	case MTL_TX_ALGORITHM_WRR:
		value |= MTL_OPERATION_SCHALG_WRR;
		break;
	case MTL_TX_ALGORITHM_WFQ:
		value |= MTL_OPERATION_SCHALG_WFQ;
		break;
	case MTL_TX_ALGORITHM_DWRR:
		value |= MTL_OPERATION_SCHALG_DWRR;
		break;
	case MTL_TX_ALGORITHM_SP:
		value |= MTL_OPERATION_SCHALG_SP;
		break;
	default:
		break;
	}
}

static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
					   u32 weight, u32 queue)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));

	value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
	value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
	writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
}

static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	if (queue < 4)
		value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
	else
		value = readl(ioaddr + MTL_RXQ_DMA_MAP1);

	if (queue == 0 || queue == 4) {
		value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
		value |= MTL_RXQ_DMA_Q04MDMACH(chan);
	} else {
		value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
		value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
	}

	if (queue < 4)
		writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
	else
		writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
}

static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
{
	void __iomem *ioaddr = hw->pcsr;
	int i;

	for (i = 0; i < GMAC_REG_NUM; i++)
		reg_space[i] = readl(ioaddr + i * 4);
}

static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + GMAC_CONFIG);

	if (hw->rx_csum)
		value |= GMAC_CONFIG_IPC;
	else
		value &= ~GMAC_CONFIG_IPC;

	writel(value, ioaddr + GMAC_CONFIG);

	value = readl(ioaddr + GMAC_CONFIG);

	return !!(value & GMAC_CONFIG_IPC);
}

static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
{
	void __iomem *ioaddr = hw->pcsr;
	unsigned int pmt = 0;

	if (mode & WAKE_MAGIC) {
		pr_debug("GMAC: WOL Magic frame\n");
		pmt |= power_down | magic_pkt_en;
	}
	if (mode & WAKE_UCAST) {
		pr_debug("GMAC: WOL on global unicast\n");
		pmt |= power_down | global_unicast | wake_up_frame_en;
	}

	writel(pmt, ioaddr + GMAC_PMT);
}

static void dwmac4_set_umac_addr(struct mac_device_info *hw,
				 unsigned char *addr, unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;

	stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				   GMAC_ADDR_LOW(reg_n));
}

static void dwmac4_get_umac_addr(struct mac_device_info *hw,
				 unsigned char *addr, unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;

	stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				   GMAC_ADDR_LOW(reg_n));
}

static void dwmac4_set_eee_mode(struct mac_device_info *hw,
				bool en_tx_lpi_clockgating)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	/* Enable the link status receive on RGMII, SGMII ore SMII
	 * receive path and instruct the transmit to enter in LPI
	 * state.
	 */
	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;

	if (en_tx_lpi_clockgating)
		value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value;

	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);

	if (link)
		value |= GMAC4_LPI_CTRL_STATUS_PLS;
	else
		value &= ~GMAC4_LPI_CTRL_STATUS_PLS;

	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
}

static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
{
	void __iomem *ioaddr = hw->pcsr;
	int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);

	/* Program the timers in the LPI timer control register:
	 * LS: minimum time (ms) for which the link
	 *  status from PHY should be ok before transmitting
	 *  the LPI pattern.
	 * TW: minimum time (us) for which the core waits
	 *  after it has stopped transmitting the LPI pattern.
	 */
	writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
}

static void dwmac4_set_filter(struct mac_device_info *hw,
			      struct net_device *dev)
{
	void __iomem *ioaddr = (void __iomem *)dev->base_addr;
	unsigned int value = 0;

	if (dev->flags & IFF_PROMISC) {
		value = GMAC_PACKET_FILTER_PR;
	} else if ((dev->flags & IFF_ALLMULTI) ||
			(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
		/* Pass all multi */
		value = GMAC_PACKET_FILTER_PM;
		/* Set the 64 bits of the HASH tab. To be updated if taller
		 * hash table is used
		 */
		writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
		writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
	} else if (!netdev_mc_empty(dev)) {
		u32 mc_filter[2];
		struct netdev_hw_addr *ha;

		/* Hash filter for multicast */
		value = GMAC_PACKET_FILTER_HMC;

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the content of the Hash Table Reg 0 and 1.
			 */
			int bit_nr =
				(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
			/* The most significant bit determines the register
			 * to use while the other 5 bits determines the bit
			 * within the selected register
			 */
			mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
		}
		writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
		writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
	}

	/* Handle multiple unicast addresses */
	if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
		/* Switch to promiscuous mode if more than 128 addrs
		 * are required
		 */
		value |= GMAC_PACKET_FILTER_PR;
	} else if (!netdev_uc_empty(dev)) {
		int reg = 1;
		struct netdev_hw_addr *ha;

		netdev_for_each_uc_addr(ha, dev) {
			dwmac4_set_umac_addr(hw, ha->addr, reg);
			reg++;
		}
	}

	writel(value, ioaddr + GMAC_PACKET_FILTER);
}

static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
			     unsigned int fc, unsigned int pause_time)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 channel = STMMAC_CHAN0;	/* FIXME */
	unsigned int flow = 0;

	pr_debug("GMAC Flow-Control:\n");
	if (fc & FLOW_RX) {
		pr_debug("\tReceive Flow-Control ON\n");
		flow |= GMAC_RX_FLOW_CTRL_RFE;
		writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
	}
	if (fc & FLOW_TX) {
		pr_debug("\tTransmit Flow-Control ON\n");
		flow |= GMAC_TX_FLOW_CTRL_TFE;
		writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));

		if (duplex) {
			pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
			flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
			writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
		}
	}
}

static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
			    bool loopback)
{
	dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
}

static void dwmac4_rane(void __iomem *ioaddr, bool restart)
{
	dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
}

static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
{
	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
}

/* RGMII or SMII interface */
static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
{
	u32 status;

	status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
	x->irq_rgmii_n++;

	/* Check the link status */
	if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
		int speed_value;

		x->pcs_link = 1;

		speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
			       GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
		if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
			x->pcs_speed = SPEED_1000;
		else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
			x->pcs_speed = SPEED_100;
		else
			x->pcs_speed = SPEED_10;

		x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);

		pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
			x->pcs_duplex ? "Full" : "Half");
	} else {
		x->pcs_link = 0;
		pr_info("Link is Down\n");
	}
}

static int dwmac4_irq_status(struct mac_device_info *hw,
			     struct stmmac_extra_stats *x)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 mtl_int_qx_status;
	u32 intr_status;
	int ret = 0;

	intr_status = readl(ioaddr + GMAC_INT_STATUS);

	/* Not used events (e.g. MMC interrupts) are not handled. */
	if ((intr_status & mmc_tx_irq))
		x->mmc_tx_irq_n++;
	if (unlikely(intr_status & mmc_rx_irq))
		x->mmc_rx_irq_n++;
	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
		x->mmc_rx_csum_offload_irq_n++;
	/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
	if (unlikely(intr_status & pmt_irq)) {
		readl(ioaddr + GMAC_PMT);
		x->irq_receive_pmt_irq_n++;
	}

	mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
	/* Check MTL Interrupt: Currently only one queue is used: Q0. */
	if (mtl_int_qx_status & MTL_INT_Q0) {
		/* read Queue 0 Interrupt status */
		u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));

		if (status & MTL_RX_OVERFLOW_INT) {
			/*  clear Interrupt */
			writel(status | MTL_RX_OVERFLOW_INT,
			       ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
			ret = CORE_IRQ_MTL_RX_OVERFLOW;
		}
	}

	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
	if (intr_status & PCS_RGSMIIIS_IRQ)
		dwmac4_phystatus(ioaddr, x);

	return ret;
}

static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x)
{
	u32 value;

	/*  Currently only channel 0 is supported */
	value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));

	if (value & MTL_DEBUG_TXSTSFSTS)
		x->mtl_tx_status_fifo_full++;
	if (value & MTL_DEBUG_TXFSTS)
		x->mtl_tx_fifo_not_empty++;
	if (value & MTL_DEBUG_TWCSTS)
		x->mmtl_fifo_ctrl++;
	if (value & MTL_DEBUG_TRCSTS_MASK) {
		u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
			     >> MTL_DEBUG_TRCSTS_SHIFT;
		if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
			x->mtl_tx_fifo_read_ctrl_write++;
		else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
			x->mtl_tx_fifo_read_ctrl_wait++;
		else if (trcsts == MTL_DEBUG_TRCSTS_READ)
			x->mtl_tx_fifo_read_ctrl_read++;
		else
			x->mtl_tx_fifo_read_ctrl_idle++;
	}
	if (value & MTL_DEBUG_TXPAUSED)
		x->mac_tx_in_pause++;

	value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));

	if (value & MTL_DEBUG_RXFSTS_MASK) {
		u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
			     >> MTL_DEBUG_RRCSTS_SHIFT;

		if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
			x->mtl_rx_fifo_fill_level_full++;
		else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
			x->mtl_rx_fifo_fill_above_thresh++;
		else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
			x->mtl_rx_fifo_fill_below_thresh++;
		else
			x->mtl_rx_fifo_fill_level_empty++;
	}
	if (value & MTL_DEBUG_RRCSTS_MASK) {
		u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
			     MTL_DEBUG_RRCSTS_SHIFT;

		if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
			x->mtl_rx_fifo_read_ctrl_flush++;
		else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
			x->mtl_rx_fifo_read_ctrl_read_data++;
		else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
			x->mtl_rx_fifo_read_ctrl_status++;
		else
			x->mtl_rx_fifo_read_ctrl_idle++;
	}
	if (value & MTL_DEBUG_RWCSTS)
		x->mtl_rx_fifo_ctrl_active++;

	/* GMAC debug */
	value = readl(ioaddr + GMAC_DEBUG);

	if (value & GMAC_DEBUG_TFCSTS_MASK) {
		u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
			      >> GMAC_DEBUG_TFCSTS_SHIFT;

		if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
			x->mac_tx_frame_ctrl_xfer++;
		else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
			x->mac_tx_frame_ctrl_pause++;
		else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
			x->mac_tx_frame_ctrl_wait++;
		else
			x->mac_tx_frame_ctrl_idle++;
	}
	if (value & GMAC_DEBUG_TPESTS)
		x->mac_gmii_tx_proto_engine++;
	if (value & GMAC_DEBUG_RFCFCSTS_MASK)
		x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
					    >> GMAC_DEBUG_RFCFCSTS_SHIFT;
	if (value & GMAC_DEBUG_RPESTS)
		x->mac_gmii_rx_proto_engine++;
}

static const struct stmmac_ops dwmac4_ops = {
	.core_init = dwmac4_core_init,
	.rx_ipc = dwmac4_rx_ipc_enable,
	.rx_queue_enable = dwmac4_rx_queue_enable,
	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
	.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
	.map_mtl_to_dma = dwmac4_map_mtl_dma,
	.dump_regs = dwmac4_dump_regs,
	.host_irq_status = dwmac4_irq_status,
	.flow_ctrl = dwmac4_flow_ctrl,
	.pmt = dwmac4_pmt,
	.set_umac_addr = dwmac4_set_umac_addr,
	.get_umac_addr = dwmac4_get_umac_addr,
	.set_eee_mode = dwmac4_set_eee_mode,
	.reset_eee_mode = dwmac4_reset_eee_mode,
	.set_eee_timer = dwmac4_set_eee_timer,
	.set_eee_pls = dwmac4_set_eee_pls,
	.pcs_ctrl_ane = dwmac4_ctrl_ane,
	.pcs_rane = dwmac4_rane,
	.pcs_get_adv_lp = dwmac4_get_adv_lp,
	.debug = dwmac4_debug,
	.set_filter = dwmac4_set_filter,
};

struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
				     int perfect_uc_entries, int *synopsys_id)
{
	struct mac_device_info *mac;
	u32 hwid = readl(ioaddr + GMAC_VERSION);

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	if (!mac)
		return NULL;

	mac->pcsr = ioaddr;
	mac->multicast_filter_bins = mcbins;
	mac->unicast_filter_entries = perfect_uc_entries;
	mac->mcast_bits_log2 = 0;

	if (mac->multicast_filter_bins)
		mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);

	mac->mac = &dwmac4_ops;

	mac->link.port = GMAC_CONFIG_PS;
	mac->link.duplex = GMAC_CONFIG_DM;
	mac->link.speed = GMAC_CONFIG_FES;
	mac->mii.addr = GMAC_MDIO_ADDR;
	mac->mii.data = GMAC_MDIO_DATA;
	mac->mii.addr_shift = 21;
	mac->mii.addr_mask = GENMASK(25, 21);
	mac->mii.reg_shift = 16;
	mac->mii.reg_mask = GENMASK(20, 16);
	mac->mii.clk_csr_shift = 8;
	mac->mii.clk_csr_mask = GENMASK(11, 8);

	/* Get and dump the chip ID */
	*synopsys_id = stmmac_get_synopsys_id(hwid);

	if (*synopsys_id > DWMAC_CORE_4_00)
		mac->dma = &dwmac410_dma_ops;
	else
		mac->dma = &dwmac4_dma_ops;

	return mac;
}
Commit	Line	Data
477286b5 AT	1	/*
	2	* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	3	* DWC Ether MAC version 4.00 has been used for developing this code.
	4	*
	5	* This only implements the mac core functions for this chip.
	6	*
	7	* Copyright (C) 2015 STMicroelectronics Ltd
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2, as published by the Free Software Foundation.
	12	*
	13	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	14	*/
	15
	16	#include <linux/crc32.h>
	17	#include <linux/slab.h>
	18	#include <linux/ethtool.h>
	19	#include <linux/io.h>
70523e63	20	#include "stmmac_pcs.h"
477286b5 AT	21	#include "dwmac4.h"
	22
	23	static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
	24	{
	25	void __iomem *ioaddr = hw->pcsr;
	26	u32 value = readl(ioaddr + GMAC_CONFIG);
	27
	28	value \|= GMAC_CORE_INIT;
	29
	30	if (mtu > 1500)
	31	value \|= GMAC_CONFIG_2K;
	32	if (mtu > 2000)
	33	value \|= GMAC_CONFIG_JE;
	34
02e57b9d GC	35	if (hw->ps) {
	36	value \|= GMAC_CONFIG_TE;
	37
	38	if (hw->ps == SPEED_1000) {
	39	value &= ~GMAC_CONFIG_PS;
	40	} else {
	41	value \|= GMAC_CONFIG_PS;
	42
	43	if (hw->ps == SPEED_10)
	44	value &= ~GMAC_CONFIG_FES;
	45	else
	46	value \|= GMAC_CONFIG_FES;
	47	}
	48	}
	49
477286b5 AT	50	writel(value, ioaddr + GMAC_CONFIG);
	51
	52	/* Mask GMAC interrupts */
3fe5cadb GC	53	value = GMAC_INT_DEFAULT_MASK;
	54	if (hw->pmt)
	55	value \|= GMAC_INT_PMT_EN;
	56	if (hw->pcs)
	57	value \|= GMAC_PCS_IRQ_DEFAULT;
	58
	59	writel(value, ioaddr + GMAC_INT_EN);
477286b5 AT	60	}
477286b5 AT	61
4f6046f5 JP	62	static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
4f6046f5 JP	63	u8 mode, u32 queue)
9eb12474	64	{
	65	void __iomem *ioaddr = hw->pcsr;
	66	u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
	67
	68	value &= GMAC_RX_QUEUE_CLEAR(queue);
4f6046f5 JP	69	if (mode == MTL_RX_AVB)
	70	value \|= GMAC_RX_AV_QUEUE_ENABLE(queue);
	71	else if (mode == MTL_RX_DCB)
	72	value \|= GMAC_RX_DCB_QUEUE_ENABLE(queue);
9eb12474	73
	74	writel(value, ioaddr + GMAC_RXQ_CTRL0);
	75	}
	76
d0a9c9f9 JP	77	static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
	78	u32 rx_alg)
	79	{
	80	void __iomem *ioaddr = hw->pcsr;
	81	u32 value = readl(ioaddr + MTL_OPERATION_MODE);
	82
	83	value &= ~MTL_OPERATION_RAA;
	84	switch (rx_alg) {
	85	case MTL_RX_ALGORITHM_SP:
	86	value \|= MTL_OPERATION_RAA_SP;
	87	break;
	88	case MTL_RX_ALGORITHM_WSP:
	89	value \|= MTL_OPERATION_RAA_WSP;
	90	break;
	91	default:
	92	break;
	93	}
	94
	95	writel(value, ioaddr + MTL_OPERATION_MODE);
	96	}
	97
	98	static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
	99	u32 tx_alg)
	100	{
	101	void __iomem *ioaddr = hw->pcsr;
	102	u32 value = readl(ioaddr + MTL_OPERATION_MODE);
	103
	104	value &= ~MTL_OPERATION_SCHALG_MASK;
	105	switch (tx_alg) {
	106	case MTL_TX_ALGORITHM_WRR:
	107	value \|= MTL_OPERATION_SCHALG_WRR;
	108	break;
	109	case MTL_TX_ALGORITHM_WFQ:
	110	value \|= MTL_OPERATION_SCHALG_WFQ;
	111	break;
	112	case MTL_TX_ALGORITHM_DWRR:
	113	value \|= MTL_OPERATION_SCHALG_DWRR;
	114	break;
	115	case MTL_TX_ALGORITHM_SP:
	116	value \|= MTL_OPERATION_SCHALG_SP;
	117	break;
	118	default:
	119	break;
	120	}
	121	}
	122
6a3a7193 JP	123	static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
	124	u32 weight, u32 queue)
	125	{
	126	void __iomem *ioaddr = hw->pcsr;
	127	u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
	128
	129	value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
	130	value \|= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
	131	writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
	132	}
	133
d43042f4 JP	134	static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
	135	{
	136	void __iomem *ioaddr = hw->pcsr;
	137	u32 value;
	138
	139	if (queue < 4)
	140	value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
	141	else
	142	value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
	143
	144	if (queue == 0 \|\| queue == 4) {
	145	value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
	146	value \|= MTL_RXQ_DMA_Q04MDMACH(chan);
	147	} else {
	148	value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
	149	value \|= MTL_RXQ_DMA_QXMDMACH(chan, queue);
	150	}
	151
	152	if (queue < 4)
	153	writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
	154	else
	155	writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
	156	}
	157
fbf68229	158	static void dwmac4_dump_regs(struct mac_device_info hw, u32 reg_space)
477286b5 AT	159	{
	160	void __iomem *ioaddr = hw->pcsr;
	161	int i;
	162
fbf68229 LC	163	for (i = 0; i < GMAC_REG_NUM; i++)
fbf68229 LC	164	reg_space[i] = readl(ioaddr + i * 4);
477286b5 AT	165	}
	166
	167	static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
	168	{
	169	void __iomem *ioaddr = hw->pcsr;
	170	u32 value = readl(ioaddr + GMAC_CONFIG);
	171
	172	if (hw->rx_csum)
	173	value \|= GMAC_CONFIG_IPC;
	174	else
	175	value &= ~GMAC_CONFIG_IPC;
	176
	177	writel(value, ioaddr + GMAC_CONFIG);
	178
	179	value = readl(ioaddr + GMAC_CONFIG);
	180
	181	return !!(value & GMAC_CONFIG_IPC);
	182	}
	183
	184	static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
	185	{
	186	void __iomem *ioaddr = hw->pcsr;
	187	unsigned int pmt = 0;
	188
	189	if (mode & WAKE_MAGIC) {
	190	pr_debug("GMAC: WOL Magic frame\n");
	191	pmt \|= power_down \| magic_pkt_en;
	192	}
	193	if (mode & WAKE_UCAST) {
	194	pr_debug("GMAC: WOL on global unicast\n");
19cd1203	195	pmt \|= power_down \| global_unicast \| wake_up_frame_en;
477286b5 AT	196	}
	197
	198	writel(pmt, ioaddr + GMAC_PMT);
	199	}
	200
	201	static void dwmac4_set_umac_addr(struct mac_device_info *hw,
	202	unsigned char *addr, unsigned int reg_n)
	203	{
	204	void __iomem *ioaddr = hw->pcsr;
	205
	206	stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	207	GMAC_ADDR_LOW(reg_n));
	208	}
	209
	210	static void dwmac4_get_umac_addr(struct mac_device_info *hw,
	211	unsigned char *addr, unsigned int reg_n)
	212	{
	213	void __iomem *ioaddr = hw->pcsr;
	214
	215	stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	216	GMAC_ADDR_LOW(reg_n));
	217	}
	218
b4b7b772	219	static void dwmac4_set_eee_mode(struct mac_device_info *hw,
b4b7b772	220	bool en_tx_lpi_clockgating)
afbb1674	221	{
	222	void __iomem *ioaddr = hw->pcsr;
	223	u32 value;
	224
	225	/* Enable the link status receive on RGMII, SGMII ore SMII
	226	* receive path and instruct the transmit to enter in LPI
	227	* state.
	228	*/
	229	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	230	value \|= GMAC4_LPI_CTRL_STATUS_LPIEN \| GMAC4_LPI_CTRL_STATUS_LPITXA;
	231
b4b7b772	232	if (en_tx_lpi_clockgating)
	233	value \|= GMAC4_LPI_CTRL_STATUS_LPITCSE;
	234
afbb1674	235	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	236	}
	237
	238	static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
	239	{
	240	void __iomem *ioaddr = hw->pcsr;
	241	u32 value;
	242
	243	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	244	value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN \| GMAC4_LPI_CTRL_STATUS_LPITXA);
	245	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	246	}
	247
	248	static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
	249	{
	250	void __iomem *ioaddr = hw->pcsr;
	251	u32 value;
	252
	253	value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
	254
	255	if (link)
	256	value \|= GMAC4_LPI_CTRL_STATUS_PLS;
	257	else
	258	value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
	259
	260	writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
	261	}
	262
	263	static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
	264	{
	265	void __iomem *ioaddr = hw->pcsr;
f4ec6064	266	int value = ((tw & 0xffff)) \| ((ls & 0x3ff) << 16);
afbb1674	267
	268	/* Program the timers in the LPI timer control register:
	269	* LS: minimum time (ms) for which the link
	270	* status from PHY should be ok before transmitting
	271	* the LPI pattern.
	272	* TW: minimum time (us) for which the core waits
	273	* after it has stopped transmitting the LPI pattern.
	274	*/
	275	writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
	276	}
	277
477286b5 AT	278	static void dwmac4_set_filter(struct mac_device_info *hw,
	279	struct net_device *dev)
	280	{
	281	void __iomem ioaddr = (void __iomem )dev->base_addr;
	282	unsigned int value = 0;
	283
	284	if (dev->flags & IFF_PROMISC) {
	285	value = GMAC_PACKET_FILTER_PR;
	286	} else if ((dev->flags & IFF_ALLMULTI) \|\|
	287	(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
	288	/* Pass all multi */
	289	value = GMAC_PACKET_FILTER_PM;
	290	/* Set the 64 bits of the HASH tab. To be updated if taller
	291	* hash table is used
	292	*/
	293	writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
	294	writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
	295	} else if (!netdev_mc_empty(dev)) {
	296	u32 mc_filter[2];
	297	struct netdev_hw_addr *ha;
	298
	299	/* Hash filter for multicast */
	300	value = GMAC_PACKET_FILTER_HMC;
	301
	302	memset(mc_filter, 0, sizeof(mc_filter));
	303	netdev_for_each_mc_addr(ha, dev) {
	304	/* The upper 6 bits of the calculated CRC are used to
	305	* index the content of the Hash Table Reg 0 and 1.
	306	*/
	307	int bit_nr =
	308	(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
	309	/* The most significant bit determines the register
	310	* to use while the other 5 bits determines the bit
	311	* within the selected register
	312	*/
	313	mc_filter[bit_nr >> 5] \|= (1 << (bit_nr & 0x1F));
	314	}
	315	writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
	316	writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
	317	}
	318
	319	/* Handle multiple unicast addresses */
	320	if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
	321	/* Switch to promiscuous mode if more than 128 addrs
	322	* are required
	323	*/
	324	value \|= GMAC_PACKET_FILTER_PR;
	325	} else if (!netdev_uc_empty(dev)) {
	326	int reg = 1;
	327	struct netdev_hw_addr *ha;
	328
	329	netdev_for_each_uc_addr(ha, dev) {
ca8bdaf1	330	dwmac4_set_umac_addr(hw, ha->addr, reg);
477286b5 AT	331	reg++;
	332	}
	333	}
	334
	335	writel(value, ioaddr + GMAC_PACKET_FILTER);
	336	}
	337
	338	static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
	339	unsigned int fc, unsigned int pause_time)
	340	{
	341	void __iomem *ioaddr = hw->pcsr;
	342	u32 channel = STMMAC_CHAN0; /* FIXME */
	343	unsigned int flow = 0;
	344
	345	pr_debug("GMAC Flow-Control:\n");
	346	if (fc & FLOW_RX) {
	347	pr_debug("\tReceive Flow-Control ON\n");
	348	flow \|= GMAC_RX_FLOW_CTRL_RFE;
	349	writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
	350	}
	351	if (fc & FLOW_TX) {
	352	pr_debug("\tTransmit Flow-Control ON\n");
	353	flow \|= GMAC_TX_FLOW_CTRL_TFE;
	354	writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
	355
	356	if (duplex) {
	357	pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
	358	flow \|= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
	359	writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel));
	360	}
	361	}
	362	}
	363
70523e63 GC	364	static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
70523e63 GC	365	bool loopback)
477286b5	366	{
70523e63 GC	367	dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
70523e63 GC	368	}
477286b5	369
70523e63 GC	370	static void dwmac4_rane(void __iomem *ioaddr, bool restart)
	371	{
	372	dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
	373	}
477286b5	374
70523e63 GC	375	static void dwmac4_get_adv_lp(void __iomem ioaddr, struct rgmii_adv adv)
	376	{
	377	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
477286b5 AT	378	}
477286b5 AT	379
70523e63 GC	380	/* RGMII or SMII interface */
70523e63 GC	381	static void dwmac4_phystatus(void __iomem ioaddr, struct stmmac_extra_stats x)
477286b5	382	{
70523e63	383	u32 status;
477286b5	384
70523e63 GC	385	status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
70523e63 GC	386	x->irq_rgmii_n++;
477286b5	387
70523e63 GC	388	/* Check the link status */
	389	if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
	390	int speed_value;
477286b5	391
70523e63	392	x->pcs_link = 1;
477286b5	393
70523e63 GC	394	speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
	395	GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
	396	if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
	397	x->pcs_speed = SPEED_1000;
	398	else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
	399	x->pcs_speed = SPEED_100;
	400	else
	401	x->pcs_speed = SPEED_10;
	402
	403	x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
477286b5	404
70523e63 GC	405	pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
	406	x->pcs_duplex ? "Full" : "Half");
	407	} else {
	408	x->pcs_link = 0;
	409	pr_info("Link is Down\n");
	410	}
477286b5 AT	411	}
	412
	413	static int dwmac4_irq_status(struct mac_device_info *hw,
	414	struct stmmac_extra_stats *x)
	415	{
	416	void __iomem *ioaddr = hw->pcsr;
	417	u32 mtl_int_qx_status;
	418	u32 intr_status;
	419	int ret = 0;
	420
	421	intr_status = readl(ioaddr + GMAC_INT_STATUS);
	422
	423	/* Not used events (e.g. MMC interrupts) are not handled. */
	424	if ((intr_status & mmc_tx_irq))
	425	x->mmc_tx_irq_n++;
	426	if (unlikely(intr_status & mmc_rx_irq))
	427	x->mmc_rx_irq_n++;
	428	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
	429	x->mmc_rx_csum_offload_irq_n++;
	430	/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
	431	if (unlikely(intr_status & pmt_irq)) {
	432	readl(ioaddr + GMAC_PMT);
	433	x->irq_receive_pmt_irq_n++;
	434	}
	435
477286b5 AT	436	mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
	437	/* Check MTL Interrupt: Currently only one queue is used: Q0. */
	438	if (mtl_int_qx_status & MTL_INT_Q0) {
	439	/* read Queue 0 Interrupt status */
	440	u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
	441
	442	if (status & MTL_RX_OVERFLOW_INT) {
	443	/* clear Interrupt */
	444	writel(status \| MTL_RX_OVERFLOW_INT,
	445	ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0));
	446	ret = CORE_IRQ_MTL_RX_OVERFLOW;
	447	}
	448	}
	449
70523e63 GC	450	dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
	451	if (intr_status & PCS_RGSMIIIS_IRQ)
	452	dwmac4_phystatus(ioaddr, x);
	453
477286b5 AT	454	return ret;
	455	}
	456
	457	static void dwmac4_debug(void __iomem ioaddr, struct stmmac_extra_stats x)
	458	{
	459	u32 value;
	460
	461	/* Currently only channel 0 is supported */
	462	value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0));
	463
	464	if (value & MTL_DEBUG_TXSTSFSTS)
	465	x->mtl_tx_status_fifo_full++;
	466	if (value & MTL_DEBUG_TXFSTS)
	467	x->mtl_tx_fifo_not_empty++;
	468	if (value & MTL_DEBUG_TWCSTS)
	469	x->mmtl_fifo_ctrl++;
	470	if (value & MTL_DEBUG_TRCSTS_MASK) {
	471	u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
	472	>> MTL_DEBUG_TRCSTS_SHIFT;
	473	if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
	474	x->mtl_tx_fifo_read_ctrl_write++;
	475	else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
	476	x->mtl_tx_fifo_read_ctrl_wait++;
	477	else if (trcsts == MTL_DEBUG_TRCSTS_READ)
	478	x->mtl_tx_fifo_read_ctrl_read++;
	479	else
	480	x->mtl_tx_fifo_read_ctrl_idle++;
	481	}
	482	if (value & MTL_DEBUG_TXPAUSED)
	483	x->mac_tx_in_pause++;
	484
	485	value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0));
	486
	487	if (value & MTL_DEBUG_RXFSTS_MASK) {
	488	u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
	489	>> MTL_DEBUG_RRCSTS_SHIFT;
	490
	491	if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
	492	x->mtl_rx_fifo_fill_level_full++;
	493	else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
	494	x->mtl_rx_fifo_fill_above_thresh++;
	495	else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
	496	x->mtl_rx_fifo_fill_below_thresh++;
	497	else
	498	x->mtl_rx_fifo_fill_level_empty++;
	499	}
	500	if (value & MTL_DEBUG_RRCSTS_MASK) {
	501	u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
	502	MTL_DEBUG_RRCSTS_SHIFT;
	503
	504	if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
	505	x->mtl_rx_fifo_read_ctrl_flush++;
	506	else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
	507	x->mtl_rx_fifo_read_ctrl_read_data++;
	508	else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
	509	x->mtl_rx_fifo_read_ctrl_status++;
	510	else
	511	x->mtl_rx_fifo_read_ctrl_idle++;
	512	}
	513	if (value & MTL_DEBUG_RWCSTS)
	514	x->mtl_rx_fifo_ctrl_active++;
	515
	516	/* GMAC debug */
	517	value = readl(ioaddr + GMAC_DEBUG);
518
519	if (value & GMAC_DEBUG_TFCSTS_MASK) {
520	u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
521	>> GMAC_DEBUG_TFCSTS_SHIFT;
522
523	if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
524	x->mac_tx_frame_ctrl_xfer++;
525	else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
526	x->mac_tx_frame_ctrl_pause++;
527	else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
528	x->mac_tx_frame_ctrl_wait++;
529	else
530	x->mac_tx_frame_ctrl_idle++;
531	}
532	if (value & GMAC_DEBUG_TPESTS)
533	x->mac_gmii_tx_proto_engine++;
534	if (value & GMAC_DEBUG_RFCFCSTS_MASK)
535	x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
536	>> GMAC_DEBUG_RFCFCSTS_SHIFT;
537	if (value & GMAC_DEBUG_RPESTS)
538	x->mac_gmii_rx_proto_engine++;
539	}
540
541	static const struct stmmac_ops dwmac4_ops = {
542	.core_init = dwmac4_core_init,
543	.rx_ipc = dwmac4_rx_ipc_enable,
9eb12474	544	.rx_queue_enable = dwmac4_rx_queue_enable,
d0a9c9f9 JP	545	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
d0a9c9f9 JP	546	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
6a3a7193	547	.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
d43042f4	548	.map_mtl_to_dma = dwmac4_map_mtl_dma,
477286b5 AT	549	.dump_regs = dwmac4_dump_regs,
	550	.host_irq_status = dwmac4_irq_status,
	551	.flow_ctrl = dwmac4_flow_ctrl,
	552	.pmt = dwmac4_pmt,
	553	.set_umac_addr = dwmac4_set_umac_addr,
	554	.get_umac_addr = dwmac4_get_umac_addr,
afbb1674	555	.set_eee_mode = dwmac4_set_eee_mode,
	556	.reset_eee_mode = dwmac4_reset_eee_mode,
	557	.set_eee_timer = dwmac4_set_eee_timer,
	558	.set_eee_pls = dwmac4_set_eee_pls,
70523e63 GC	559	.pcs_ctrl_ane = dwmac4_ctrl_ane,
	560	.pcs_rane = dwmac4_rane,
	561	.pcs_get_adv_lp = dwmac4_get_adv_lp,
477286b5 AT	562	.debug = dwmac4_debug,
	563	.set_filter = dwmac4_set_filter,
	564	};
	565
	566	struct mac_device_info dwmac4_setup(void __iomem ioaddr, int mcbins,
	567	int perfect_uc_entries, int *synopsys_id)
	568	{
	569	struct mac_device_info *mac;
	570	u32 hwid = readl(ioaddr + GMAC_VERSION);
	571
	572	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	573	if (!mac)
	574	return NULL;
	575
	576	mac->pcsr = ioaddr;
	577	mac->multicast_filter_bins = mcbins;
	578	mac->unicast_filter_entries = perfect_uc_entries;
	579	mac->mcast_bits_log2 = 0;
	580
	581	if (mac->multicast_filter_bins)
	582	mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
	583
	584	mac->mac = &dwmac4_ops;
	585
	586	mac->link.port = GMAC_CONFIG_PS;
	587	mac->link.duplex = GMAC_CONFIG_DM;
	588	mac->link.speed = GMAC_CONFIG_FES;
	589	mac->mii.addr = GMAC_MDIO_ADDR;
	590	mac->mii.data = GMAC_MDIO_DATA;
b91dce4c LC	591	mac->mii.addr_shift = 21;
	592	mac->mii.addr_mask = GENMASK(25, 21);
	593	mac->mii.reg_shift = 16;
	594	mac->mii.reg_mask = GENMASK(20, 16);
	595	mac->mii.clk_csr_shift = 8;
	596	mac->mii.clk_csr_mask = GENMASK(11, 8);
477286b5 AT	597
	598	/* Get and dump the chip ID */
	599	*synopsys_id = stmmac_get_synopsys_id(hwid);
	600
	601	if (*synopsys_id > DWMAC_CORE_4_00)
	602	mac->dma = &dwmac410_dma_ops;
	603	else
	604	mac->dma = &dwmac4_dma_ops;
	605
	606	return mac;
	607	}