[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / stmicro / stmmac / enh_desc.c

/*******************************************************************************
  This contains the functions to handle the enhanced descriptors.

  Copyright (C) 2007-2014  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/stmmac.h>
#include "common.h"
#include "descs_com.h"

static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x,
				  struct dma_desc *p, void __iomem *ioaddr)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	unsigned int tdes0 = p->des0;
	int ret = tx_done;

	/* Get tx owner first */
	if (unlikely(tdes0 & ETDES0_OWN))
		return tx_dma_own;

	/* Verify tx error by looking at the last segment. */
	if (likely(!(tdes0 & ETDES0_LAST_SEGMENT)))
		return tx_not_ls;

	if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) {
		if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT))
			x->tx_jabber++;

		if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) {
			x->tx_frame_flushed++;
			dwmac_dma_flush_tx_fifo(ioaddr);
		}

		if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) {
			x->tx_losscarrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely(tdes0 & ETDES0_NO_CARRIER)) {
			x->tx_carrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely((tdes0 & ETDES0_LATE_COLLISION) ||
			     (tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
			stats->collisions +=
				(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;

		if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
			x->tx_deferred++;

		if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) {
			dwmac_dma_flush_tx_fifo(ioaddr);
			x->tx_underflow++;
		}

		if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR))
			x->tx_ip_header_error++;

		if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) {
			x->tx_payload_error++;
			dwmac_dma_flush_tx_fifo(ioaddr);
		}

		ret = tx_err;
	}

	if (unlikely(tdes0 & ETDES0_DEFERRED))
		x->tx_deferred++;

#ifdef STMMAC_VLAN_TAG_USED
	if (tdes0 & ETDES0_VLAN_FRAME)
		x->tx_vlan++;
#endif

	return ret;
}

static int enh_desc_get_tx_len(struct dma_desc *p)
{
	return (p->des1 & ETDES1_BUFFER1_SIZE_MASK);
}

static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
{
	int ret = good_frame;
	u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;

	/* bits 5 7 0 | Frame status
	 * ----------------------------------------------------------
	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
	 *      1 0 0 | IPv4/6 No CSUM errorS.
	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
	 *      1 1 0 | IPv4/6 CSUM IP HR error
	 *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD
	 *      0 1 1 | COE bypassed.. no IPv4/6 frame
	 *      0 1 0 | Reserved.
	 */
	if (status == 0x0)
		ret = llc_snap;
	else if (status == 0x4)
		ret = good_frame;
	else if (status == 0x5)
		ret = csum_none;
	else if (status == 0x6)
		ret = csum_none;
	else if (status == 0x7)
		ret = csum_none;
	else if (status == 0x1)
		ret = discard_frame;
	else if (status == 0x3)
		ret = discard_frame;
	return ret;
}

static void enh_desc_get_ext_status(void *data, struct stmmac_extra_stats *x,
				    struct dma_extended_desc *p)
{
	unsigned int rdes0 = p->basic.des0;
	unsigned int rdes4 = p->des4;

	if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
		int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;

		if (rdes4 & ERDES4_IP_HDR_ERR)
			x->ip_hdr_err++;
		if (rdes4 & ERDES4_IP_PAYLOAD_ERR)
			x->ip_payload_err++;
		if (rdes4 & ERDES4_IP_CSUM_BYPASSED)
			x->ip_csum_bypassed++;
		if (rdes4 & ERDES4_IPV4_PKT_RCVD)
			x->ipv4_pkt_rcvd++;
		if (rdes4 & ERDES4_IPV6_PKT_RCVD)
			x->ipv6_pkt_rcvd++;

		if (message_type == RDES_EXT_NO_PTP)
			x->no_ptp_rx_msg_type_ext++;
		else if (message_type == RDES_EXT_SYNC)
			x->ptp_rx_msg_type_sync++;
		else if (message_type == RDES_EXT_FOLLOW_UP)
			x->ptp_rx_msg_type_follow_up++;
		else if (message_type == RDES_EXT_DELAY_REQ)
			x->ptp_rx_msg_type_delay_req++;
		else if (message_type == RDES_EXT_DELAY_RESP)
			x->ptp_rx_msg_type_delay_resp++;
		else if (message_type == RDES_EXT_PDELAY_REQ)
			x->ptp_rx_msg_type_pdelay_req++;
		else if (message_type == RDES_EXT_PDELAY_RESP)
			x->ptp_rx_msg_type_pdelay_resp++;
		else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
			x->ptp_rx_msg_type_pdelay_follow_up++;
		else if (message_type == RDES_PTP_ANNOUNCE)
			x->ptp_rx_msg_type_announce++;
		else if (message_type == RDES_PTP_MANAGEMENT)
			x->ptp_rx_msg_type_management++;
		else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
			x->ptp_rx_msg_pkt_reserved_type++;

		if (rdes4 & ERDES4_PTP_FRAME_TYPE)
			x->ptp_frame_type++;
		if (rdes4 & ERDES4_PTP_VER)
			x->ptp_ver++;
		if (rdes4 & ERDES4_TIMESTAMP_DROPPED)
			x->timestamp_dropped++;
		if (rdes4 & ERDES4_AV_PKT_RCVD)
			x->av_pkt_rcvd++;
		if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
			x->av_tagged_pkt_rcvd++;
		if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
			x->vlan_tag_priority_val++;
		if (rdes4 & ERDES4_L3_FILTER_MATCH)
			x->l3_filter_match++;
		if (rdes4 & ERDES4_L4_FILTER_MATCH)
			x->l4_filter_match++;
		if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
			x->l3_l4_filter_no_match++;
	}
}

static int enh_desc_get_rx_status(void *data, struct stmmac_extra_stats *x,
				  struct dma_desc *p)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	unsigned int rdes0 = p->des0;
	int ret = good_frame;

	if (unlikely(rdes0 & RDES0_OWN))
		return dma_own;

	if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
		if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {
			x->rx_desc++;
			stats->rx_length_errors++;
		}
		if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
			x->rx_gmac_overflow++;

		if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
			pr_err("\tIPC Csum Error/Giant frame\n");

		if (unlikely(rdes0 & RDES0_COLLISION))
			stats->collisions++;
		if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG))
			x->rx_watchdog++;

		if (unlikely(rdes0 & RDES0_MII_ERROR))	/* GMII */
			x->rx_mii++;

		if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
			x->rx_crc++;
			stats->rx_crc_errors++;
		}
		ret = discard_frame;
	}

	/* After a payload csum error, the ES bit is set.
	 * It doesn't match with the information reported into the databook.
	 * At any rate, we need to understand if the CSUM hw computation is ok
	 * and report this info to the upper layers. */
	ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
				 !!(rdes0 & RDES0_FRAME_TYPE),
				 !!(rdes0 & ERDES0_RX_MAC_ADDR));

	if (unlikely(rdes0 & RDES0_DRIBBLING))
		x->dribbling_bit++;

	if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) {
		x->sa_rx_filter_fail++;
		ret = discard_frame;
	}
	if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) {
		x->da_rx_filter_fail++;
		ret = discard_frame;
	}
	if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
		x->rx_length++;
		ret = discard_frame;
	}
#ifdef STMMAC_VLAN_TAG_USED
	if (rdes0 & RDES0_VLAN_TAG)
		x->rx_vlan++;
#endif

	return ret;
}

static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
				  int mode, int end)
{
	p->des0 |= RDES0_OWN;
	p->des1 |= ((BUF_SIZE_8KiB - 1) & ERDES1_BUFFER1_SIZE_MASK);

	if (mode == STMMAC_CHAIN_MODE)
		ehn_desc_rx_set_on_chain(p);
	else
		ehn_desc_rx_set_on_ring(p, end);

	if (disable_rx_ic)
		p->des1 |= ERDES1_DISABLE_IC;
}

static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)
{
	p->des0 &= ~ETDES0_OWN;
	if (mode == STMMAC_CHAIN_MODE)
		enh_desc_end_tx_desc_on_chain(p);
	else
		enh_desc_end_tx_desc_on_ring(p, end);
}

static int enh_desc_get_tx_owner(struct dma_desc *p)
{
	return (p->des0 & ETDES0_OWN) >> 31;
}

static void enh_desc_set_tx_owner(struct dma_desc *p)
{
	p->des0 |= ETDES0_OWN;
}

static void enh_desc_set_rx_owner(struct dma_desc *p)
{
	p->des0 |= RDES0_OWN;
}

static int enh_desc_get_tx_ls(struct dma_desc *p)
{
	return (p->des0 & ETDES0_LAST_SEGMENT) >> 29;
}

static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
{
	int ter = (p->des0 & ETDES0_END_RING) >> 21;

	memset(p, 0, offsetof(struct dma_desc, des2));
	if (mode == STMMAC_CHAIN_MODE)
		enh_desc_end_tx_desc_on_chain(p);
	else
		enh_desc_end_tx_desc_on_ring(p, ter);
}

static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
				     bool csum_flag, int mode, bool tx_own,
				     bool ls)
{
	unsigned int tdes0 = p->des0;

	if (mode == STMMAC_CHAIN_MODE)
		enh_set_tx_desc_len_on_chain(p, len);
	else
		enh_set_tx_desc_len_on_ring(p, len);

	if (is_fs)
		tdes0 |= ETDES0_FIRST_SEGMENT;
	else
		tdes0 &= ~ETDES0_FIRST_SEGMENT;

	if (likely(csum_flag))
		tdes0 |= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
	else
		tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);

	if (ls)
		tdes0 |= ETDES0_LAST_SEGMENT;

	/* Finally set the OWN bit. Later the DMA will start! */
	if (tx_own)
		tdes0 |= ETDES0_OWN;

	if (is_fs & tx_own)
		/* When the own bit, for the first frame, has to be set, all
		 * descriptors for the same frame has to be set before, to
		 * avoid race condition.
		 */
		wmb();

	p->des0 = tdes0;
}

static void enh_desc_set_tx_ic(struct dma_desc *p)
{
	p->des0 |= ETDES0_INTERRUPT;
}

static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
{
	unsigned int csum = 0;
	/* The type-1 checksum offload engines append the checksum at
	 * the end of frame and the two bytes of checksum are added in
	 * the length.
	 * Adjust for that in the framelen for type-1 checksum offload
	 * engines.
	 */
	if (rx_coe_type == STMMAC_RX_COE_TYPE1)
		csum = 2;

	return (((p->des0 & RDES0_FRAME_LEN_MASK) >> RDES0_FRAME_LEN_SHIFT) -
		csum);
}

static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
{
	p->des0 |= ETDES0_TIME_STAMP_ENABLE;
}

static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)
{
	return (p->des0 & ETDES0_TIME_STAMP_STATUS) >> 17;
}

static u64 enh_desc_get_timestamp(void *desc, u32 ats)
{
	u64 ns;

	if (ats) {
		struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
		ns = p->des6;
		/* convert high/sec time stamp value to nanosecond */
		ns += p->des7 * 1000000000ULL;
	} else {
		struct dma_desc *p = (struct dma_desc *)desc;
		ns = p->des2;
		ns += p->des3 * 1000000000ULL;
	}

	return ns;
}

static int enh_desc_get_rx_timestamp_status(void *desc, u32 ats)
{
	if (ats) {
		struct dma_extended_desc *p = (struct dma_extended_desc *)desc;
		return (p->basic.des0 & RDES0_IPC_CSUM_ERROR) >> 7;
	} else {
		struct dma_desc *p = (struct dma_desc *)desc;
		if ((p->des2 == 0xffffffff) && (p->des3 == 0xffffffff))
			/* timestamp is corrupted, hence don't store it */
			return 0;
		else
			return 1;
	}
}

static void enh_desc_display_ring(void *head, unsigned int size, bool rx)
{
	struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
	int i;

	pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX");

	for (i = 0; i < size; i++) {
		u64 x;

		x = *(u64 *)ep;
		pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
			i, (unsigned int)virt_to_phys(ep),
			(unsigned int)x, (unsigned int)(x >> 32),
			ep->basic.des2, ep->basic.des3);
		ep++;
	}
	pr_info("\n");
}

const struct stmmac_desc_ops enh_desc_ops = {
	.tx_status = enh_desc_get_tx_status,
	.rx_status = enh_desc_get_rx_status,
	.get_tx_len = enh_desc_get_tx_len,
	.init_rx_desc = enh_desc_init_rx_desc,
	.init_tx_desc = enh_desc_init_tx_desc,
	.get_tx_owner = enh_desc_get_tx_owner,
	.release_tx_desc = enh_desc_release_tx_desc,
	.prepare_tx_desc = enh_desc_prepare_tx_desc,
	.set_tx_ic = enh_desc_set_tx_ic,
	.get_tx_ls = enh_desc_get_tx_ls,
	.set_tx_owner = enh_desc_set_tx_owner,
	.set_rx_owner = enh_desc_set_rx_owner,
	.get_rx_frame_len = enh_desc_get_rx_frame_len,
	.rx_extended_status = enh_desc_get_ext_status,
	.enable_tx_timestamp = enh_desc_enable_tx_timestamp,
	.get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,
	.get_timestamp = enh_desc_get_timestamp,
	.get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,
	.display_ring = enh_desc_display_ring,
};
Commit	Line	Data
56b106ae GC	1	/*******************************************************************************
	2	This contains the functions to handle the enhanced descriptors.
	3
293e4365	4	Copyright (C) 2007-2014 STMicroelectronics Ltd
56b106ae GC	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	23	*******************************************************************************/
	24
38912bdb	25	#include <linux/stmmac.h>
56b106ae	26	#include "common.h"
286a8372	27	#include "descs_com.h"
56b106ae GC	28
56b106ae GC	29	static int enh_desc_get_tx_status(void data, struct stmmac_extra_stats x,
ad01b7d4	30	struct dma_desc p, void __iomem ioaddr)
56b106ae	31	{
56b106ae	32	struct net_device_stats stats = (struct net_device_stats )data;
293e4365	33	unsigned int tdes0 = p->des0;
c363b658 FG	34	int ret = tx_done;
	35
	36	/* Get tx owner first */
	37	if (unlikely(tdes0 & ETDES0_OWN))
	38	return tx_dma_own;
	39
	40	/* Verify tx error by looking at the last segment. */
	41	if (likely(!(tdes0 & ETDES0_LAST_SEGMENT)))
	42	return tx_not_ls;
56b106ae	43
293e4365 GC	44	if (unlikely(tdes0 & ETDES0_ERROR_SUMMARY)) {
293e4365 GC	45	if (unlikely(tdes0 & ETDES0_JABBER_TIMEOUT))
56b106ae	46	x->tx_jabber++;
56b106ae	47
293e4365	48	if (unlikely(tdes0 & ETDES0_FRAME_FLUSHED)) {
56b106ae	49	x->tx_frame_flushed++;
688911c2	50	dwmac_dma_flush_tx_fifo(ioaddr);
56b106ae GC	51	}
56b106ae GC	52
293e4365	53	if (unlikely(tdes0 & ETDES0_LOSS_CARRIER)) {
56b106ae GC	54	x->tx_losscarrier++;
	55	stats->tx_carrier_errors++;
	56	}
293e4365	57	if (unlikely(tdes0 & ETDES0_NO_CARRIER)) {
56b106ae GC	58	x->tx_carrier++;
	59	stats->tx_carrier_errors++;
	60	}
293e4365 GC	61	if (unlikely((tdes0 & ETDES0_LATE_COLLISION) \|\|
	62	(tdes0 & ETDES0_EXCESSIVE_COLLISIONS)))
	63	stats->collisions +=
	64	(tdes0 & ETDES0_COLLISION_COUNT_MASK) >> 3;
83d7af64	65
293e4365	66	if (unlikely(tdes0 & ETDES0_EXCESSIVE_DEFERRAL))
56b106ae	67	x->tx_deferred++;
56b106ae	68
293e4365	69	if (unlikely(tdes0 & ETDES0_UNDERFLOW_ERROR)) {
688911c2	70	dwmac_dma_flush_tx_fifo(ioaddr);
56b106ae GC	71	x->tx_underflow++;
	72	}
	73
293e4365	74	if (unlikely(tdes0 & ETDES0_IP_HEADER_ERROR))
56b106ae	75	x->tx_ip_header_error++;
56b106ae	76
293e4365	77	if (unlikely(tdes0 & ETDES0_PAYLOAD_ERROR)) {
56b106ae	78	x->tx_payload_error++;
688911c2	79	dwmac_dma_flush_tx_fifo(ioaddr);
56b106ae GC	80	}
56b106ae GC	81
c363b658	82	ret = tx_err;
56b106ae GC	83	}
56b106ae GC	84
293e4365	85	if (unlikely(tdes0 & ETDES0_DEFERRED))
56b106ae	86	x->tx_deferred++;
83d7af64	87
56b106ae	88	#ifdef STMMAC_VLAN_TAG_USED
293e4365	89	if (tdes0 & ETDES0_VLAN_FRAME)
56b106ae	90	x->tx_vlan++;
56b106ae GC	91	#endif
	92
	93	return ret;
	94	}
	95
	96	static int enh_desc_get_tx_len(struct dma_desc *p)
	97	{
293e4365	98	return (p->des1 & ETDES1_BUFFER1_SIZE_MASK);
56b106ae GC	99	}
	100
	101	static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
	102	{
	103	int ret = good_frame;
	104	u32 status = (type << 2 \| ipc_err << 1 \| payload_err) & 0x7;
	105
	106	/* bits 5 7 0 \| Frame status
	107	* ----------------------------------------------------------
	108	* 0 0 0 \| IEEE 802.3 Type frame (length < 1536 octects)
	109	* 1 0 0 \| IPv4/6 No CSUM errorS.
	110	* 1 0 1 \| IPv4/6 CSUM PAYLOAD error
	111	* 1 1 0 \| IPv4/6 CSUM IP HR error
	112	* 1 1 1 \| IPv4/6 IP PAYLOAD AND HEADER errorS
	113	* 0 0 1 \| IPv4/6 unsupported IP PAYLOAD
	114	* 0 1 1 \| COE bypassed.. no IPv4/6 frame
	115	* 0 1 0 \| Reserved.
	116	*/
83d7af64	117	if (status == 0x0)
3eeb2997	118	ret = llc_snap;
83d7af64	119	else if (status == 0x4)
56b106ae	120	ret = good_frame;
83d7af64	121	else if (status == 0x5)
56b106ae	122	ret = csum_none;
83d7af64	123	else if (status == 0x6)
56b106ae	124	ret = csum_none;
83d7af64	125	else if (status == 0x7)
56b106ae	126	ret = csum_none;
83d7af64	127	else if (status == 0x1)
56b106ae	128	ret = discard_frame;
83d7af64	129	else if (status == 0x3)
56b106ae	130	ret = discard_frame;
56b106ae GC	131	return ret;
	132	}
	133
c24602ef GC	134	static void enh_desc_get_ext_status(void data, struct stmmac_extra_stats x,
	135	struct dma_extended_desc *p)
	136	{
293e4365 GC	137	unsigned int rdes0 = p->basic.des0;
	138	unsigned int rdes4 = p->des4;
	139
	140	if (unlikely(rdes0 & ERDES0_RX_MAC_ADDR)) {
	141	int message_type = (rdes4 & ERDES4_MSG_TYPE_MASK) >> 8;
	142
	143	if (rdes4 & ERDES4_IP_HDR_ERR)
c24602ef	144	x->ip_hdr_err++;
293e4365	145	if (rdes4 & ERDES4_IP_PAYLOAD_ERR)
c24602ef	146	x->ip_payload_err++;
293e4365	147	if (rdes4 & ERDES4_IP_CSUM_BYPASSED)
c24602ef	148	x->ip_csum_bypassed++;
293e4365	149	if (rdes4 & ERDES4_IPV4_PKT_RCVD)
c24602ef	150	x->ipv4_pkt_rcvd++;
293e4365	151	if (rdes4 & ERDES4_IPV6_PKT_RCVD)
c24602ef	152	x->ipv6_pkt_rcvd++;
ee112c12 GC	153
	154	if (message_type == RDES_EXT_NO_PTP)
	155	x->no_ptp_rx_msg_type_ext++;
	156	else if (message_type == RDES_EXT_SYNC)
	157	x->ptp_rx_msg_type_sync++;
293e4365	158	else if (message_type == RDES_EXT_FOLLOW_UP)
ee112c12	159	x->ptp_rx_msg_type_follow_up++;
293e4365	160	else if (message_type == RDES_EXT_DELAY_REQ)
ee112c12	161	x->ptp_rx_msg_type_delay_req++;
293e4365	162	else if (message_type == RDES_EXT_DELAY_RESP)
ee112c12	163	x->ptp_rx_msg_type_delay_resp++;
293e4365	164	else if (message_type == RDES_EXT_PDELAY_REQ)
ee112c12	165	x->ptp_rx_msg_type_pdelay_req++;
293e4365	166	else if (message_type == RDES_EXT_PDELAY_RESP)
ee112c12	167	x->ptp_rx_msg_type_pdelay_resp++;
293e4365	168	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
ee112c12 GC	169	x->ptp_rx_msg_type_pdelay_follow_up++;
	170	else if (message_type == RDES_PTP_ANNOUNCE)
	171	x->ptp_rx_msg_type_announce++;
	172	else if (message_type == RDES_PTP_MANAGEMENT)
	173	x->ptp_rx_msg_type_management++;
	174	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
	175	x->ptp_rx_msg_pkt_reserved_type++;
	176
293e4365	177	if (rdes4 & ERDES4_PTP_FRAME_TYPE)
c24602ef	178	x->ptp_frame_type++;
293e4365	179	if (rdes4 & ERDES4_PTP_VER)
c24602ef	180	x->ptp_ver++;
293e4365	181	if (rdes4 & ERDES4_TIMESTAMP_DROPPED)
c24602ef	182	x->timestamp_dropped++;
293e4365	183	if (rdes4 & ERDES4_AV_PKT_RCVD)
c24602ef	184	x->av_pkt_rcvd++;
293e4365	185	if (rdes4 & ERDES4_AV_TAGGED_PKT_RCVD)
c24602ef	186	x->av_tagged_pkt_rcvd++;
293e4365	187	if ((rdes4 & ERDES4_VLAN_TAG_PRI_VAL_MASK) >> 18)
c24602ef	188	x->vlan_tag_priority_val++;
293e4365	189	if (rdes4 & ERDES4_L3_FILTER_MATCH)
c24602ef	190	x->l3_filter_match++;
293e4365	191	if (rdes4 & ERDES4_L4_FILTER_MATCH)
c24602ef	192	x->l4_filter_match++;
293e4365	193	if ((rdes4 & ERDES4_L3_L4_FILT_NO_MATCH_MASK) >> 26)
c24602ef GC	194	x->l3_l4_filter_no_match++;
	195	}
	196	}
	197
56b106ae GC	198	static int enh_desc_get_rx_status(void data, struct stmmac_extra_stats x,
	199	struct dma_desc *p)
	200	{
56b106ae	201	struct net_device_stats stats = (struct net_device_stats )data;
293e4365 GC	202	unsigned int rdes0 = p->des0;
293e4365 GC	203	int ret = good_frame;
56b106ae	204
c1fa3212 FG	205	if (unlikely(rdes0 & RDES0_OWN))
	206	return dma_own;
	207
293e4365 GC	208	if (unlikely(rdes0 & RDES0_ERROR_SUMMARY)) {
293e4365 GC	209	if (unlikely(rdes0 & RDES0_DESCRIPTOR_ERROR)) {
56b106ae GC	210	x->rx_desc++;
	211	stats->rx_length_errors++;
	212	}
293e4365	213	if (unlikely(rdes0 & RDES0_OVERFLOW_ERROR))
56b106ae	214	x->rx_gmac_overflow++;
56b106ae	215
293e4365	216	if (unlikely(rdes0 & RDES0_IPC_CSUM_ERROR))
83d7af64	217	pr_err("\tIPC Csum Error/Giant frame\n");
56b106ae	218
293e4365	219	if (unlikely(rdes0 & RDES0_COLLISION))
56b106ae	220	stats->collisions++;
293e4365	221	if (unlikely(rdes0 & RDES0_RECEIVE_WATCHDOG))
56b106ae	222	x->rx_watchdog++;
83d7af64	223
293e4365	224	if (unlikely(rdes0 & RDES0_MII_ERROR)) /* GMII */
56b106ae	225	x->rx_mii++;
83d7af64	226
293e4365	227	if (unlikely(rdes0 & RDES0_CRC_ERROR)) {
56b106ae GC	228	x->rx_crc++;
	229	stats->rx_crc_errors++;
	230	}
	231	ret = discard_frame;
	232	}
	233
	234	/* After a payload csum error, the ES bit is set.
	235	* It doesn't match with the information reported into the databook.
	236	* At any rate, we need to understand if the CSUM hw computation is ok
	237	* and report this info to the upper layers. */
293e4365 GC	238	ret = enh_desc_coe_rdes0(!!(rdes0 & RDES0_IPC_CSUM_ERROR),
	239	!!(rdes0 & RDES0_FRAME_TYPE),
	240	!!(rdes0 & ERDES0_RX_MAC_ADDR));
56b106ae	241
293e4365	242	if (unlikely(rdes0 & RDES0_DRIBBLING))
1cc5a735	243	x->dribbling_bit++;
83d7af64	244
293e4365	245	if (unlikely(rdes0 & RDES0_SA_FILTER_FAIL)) {
56b106ae GC	246	x->sa_rx_filter_fail++;
	247	ret = discard_frame;
	248	}
293e4365	249	if (unlikely(rdes0 & RDES0_DA_FILTER_FAIL)) {
56b106ae GC	250	x->da_rx_filter_fail++;
	251	ret = discard_frame;
	252	}
293e4365	253	if (unlikely(rdes0 & RDES0_LENGTH_ERROR)) {
56b106ae GC	254	x->rx_length++;
	255	ret = discard_frame;
	256	}
	257	#ifdef STMMAC_VLAN_TAG_USED
293e4365	258	if (rdes0 & RDES0_VLAN_TAG)
56b106ae	259	x->rx_vlan++;
56b106ae	260	#endif
c24602ef	261
56b106ae GC	262	return ret;
	263	}
	264
c24602ef GC	265	static void enh_desc_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
c24602ef GC	266	int mode, int end)
56b106ae	267	{
293e4365 GC	268	p->des0 \|= RDES0_OWN;
293e4365 GC	269	p->des1 \|= ((BUF_SIZE_8KiB - 1) & ERDES1_BUFFER1_SIZE_MASK);
286a8372	270
c24602ef	271	if (mode == STMMAC_CHAIN_MODE)
293e4365	272	ehn_desc_rx_set_on_chain(p);
c24602ef GC	273	else
c24602ef GC	274	ehn_desc_rx_set_on_ring(p, end);
286a8372	275
c24602ef	276	if (disable_rx_ic)
293e4365	277	p->des1 \|= ERDES1_DISABLE_IC;
56b106ae GC	278	}
56b106ae GC	279
c24602ef	280	static void enh_desc_init_tx_desc(struct dma_desc *p, int mode, int end)
56b106ae	281	{
293e4365	282	p->des0 &= ~ETDES0_OWN;
c24602ef	283	if (mode == STMMAC_CHAIN_MODE)
293e4365	284	enh_desc_end_tx_desc_on_chain(p);
c24602ef	285	else
293e4365	286	enh_desc_end_tx_desc_on_ring(p, end);
56b106ae GC	287	}
	288
	289	static int enh_desc_get_tx_owner(struct dma_desc *p)
	290	{
293e4365	291	return (p->des0 & ETDES0_OWN) >> 31;
56b106ae GC	292	}
56b106ae GC	293
56b106ae GC	294	static void enh_desc_set_tx_owner(struct dma_desc *p)
56b106ae GC	295	{
293e4365	296	p->des0 \|= ETDES0_OWN;
56b106ae GC	297	}
	298
	299	static void enh_desc_set_rx_owner(struct dma_desc *p)
	300	{
293e4365	301	p->des0 \|= RDES0_OWN;
56b106ae GC	302	}
	303
	304	static int enh_desc_get_tx_ls(struct dma_desc *p)
	305	{
293e4365	306	return (p->des0 & ETDES0_LAST_SEGMENT) >> 29;
56b106ae GC	307	}
56b106ae GC	308
4a7d666a	309	static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
56b106ae	310	{
293e4365	311	int ter = (p->des0 & ETDES0_END_RING) >> 21;
56b106ae	312
b71c7aaa	313	memset(p, 0, offsetof(struct dma_desc, des2));
4a7d666a	314	if (mode == STMMAC_CHAIN_MODE)
293e4365	315	enh_desc_end_tx_desc_on_chain(p);
4a7d666a GC	316	else
4a7d666a GC	317	enh_desc_end_tx_desc_on_ring(p, ter);
56b106ae GC	318	}
	319
	320	static void enh_desc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
be434d50	321	bool csum_flag, int mode, bool tx_own,
0e80bdc9	322	bool ls)
56b106ae	323	{
293e4365 GC	324	unsigned int tdes0 = p->des0;
293e4365 GC	325
0e80bdc9 GC	326	if (mode == STMMAC_CHAIN_MODE)
	327	enh_set_tx_desc_len_on_chain(p, len);
	328	else
	329	enh_set_tx_desc_len_on_ring(p, len);
	330
293e4365 GC	331	if (is_fs)
	332	tdes0 \|= ETDES0_FIRST_SEGMENT;
	333	else
	334	tdes0 &= ~ETDES0_FIRST_SEGMENT;
	335
	336	if (likely(csum_flag))
	337	tdes0 \|= (TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
	338	else
	339	tdes0 &= ~(TX_CIC_FULL << ETDES0_CHECKSUM_INSERTION_SHIFT);
	340
0e80bdc9 GC	341	if (ls)
	342	tdes0 \|= ETDES0_LAST_SEGMENT;
	343
	344	/* Finally set the OWN bit. Later the DMA will start! */
be434d50 GC	345	if (tx_own)
	346	tdes0 \|= ETDES0_OWN;
	347
	348	if (is_fs & tx_own)
	349	/* When the own bit, for the first frame, has to be set, all
	350	* descriptors for the same frame has to be set before, to
	351	* avoid race condition.
	352	*/
	353	wmb();
	354
293e4365	355	p->des0 = tdes0;
56b106ae GC	356	}
56b106ae GC	357
0e80bdc9	358	static void enh_desc_set_tx_ic(struct dma_desc *p)
56b106ae	359	{
0e80bdc9	360	p->des0 \|= ETDES0_INTERRUPT;
56b106ae GC	361	}
56b106ae GC	362
38912bdb	363	static int enh_desc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
56b106ae	364	{
293e4365	365	unsigned int csum = 0;
38912bdb DS	366	/* The type-1 checksum offload engines append the checksum at
	367	* the end of frame and the two bytes of checksum are added in
	368	* the length.
	369	* Adjust for that in the framelen for type-1 checksum offload
293e4365 GC	370	* engines.
293e4365 GC	371	*/
38912bdb	372	if (rx_coe_type == STMMAC_RX_COE_TYPE1)
293e4365 GC	373	csum = 2;
	374
	375	return (((p->des0 & RDES0_FRAME_LEN_MASK) >> RDES0_FRAME_LEN_SHIFT) -
	376	csum);
56b106ae GC	377	}
56b106ae GC	378
891434b1 RK	379	static void enh_desc_enable_tx_timestamp(struct dma_desc *p)
891434b1 RK	380	{
293e4365	381	p->des0 \|= ETDES0_TIME_STAMP_ENABLE;
891434b1 RK	382	}
	383
	384	static int enh_desc_get_tx_timestamp_status(struct dma_desc *p)
	385	{
293e4365	386	return (p->des0 & ETDES0_TIME_STAMP_STATUS) >> 17;
891434b1 RK	387	}
	388
	389	static u64 enh_desc_get_timestamp(void *desc, u32 ats)
	390	{
	391	u64 ns;
	392
	393	if (ats) {
	394	struct dma_extended_desc p = (struct dma_extended_desc )desc;
	395	ns = p->des6;
	396	/* convert high/sec time stamp value to nanosecond */
	397	ns += p->des7 * 1000000000ULL;
	398	} else {
	399	struct dma_desc p = (struct dma_desc )desc;
	400	ns = p->des2;
	401	ns += p->des3 * 1000000000ULL;
	402	}
	403
	404	return ns;
	405	}
	406
	407	static int enh_desc_get_rx_timestamp_status(void *desc, u32 ats)
	408	{
	409	if (ats) {
	410	struct dma_extended_desc p = (struct dma_extended_desc )desc;
293e4365	411	return (p->basic.des0 & RDES0_IPC_CSUM_ERROR) >> 7;
891434b1 RK	412	} else {
	413	struct dma_desc p = (struct dma_desc )desc;
	414	if ((p->des2 == 0xffffffff) && (p->des3 == 0xffffffff))
	415	/* timestamp is corrupted, hence don't store it */
	416	return 0;
	417	else
	418	return 1;
	419	}
	420	}
	421
d0225e7d AT	422	static void enh_desc_display_ring(void *head, unsigned int size, bool rx)
	423	{
	424	struct dma_extended_desc ep = (struct dma_extended_desc )head;
	425	int i;
	426
	427	pr_info("Extended %s descriptor ring:\n", rx ? "RX" : "TX");
	428
	429	for (i = 0; i < size; i++) {
	430	u64 x;
	431
	432	x = (u64 )ep;
	433	pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
	434	i, (unsigned int)virt_to_phys(ep),
	435	(unsigned int)x, (unsigned int)(x >> 32),
	436	ep->basic.des2, ep->basic.des3);
	437	ep++;
	438	}
	439	pr_info("\n");
	440	}
	441
cadb7924	442	const struct stmmac_desc_ops enh_desc_ops = {
56b106ae GC	443	.tx_status = enh_desc_get_tx_status,
	444	.rx_status = enh_desc_get_rx_status,
	445	.get_tx_len = enh_desc_get_tx_len,
	446	.init_rx_desc = enh_desc_init_rx_desc,
	447	.init_tx_desc = enh_desc_init_tx_desc,
	448	.get_tx_owner = enh_desc_get_tx_owner,
56b106ae GC	449	.release_tx_desc = enh_desc_release_tx_desc,
56b106ae GC	450	.prepare_tx_desc = enh_desc_prepare_tx_desc,
0e80bdc9	451	.set_tx_ic = enh_desc_set_tx_ic,
56b106ae GC	452	.get_tx_ls = enh_desc_get_tx_ls,
	453	.set_tx_owner = enh_desc_set_tx_owner,
	454	.set_rx_owner = enh_desc_set_rx_owner,
	455	.get_rx_frame_len = enh_desc_get_rx_frame_len,
c24602ef	456	.rx_extended_status = enh_desc_get_ext_status,
891434b1 RK	457	.enable_tx_timestamp = enh_desc_enable_tx_timestamp,
	458	.get_tx_timestamp_status = enh_desc_get_tx_timestamp_status,
	459	.get_timestamp = enh_desc_get_timestamp,
	460	.get_rx_timestamp_status = enh_desc_get_rx_timestamp_status,
d0225e7d	461	.display_ring = enh_desc_display_ring,
56b106ae	462	};