[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / stmicro / stmmac / stmmac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************
  Copyright (C) 2007-2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_H__
#define __STMMAC_H__

#define STMMAC_RESOURCE_NAME   "stmmaceth"
#define DRV_MODULE_VERSION	"Jan_2016"

#include <linux/clk.h>
#include <linux/stmmac.h>
#include <linux/phy.h>
#include <linux/pci.h>
#include "common.h"
#include <linux/ptp_clock_kernel.h>
#include <linux/net_tstamp.h>
#include <linux/reset.h>

struct stmmac_resources {
	void __iomem *addr;
	const char *mac;
	int wol_irq;
	int lpi_irq;
	int irq;
};

struct stmmac_tx_info {
	dma_addr_t buf;
	bool map_as_page;
	unsigned len;
	bool last_segment;
	bool is_jumbo;
};

/* Frequently used values are kept adjacent for cache effect */
struct stmmac_tx_queue {
	u32 tx_count_frames;
	struct timer_list txtimer;
	u32 queue_index;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
	struct dma_desc *dma_tx;
	struct sk_buff **tx_skbuff;
	struct stmmac_tx_info *tx_skbuff_dma;
	unsigned int cur_tx;
	unsigned int dirty_tx;
	dma_addr_t dma_tx_phy;
	u32 tx_tail_addr;
	u32 mss;
};

struct stmmac_rx_queue {
	u32 queue_index;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_erx;
	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
	struct sk_buff **rx_skbuff;
	dma_addr_t *rx_skbuff_dma;
	unsigned int cur_rx;
	unsigned int dirty_rx;
	u32 rx_zeroc_thresh;
	dma_addr_t dma_rx_phy;
	u32 rx_tail_addr;
};

struct stmmac_channel {
	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
	struct stmmac_priv *priv_data;
	u32 index;
};

struct stmmac_tc_entry {
	bool in_use;
	bool in_hw;
	bool is_last;
	bool is_frag;
	void *frag_ptr;
	unsigned int table_pos;
	u32 handle;
	u32 prio;
	struct {
		u32 match_data;
		u32 match_en;
		u8 af:1;
		u8 rf:1;
		u8 im:1;
		u8 nc:1;
		u8 res1:4;
		u8 frame_offset;
		u8 ok_index;
		u8 dma_ch_no;
		u32 res2;
	} __packed val;
};

#define STMMAC_PPS_MAX		4
struct stmmac_pps_cfg {
	bool available;
	struct timespec64 start;
	struct timespec64 period;
};

struct stmmac_priv {
	/* Frequently used values are kept adjacent for cache effect */
	u32 tx_coal_frames;
	u32 tx_coal_timer;

	int tx_coalesce;
	int hwts_tx_en;
	bool tx_path_in_lpi_mode;
	bool tso;

	unsigned int dma_buf_sz;
	unsigned int rx_copybreak;
	u32 rx_riwt;
	int hwts_rx_en;

	void __iomem *ioaddr;
	struct net_device *dev;
	struct device *device;
	struct mac_device_info *hw;
	int (*hwif_quirks)(struct stmmac_priv *priv);
	struct mutex lock;

	/* RX Queue */
	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];

	/* TX Queue */
	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];

	/* Generic channel for NAPI */
	struct stmmac_channel channel[STMMAC_CH_MAX];

	bool oldlink;
	int speed;
	int oldduplex;
	unsigned int flow_ctrl;
	unsigned int pause;
	struct mii_bus *mii;
	int mii_irq[PHY_MAX_ADDR];

	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
	struct stmmac_safety_stats sstats;
	struct plat_stmmacenet_data *plat;
	struct dma_features dma_cap;
	struct stmmac_counters mmc;
	int hw_cap_support;
	int synopsys_id;
	u32 msg_enable;
	int wolopts;
	int wol_irq;
	int clk_csr;
	struct timer_list eee_ctrl_timer;
	int lpi_irq;
	int eee_enabled;
	int eee_active;
	int tx_lpi_timer;
	unsigned int mode;
	unsigned int chain_mode;
	int extend_desc;
	struct hwtstamp_config tstamp_config;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_clock_ops;
	unsigned int default_addend;
	u32 sub_second_inc;
	u32 systime_flags;
	u32 adv_ts;
	int use_riwt;
	int irq_wake;
	spinlock_t ptp_lock;
	void __iomem *mmcaddr;
	void __iomem *ptpaddr;

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbgfs_dir;
	struct dentry *dbgfs_rings_status;
	struct dentry *dbgfs_dma_cap;
#endif

	unsigned long state;
	struct workqueue_struct *wq;
	struct work_struct service_task;

	/* TC Handling */
	unsigned int tc_entries_max;
	unsigned int tc_off_max;
	struct stmmac_tc_entry *tc_entries;

	/* Pulse Per Second output */
	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
};

enum stmmac_state {
	STMMAC_DOWN,
	STMMAC_RESET_REQUESTED,
	STMMAC_RESETING,
	STMMAC_SERVICE_SCHED,
};

int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
void stmmac_set_ethtool_ops(struct net_device *netdev);

void stmmac_ptp_register(struct stmmac_priv *priv);
void stmmac_ptp_unregister(struct stmmac_priv *priv);
int stmmac_resume(struct device *dev);
int stmmac_suspend(struct device *dev);
int stmmac_dvr_remove(struct device *dev);
int stmmac_dvr_probe(struct device *device,
		     struct plat_stmmacenet_data *plat_dat,
		     struct stmmac_resources *res);
void stmmac_disable_eee_mode(struct stmmac_priv *priv);
bool stmmac_eee_init(struct stmmac_priv *priv);

#endif /* __STMMAC_H__ */
Commit	Line	Data
4fa9c49f	1	/* SPDX-License-Identifier: GPL-2.0-only */
47dd7a54 GC	2	/*******************************************************************************
	3	Copyright (C) 2007-2009 STMicroelectronics Ltd
	4
47dd7a54 GC	5
	6	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	7	*******************************************************************************/
	8
bd4242df RK	9	#ifndef __STMMAC_H__
	10	#define __STMMAC_H__
	11
bfab27a1	12	#define STMMAC_RESOURCE_NAME "stmmaceth"
06bce7dd	13	#define DRV_MODULE_VERSION "Jan_2016"
ba1377ff GC	14
ba1377ff GC	15	#include <linux/clk.h>
ee7946a7	16	#include <linux/stmmac.h>
286a8372	17	#include <linux/phy.h>
33d5e332	18	#include <linux/pci.h>
47dd7a54	19	#include "common.h"
92ba6888	20	#include <linux/ptp_clock_kernel.h>
d6228b7c	21	#include <linux/net_tstamp.h>
c5e4ddbd	22	#include <linux/reset.h>
47dd7a54	23
e56788cf JE	24	struct stmmac_resources {
	25	void __iomem *addr;
	26	const char *mac;
	27	int wol_irq;
	28	int lpi_irq;
	29	int irq;
	30	};
	31
362b37be GC	32	struct stmmac_tx_info {
	33	dma_addr_t buf;
	34	bool map_as_page;
553e2ab3	35	unsigned len;
2a6d8e17	36	bool last_segment;
96951366	37	bool is_jumbo;
362b37be GC	38	};
362b37be GC	39
ce736788 JP	40	/* Frequently used values are kept adjacent for cache effect */
ce736788 JP	41	struct stmmac_tx_queue {
8fce3331 JA	42	u32 tx_count_frames;
8fce3331 JA	43	struct timer_list txtimer;
ce736788 JP	44	u32 queue_index;
	45	struct stmmac_priv *priv_data;
	46	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
	47	struct dma_desc *dma_tx;
	48	struct sk_buff **tx_skbuff;
	49	struct stmmac_tx_info *tx_skbuff_dma;
	50	unsigned int cur_tx;
	51	unsigned int dirty_tx;
	52	dma_addr_t dma_tx_phy;
	53	u32 tx_tail_addr;
8d212a9e	54	u32 mss;
ce736788 JP	55	};
ce736788 JP	56
54139cf3 JP	57	struct stmmac_rx_queue {
	58	u32 queue_index;
	59	struct stmmac_priv *priv_data;
	60	struct dma_extended_desc *dma_erx;
	61	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
	62	struct sk_buff **rx_skbuff;
	63	dma_addr_t *rx_skbuff_dma;
	64	unsigned int cur_rx;
	65	unsigned int dirty_rx;
	66	u32 rx_zeroc_thresh;
	67	dma_addr_t dma_rx_phy;
	68	u32 rx_tail_addr;
8fce3331 JA	69	};
	70
	71	struct stmmac_channel {
4ccb4585 JA	72	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
4ccb4585 JA	73	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
8fce3331 JA	74	struct stmmac_priv *priv_data;
8fce3331 JA	75	u32 index;
54139cf3 JP	76	};
54139cf3 JP	77
4dbbe8dd JA	78	struct stmmac_tc_entry {
	79	bool in_use;
	80	bool in_hw;
	81	bool is_last;
	82	bool is_frag;
	83	void *frag_ptr;
	84	unsigned int table_pos;
	85	u32 handle;
	86	u32 prio;
	87	struct {
	88	u32 match_data;
	89	u32 match_en;
	90	u8 af:1;
	91	u8 rf:1;
	92	u8 im:1;
	93	u8 nc:1;
	94	u8 res1:4;
	95	u8 frame_offset;
	96	u8 ok_index;
	97	u8 dma_ch_no;
	98	u32 res2;
	99	} __packed val;
	100	};
	101
9a8a02c9 JA	102	#define STMMAC_PPS_MAX 4
	103	struct stmmac_pps_cfg {
	104	bool available;
	105	struct timespec64 start;
	106	struct timespec64 period;
	107	};
	108
47dd7a54 GC	109	struct stmmac_priv {
47dd7a54 GC	110	/* Frequently used values are kept adjacent for cache effect */
1bb6dea8 GC	111	u32 tx_coal_frames;
1bb6dea8 GC	112	u32 tx_coal_timer;
ce736788	113
47dd7a54	114	int tx_coalesce;
1bb6dea8	115	int hwts_tx_en;
1bb6dea8	116	bool tx_path_in_lpi_mode;
f748be53	117	bool tso;
47dd7a54	118
1bb6dea8	119	unsigned int dma_buf_sz;
22ad3838	120	unsigned int rx_copybreak;
1bb6dea8 GC	121	u32 rx_riwt;
1bb6dea8 GC	122	int hwts_rx_en;
5bacd778	123
1bb6dea8	124	void __iomem *ioaddr;
47dd7a54	125	struct net_device *dev;
47dd7a54	126	struct device *device;
db98a0b0	127	struct mac_device_info *hw;
7cfde0af	128	int (hwif_quirks)(struct stmmac_priv priv);
29555fa3	129	struct mutex lock;
47dd7a54	130
54139cf3 JP	131	/* RX Queue */
	132	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
	133
ce736788 JP	134	/* TX Queue */
	135	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
	136
8fce3331 JA	137	/* Generic channel for NAPI */
	138	struct stmmac_channel channel[STMMAC_CH_MAX];
	139
4d869b03	140	bool oldlink;
47dd7a54 GC	141	int speed;
	142	int oldduplex;
	143	unsigned int flow_ctrl;
	144	unsigned int pause;
	145	struct mii_bus *mii;
36bcfe7d	146	int mii_irq[PHY_MAX_ADDR];
47dd7a54	147
1bb6dea8	148	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
8bf993a5	149	struct stmmac_safety_stats sstats;
9dfeb4d9	150	struct plat_stmmacenet_data *plat;
e7434821	151	struct dma_features dma_cap;
1bb6dea8	152	struct stmmac_counters mmc;
19e30c14	153	int hw_cap_support;
1bb6dea8 GC	154	int synopsys_id;
	155	u32 msg_enable;
	156	int wolopts;
	157	int wol_irq;
cd7201f4	158	int clk_csr;
d765955d	159	struct timer_list eee_ctrl_timer;
d765955d GC	160	int lpi_irq;
	161	int eee_enabled;
	162	int eee_active;
	163	int tx_lpi_timer;
4a7d666a	164	unsigned int mode;
5f0456b4	165	unsigned int chain_mode;
c24602ef	166	int extend_desc;
d6228b7c	167	struct hwtstamp_config tstamp_config;
92ba6888 RK	168	struct ptp_clock *ptp_clock;
92ba6888 RK	169	struct ptp_clock_info ptp_clock_ops;
1bb6dea8	170	unsigned int default_addend;
9a8a02c9 JA	171	u32 sub_second_inc;
9a8a02c9 JA	172	u32 systime_flags;
1bb6dea8 GC	173	u32 adv_ts;
1bb6dea8 GC	174	int use_riwt;
89f7f2cf	175	int irq_wake;
92ba6888	176	spinlock_t ptp_lock;
36ff7c1e	177	void __iomem *mmcaddr;
ba1ffd74	178	void __iomem *ptpaddr;
466c5ac8 MO	179
	180	#ifdef CONFIG_DEBUG_FS
	181	struct dentry *dbgfs_dir;
	182	struct dentry *dbgfs_rings_status;
	183	struct dentry *dbgfs_dma_cap;
	184	#endif
34877a15 JA	185
	186	unsigned long state;
	187	struct workqueue_struct *wq;
	188	struct work_struct service_task;
4dbbe8dd JA	189
	190	/* TC Handling */
	191	unsigned int tc_entries_max;
	192	unsigned int tc_off_max;
	193	struct stmmac_tc_entry *tc_entries;
9a8a02c9 JA	194
	195	/* Pulse Per Second output */
	196	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
34877a15 JA	197	};
	198
	199	enum stmmac_state {
	200	STMMAC_DOWN,
	201	STMMAC_RESET_REQUESTED,
	202	STMMAC_RESETING,
	203	STMMAC_SERVICE_SCHED,
47dd7a54 GC	204	};
47dd7a54 GC	205
d6cc64ef JP	206	int stmmac_mdio_unregister(struct net_device *ndev);
d6cc64ef JP	207	int stmmac_mdio_register(struct net_device *ndev);
073752aa	208	int stmmac_mdio_reset(struct mii_bus *mii);
d6cc64ef	209	void stmmac_set_ethtool_ops(struct net_device *netdev);
915af656	210
c30a70d3	211	void stmmac_ptp_register(struct stmmac_priv *priv);
d6cc64ef	212	void stmmac_ptp_unregister(struct stmmac_priv *priv);
f4e7bd81 JE	213	int stmmac_resume(struct device *dev);
	214	int stmmac_suspend(struct device *dev);
	215	int stmmac_dvr_remove(struct device *dev);
15ffac73 JE	216	int stmmac_dvr_probe(struct device *device,
	217	struct plat_stmmacenet_data *plat_dat,
	218	struct stmmac_resources *res);
d765955d GC	219	void stmmac_disable_eee_mode(struct stmmac_priv *priv);
d765955d GC	220	bool stmmac_eee_init(struct stmmac_priv *priv);
ba1377ff	221
bd4242df	222	#endif /* __STMMAC_H__ */