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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
6a81c26f 31#include <linux/clk.h>
47dd7a54
GC		 32#include <linux/kernel.h>
33#include <linux/interrupt.h>
47dd7a54
GC		 34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/skbuff.h>
37#include <linux/ethtool.h>
38#include <linux/if_ether.h>
39#include <linux/crc32.h>
40#include <linux/mii.h>
01789349 41#include <linux/if.h>
47dd7a54
GC		 42#include <linux/if_vlan.h>
43#include <linux/dma-mapping.h>
5a0e3ad6 44#include <linux/slab.h>
70c71606 45#include <linux/prefetch.h>
7ac29055
GC		 46#ifdef CONFIG_STMMAC_DEBUG_FS
47#include <linux/debugfs.h>
48#include <linux/seq_file.h>
ceb69499 49#endif /* CONFIG_STMMAC_DEBUG_FS */
891434b1
RK		 50#include <linux/net_tstamp.h>
51#include "stmmac_ptp.h"
286a8372 52#include "stmmac.h"
47dd7a54 53
47dd7a54
GC		 54#undef STMMAC_DEBUG
55/*#define STMMAC_DEBUG*/
56#ifdef STMMAC_DEBUG
57#define DBG(nlevel, klevel, fmt, args...) \
58 ((void)(netif_msg_##nlevel(priv) && \
59 printk(KERN_##klevel fmt, ## args)))
60#else
61#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
62#endif
63
64#undef STMMAC_RX_DEBUG
65/*#define STMMAC_RX_DEBUG*/
66#ifdef STMMAC_RX_DEBUG
67#define RX_DBG(fmt, args...) printk(fmt, ## args)
68#else
69#define RX_DBG(fmt, args...) do { } while (0)
70#endif
71
72#undef STMMAC_XMIT_DEBUG
73/*#define STMMAC_XMIT_DEBUG*/
de53d557 74#ifdef STMMAC_XMIT_DEBUG
47dd7a54
GC		 75#define TX_DBG(fmt, args...) printk(fmt, ## args)
76#else
77#define TX_DBG(fmt, args...) do { } while (0)
78#endif
79
80#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
81#define JUMBO_LEN 9000
82
83/* Module parameters */
32ceabca 84#define TX_TIMEO 5000
47dd7a54
GC		 85static int watchdog = TX_TIMEO;
86module_param(watchdog, int, S_IRUGO | S_IWUSR);
32ceabca 87MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
47dd7a54 88
32ceabca 89static int debug = -1;
47dd7a54 90module_param(debug, int, S_IRUGO | S_IWUSR);
32ceabca 91MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
47dd7a54 92
bfab27a1 93int phyaddr = -1;
47dd7a54
GC		 94module_param(phyaddr, int, S_IRUGO);
95MODULE_PARM_DESC(phyaddr, "Physical device address");
96
97#define DMA_TX_SIZE 256
98static int dma_txsize = DMA_TX_SIZE;
99module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
100MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
101
102#define DMA_RX_SIZE 256
103static int dma_rxsize = DMA_RX_SIZE;
104module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
105MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
106
107static int flow_ctrl = FLOW_OFF;
108module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
109MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
110
111static int pause = PAUSE_TIME;
112module_param(pause, int, S_IRUGO | S_IWUSR);
113MODULE_PARM_DESC(pause, "Flow Control Pause Time");
114
115#define TC_DEFAULT 64
116static int tc = TC_DEFAULT;
117module_param(tc, int, S_IRUGO | S_IWUSR);
118MODULE_PARM_DESC(tc, "DMA threshold control value");
119
47dd7a54
GC		 120#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
121static int buf_sz = DMA_BUFFER_SIZE;
122module_param(buf_sz, int, S_IRUGO | S_IWUSR);
123MODULE_PARM_DESC(buf_sz, "DMA buffer size");
124
47dd7a54
GC		 125static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
126 NETIF_MSG_LINK | NETIF_MSG_IFUP |
127 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
128
d765955d
GC		 129#define STMMAC_DEFAULT_LPI_TIMER 1000
130static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
131module_param(eee_timer, int, S_IRUGO | S_IWUSR);
132MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
133#define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
134
4a7d666a
GC		 135/* By default the driver will use the ring mode to manage tx and rx descriptors
136 * but passing this value so user can force to use the chain instead of the ring
137 */
138static unsigned int chain_mode;
139module_param(chain_mode, int, S_IRUGO);
140MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
141
47dd7a54 142static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54 143
bfab27a1
GC		 144#ifdef CONFIG_STMMAC_DEBUG_FS
145static int stmmac_init_fs(struct net_device *dev);
146static void stmmac_exit_fs(void);
147#endif
148
9125cdd1
GC		 149#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
150
47dd7a54
GC		 151/**
152 * stmmac_verify_args - verify the driver parameters.
153 * Description: it verifies if some wrong parameter is passed to the driver.
154 * Note that wrong parameters are replaced with the default values.
155 */
156static void stmmac_verify_args(void)
157{
158 if (unlikely(watchdog < 0))
159 watchdog = TX_TIMEO;
160 if (unlikely(dma_rxsize < 0))
161 dma_rxsize = DMA_RX_SIZE;
162 if (unlikely(dma_txsize < 0))
163 dma_txsize = DMA_TX_SIZE;
164 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
165 buf_sz = DMA_BUFFER_SIZE;
166 if (unlikely(flow_ctrl > 1))
167 flow_ctrl = FLOW_AUTO;
168 else if (likely(flow_ctrl < 0))
169 flow_ctrl = FLOW_OFF;
170 if (unlikely((pause < 0) || (pause > 0xffff)))
171 pause = PAUSE_TIME;
d765955d
GC		 172 if (eee_timer < 0)
173 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
47dd7a54
GC		 174}
175
32ceabca
GC		 176/**
177 * stmmac_clk_csr_set - dynamically set the MDC clock
178 * @priv: driver private structure
179 * Description: this is to dynamically set the MDC clock according to the csr
180 * clock input.
181 * Note:
182 * If a specific clk_csr value is passed from the platform
183 * this means that the CSR Clock Range selection cannot be
184 * changed at run-time and it is fixed (as reported in the driver
185 * documentation). Viceversa the driver will try to set the MDC
186 * clock dynamically according to the actual clock input.
187 */
cd7201f4
GC		 188static void stmmac_clk_csr_set(struct stmmac_priv *priv)
189{
cd7201f4
GC		 190 u32 clk_rate;
191
192 clk_rate = clk_get_rate(priv->stmmac_clk);
193
194 /* Platform provided default clk_csr would be assumed valid
ceb69499
GC		 195 * for all other cases except for the below mentioned ones.
196 * For values higher than the IEEE 802.3 specified frequency
197 * we can not estimate the proper divider as it is not known
198 * the frequency of clk_csr_i. So we do not change the default
199 * divider.
200 */
cd7201f4
GC		 201 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
202 if (clk_rate < CSR_F_35M)
203 priv->clk_csr = STMMAC_CSR_20_35M;
204 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
205 priv->clk_csr = STMMAC_CSR_35_60M;
206 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
207 priv->clk_csr = STMMAC_CSR_60_100M;
208 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
209 priv->clk_csr = STMMAC_CSR_100_150M;
210 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
211 priv->clk_csr = STMMAC_CSR_150_250M;
212 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
213 priv->clk_csr = STMMAC_CSR_250_300M;
ceb69499 214 }
cd7201f4
GC		 215}
216
47dd7a54
GC		 217#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
218static void print_pkt(unsigned char *buf, int len)
219{
220 int j;
221 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
222 for (j = 0; j < len; j++) {
223 if ((j % 16) == 0)
224 pr_info("\n %03x:", j);
225 pr_info(" %02x", buf[j]);
226 }
227 pr_info("\n");
47dd7a54
GC		 228}
229#endif
230
231/* minimum number of free TX descriptors required to wake up TX process */
232#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
233
234static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
235{
236 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
237}
238
32ceabca
GC		 239/**
240 * stmmac_hw_fix_mac_speed: callback for speed selection
241 * @priv: driver private structure
242 * Description: on some platforms (e.g. ST), some HW system configuraton
243 * registers have to be set according to the link speed negotiated.
9dfeb4d9
GC		 244 */
245static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
246{
247 struct phy_device *phydev = priv->phydev;
248
249 if (likely(priv->plat->fix_mac_speed))
ceb69499 250 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
9dfeb4d9
GC		 251}
252
32ceabca
GC		 253/**
254 * stmmac_enable_eee_mode: Check and enter in LPI mode
255 * @priv: driver private structure
256 * Description: this function is to verify and enter in LPI mode for EEE.
257 */
d765955d
GC		 258static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
259{
260 /* Check and enter in LPI mode */
261 if ((priv->dirty_tx == priv->cur_tx) &&
262 (priv->tx_path_in_lpi_mode == false))
263 priv->hw->mac->set_eee_mode(priv->ioaddr);
264}
265
32ceabca
GC		 266/**
267 * stmmac_disable_eee_mode: disable/exit from EEE
268 * @priv: driver private structure
269 * Description: this function is to exit and disable EEE in case of
270 * LPI state is true. This is called by the xmit.
271 */
d765955d
GC		 272void stmmac_disable_eee_mode(struct stmmac_priv *priv)
273{
d765955d
GC		 274 priv->hw->mac->reset_eee_mode(priv->ioaddr);
275 del_timer_sync(&priv->eee_ctrl_timer);
276 priv->tx_path_in_lpi_mode = false;
277}
278
279/**
32ceabca 280 * stmmac_eee_ctrl_timer: EEE TX SW timer.
d765955d
GC		 281 * @arg : data hook
282 * Description:
32ceabca 283 * if there is no data transfer and if we are not in LPI state,
d765955d
GC		 284 * then MAC Transmitter can be moved to LPI state.
285 */
286static void stmmac_eee_ctrl_timer(unsigned long arg)
287{
288 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
289
290 stmmac_enable_eee_mode(priv);
291 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
292}
293
294/**
32ceabca
GC		 295 * stmmac_eee_init: init EEE
296 * @priv: driver private structure
d765955d
GC		 297 * Description:
298 * If the EEE support has been enabled while configuring the driver,
299 * if the GMAC actually supports the EEE (from the HW cap reg) and the
300 * phy can also manage EEE, so enable the LPI state and start the timer
301 * to verify if the tx path can enter in LPI state.
302 */
303bool stmmac_eee_init(struct stmmac_priv *priv)
304{
305 bool ret = false;
306
307 /* MAC core supports the EEE feature. */
308 if (priv->dma_cap.eee) {
309 /* Check if the PHY supports EEE */
310 if (phy_init_eee(priv->phydev, 1))
311 goto out;
312
313 priv->eee_active = 1;
314 init_timer(&priv->eee_ctrl_timer);
315 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
316 priv->eee_ctrl_timer.data = (unsigned long)priv;
317 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
318 add_timer(&priv->eee_ctrl_timer);
319
320 priv->hw->mac->set_eee_timer(priv->ioaddr,
321 STMMAC_DEFAULT_LIT_LS_TIMER,
322 priv->tx_lpi_timer);
323
324 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
325
326 ret = true;
327 }
328out:
329 return ret;
330}
331
32ceabca
GC		 332/**
333 * stmmac_eee_adjust: adjust HW EEE according to the speed
334 * @priv: driver private structure
335 * Description:
336 * When the EEE has been already initialised we have to
337 * modify the PLS bit in the LPI ctrl & status reg according
338 * to the PHY link status. For this reason.
339 */
d765955d
GC		 340static void stmmac_eee_adjust(struct stmmac_priv *priv)
341{
d765955d
GC		 342 if (priv->eee_enabled)
343 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
344}
345
32ceabca
GC		 346/* stmmac_get_tx_hwtstamp: get HW TX timestamps
347 * @priv: driver private structure
891434b1
RK		 348 * @entry : descriptor index to be used.
349 * @skb : the socket buffer
350 * Description :
351 * This function will read timestamp from the descriptor & pass it to stack.
352 * and also perform some sanity checks.
353 */
354static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
ceb69499 355 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 356{
357 struct skb_shared_hwtstamps shhwtstamp;
358 u64 ns;
359 void *desc = NULL;
360
361 if (!priv->hwts_tx_en)
362 return;
363
ceb69499 364 /* exit if skb doesn't support hw tstamp */
891434b1
RK		 365 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
366 return;
367
368 if (priv->adv_ts)
369 desc = (priv->dma_etx + entry);
370 else
371 desc = (priv->dma_tx + entry);
372
373 /* check tx tstamp status */
374 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
375 return;
376
377 /* get the valid tstamp */
378 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
379
380 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
381 shhwtstamp.hwtstamp = ns_to_ktime(ns);
382 /* pass tstamp to stack */
383 skb_tstamp_tx(skb, &shhwtstamp);
384
385 return;
386}
387
32ceabca
GC		 388/* stmmac_get_rx_hwtstamp: get HW RX timestamps
389 * @priv: driver private structure
891434b1
RK		 390 * @entry : descriptor index to be used.
391 * @skb : the socket buffer
392 * Description :
393 * This function will read received packet's timestamp from the descriptor
394 * and pass it to stack. It also perform some sanity checks.
395 */
396static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
ceb69499 397 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 398{
399 struct skb_shared_hwtstamps *shhwtstamp = NULL;
400 u64 ns;
401 void *desc = NULL;
402
403 if (!priv->hwts_rx_en)
404 return;
405
406 if (priv->adv_ts)
407 desc = (priv->dma_erx + entry);
408 else
409 desc = (priv->dma_rx + entry);
410
ceb69499 411 /* exit if rx tstamp is not valid */
891434b1
RK		 412 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
413 return;
414
415 /* get valid tstamp */
416 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
417 shhwtstamp = skb_hwtstamps(skb);
418 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
419 shhwtstamp->hwtstamp = ns_to_ktime(ns);
420}
421
422/**
423 * stmmac_hwtstamp_ioctl - control hardware timestamping.
424 * @dev: device pointer.
425 * @ifr: An IOCTL specefic structure, that can contain a pointer to
426 * a proprietary structure used to pass information to the driver.
427 * Description:
428 * This function configures the MAC to enable/disable both outgoing(TX)
429 * and incoming(RX) packets time stamping based on user input.
430 * Return Value:
431 * 0 on success and an appropriate -ve integer on failure.
432 */
433static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
434{
435 struct stmmac_priv *priv = netdev_priv(dev);
436 struct hwtstamp_config config;
437 struct timespec now;
438 u64 temp = 0;
439 u32 ptp_v2 = 0;
440 u32 tstamp_all = 0;
441 u32 ptp_over_ipv4_udp = 0;
442 u32 ptp_over_ipv6_udp = 0;
443 u32 ptp_over_ethernet = 0;
444 u32 snap_type_sel = 0;
445 u32 ts_master_en = 0;
446 u32 ts_event_en = 0;
447 u32 value = 0;
448
449 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
450 netdev_alert(priv->dev, "No support for HW time stamping\n");
451 priv->hwts_tx_en = 0;
452 priv->hwts_rx_en = 0;
453
454 return -EOPNOTSUPP;
455 }
456
457 if (copy_from_user(&config, ifr->ifr_data,
ceb69499 458 sizeof(struct hwtstamp_config)))
891434b1
RK		 459 return -EFAULT;
460
461 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
462 __func__, config.flags, config.tx_type, config.rx_filter);
463
464 /* reserved for future extensions */
465 if (config.flags)
466 return -EINVAL;
467
468 switch (config.tx_type) {
469 case HWTSTAMP_TX_OFF:
470 priv->hwts_tx_en = 0;
471 break;
472 case HWTSTAMP_TX_ON:
473 priv->hwts_tx_en = 1;
474 break;
475 default:
476 return -ERANGE;
477 }
478
479 if (priv->adv_ts) {
480 switch (config.rx_filter) {
891434b1 481 case HWTSTAMP_FILTER_NONE:
ceb69499 482 /* time stamp no incoming packet at all */
891434b1
RK		 483 config.rx_filter = HWTSTAMP_FILTER_NONE;
484 break;
485
891434b1 486 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
ceb69499 487 /* PTP v1, UDP, any kind of event packet */
891434b1
RK		 488 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
489 /* take time stamp for all event messages */
490 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
491
492 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
493 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
494 break;
495
891434b1 496 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
ceb69499 497 /* PTP v1, UDP, Sync packet */
891434b1
RK		 498 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
499 /* take time stamp for SYNC messages only */
500 ts_event_en = PTP_TCR_TSEVNTENA;
501
502 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
503 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
504 break;
505
891434b1 506 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
ceb69499 507 /* PTP v1, UDP, Delay_req packet */
891434b1
RK		 508 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
509 /* take time stamp for Delay_Req messages only */
510 ts_master_en = PTP_TCR_TSMSTRENA;
511 ts_event_en = PTP_TCR_TSEVNTENA;
512
513 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
514 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
515 break;
516
891434b1 517 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
ceb69499 518 /* PTP v2, UDP, any kind of event packet */
891434b1
RK		 519 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
520 ptp_v2 = PTP_TCR_TSVER2ENA;
521 /* take time stamp for all event messages */
522 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
523
524 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
525 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
526 break;
527
891434b1 528 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
ceb69499 529 /* PTP v2, UDP, Sync packet */
891434b1
RK		 530 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
531 ptp_v2 = PTP_TCR_TSVER2ENA;
532 /* take time stamp for SYNC messages only */
533 ts_event_en = PTP_TCR_TSEVNTENA;
534
535 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
536 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
537 break;
538
891434b1 539 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
ceb69499 540 /* PTP v2, UDP, Delay_req packet */
891434b1
RK		 541 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
542 ptp_v2 = PTP_TCR_TSVER2ENA;
543 /* take time stamp for Delay_Req messages only */
544 ts_master_en = PTP_TCR_TSMSTRENA;
545 ts_event_en = PTP_TCR_TSEVNTENA;
546
547 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
548 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
549 break;
550
891434b1 551 case HWTSTAMP_FILTER_PTP_V2_EVENT:
ceb69499 552 /* PTP v2/802.AS1 any layer, any kind of event packet */
891434b1
RK		 553 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
554 ptp_v2 = PTP_TCR_TSVER2ENA;
555 /* take time stamp for all event messages */
556 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
557
558 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
559 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
560 ptp_over_ethernet = PTP_TCR_TSIPENA;
561 break;
562
891434b1 563 case HWTSTAMP_FILTER_PTP_V2_SYNC:
ceb69499 564 /* PTP v2/802.AS1, any layer, Sync packet */
891434b1
RK		 565 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
566 ptp_v2 = PTP_TCR_TSVER2ENA;
567 /* take time stamp for SYNC messages only */
568 ts_event_en = PTP_TCR_TSEVNTENA;
569
570 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
571 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
572 ptp_over_ethernet = PTP_TCR_TSIPENA;
573 break;
574
891434b1 575 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
ceb69499 576 /* PTP v2/802.AS1, any layer, Delay_req packet */
891434b1
RK		 577 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
578 ptp_v2 = PTP_TCR_TSVER2ENA;
579 /* take time stamp for Delay_Req messages only */
580 ts_master_en = PTP_TCR_TSMSTRENA;
581 ts_event_en = PTP_TCR_TSEVNTENA;
582
583 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
584 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
585 ptp_over_ethernet = PTP_TCR_TSIPENA;
586 break;
587
891434b1 588 case HWTSTAMP_FILTER_ALL:
ceb69499 589 /* time stamp any incoming packet */
891434b1
RK		 590 config.rx_filter = HWTSTAMP_FILTER_ALL;
591 tstamp_all = PTP_TCR_TSENALL;
592 break;
593
594 default:
595 return -ERANGE;
596 }
597 } else {
598 switch (config.rx_filter) {
599 case HWTSTAMP_FILTER_NONE:
600 config.rx_filter = HWTSTAMP_FILTER_NONE;
601 break;
602 default:
603 /* PTP v1, UDP, any kind of event packet */
604 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
605 break;
606 }
607 }
608 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
609
610 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
611 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
612 else {
613 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
ceb69499
GC		 614 tstamp_all | ptp_v2 | ptp_over_ethernet |
615 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
616 ts_master_en | snap_type_sel);
891434b1
RK		 617
618 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
619
620 /* program Sub Second Increment reg */
621 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
622
623 /* calculate default added value:
624 * formula is :
625 * addend = (2^32)/freq_div_ratio;
626 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
627 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
628 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
629 * achive 20ns accuracy.
630 *
631 * 2^x * y == (y << x), hence
632 * 2^32 * 50000000 ==> (50000000 << 32)
633 */
ceb69499 634 temp = (u64) (50000000ULL << 32);
891434b1
RK		 635 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
636 priv->hw->ptp->config_addend(priv->ioaddr,
637 priv->default_addend);
638
639 /* initialize system time */
640 getnstimeofday(&now);
641 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
642 now.tv_nsec);
643 }
644
645 return copy_to_user(ifr->ifr_data, &config,
646 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
647}
648
32ceabca
GC		 649/**
650 * stmmac_init_ptp: init PTP
651 * @priv: driver private structure
652 * Description: this is to verify if the HW supports the PTPv1 or v2.
653 * This is done by looking at the HW cap. register.
654 * Also it registers the ptp driver.
655 */
92ba6888 656static int stmmac_init_ptp(struct stmmac_priv *priv)
891434b1 657{
92ba6888
RK		 658 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
659 return -EOPNOTSUPP;
660
661 if (netif_msg_hw(priv)) {
662 if (priv->dma_cap.time_stamp) {
663 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
664 priv->adv_ts = 0;
665 }
666 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
ceb69499
GC		 667 pr_debug
668 ("IEEE 1588-2008 Advanced Time Stamp supported\n");
92ba6888
RK		 669 priv->adv_ts = 1;
670 }
891434b1
RK		 671 }
672
673 priv->hw->ptp = &stmmac_ptp;
674 priv->hwts_tx_en = 0;
675 priv->hwts_rx_en = 0;
92ba6888
RK		 676
677 return stmmac_ptp_register(priv);
678}
679
680static void stmmac_release_ptp(struct stmmac_priv *priv)
681{
682 stmmac_ptp_unregister(priv);
891434b1
RK		 683}
684
47dd7a54
GC		 685/**
686 * stmmac_adjust_link
687 * @dev: net device structure
688 * Description: it adjusts the link parameters.
689 */
690static void stmmac_adjust_link(struct net_device *dev)
691{
692 struct stmmac_priv *priv = netdev_priv(dev);
693 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 694 unsigned long flags;
695 int new_state = 0;
696 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
697
698 if (phydev == NULL)
699 return;
700
701 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
702 phydev->addr, phydev->link);
703
704 spin_lock_irqsave(&priv->lock, flags);
d765955d 705
47dd7a54 706 if (phydev->link) {
ad01b7d4 707 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 708
709 /* Now we make sure that we can be in full duplex mode.
710 * If not, we operate in half-duplex mode. */
711 if (phydev->duplex != priv->oldduplex) {
712 new_state = 1;
713 if (!(phydev->duplex))
db98a0b0 714 ctrl &= ~priv->hw->link.duplex;
47dd7a54 715 else
db98a0b0 716 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 717 priv->oldduplex = phydev->duplex;
718 }
719 /* Flow Control operation */
720 if (phydev->pause)
ad01b7d4 721 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 722 fc, pause_time);
47dd7a54
GC		 723
724 if (phydev->speed != priv->speed) {
725 new_state = 1;
726 switch (phydev->speed) {
727 case 1000:
9dfeb4d9 728 if (likely(priv->plat->has_gmac))
db98a0b0 729 ctrl &= ~priv->hw->link.port;
ceb69499 730 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 731 break;
732 case 100:
733 case 10:
9dfeb4d9 734 if (priv->plat->has_gmac) {
db98a0b0 735 ctrl |= priv->hw->link.port;
47dd7a54 736 if (phydev->speed == SPEED_100) {
db98a0b0 737 ctrl |= priv->hw->link.speed;
47dd7a54 738 } else {
db98a0b0 739 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 740 }
741 } else {
db98a0b0 742 ctrl &= ~priv->hw->link.port;
47dd7a54 743 }
9dfeb4d9 744 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 745 break;
746 default:
747 if (netif_msg_link(priv))
ceb69499
GC		 748 pr_warn("%s: Speed (%d) not 10/100\n",
749 dev->name, phydev->speed);
47dd7a54
GC		 750 break;
751 }
752
753 priv->speed = phydev->speed;
754 }
755
ad01b7d4 756 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 757
758 if (!priv->oldlink) {
759 new_state = 1;
760 priv->oldlink = 1;
761 }
762 } else if (priv->oldlink) {
763 new_state = 1;
764 priv->oldlink = 0;
765 priv->speed = 0;
766 priv->oldduplex = -1;
767 }
768
769 if (new_state && netif_msg_link(priv))
770 phy_print_status(phydev);
771
d765955d
GC		 772 stmmac_eee_adjust(priv);
773
47dd7a54
GC		 774 spin_unlock_irqrestore(&priv->lock, flags);
775
776 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
777}
778
32ceabca
GC		 779/**
780 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
781 * @priv: driver private structure
782 * Description: this is to verify if the HW supports the PCS.
783 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
784 * configured for the TBI, RTBI, or SGMII PHY interface.
785 */
e58bb43f
GC		 786static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
787{
788 int interface = priv->plat->interface;
789
790 if (priv->dma_cap.pcs) {
0d909dcd
BA		 791 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
792 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
793 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
794 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
e58bb43f
GC		 795 pr_debug("STMMAC: PCS RGMII support enable\n");
796 priv->pcs = STMMAC_PCS_RGMII;
0d909dcd 797 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
e58bb43f
GC		 798 pr_debug("STMMAC: PCS SGMII support enable\n");
799 priv->pcs = STMMAC_PCS_SGMII;
800 }
801 }
802}
803
47dd7a54
GC		 804/**
805 * stmmac_init_phy - PHY initialization
806 * @dev: net device structure
807 * Description: it initializes the driver's PHY state, and attaches the PHY
808 * to the mac driver.
809 * Return value:
810 * 0 on success
811 */
812static int stmmac_init_phy(struct net_device *dev)
813{
814 struct stmmac_priv *priv = netdev_priv(dev);
815 struct phy_device *phydev;
d765955d 816 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
109cdd66 817 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 818 int interface = priv->plat->interface;
47dd7a54
GC		 819 priv->oldlink = 0;
820 priv->speed = 0;
821 priv->oldduplex = -1;
822
f142af2e
SK		 823 if (priv->plat->phy_bus_name)
824 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
ceb69499 825 priv->plat->phy_bus_name, priv->plat->bus_id);
f142af2e
SK		 826 else
827 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
ceb69499 828 priv->plat->bus_id);
f142af2e 829
d765955d 830 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 831 priv->plat->phy_addr);
d765955d 832 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
47dd7a54 833
f9a8f83b 834 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
47dd7a54
GC		 835
836 if (IS_ERR(phydev)) {
837 pr_err("%s: Could not attach to PHY\n", dev->name);
838 return PTR_ERR(phydev);
839 }
840
79ee1dc3 841 /* Stop Advertising 1000BASE Capability if interface is not GMII */
c5b9b4e4
SK		 842 if ((interface == PHY_INTERFACE_MODE_MII) ||
843 (interface == PHY_INTERFACE_MODE_RMII))
844 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
845 SUPPORTED_1000baseT_Full);
79ee1dc3 846
47dd7a54
GC		 847 /*
848 * Broken HW is sometimes missing the pull-up resistor on the
849 * MDIO line, which results in reads to non-existent devices returning
850 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
851 * device as well.
852 * Note: phydev->phy_id is the result of reading the UID PHY registers.
853 */
854 if (phydev->phy_id == 0) {
855 phy_disconnect(phydev);
856 return -ENODEV;
857 }
858 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 859 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 860
861 priv->phydev = phydev;
862
863 return 0;
864}
865
47dd7a54 866/**
32ceabca
GC		 867 * stmmac_display_ring: display ring
868 * @head: pointer to the head of the ring passed.
47dd7a54 869 * @size: size of the ring.
32ceabca 870 * @extend_desc: to verify if extended descriptors are used.
c24602ef 871 * Description: display the control/status and buffer descriptors.
47dd7a54 872 */
c24602ef 873static void stmmac_display_ring(void *head, int size, int extend_desc)
47dd7a54 874{
47dd7a54 875 int i;
ceb69499
GC		 876 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
877 struct dma_desc *p = (struct dma_desc *)head;
c24602ef 878
47dd7a54 879 for (i = 0; i < size; i++) {
c24602ef
GC		 880 u64 x;
881 if (extend_desc) {
882 x = *(u64 *) ep;
883 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 884 i, (unsigned int)virt_to_phys(ep),
885 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 886 ep->basic.des2, ep->basic.des3);
887 ep++;
888 } else {
889 x = *(u64 *) p;
890 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
ceb69499
GC		 891 i, (unsigned int)virt_to_phys(p),
892 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 893 p->des2, p->des3);
894 p++;
895 }
47dd7a54
GC		 896 pr_info("\n");
897 }
898}
899
c24602ef
GC		 900static void stmmac_display_rings(struct stmmac_priv *priv)
901{
902 unsigned int txsize = priv->dma_tx_size;
903 unsigned int rxsize = priv->dma_rx_size;
904
905 if (priv->extend_desc) {
906 pr_info("Extended RX descriptor ring:\n");
ceb69499 907 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef 908 pr_info("Extended TX descriptor ring:\n");
ceb69499 909 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
c24602ef
GC		 910 } else {
911 pr_info("RX descriptor ring:\n");
912 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
913 pr_info("TX descriptor ring:\n");
914 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
915 }
916}
917
286a8372
GC		 918static int stmmac_set_bfsize(int mtu, int bufsize)
919{
920 int ret = bufsize;
921
922 if (mtu >= BUF_SIZE_4KiB)
923 ret = BUF_SIZE_8KiB;
924 else if (mtu >= BUF_SIZE_2KiB)
925 ret = BUF_SIZE_4KiB;
926 else if (mtu >= DMA_BUFFER_SIZE)
927 ret = BUF_SIZE_2KiB;
928 else
929 ret = DMA_BUFFER_SIZE;
930
931 return ret;
932}
933
32ceabca
GC		 934/**
935 * stmmac_clear_descriptors: clear descriptors
936 * @priv: driver private structure
937 * Description: this function is called to clear the tx and rx descriptors
938 * in case of both basic and extended descriptors are used.
939 */
c24602ef
GC		 940static void stmmac_clear_descriptors(struct stmmac_priv *priv)
941{
942 int i;
943 unsigned int txsize = priv->dma_tx_size;
944 unsigned int rxsize = priv->dma_rx_size;
945
946 /* Clear the Rx/Tx descriptors */
947 for (i = 0; i < rxsize; i++)
948 if (priv->extend_desc)
949 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
950 priv->use_riwt, priv->mode,
951 (i == rxsize - 1));
952 else
953 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
954 priv->use_riwt, priv->mode,
955 (i == rxsize - 1));
956 for (i = 0; i < txsize; i++)
957 if (priv->extend_desc)
958 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
959 priv->mode,
960 (i == txsize - 1));
961 else
962 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
963 priv->mode,
964 (i == txsize - 1));
965}
966
967static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
968 int i)
969{
970 struct sk_buff *skb;
971
972 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
973 GFP_KERNEL);
974 if (unlikely(skb == NULL)) {
975 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
976 return 1;
977 }
978 skb_reserve(skb, NET_IP_ALIGN);
979 priv->rx_skbuff[i] = skb;
980 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
981 priv->dma_buf_sz,
982 DMA_FROM_DEVICE);
983
984 p->des2 = priv->rx_skbuff_dma[i];
985
986 if ((priv->mode == STMMAC_RING_MODE) &&
987 (priv->dma_buf_sz == BUF_SIZE_16KiB))
988 priv->hw->ring->init_desc3(p);
989
990 return 0;
991}
992
47dd7a54
GC		 993/**
994 * init_dma_desc_rings - init the RX/TX descriptor rings
995 * @dev: net device structure
996 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 997 * and allocates the socket buffers. It suppors the chained and ring
998 * modes.
47dd7a54
GC		 999 */
1000static void init_dma_desc_rings(struct net_device *dev)
1001{
1002 int i;
1003 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1004 unsigned int txsize = priv->dma_tx_size;
1005 unsigned int rxsize = priv->dma_rx_size;
4a7d666a 1006 unsigned int bfsize = 0;
47dd7a54 1007
286a8372 1008 /* Set the max buffer size according to the DESC mode
ceb69499
GC		 1009 * and the MTU. Note that RING mode allows 16KiB bsize.
1010 */
4a7d666a
GC		 1011 if (priv->mode == STMMAC_RING_MODE)
1012 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
286a8372 1013
4a7d666a 1014 if (bfsize < BUF_SIZE_16KiB)
286a8372 1015 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 1016
47dd7a54
GC		 1017 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1018 txsize, rxsize, bfsize);
1019
c24602ef
GC		 1020 if (priv->extend_desc) {
1021 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1022 sizeof(struct
1023 dma_extended_desc),
1024 &priv->dma_rx_phy,
1025 GFP_KERNEL);
1026 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1027 sizeof(struct
1028 dma_extended_desc),
1029 &priv->dma_tx_phy,
1030 GFP_KERNEL);
1031 if ((!priv->dma_erx) || (!priv->dma_etx))
1032 return;
1033 } else {
1034 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1035 sizeof(struct dma_desc),
1036 &priv->dma_rx_phy,
1037 GFP_KERNEL);
1038 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1039 sizeof(struct dma_desc),
1040 &priv->dma_tx_phy,
1041 GFP_KERNEL);
1042 if ((!priv->dma_rx) || (!priv->dma_tx))
1043 return;
1044 }
1045
b2adaca9
JP		 1046 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1047 GFP_KERNEL);
1048 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1049 GFP_KERNEL);
cf32deec 1050 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
ceb69499 1051 GFP_KERNEL);
b2adaca9
JP		 1052 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1053 GFP_KERNEL);
c24602ef
GC		 1054 if (netif_msg_drv(priv))
1055 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1056 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
47dd7a54
GC		 1057
1058 /* RX INITIALIZATION */
c24602ef 1059 DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
47dd7a54 1060 for (i = 0; i < rxsize; i++) {
c24602ef
GC		 1061 struct dma_desc *p;
1062 if (priv->extend_desc)
1063 p = &((priv->dma_erx + i)->basic);
1064 else
1065 p = priv->dma_rx + i;
47dd7a54 1066
c24602ef 1067 if (stmmac_init_rx_buffers(priv, p, i))
47dd7a54 1068 break;
286a8372 1069
47dd7a54 1070 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
ceb69499 1071 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
47dd7a54
GC		 1072 }
1073 priv->cur_rx = 0;
1074 priv->dirty_rx = (unsigned int)(i - rxsize);
1075 priv->dma_buf_sz = bfsize;
1076 buf_sz = bfsize;
1077
c24602ef
GC		 1078 /* Setup the chained descriptor addresses */
1079 if (priv->mode == STMMAC_CHAIN_MODE) {
1080 if (priv->extend_desc) {
1081 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1082 rxsize, 1);
1083 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1084 txsize, 1);
1085 } else {
1086 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1087 rxsize, 0);
1088 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1089 txsize, 0);
1090 }
1091 }
1092
47dd7a54
GC		 1093 /* TX INITIALIZATION */
1094 for (i = 0; i < txsize; i++) {
c24602ef
GC		 1095 struct dma_desc *p;
1096 if (priv->extend_desc)
1097 p = &((priv->dma_etx + i)->basic);
1098 else
1099 p = priv->dma_tx + i;
1100 p->des2 = 0;
cf32deec 1101 priv->tx_skbuff_dma[i] = 0;
47dd7a54 1102 priv->tx_skbuff[i] = NULL;
47dd7a54 1103 }
286a8372 1104
47dd7a54
GC		 1105 priv->dirty_tx = 0;
1106 priv->cur_tx = 0;
1107
c24602ef 1108 stmmac_clear_descriptors(priv);
47dd7a54 1109
c24602ef
GC		 1110 if (netif_msg_hw(priv))
1111 stmmac_display_rings(priv);
47dd7a54
GC		 1112}
1113
1114static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1115{
1116 int i;
1117
1118 for (i = 0; i < priv->dma_rx_size; i++) {
1119 if (priv->rx_skbuff[i]) {
1120 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1121 priv->dma_buf_sz, DMA_FROM_DEVICE);
1122 dev_kfree_skb_any(priv->rx_skbuff[i]);
1123 }
1124 priv->rx_skbuff[i] = NULL;
1125 }
47dd7a54
GC		 1126}
1127
1128static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1129{
1130 int i;
1131
1132 for (i = 0; i < priv->dma_tx_size; i++) {
1133 if (priv->tx_skbuff[i] != NULL) {
c24602ef
GC		 1134 struct dma_desc *p;
1135 if (priv->extend_desc)
1136 p = &((priv->dma_etx + i)->basic);
1137 else
1138 p = priv->dma_tx + i;
1139
cf32deec
RK		 1140 if (priv->tx_skbuff_dma[i])
1141 dma_unmap_single(priv->device,
1142 priv->tx_skbuff_dma[i],
db98a0b0
GC		 1143 priv->hw->desc->get_tx_len(p),
1144 DMA_TO_DEVICE);
47dd7a54
GC		 1145 dev_kfree_skb_any(priv->tx_skbuff[i]);
1146 priv->tx_skbuff[i] = NULL;
cf32deec 1147 priv->tx_skbuff_dma[i] = 0;
47dd7a54
GC		 1148 }
1149 }
47dd7a54
GC		 1150}
1151
1152static void free_dma_desc_resources(struct stmmac_priv *priv)
1153{
1154 /* Release the DMA TX/RX socket buffers */
1155 dma_free_rx_skbufs(priv);
1156 dma_free_tx_skbufs(priv);
1157
ceb69499 1158 /* Free DMA regions of consistent memory previously allocated */
c24602ef
GC		 1159 if (!priv->extend_desc) {
1160 dma_free_coherent(priv->device,
1161 priv->dma_tx_size * sizeof(struct dma_desc),
1162 priv->dma_tx, priv->dma_tx_phy);
1163 dma_free_coherent(priv->device,
1164 priv->dma_rx_size * sizeof(struct dma_desc),
1165 priv->dma_rx, priv->dma_rx_phy);
1166 } else {
1167 dma_free_coherent(priv->device, priv->dma_tx_size *
1168 sizeof(struct dma_extended_desc),
1169 priv->dma_etx, priv->dma_tx_phy);
1170 dma_free_coherent(priv->device, priv->dma_rx_size *
1171 sizeof(struct dma_extended_desc),
1172 priv->dma_erx, priv->dma_rx_phy);
1173 }
47dd7a54
GC		 1174 kfree(priv->rx_skbuff_dma);
1175 kfree(priv->rx_skbuff);
cf32deec 1176 kfree(priv->tx_skbuff_dma);
47dd7a54 1177 kfree(priv->tx_skbuff);
47dd7a54
GC		 1178}
1179
47dd7a54
GC		 1180/**
1181 * stmmac_dma_operation_mode - HW DMA operation mode
32ceabca 1182 * @priv: driver private structure
47dd7a54 1183 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 1184 * or Store-And-Forward capability.
47dd7a54
GC		 1185 */
1186static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1187{
61b8013a 1188 if (likely(priv->plat->force_sf_dma_mode ||
ceb69499 1189 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
61b8013a
SK		 1190 /*
1191 * In case of GMAC, SF mode can be enabled
1192 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 1193 * 1) TX COE if actually supported
1194 * 2) There is no bugged Jumbo frame support
1195 * that needs to not insert csum in the TDES.
1196 */
ceb69499 1197 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
ebbb293f
GC		 1198 tc = SF_DMA_MODE;
1199 } else
1200 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 1201}
1202
47dd7a54 1203/**
9125cdd1 1204 * stmmac_tx_clean:
32ceabca 1205 * @priv: driver private structure
47dd7a54
GC		 1206 * Description: it reclaims resources after transmission completes.
1207 */
9125cdd1 1208static void stmmac_tx_clean(struct stmmac_priv *priv)
47dd7a54
GC		 1209{
1210 unsigned int txsize = priv->dma_tx_size;
47dd7a54 1211
a9097a96
GC		 1212 spin_lock(&priv->tx_lock);
1213
9125cdd1
GC		 1214 priv->xstats.tx_clean++;
1215
47dd7a54
GC		 1216 while (priv->dirty_tx != priv->cur_tx) {
1217 int last;
1218 unsigned int entry = priv->dirty_tx % txsize;
1219 struct sk_buff *skb = priv->tx_skbuff[entry];
c24602ef
GC		 1220 struct dma_desc *p;
1221
1222 if (priv->extend_desc)
ceb69499 1223 p = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1224 else
1225 p = priv->dma_tx + entry;
47dd7a54
GC		 1226
1227 /* Check if the descriptor is owned by the DMA. */
db98a0b0 1228 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 1229 break;
1230
c24602ef 1231 /* Verify tx error by looking at the last segment. */
db98a0b0 1232 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 1233 if (likely(last)) {
1234 int tx_error =
ceb69499
GC		 1235 priv->hw->desc->tx_status(&priv->dev->stats,
1236 &priv->xstats, p,
1237 priv->ioaddr);
47dd7a54
GC		 1238 if (likely(tx_error == 0)) {
1239 priv->dev->stats.tx_packets++;
1240 priv->xstats.tx_pkt_n++;
1241 } else
1242 priv->dev->stats.tx_errors++;
891434b1
RK		 1243
1244 stmmac_get_tx_hwtstamp(priv, entry, skb);
47dd7a54
GC		 1245 }
1246 TX_DBG("%s: curr %d, dirty %d\n", __func__,
ceb69499 1247 priv->cur_tx, priv->dirty_tx);
47dd7a54 1248
cf32deec
RK		 1249 if (likely(priv->tx_skbuff_dma[entry])) {
1250 dma_unmap_single(priv->device,
1251 priv->tx_skbuff_dma[entry],
db98a0b0 1252 priv->hw->desc->get_tx_len(p),
47dd7a54 1253 DMA_TO_DEVICE);
cf32deec
RK		 1254 priv->tx_skbuff_dma[entry] = 0;
1255 }
891434b1 1256 priv->hw->ring->clean_desc3(priv, p);
47dd7a54
GC		 1257
1258 if (likely(skb != NULL)) {
acb600de 1259 dev_kfree_skb(skb);
47dd7a54
GC		 1260 priv->tx_skbuff[entry] = NULL;
1261 }
1262
4a7d666a 1263 priv->hw->desc->release_tx_desc(p, priv->mode);
47dd7a54 1264
13497f58 1265 priv->dirty_tx++;
47dd7a54
GC		 1266 }
1267 if (unlikely(netif_queue_stopped(priv->dev) &&
1268 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1269 netif_tx_lock(priv->dev);
1270 if (netif_queue_stopped(priv->dev) &&
ceb69499 1271 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
47dd7a54
GC		 1272 TX_DBG("%s: restart transmit\n", __func__);
1273 netif_wake_queue(priv->dev);
1274 }
1275 netif_tx_unlock(priv->dev);
1276 }
d765955d
GC		 1277
1278 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1279 stmmac_enable_eee_mode(priv);
1280 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
1281 }
a9097a96 1282 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 1283}
1284
9125cdd1 1285static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1286{
7284a3f1 1287 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1288}
1289
9125cdd1 1290static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1291{
7284a3f1 1292 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1293}
1294
47dd7a54 1295/**
32ceabca
GC		 1296 * stmmac_tx_err: irq tx error mng function
1297 * @priv: driver private structure
47dd7a54
GC		 1298 * Description: it cleans the descriptors and restarts the transmission
1299 * in case of errors.
1300 */
1301static void stmmac_tx_err(struct stmmac_priv *priv)
1302{
c24602ef
GC		 1303 int i;
1304 int txsize = priv->dma_tx_size;
47dd7a54
GC		 1305 netif_stop_queue(priv->dev);
1306
ad01b7d4 1307 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1308 dma_free_tx_skbufs(priv);
c24602ef
GC		 1309 for (i = 0; i < txsize; i++)
1310 if (priv->extend_desc)
1311 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1312 priv->mode,
1313 (i == txsize - 1));
1314 else
1315 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1316 priv->mode,
1317 (i == txsize - 1));
47dd7a54
GC		 1318 priv->dirty_tx = 0;
1319 priv->cur_tx = 0;
ad01b7d4 1320 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 1321
1322 priv->dev->stats.tx_errors++;
1323 netif_wake_queue(priv->dev);
47dd7a54
GC		 1324}
1325
32ceabca
GC		 1326/**
1327 * stmmac_dma_interrupt: DMA ISR
1328 * @priv: driver private structure
1329 * Description: this is the DMA ISR. It is called by the main ISR.
1330 * It calls the dwmac dma routine to understand which type of interrupt
1331 * happened. In case of there is a Normal interrupt and either TX or RX
1332 * interrupt happened so the NAPI is scheduled.
1333 */
aec7ff27
GC		 1334static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1335{
aec7ff27
GC		 1336 int status;
1337
ad01b7d4 1338 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
9125cdd1
GC		 1339 if (likely((status & handle_rx)) || (status & handle_tx)) {
1340 if (likely(napi_schedule_prep(&priv->napi))) {
1341 stmmac_disable_dma_irq(priv);
1342 __napi_schedule(&priv->napi);
1343 }
1344 }
1345 if (unlikely(status & tx_hard_error_bump_tc)) {
aec7ff27
GC		 1346 /* Try to bump up the dma threshold on this failure */
1347 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1348 tc += 64;
ad01b7d4 1349 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 1350 priv->xstats.threshold = tc;
47dd7a54 1351 }
aec7ff27
GC		 1352 } else if (unlikely(status == tx_hard_error))
1353 stmmac_tx_err(priv);
47dd7a54
GC		 1354}
1355
32ceabca
GC		 1356/**
1357 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1358 * @priv: driver private structure
1359 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1360 */
1c901a46
GC		 1361static void stmmac_mmc_setup(struct stmmac_priv *priv)
1362{
1363 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
ceb69499 1364 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1c901a46 1365
1c901a46 1366 dwmac_mmc_intr_all_mask(priv->ioaddr);
4f795b25
GC		 1367
1368 if (priv->dma_cap.rmon) {
1369 dwmac_mmc_ctrl(priv->ioaddr, mode);
1370 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1371 } else
aae54cff 1372 pr_info(" No MAC Management Counters available\n");
1c901a46
GC		 1373}
1374
f0b9d786
GC		 1375static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1376{
1377 u32 hwid = priv->hw->synopsys_uid;
1378
ceb69499 1379 /* Check Synopsys Id (not available on old chips) */
f0b9d786
GC		 1380 if (likely(hwid)) {
1381 u32 uid = ((hwid & 0x0000ff00) >> 8);
1382 u32 synid = (hwid & 0x000000ff);
1383
cf3f047b 1384 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
f0b9d786
GC		 1385 uid, synid);
1386
1387 return synid;
1388 }
1389 return 0;
1390}
e7434821 1391
19e30c14 1392/**
32ceabca
GC		 1393 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1394 * @priv: driver private structure
1395 * Description: select the Enhanced/Alternate or Normal descriptors.
1396 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1397 * supported by the HW cap. register.
ff3dd78c 1398 */
19e30c14
GC		 1399static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1400{
1401 if (priv->plat->enh_desc) {
1402 pr_info(" Enhanced/Alternate descriptors\n");
c24602ef
GC		 1403
1404 /* GMAC older than 3.50 has no extended descriptors */
1405 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1406 pr_info("\tEnabled extended descriptors\n");
1407 priv->extend_desc = 1;
1408 } else
1409 pr_warn("Extended descriptors not supported\n");
1410
19e30c14
GC		 1411 priv->hw->desc = &enh_desc_ops;
1412 } else {
1413 pr_info(" Normal descriptors\n");
1414 priv->hw->desc = &ndesc_ops;
1415 }
1416}
1417
1418/**
32ceabca
GC		 1419 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1420 * @priv: driver private structure
19e30c14
GC		 1421 * Description:
1422 * new GMAC chip generations have a new register to indicate the
1423 * presence of the optional feature/functions.
1424 * This can be also used to override the value passed through the
1425 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 1426 */
1427static int stmmac_get_hw_features(struct stmmac_priv *priv)
1428{
5e6efe88 1429 u32 hw_cap = 0;
3c20f72f 1430
5e6efe88
GC		 1431 if (priv->hw->dma->get_hw_feature) {
1432 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
e7434821 1433
1db123fb
RK		 1434 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1435 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1436 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1437 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
ceb69499 1438 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1db123fb
RK		 1439 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1440 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1441 priv->dma_cap.pmt_remote_wake_up =
ceb69499 1442 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1db123fb 1443 priv->dma_cap.pmt_magic_frame =
ceb69499 1444 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
19e30c14 1445 /* MMC */
1db123fb 1446 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
ceb69499 1447 /* IEEE 1588-2002 */
1db123fb 1448 priv->dma_cap.time_stamp =
ceb69499
GC		 1449 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1450 /* IEEE 1588-2008 */
1db123fb 1451 priv->dma_cap.atime_stamp =
ceb69499 1452 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 1453 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 1454 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1455 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 1456 /* TX and RX csum */
1db123fb
RK		 1457 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1458 priv->dma_cap.rx_coe_type1 =
ceb69499 1459 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1db123fb 1460 priv->dma_cap.rx_coe_type2 =
ceb69499 1461 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1db123fb 1462 priv->dma_cap.rxfifo_over_2048 =
ceb69499 1463 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 1464 /* TX and RX number of channels */
1db123fb 1465 priv->dma_cap.number_rx_channel =
ceb69499 1466 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1db123fb 1467 priv->dma_cap.number_tx_channel =
ceb69499
GC		 1468 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1469 /* Alternate (enhanced) DESC mode */
1470 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
19e30c14 1471 }
e7434821
GC		 1472
1473 return hw_cap;
1474}
1475
32ceabca
GC		 1476/**
1477 * stmmac_check_ether_addr: check if the MAC addr is valid
1478 * @priv: driver private structure
1479 * Description:
1480 * it is to verify if the MAC address is valid, in case of failures it
1481 * generates a random MAC address
1482 */
bfab27a1
GC		 1483static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1484{
bfab27a1
GC		 1485 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1486 priv->hw->mac->get_umac_addr((void __iomem *)
1487 priv->dev->base_addr,
1488 priv->dev->dev_addr, 0);
ceb69499 1489 if (!is_valid_ether_addr(priv->dev->dev_addr))
f2cedb63 1490 eth_hw_addr_random(priv->dev);
bfab27a1 1491 }
ceb69499
GC		 1492 pr_warn("%s: device MAC address %pM\n", priv->dev->name,
1493 priv->dev->dev_addr);
bfab27a1
GC		 1494}
1495
32ceabca
GC		 1496/**
1497 * stmmac_init_dma_engine: DMA init.
1498 * @priv: driver private structure
1499 * Description:
1500 * It inits the DMA invoking the specific MAC/GMAC callback.
1501 * Some DMA parameters can be passed from the platform;
1502 * in case of these are not passed a default is kept for the MAC or GMAC.
1503 */
0f1f88a8
GC		 1504static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1505{
1506 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
b9cde0a8 1507 int mixed_burst = 0;
c24602ef 1508 int atds = 0;
0f1f88a8 1509
0f1f88a8
GC		 1510 if (priv->plat->dma_cfg) {
1511 pbl = priv->plat->dma_cfg->pbl;
1512 fixed_burst = priv->plat->dma_cfg->fixed_burst;
b9cde0a8 1513 mixed_burst = priv->plat->dma_cfg->mixed_burst;
0f1f88a8
GC		 1514 burst_len = priv->plat->dma_cfg->burst_len;
1515 }
1516
c24602ef
GC		 1517 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1518 atds = 1;
1519
b9cde0a8 1520 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
0f1f88a8 1521 burst_len, priv->dma_tx_phy,
c24602ef 1522 priv->dma_rx_phy, atds);
0f1f88a8
GC		 1523}
1524
9125cdd1 1525/**
32ceabca 1526 * stmmac_tx_timer: mitigation sw timer for tx.
9125cdd1
GC		 1527 * @data: data pointer
1528 * Description:
1529 * This is the timer handler to directly invoke the stmmac_tx_clean.
1530 */
1531static void stmmac_tx_timer(unsigned long data)
1532{
1533 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1534
1535 stmmac_tx_clean(priv);
1536}
1537
1538/**
32ceabca
GC		 1539 * stmmac_init_tx_coalesce: init tx mitigation options.
1540 * @priv: driver private structure
9125cdd1
GC		 1541 * Description:
1542 * This inits the transmit coalesce parameters: i.e. timer rate,
1543 * timer handler and default threshold used for enabling the
1544 * interrupt on completion bit.
1545 */
1546static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1547{
1548 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1549 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1550 init_timer(&priv->txtimer);
1551 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1552 priv->txtimer.data = (unsigned long)priv;
1553 priv->txtimer.function = stmmac_tx_timer;
1554 add_timer(&priv->txtimer);
1555}
1556
47dd7a54
GC		 1557/**
1558 * stmmac_open - open entry point of the driver
1559 * @dev : pointer to the device structure.
1560 * Description:
1561 * This function is the open entry point of the driver.
1562 * Return value:
1563 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1564 * file on failure.
1565 */
1566static int stmmac_open(struct net_device *dev)
1567{
1568 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1569 int ret;
1570
a630844d 1571 clk_prepare_enable(priv->stmmac_clk);
4bfcbd7a
FV		 1572
1573 stmmac_check_ether_addr(priv);
1574
4d8f0825
BA		 1575 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1576 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 1577 ret = stmmac_init_phy(dev);
1578 if (ret) {
1579 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1580 __func__, ret);
1581 goto open_error;
1582 }
f66ffe28 1583 }
47dd7a54
GC		 1584
1585 /* Create and initialize the TX/RX descriptors chains. */
1586 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1587 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1588 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1589 init_dma_desc_rings(dev);
1590
1591 /* DMA initialization and SW reset */
0f1f88a8 1592 ret = stmmac_init_dma_engine(priv);
f66ffe28 1593 if (ret < 0) {
47dd7a54 1594 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 1595 goto open_error;
47dd7a54
GC		 1596 }
1597
1598 /* Copy the MAC addr into the HW */
ad01b7d4 1599 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
cf3f047b 1600
ca5f12c1 1601 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 1602 if (priv->plat->bus_setup)
1603 priv->plat->bus_setup(priv->ioaddr);
cf3f047b 1604
47dd7a54 1605 /* Initialize the MAC Core */
ad01b7d4 1606 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 1607
f66ffe28
GC		 1608 /* Request the IRQ lines */
1609 ret = request_irq(dev->irq, stmmac_interrupt,
ceb69499 1610 IRQF_SHARED, dev->name, dev);
f66ffe28
GC		 1611 if (unlikely(ret < 0)) {
1612 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1613 __func__, dev->irq, ret);
1614 goto open_error;
1615 }
1616
7a13f8f5
FV		 1617 /* Request the Wake IRQ in case of another line is used for WoL */
1618 if (priv->wol_irq != dev->irq) {
1619 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1620 IRQF_SHARED, dev->name, dev);
1621 if (unlikely(ret < 0)) {
ceb69499
GC		 1622 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1623 __func__, priv->wol_irq, ret);
7a13f8f5
FV		 1624 goto open_error_wolirq;
1625 }
1626 }
1627
d765955d
GC		 1628 /* Request the IRQ lines */
1629 if (priv->lpi_irq != -ENXIO) {
1630 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1631 dev->name, dev);
1632 if (unlikely(ret < 0)) {
1633 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1634 __func__, priv->lpi_irq, ret);
1635 goto open_error_lpiirq;
1636 }
1637 }
1638
47dd7a54 1639 /* Enable the MAC Rx/Tx */
bfab27a1 1640 stmmac_set_mac(priv->ioaddr, true);
47dd7a54
GC		 1641
1642 /* Set the HW DMA mode and the COE */
1643 stmmac_dma_operation_mode(priv);
1644
1645 /* Extra statistics */
1646 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1647 priv->xstats.threshold = tc;
1648
4f795b25 1649 stmmac_mmc_setup(priv);
1c901a46 1650
92ba6888
RK		 1651 ret = stmmac_init_ptp(priv);
1652 if (ret)
1653 pr_warn("%s: failed PTP initialisation\n", __func__);
891434b1 1654
bfab27a1
GC		 1655#ifdef CONFIG_STMMAC_DEBUG_FS
1656 ret = stmmac_init_fs(dev);
1657 if (ret < 0)
ceb69499 1658 pr_warn("%s: failed debugFS registration\n", __func__);
bfab27a1 1659#endif
47dd7a54
GC		 1660 /* Start the ball rolling... */
1661 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 1662 priv->hw->dma->start_tx(priv->ioaddr);
1663 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54 1664
47dd7a54
GC		 1665 /* Dump DMA/MAC registers */
1666 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 1667 priv->hw->mac->dump_regs(priv->ioaddr);
1668 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 1669 }
1670
1671 if (priv->phydev)
1672 phy_start(priv->phydev);
1673
d765955d 1674 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
e58bb43f
GC		 1675
1676 /* Using PCS we cannot dial with the phy registers at this stage
1677 * so we do not support extra feature like EEE.
1678 */
4d8f0825
BA		 1679 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1680 priv->pcs != STMMAC_PCS_RTBI)
e58bb43f 1681 priv->eee_enabled = stmmac_eee_init(priv);
d765955d 1682
9125cdd1
GC		 1683 stmmac_init_tx_coalesce(priv);
1684
62a2ab93
GC		 1685 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1686 priv->rx_riwt = MAX_DMA_RIWT;
1687 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1688 }
1689
e58bb43f
GC		 1690 if (priv->pcs && priv->hw->mac->ctrl_ane)
1691 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1692
47dd7a54 1693 napi_enable(&priv->napi);
47dd7a54 1694 netif_start_queue(dev);
f66ffe28 1695
47dd7a54 1696 return 0;
f66ffe28 1697
d765955d
GC		 1698open_error_lpiirq:
1699 if (priv->wol_irq != dev->irq)
1700 free_irq(priv->wol_irq, dev);
1701
7a13f8f5
FV		 1702open_error_wolirq:
1703 free_irq(dev->irq, dev);
1704
f66ffe28 1705open_error:
f66ffe28
GC		 1706 if (priv->phydev)
1707 phy_disconnect(priv->phydev);
1708
a630844d 1709 clk_disable_unprepare(priv->stmmac_clk);
4bfcbd7a 1710
f66ffe28 1711 return ret;
47dd7a54
GC		 1712}
1713
1714/**
1715 * stmmac_release - close entry point of the driver
1716 * @dev : device pointer.
1717 * Description:
1718 * This is the stop entry point of the driver.
1719 */
1720static int stmmac_release(struct net_device *dev)
1721{
1722 struct stmmac_priv *priv = netdev_priv(dev);
1723
d765955d
GC		 1724 if (priv->eee_enabled)
1725 del_timer_sync(&priv->eee_ctrl_timer);
1726
47dd7a54
GC		 1727 /* Stop and disconnect the PHY */
1728 if (priv->phydev) {
1729 phy_stop(priv->phydev);
1730 phy_disconnect(priv->phydev);
1731 priv->phydev = NULL;
1732 }
1733
1734 netif_stop_queue(dev);
1735
47dd7a54 1736 napi_disable(&priv->napi);
47dd7a54 1737
9125cdd1
GC		 1738 del_timer_sync(&priv->txtimer);
1739
47dd7a54
GC		 1740 /* Free the IRQ lines */
1741 free_irq(dev->irq, dev);
7a13f8f5
FV		 1742 if (priv->wol_irq != dev->irq)
1743 free_irq(priv->wol_irq, dev);
d765955d
GC		 1744 if (priv->lpi_irq != -ENXIO)
1745 free_irq(priv->lpi_irq, dev);
47dd7a54
GC		 1746
1747 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1748 priv->hw->dma->stop_tx(priv->ioaddr);
1749 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1750
1751 /* Release and free the Rx/Tx resources */
1752 free_dma_desc_resources(priv);
1753
19449bfc 1754 /* Disable the MAC Rx/Tx */
bfab27a1 1755 stmmac_set_mac(priv->ioaddr, false);
47dd7a54
GC		 1756
1757 netif_carrier_off(dev);
1758
bfab27a1
GC		 1759#ifdef CONFIG_STMMAC_DEBUG_FS
1760 stmmac_exit_fs();
1761#endif
a630844d 1762 clk_disable_unprepare(priv->stmmac_clk);
bfab27a1 1763
92ba6888
RK		 1764 stmmac_release_ptp(priv);
1765
47dd7a54
GC		 1766 return 0;
1767}
1768
47dd7a54 1769/**
32ceabca 1770 * stmmac_xmit: Tx entry point of the driver
47dd7a54
GC		 1771 * @skb : the socket buffer
1772 * @dev : device pointer
32ceabca
GC		 1773 * Description : this is the tx entry point of the driver.
1774 * It programs the chain or the ring and supports oversized frames
1775 * and SG feature.
47dd7a54
GC		 1776 */
1777static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1778{
1779 struct stmmac_priv *priv = netdev_priv(dev);
1780 unsigned int txsize = priv->dma_tx_size;
1781 unsigned int entry;
4a7d666a 1782 int i, csum_insertion = 0, is_jumbo = 0;
47dd7a54
GC		 1783 int nfrags = skb_shinfo(skb)->nr_frags;
1784 struct dma_desc *desc, *first;
286a8372 1785 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1786
1787 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1788 if (!netif_queue_stopped(dev)) {
1789 netif_stop_queue(dev);
1790 /* This is a hard error, log it. */
ceb69499 1791 pr_err("%s: Tx Ring full when queue awake\n", __func__);
47dd7a54
GC		 1792 }
1793 return NETDEV_TX_BUSY;
1794 }
1795
a9097a96
GC		 1796 spin_lock(&priv->tx_lock);
1797
d765955d
GC		 1798 if (priv->tx_path_in_lpi_mode)
1799 stmmac_disable_eee_mode(priv);
1800
47dd7a54
GC		 1801 entry = priv->cur_tx % txsize;
1802
1803#ifdef STMMAC_XMIT_DEBUG
1804 if ((skb->len > ETH_FRAME_LEN) || nfrags)
ceb69499 1805 pr_debug("%s: [entry %d]: skb addr %p len: %d nopagedlen: %d\n"
9125cdd1 1806 "\tn_frags: %d - ip_summed: %d - %s gso\n"
ceb69499 1807 "\ttx_count_frames %d\n", __func__, entry,
9125cdd1
GC		 1808 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1809 !skb_is_gso(skb) ? "isn't" : "is",
1810 priv->tx_count_frames);
47dd7a54
GC		 1811#endif
1812
5e982f3b 1813 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54 1814
c24602ef 1815 if (priv->extend_desc)
ceb69499 1816 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1817 else
1818 desc = priv->dma_tx + entry;
1819
47dd7a54
GC		 1820 first = desc;
1821
1822#ifdef STMMAC_XMIT_DEBUG
1823 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
9125cdd1
GC		 1824 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1825 "\t\tn_frags: %d, ip_summed: %d\n",
1826 skb->len, nopaged_len, nfrags, skb->ip_summed);
47dd7a54
GC		 1827#endif
1828 priv->tx_skbuff[entry] = skb;
286a8372 1829
4a7d666a
GC		 1830 /* To program the descriptors according to the size of the frame */
1831 if (priv->mode == STMMAC_RING_MODE) {
1832 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1833 priv->plat->enh_desc);
1834 if (unlikely(is_jumbo))
1835 entry = priv->hw->ring->jumbo_frm(priv, skb,
1836 csum_insertion);
47dd7a54 1837 } else {
4a7d666a 1838 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
ceb69499 1839 priv->plat->enh_desc);
4a7d666a
GC		 1840 if (unlikely(is_jumbo))
1841 entry = priv->hw->chain->jumbo_frm(priv, skb,
1842 csum_insertion);
1843 }
1844 if (likely(!is_jumbo)) {
47dd7a54 1845 desc->des2 = dma_map_single(priv->device, skb->data,
ceb69499 1846 nopaged_len, DMA_TO_DEVICE);
cf32deec 1847 priv->tx_skbuff_dma[entry] = desc->des2;
db98a0b0 1848 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
4a7d666a
GC		 1849 csum_insertion, priv->mode);
1850 } else
c24602ef 1851 desc = first;
47dd7a54
GC		 1852
1853 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1854 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1855 int len = skb_frag_size(frag);
47dd7a54
GC		 1856
1857 entry = (++priv->cur_tx) % txsize;
c24602ef 1858 if (priv->extend_desc)
ceb69499 1859 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1860 else
1861 desc = priv->dma_tx + entry;
47dd7a54
GC		 1862
1863 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1864 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1865 DMA_TO_DEVICE);
cf32deec 1866 priv->tx_skbuff_dma[entry] = desc->des2;
47dd7a54 1867 priv->tx_skbuff[entry] = NULL;
4a7d666a
GC		 1868 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1869 priv->mode);
eb0dc4bb 1870 wmb();
db98a0b0 1871 priv->hw->desc->set_tx_owner(desc);
8e839891 1872 wmb();
47dd7a54
GC		 1873 }
1874
9125cdd1 1875 /* Finalize the latest segment. */
db98a0b0 1876 priv->hw->desc->close_tx_desc(desc);
73cfe264 1877
eb0dc4bb 1878 wmb();
9125cdd1
GC		 1879 /* According to the coalesce parameter the IC bit for the latest
1880 * segment could be reset and the timer re-started to invoke the
1881 * stmmac_tx function. This approach takes care about the fragments.
1882 */
1883 priv->tx_count_frames += nfrags + 1;
1884 if (priv->tx_coal_frames > priv->tx_count_frames) {
1885 priv->hw->desc->clear_tx_ic(desc);
1886 priv->xstats.tx_reset_ic_bit++;
1887 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1888 priv->tx_count_frames);
1889 mod_timer(&priv->txtimer,
1890 STMMAC_COAL_TIMER(priv->tx_coal_timer));
1891 } else
1892 priv->tx_count_frames = 0;
eb0dc4bb 1893
47dd7a54 1894 /* To avoid raise condition */
db98a0b0 1895 priv->hw->desc->set_tx_owner(first);
8e839891 1896 wmb();
47dd7a54
GC		 1897
1898 priv->cur_tx++;
1899
1900#ifdef STMMAC_XMIT_DEBUG
1901 if (netif_msg_pktdata(priv)) {
631f24a2 1902 pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
ceb69499
GC		 1903 __func__, (priv->cur_tx % txsize),
1904 (priv->dirty_tx % txsize), entry, first, nfrags);
c24602ef
GC		 1905 if (priv->extend_desc)
1906 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1907 else
1908 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1909
47dd7a54
GC		 1910 pr_info(">>> frame to be transmitted: ");
1911 print_pkt(skb->data, skb->len);
1912 }
1913#endif
1914 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1915 TX_DBG("%s: stop transmitted packets\n", __func__);
1916 netif_stop_queue(dev);
1917 }
1918
1919 dev->stats.tx_bytes += skb->len;
1920
891434b1
RK		 1921 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1922 priv->hwts_tx_en)) {
1923 /* declare that device is doing timestamping */
1924 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1925 priv->hw->desc->enable_tx_timestamp(first);
1926 }
1927
1928 if (!priv->hwts_tx_en)
1929 skb_tx_timestamp(skb);
3e82ce12 1930
52f64fae
RC		 1931 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1932
a9097a96
GC		 1933 spin_unlock(&priv->tx_lock);
1934
47dd7a54
GC		 1935 return NETDEV_TX_OK;
1936}
1937
32ceabca
GC		 1938/**
1939 * stmmac_rx_refill: refill used skb preallocated buffers
1940 * @priv: driver private structure
1941 * Description : this is to reallocate the skb for the reception process
1942 * that is based on zero-copy.
1943 */
47dd7a54
GC		 1944static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1945{
1946 unsigned int rxsize = priv->dma_rx_size;
1947 int bfsize = priv->dma_buf_sz;
47dd7a54
GC		 1948
1949 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1950 unsigned int entry = priv->dirty_rx % rxsize;
c24602ef
GC		 1951 struct dma_desc *p;
1952
1953 if (priv->extend_desc)
ceb69499 1954 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef
GC		 1955 else
1956 p = priv->dma_rx + entry;
1957
47dd7a54
GC		 1958 if (likely(priv->rx_skbuff[entry] == NULL)) {
1959 struct sk_buff *skb;
1960
acb600de 1961 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
47dd7a54
GC		 1962
1963 if (unlikely(skb == NULL))
1964 break;
1965
1966 priv->rx_skbuff[entry] = skb;
1967 priv->rx_skbuff_dma[entry] =
1968 dma_map_single(priv->device, skb->data, bfsize,
1969 DMA_FROM_DEVICE);
1970
c24602ef 1971 p->des2 = priv->rx_skbuff_dma[entry];
286a8372 1972
891434b1 1973 priv->hw->ring->refill_desc3(priv, p);
286a8372 1974
47dd7a54
GC		 1975 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1976 }
eb0dc4bb 1977 wmb();
c24602ef 1978 priv->hw->desc->set_rx_owner(p);
8e839891 1979 wmb();
47dd7a54 1980 }
47dd7a54
GC		 1981}
1982
32ceabca
GC		 1983/**
1984 * stmmac_rx_refill: refill used skb preallocated buffers
1985 * @priv: driver private structure
1986 * @limit: napi bugget.
1987 * Description : this the function called by the napi poll method.
1988 * It gets all the frames inside the ring.
1989 */
47dd7a54
GC		 1990static int stmmac_rx(struct stmmac_priv *priv, int limit)
1991{
1992 unsigned int rxsize = priv->dma_rx_size;
1993 unsigned int entry = priv->cur_rx % rxsize;
1994 unsigned int next_entry;
1995 unsigned int count = 0;
ceb69499 1996 int coe = priv->plat->rx_coe;
47dd7a54
GC		 1997
1998#ifdef STMMAC_RX_DEBUG
1999 if (netif_msg_hw(priv)) {
2000 pr_debug(">>> stmmac_rx: descriptor ring:\n");
c24602ef 2001 if (priv->extend_desc)
ceb69499 2002 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef
GC		 2003 else
2004 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
47dd7a54
GC		 2005 }
2006#endif
c24602ef 2007 while (count < limit) {
47dd7a54 2008 int status;
9401bb5c 2009 struct dma_desc *p;
47dd7a54 2010
c24602ef 2011 if (priv->extend_desc)
ceb69499 2012 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef 2013 else
ceb69499 2014 p = priv->dma_rx + entry;
c24602ef
GC		 2015
2016 if (priv->hw->desc->get_rx_owner(p))
47dd7a54
GC		 2017 break;
2018
2019 count++;
2020
2021 next_entry = (++priv->cur_rx) % rxsize;
c24602ef 2022 if (priv->extend_desc)
9401bb5c 2023 prefetch(priv->dma_erx + next_entry);
c24602ef 2024 else
9401bb5c 2025 prefetch(priv->dma_rx + next_entry);
47dd7a54
GC		 2026
2027 /* read the status of the incoming frame */
c24602ef
GC		 2028 status = priv->hw->desc->rx_status(&priv->dev->stats,
2029 &priv->xstats, p);
2030 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2031 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2032 &priv->xstats,
2033 priv->dma_erx +
2034 entry);
891434b1 2035 if (unlikely(status == discard_frame)) {
47dd7a54 2036 priv->dev->stats.rx_errors++;
891434b1
RK		 2037 if (priv->hwts_rx_en && !priv->extend_desc) {
2038 /* DESC2 & DESC3 will be overwitten by device
2039 * with timestamp value, hence reinitialize
2040 * them in stmmac_rx_refill() function so that
2041 * device can reuse it.
2042 */
2043 priv->rx_skbuff[entry] = NULL;
2044 dma_unmap_single(priv->device,
ceb69499
GC		 2045 priv->rx_skbuff_dma[entry],
2046 priv->dma_buf_sz,
2047 DMA_FROM_DEVICE);
891434b1
RK		 2048 }
2049 } else {
47dd7a54 2050 struct sk_buff *skb;
3eeb2997 2051 int frame_len;
47dd7a54 2052
ceb69499
GC		 2053 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2054
3eeb2997 2055 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
ceb69499
GC		 2056 * Type frames (LLC/LLC-SNAP)
2057 */
3eeb2997
GC		 2058 if (unlikely(status != llc_snap))
2059 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 2060#ifdef STMMAC_RX_DEBUG
2061 if (frame_len > ETH_FRAME_LEN)
2062 pr_debug("\tRX frame size %d, COE status: %d\n",
ceb69499 2063 frame_len, status);
47dd7a54
GC		 2064
2065 if (netif_msg_hw(priv))
2066 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
ceb69499 2067 p, entry, p->des2);
47dd7a54
GC		 2068#endif
2069 skb = priv->rx_skbuff[entry];
2070 if (unlikely(!skb)) {
2071 pr_err("%s: Inconsistent Rx descriptor chain\n",
ceb69499 2072 priv->dev->name);
47dd7a54
GC		 2073 priv->dev->stats.rx_dropped++;
2074 break;
2075 }
2076 prefetch(skb->data - NET_IP_ALIGN);
2077 priv->rx_skbuff[entry] = NULL;
2078
891434b1
RK		 2079 stmmac_get_rx_hwtstamp(priv, entry, skb);
2080
47dd7a54
GC		 2081 skb_put(skb, frame_len);
2082 dma_unmap_single(priv->device,
2083 priv->rx_skbuff_dma[entry],
2084 priv->dma_buf_sz, DMA_FROM_DEVICE);
2085#ifdef STMMAC_RX_DEBUG
2086 if (netif_msg_pktdata(priv)) {
2087 pr_info(" frame received (%dbytes)", frame_len);
2088 print_pkt(skb->data, frame_len);
2089 }
2090#endif
2091 skb->protocol = eth_type_trans(skb, priv->dev);
2092
ceb69499 2093 if (unlikely(!coe))
bc8acf2c 2094 skb_checksum_none_assert(skb);
62a2ab93 2095 else
47dd7a54 2096 skb->ip_summed = CHECKSUM_UNNECESSARY;
62a2ab93
GC		 2097
2098 napi_gro_receive(&priv->napi, skb);
47dd7a54
GC		 2099
2100 priv->dev->stats.rx_packets++;
2101 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 2102 }
2103 entry = next_entry;
47dd7a54
GC		 2104 }
2105
2106 stmmac_rx_refill(priv);
2107
2108 priv->xstats.rx_pkt_n += count;
2109
2110 return count;
2111}
2112
2113/**
2114 * stmmac_poll - stmmac poll method (NAPI)
2115 * @napi : pointer to the napi structure.
2116 * @budget : maximum number of packets that the current CPU can receive from
2117 * all interfaces.
2118 * Description :
9125cdd1 2119 * To look at the incoming frames and clear the tx resources.
47dd7a54
GC		 2120 */
2121static int stmmac_poll(struct napi_struct *napi, int budget)
2122{
2123 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2124 int work_done = 0;
2125
9125cdd1
GC		 2126 priv->xstats.napi_poll++;
2127 stmmac_tx_clean(priv);
47dd7a54 2128
9125cdd1 2129 work_done = stmmac_rx(priv, budget);
47dd7a54
GC		 2130 if (work_done < budget) {
2131 napi_complete(napi);
9125cdd1 2132 stmmac_enable_dma_irq(priv);
47dd7a54
GC		 2133 }
2134 return work_done;
2135}
2136
2137/**
2138 * stmmac_tx_timeout
2139 * @dev : Pointer to net device structure
2140 * Description: this function is called when a packet transmission fails to
7284a3f1 2141 * complete within a reasonable time. The driver will mark the error in the
47dd7a54
GC		 2142 * netdev structure and arrange for the device to be reset to a sane state
2143 * in order to transmit a new packet.
2144 */
2145static void stmmac_tx_timeout(struct net_device *dev)
2146{
2147 struct stmmac_priv *priv = netdev_priv(dev);
2148
2149 /* Clear Tx resources and restart transmitting again */
2150 stmmac_tx_err(priv);
47dd7a54
GC		 2151}
2152
2153/* Configuration changes (passed on by ifconfig) */
2154static int stmmac_config(struct net_device *dev, struct ifmap *map)
2155{
2156 if (dev->flags & IFF_UP) /* can't act on a running interface */
2157 return -EBUSY;
2158
2159 /* Don't allow changing the I/O address */
2160 if (map->base_addr != dev->base_addr) {
ceb69499 2161 pr_warn("%s: can't change I/O address\n", dev->name);
47dd7a54
GC		 2162 return -EOPNOTSUPP;
2163 }
2164
2165 /* Don't allow changing the IRQ */
2166 if (map->irq != dev->irq) {
ceb69499 2167 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
47dd7a54
GC		 2168 return -EOPNOTSUPP;
2169 }
2170
47dd7a54
GC		 2171 return 0;
2172}
2173
2174/**
01789349 2175 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 2176 * @dev : pointer to the device structure
2177 * Description:
2178 * This function is a driver entry point which gets called by the kernel
2179 * whenever multicast addresses must be enabled/disabled.
2180 * Return value:
2181 * void.
2182 */
01789349 2183static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 2184{
2185 struct stmmac_priv *priv = netdev_priv(dev);
2186
2187 spin_lock(&priv->lock);
cffb13f4 2188 priv->hw->mac->set_filter(dev, priv->synopsys_id);
47dd7a54 2189 spin_unlock(&priv->lock);
47dd7a54
GC		 2190}
2191
2192/**
2193 * stmmac_change_mtu - entry point to change MTU size for the device.
2194 * @dev : device pointer.
2195 * @new_mtu : the new MTU size for the device.
2196 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2197 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2198 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2199 * Return value:
2200 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2201 * file on failure.
2202 */
2203static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2204{
2205 struct stmmac_priv *priv = netdev_priv(dev);
2206 int max_mtu;
2207
2208 if (netif_running(dev)) {
2209 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2210 return -EBUSY;
2211 }
2212
48febf7e 2213 if (priv->plat->enh_desc)
47dd7a54
GC		 2214 max_mtu = JUMBO_LEN;
2215 else
45db81e1 2216 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54
GC		 2217
2218 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2219 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2220 return -EINVAL;
2221 }
2222
5e982f3b
MM		 2223 dev->mtu = new_mtu;
2224 netdev_update_features(dev);
2225
2226 return 0;
2227}
2228
c8f44aff 2229static netdev_features_t stmmac_fix_features(struct net_device *dev,
ceb69499 2230 netdev_features_t features)
5e982f3b
MM		 2231{
2232 struct stmmac_priv *priv = netdev_priv(dev);
2233
38912bdb 2234 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5e982f3b 2235 features &= ~NETIF_F_RXCSUM;
38912bdb
DS		 2236 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2237 features &= ~NETIF_F_IPV6_CSUM;
5e982f3b
MM		 2238 if (!priv->plat->tx_coe)
2239 features &= ~NETIF_F_ALL_CSUM;
2240
ebbb293f
GC		 2241 /* Some GMAC devices have a bugged Jumbo frame support that
2242 * needs to have the Tx COE disabled for oversized frames
2243 * (due to limited buffer sizes). In this case we disable
ceb69499
GC		 2244 * the TX csum insertionin the TDES and not use SF.
2245 */
5e982f3b
MM		 2246 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2247 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 2248
5e982f3b 2249 return features;
47dd7a54
GC		 2250}
2251
32ceabca
GC		 2252/**
2253 * stmmac_interrupt - main ISR
2254 * @irq: interrupt number.
2255 * @dev_id: to pass the net device pointer.
2256 * Description: this is the main driver interrupt service routine.
2257 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2258 * interrupts.
2259 */
47dd7a54
GC		 2260static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2261{
2262 struct net_device *dev = (struct net_device *)dev_id;
2263 struct stmmac_priv *priv = netdev_priv(dev);
2264
2265 if (unlikely(!dev)) {
2266 pr_err("%s: invalid dev pointer\n", __func__);
2267 return IRQ_NONE;
2268 }
2269
d765955d
GC		 2270 /* To handle GMAC own interrupts */
2271 if (priv->plat->has_gmac) {
2272 int status = priv->hw->mac->host_irq_status((void __iomem *)
0982a0f6
GC		 2273 dev->base_addr,
2274 &priv->xstats);
d765955d 2275 if (unlikely(status)) {
d765955d 2276 /* For LPI we need to save the tx status */
0982a0f6 2277 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
d765955d 2278 priv->tx_path_in_lpi_mode = true;
0982a0f6 2279 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
d765955d 2280 priv->tx_path_in_lpi_mode = false;
d765955d
GC		 2281 }
2282 }
aec7ff27 2283
d765955d 2284 /* To handle DMA interrupts */
aec7ff27 2285 stmmac_dma_interrupt(priv);
47dd7a54
GC		 2286
2287 return IRQ_HANDLED;
2288}
2289
2290#ifdef CONFIG_NET_POLL_CONTROLLER
2291/* Polling receive - used by NETCONSOLE and other diagnostic tools
ceb69499
GC		 2292 * to allow network I/O with interrupts disabled.
2293 */
47dd7a54
GC		 2294static void stmmac_poll_controller(struct net_device *dev)
2295{
2296 disable_irq(dev->irq);
2297 stmmac_interrupt(dev->irq, dev);
2298 enable_irq(dev->irq);
2299}
2300#endif
2301
2302/**
2303 * stmmac_ioctl - Entry point for the Ioctl
2304 * @dev: Device pointer.
2305 * @rq: An IOCTL specefic structure, that can contain a pointer to
2306 * a proprietary structure used to pass information to the driver.
2307 * @cmd: IOCTL command
2308 * Description:
32ceabca 2309 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
47dd7a54
GC		 2310 */
2311static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2312{
2313 struct stmmac_priv *priv = netdev_priv(dev);
891434b1 2314 int ret = -EOPNOTSUPP;
47dd7a54
GC		 2315
2316 if (!netif_running(dev))
2317 return -EINVAL;
2318
891434b1
RK		 2319 switch (cmd) {
2320 case SIOCGMIIPHY:
2321 case SIOCGMIIREG:
2322 case SIOCSMIIREG:
2323 if (!priv->phydev)
2324 return -EINVAL;
2325 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2326 break;
2327 case SIOCSHWTSTAMP:
2328 ret = stmmac_hwtstamp_ioctl(dev, rq);
2329 break;
2330 default:
2331 break;
2332 }
28b04113 2333
47dd7a54
GC		 2334 return ret;
2335}
2336
7ac29055
GC		 2337#ifdef CONFIG_STMMAC_DEBUG_FS
2338static struct dentry *stmmac_fs_dir;
2339static struct dentry *stmmac_rings_status;
e7434821 2340static struct dentry *stmmac_dma_cap;
7ac29055 2341
c24602ef 2342static void sysfs_display_ring(void *head, int size, int extend_desc,
ceb69499 2343 struct seq_file *seq)
7ac29055 2344{
7ac29055 2345 int i;
ceb69499
GC		 2346 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2347 struct dma_desc *p = (struct dma_desc *)head;
7ac29055 2348
c24602ef
GC		 2349 for (i = 0; i < size; i++) {
2350 u64 x;
2351 if (extend_desc) {
2352 x = *(u64 *) ep;
2353 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2354 i, (unsigned int)virt_to_phys(ep),
2355 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2356 ep->basic.des2, ep->basic.des3);
2357 ep++;
2358 } else {
2359 x = *(u64 *) p;
2360 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2361 i, (unsigned int)virt_to_phys(ep),
2362 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2363 p->des2, p->des3);
2364 p++;
2365 }
7ac29055
GC		 2366 seq_printf(seq, "\n");
2367 }
c24602ef 2368}
7ac29055 2369
c24602ef
GC		 2370static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2371{
2372 struct net_device *dev = seq->private;
2373 struct stmmac_priv *priv = netdev_priv(dev);
2374 unsigned int txsize = priv->dma_tx_size;
2375 unsigned int rxsize = priv->dma_rx_size;
7ac29055 2376
c24602ef
GC		 2377 if (priv->extend_desc) {
2378 seq_printf(seq, "Extended RX descriptor ring:\n");
ceb69499 2379 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
c24602ef 2380 seq_printf(seq, "Extended TX descriptor ring:\n");
ceb69499 2381 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
c24602ef
GC		 2382 } else {
2383 seq_printf(seq, "RX descriptor ring:\n");
2384 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2385 seq_printf(seq, "TX descriptor ring:\n");
2386 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
7ac29055
GC		 2387 }
2388
2389 return 0;
2390}
2391
2392static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2393{
2394 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2395}
2396
2397static const struct file_operations stmmac_rings_status_fops = {
2398 .owner = THIS_MODULE,
2399 .open = stmmac_sysfs_ring_open,
2400 .read = seq_read,
2401 .llseek = seq_lseek,
74863948 2402 .release = single_release,
7ac29055
GC		 2403};
2404
e7434821
GC		 2405static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2406{
2407 struct net_device *dev = seq->private;
2408 struct stmmac_priv *priv = netdev_priv(dev);
2409
19e30c14 2410 if (!priv->hw_cap_support) {
e7434821
GC		 2411 seq_printf(seq, "DMA HW features not supported\n");
2412 return 0;
2413 }
2414
2415 seq_printf(seq, "==============================\n");
2416 seq_printf(seq, "\tDMA HW features\n");
2417 seq_printf(seq, "==============================\n");
2418
2419 seq_printf(seq, "\t10/100 Mbps %s\n",
2420 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2421 seq_printf(seq, "\t1000 Mbps %s\n",
2422 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2423 seq_printf(seq, "\tHalf duple %s\n",
2424 (priv->dma_cap.half_duplex) ? "Y" : "N");
2425 seq_printf(seq, "\tHash Filter: %s\n",
2426 (priv->dma_cap.hash_filter) ? "Y" : "N");
2427 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2428 (priv->dma_cap.multi_addr) ? "Y" : "N");
2429 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2430 (priv->dma_cap.pcs) ? "Y" : "N");
2431 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2432 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2433 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2434 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2435 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2436 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2437 seq_printf(seq, "\tRMON module: %s\n",
2438 (priv->dma_cap.rmon) ? "Y" : "N");
2439 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2440 (priv->dma_cap.time_stamp) ? "Y" : "N");
2441 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2442 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2443 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2444 (priv->dma_cap.eee) ? "Y" : "N");
2445 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2446 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2447 (priv->dma_cap.tx_coe) ? "Y" : "N");
2448 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2449 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2450 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2451 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2452 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2453 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2454 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2455 priv->dma_cap.number_rx_channel);
2456 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2457 priv->dma_cap.number_tx_channel);
2458 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2459 (priv->dma_cap.enh_desc) ? "Y" : "N");
2460
2461 return 0;
2462}
2463
2464static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2465{
2466 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2467}
2468
2469static const struct file_operations stmmac_dma_cap_fops = {
2470 .owner = THIS_MODULE,
2471 .open = stmmac_sysfs_dma_cap_open,
2472 .read = seq_read,
2473 .llseek = seq_lseek,
74863948 2474 .release = single_release,
e7434821
GC		 2475};
2476
7ac29055
GC		 2477static int stmmac_init_fs(struct net_device *dev)
2478{
2479 /* Create debugfs entries */
2480 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2481
2482 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2483 pr_err("ERROR %s, debugfs create directory failed\n",
2484 STMMAC_RESOURCE_NAME);
2485
2486 return -ENOMEM;
2487 }
2488
2489 /* Entry to report DMA RX/TX rings */
2490 stmmac_rings_status = debugfs_create_file("descriptors_status",
ceb69499
GC		 2491 S_IRUGO, stmmac_fs_dir, dev,
2492 &stmmac_rings_status_fops);
7ac29055
GC		 2493
2494 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2495 pr_info("ERROR creating stmmac ring debugfs file\n");
2496 debugfs_remove(stmmac_fs_dir);
2497
2498 return -ENOMEM;
2499 }
2500
e7434821
GC		 2501 /* Entry to report the DMA HW features */
2502 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2503 dev, &stmmac_dma_cap_fops);
2504
2505 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2506 pr_info("ERROR creating stmmac MMC debugfs file\n");
2507 debugfs_remove(stmmac_rings_status);
2508 debugfs_remove(stmmac_fs_dir);
2509
2510 return -ENOMEM;
2511 }
2512
7ac29055
GC		 2513 return 0;
2514}
2515
2516static void stmmac_exit_fs(void)
2517{
2518 debugfs_remove(stmmac_rings_status);
e7434821 2519 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 2520 debugfs_remove(stmmac_fs_dir);
2521}
2522#endif /* CONFIG_STMMAC_DEBUG_FS */
2523
47dd7a54
GC		 2524static const struct net_device_ops stmmac_netdev_ops = {
2525 .ndo_open = stmmac_open,
2526 .ndo_start_xmit = stmmac_xmit,
2527 .ndo_stop = stmmac_release,
2528 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 2529 .ndo_fix_features = stmmac_fix_features,
01789349 2530 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 2531 .ndo_tx_timeout = stmmac_tx_timeout,
2532 .ndo_do_ioctl = stmmac_ioctl,
2533 .ndo_set_config = stmmac_config,
47dd7a54
GC		 2534#ifdef CONFIG_NET_POLL_CONTROLLER
2535 .ndo_poll_controller = stmmac_poll_controller,
2536#endif
2537 .ndo_set_mac_address = eth_mac_addr,
2538};
2539
cf3f047b
GC		 2540/**
2541 * stmmac_hw_init - Init the MAC device
32ceabca 2542 * @priv: driver private structure
cf3f047b
GC		 2543 * Description: this function detects which MAC device
2544 * (GMAC/MAC10-100) has to attached, checks the HW capability
2545 * (if supported) and sets the driver's features (for example
2546 * to use the ring or chaine mode or support the normal/enh
2547 * descriptor structure).
2548 */
2549static int stmmac_hw_init(struct stmmac_priv *priv)
2550{
c24602ef 2551 int ret;
cf3f047b
GC		 2552 struct mac_device_info *mac;
2553
2554 /* Identify the MAC HW device */
03f2eecd
MKB		 2555 if (priv->plat->has_gmac) {
2556 priv->dev->priv_flags |= IFF_UNICAST_FLT;
cf3f047b 2557 mac = dwmac1000_setup(priv->ioaddr);
03f2eecd 2558 } else {
cf3f047b 2559 mac = dwmac100_setup(priv->ioaddr);
03f2eecd 2560 }
cf3f047b
GC		 2561 if (!mac)
2562 return -ENOMEM;
2563
2564 priv->hw = mac;
2565
cf3f047b 2566 /* Get and dump the chip ID */
cffb13f4 2567 priv->synopsys_id = stmmac_get_synopsys_id(priv);
cf3f047b 2568
4a7d666a 2569 /* To use the chained or ring mode */
ceb69499 2570 if (chain_mode) {
4a7d666a
GC		 2571 priv->hw->chain = &chain_mode_ops;
2572 pr_info(" Chain mode enabled\n");
2573 priv->mode = STMMAC_CHAIN_MODE;
2574 } else {
2575 priv->hw->ring = &ring_mode_ops;
2576 pr_info(" Ring mode enabled\n");
2577 priv->mode = STMMAC_RING_MODE;
2578 }
2579
cf3f047b
GC		 2580 /* Get the HW capability (new GMAC newer than 3.50a) */
2581 priv->hw_cap_support = stmmac_get_hw_features(priv);
2582 if (priv->hw_cap_support) {
2583 pr_info(" DMA HW capability register supported");
2584
2585 /* We can override some gmac/dma configuration fields: e.g.
2586 * enh_desc, tx_coe (e.g. that are passed through the
2587 * platform) with the values from the HW capability
2588 * register (if supported).
2589 */
2590 priv->plat->enh_desc = priv->dma_cap.enh_desc;
cf3f047b 2591 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
38912bdb
DS		 2592
2593 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2594
2595 if (priv->dma_cap.rx_coe_type2)
2596 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2597 else if (priv->dma_cap.rx_coe_type1)
2598 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2599
cf3f047b
GC		 2600 } else
2601 pr_info(" No HW DMA feature register supported");
2602
61369d02
BA		 2603 /* To use alternate (extended) or normal descriptor structures */
2604 stmmac_selec_desc_mode(priv);
2605
38912bdb
DS		 2606 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2607 if (!ret) {
ceb69499 2608 pr_warn(" RX IPC Checksum Offload not configured.\n");
38912bdb
DS		 2609 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2610 }
2611
2612 if (priv->plat->rx_coe)
2613 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2614 priv->plat->rx_coe);
cf3f047b
GC		 2615 if (priv->plat->tx_coe)
2616 pr_info(" TX Checksum insertion supported\n");
2617
2618 if (priv->plat->pmt) {
2619 pr_info(" Wake-Up On Lan supported\n");
2620 device_set_wakeup_capable(priv->device, 1);
2621 }
2622
c24602ef 2623 return 0;
cf3f047b
GC		 2624}
2625
47dd7a54 2626/**
bfab27a1
GC		 2627 * stmmac_dvr_probe
2628 * @device: device pointer
ff3dd78c
GC		 2629 * @plat_dat: platform data pointer
2630 * @addr: iobase memory address
bfab27a1
GC		 2631 * Description: this is the main probe function used to
2632 * call the alloc_etherdev, allocate the priv structure.
47dd7a54 2633 */
bfab27a1 2634struct stmmac_priv *stmmac_dvr_probe(struct device *device,
cf3f047b
GC		 2635 struct plat_stmmacenet_data *plat_dat,
2636 void __iomem *addr)
47dd7a54
GC		 2637{
2638 int ret = 0;
bfab27a1
GC		 2639 struct net_device *ndev = NULL;
2640 struct stmmac_priv *priv;
47dd7a54 2641
bfab27a1 2642 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
41de8d4c 2643 if (!ndev)
bfab27a1 2644 return NULL;
bfab27a1
GC		 2645
2646 SET_NETDEV_DEV(ndev, device);
2647
2648 priv = netdev_priv(ndev);
2649 priv->device = device;
2650 priv->dev = ndev;
47dd7a54 2651
bfab27a1 2652 ether_setup(ndev);
47dd7a54 2653
bfab27a1 2654 stmmac_set_ethtool_ops(ndev);
cf3f047b
GC		 2655 priv->pause = pause;
2656 priv->plat = plat_dat;
2657 priv->ioaddr = addr;
2658 priv->dev->base_addr = (unsigned long)addr;
2659
2660 /* Verify driver arguments */
2661 stmmac_verify_args();
bfab27a1 2662
cf3f047b 2663 /* Override with kernel parameters if supplied XXX CRS XXX
ceb69499
GC		 2664 * this needs to have multiple instances
2665 */
cf3f047b
GC		 2666 if ((phyaddr >= 0) && (phyaddr <= 31))
2667 priv->plat->phy_addr = phyaddr;
2668
2669 /* Init MAC and get the capabilities */
c24602ef
GC		 2670 ret = stmmac_hw_init(priv);
2671 if (ret)
2672 goto error_free_netdev;
cf3f047b
GC		 2673
2674 ndev->netdev_ops = &stmmac_netdev_ops;
bfab27a1 2675
cf3f047b
GC		 2676 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2677 NETIF_F_RXCSUM;
bfab27a1
GC		 2678 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2679 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
47dd7a54
GC		 2680#ifdef STMMAC_VLAN_TAG_USED
2681 /* Both mac100 and gmac support receive VLAN tag detection */
f646968f 2682 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
47dd7a54
GC		 2683#endif
2684 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2685
47dd7a54
GC		 2686 if (flow_ctrl)
2687 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2688
62a2ab93
GC		 2689 /* Rx Watchdog is available in the COREs newer than the 3.40.
2690 * In some case, for example on bugged HW this feature
2691 * has to be disable and this can be done by passing the
2692 * riwt_off field from the platform.
2693 */
2694 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2695 priv->use_riwt = 1;
2696 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2697 }
2698
bfab27a1 2699 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
47dd7a54 2700
f8e96161 2701 spin_lock_init(&priv->lock);
a9097a96 2702 spin_lock_init(&priv->tx_lock);
f8e96161 2703
bfab27a1 2704 ret = register_netdev(ndev);
47dd7a54 2705 if (ret) {
cf3f047b 2706 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
6a81c26f 2707 goto error_netdev_register;
47dd7a54
GC		 2708 }
2709
ae4d8cf2 2710 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
6a81c26f 2711 if (IS_ERR(priv->stmmac_clk)) {
ceb69499 2712 pr_warn("%s: warning: cannot get CSR clock\n", __func__);
6a81c26f
VK		 2713 goto error_clk_get;
2714 }
ba1377ff 2715
cd7201f4
GC		 2716 /* If a specific clk_csr value is passed from the platform
2717 * this means that the CSR Clock Range selection cannot be
2718 * changed at run-time and it is fixed. Viceversa the driver'll try to
2719 * set the MDC clock dynamically according to the csr actual
2720 * clock input.
2721 */
2722 if (!priv->plat->clk_csr)
2723 stmmac_clk_csr_set(priv);
2724 else
2725 priv->clk_csr = priv->plat->clk_csr;
2726
e58bb43f
GC		 2727 stmmac_check_pcs_mode(priv);
2728
4d8f0825
BA		 2729 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2730 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 2731 /* MDIO bus Registration */
2732 ret = stmmac_mdio_register(ndev);
2733 if (ret < 0) {
2734 pr_debug("%s: MDIO bus (id: %d) registration failed",
2735 __func__, priv->plat->bus_id);
2736 goto error_mdio_register;
2737 }
4bfcbd7a
FV		 2738 }
2739
bfab27a1 2740 return priv;
47dd7a54 2741
6a81c26f
VK		 2742error_mdio_register:
2743 clk_put(priv->stmmac_clk);
2744error_clk_get:
34a52f36 2745 unregister_netdev(ndev);
6a81c26f
VK		 2746error_netdev_register:
2747 netif_napi_del(&priv->napi);
c24602ef 2748error_free_netdev:
34a52f36 2749 free_netdev(ndev);
47dd7a54 2750
bfab27a1 2751 return NULL;
47dd7a54
GC		 2752}
2753
2754/**
2755 * stmmac_dvr_remove
bfab27a1 2756 * @ndev: net device pointer
47dd7a54 2757 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
bfab27a1 2758 * changes the link status, releases the DMA descriptor rings.
47dd7a54 2759 */
bfab27a1 2760int stmmac_dvr_remove(struct net_device *ndev)
47dd7a54 2761{
aec7ff27 2762 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 2763
2764 pr_info("%s:\n\tremoving driver", __func__);
2765
ad01b7d4
GC		 2766 priv->hw->dma->stop_rx(priv->ioaddr);
2767 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 2768
bfab27a1 2769 stmmac_set_mac(priv->ioaddr, false);
4d8f0825
BA		 2770 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2771 priv->pcs != STMMAC_PCS_RTBI)
e58bb43f 2772 stmmac_mdio_unregister(ndev);
47dd7a54 2773 netif_carrier_off(ndev);
47dd7a54 2774 unregister_netdev(ndev);
47dd7a54
GC		 2775 free_netdev(ndev);
2776
2777 return 0;
2778}
2779
2780#ifdef CONFIG_PM
bfab27a1 2781int stmmac_suspend(struct net_device *ndev)
47dd7a54 2782{
874bd42d 2783 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2784 unsigned long flags;
47dd7a54 2785
874bd42d 2786 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 2787 return 0;
2788
102463b1
FV		 2789 if (priv->phydev)
2790 phy_stop(priv->phydev);
2791
f8c5a875 2792 spin_lock_irqsave(&priv->lock, flags);
47dd7a54 2793
874bd42d
GC		 2794 netif_device_detach(ndev);
2795 netif_stop_queue(ndev);
47dd7a54 2796
874bd42d
GC		 2797 napi_disable(&priv->napi);
2798
2799 /* Stop TX/RX DMA */
2800 priv->hw->dma->stop_tx(priv->ioaddr);
2801 priv->hw->dma->stop_rx(priv->ioaddr);
c24602ef
GC		 2802
2803 stmmac_clear_descriptors(priv);
874bd42d
GC		 2804
2805 /* Enable Power down mode by programming the PMT regs */
2806 if (device_may_wakeup(priv->device))
2807 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
ba1377ff 2808 else {
bfab27a1 2809 stmmac_set_mac(priv->ioaddr, false);
ba1377ff 2810 /* Disable clock in case of PWM is off */
a630844d 2811 clk_disable_unprepare(priv->stmmac_clk);
ba1377ff 2812 }
f8c5a875 2813 spin_unlock_irqrestore(&priv->lock, flags);
47dd7a54
GC		 2814 return 0;
2815}
2816
bfab27a1 2817int stmmac_resume(struct net_device *ndev)
47dd7a54 2818{
874bd42d 2819 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2820 unsigned long flags;
47dd7a54 2821
874bd42d 2822 if (!netif_running(ndev))
47dd7a54
GC		 2823 return 0;
2824
f8c5a875 2825 spin_lock_irqsave(&priv->lock, flags);
c4433be6 2826
47dd7a54
GC		 2827 /* Power Down bit, into the PM register, is cleared
2828 * automatically as soon as a magic packet or a Wake-up frame
2829 * is received. Anyway, it's better to manually clear
2830 * this bit because it can generate problems while resuming
ceb69499
GC		 2831 * from another devices (e.g. serial console).
2832 */
874bd42d 2833 if (device_may_wakeup(priv->device))
543876c9 2834 priv->hw->mac->pmt(priv->ioaddr, 0);
ba1377ff
GC		 2835 else
2836 /* enable the clk prevously disabled */
a630844d 2837 clk_prepare_enable(priv->stmmac_clk);
47dd7a54 2838
874bd42d 2839 netif_device_attach(ndev);
47dd7a54
GC		 2840
2841 /* Enable the MAC and DMA */
bfab27a1 2842 stmmac_set_mac(priv->ioaddr, true);
ad01b7d4
GC		 2843 priv->hw->dma->start_tx(priv->ioaddr);
2844 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54 2845
47dd7a54
GC		 2846 napi_enable(&priv->napi);
2847
874bd42d 2848 netif_start_queue(ndev);
47dd7a54 2849
f8c5a875 2850 spin_unlock_irqrestore(&priv->lock, flags);
102463b1
FV		 2851
2852 if (priv->phydev)
2853 phy_start(priv->phydev);
2854
47dd7a54
GC		 2855 return 0;
2856}
47dd7a54 2857
bfab27a1 2858int stmmac_freeze(struct net_device *ndev)
874bd42d 2859{
874bd42d
GC		 2860 if (!ndev || !netif_running(ndev))
2861 return 0;
2862
2863 return stmmac_release(ndev);
2864}
2865
bfab27a1 2866int stmmac_restore(struct net_device *ndev)
874bd42d 2867{
874bd42d
GC		 2868 if (!ndev || !netif_running(ndev))
2869 return 0;
2870
2871 return stmmac_open(ndev);
2872}
874bd42d 2873#endif /* CONFIG_PM */
47dd7a54 2874
33d5e332
GC		 2875/* Driver can be configured w/ and w/ both PCI and Platf drivers
2876 * depending on the configuration selected.
2877 */
ba27ec66
GC		 2878static int __init stmmac_init(void)
2879{
493682b8 2880 int ret;
ba27ec66 2881
493682b8
KK		 2882 ret = stmmac_register_platform();
2883 if (ret)
2884 goto err;
2885 ret = stmmac_register_pci();
2886 if (ret)
2887 goto err_pci;
33d5e332 2888 return 0;
493682b8
KK		 2889err_pci:
2890 stmmac_unregister_platform();
2891err:
2892 pr_err("stmmac: driver registration failed\n");
2893 return ret;
ba27ec66
GC		 2894}
2895
2896static void __exit stmmac_exit(void)
2897{
33d5e332
GC		 2898 stmmac_unregister_platform();
2899 stmmac_unregister_pci();
ba27ec66
GC		 2900}
2901
2902module_init(stmmac_init);
2903module_exit(stmmac_exit);
2904
47dd7a54
GC		 2905#ifndef MODULE
2906static int __init stmmac_cmdline_opt(char *str)
2907{
2908 char *opt;
2909
2910 if (!str || !*str)
2911 return -EINVAL;
2912 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28 2913 if (!strncmp(opt, "debug:", 6)) {
ea2ab871 2914 if (kstrtoint(opt + 6, 0, &debug))
f3240e28
GC		 2915 goto err;
2916 } else if (!strncmp(opt, "phyaddr:", 8)) {
ea2ab871 2917 if (kstrtoint(opt + 8, 0, &phyaddr))
f3240e28
GC		 2918 goto err;
2919 } else if (!strncmp(opt, "dma_txsize:", 11)) {
ea2ab871 2920 if (kstrtoint(opt + 11, 0, &dma_txsize))
f3240e28
GC		 2921 goto err;
2922 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
ea2ab871 2923 if (kstrtoint(opt + 11, 0, &dma_rxsize))
f3240e28
GC		 2924 goto err;
2925 } else if (!strncmp(opt, "buf_sz:", 7)) {
ea2ab871 2926 if (kstrtoint(opt + 7, 0, &buf_sz))
f3240e28
GC		 2927 goto err;
2928 } else if (!strncmp(opt, "tc:", 3)) {
ea2ab871 2929 if (kstrtoint(opt + 3, 0, &tc))
f3240e28
GC		 2930 goto err;
2931 } else if (!strncmp(opt, "watchdog:", 9)) {
ea2ab871 2932 if (kstrtoint(opt + 9, 0, &watchdog))
f3240e28
GC		 2933 goto err;
2934 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
ea2ab871 2935 if (kstrtoint(opt + 10, 0, &flow_ctrl))
f3240e28
GC		 2936 goto err;
2937 } else if (!strncmp(opt, "pause:", 6)) {
ea2ab871 2938 if (kstrtoint(opt + 6, 0, &pause))
f3240e28 2939 goto err;
506f669c 2940 } else if (!strncmp(opt, "eee_timer:", 10)) {
d765955d
GC		 2941 if (kstrtoint(opt + 10, 0, &eee_timer))
2942 goto err;
4a7d666a
GC		 2943 } else if (!strncmp(opt, "chain_mode:", 11)) {
2944 if (kstrtoint(opt + 11, 0, &chain_mode))
2945 goto err;
f3240e28 2946 }
47dd7a54
GC		 2947 }
2948 return 0;
f3240e28
GC		 2949
2950err:
2951 pr_err("%s: ERROR broken module parameter conversion", __func__);
2952 return -EINVAL;
47dd7a54
GC		 2953}
2954
2955__setup("stmmaceth=", stmmac_cmdline_opt);
ceb69499 2956#endif /* MODULE */
6fc0d0f2
GC		 2957
2958MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2959MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2960MODULE_LICENSE("GPL");
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