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stmmac: limit max_mtu in case of 4KiB and use __netdev_alloc_skb (V2)
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/kernel.h>
34#include <linux/interrupt.h>
47dd7a54
GC		 35#include <linux/etherdevice.h>
36#include <linux/platform_device.h>
37#include <linux/ip.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/ethtool.h>
41#include <linux/if_ether.h>
42#include <linux/crc32.h>
43#include <linux/mii.h>
01789349 44#include <linux/if.h>
47dd7a54
GC		 45#include <linux/if_vlan.h>
46#include <linux/dma-mapping.h>
5a0e3ad6 47#include <linux/slab.h>
70c71606 48#include <linux/prefetch.h>
7ac29055
GC		 49#ifdef CONFIG_STMMAC_DEBUG_FS
50#include <linux/debugfs.h>
51#include <linux/seq_file.h>
52#endif
286a8372 53#include "stmmac.h"
47dd7a54
GC		 54
55#define STMMAC_RESOURCE_NAME "stmmaceth"
47dd7a54
GC		 56
57#undef STMMAC_DEBUG
58/*#define STMMAC_DEBUG*/
59#ifdef STMMAC_DEBUG
60#define DBG(nlevel, klevel, fmt, args...) \
61 ((void)(netif_msg_##nlevel(priv) && \
62 printk(KERN_##klevel fmt, ## args)))
63#else
64#define DBG(nlevel, klevel, fmt, args...) do { } while (0)
65#endif
66
67#undef STMMAC_RX_DEBUG
68/*#define STMMAC_RX_DEBUG*/
69#ifdef STMMAC_RX_DEBUG
70#define RX_DBG(fmt, args...) printk(fmt, ## args)
71#else
72#define RX_DBG(fmt, args...) do { } while (0)
73#endif
74
75#undef STMMAC_XMIT_DEBUG
76/*#define STMMAC_XMIT_DEBUG*/
77#ifdef STMMAC_TX_DEBUG
78#define TX_DBG(fmt, args...) printk(fmt, ## args)
79#else
80#define TX_DBG(fmt, args...) do { } while (0)
81#endif
82
83#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
84#define JUMBO_LEN 9000
85
86/* Module parameters */
87#define TX_TIMEO 5000 /* default 5 seconds */
88static int watchdog = TX_TIMEO;
89module_param(watchdog, int, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
91
92static int debug = -1; /* -1: default, 0: no output, 16: all */
93module_param(debug, int, S_IRUGO | S_IWUSR);
94MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
95
96static int phyaddr = -1;
97module_param(phyaddr, int, S_IRUGO);
98MODULE_PARM_DESC(phyaddr, "Physical device address");
99
100#define DMA_TX_SIZE 256
101static int dma_txsize = DMA_TX_SIZE;
102module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
103MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
104
105#define DMA_RX_SIZE 256
106static int dma_rxsize = DMA_RX_SIZE;
107module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
108MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
109
110static int flow_ctrl = FLOW_OFF;
111module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
112MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
113
114static int pause = PAUSE_TIME;
115module_param(pause, int, S_IRUGO | S_IWUSR);
116MODULE_PARM_DESC(pause, "Flow Control Pause Time");
117
118#define TC_DEFAULT 64
119static int tc = TC_DEFAULT;
120module_param(tc, int, S_IRUGO | S_IWUSR);
121MODULE_PARM_DESC(tc, "DMA threshold control value");
122
47dd7a54
GC		 123/* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126#ifdef CONFIG_STMMAC_TIMER
127#define DEFAULT_PERIODIC_RATE 256
128static int tmrate = DEFAULT_PERIODIC_RATE;
129module_param(tmrate, int, S_IRUGO | S_IWUSR);
130MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131#endif
132
133#define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134static int buf_sz = DMA_BUFFER_SIZE;
135module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
47dd7a54
GC		 138static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
139 NETIF_MSG_LINK | NETIF_MSG_IFUP |
140 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
141
142static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54
GC		 143
144/**
145 * stmmac_verify_args - verify the driver parameters.
146 * Description: it verifies if some wrong parameter is passed to the driver.
147 * Note that wrong parameters are replaced with the default values.
148 */
149static void stmmac_verify_args(void)
150{
151 if (unlikely(watchdog < 0))
152 watchdog = TX_TIMEO;
153 if (unlikely(dma_rxsize < 0))
154 dma_rxsize = DMA_RX_SIZE;
155 if (unlikely(dma_txsize < 0))
156 dma_txsize = DMA_TX_SIZE;
157 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
158 buf_sz = DMA_BUFFER_SIZE;
159 if (unlikely(flow_ctrl > 1))
160 flow_ctrl = FLOW_AUTO;
161 else if (likely(flow_ctrl < 0))
162 flow_ctrl = FLOW_OFF;
163 if (unlikely((pause < 0) || (pause > 0xffff)))
164 pause = PAUSE_TIME;
47dd7a54
GC		 165}
166
167#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
168static void print_pkt(unsigned char *buf, int len)
169{
170 int j;
171 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
172 for (j = 0; j < len; j++) {
173 if ((j % 16) == 0)
174 pr_info("\n %03x:", j);
175 pr_info(" %02x", buf[j]);
176 }
177 pr_info("\n");
47dd7a54
GC		 178}
179#endif
180
181/* minimum number of free TX descriptors required to wake up TX process */
182#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183
184static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185{
186 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
187}
188
9dfeb4d9
GC		 189/* On some ST platforms, some HW system configuraton registers have to be
190 * set according to the link speed negotiated.
191 */
192static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193{
194 struct phy_device *phydev = priv->phydev;
195
196 if (likely(priv->plat->fix_mac_speed))
197 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
198 phydev->speed);
199}
200
47dd7a54
GC		 201/**
202 * stmmac_adjust_link
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
205 */
206static void stmmac_adjust_link(struct net_device *dev)
207{
208 struct stmmac_priv *priv = netdev_priv(dev);
209 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
ad01b7d4 222 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
db98a0b0 229 ctrl &= ~priv->hw->link.duplex;
47dd7a54 230 else
db98a0b0 231 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
ad01b7d4 236 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 237 fc, pause_time);
47dd7a54
GC		 238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
9dfeb4d9 243 if (likely(priv->plat->has_gmac))
db98a0b0 244 ctrl &= ~priv->hw->link.port;
9dfeb4d9 245 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 246 break;
247 case 100:
248 case 10:
9dfeb4d9 249 if (priv->plat->has_gmac) {
db98a0b0 250 ctrl |= priv->hw->link.port;
47dd7a54 251 if (phydev->speed == SPEED_100) {
db98a0b0 252 ctrl |= priv->hw->link.speed;
47dd7a54 253 } else {
db98a0b0 254 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 255 }
256 } else {
db98a0b0 257 ctrl &= ~priv->hw->link.port;
47dd7a54 258 }
9dfeb4d9 259 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 260 break;
261 default:
262 if (netif_msg_link(priv))
263 pr_warning("%s: Speed (%d) is not 10"
264 " or 100!\n", dev->name, phydev->speed);
265 break;
266 }
267
268 priv->speed = phydev->speed;
269 }
270
ad01b7d4 271 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 272
273 if (!priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 1;
276 }
277 } else if (priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 0;
280 priv->speed = 0;
281 priv->oldduplex = -1;
282 }
283
284 if (new_state && netif_msg_link(priv))
285 phy_print_status(phydev);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
290}
291
292/**
293 * stmmac_init_phy - PHY initialization
294 * @dev: net device structure
295 * Description: it initializes the driver's PHY state, and attaches the PHY
296 * to the mac driver.
297 * Return value:
298 * 0 on success
299 */
300static int stmmac_init_phy(struct net_device *dev)
301{
302 struct stmmac_priv *priv = netdev_priv(dev);
303 struct phy_device *phydev;
109cdd66
GC		 304 char phy_id[MII_BUS_ID_SIZE + 3];
305 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 306 int interface = priv->plat->interface;
47dd7a54
GC		 307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310
9dfeb4d9 311 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
109cdd66 312 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 313 priv->plat->phy_addr);
47dd7a54
GC		 314 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315
79ee1dc3 316 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
47dd7a54
GC		 317
318 if (IS_ERR(phydev)) {
319 pr_err("%s: Could not attach to PHY\n", dev->name);
320 return PTR_ERR(phydev);
321 }
322
79ee1dc3
SK		 323 /* Stop Advertising 1000BASE Capability if interface is not GMII */
324 if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) ||
325 (interface == PHY_INTERFACE_MODE_RMII))) {
326 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
327 SUPPORTED_Asym_Pause);
328 priv->phydev->advertising = priv->phydev->supported;
329 }
330
47dd7a54
GC		 331 /*
332 * Broken HW is sometimes missing the pull-up resistor on the
333 * MDIO line, which results in reads to non-existent devices returning
334 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
335 * device as well.
336 * Note: phydev->phy_id is the result of reading the UID PHY registers.
337 */
338 if (phydev->phy_id == 0) {
339 phy_disconnect(phydev);
340 return -ENODEV;
341 }
342 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 343 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 344
345 priv->phydev = phydev;
346
347 return 0;
348}
349
19449bfc 350static inline void stmmac_enable_mac(void __iomem *ioaddr)
47dd7a54
GC		 351{
352 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 353
19449bfc 354 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
47dd7a54
GC		 355 writel(value, ioaddr + MAC_CTRL_REG);
356}
357
19449bfc 358static inline void stmmac_disable_mac(void __iomem *ioaddr)
47dd7a54
GC		 359{
360 u32 value = readl(ioaddr + MAC_CTRL_REG);
47dd7a54 361
19449bfc 362 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
47dd7a54
GC		 363 writel(value, ioaddr + MAC_CTRL_REG);
364}
365
366/**
367 * display_ring
368 * @p: pointer to the ring.
369 * @size: size of the ring.
370 * Description: display all the descriptors within the ring.
371 */
372static void display_ring(struct dma_desc *p, int size)
373{
374 struct tmp_s {
375 u64 a;
376 unsigned int b;
377 unsigned int c;
378 };
379 int i;
380 for (i = 0; i < size; i++) {
381 struct tmp_s *x = (struct tmp_s *)(p + i);
382 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
383 i, (unsigned int)virt_to_phys(&p[i]),
384 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
385 x->b, x->c);
386 pr_info("\n");
387 }
388}
389
286a8372
GC		 390static int stmmac_set_bfsize(int mtu, int bufsize)
391{
392 int ret = bufsize;
393
394 if (mtu >= BUF_SIZE_4KiB)
395 ret = BUF_SIZE_8KiB;
396 else if (mtu >= BUF_SIZE_2KiB)
397 ret = BUF_SIZE_4KiB;
398 else if (mtu >= DMA_BUFFER_SIZE)
399 ret = BUF_SIZE_2KiB;
400 else
401 ret = DMA_BUFFER_SIZE;
402
403 return ret;
404}
405
47dd7a54
GC		 406/**
407 * init_dma_desc_rings - init the RX/TX descriptor rings
408 * @dev: net device structure
409 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 410 * and allocates the socket buffers. It suppors the chained and ring
411 * modes.
47dd7a54
GC		 412 */
413static void init_dma_desc_rings(struct net_device *dev)
414{
415 int i;
416 struct stmmac_priv *priv = netdev_priv(dev);
417 struct sk_buff *skb;
418 unsigned int txsize = priv->dma_tx_size;
419 unsigned int rxsize = priv->dma_rx_size;
286a8372
GC		 420 unsigned int bfsize;
421 int dis_ic = 0;
422 int des3_as_data_buf = 0;
47dd7a54 423
286a8372
GC		 424 /* Set the max buffer size according to the DESC mode
425 * and the MTU. Note that RING mode allows 16KiB bsize. */
426 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
427
428 if (bfsize == BUF_SIZE_16KiB)
429 des3_as_data_buf = 1;
47dd7a54 430 else
286a8372 431 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 432
73cfe264
GC		 433#ifdef CONFIG_STMMAC_TIMER
434 /* Disable interrupts on completion for the reception if timer is on */
435 if (likely(priv->tm->enable))
436 dis_ic = 1;
437#endif
47dd7a54
GC		 438
439 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
440 txsize, rxsize, bfsize);
441
442 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
443 priv->rx_skbuff =
444 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
445 priv->dma_rx =
446 (struct dma_desc *)dma_alloc_coherent(priv->device,
447 rxsize *
448 sizeof(struct dma_desc),
449 &priv->dma_rx_phy,
450 GFP_KERNEL);
451 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
452 GFP_KERNEL);
453 priv->dma_tx =
454 (struct dma_desc *)dma_alloc_coherent(priv->device,
455 txsize *
456 sizeof(struct dma_desc),
457 &priv->dma_tx_phy,
458 GFP_KERNEL);
459
460 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
461 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
462 return;
463 }
464
286a8372 465 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
47dd7a54
GC		 466 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
467 dev->name, priv->dma_rx, priv->dma_tx,
468 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
469
470 /* RX INITIALIZATION */
471 DBG(probe, INFO, "stmmac: SKB addresses:\n"
472 "skb\t\tskb data\tdma data\n");
473
474 for (i = 0; i < rxsize; i++) {
475 struct dma_desc *p = priv->dma_rx + i;
476
45db81e1
GC		 477 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
478 GFP_KERNEL);
47dd7a54
GC		 479 if (unlikely(skb == NULL)) {
480 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
481 break;
482 }
45db81e1 483 skb_reserve(skb, NET_IP_ALIGN);
47dd7a54
GC		 484 priv->rx_skbuff[i] = skb;
485 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
486 bfsize, DMA_FROM_DEVICE);
487
488 p->des2 = priv->rx_skbuff_dma[i];
286a8372
GC		 489
490 priv->hw->ring->init_desc3(des3_as_data_buf, p);
491
47dd7a54
GC		 492 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
493 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
494 }
495 priv->cur_rx = 0;
496 priv->dirty_rx = (unsigned int)(i - rxsize);
497 priv->dma_buf_sz = bfsize;
498 buf_sz = bfsize;
499
500 /* TX INITIALIZATION */
501 for (i = 0; i < txsize; i++) {
502 priv->tx_skbuff[i] = NULL;
503 priv->dma_tx[i].des2 = 0;
504 }
286a8372
GC		 505
506 /* In case of Chained mode this sets the des3 to the next
507 * element in the chain */
508 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
509 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
510
47dd7a54
GC		 511 priv->dirty_tx = 0;
512 priv->cur_tx = 0;
513
514 /* Clear the Rx/Tx descriptors */
db98a0b0
GC		 515 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
516 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
47dd7a54
GC		 517
518 if (netif_msg_hw(priv)) {
519 pr_info("RX descriptor ring:\n");
520 display_ring(priv->dma_rx, rxsize);
521 pr_info("TX descriptor ring:\n");
522 display_ring(priv->dma_tx, txsize);
523 }
47dd7a54
GC		 524}
525
526static void dma_free_rx_skbufs(struct stmmac_priv *priv)
527{
528 int i;
529
530 for (i = 0; i < priv->dma_rx_size; i++) {
531 if (priv->rx_skbuff[i]) {
532 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
533 priv->dma_buf_sz, DMA_FROM_DEVICE);
534 dev_kfree_skb_any(priv->rx_skbuff[i]);
535 }
536 priv->rx_skbuff[i] = NULL;
537 }
47dd7a54
GC		 538}
539
540static void dma_free_tx_skbufs(struct stmmac_priv *priv)
541{
542 int i;
543
544 for (i = 0; i < priv->dma_tx_size; i++) {
545 if (priv->tx_skbuff[i] != NULL) {
546 struct dma_desc *p = priv->dma_tx + i;
547 if (p->des2)
548 dma_unmap_single(priv->device, p->des2,
db98a0b0
GC		 549 priv->hw->desc->get_tx_len(p),
550 DMA_TO_DEVICE);
47dd7a54
GC		 551 dev_kfree_skb_any(priv->tx_skbuff[i]);
552 priv->tx_skbuff[i] = NULL;
553 }
554 }
47dd7a54
GC		 555}
556
557static void free_dma_desc_resources(struct stmmac_priv *priv)
558{
559 /* Release the DMA TX/RX socket buffers */
560 dma_free_rx_skbufs(priv);
561 dma_free_tx_skbufs(priv);
562
563 /* Free the region of consistent memory previously allocated for
564 * the DMA */
565 dma_free_coherent(priv->device,
566 priv->dma_tx_size * sizeof(struct dma_desc),
567 priv->dma_tx, priv->dma_tx_phy);
568 dma_free_coherent(priv->device,
569 priv->dma_rx_size * sizeof(struct dma_desc),
570 priv->dma_rx, priv->dma_rx_phy);
571 kfree(priv->rx_skbuff_dma);
572 kfree(priv->rx_skbuff);
573 kfree(priv->tx_skbuff);
47dd7a54
GC		 574}
575
47dd7a54
GC		 576/**
577 * stmmac_dma_operation_mode - HW DMA operation mode
578 * @priv : pointer to the private device structure.
579 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 580 * or Store-And-Forward capability.
47dd7a54
GC		 581 */
582static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
583{
61b8013a
SK		 584 if (likely(priv->plat->force_sf_dma_mode ||
585 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
586 /*
587 * In case of GMAC, SF mode can be enabled
588 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 589 * 1) TX COE if actually supported
590 * 2) There is no bugged Jumbo frame support
591 * that needs to not insert csum in the TDES.
592 */
593 priv->hw->dma->dma_mode(priv->ioaddr,
594 SF_DMA_MODE, SF_DMA_MODE);
595 tc = SF_DMA_MODE;
596 } else
597 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 598}
599
47dd7a54
GC		 600/**
601 * stmmac_tx:
602 * @priv: private driver structure
603 * Description: it reclaims resources after transmission completes.
604 */
605static void stmmac_tx(struct stmmac_priv *priv)
606{
607 unsigned int txsize = priv->dma_tx_size;
47dd7a54 608
a9097a96
GC		 609 spin_lock(&priv->tx_lock);
610
47dd7a54
GC		 611 while (priv->dirty_tx != priv->cur_tx) {
612 int last;
613 unsigned int entry = priv->dirty_tx % txsize;
614 struct sk_buff *skb = priv->tx_skbuff[entry];
615 struct dma_desc *p = priv->dma_tx + entry;
616
617 /* Check if the descriptor is owned by the DMA. */
db98a0b0 618 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 619 break;
620
621 /* Verify tx error by looking at the last segment */
db98a0b0 622 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 623 if (likely(last)) {
624 int tx_error =
db98a0b0
GC		 625 priv->hw->desc->tx_status(&priv->dev->stats,
626 &priv->xstats, p,
ad01b7d4 627 priv->ioaddr);
47dd7a54
GC		 628 if (likely(tx_error == 0)) {
629 priv->dev->stats.tx_packets++;
630 priv->xstats.tx_pkt_n++;
631 } else
632 priv->dev->stats.tx_errors++;
633 }
634 TX_DBG("%s: curr %d, dirty %d\n", __func__,
635 priv->cur_tx, priv->dirty_tx);
636
637 if (likely(p->des2))
638 dma_unmap_single(priv->device, p->des2,
db98a0b0 639 priv->hw->desc->get_tx_len(p),
47dd7a54 640 DMA_TO_DEVICE);
286a8372 641 priv->hw->ring->clean_desc3(p);
47dd7a54
GC		 642
643 if (likely(skb != NULL)) {
644 /*
645 * If there's room in the queue (limit it to size)
646 * we add this skb back into the pool,
647 * if it's the right size.
648 */
649 if ((skb_queue_len(&priv->rx_recycle) <
650 priv->dma_rx_size) &&
651 skb_recycle_check(skb, priv->dma_buf_sz))
652 __skb_queue_head(&priv->rx_recycle, skb);
653 else
654 dev_kfree_skb(skb);
655
656 priv->tx_skbuff[entry] = NULL;
657 }
658
db98a0b0 659 priv->hw->desc->release_tx_desc(p);
47dd7a54
GC		 660
661 entry = (++priv->dirty_tx) % txsize;
662 }
663 if (unlikely(netif_queue_stopped(priv->dev) &&
664 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
665 netif_tx_lock(priv->dev);
666 if (netif_queue_stopped(priv->dev) &&
667 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
668 TX_DBG("%s: restart transmit\n", __func__);
669 netif_wake_queue(priv->dev);
670 }
671 netif_tx_unlock(priv->dev);
672 }
a9097a96 673 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 674}
675
676static inline void stmmac_enable_irq(struct stmmac_priv *priv)
677{
73cfe264
GC		 678#ifdef CONFIG_STMMAC_TIMER
679 if (likely(priv->tm->enable))
680 priv->tm->timer_start(tmrate);
681 else
47dd7a54 682#endif
ad01b7d4 683 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 684}
685
686static inline void stmmac_disable_irq(struct stmmac_priv *priv)
687{
73cfe264
GC		 688#ifdef CONFIG_STMMAC_TIMER
689 if (likely(priv->tm->enable))
690 priv->tm->timer_stop();
691 else
47dd7a54 692#endif
ad01b7d4 693 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 694}
695
696static int stmmac_has_work(struct stmmac_priv *priv)
697{
698 unsigned int has_work = 0;
699 int rxret, tx_work = 0;
700
db98a0b0 701 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
47dd7a54
GC		 702 (priv->cur_rx % priv->dma_rx_size));
703
704 if (priv->dirty_tx != priv->cur_tx)
705 tx_work = 1;
706
707 if (likely(!rxret || tx_work))
708 has_work = 1;
709
710 return has_work;
711}
712
713static inline void _stmmac_schedule(struct stmmac_priv *priv)
714{
715 if (likely(stmmac_has_work(priv))) {
716 stmmac_disable_irq(priv);
717 napi_schedule(&priv->napi);
718 }
719}
720
721#ifdef CONFIG_STMMAC_TIMER
722void stmmac_schedule(struct net_device *dev)
723{
724 struct stmmac_priv *priv = netdev_priv(dev);
725
726 priv->xstats.sched_timer_n++;
727
728 _stmmac_schedule(priv);
47dd7a54
GC		 729}
730
731static void stmmac_no_timer_started(unsigned int x)
732{;
733};
734
735static void stmmac_no_timer_stopped(void)
736{;
737};
738#endif
739
740/**
741 * stmmac_tx_err:
742 * @priv: pointer to the private device structure
743 * Description: it cleans the descriptors and restarts the transmission
744 * in case of errors.
745 */
746static void stmmac_tx_err(struct stmmac_priv *priv)
747{
748 netif_stop_queue(priv->dev);
749
ad01b7d4 750 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 751 dma_free_tx_skbufs(priv);
db98a0b0 752 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
47dd7a54
GC		 753 priv->dirty_tx = 0;
754 priv->cur_tx = 0;
ad01b7d4 755 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 756
757 priv->dev->stats.tx_errors++;
758 netif_wake_queue(priv->dev);
47dd7a54
GC		 759}
760
47dd7a54 761
aec7ff27
GC		 762static void stmmac_dma_interrupt(struct stmmac_priv *priv)
763{
aec7ff27
GC		 764 int status;
765
ad01b7d4 766 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
aec7ff27
GC		 767 if (likely(status == handle_tx_rx))
768 _stmmac_schedule(priv);
769
770 else if (unlikely(status == tx_hard_error_bump_tc)) {
771 /* Try to bump up the dma threshold on this failure */
772 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
773 tc += 64;
ad01b7d4 774 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 775 priv->xstats.threshold = tc;
47dd7a54 776 }
aec7ff27
GC		 777 } else if (unlikely(status == tx_hard_error))
778 stmmac_tx_err(priv);
47dd7a54
GC		 779}
780
1c901a46
GC		 781static void stmmac_mmc_setup(struct stmmac_priv *priv)
782{
783 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
784 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
785
786 /* Do not manage MMC IRQ (FIXME) */
787 dwmac_mmc_intr_all_mask(priv->ioaddr);
788 dwmac_mmc_ctrl(priv->ioaddr, mode);
789 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
790}
791
f0b9d786
GC		 792static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
793{
794 u32 hwid = priv->hw->synopsys_uid;
795
796 /* Only check valid Synopsys Id because old MAC chips
797 * have no HW registers where get the ID */
798 if (likely(hwid)) {
799 u32 uid = ((hwid & 0x0000ff00) >> 8);
800 u32 synid = (hwid & 0x000000ff);
801
802 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
803 uid, synid);
804
805 return synid;
806 }
807 return 0;
808}
e7434821
GC		 809
810/* New GMAC chips support a new register to indicate the
811 * presence of the optional feature/functions.
812 */
813static int stmmac_get_hw_features(struct stmmac_priv *priv)
814{
815 u32 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
816
817 if (likely(hw_cap)) {
1db123fb
RK		 818 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
819 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
820 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
821 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
822 priv->dma_cap.multi_addr =
823 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
824 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
825 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
826 priv->dma_cap.pmt_remote_wake_up =
827 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
828 priv->dma_cap.pmt_magic_frame =
829 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
830 /*MMC*/
831 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
e7434821 832 /* IEEE 1588-2002*/
1db123fb
RK		 833 priv->dma_cap.time_stamp =
834 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
e7434821 835 /* IEEE 1588-2008*/
1db123fb
RK		 836 priv->dma_cap.atime_stamp =
837 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 838 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 839 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
840 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 841 /* TX and RX csum */
1db123fb
RK		 842 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
843 priv->dma_cap.rx_coe_type1 =
844 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
845 priv->dma_cap.rx_coe_type2 =
846 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
847 priv->dma_cap.rxfifo_over_2048 =
848 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 849 /* TX and RX number of channels */
1db123fb
RK		 850 priv->dma_cap.number_rx_channel =
851 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
852 priv->dma_cap.number_tx_channel =
853 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
e7434821 854 /* Alternate (enhanced) DESC mode*/
1db123fb
RK		 855 priv->dma_cap.enh_desc =
856 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
e7434821
GC		 857
858 } else
859 pr_debug("\tNo HW DMA feature register supported");
860
861 return hw_cap;
862}
863
47dd7a54
GC		 864/**
865 * stmmac_open - open entry point of the driver
866 * @dev : pointer to the device structure.
867 * Description:
868 * This function is the open entry point of the driver.
869 * Return value:
870 * 0 on success and an appropriate (-)ve integer as defined in errno.h
871 * file on failure.
872 */
873static int stmmac_open(struct net_device *dev)
874{
875 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 876 int ret;
877
878 /* Check that the MAC address is valid. If its not, refuse
879 * to bring the device up. The user must specify an
880 * address using the following linux command:
881 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
882 if (!is_valid_ether_addr(dev->dev_addr)) {
883 random_ether_addr(dev->dev_addr);
884 pr_warning("%s: generated random MAC address %pM\n", dev->name,
885 dev->dev_addr);
886 }
887
888 stmmac_verify_args();
889
47dd7a54 890#ifdef CONFIG_STMMAC_TIMER
73cfe264 891 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
47dd7a54 892 if (unlikely(priv->tm == NULL)) {
2381a55c 893 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
47dd7a54
GC		 894 return -ENOMEM;
895 }
896 priv->tm->freq = tmrate;
897
73cfe264
GC		 898 /* Test if the external timer can be actually used.
899 * In case of failure continue without timer. */
47dd7a54 900 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
73cfe264 901 pr_warning("stmmaceth: cannot attach the external timer.\n");
47dd7a54
GC		 902 priv->tm->freq = 0;
903 priv->tm->timer_start = stmmac_no_timer_started;
904 priv->tm->timer_stop = stmmac_no_timer_stopped;
73cfe264
GC		 905 } else
906 priv->tm->enable = 1;
47dd7a54 907#endif
f66ffe28
GC		 908 ret = stmmac_init_phy(dev);
909 if (unlikely(ret)) {
910 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
911 goto open_error;
912 }
47dd7a54
GC		 913
914 /* Create and initialize the TX/RX descriptors chains. */
915 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
916 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
917 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
918 init_dma_desc_rings(dev);
919
920 /* DMA initialization and SW reset */
f66ffe28
GC		 921 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
922 priv->dma_tx_phy, priv->dma_rx_phy);
923 if (ret < 0) {
47dd7a54 924 pr_err("%s: DMA initialization failed\n", __func__);
f66ffe28 925 goto open_error;
47dd7a54
GC		 926 }
927
928 /* Copy the MAC addr into the HW */
ad01b7d4 929 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
ca5f12c1 930 /* If required, perform hw setup of the bus. */
9dfeb4d9
GC		 931 if (priv->plat->bus_setup)
932 priv->plat->bus_setup(priv->ioaddr);
47dd7a54 933 /* Initialize the MAC Core */
ad01b7d4 934 priv->hw->mac->core_init(priv->ioaddr);
47dd7a54 935
f0b9d786
GC		 936 stmmac_get_synopsys_id(priv);
937
e7434821
GC		 938 stmmac_get_hw_features(priv);
939
ebbb293f
GC		 940 if (priv->rx_coe)
941 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
9dfeb4d9 942 if (priv->plat->tx_coe)
ebbb293f 943 pr_info("\tTX Checksum insertion supported\n");
5e982f3b 944 netdev_update_features(dev);
ebbb293f 945
f66ffe28
GC		 946 /* Request the IRQ lines */
947 ret = request_irq(dev->irq, stmmac_interrupt,
948 IRQF_SHARED, dev->name, dev);
949 if (unlikely(ret < 0)) {
950 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
951 __func__, dev->irq, ret);
952 goto open_error;
953 }
954
47dd7a54 955 /* Enable the MAC Rx/Tx */
19449bfc 956 stmmac_enable_mac(priv->ioaddr);
47dd7a54
GC		 957
958 /* Set the HW DMA mode and the COE */
959 stmmac_dma_operation_mode(priv);
960
961 /* Extra statistics */
962 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
963 priv->xstats.threshold = tc;
964
38fe7a93
GC		 965 if (priv->dma_cap.rmon)
966 stmmac_mmc_setup(priv);
1c901a46 967
47dd7a54
GC		 968 /* Start the ball rolling... */
969 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
ad01b7d4
GC		 970 priv->hw->dma->start_tx(priv->ioaddr);
971 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 972
973#ifdef CONFIG_STMMAC_TIMER
974 priv->tm->timer_start(tmrate);
975#endif
976 /* Dump DMA/MAC registers */
977 if (netif_msg_hw(priv)) {
ad01b7d4
GC		 978 priv->hw->mac->dump_regs(priv->ioaddr);
979 priv->hw->dma->dump_regs(priv->ioaddr);
47dd7a54
GC		 980 }
981
982 if (priv->phydev)
983 phy_start(priv->phydev);
984
985 napi_enable(&priv->napi);
986 skb_queue_head_init(&priv->rx_recycle);
987 netif_start_queue(dev);
f66ffe28 988
47dd7a54 989 return 0;
f66ffe28
GC		 990
991open_error:
992#ifdef CONFIG_STMMAC_TIMER
993 kfree(priv->tm);
994#endif
995 if (priv->phydev)
996 phy_disconnect(priv->phydev);
997
998 return ret;
47dd7a54
GC		 999}
1000
1001/**
1002 * stmmac_release - close entry point of the driver
1003 * @dev : device pointer.
1004 * Description:
1005 * This is the stop entry point of the driver.
1006 */
1007static int stmmac_release(struct net_device *dev)
1008{
1009 struct stmmac_priv *priv = netdev_priv(dev);
1010
1011 /* Stop and disconnect the PHY */
1012 if (priv->phydev) {
1013 phy_stop(priv->phydev);
1014 phy_disconnect(priv->phydev);
1015 priv->phydev = NULL;
1016 }
1017
1018 netif_stop_queue(dev);
1019
1020#ifdef CONFIG_STMMAC_TIMER
1021 /* Stop and release the timer */
1022 stmmac_close_ext_timer();
1023 if (priv->tm != NULL)
1024 kfree(priv->tm);
1025#endif
1026 napi_disable(&priv->napi);
1027 skb_queue_purge(&priv->rx_recycle);
1028
1029 /* Free the IRQ lines */
1030 free_irq(dev->irq, dev);
1031
1032 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1033 priv->hw->dma->stop_tx(priv->ioaddr);
1034 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1035
1036 /* Release and free the Rx/Tx resources */
1037 free_dma_desc_resources(priv);
1038
19449bfc 1039 /* Disable the MAC Rx/Tx */
1040 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1041
1042 netif_carrier_off(dev);
1043
1044 return 0;
1045}
1046
47dd7a54
GC		 1047/**
1048 * stmmac_xmit:
1049 * @skb : the socket buffer
1050 * @dev : device pointer
1051 * Description : Tx entry point of the driver.
1052 */
1053static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1054{
1055 struct stmmac_priv *priv = netdev_priv(dev);
1056 unsigned int txsize = priv->dma_tx_size;
1057 unsigned int entry;
1058 int i, csum_insertion = 0;
1059 int nfrags = skb_shinfo(skb)->nr_frags;
1060 struct dma_desc *desc, *first;
286a8372 1061 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1062
1063 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1064 if (!netif_queue_stopped(dev)) {
1065 netif_stop_queue(dev);
1066 /* This is a hard error, log it. */
1067 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1068 __func__);
1069 }
1070 return NETDEV_TX_BUSY;
1071 }
1072
a9097a96
GC		 1073 spin_lock(&priv->tx_lock);
1074
47dd7a54
GC		 1075 entry = priv->cur_tx % txsize;
1076
1077#ifdef STMMAC_XMIT_DEBUG
1078 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1079 pr_info("stmmac xmit:\n"
1080 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1081 "\tn_frags: %d - ip_summed: %d - %s gso\n",
286a8372 1082 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
47dd7a54
GC		 1083 !skb_is_gso(skb) ? "isn't" : "is");
1084#endif
1085
5e982f3b 1086 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54
GC		 1087
1088 desc = priv->dma_tx + entry;
1089 first = desc;
1090
1091#ifdef STMMAC_XMIT_DEBUG
1092 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1093 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1094 "\t\tn_frags: %d, ip_summed: %d\n",
286a8372 1095 skb->len, nopaged_len, nfrags, skb->ip_summed);
47dd7a54
GC		 1096#endif
1097 priv->tx_skbuff[entry] = skb;
286a8372
GC		 1098
1099 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1100 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
47dd7a54
GC		 1101 desc = priv->dma_tx + entry;
1102 } else {
47dd7a54
GC		 1103 desc->des2 = dma_map_single(priv->device, skb->data,
1104 nopaged_len, DMA_TO_DEVICE);
db98a0b0
GC		 1105 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1106 csum_insertion);
47dd7a54
GC		 1107 }
1108
1109 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1110 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1111 int len = skb_frag_size(frag);
47dd7a54
GC		 1112
1113 entry = (++priv->cur_tx) % txsize;
1114 desc = priv->dma_tx + entry;
1115
1116 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
f722380d
IC		 1117 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1118 DMA_TO_DEVICE);
47dd7a54 1119 priv->tx_skbuff[entry] = NULL;
db98a0b0 1120 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
eb0dc4bb 1121 wmb();
db98a0b0 1122 priv->hw->desc->set_tx_owner(desc);
47dd7a54
GC		 1123 }
1124
1125 /* Interrupt on completition only for the latest segment */
db98a0b0 1126 priv->hw->desc->close_tx_desc(desc);
73cfe264 1127
47dd7a54 1128#ifdef CONFIG_STMMAC_TIMER
73cfe264
GC		 1129 /* Clean IC while using timer */
1130 if (likely(priv->tm->enable))
db98a0b0 1131 priv->hw->desc->clear_tx_ic(desc);
47dd7a54 1132#endif
eb0dc4bb
SH		 1133
1134 wmb();
1135
47dd7a54 1136 /* To avoid raise condition */
db98a0b0 1137 priv->hw->desc->set_tx_owner(first);
47dd7a54
GC		 1138
1139 priv->cur_tx++;
1140
1141#ifdef STMMAC_XMIT_DEBUG
1142 if (netif_msg_pktdata(priv)) {
1143 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1144 "first=%p, nfrags=%d\n",
1145 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1146 entry, first, nfrags);
1147 display_ring(priv->dma_tx, txsize);
1148 pr_info(">>> frame to be transmitted: ");
1149 print_pkt(skb->data, skb->len);
1150 }
1151#endif
1152 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1153 TX_DBG("%s: stop transmitted packets\n", __func__);
1154 netif_stop_queue(dev);
1155 }
1156
1157 dev->stats.tx_bytes += skb->len;
1158
3e82ce12
RC		 1159 skb_tx_timestamp(skb);
1160
52f64fae
RC		 1161 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1162
a9097a96
GC		 1163 spin_unlock(&priv->tx_lock);
1164
47dd7a54
GC		 1165 return NETDEV_TX_OK;
1166}
1167
1168static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1169{
1170 unsigned int rxsize = priv->dma_rx_size;
1171 int bfsize = priv->dma_buf_sz;
1172 struct dma_desc *p = priv->dma_rx;
1173
1174 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1175 unsigned int entry = priv->dirty_rx % rxsize;
1176 if (likely(priv->rx_skbuff[entry] == NULL)) {
1177 struct sk_buff *skb;
1178
1179 skb = __skb_dequeue(&priv->rx_recycle);
1180 if (skb == NULL)
1181 skb = netdev_alloc_skb_ip_align(priv->dev,
1182 bfsize);
1183
1184 if (unlikely(skb == NULL))
1185 break;
1186
1187 priv->rx_skbuff[entry] = skb;
1188 priv->rx_skbuff_dma[entry] =
1189 dma_map_single(priv->device, skb->data, bfsize,
1190 DMA_FROM_DEVICE);
1191
1192 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
286a8372
GC		 1193
1194 if (unlikely(priv->plat->has_gmac))
1195 priv->hw->ring->refill_desc3(bfsize, p + entry);
1196
47dd7a54
GC		 1197 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1198 }
eb0dc4bb 1199 wmb();
db98a0b0 1200 priv->hw->desc->set_rx_owner(p + entry);
47dd7a54 1201 }
47dd7a54
GC		 1202}
1203
1204static int stmmac_rx(struct stmmac_priv *priv, int limit)
1205{
1206 unsigned int rxsize = priv->dma_rx_size;
1207 unsigned int entry = priv->cur_rx % rxsize;
1208 unsigned int next_entry;
1209 unsigned int count = 0;
1210 struct dma_desc *p = priv->dma_rx + entry;
1211 struct dma_desc *p_next;
1212
1213#ifdef STMMAC_RX_DEBUG
1214 if (netif_msg_hw(priv)) {
1215 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1216 display_ring(priv->dma_rx, rxsize);
1217 }
1218#endif
1219 count = 0;
db98a0b0 1220 while (!priv->hw->desc->get_rx_owner(p)) {
47dd7a54
GC		 1221 int status;
1222
1223 if (count >= limit)
1224 break;
1225
1226 count++;
1227
1228 next_entry = (++priv->cur_rx) % rxsize;
1229 p_next = priv->dma_rx + next_entry;
1230 prefetch(p_next);
1231
1232 /* read the status of the incoming frame */
db98a0b0
GC		 1233 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1234 &priv->xstats, p));
47dd7a54
GC		 1235 if (unlikely(status == discard_frame))
1236 priv->dev->stats.rx_errors++;
1237 else {
1238 struct sk_buff *skb;
3eeb2997 1239 int frame_len;
47dd7a54 1240
3eeb2997
GC		 1241 frame_len = priv->hw->desc->get_rx_frame_len(p);
1242 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1243 * Type frames (LLC/LLC-SNAP) */
1244 if (unlikely(status != llc_snap))
1245 frame_len -= ETH_FCS_LEN;
47dd7a54
GC		 1246#ifdef STMMAC_RX_DEBUG
1247 if (frame_len > ETH_FRAME_LEN)
1248 pr_debug("\tRX frame size %d, COE status: %d\n",
1249 frame_len, status);
1250
1251 if (netif_msg_hw(priv))
1252 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1253 p, entry, p->des2);
1254#endif
1255 skb = priv->rx_skbuff[entry];
1256 if (unlikely(!skb)) {
1257 pr_err("%s: Inconsistent Rx descriptor chain\n",
1258 priv->dev->name);
1259 priv->dev->stats.rx_dropped++;
1260 break;
1261 }
1262 prefetch(skb->data - NET_IP_ALIGN);
1263 priv->rx_skbuff[entry] = NULL;
1264
1265 skb_put(skb, frame_len);
1266 dma_unmap_single(priv->device,
1267 priv->rx_skbuff_dma[entry],
1268 priv->dma_buf_sz, DMA_FROM_DEVICE);
1269#ifdef STMMAC_RX_DEBUG
1270 if (netif_msg_pktdata(priv)) {
1271 pr_info(" frame received (%dbytes)", frame_len);
1272 print_pkt(skb->data, frame_len);
1273 }
1274#endif
1275 skb->protocol = eth_type_trans(skb, priv->dev);
1276
1277 if (unlikely(status == csum_none)) {
1278 /* always for the old mac 10/100 */
bc8acf2c 1279 skb_checksum_none_assert(skb);
47dd7a54
GC		 1280 netif_receive_skb(skb);
1281 } else {
1282 skb->ip_summed = CHECKSUM_UNNECESSARY;
1283 napi_gro_receive(&priv->napi, skb);
1284 }
1285
1286 priv->dev->stats.rx_packets++;
1287 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 1288 }
1289 entry = next_entry;
1290 p = p_next; /* use prefetched values */
1291 }
1292
1293 stmmac_rx_refill(priv);
1294
1295 priv->xstats.rx_pkt_n += count;
1296
1297 return count;
1298}
1299
1300/**
1301 * stmmac_poll - stmmac poll method (NAPI)
1302 * @napi : pointer to the napi structure.
1303 * @budget : maximum number of packets that the current CPU can receive from
1304 * all interfaces.
1305 * Description :
1306 * This function implements the the reception process.
1307 * Also it runs the TX completion thread
1308 */
1309static int stmmac_poll(struct napi_struct *napi, int budget)
1310{
1311 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1312 int work_done = 0;
1313
1314 priv->xstats.poll_n++;
1315 stmmac_tx(priv);
1316 work_done = stmmac_rx(priv, budget);
1317
1318 if (work_done < budget) {
1319 napi_complete(napi);
1320 stmmac_enable_irq(priv);
1321 }
1322 return work_done;
1323}
1324
1325/**
1326 * stmmac_tx_timeout
1327 * @dev : Pointer to net device structure
1328 * Description: this function is called when a packet transmission fails to
1329 * complete within a reasonable tmrate. The driver will mark the error in the
1330 * netdev structure and arrange for the device to be reset to a sane state
1331 * in order to transmit a new packet.
1332 */
1333static void stmmac_tx_timeout(struct net_device *dev)
1334{
1335 struct stmmac_priv *priv = netdev_priv(dev);
1336
1337 /* Clear Tx resources and restart transmitting again */
1338 stmmac_tx_err(priv);
47dd7a54
GC		 1339}
1340
1341/* Configuration changes (passed on by ifconfig) */
1342static int stmmac_config(struct net_device *dev, struct ifmap *map)
1343{
1344 if (dev->flags & IFF_UP) /* can't act on a running interface */
1345 return -EBUSY;
1346
1347 /* Don't allow changing the I/O address */
1348 if (map->base_addr != dev->base_addr) {
1349 pr_warning("%s: can't change I/O address\n", dev->name);
1350 return -EOPNOTSUPP;
1351 }
1352
1353 /* Don't allow changing the IRQ */
1354 if (map->irq != dev->irq) {
1355 pr_warning("%s: can't change IRQ number %d\n",
1356 dev->name, dev->irq);
1357 return -EOPNOTSUPP;
1358 }
1359
1360 /* ignore other fields */
1361 return 0;
1362}
1363
1364/**
01789349 1365 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 1366 * @dev : pointer to the device structure
1367 * Description:
1368 * This function is a driver entry point which gets called by the kernel
1369 * whenever multicast addresses must be enabled/disabled.
1370 * Return value:
1371 * void.
1372 */
01789349 1373static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 1374{
1375 struct stmmac_priv *priv = netdev_priv(dev);
1376
1377 spin_lock(&priv->lock);
db98a0b0 1378 priv->hw->mac->set_filter(dev);
47dd7a54 1379 spin_unlock(&priv->lock);
47dd7a54
GC		 1380}
1381
1382/**
1383 * stmmac_change_mtu - entry point to change MTU size for the device.
1384 * @dev : device pointer.
1385 * @new_mtu : the new MTU size for the device.
1386 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1387 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1388 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1389 * Return value:
1390 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1391 * file on failure.
1392 */
1393static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1394{
1395 struct stmmac_priv *priv = netdev_priv(dev);
1396 int max_mtu;
1397
1398 if (netif_running(dev)) {
1399 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1400 return -EBUSY;
1401 }
1402
48febf7e 1403 if (priv->plat->enh_desc)
47dd7a54
GC		 1404 max_mtu = JUMBO_LEN;
1405 else
45db81e1 1406 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54
GC		 1407
1408 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1409 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1410 return -EINVAL;
1411 }
1412
5e982f3b
MM		 1413 dev->mtu = new_mtu;
1414 netdev_update_features(dev);
1415
1416 return 0;
1417}
1418
1419static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1420{
1421 struct stmmac_priv *priv = netdev_priv(dev);
1422
1423 if (!priv->rx_coe)
1424 features &= ~NETIF_F_RXCSUM;
1425 if (!priv->plat->tx_coe)
1426 features &= ~NETIF_F_ALL_CSUM;
1427
ebbb293f
GC		 1428 /* Some GMAC devices have a bugged Jumbo frame support that
1429 * needs to have the Tx COE disabled for oversized frames
1430 * (due to limited buffer sizes). In this case we disable
1431 * the TX csum insertionin the TDES and not use SF. */
5e982f3b
MM		 1432 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1433 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 1434
5e982f3b 1435 return features;
47dd7a54
GC		 1436}
1437
1438static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1439{
1440 struct net_device *dev = (struct net_device *)dev_id;
1441 struct stmmac_priv *priv = netdev_priv(dev);
1442
1443 if (unlikely(!dev)) {
1444 pr_err("%s: invalid dev pointer\n", __func__);
1445 return IRQ_NONE;
1446 }
1447
9dfeb4d9 1448 if (priv->plat->has_gmac)
47dd7a54 1449 /* To handle GMAC own interrupts */
ad01b7d4 1450 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
aec7ff27
GC		 1451
1452 stmmac_dma_interrupt(priv);
47dd7a54
GC		 1453
1454 return IRQ_HANDLED;
1455}
1456
1457#ifdef CONFIG_NET_POLL_CONTROLLER
1458/* Polling receive - used by NETCONSOLE and other diagnostic tools
1459 * to allow network I/O with interrupts disabled. */
1460static void stmmac_poll_controller(struct net_device *dev)
1461{
1462 disable_irq(dev->irq);
1463 stmmac_interrupt(dev->irq, dev);
1464 enable_irq(dev->irq);
1465}
1466#endif
1467
1468/**
1469 * stmmac_ioctl - Entry point for the Ioctl
1470 * @dev: Device pointer.
1471 * @rq: An IOCTL specefic structure, that can contain a pointer to
1472 * a proprietary structure used to pass information to the driver.
1473 * @cmd: IOCTL command
1474 * Description:
1475 * Currently there are no special functionality supported in IOCTL, just the
1476 * phy_mii_ioctl(...) can be invoked.
1477 */
1478static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1479{
1480 struct stmmac_priv *priv = netdev_priv(dev);
28b04113 1481 int ret;
47dd7a54
GC		 1482
1483 if (!netif_running(dev))
1484 return -EINVAL;
1485
28b04113
RC		 1486 if (!priv->phydev)
1487 return -EINVAL;
1488
1489 spin_lock(&priv->lock);
1490 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1491 spin_unlock(&priv->lock);
1492
47dd7a54
GC		 1493 return ret;
1494}
1495
7ac29055
GC		 1496#ifdef CONFIG_STMMAC_DEBUG_FS
1497static struct dentry *stmmac_fs_dir;
1498static struct dentry *stmmac_rings_status;
e7434821 1499static struct dentry *stmmac_dma_cap;
7ac29055
GC		 1500
1501static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1502{
1503 struct tmp_s {
1504 u64 a;
1505 unsigned int b;
1506 unsigned int c;
1507 };
1508 int i;
1509 struct net_device *dev = seq->private;
1510 struct stmmac_priv *priv = netdev_priv(dev);
1511
1512 seq_printf(seq, "=======================\n");
1513 seq_printf(seq, " RX descriptor ring\n");
1514 seq_printf(seq, "=======================\n");
1515
1516 for (i = 0; i < priv->dma_rx_size; i++) {
1517 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1518 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1519 i, (unsigned int)(x->a),
1520 (unsigned int)((x->a) >> 32), x->b, x->c);
1521 seq_printf(seq, "\n");
1522 }
1523
1524 seq_printf(seq, "\n");
1525 seq_printf(seq, "=======================\n");
1526 seq_printf(seq, " TX descriptor ring\n");
1527 seq_printf(seq, "=======================\n");
1528
1529 for (i = 0; i < priv->dma_tx_size; i++) {
1530 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1531 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1532 i, (unsigned int)(x->a),
1533 (unsigned int)((x->a) >> 32), x->b, x->c);
1534 seq_printf(seq, "\n");
1535 }
1536
1537 return 0;
1538}
1539
1540static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1541{
1542 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1543}
1544
1545static const struct file_operations stmmac_rings_status_fops = {
1546 .owner = THIS_MODULE,
1547 .open = stmmac_sysfs_ring_open,
1548 .read = seq_read,
1549 .llseek = seq_lseek,
1550 .release = seq_release,
1551};
1552
e7434821
GC		 1553static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1554{
1555 struct net_device *dev = seq->private;
1556 struct stmmac_priv *priv = netdev_priv(dev);
1557
1558 if (!stmmac_get_hw_features(priv)) {
1559 seq_printf(seq, "DMA HW features not supported\n");
1560 return 0;
1561 }
1562
1563 seq_printf(seq, "==============================\n");
1564 seq_printf(seq, "\tDMA HW features\n");
1565 seq_printf(seq, "==============================\n");
1566
1567 seq_printf(seq, "\t10/100 Mbps %s\n",
1568 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1569 seq_printf(seq, "\t1000 Mbps %s\n",
1570 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1571 seq_printf(seq, "\tHalf duple %s\n",
1572 (priv->dma_cap.half_duplex) ? "Y" : "N");
1573 seq_printf(seq, "\tHash Filter: %s\n",
1574 (priv->dma_cap.hash_filter) ? "Y" : "N");
1575 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1576 (priv->dma_cap.multi_addr) ? "Y" : "N");
1577 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1578 (priv->dma_cap.pcs) ? "Y" : "N");
1579 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1580 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1581 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1582 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1583 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1584 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1585 seq_printf(seq, "\tRMON module: %s\n",
1586 (priv->dma_cap.rmon) ? "Y" : "N");
1587 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1588 (priv->dma_cap.time_stamp) ? "Y" : "N");
1589 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1590 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1591 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1592 (priv->dma_cap.eee) ? "Y" : "N");
1593 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1594 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1595 (priv->dma_cap.tx_coe) ? "Y" : "N");
1596 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1597 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1598 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1599 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1600 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1601 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1602 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1603 priv->dma_cap.number_rx_channel);
1604 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1605 priv->dma_cap.number_tx_channel);
1606 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1607 (priv->dma_cap.enh_desc) ? "Y" : "N");
1608
1609 return 0;
1610}
1611
1612static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1613{
1614 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1615}
1616
1617static const struct file_operations stmmac_dma_cap_fops = {
1618 .owner = THIS_MODULE,
1619 .open = stmmac_sysfs_dma_cap_open,
1620 .read = seq_read,
1621 .llseek = seq_lseek,
1622 .release = seq_release,
1623};
1624
7ac29055
GC		 1625static int stmmac_init_fs(struct net_device *dev)
1626{
1627 /* Create debugfs entries */
1628 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1629
1630 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1631 pr_err("ERROR %s, debugfs create directory failed\n",
1632 STMMAC_RESOURCE_NAME);
1633
1634 return -ENOMEM;
1635 }
1636
1637 /* Entry to report DMA RX/TX rings */
1638 stmmac_rings_status = debugfs_create_file("descriptors_status",
1639 S_IRUGO, stmmac_fs_dir, dev,
1640 &stmmac_rings_status_fops);
1641
1642 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1643 pr_info("ERROR creating stmmac ring debugfs file\n");
1644 debugfs_remove(stmmac_fs_dir);
1645
1646 return -ENOMEM;
1647 }
1648
e7434821
GC		 1649 /* Entry to report the DMA HW features */
1650 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1651 dev, &stmmac_dma_cap_fops);
1652
1653 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1654 pr_info("ERROR creating stmmac MMC debugfs file\n");
1655 debugfs_remove(stmmac_rings_status);
1656 debugfs_remove(stmmac_fs_dir);
1657
1658 return -ENOMEM;
1659 }
1660
7ac29055
GC		 1661 return 0;
1662}
1663
1664static void stmmac_exit_fs(void)
1665{
1666 debugfs_remove(stmmac_rings_status);
e7434821 1667 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 1668 debugfs_remove(stmmac_fs_dir);
1669}
1670#endif /* CONFIG_STMMAC_DEBUG_FS */
1671
47dd7a54
GC		 1672static const struct net_device_ops stmmac_netdev_ops = {
1673 .ndo_open = stmmac_open,
1674 .ndo_start_xmit = stmmac_xmit,
1675 .ndo_stop = stmmac_release,
1676 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 1677 .ndo_fix_features = stmmac_fix_features,
01789349 1678 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 1679 .ndo_tx_timeout = stmmac_tx_timeout,
1680 .ndo_do_ioctl = stmmac_ioctl,
1681 .ndo_set_config = stmmac_config,
47dd7a54
GC		 1682#ifdef CONFIG_NET_POLL_CONTROLLER
1683 .ndo_poll_controller = stmmac_poll_controller,
1684#endif
1685 .ndo_set_mac_address = eth_mac_addr,
1686};
1687
1688/**
1689 * stmmac_probe - Initialization of the adapter .
1690 * @dev : device pointer
1691 * Description: The function initializes the network device structure for
1692 * the STMMAC driver. It also calls the low level routines
1693 * in order to init the HW (i.e. the DMA engine)
1694 */
1695static int stmmac_probe(struct net_device *dev)
1696{
1697 int ret = 0;
1698 struct stmmac_priv *priv = netdev_priv(dev);
1699
1700 ether_setup(dev);
1701
1702 dev->netdev_ops = &stmmac_netdev_ops;
1703 stmmac_set_ethtool_ops(dev);
1704
5e982f3b
MM		 1705 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1706 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
47dd7a54
GC		 1707 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1708#ifdef STMMAC_VLAN_TAG_USED
1709 /* Both mac100 and gmac support receive VLAN tag detection */
1710 dev->features |= NETIF_F_HW_VLAN_RX;
1711#endif
1712 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1713
47dd7a54
GC		 1714 if (flow_ctrl)
1715 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1716
1717 priv->pause = pause;
1718 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1719
1720 /* Get the MAC address */
ad01b7d4
GC		 1721 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1722 dev->dev_addr, 0);
47dd7a54
GC		 1723
1724 if (!is_valid_ether_addr(dev->dev_addr))
1725 pr_warning("\tno valid MAC address;"
1726 "please, use ifconfig or nwhwconfig!\n");
1727
f8e96161 1728 spin_lock_init(&priv->lock);
a9097a96 1729 spin_lock_init(&priv->tx_lock);
f8e96161 1730
47dd7a54
GC		 1731 ret = register_netdev(dev);
1732 if (ret) {
1733 pr_err("%s: ERROR %i registering the device\n",
1734 __func__, ret);
1735 return -ENODEV;
1736 }
1737
1738 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1739 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
79032644 1740 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
47dd7a54 1741
47dd7a54
GC		 1742 return ret;
1743}
1744
1745/**
1746 * stmmac_mac_device_setup
1747 * @dev : device pointer
1748 * Description: select and initialise the mac device (mac100 or Gmac).
1749 */
1750static int stmmac_mac_device_setup(struct net_device *dev)
1751{
1752 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1753
1754 struct mac_device_info *device;
1755
01789349
JP		 1756 if (priv->plat->has_gmac) {
1757 dev->priv_flags |= IFF_UNICAST_FLT;
ad01b7d4 1758 device = dwmac1000_setup(priv->ioaddr);
01789349 1759 } else {
ad01b7d4 1760 device = dwmac100_setup(priv->ioaddr);
01789349 1761 }
3d90c508 1762
1ff21906
DC		 1763 if (!device)
1764 return -ENOMEM;
1765
9dfeb4d9 1766 if (priv->plat->enh_desc) {
3d90c508
GC		 1767 device->desc = &enh_desc_ops;
1768 pr_info("\tEnhanced descriptor structure\n");
1769 } else
56b106ae 1770 device->desc = &ndesc_ops;
47dd7a54 1771
db98a0b0 1772 priv->hw = device;
286a8372 1773 priv->hw->ring = &ring_mode_ops;
47dd7a54 1774
539c9aa5 1775 if (device_can_wakeup(priv->device)) {
543876c9 1776 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
3172d3af 1777 enable_irq_wake(priv->wol_irq);
539c9aa5 1778 }
47dd7a54
GC		 1779
1780 return 0;
1781}
1782
47dd7a54
GC		 1783/**
1784 * stmmac_dvr_probe
1785 * @pdev: platform device pointer
1786 * Description: the driver is initialized through platform_device.
1787 */
1788static int stmmac_dvr_probe(struct platform_device *pdev)
1789{
1790 int ret = 0;
1791 struct resource *res;
ad01b7d4 1792 void __iomem *addr = NULL;
47dd7a54 1793 struct net_device *ndev = NULL;
293bb1c4 1794 struct stmmac_priv *priv = NULL;
47dd7a54
GC		 1795 struct plat_stmmacenet_data *plat_dat;
1796
1797 pr_info("STMMAC driver:\n\tplatform registration... ");
1798 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
34a52f36
DC		 1799 if (!res)
1800 return -ENODEV;
ebbb293f 1801 pr_info("\tdone!\n");
47dd7a54 1802
b6222682 1803 if (!request_mem_region(res->start, resource_size(res),
47dd7a54
GC		 1804 pdev->name)) {
1805 pr_err("%s: ERROR: memory allocation failed"
1806 "cannot get the I/O addr 0x%x\n",
1807 __func__, (unsigned int)res->start);
34a52f36 1808 return -EBUSY;
47dd7a54
GC		 1809 }
1810
7c5365bc 1811 addr = ioremap(res->start, resource_size(res));
47dd7a54 1812 if (!addr) {
7c5365bc 1813 pr_err("%s: ERROR: memory mapping failed\n", __func__);
47dd7a54 1814 ret = -ENOMEM;
34a52f36 1815 goto out_release_region;
47dd7a54
GC		 1816 }
1817
1818 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1819 if (!ndev) {
1820 pr_err("%s: ERROR: allocating the device\n", __func__);
1821 ret = -ENOMEM;
34a52f36 1822 goto out_unmap;
47dd7a54
GC		 1823 }
1824
1825 SET_NETDEV_DEV(ndev, &pdev->dev);
1826
1827 /* Get the MAC information */
1828 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1829 if (ndev->irq == -ENXIO) {
1830 pr_err("%s: ERROR: MAC IRQ configuration "
1831 "information not found\n", __func__);
34a52f36
DC		 1832 ret = -ENXIO;
1833 goto out_free_ndev;
47dd7a54
GC		 1834 }
1835
1836 priv = netdev_priv(ndev);
1837 priv->device = &(pdev->dev);
1838 priv->dev = ndev;
ee7946a7 1839 plat_dat = pdev->dev.platform_data;
9dfeb4d9
GC		 1840
1841 priv->plat = plat_dat;
1842
ad01b7d4 1843 priv->ioaddr = addr;
47dd7a54 1844
543876c9
GC		 1845 /* PMT module is not integrated in all the MAC devices. */
1846 if (plat_dat->pmt) {
1847 pr_info("\tPMT module supported\n");
1848 device_set_wakeup_capable(&pdev->dev, 1);
1849 }
3172d3af
DS		 1850 /*
1851 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1852 * The external wake up irq can be passed through the platform code
1853 * named as "eth_wake_irq"
1854 *
1855 * In case the wake up interrupt is not passed from the platform
1856 * so the driver will continue to use the mac irq (ndev->irq)
1857 */
1858 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1859 if (priv->wol_irq == -ENXIO)
1860 priv->wol_irq = ndev->irq;
1861
543876c9 1862
47dd7a54
GC		 1863 platform_set_drvdata(pdev, ndev);
1864
1865 /* Set the I/O base addr */
1866 ndev->base_addr = (unsigned long)addr;
1867
293bb1c4
GC		 1868 /* Custom initialisation */
1869 if (priv->plat->init) {
1870 ret = priv->plat->init(pdev);
1871 if (unlikely(ret))
34a52f36 1872 goto out_free_ndev;
293bb1c4 1873 }
ee7946a7 1874
47dd7a54
GC		 1875 /* MAC HW revice detection */
1876 ret = stmmac_mac_device_setup(ndev);
1877 if (ret < 0)
34a52f36 1878 goto out_plat_exit;
47dd7a54
GC		 1879
1880 /* Network Device Registration */
1881 ret = stmmac_probe(ndev);
1882 if (ret < 0)
34a52f36 1883 goto out_plat_exit;
47dd7a54 1884
36bcfe7d
GC		 1885 /* Override with kernel parameters if supplied XXX CRS XXX
1886 * this needs to have multiple instances */
1887 if ((phyaddr >= 0) && (phyaddr <= 31))
1888 priv->plat->phy_addr = phyaddr;
47dd7a54 1889
47dd7a54 1890 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1f0f6388
DM		 1891 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1892 pdev->id, ndev->irq, addr);
47dd7a54
GC		 1893
1894 /* MDIO bus Registration */
9dfeb4d9 1895 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
47dd7a54
GC		 1896 ret = stmmac_mdio_register(ndev);
1897 if (ret < 0)
34a52f36 1898 goto out_unregister;
47dd7a54 1899 pr_debug("registered!\n");
7ac29055
GC		 1900
1901#ifdef CONFIG_STMMAC_DEBUG_FS
1902 ret = stmmac_init_fs(ndev);
1903 if (ret < 0)
1904 pr_warning("\tFailed debugFS registration");
1905#endif
1906
34a52f36 1907 return 0;
47dd7a54 1908
34a52f36
DC		 1909out_unregister:
1910 unregister_netdev(ndev);
1911out_plat_exit:
1912 if (priv->plat->exit)
1913 priv->plat->exit(pdev);
1914out_free_ndev:
1915 free_netdev(ndev);
1916 platform_set_drvdata(pdev, NULL);
1917out_unmap:
1918 iounmap(addr);
1919out_release_region:
1920 release_mem_region(res->start, resource_size(res));
47dd7a54
GC		 1921
1922 return ret;
1923}
1924
1925/**
1926 * stmmac_dvr_remove
1927 * @pdev: platform device pointer
1928 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1929 * changes the link status, releases the DMA descriptor rings,
1930 * unregisters the MDIO bus and unmaps the allocated memory.
1931 */
1932static int stmmac_dvr_remove(struct platform_device *pdev)
1933{
1934 struct net_device *ndev = platform_get_drvdata(pdev);
aec7ff27 1935 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1936 struct resource *res;
1937
1938 pr_info("%s:\n\tremoving driver", __func__);
1939
ad01b7d4
GC		 1940 priv->hw->dma->stop_rx(priv->ioaddr);
1941 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1942
19449bfc 1943 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 1944
1945 netif_carrier_off(ndev);
1946
1947 stmmac_mdio_unregister(ndev);
1948
293bb1c4
GC		 1949 if (priv->plat->exit)
1950 priv->plat->exit(pdev);
1951
47dd7a54
GC		 1952 platform_set_drvdata(pdev, NULL);
1953 unregister_netdev(ndev);
1954
ad01b7d4 1955 iounmap((void *)priv->ioaddr);
47dd7a54 1956 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7c5365bc 1957 release_mem_region(res->start, resource_size(res));
47dd7a54 1958
7ac29055
GC		 1959#ifdef CONFIG_STMMAC_DEBUG_FS
1960 stmmac_exit_fs();
1961#endif
1962
47dd7a54
GC		 1963 free_netdev(ndev);
1964
1965 return 0;
1966}
1967
1968#ifdef CONFIG_PM
874bd42d 1969static int stmmac_suspend(struct device *dev)
47dd7a54 1970{
874bd42d
GC		 1971 struct net_device *ndev = dev_get_drvdata(dev);
1972 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 1973 int dis_ic = 0;
1974
874bd42d 1975 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 1976 return 0;
1977
1978 spin_lock(&priv->lock);
1979
874bd42d
GC		 1980 netif_device_detach(ndev);
1981 netif_stop_queue(ndev);
1982 if (priv->phydev)
1983 phy_stop(priv->phydev);
47dd7a54
GC		 1984
1985#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 1986 priv->tm->timer_stop();
1987 if (likely(priv->tm->enable))
1988 dis_ic = 1;
47dd7a54 1989#endif
874bd42d
GC		 1990 napi_disable(&priv->napi);
1991
1992 /* Stop TX/RX DMA */
1993 priv->hw->dma->stop_tx(priv->ioaddr);
1994 priv->hw->dma->stop_rx(priv->ioaddr);
1995 /* Clear the Rx/Tx descriptors */
1996 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1997 dis_ic);
1998 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1999
2000 /* Enable Power down mode by programming the PMT regs */
2001 if (device_may_wakeup(priv->device))
2002 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2003 else
2004 stmmac_disable_mac(priv->ioaddr);
47dd7a54
GC		 2005
2006 spin_unlock(&priv->lock);
2007 return 0;
2008}
2009
874bd42d 2010static int stmmac_resume(struct device *dev)
47dd7a54 2011{
874bd42d
GC		 2012 struct net_device *ndev = dev_get_drvdata(dev);
2013 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54 2014
874bd42d 2015 if (!netif_running(ndev))
47dd7a54
GC		 2016 return 0;
2017
c4433be6
GC		 2018 spin_lock(&priv->lock);
2019
47dd7a54
GC		 2020 /* Power Down bit, into the PM register, is cleared
2021 * automatically as soon as a magic packet or a Wake-up frame
2022 * is received. Anyway, it's better to manually clear
2023 * this bit because it can generate problems while resuming
2024 * from another devices (e.g. serial console). */
874bd42d 2025 if (device_may_wakeup(priv->device))
543876c9 2026 priv->hw->mac->pmt(priv->ioaddr, 0);
47dd7a54 2027
874bd42d 2028 netif_device_attach(ndev);
47dd7a54
GC		 2029
2030 /* Enable the MAC and DMA */
19449bfc 2031 stmmac_enable_mac(priv->ioaddr);
ad01b7d4
GC		 2032 priv->hw->dma->start_tx(priv->ioaddr);
2033 priv->hw->dma->start_rx(priv->ioaddr);
47dd7a54
GC		 2034
2035#ifdef CONFIG_STMMAC_TIMER
874bd42d
GC		 2036 if (likely(priv->tm->enable))
2037 priv->tm->timer_start(tmrate);
47dd7a54
GC		 2038#endif
2039 napi_enable(&priv->napi);
2040
2041 if (priv->phydev)
2042 phy_start(priv->phydev);
2043
874bd42d 2044 netif_start_queue(ndev);
47dd7a54 2045
47dd7a54
GC		 2046 spin_unlock(&priv->lock);
2047 return 0;
2048}
47dd7a54 2049
874bd42d
GC		 2050static int stmmac_freeze(struct device *dev)
2051{
2052 struct net_device *ndev = dev_get_drvdata(dev);
2053
2054 if (!ndev || !netif_running(ndev))
2055 return 0;
2056
2057 return stmmac_release(ndev);
2058}
2059
2060static int stmmac_restore(struct device *dev)
2061{
2062 struct net_device *ndev = dev_get_drvdata(dev);
2063
2064 if (!ndev || !netif_running(ndev))
2065 return 0;
2066
2067 return stmmac_open(ndev);
2068}
2069
2070static const struct dev_pm_ops stmmac_pm_ops = {
47dd7a54
GC		 2071 .suspend = stmmac_suspend,
2072 .resume = stmmac_resume,
874bd42d
GC		 2073 .freeze = stmmac_freeze,
2074 .thaw = stmmac_restore,
2075 .restore = stmmac_restore,
2076};
2077#else
2078static const struct dev_pm_ops stmmac_pm_ops;
2079#endif /* CONFIG_PM */
47dd7a54 2080
874bd42d
GC		 2081static struct platform_driver stmmac_driver = {
2082 .probe = stmmac_dvr_probe,
2083 .remove = stmmac_dvr_remove,
2084 .driver = {
2085 .name = STMMAC_RESOURCE_NAME,
2086 .owner = THIS_MODULE,
2087 .pm = &stmmac_pm_ops,
2088 },
47dd7a54
GC		 2089};
2090
2091/**
2092 * stmmac_init_module - Entry point for the driver
2093 * Description: This function is the entry point for the driver.
2094 */
2095static int __init stmmac_init_module(void)
2096{
2097 int ret;
2098
47dd7a54
GC		 2099 ret = platform_driver_register(&stmmac_driver);
2100 return ret;
2101}
2102
2103/**
2104 * stmmac_cleanup_module - Cleanup routine for the driver
2105 * Description: This function is the cleanup routine for the driver.
2106 */
2107static void __exit stmmac_cleanup_module(void)
2108{
47dd7a54
GC		 2109 platform_driver_unregister(&stmmac_driver);
2110}
2111
2112#ifndef MODULE
2113static int __init stmmac_cmdline_opt(char *str)
2114{
2115 char *opt;
2116
2117 if (!str || !*str)
2118 return -EINVAL;
2119 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28
GC		 2120 if (!strncmp(opt, "debug:", 6)) {
2121 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2122 goto err;
2123 } else if (!strncmp(opt, "phyaddr:", 8)) {
2124 if (strict_strtoul(opt + 8, 0,
2125 (unsigned long *)&phyaddr))
2126 goto err;
2127 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2128 if (strict_strtoul(opt + 11, 0,
2129 (unsigned long *)&dma_txsize))
2130 goto err;
2131 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2132 if (strict_strtoul(opt + 11, 0,
2133 (unsigned long *)&dma_rxsize))
2134 goto err;
2135 } else if (!strncmp(opt, "buf_sz:", 7)) {
2136 if (strict_strtoul(opt + 7, 0,
2137 (unsigned long *)&buf_sz))
2138 goto err;
2139 } else if (!strncmp(opt, "tc:", 3)) {
2140 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2141 goto err;
2142 } else if (!strncmp(opt, "watchdog:", 9)) {
2143 if (strict_strtoul(opt + 9, 0,
2144 (unsigned long *)&watchdog))
2145 goto err;
2146 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2147 if (strict_strtoul(opt + 10, 0,
2148 (unsigned long *)&flow_ctrl))
2149 goto err;
2150 } else if (!strncmp(opt, "pause:", 6)) {
2151 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2152 goto err;
47dd7a54 2153#ifdef CONFIG_STMMAC_TIMER
f3240e28
GC		 2154 } else if (!strncmp(opt, "tmrate:", 7)) {
2155 if (strict_strtoul(opt + 7, 0,
2156 (unsigned long *)&tmrate))
2157 goto err;
47dd7a54 2158#endif
f3240e28 2159 }
47dd7a54
GC		 2160 }
2161 return 0;
f3240e28
GC		 2162
2163err:
2164 pr_err("%s: ERROR broken module parameter conversion", __func__);
2165 return -EINVAL;
47dd7a54
GC		 2166}
2167
2168__setup("stmmaceth=", stmmac_cmdline_opt);
2169#endif
2170
2171module_init(stmmac_init_module);
2172module_exit(stmmac_cleanup_module);
2173
2174MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2175MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2176MODULE_LICENSE("GPL");
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