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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/interrupt.h> | |
47dd7a54 GC |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/ip.h> | |
38 | #include <linux/tcp.h> | |
39 | #include <linux/skbuff.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_ether.h> | |
42 | #include <linux/crc32.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/phy.h> | |
01789349 | 45 | #include <linux/if.h> |
47dd7a54 GC |
46 | #include <linux/if_vlan.h> |
47 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 48 | #include <linux/slab.h> |
70c71606 | 49 | #include <linux/prefetch.h> |
47dd7a54 | 50 | #include "stmmac.h" |
7ac29055 GC |
51 | #ifdef CONFIG_STMMAC_DEBUG_FS |
52 | #include <linux/debugfs.h> | |
53 | #include <linux/seq_file.h> | |
54 | #endif | |
47dd7a54 GC |
55 | |
56 | #define STMMAC_RESOURCE_NAME "stmmaceth" | |
47dd7a54 GC |
57 | |
58 | #undef STMMAC_DEBUG | |
59 | /*#define STMMAC_DEBUG*/ | |
60 | #ifdef STMMAC_DEBUG | |
61 | #define DBG(nlevel, klevel, fmt, args...) \ | |
62 | ((void)(netif_msg_##nlevel(priv) && \ | |
63 | printk(KERN_##klevel fmt, ## args))) | |
64 | #else | |
65 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
66 | #endif | |
67 | ||
68 | #undef STMMAC_RX_DEBUG | |
69 | /*#define STMMAC_RX_DEBUG*/ | |
70 | #ifdef STMMAC_RX_DEBUG | |
71 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
72 | #else | |
73 | #define RX_DBG(fmt, args...) do { } while (0) | |
74 | #endif | |
75 | ||
76 | #undef STMMAC_XMIT_DEBUG | |
77 | /*#define STMMAC_XMIT_DEBUG*/ | |
78 | #ifdef STMMAC_TX_DEBUG | |
79 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
80 | #else | |
81 | #define TX_DBG(fmt, args...) do { } while (0) | |
82 | #endif | |
83 | ||
84 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
85 | #define JUMBO_LEN 9000 | |
86 | ||
87 | /* Module parameters */ | |
88 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
89 | static int watchdog = TX_TIMEO; | |
90 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
91 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
92 | ||
93 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
94 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
95 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
96 | ||
97 | static int phyaddr = -1; | |
98 | module_param(phyaddr, int, S_IRUGO); | |
99 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
100 | ||
101 | #define DMA_TX_SIZE 256 | |
102 | static int dma_txsize = DMA_TX_SIZE; | |
103 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
104 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
105 | ||
106 | #define DMA_RX_SIZE 256 | |
107 | static int dma_rxsize = DMA_RX_SIZE; | |
108 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
109 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
110 | ||
111 | static int flow_ctrl = FLOW_OFF; | |
112 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
113 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
114 | ||
115 | static int pause = PAUSE_TIME; | |
116 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
117 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
118 | ||
119 | #define TC_DEFAULT 64 | |
120 | static int tc = TC_DEFAULT; | |
121 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
122 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
123 | ||
47dd7a54 GC |
124 | /* Pay attention to tune this parameter; take care of both |
125 | * hardware capability and network stabitily/performance impact. | |
126 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
127 | #ifdef CONFIG_STMMAC_TIMER | |
128 | #define DEFAULT_PERIODIC_RATE 256 | |
129 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
130 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
131 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
132 | #endif | |
133 | ||
134 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
135 | static int buf_sz = DMA_BUFFER_SIZE; | |
136 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
137 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
138 | ||
47dd7a54 GC |
139 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
140 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
141 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
142 | ||
143 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 GC |
144 | |
145 | /** | |
146 | * stmmac_verify_args - verify the driver parameters. | |
147 | * Description: it verifies if some wrong parameter is passed to the driver. | |
148 | * Note that wrong parameters are replaced with the default values. | |
149 | */ | |
150 | static void stmmac_verify_args(void) | |
151 | { | |
152 | if (unlikely(watchdog < 0)) | |
153 | watchdog = TX_TIMEO; | |
154 | if (unlikely(dma_rxsize < 0)) | |
155 | dma_rxsize = DMA_RX_SIZE; | |
156 | if (unlikely(dma_txsize < 0)) | |
157 | dma_txsize = DMA_TX_SIZE; | |
158 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
159 | buf_sz = DMA_BUFFER_SIZE; | |
160 | if (unlikely(flow_ctrl > 1)) | |
161 | flow_ctrl = FLOW_AUTO; | |
162 | else if (likely(flow_ctrl < 0)) | |
163 | flow_ctrl = FLOW_OFF; | |
164 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
165 | pause = PAUSE_TIME; | |
47dd7a54 GC |
166 | } |
167 | ||
168 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) | |
169 | static void print_pkt(unsigned char *buf, int len) | |
170 | { | |
171 | int j; | |
172 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
173 | for (j = 0; j < len; j++) { | |
174 | if ((j % 16) == 0) | |
175 | pr_info("\n %03x:", j); | |
176 | pr_info(" %02x", buf[j]); | |
177 | } | |
178 | pr_info("\n"); | |
47dd7a54 GC |
179 | } |
180 | #endif | |
181 | ||
182 | /* minimum number of free TX descriptors required to wake up TX process */ | |
183 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
184 | ||
185 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
186 | { | |
187 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
188 | } | |
189 | ||
9dfeb4d9 GC |
190 | /* On some ST platforms, some HW system configuraton registers have to be |
191 | * set according to the link speed negotiated. | |
192 | */ | |
193 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
194 | { | |
195 | struct phy_device *phydev = priv->phydev; | |
196 | ||
197 | if (likely(priv->plat->fix_mac_speed)) | |
198 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
199 | phydev->speed); | |
200 | } | |
201 | ||
47dd7a54 GC |
202 | /** |
203 | * stmmac_adjust_link | |
204 | * @dev: net device structure | |
205 | * Description: it adjusts the link parameters. | |
206 | */ | |
207 | static void stmmac_adjust_link(struct net_device *dev) | |
208 | { | |
209 | struct stmmac_priv *priv = netdev_priv(dev); | |
210 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
211 | unsigned long flags; |
212 | int new_state = 0; | |
213 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
214 | ||
215 | if (phydev == NULL) | |
216 | return; | |
217 | ||
218 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
219 | phydev->addr, phydev->link); | |
220 | ||
221 | spin_lock_irqsave(&priv->lock, flags); | |
222 | if (phydev->link) { | |
ad01b7d4 | 223 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
224 | |
225 | /* Now we make sure that we can be in full duplex mode. | |
226 | * If not, we operate in half-duplex mode. */ | |
227 | if (phydev->duplex != priv->oldduplex) { | |
228 | new_state = 1; | |
229 | if (!(phydev->duplex)) | |
db98a0b0 | 230 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 231 | else |
db98a0b0 | 232 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
233 | priv->oldduplex = phydev->duplex; |
234 | } | |
235 | /* Flow Control operation */ | |
236 | if (phydev->pause) | |
ad01b7d4 | 237 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 238 | fc, pause_time); |
47dd7a54 GC |
239 | |
240 | if (phydev->speed != priv->speed) { | |
241 | new_state = 1; | |
242 | switch (phydev->speed) { | |
243 | case 1000: | |
9dfeb4d9 | 244 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 245 | ctrl &= ~priv->hw->link.port; |
9dfeb4d9 | 246 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
247 | break; |
248 | case 100: | |
249 | case 10: | |
9dfeb4d9 | 250 | if (priv->plat->has_gmac) { |
db98a0b0 | 251 | ctrl |= priv->hw->link.port; |
47dd7a54 | 252 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 253 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 254 | } else { |
db98a0b0 | 255 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
256 | } |
257 | } else { | |
db98a0b0 | 258 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 259 | } |
9dfeb4d9 | 260 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
261 | break; |
262 | default: | |
263 | if (netif_msg_link(priv)) | |
264 | pr_warning("%s: Speed (%d) is not 10" | |
265 | " or 100!\n", dev->name, phydev->speed); | |
266 | break; | |
267 | } | |
268 | ||
269 | priv->speed = phydev->speed; | |
270 | } | |
271 | ||
ad01b7d4 | 272 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
273 | |
274 | if (!priv->oldlink) { | |
275 | new_state = 1; | |
276 | priv->oldlink = 1; | |
277 | } | |
278 | } else if (priv->oldlink) { | |
279 | new_state = 1; | |
280 | priv->oldlink = 0; | |
281 | priv->speed = 0; | |
282 | priv->oldduplex = -1; | |
283 | } | |
284 | ||
285 | if (new_state && netif_msg_link(priv)) | |
286 | phy_print_status(phydev); | |
287 | ||
288 | spin_unlock_irqrestore(&priv->lock, flags); | |
289 | ||
290 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
291 | } | |
292 | ||
293 | /** | |
294 | * stmmac_init_phy - PHY initialization | |
295 | * @dev: net device structure | |
296 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
297 | * to the mac driver. | |
298 | * Return value: | |
299 | * 0 on success | |
300 | */ | |
301 | static int stmmac_init_phy(struct net_device *dev) | |
302 | { | |
303 | struct stmmac_priv *priv = netdev_priv(dev); | |
304 | struct phy_device *phydev; | |
109cdd66 GC |
305 | char phy_id[MII_BUS_ID_SIZE + 3]; |
306 | char bus_id[MII_BUS_ID_SIZE]; | |
47dd7a54 GC |
307 | |
308 | priv->oldlink = 0; | |
309 | priv->speed = 0; | |
310 | priv->oldduplex = -1; | |
311 | ||
9dfeb4d9 | 312 | snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id); |
109cdd66 | 313 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 314 | priv->plat->phy_addr); |
47dd7a54 GC |
315 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
316 | ||
317 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, | |
36bcfe7d | 318 | priv->plat->interface); |
47dd7a54 GC |
319 | |
320 | if (IS_ERR(phydev)) { | |
321 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
322 | return PTR_ERR(phydev); | |
323 | } | |
324 | ||
325 | /* | |
326 | * Broken HW is sometimes missing the pull-up resistor on the | |
327 | * MDIO line, which results in reads to non-existent devices returning | |
328 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
329 | * device as well. | |
330 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
331 | */ | |
332 | if (phydev->phy_id == 0) { | |
333 | phy_disconnect(phydev); | |
334 | return -ENODEV; | |
335 | } | |
336 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 337 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
338 | |
339 | priv->phydev = phydev; | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
19449bfc | 344 | static inline void stmmac_enable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
345 | { |
346 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 347 | |
19449bfc | 348 | value |= MAC_RNABLE_RX | MAC_ENABLE_TX; |
47dd7a54 GC |
349 | writel(value, ioaddr + MAC_CTRL_REG); |
350 | } | |
351 | ||
19449bfc | 352 | static inline void stmmac_disable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
353 | { |
354 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 355 | |
19449bfc | 356 | value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); |
47dd7a54 GC |
357 | writel(value, ioaddr + MAC_CTRL_REG); |
358 | } | |
359 | ||
360 | /** | |
361 | * display_ring | |
362 | * @p: pointer to the ring. | |
363 | * @size: size of the ring. | |
364 | * Description: display all the descriptors within the ring. | |
365 | */ | |
366 | static void display_ring(struct dma_desc *p, int size) | |
367 | { | |
368 | struct tmp_s { | |
369 | u64 a; | |
370 | unsigned int b; | |
371 | unsigned int c; | |
372 | }; | |
373 | int i; | |
374 | for (i = 0; i < size; i++) { | |
375 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
376 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
377 | i, (unsigned int)virt_to_phys(&p[i]), | |
378 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
379 | x->b, x->c); | |
380 | pr_info("\n"); | |
381 | } | |
382 | } | |
383 | ||
384 | /** | |
385 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
386 | * @dev: net device structure | |
387 | * Description: this function initializes the DMA RX/TX descriptors | |
388 | * and allocates the socket buffers. | |
389 | */ | |
390 | static void init_dma_desc_rings(struct net_device *dev) | |
391 | { | |
392 | int i; | |
393 | struct stmmac_priv *priv = netdev_priv(dev); | |
394 | struct sk_buff *skb; | |
395 | unsigned int txsize = priv->dma_tx_size; | |
396 | unsigned int rxsize = priv->dma_rx_size; | |
397 | unsigned int bfsize = priv->dma_buf_sz; | |
73cfe264 | 398 | int buff2_needed = 0, dis_ic = 0; |
47dd7a54 | 399 | |
47dd7a54 GC |
400 | /* Set the Buffer size according to the MTU; |
401 | * indeed, in case of jumbo we need to bump-up the buffer sizes. | |
402 | */ | |
403 | if (unlikely(dev->mtu >= BUF_SIZE_8KiB)) | |
404 | bfsize = BUF_SIZE_16KiB; | |
405 | else if (unlikely(dev->mtu >= BUF_SIZE_4KiB)) | |
406 | bfsize = BUF_SIZE_8KiB; | |
407 | else if (unlikely(dev->mtu >= BUF_SIZE_2KiB)) | |
408 | bfsize = BUF_SIZE_4KiB; | |
409 | else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE)) | |
410 | bfsize = BUF_SIZE_2KiB; | |
411 | else | |
412 | bfsize = DMA_BUFFER_SIZE; | |
413 | ||
73cfe264 GC |
414 | #ifdef CONFIG_STMMAC_TIMER |
415 | /* Disable interrupts on completion for the reception if timer is on */ | |
416 | if (likely(priv->tm->enable)) | |
417 | dis_ic = 1; | |
418 | #endif | |
47dd7a54 GC |
419 | /* If the MTU exceeds 8k so use the second buffer in the chain */ |
420 | if (bfsize >= BUF_SIZE_8KiB) | |
421 | buff2_needed = 1; | |
422 | ||
423 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
424 | txsize, rxsize, bfsize); | |
425 | ||
426 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
427 | priv->rx_skbuff = | |
428 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
429 | priv->dma_rx = | |
430 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
431 | rxsize * | |
432 | sizeof(struct dma_desc), | |
433 | &priv->dma_rx_phy, | |
434 | GFP_KERNEL); | |
435 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
436 | GFP_KERNEL); | |
437 | priv->dma_tx = | |
438 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
439 | txsize * | |
440 | sizeof(struct dma_desc), | |
441 | &priv->dma_tx_phy, | |
442 | GFP_KERNEL); | |
443 | ||
444 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
445 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
446 | return; | |
447 | } | |
448 | ||
449 | DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, " | |
450 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", | |
451 | dev->name, priv->dma_rx, priv->dma_tx, | |
452 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
453 | ||
454 | /* RX INITIALIZATION */ | |
455 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
456 | "skb\t\tskb data\tdma data\n"); | |
457 | ||
458 | for (i = 0; i < rxsize; i++) { | |
459 | struct dma_desc *p = priv->dma_rx + i; | |
460 | ||
461 | skb = netdev_alloc_skb_ip_align(dev, bfsize); | |
462 | if (unlikely(skb == NULL)) { | |
463 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
464 | break; | |
465 | } | |
466 | priv->rx_skbuff[i] = skb; | |
467 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
468 | bfsize, DMA_FROM_DEVICE); | |
469 | ||
470 | p->des2 = priv->rx_skbuff_dma[i]; | |
471 | if (unlikely(buff2_needed)) | |
472 | p->des3 = p->des2 + BUF_SIZE_8KiB; | |
473 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
474 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
475 | } | |
476 | priv->cur_rx = 0; | |
477 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
478 | priv->dma_buf_sz = bfsize; | |
479 | buf_sz = bfsize; | |
480 | ||
481 | /* TX INITIALIZATION */ | |
482 | for (i = 0; i < txsize; i++) { | |
483 | priv->tx_skbuff[i] = NULL; | |
484 | priv->dma_tx[i].des2 = 0; | |
485 | } | |
486 | priv->dirty_tx = 0; | |
487 | priv->cur_tx = 0; | |
488 | ||
489 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
490 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
491 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
492 | |
493 | if (netif_msg_hw(priv)) { | |
494 | pr_info("RX descriptor ring:\n"); | |
495 | display_ring(priv->dma_rx, rxsize); | |
496 | pr_info("TX descriptor ring:\n"); | |
497 | display_ring(priv->dma_tx, txsize); | |
498 | } | |
47dd7a54 GC |
499 | } |
500 | ||
501 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
502 | { | |
503 | int i; | |
504 | ||
505 | for (i = 0; i < priv->dma_rx_size; i++) { | |
506 | if (priv->rx_skbuff[i]) { | |
507 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
508 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
509 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
510 | } | |
511 | priv->rx_skbuff[i] = NULL; | |
512 | } | |
47dd7a54 GC |
513 | } |
514 | ||
515 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
516 | { | |
517 | int i; | |
518 | ||
519 | for (i = 0; i < priv->dma_tx_size; i++) { | |
520 | if (priv->tx_skbuff[i] != NULL) { | |
521 | struct dma_desc *p = priv->dma_tx + i; | |
522 | if (p->des2) | |
523 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
524 | priv->hw->desc->get_tx_len(p), |
525 | DMA_TO_DEVICE); | |
47dd7a54 GC |
526 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
527 | priv->tx_skbuff[i] = NULL; | |
528 | } | |
529 | } | |
47dd7a54 GC |
530 | } |
531 | ||
532 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
533 | { | |
534 | /* Release the DMA TX/RX socket buffers */ | |
535 | dma_free_rx_skbufs(priv); | |
536 | dma_free_tx_skbufs(priv); | |
537 | ||
538 | /* Free the region of consistent memory previously allocated for | |
539 | * the DMA */ | |
540 | dma_free_coherent(priv->device, | |
541 | priv->dma_tx_size * sizeof(struct dma_desc), | |
542 | priv->dma_tx, priv->dma_tx_phy); | |
543 | dma_free_coherent(priv->device, | |
544 | priv->dma_rx_size * sizeof(struct dma_desc), | |
545 | priv->dma_rx, priv->dma_rx_phy); | |
546 | kfree(priv->rx_skbuff_dma); | |
547 | kfree(priv->rx_skbuff); | |
548 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
549 | } |
550 | ||
47dd7a54 GC |
551 | /** |
552 | * stmmac_dma_operation_mode - HW DMA operation mode | |
553 | * @priv : pointer to the private device structure. | |
554 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 555 | * or Store-And-Forward capability. |
47dd7a54 GC |
556 | */ |
557 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
558 | { | |
61b8013a SK |
559 | if (likely(priv->plat->force_sf_dma_mode || |
560 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
561 | /* | |
562 | * In case of GMAC, SF mode can be enabled | |
563 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
564 | * 1) TX COE if actually supported |
565 | * 2) There is no bugged Jumbo frame support | |
566 | * that needs to not insert csum in the TDES. | |
567 | */ | |
568 | priv->hw->dma->dma_mode(priv->ioaddr, | |
569 | SF_DMA_MODE, SF_DMA_MODE); | |
570 | tc = SF_DMA_MODE; | |
571 | } else | |
572 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
573 | } |
574 | ||
47dd7a54 GC |
575 | /** |
576 | * stmmac_tx: | |
577 | * @priv: private driver structure | |
578 | * Description: it reclaims resources after transmission completes. | |
579 | */ | |
580 | static void stmmac_tx(struct stmmac_priv *priv) | |
581 | { | |
582 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 GC |
583 | |
584 | while (priv->dirty_tx != priv->cur_tx) { | |
585 | int last; | |
586 | unsigned int entry = priv->dirty_tx % txsize; | |
587 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
588 | struct dma_desc *p = priv->dma_tx + entry; | |
589 | ||
590 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 591 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
592 | break; |
593 | ||
594 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 595 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
596 | if (likely(last)) { |
597 | int tx_error = | |
db98a0b0 GC |
598 | priv->hw->desc->tx_status(&priv->dev->stats, |
599 | &priv->xstats, p, | |
ad01b7d4 | 600 | priv->ioaddr); |
47dd7a54 GC |
601 | if (likely(tx_error == 0)) { |
602 | priv->dev->stats.tx_packets++; | |
603 | priv->xstats.tx_pkt_n++; | |
604 | } else | |
605 | priv->dev->stats.tx_errors++; | |
606 | } | |
607 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
608 | priv->cur_tx, priv->dirty_tx); | |
609 | ||
610 | if (likely(p->des2)) | |
611 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 612 | priv->hw->desc->get_tx_len(p), |
47dd7a54 GC |
613 | DMA_TO_DEVICE); |
614 | if (unlikely(p->des3)) | |
615 | p->des3 = 0; | |
616 | ||
617 | if (likely(skb != NULL)) { | |
618 | /* | |
619 | * If there's room in the queue (limit it to size) | |
620 | * we add this skb back into the pool, | |
621 | * if it's the right size. | |
622 | */ | |
623 | if ((skb_queue_len(&priv->rx_recycle) < | |
624 | priv->dma_rx_size) && | |
625 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
626 | __skb_queue_head(&priv->rx_recycle, skb); | |
627 | else | |
628 | dev_kfree_skb(skb); | |
629 | ||
630 | priv->tx_skbuff[entry] = NULL; | |
631 | } | |
632 | ||
db98a0b0 | 633 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
634 | |
635 | entry = (++priv->dirty_tx) % txsize; | |
636 | } | |
637 | if (unlikely(netif_queue_stopped(priv->dev) && | |
638 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
639 | netif_tx_lock(priv->dev); | |
640 | if (netif_queue_stopped(priv->dev) && | |
641 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
642 | TX_DBG("%s: restart transmit\n", __func__); | |
643 | netif_wake_queue(priv->dev); | |
644 | } | |
645 | netif_tx_unlock(priv->dev); | |
646 | } | |
47dd7a54 GC |
647 | } |
648 | ||
649 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
650 | { | |
73cfe264 GC |
651 | #ifdef CONFIG_STMMAC_TIMER |
652 | if (likely(priv->tm->enable)) | |
653 | priv->tm->timer_start(tmrate); | |
654 | else | |
47dd7a54 | 655 | #endif |
ad01b7d4 | 656 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
657 | } |
658 | ||
659 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
660 | { | |
73cfe264 GC |
661 | #ifdef CONFIG_STMMAC_TIMER |
662 | if (likely(priv->tm->enable)) | |
663 | priv->tm->timer_stop(); | |
664 | else | |
47dd7a54 | 665 | #endif |
ad01b7d4 | 666 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
667 | } |
668 | ||
669 | static int stmmac_has_work(struct stmmac_priv *priv) | |
670 | { | |
671 | unsigned int has_work = 0; | |
672 | int rxret, tx_work = 0; | |
673 | ||
db98a0b0 | 674 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
675 | (priv->cur_rx % priv->dma_rx_size)); |
676 | ||
677 | if (priv->dirty_tx != priv->cur_tx) | |
678 | tx_work = 1; | |
679 | ||
680 | if (likely(!rxret || tx_work)) | |
681 | has_work = 1; | |
682 | ||
683 | return has_work; | |
684 | } | |
685 | ||
686 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
687 | { | |
688 | if (likely(stmmac_has_work(priv))) { | |
689 | stmmac_disable_irq(priv); | |
690 | napi_schedule(&priv->napi); | |
691 | } | |
692 | } | |
693 | ||
694 | #ifdef CONFIG_STMMAC_TIMER | |
695 | void stmmac_schedule(struct net_device *dev) | |
696 | { | |
697 | struct stmmac_priv *priv = netdev_priv(dev); | |
698 | ||
699 | priv->xstats.sched_timer_n++; | |
700 | ||
701 | _stmmac_schedule(priv); | |
47dd7a54 GC |
702 | } |
703 | ||
704 | static void stmmac_no_timer_started(unsigned int x) | |
705 | {; | |
706 | }; | |
707 | ||
708 | static void stmmac_no_timer_stopped(void) | |
709 | {; | |
710 | }; | |
711 | #endif | |
712 | ||
713 | /** | |
714 | * stmmac_tx_err: | |
715 | * @priv: pointer to the private device structure | |
716 | * Description: it cleans the descriptors and restarts the transmission | |
717 | * in case of errors. | |
718 | */ | |
719 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
720 | { | |
ad01b7d4 | 721 | |
47dd7a54 GC |
722 | netif_stop_queue(priv->dev); |
723 | ||
ad01b7d4 | 724 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 725 | dma_free_tx_skbufs(priv); |
db98a0b0 | 726 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
727 | priv->dirty_tx = 0; |
728 | priv->cur_tx = 0; | |
ad01b7d4 | 729 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
730 | |
731 | priv->dev->stats.tx_errors++; | |
732 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
733 | } |
734 | ||
47dd7a54 | 735 | |
aec7ff27 GC |
736 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
737 | { | |
aec7ff27 GC |
738 | int status; |
739 | ||
ad01b7d4 | 740 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
741 | if (likely(status == handle_tx_rx)) |
742 | _stmmac_schedule(priv); | |
743 | ||
744 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
745 | /* Try to bump up the dma threshold on this failure */ | |
746 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
747 | tc += 64; | |
ad01b7d4 | 748 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 749 | priv->xstats.threshold = tc; |
47dd7a54 | 750 | } |
aec7ff27 GC |
751 | } else if (unlikely(status == tx_hard_error)) |
752 | stmmac_tx_err(priv); | |
47dd7a54 GC |
753 | } |
754 | ||
1c901a46 GC |
755 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
756 | { | |
757 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
758 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
759 | ||
760 | /* Do not manage MMC IRQ (FIXME) */ | |
761 | dwmac_mmc_intr_all_mask(priv->ioaddr); | |
762 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
763 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
764 | } | |
765 | ||
47dd7a54 GC |
766 | /** |
767 | * stmmac_open - open entry point of the driver | |
768 | * @dev : pointer to the device structure. | |
769 | * Description: | |
770 | * This function is the open entry point of the driver. | |
771 | * Return value: | |
772 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
773 | * file on failure. | |
774 | */ | |
775 | static int stmmac_open(struct net_device *dev) | |
776 | { | |
777 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
778 | int ret; |
779 | ||
780 | /* Check that the MAC address is valid. If its not, refuse | |
781 | * to bring the device up. The user must specify an | |
782 | * address using the following linux command: | |
783 | * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ | |
784 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
785 | random_ether_addr(dev->dev_addr); | |
786 | pr_warning("%s: generated random MAC address %pM\n", dev->name, | |
787 | dev->dev_addr); | |
788 | } | |
789 | ||
790 | stmmac_verify_args(); | |
791 | ||
47dd7a54 | 792 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 793 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
47dd7a54 | 794 | if (unlikely(priv->tm == NULL)) { |
2381a55c | 795 | pr_err("%s: ERROR: timer memory alloc failed\n", __func__); |
47dd7a54 GC |
796 | return -ENOMEM; |
797 | } | |
798 | priv->tm->freq = tmrate; | |
799 | ||
73cfe264 GC |
800 | /* Test if the external timer can be actually used. |
801 | * In case of failure continue without timer. */ | |
47dd7a54 | 802 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 803 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
804 | priv->tm->freq = 0; |
805 | priv->tm->timer_start = stmmac_no_timer_started; | |
806 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
807 | } else |
808 | priv->tm->enable = 1; | |
47dd7a54 | 809 | #endif |
f66ffe28 GC |
810 | ret = stmmac_init_phy(dev); |
811 | if (unlikely(ret)) { | |
812 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
813 | goto open_error; | |
814 | } | |
47dd7a54 GC |
815 | |
816 | /* Create and initialize the TX/RX descriptors chains. */ | |
817 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
818 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
819 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
820 | init_dma_desc_rings(dev); | |
821 | ||
822 | /* DMA initialization and SW reset */ | |
f66ffe28 GC |
823 | ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, |
824 | priv->dma_tx_phy, priv->dma_rx_phy); | |
825 | if (ret < 0) { | |
47dd7a54 | 826 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 827 | goto open_error; |
47dd7a54 GC |
828 | } |
829 | ||
830 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 831 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
ca5f12c1 | 832 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
833 | if (priv->plat->bus_setup) |
834 | priv->plat->bus_setup(priv->ioaddr); | |
47dd7a54 | 835 | /* Initialize the MAC Core */ |
ad01b7d4 | 836 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 837 | |
ebbb293f GC |
838 | priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); |
839 | if (priv->rx_coe) | |
840 | pr_info("stmmac: Rx Checksum Offload Engine supported\n"); | |
9dfeb4d9 | 841 | if (priv->plat->tx_coe) |
ebbb293f | 842 | pr_info("\tTX Checksum insertion supported\n"); |
5e982f3b | 843 | netdev_update_features(dev); |
ebbb293f | 844 | |
f66ffe28 GC |
845 | /* Request the IRQ lines */ |
846 | ret = request_irq(dev->irq, stmmac_interrupt, | |
847 | IRQF_SHARED, dev->name, dev); | |
848 | if (unlikely(ret < 0)) { | |
849 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
850 | __func__, dev->irq, ret); | |
851 | goto open_error; | |
852 | } | |
853 | ||
47dd7a54 | 854 | /* Enable the MAC Rx/Tx */ |
19449bfc | 855 | stmmac_enable_mac(priv->ioaddr); |
47dd7a54 GC |
856 | |
857 | /* Set the HW DMA mode and the COE */ | |
858 | stmmac_dma_operation_mode(priv); | |
859 | ||
860 | /* Extra statistics */ | |
861 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
862 | priv->xstats.threshold = tc; | |
863 | ||
1c901a46 GC |
864 | stmmac_mmc_setup(priv); |
865 | ||
47dd7a54 GC |
866 | /* Start the ball rolling... */ |
867 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
868 | priv->hw->dma->start_tx(priv->ioaddr); |
869 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
870 | |
871 | #ifdef CONFIG_STMMAC_TIMER | |
872 | priv->tm->timer_start(tmrate); | |
873 | #endif | |
874 | /* Dump DMA/MAC registers */ | |
875 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
876 | priv->hw->mac->dump_regs(priv->ioaddr); |
877 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
878 | } |
879 | ||
880 | if (priv->phydev) | |
881 | phy_start(priv->phydev); | |
882 | ||
883 | napi_enable(&priv->napi); | |
884 | skb_queue_head_init(&priv->rx_recycle); | |
885 | netif_start_queue(dev); | |
f66ffe28 | 886 | |
47dd7a54 | 887 | return 0; |
f66ffe28 GC |
888 | |
889 | open_error: | |
890 | #ifdef CONFIG_STMMAC_TIMER | |
891 | kfree(priv->tm); | |
892 | #endif | |
893 | if (priv->phydev) | |
894 | phy_disconnect(priv->phydev); | |
895 | ||
896 | return ret; | |
47dd7a54 GC |
897 | } |
898 | ||
899 | /** | |
900 | * stmmac_release - close entry point of the driver | |
901 | * @dev : device pointer. | |
902 | * Description: | |
903 | * This is the stop entry point of the driver. | |
904 | */ | |
905 | static int stmmac_release(struct net_device *dev) | |
906 | { | |
907 | struct stmmac_priv *priv = netdev_priv(dev); | |
908 | ||
909 | /* Stop and disconnect the PHY */ | |
910 | if (priv->phydev) { | |
911 | phy_stop(priv->phydev); | |
912 | phy_disconnect(priv->phydev); | |
913 | priv->phydev = NULL; | |
914 | } | |
915 | ||
916 | netif_stop_queue(dev); | |
917 | ||
918 | #ifdef CONFIG_STMMAC_TIMER | |
919 | /* Stop and release the timer */ | |
920 | stmmac_close_ext_timer(); | |
921 | if (priv->tm != NULL) | |
922 | kfree(priv->tm); | |
923 | #endif | |
924 | napi_disable(&priv->napi); | |
925 | skb_queue_purge(&priv->rx_recycle); | |
926 | ||
927 | /* Free the IRQ lines */ | |
928 | free_irq(dev->irq, dev); | |
929 | ||
930 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
931 | priv->hw->dma->stop_tx(priv->ioaddr); |
932 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
933 | |
934 | /* Release and free the Rx/Tx resources */ | |
935 | free_dma_desc_resources(priv); | |
936 | ||
19449bfc | 937 | /* Disable the MAC Rx/Tx */ |
938 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
939 | |
940 | netif_carrier_off(dev); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
47dd7a54 GC |
945 | static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb, |
946 | struct net_device *dev, | |
947 | int csum_insertion) | |
948 | { | |
949 | struct stmmac_priv *priv = netdev_priv(dev); | |
950 | unsigned int nopaged_len = skb_headlen(skb); | |
951 | unsigned int txsize = priv->dma_tx_size; | |
952 | unsigned int entry = priv->cur_tx % txsize; | |
953 | struct dma_desc *desc = priv->dma_tx + entry; | |
954 | ||
955 | if (nopaged_len > BUF_SIZE_8KiB) { | |
956 | ||
957 | int buf2_size = nopaged_len - BUF_SIZE_8KiB; | |
958 | ||
959 | desc->des2 = dma_map_single(priv->device, skb->data, | |
960 | BUF_SIZE_8KiB, DMA_TO_DEVICE); | |
961 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
962 | priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB, |
963 | csum_insertion); | |
47dd7a54 GC |
964 | |
965 | entry = (++priv->cur_tx) % txsize; | |
966 | desc = priv->dma_tx + entry; | |
967 | ||
968 | desc->des2 = dma_map_single(priv->device, | |
969 | skb->data + BUF_SIZE_8KiB, | |
970 | buf2_size, DMA_TO_DEVICE); | |
971 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
972 | priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size, |
973 | csum_insertion); | |
974 | priv->hw->desc->set_tx_owner(desc); | |
47dd7a54 GC |
975 | priv->tx_skbuff[entry] = NULL; |
976 | } else { | |
977 | desc->des2 = dma_map_single(priv->device, skb->data, | |
978 | nopaged_len, DMA_TO_DEVICE); | |
979 | desc->des3 = desc->des2 + BUF_SIZE_4KiB; | |
db98a0b0 GC |
980 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
981 | csum_insertion); | |
47dd7a54 GC |
982 | } |
983 | return entry; | |
984 | } | |
985 | ||
986 | /** | |
987 | * stmmac_xmit: | |
988 | * @skb : the socket buffer | |
989 | * @dev : device pointer | |
990 | * Description : Tx entry point of the driver. | |
991 | */ | |
992 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
993 | { | |
994 | struct stmmac_priv *priv = netdev_priv(dev); | |
995 | unsigned int txsize = priv->dma_tx_size; | |
996 | unsigned int entry; | |
997 | int i, csum_insertion = 0; | |
998 | int nfrags = skb_shinfo(skb)->nr_frags; | |
999 | struct dma_desc *desc, *first; | |
1000 | ||
1001 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1002 | if (!netif_queue_stopped(dev)) { | |
1003 | netif_stop_queue(dev); | |
1004 | /* This is a hard error, log it. */ | |
1005 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1006 | __func__); | |
1007 | } | |
1008 | return NETDEV_TX_BUSY; | |
1009 | } | |
1010 | ||
1011 | entry = priv->cur_tx % txsize; | |
1012 | ||
1013 | #ifdef STMMAC_XMIT_DEBUG | |
1014 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1015 | pr_info("stmmac xmit:\n" | |
1016 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1017 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
1018 | skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed, | |
1019 | !skb_is_gso(skb) ? "isn't" : "is"); | |
1020 | #endif | |
1021 | ||
5e982f3b | 1022 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1023 | |
1024 | desc = priv->dma_tx + entry; | |
1025 | first = desc; | |
1026 | ||
1027 | #ifdef STMMAC_XMIT_DEBUG | |
1028 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1029 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1030 | "\t\tn_frags: %d, ip_summed: %d\n", | |
1031 | skb->len, skb_headlen(skb), nfrags, skb->ip_summed); | |
1032 | #endif | |
1033 | priv->tx_skbuff[entry] = skb; | |
1034 | if (unlikely(skb->len >= BUF_SIZE_4KiB)) { | |
1035 | entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion); | |
1036 | desc = priv->dma_tx + entry; | |
1037 | } else { | |
1038 | unsigned int nopaged_len = skb_headlen(skb); | |
1039 | desc->des2 = dma_map_single(priv->device, skb->data, | |
1040 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1041 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1042 | csum_insertion); | |
47dd7a54 GC |
1043 | } |
1044 | ||
1045 | for (i = 0; i < nfrags; i++) { | |
1046 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1047 | int len = frag->size; | |
1048 | ||
1049 | entry = (++priv->cur_tx) % txsize; | |
1050 | desc = priv->dma_tx + entry; | |
1051 | ||
1052 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
1053 | desc->des2 = dma_map_page(priv->device, frag->page, | |
1054 | frag->page_offset, | |
1055 | len, DMA_TO_DEVICE); | |
1056 | priv->tx_skbuff[entry] = NULL; | |
db98a0b0 | 1057 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1058 | wmb(); |
db98a0b0 | 1059 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1060 | } |
1061 | ||
1062 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1063 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1064 | |
47dd7a54 | 1065 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1066 | /* Clean IC while using timer */ |
1067 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1068 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1069 | #endif |
eb0dc4bb SH |
1070 | |
1071 | wmb(); | |
1072 | ||
47dd7a54 | 1073 | /* To avoid raise condition */ |
db98a0b0 | 1074 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1075 | |
1076 | priv->cur_tx++; | |
1077 | ||
1078 | #ifdef STMMAC_XMIT_DEBUG | |
1079 | if (netif_msg_pktdata(priv)) { | |
1080 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1081 | "first=%p, nfrags=%d\n", | |
1082 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1083 | entry, first, nfrags); | |
1084 | display_ring(priv->dma_tx, txsize); | |
1085 | pr_info(">>> frame to be transmitted: "); | |
1086 | print_pkt(skb->data, skb->len); | |
1087 | } | |
1088 | #endif | |
1089 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1090 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1091 | netif_stop_queue(dev); | |
1092 | } | |
1093 | ||
1094 | dev->stats.tx_bytes += skb->len; | |
1095 | ||
3e82ce12 RC |
1096 | skb_tx_timestamp(skb); |
1097 | ||
52f64fae RC |
1098 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1099 | ||
47dd7a54 GC |
1100 | return NETDEV_TX_OK; |
1101 | } | |
1102 | ||
1103 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1104 | { | |
1105 | unsigned int rxsize = priv->dma_rx_size; | |
1106 | int bfsize = priv->dma_buf_sz; | |
1107 | struct dma_desc *p = priv->dma_rx; | |
1108 | ||
1109 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1110 | unsigned int entry = priv->dirty_rx % rxsize; | |
1111 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1112 | struct sk_buff *skb; | |
1113 | ||
1114 | skb = __skb_dequeue(&priv->rx_recycle); | |
1115 | if (skb == NULL) | |
1116 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1117 | bfsize); | |
1118 | ||
1119 | if (unlikely(skb == NULL)) | |
1120 | break; | |
1121 | ||
1122 | priv->rx_skbuff[entry] = skb; | |
1123 | priv->rx_skbuff_dma[entry] = | |
1124 | dma_map_single(priv->device, skb->data, bfsize, | |
1125 | DMA_FROM_DEVICE); | |
1126 | ||
1127 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
9dfeb4d9 | 1128 | if (unlikely(priv->plat->has_gmac)) { |
47dd7a54 GC |
1129 | if (bfsize >= BUF_SIZE_8KiB) |
1130 | (p + entry)->des3 = | |
1131 | (p + entry)->des2 + BUF_SIZE_8KiB; | |
1132 | } | |
1133 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); | |
1134 | } | |
eb0dc4bb | 1135 | wmb(); |
db98a0b0 | 1136 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1137 | } |
47dd7a54 GC |
1138 | } |
1139 | ||
1140 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1141 | { | |
1142 | unsigned int rxsize = priv->dma_rx_size; | |
1143 | unsigned int entry = priv->cur_rx % rxsize; | |
1144 | unsigned int next_entry; | |
1145 | unsigned int count = 0; | |
1146 | struct dma_desc *p = priv->dma_rx + entry; | |
1147 | struct dma_desc *p_next; | |
1148 | ||
1149 | #ifdef STMMAC_RX_DEBUG | |
1150 | if (netif_msg_hw(priv)) { | |
1151 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1152 | display_ring(priv->dma_rx, rxsize); | |
1153 | } | |
1154 | #endif | |
1155 | count = 0; | |
db98a0b0 | 1156 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1157 | int status; |
1158 | ||
1159 | if (count >= limit) | |
1160 | break; | |
1161 | ||
1162 | count++; | |
1163 | ||
1164 | next_entry = (++priv->cur_rx) % rxsize; | |
1165 | p_next = priv->dma_rx + next_entry; | |
1166 | prefetch(p_next); | |
1167 | ||
1168 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1169 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1170 | &priv->xstats, p)); | |
47dd7a54 GC |
1171 | if (unlikely(status == discard_frame)) |
1172 | priv->dev->stats.rx_errors++; | |
1173 | else { | |
1174 | struct sk_buff *skb; | |
3eeb2997 | 1175 | int frame_len; |
47dd7a54 | 1176 | |
3eeb2997 GC |
1177 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
1178 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 | |
1179 | * Type frames (LLC/LLC-SNAP) */ | |
1180 | if (unlikely(status != llc_snap)) | |
1181 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1182 | #ifdef STMMAC_RX_DEBUG |
1183 | if (frame_len > ETH_FRAME_LEN) | |
1184 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1185 | frame_len, status); | |
1186 | ||
1187 | if (netif_msg_hw(priv)) | |
1188 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1189 | p, entry, p->des2); | |
1190 | #endif | |
1191 | skb = priv->rx_skbuff[entry]; | |
1192 | if (unlikely(!skb)) { | |
1193 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1194 | priv->dev->name); | |
1195 | priv->dev->stats.rx_dropped++; | |
1196 | break; | |
1197 | } | |
1198 | prefetch(skb->data - NET_IP_ALIGN); | |
1199 | priv->rx_skbuff[entry] = NULL; | |
1200 | ||
1201 | skb_put(skb, frame_len); | |
1202 | dma_unmap_single(priv->device, | |
1203 | priv->rx_skbuff_dma[entry], | |
1204 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1205 | #ifdef STMMAC_RX_DEBUG | |
1206 | if (netif_msg_pktdata(priv)) { | |
1207 | pr_info(" frame received (%dbytes)", frame_len); | |
1208 | print_pkt(skb->data, frame_len); | |
1209 | } | |
1210 | #endif | |
1211 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1212 | ||
1213 | if (unlikely(status == csum_none)) { | |
1214 | /* always for the old mac 10/100 */ | |
bc8acf2c | 1215 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1216 | netif_receive_skb(skb); |
1217 | } else { | |
1218 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1219 | napi_gro_receive(&priv->napi, skb); | |
1220 | } | |
1221 | ||
1222 | priv->dev->stats.rx_packets++; | |
1223 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1224 | } |
1225 | entry = next_entry; | |
1226 | p = p_next; /* use prefetched values */ | |
1227 | } | |
1228 | ||
1229 | stmmac_rx_refill(priv); | |
1230 | ||
1231 | priv->xstats.rx_pkt_n += count; | |
1232 | ||
1233 | return count; | |
1234 | } | |
1235 | ||
1236 | /** | |
1237 | * stmmac_poll - stmmac poll method (NAPI) | |
1238 | * @napi : pointer to the napi structure. | |
1239 | * @budget : maximum number of packets that the current CPU can receive from | |
1240 | * all interfaces. | |
1241 | * Description : | |
1242 | * This function implements the the reception process. | |
1243 | * Also it runs the TX completion thread | |
1244 | */ | |
1245 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1246 | { | |
1247 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1248 | int work_done = 0; | |
1249 | ||
1250 | priv->xstats.poll_n++; | |
1251 | stmmac_tx(priv); | |
1252 | work_done = stmmac_rx(priv, budget); | |
1253 | ||
1254 | if (work_done < budget) { | |
1255 | napi_complete(napi); | |
1256 | stmmac_enable_irq(priv); | |
1257 | } | |
1258 | return work_done; | |
1259 | } | |
1260 | ||
1261 | /** | |
1262 | * stmmac_tx_timeout | |
1263 | * @dev : Pointer to net device structure | |
1264 | * Description: this function is called when a packet transmission fails to | |
1265 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1266 | * netdev structure and arrange for the device to be reset to a sane state | |
1267 | * in order to transmit a new packet. | |
1268 | */ | |
1269 | static void stmmac_tx_timeout(struct net_device *dev) | |
1270 | { | |
1271 | struct stmmac_priv *priv = netdev_priv(dev); | |
1272 | ||
1273 | /* Clear Tx resources and restart transmitting again */ | |
1274 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1275 | } |
1276 | ||
1277 | /* Configuration changes (passed on by ifconfig) */ | |
1278 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1279 | { | |
1280 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1281 | return -EBUSY; | |
1282 | ||
1283 | /* Don't allow changing the I/O address */ | |
1284 | if (map->base_addr != dev->base_addr) { | |
1285 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1286 | return -EOPNOTSUPP; | |
1287 | } | |
1288 | ||
1289 | /* Don't allow changing the IRQ */ | |
1290 | if (map->irq != dev->irq) { | |
1291 | pr_warning("%s: can't change IRQ number %d\n", | |
1292 | dev->name, dev->irq); | |
1293 | return -EOPNOTSUPP; | |
1294 | } | |
1295 | ||
1296 | /* ignore other fields */ | |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | /** | |
01789349 | 1301 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1302 | * @dev : pointer to the device structure |
1303 | * Description: | |
1304 | * This function is a driver entry point which gets called by the kernel | |
1305 | * whenever multicast addresses must be enabled/disabled. | |
1306 | * Return value: | |
1307 | * void. | |
1308 | */ | |
01789349 | 1309 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1310 | { |
1311 | struct stmmac_priv *priv = netdev_priv(dev); | |
1312 | ||
1313 | spin_lock(&priv->lock); | |
db98a0b0 | 1314 | priv->hw->mac->set_filter(dev); |
47dd7a54 | 1315 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1316 | } |
1317 | ||
1318 | /** | |
1319 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1320 | * @dev : device pointer. | |
1321 | * @new_mtu : the new MTU size for the device. | |
1322 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1323 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1324 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1325 | * Return value: | |
1326 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1327 | * file on failure. | |
1328 | */ | |
1329 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1330 | { | |
1331 | struct stmmac_priv *priv = netdev_priv(dev); | |
1332 | int max_mtu; | |
1333 | ||
1334 | if (netif_running(dev)) { | |
1335 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1336 | return -EBUSY; | |
1337 | } | |
1338 | ||
9dfeb4d9 | 1339 | if (priv->plat->has_gmac) |
47dd7a54 GC |
1340 | max_mtu = JUMBO_LEN; |
1341 | else | |
1342 | max_mtu = ETH_DATA_LEN; | |
1343 | ||
1344 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1345 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1346 | return -EINVAL; | |
1347 | } | |
1348 | ||
5e982f3b MM |
1349 | dev->mtu = new_mtu; |
1350 | netdev_update_features(dev); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | static u32 stmmac_fix_features(struct net_device *dev, u32 features) | |
1356 | { | |
1357 | struct stmmac_priv *priv = netdev_priv(dev); | |
1358 | ||
1359 | if (!priv->rx_coe) | |
1360 | features &= ~NETIF_F_RXCSUM; | |
1361 | if (!priv->plat->tx_coe) | |
1362 | features &= ~NETIF_F_ALL_CSUM; | |
1363 | ||
ebbb293f GC |
1364 | /* Some GMAC devices have a bugged Jumbo frame support that |
1365 | * needs to have the Tx COE disabled for oversized frames | |
1366 | * (due to limited buffer sizes). In this case we disable | |
1367 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1368 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1369 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1370 | |
5e982f3b | 1371 | return features; |
47dd7a54 GC |
1372 | } |
1373 | ||
1374 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1375 | { | |
1376 | struct net_device *dev = (struct net_device *)dev_id; | |
1377 | struct stmmac_priv *priv = netdev_priv(dev); | |
1378 | ||
1379 | if (unlikely(!dev)) { | |
1380 | pr_err("%s: invalid dev pointer\n", __func__); | |
1381 | return IRQ_NONE; | |
1382 | } | |
1383 | ||
9dfeb4d9 | 1384 | if (priv->plat->has_gmac) |
47dd7a54 | 1385 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1386 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1387 | |
1388 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1389 | |
1390 | return IRQ_HANDLED; | |
1391 | } | |
1392 | ||
1393 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1394 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1395 | * to allow network I/O with interrupts disabled. */ | |
1396 | static void stmmac_poll_controller(struct net_device *dev) | |
1397 | { | |
1398 | disable_irq(dev->irq); | |
1399 | stmmac_interrupt(dev->irq, dev); | |
1400 | enable_irq(dev->irq); | |
1401 | } | |
1402 | #endif | |
1403 | ||
1404 | /** | |
1405 | * stmmac_ioctl - Entry point for the Ioctl | |
1406 | * @dev: Device pointer. | |
1407 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1408 | * a proprietary structure used to pass information to the driver. | |
1409 | * @cmd: IOCTL command | |
1410 | * Description: | |
1411 | * Currently there are no special functionality supported in IOCTL, just the | |
1412 | * phy_mii_ioctl(...) can be invoked. | |
1413 | */ | |
1414 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1415 | { | |
1416 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1417 | int ret; |
47dd7a54 GC |
1418 | |
1419 | if (!netif_running(dev)) | |
1420 | return -EINVAL; | |
1421 | ||
28b04113 RC |
1422 | if (!priv->phydev) |
1423 | return -EINVAL; | |
1424 | ||
1425 | spin_lock(&priv->lock); | |
1426 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
1427 | spin_unlock(&priv->lock); | |
1428 | ||
47dd7a54 GC |
1429 | return ret; |
1430 | } | |
1431 | ||
7ac29055 GC |
1432 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1433 | static struct dentry *stmmac_fs_dir; | |
1434 | static struct dentry *stmmac_rings_status; | |
1435 | ||
1436 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1437 | { | |
1438 | struct tmp_s { | |
1439 | u64 a; | |
1440 | unsigned int b; | |
1441 | unsigned int c; | |
1442 | }; | |
1443 | int i; | |
1444 | struct net_device *dev = seq->private; | |
1445 | struct stmmac_priv *priv = netdev_priv(dev); | |
1446 | ||
1447 | seq_printf(seq, "=======================\n"); | |
1448 | seq_printf(seq, " RX descriptor ring\n"); | |
1449 | seq_printf(seq, "=======================\n"); | |
1450 | ||
1451 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1452 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1453 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1454 | i, (unsigned int)(x->a), | |
1455 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1456 | seq_printf(seq, "\n"); | |
1457 | } | |
1458 | ||
1459 | seq_printf(seq, "\n"); | |
1460 | seq_printf(seq, "=======================\n"); | |
1461 | seq_printf(seq, " TX descriptor ring\n"); | |
1462 | seq_printf(seq, "=======================\n"); | |
1463 | ||
1464 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1465 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1466 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1467 | i, (unsigned int)(x->a), | |
1468 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1469 | seq_printf(seq, "\n"); | |
1470 | } | |
1471 | ||
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1476 | { | |
1477 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1478 | } | |
1479 | ||
1480 | static const struct file_operations stmmac_rings_status_fops = { | |
1481 | .owner = THIS_MODULE, | |
1482 | .open = stmmac_sysfs_ring_open, | |
1483 | .read = seq_read, | |
1484 | .llseek = seq_lseek, | |
1485 | .release = seq_release, | |
1486 | }; | |
1487 | ||
1488 | static int stmmac_init_fs(struct net_device *dev) | |
1489 | { | |
1490 | /* Create debugfs entries */ | |
1491 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1492 | ||
1493 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1494 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1495 | STMMAC_RESOURCE_NAME); | |
1496 | ||
1497 | return -ENOMEM; | |
1498 | } | |
1499 | ||
1500 | /* Entry to report DMA RX/TX rings */ | |
1501 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1502 | S_IRUGO, stmmac_fs_dir, dev, | |
1503 | &stmmac_rings_status_fops); | |
1504 | ||
1505 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1506 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1507 | debugfs_remove(stmmac_fs_dir); | |
1508 | ||
1509 | return -ENOMEM; | |
1510 | } | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | static void stmmac_exit_fs(void) | |
1516 | { | |
1517 | debugfs_remove(stmmac_rings_status); | |
1518 | debugfs_remove(stmmac_fs_dir); | |
1519 | } | |
1520 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1521 | ||
47dd7a54 GC |
1522 | static const struct net_device_ops stmmac_netdev_ops = { |
1523 | .ndo_open = stmmac_open, | |
1524 | .ndo_start_xmit = stmmac_xmit, | |
1525 | .ndo_stop = stmmac_release, | |
1526 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1527 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1528 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1529 | .ndo_tx_timeout = stmmac_tx_timeout, |
1530 | .ndo_do_ioctl = stmmac_ioctl, | |
1531 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1532 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1533 | .ndo_poll_controller = stmmac_poll_controller, | |
1534 | #endif | |
1535 | .ndo_set_mac_address = eth_mac_addr, | |
1536 | }; | |
1537 | ||
1538 | /** | |
1539 | * stmmac_probe - Initialization of the adapter . | |
1540 | * @dev : device pointer | |
1541 | * Description: The function initializes the network device structure for | |
1542 | * the STMMAC driver. It also calls the low level routines | |
1543 | * in order to init the HW (i.e. the DMA engine) | |
1544 | */ | |
1545 | static int stmmac_probe(struct net_device *dev) | |
1546 | { | |
1547 | int ret = 0; | |
1548 | struct stmmac_priv *priv = netdev_priv(dev); | |
1549 | ||
1550 | ether_setup(dev); | |
1551 | ||
1552 | dev->netdev_ops = &stmmac_netdev_ops; | |
1553 | stmmac_set_ethtool_ops(dev); | |
1554 | ||
5e982f3b MM |
1555 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
1556 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; | |
47dd7a54 GC |
1557 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
1558 | #ifdef STMMAC_VLAN_TAG_USED | |
1559 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
1560 | dev->features |= NETIF_F_HW_VLAN_RX; | |
1561 | #endif | |
1562 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1563 | ||
47dd7a54 GC |
1564 | if (flow_ctrl) |
1565 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1566 | ||
1567 | priv->pause = pause; | |
1568 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); | |
1569 | ||
1570 | /* Get the MAC address */ | |
ad01b7d4 GC |
1571 | priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr, |
1572 | dev->dev_addr, 0); | |
47dd7a54 GC |
1573 | |
1574 | if (!is_valid_ether_addr(dev->dev_addr)) | |
1575 | pr_warning("\tno valid MAC address;" | |
1576 | "please, use ifconfig or nwhwconfig!\n"); | |
1577 | ||
f8e96161 VL |
1578 | spin_lock_init(&priv->lock); |
1579 | ||
47dd7a54 GC |
1580 | ret = register_netdev(dev); |
1581 | if (ret) { | |
1582 | pr_err("%s: ERROR %i registering the device\n", | |
1583 | __func__, ret); | |
1584 | return -ENODEV; | |
1585 | } | |
1586 | ||
1587 | DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", | |
1588 | dev->name, (dev->features & NETIF_F_SG) ? "on" : "off", | |
79032644 | 1589 | (dev->features & NETIF_F_IP_CSUM) ? "on" : "off"); |
47dd7a54 | 1590 | |
47dd7a54 GC |
1591 | return ret; |
1592 | } | |
1593 | ||
1594 | /** | |
1595 | * stmmac_mac_device_setup | |
1596 | * @dev : device pointer | |
1597 | * Description: select and initialise the mac device (mac100 or Gmac). | |
1598 | */ | |
1599 | static int stmmac_mac_device_setup(struct net_device *dev) | |
1600 | { | |
1601 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1602 | |
1603 | struct mac_device_info *device; | |
1604 | ||
01789349 JP |
1605 | if (priv->plat->has_gmac) { |
1606 | dev->priv_flags |= IFF_UNICAST_FLT; | |
ad01b7d4 | 1607 | device = dwmac1000_setup(priv->ioaddr); |
01789349 | 1608 | } else { |
ad01b7d4 | 1609 | device = dwmac100_setup(priv->ioaddr); |
01789349 | 1610 | } |
3d90c508 | 1611 | |
1ff21906 DC |
1612 | if (!device) |
1613 | return -ENOMEM; | |
1614 | ||
9dfeb4d9 | 1615 | if (priv->plat->enh_desc) { |
3d90c508 GC |
1616 | device->desc = &enh_desc_ops; |
1617 | pr_info("\tEnhanced descriptor structure\n"); | |
1618 | } else | |
56b106ae | 1619 | device->desc = &ndesc_ops; |
47dd7a54 | 1620 | |
db98a0b0 | 1621 | priv->hw = device; |
47dd7a54 | 1622 | |
539c9aa5 | 1623 | if (device_can_wakeup(priv->device)) { |
543876c9 | 1624 | priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ |
3172d3af | 1625 | enable_irq_wake(priv->wol_irq); |
539c9aa5 | 1626 | } |
47dd7a54 GC |
1627 | |
1628 | return 0; | |
1629 | } | |
1630 | ||
47dd7a54 GC |
1631 | /** |
1632 | * stmmac_dvr_probe | |
1633 | * @pdev: platform device pointer | |
1634 | * Description: the driver is initialized through platform_device. | |
1635 | */ | |
1636 | static int stmmac_dvr_probe(struct platform_device *pdev) | |
1637 | { | |
1638 | int ret = 0; | |
1639 | struct resource *res; | |
ad01b7d4 | 1640 | void __iomem *addr = NULL; |
47dd7a54 | 1641 | struct net_device *ndev = NULL; |
293bb1c4 | 1642 | struct stmmac_priv *priv = NULL; |
47dd7a54 GC |
1643 | struct plat_stmmacenet_data *plat_dat; |
1644 | ||
1645 | pr_info("STMMAC driver:\n\tplatform registration... "); | |
1646 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
34a52f36 DC |
1647 | if (!res) |
1648 | return -ENODEV; | |
ebbb293f | 1649 | pr_info("\tdone!\n"); |
47dd7a54 | 1650 | |
b6222682 | 1651 | if (!request_mem_region(res->start, resource_size(res), |
47dd7a54 GC |
1652 | pdev->name)) { |
1653 | pr_err("%s: ERROR: memory allocation failed" | |
1654 | "cannot get the I/O addr 0x%x\n", | |
1655 | __func__, (unsigned int)res->start); | |
34a52f36 | 1656 | return -EBUSY; |
47dd7a54 GC |
1657 | } |
1658 | ||
7c5365bc | 1659 | addr = ioremap(res->start, resource_size(res)); |
47dd7a54 | 1660 | if (!addr) { |
7c5365bc | 1661 | pr_err("%s: ERROR: memory mapping failed\n", __func__); |
47dd7a54 | 1662 | ret = -ENOMEM; |
34a52f36 | 1663 | goto out_release_region; |
47dd7a54 GC |
1664 | } |
1665 | ||
1666 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); | |
1667 | if (!ndev) { | |
1668 | pr_err("%s: ERROR: allocating the device\n", __func__); | |
1669 | ret = -ENOMEM; | |
34a52f36 | 1670 | goto out_unmap; |
47dd7a54 GC |
1671 | } |
1672 | ||
1673 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1674 | ||
1675 | /* Get the MAC information */ | |
1676 | ndev->irq = platform_get_irq_byname(pdev, "macirq"); | |
1677 | if (ndev->irq == -ENXIO) { | |
1678 | pr_err("%s: ERROR: MAC IRQ configuration " | |
1679 | "information not found\n", __func__); | |
34a52f36 DC |
1680 | ret = -ENXIO; |
1681 | goto out_free_ndev; | |
47dd7a54 GC |
1682 | } |
1683 | ||
1684 | priv = netdev_priv(ndev); | |
1685 | priv->device = &(pdev->dev); | |
1686 | priv->dev = ndev; | |
ee7946a7 | 1687 | plat_dat = pdev->dev.platform_data; |
9dfeb4d9 GC |
1688 | |
1689 | priv->plat = plat_dat; | |
1690 | ||
ad01b7d4 | 1691 | priv->ioaddr = addr; |
47dd7a54 | 1692 | |
543876c9 GC |
1693 | /* PMT module is not integrated in all the MAC devices. */ |
1694 | if (plat_dat->pmt) { | |
1695 | pr_info("\tPMT module supported\n"); | |
1696 | device_set_wakeup_capable(&pdev->dev, 1); | |
1697 | } | |
3172d3af DS |
1698 | /* |
1699 | * On some platforms e.g. SPEAr the wake up irq differs from the mac irq | |
1700 | * The external wake up irq can be passed through the platform code | |
1701 | * named as "eth_wake_irq" | |
1702 | * | |
1703 | * In case the wake up interrupt is not passed from the platform | |
1704 | * so the driver will continue to use the mac irq (ndev->irq) | |
1705 | */ | |
1706 | priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq"); | |
1707 | if (priv->wol_irq == -ENXIO) | |
1708 | priv->wol_irq = ndev->irq; | |
1709 | ||
543876c9 | 1710 | |
47dd7a54 GC |
1711 | platform_set_drvdata(pdev, ndev); |
1712 | ||
1713 | /* Set the I/O base addr */ | |
1714 | ndev->base_addr = (unsigned long)addr; | |
1715 | ||
293bb1c4 GC |
1716 | /* Custom initialisation */ |
1717 | if (priv->plat->init) { | |
1718 | ret = priv->plat->init(pdev); | |
1719 | if (unlikely(ret)) | |
34a52f36 | 1720 | goto out_free_ndev; |
293bb1c4 | 1721 | } |
ee7946a7 | 1722 | |
47dd7a54 GC |
1723 | /* MAC HW revice detection */ |
1724 | ret = stmmac_mac_device_setup(ndev); | |
1725 | if (ret < 0) | |
34a52f36 | 1726 | goto out_plat_exit; |
47dd7a54 GC |
1727 | |
1728 | /* Network Device Registration */ | |
1729 | ret = stmmac_probe(ndev); | |
1730 | if (ret < 0) | |
34a52f36 | 1731 | goto out_plat_exit; |
47dd7a54 | 1732 | |
36bcfe7d GC |
1733 | /* Override with kernel parameters if supplied XXX CRS XXX |
1734 | * this needs to have multiple instances */ | |
1735 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1736 | priv->plat->phy_addr = phyaddr; | |
47dd7a54 | 1737 | |
47dd7a54 | 1738 | pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" |
1f0f6388 DM |
1739 | "\tIO base addr: 0x%p)\n", ndev->name, pdev->name, |
1740 | pdev->id, ndev->irq, addr); | |
47dd7a54 GC |
1741 | |
1742 | /* MDIO bus Registration */ | |
9dfeb4d9 | 1743 | pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id); |
47dd7a54 GC |
1744 | ret = stmmac_mdio_register(ndev); |
1745 | if (ret < 0) | |
34a52f36 | 1746 | goto out_unregister; |
47dd7a54 | 1747 | pr_debug("registered!\n"); |
7ac29055 GC |
1748 | |
1749 | #ifdef CONFIG_STMMAC_DEBUG_FS | |
1750 | ret = stmmac_init_fs(ndev); | |
1751 | if (ret < 0) | |
1752 | pr_warning("\tFailed debugFS registration"); | |
1753 | #endif | |
1754 | ||
34a52f36 | 1755 | return 0; |
47dd7a54 | 1756 | |
34a52f36 DC |
1757 | out_unregister: |
1758 | unregister_netdev(ndev); | |
1759 | out_plat_exit: | |
1760 | if (priv->plat->exit) | |
1761 | priv->plat->exit(pdev); | |
1762 | out_free_ndev: | |
1763 | free_netdev(ndev); | |
1764 | platform_set_drvdata(pdev, NULL); | |
1765 | out_unmap: | |
1766 | iounmap(addr); | |
1767 | out_release_region: | |
1768 | release_mem_region(res->start, resource_size(res)); | |
47dd7a54 GC |
1769 | |
1770 | return ret; | |
1771 | } | |
1772 | ||
1773 | /** | |
1774 | * stmmac_dvr_remove | |
1775 | * @pdev: platform device pointer | |
1776 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX | |
1777 | * changes the link status, releases the DMA descriptor rings, | |
1778 | * unregisters the MDIO bus and unmaps the allocated memory. | |
1779 | */ | |
1780 | static int stmmac_dvr_remove(struct platform_device *pdev) | |
1781 | { | |
1782 | struct net_device *ndev = platform_get_drvdata(pdev); | |
aec7ff27 | 1783 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1784 | struct resource *res; |
1785 | ||
1786 | pr_info("%s:\n\tremoving driver", __func__); | |
1787 | ||
ad01b7d4 GC |
1788 | priv->hw->dma->stop_rx(priv->ioaddr); |
1789 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1790 | |
19449bfc | 1791 | stmmac_disable_mac(priv->ioaddr); |
47dd7a54 GC |
1792 | |
1793 | netif_carrier_off(ndev); | |
1794 | ||
1795 | stmmac_mdio_unregister(ndev); | |
1796 | ||
293bb1c4 GC |
1797 | if (priv->plat->exit) |
1798 | priv->plat->exit(pdev); | |
1799 | ||
47dd7a54 GC |
1800 | platform_set_drvdata(pdev, NULL); |
1801 | unregister_netdev(ndev); | |
1802 | ||
ad01b7d4 | 1803 | iounmap((void *)priv->ioaddr); |
47dd7a54 | 1804 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7c5365bc | 1805 | release_mem_region(res->start, resource_size(res)); |
47dd7a54 | 1806 | |
7ac29055 GC |
1807 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1808 | stmmac_exit_fs(); | |
1809 | #endif | |
1810 | ||
47dd7a54 GC |
1811 | free_netdev(ndev); |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | #ifdef CONFIG_PM | |
874bd42d | 1817 | static int stmmac_suspend(struct device *dev) |
47dd7a54 | 1818 | { |
874bd42d GC |
1819 | struct net_device *ndev = dev_get_drvdata(dev); |
1820 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 GC |
1821 | int dis_ic = 0; |
1822 | ||
874bd42d | 1823 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1824 | return 0; |
1825 | ||
1826 | spin_lock(&priv->lock); | |
1827 | ||
874bd42d GC |
1828 | netif_device_detach(ndev); |
1829 | netif_stop_queue(ndev); | |
1830 | if (priv->phydev) | |
1831 | phy_stop(priv->phydev); | |
47dd7a54 GC |
1832 | |
1833 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1834 | priv->tm->timer_stop(); |
1835 | if (likely(priv->tm->enable)) | |
1836 | dis_ic = 1; | |
47dd7a54 | 1837 | #endif |
874bd42d GC |
1838 | napi_disable(&priv->napi); |
1839 | ||
1840 | /* Stop TX/RX DMA */ | |
1841 | priv->hw->dma->stop_tx(priv->ioaddr); | |
1842 | priv->hw->dma->stop_rx(priv->ioaddr); | |
1843 | /* Clear the Rx/Tx descriptors */ | |
1844 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
1845 | dis_ic); | |
1846 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
1847 | ||
1848 | /* Enable Power down mode by programming the PMT regs */ | |
1849 | if (device_may_wakeup(priv->device)) | |
1850 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
1851 | else | |
1852 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
1853 | |
1854 | spin_unlock(&priv->lock); | |
1855 | return 0; | |
1856 | } | |
1857 | ||
874bd42d | 1858 | static int stmmac_resume(struct device *dev) |
47dd7a54 | 1859 | { |
874bd42d GC |
1860 | struct net_device *ndev = dev_get_drvdata(dev); |
1861 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 | 1862 | |
874bd42d | 1863 | if (!netif_running(ndev)) |
47dd7a54 GC |
1864 | return 0; |
1865 | ||
c4433be6 GC |
1866 | spin_lock(&priv->lock); |
1867 | ||
47dd7a54 GC |
1868 | /* Power Down bit, into the PM register, is cleared |
1869 | * automatically as soon as a magic packet or a Wake-up frame | |
1870 | * is received. Anyway, it's better to manually clear | |
1871 | * this bit because it can generate problems while resuming | |
1872 | * from another devices (e.g. serial console). */ | |
874bd42d | 1873 | if (device_may_wakeup(priv->device)) |
543876c9 | 1874 | priv->hw->mac->pmt(priv->ioaddr, 0); |
47dd7a54 | 1875 | |
874bd42d | 1876 | netif_device_attach(ndev); |
47dd7a54 GC |
1877 | |
1878 | /* Enable the MAC and DMA */ | |
19449bfc | 1879 | stmmac_enable_mac(priv->ioaddr); |
ad01b7d4 GC |
1880 | priv->hw->dma->start_tx(priv->ioaddr); |
1881 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1882 | |
1883 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1884 | if (likely(priv->tm->enable)) |
1885 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
1886 | #endif |
1887 | napi_enable(&priv->napi); | |
1888 | ||
1889 | if (priv->phydev) | |
1890 | phy_start(priv->phydev); | |
1891 | ||
874bd42d | 1892 | netif_start_queue(ndev); |
47dd7a54 | 1893 | |
47dd7a54 GC |
1894 | spin_unlock(&priv->lock); |
1895 | return 0; | |
1896 | } | |
47dd7a54 | 1897 | |
874bd42d GC |
1898 | static int stmmac_freeze(struct device *dev) |
1899 | { | |
1900 | struct net_device *ndev = dev_get_drvdata(dev); | |
1901 | ||
1902 | if (!ndev || !netif_running(ndev)) | |
1903 | return 0; | |
1904 | ||
1905 | return stmmac_release(ndev); | |
1906 | } | |
1907 | ||
1908 | static int stmmac_restore(struct device *dev) | |
1909 | { | |
1910 | struct net_device *ndev = dev_get_drvdata(dev); | |
1911 | ||
1912 | if (!ndev || !netif_running(ndev)) | |
1913 | return 0; | |
1914 | ||
1915 | return stmmac_open(ndev); | |
1916 | } | |
1917 | ||
1918 | static const struct dev_pm_ops stmmac_pm_ops = { | |
47dd7a54 GC |
1919 | .suspend = stmmac_suspend, |
1920 | .resume = stmmac_resume, | |
874bd42d GC |
1921 | .freeze = stmmac_freeze, |
1922 | .thaw = stmmac_restore, | |
1923 | .restore = stmmac_restore, | |
1924 | }; | |
1925 | #else | |
1926 | static const struct dev_pm_ops stmmac_pm_ops; | |
1927 | #endif /* CONFIG_PM */ | |
47dd7a54 | 1928 | |
874bd42d GC |
1929 | static struct platform_driver stmmac_driver = { |
1930 | .probe = stmmac_dvr_probe, | |
1931 | .remove = stmmac_dvr_remove, | |
1932 | .driver = { | |
1933 | .name = STMMAC_RESOURCE_NAME, | |
1934 | .owner = THIS_MODULE, | |
1935 | .pm = &stmmac_pm_ops, | |
1936 | }, | |
47dd7a54 GC |
1937 | }; |
1938 | ||
1939 | /** | |
1940 | * stmmac_init_module - Entry point for the driver | |
1941 | * Description: This function is the entry point for the driver. | |
1942 | */ | |
1943 | static int __init stmmac_init_module(void) | |
1944 | { | |
1945 | int ret; | |
1946 | ||
47dd7a54 GC |
1947 | ret = platform_driver_register(&stmmac_driver); |
1948 | return ret; | |
1949 | } | |
1950 | ||
1951 | /** | |
1952 | * stmmac_cleanup_module - Cleanup routine for the driver | |
1953 | * Description: This function is the cleanup routine for the driver. | |
1954 | */ | |
1955 | static void __exit stmmac_cleanup_module(void) | |
1956 | { | |
47dd7a54 GC |
1957 | platform_driver_unregister(&stmmac_driver); |
1958 | } | |
1959 | ||
1960 | #ifndef MODULE | |
1961 | static int __init stmmac_cmdline_opt(char *str) | |
1962 | { | |
1963 | char *opt; | |
1964 | ||
1965 | if (!str || !*str) | |
1966 | return -EINVAL; | |
1967 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
1968 | if (!strncmp(opt, "debug:", 6)) { |
1969 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
1970 | goto err; | |
1971 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
1972 | if (strict_strtoul(opt + 8, 0, | |
1973 | (unsigned long *)&phyaddr)) | |
1974 | goto err; | |
1975 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
1976 | if (strict_strtoul(opt + 11, 0, | |
1977 | (unsigned long *)&dma_txsize)) | |
1978 | goto err; | |
1979 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
1980 | if (strict_strtoul(opt + 11, 0, | |
1981 | (unsigned long *)&dma_rxsize)) | |
1982 | goto err; | |
1983 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
1984 | if (strict_strtoul(opt + 7, 0, | |
1985 | (unsigned long *)&buf_sz)) | |
1986 | goto err; | |
1987 | } else if (!strncmp(opt, "tc:", 3)) { | |
1988 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
1989 | goto err; | |
1990 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
1991 | if (strict_strtoul(opt + 9, 0, | |
1992 | (unsigned long *)&watchdog)) | |
1993 | goto err; | |
1994 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
1995 | if (strict_strtoul(opt + 10, 0, | |
1996 | (unsigned long *)&flow_ctrl)) | |
1997 | goto err; | |
1998 | } else if (!strncmp(opt, "pause:", 6)) { | |
1999 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2000 | goto err; | |
47dd7a54 | 2001 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2002 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2003 | if (strict_strtoul(opt + 7, 0, | |
2004 | (unsigned long *)&tmrate)) | |
2005 | goto err; | |
47dd7a54 | 2006 | #endif |
f3240e28 | 2007 | } |
47dd7a54 GC |
2008 | } |
2009 | return 0; | |
f3240e28 GC |
2010 | |
2011 | err: | |
2012 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2013 | return -EINVAL; | |
47dd7a54 GC |
2014 | } |
2015 | ||
2016 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2017 | #endif | |
2018 | ||
2019 | module_init(stmmac_init_module); | |
2020 | module_exit(stmmac_cleanup_module); | |
2021 | ||
2022 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver"); | |
2023 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2024 | MODULE_LICENSE("GPL"); |