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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
50fb4f74 | 47 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
48 | #include <linux/debugfs.h> |
49 | #include <linux/seq_file.h> | |
50fb4f74 | 50 | #endif /* CONFIG_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
5790cf3c | 55 | #include <linux/of_mdio.h> |
19d857c9 | 56 | #include "dwmac1000.h" |
47dd7a54 | 57 | |
47dd7a54 | 58 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
f748be53 | 59 | #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) |
47dd7a54 GC |
60 | |
61 | /* Module parameters */ | |
32ceabca | 62 | #define TX_TIMEO 5000 |
47dd7a54 GC |
63 | static int watchdog = TX_TIMEO; |
64 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 65 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 66 | |
32ceabca | 67 | static int debug = -1; |
47dd7a54 | 68 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 69 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 70 | |
47d1f71f | 71 | static int phyaddr = -1; |
47dd7a54 GC |
72 | module_param(phyaddr, int, S_IRUGO); |
73 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
74 | ||
e3ad57c9 | 75 | #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) |
120e87f9 | 76 | #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) |
47dd7a54 GC |
77 | |
78 | static int flow_ctrl = FLOW_OFF; | |
79 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
80 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
81 | ||
82 | static int pause = PAUSE_TIME; | |
83 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
85 | ||
86 | #define TC_DEFAULT 64 | |
87 | static int tc = TC_DEFAULT; | |
88 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
89 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
90 | ||
d916701c GC |
91 | #define DEFAULT_BUFSIZE 1536 |
92 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
93 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
94 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
95 | ||
22ad3838 GC |
96 | #define STMMAC_RX_COPYBREAK 256 |
97 | ||
47dd7a54 GC |
98 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
99 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
100 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
101 | ||
d765955d GC |
102 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
103 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
104 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
105 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 106 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 107 | |
22d3efe5 PM |
108 | /* By default the driver will use the ring mode to manage tx and rx descriptors, |
109 | * but allow user to force to use the chain instead of the ring | |
4a7d666a GC |
110 | */ |
111 | static unsigned int chain_mode; | |
112 | module_param(chain_mode, int, S_IRUGO); | |
113 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
114 | ||
47dd7a54 | 115 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 116 | |
50fb4f74 | 117 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 | 118 | static int stmmac_init_fs(struct net_device *dev); |
466c5ac8 | 119 | static void stmmac_exit_fs(struct net_device *dev); |
bfab27a1 GC |
120 | #endif |
121 | ||
9125cdd1 GC |
122 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
123 | ||
47dd7a54 GC |
124 | /** |
125 | * stmmac_verify_args - verify the driver parameters. | |
732fdf0e GC |
126 | * Description: it checks the driver parameters and set a default in case of |
127 | * errors. | |
47dd7a54 GC |
128 | */ |
129 | static void stmmac_verify_args(void) | |
130 | { | |
131 | if (unlikely(watchdog < 0)) | |
132 | watchdog = TX_TIMEO; | |
d916701c GC |
133 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
134 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
135 | if (unlikely(flow_ctrl > 1)) |
136 | flow_ctrl = FLOW_AUTO; | |
137 | else if (likely(flow_ctrl < 0)) | |
138 | flow_ctrl = FLOW_OFF; | |
139 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
140 | pause = PAUSE_TIME; | |
d765955d GC |
141 | if (eee_timer < 0) |
142 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
143 | } |
144 | ||
32ceabca GC |
145 | /** |
146 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
147 | * @priv: driver private structure | |
148 | * Description: this is to dynamically set the MDC clock according to the csr | |
149 | * clock input. | |
150 | * Note: | |
151 | * If a specific clk_csr value is passed from the platform | |
152 | * this means that the CSR Clock Range selection cannot be | |
153 | * changed at run-time and it is fixed (as reported in the driver | |
154 | * documentation). Viceversa the driver will try to set the MDC | |
155 | * clock dynamically according to the actual clock input. | |
156 | */ | |
cd7201f4 GC |
157 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
158 | { | |
cd7201f4 GC |
159 | u32 clk_rate; |
160 | ||
161 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
162 | ||
163 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
164 | * for all other cases except for the below mentioned ones. |
165 | * For values higher than the IEEE 802.3 specified frequency | |
166 | * we can not estimate the proper divider as it is not known | |
167 | * the frequency of clk_csr_i. So we do not change the default | |
168 | * divider. | |
169 | */ | |
cd7201f4 GC |
170 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
171 | if (clk_rate < CSR_F_35M) | |
172 | priv->clk_csr = STMMAC_CSR_20_35M; | |
173 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
174 | priv->clk_csr = STMMAC_CSR_35_60M; | |
175 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
176 | priv->clk_csr = STMMAC_CSR_60_100M; | |
177 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
178 | priv->clk_csr = STMMAC_CSR_100_150M; | |
179 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
180 | priv->clk_csr = STMMAC_CSR_150_250M; | |
19d857c9 | 181 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
cd7201f4 | 182 | priv->clk_csr = STMMAC_CSR_250_300M; |
ceb69499 | 183 | } |
cd7201f4 GC |
184 | } |
185 | ||
47dd7a54 GC |
186 | static void print_pkt(unsigned char *buf, int len) |
187 | { | |
424c4f78 AS |
188 | pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
189 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); | |
47dd7a54 | 190 | } |
47dd7a54 | 191 | |
47dd7a54 GC |
192 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) |
193 | { | |
e3ad57c9 GC |
194 | unsigned avail; |
195 | ||
196 | if (priv->dirty_tx > priv->cur_tx) | |
197 | avail = priv->dirty_tx - priv->cur_tx - 1; | |
198 | else | |
199 | avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; | |
200 | ||
201 | return avail; | |
202 | } | |
203 | ||
204 | static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) | |
205 | { | |
206 | unsigned dirty; | |
207 | ||
208 | if (priv->dirty_rx <= priv->cur_rx) | |
209 | dirty = priv->cur_rx - priv->dirty_rx; | |
210 | else | |
211 | dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; | |
212 | ||
213 | return dirty; | |
47dd7a54 GC |
214 | } |
215 | ||
32ceabca | 216 | /** |
732fdf0e | 217 | * stmmac_hw_fix_mac_speed - callback for speed selection |
32ceabca GC |
218 | * @priv: driver private structure |
219 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
220 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
221 | */ |
222 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
223 | { | |
d6d50c7e PR |
224 | struct net_device *ndev = priv->dev; |
225 | struct phy_device *phydev = ndev->phydev; | |
9dfeb4d9 GC |
226 | |
227 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 228 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
229 | } |
230 | ||
32ceabca | 231 | /** |
732fdf0e | 232 | * stmmac_enable_eee_mode - check and enter in LPI mode |
32ceabca | 233 | * @priv: driver private structure |
732fdf0e GC |
234 | * Description: this function is to verify and enter in LPI mode in case of |
235 | * EEE. | |
32ceabca | 236 | */ |
d765955d GC |
237 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
238 | { | |
239 | /* Check and enter in LPI mode */ | |
240 | if ((priv->dirty_tx == priv->cur_tx) && | |
241 | (priv->tx_path_in_lpi_mode == false)) | |
b4b7b772 | 242 | priv->hw->mac->set_eee_mode(priv->hw, |
243 | priv->plat->en_tx_lpi_clockgating); | |
d765955d GC |
244 | } |
245 | ||
32ceabca | 246 | /** |
732fdf0e | 247 | * stmmac_disable_eee_mode - disable and exit from LPI mode |
32ceabca GC |
248 | * @priv: driver private structure |
249 | * Description: this function is to exit and disable EEE in case of | |
250 | * LPI state is true. This is called by the xmit. | |
251 | */ | |
d765955d GC |
252 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
253 | { | |
7ed24bbe | 254 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
255 | del_timer_sync(&priv->eee_ctrl_timer); |
256 | priv->tx_path_in_lpi_mode = false; | |
257 | } | |
258 | ||
259 | /** | |
732fdf0e | 260 | * stmmac_eee_ctrl_timer - EEE TX SW timer. |
d765955d GC |
261 | * @arg : data hook |
262 | * Description: | |
32ceabca | 263 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
264 | * then MAC Transmitter can be moved to LPI state. |
265 | */ | |
266 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
267 | { | |
268 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
269 | ||
270 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 271 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
272 | } |
273 | ||
274 | /** | |
732fdf0e | 275 | * stmmac_eee_init - init EEE |
32ceabca | 276 | * @priv: driver private structure |
d765955d | 277 | * Description: |
732fdf0e GC |
278 | * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
279 | * can also manage EEE, this function enable the LPI state and start related | |
280 | * timer. | |
d765955d GC |
281 | */ |
282 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
283 | { | |
d6d50c7e | 284 | struct net_device *ndev = priv->dev; |
4741cf9c | 285 | unsigned long flags; |
d765955d GC |
286 | bool ret = false; |
287 | ||
f5351ef7 GC |
288 | /* Using PCS we cannot dial with the phy registers at this stage |
289 | * so we do not support extra feature like EEE. | |
290 | */ | |
3fe5cadb GC |
291 | if ((priv->hw->pcs == STMMAC_PCS_RGMII) || |
292 | (priv->hw->pcs == STMMAC_PCS_TBI) || | |
293 | (priv->hw->pcs == STMMAC_PCS_RTBI)) | |
f5351ef7 GC |
294 | goto out; |
295 | ||
d765955d GC |
296 | /* MAC core supports the EEE feature. */ |
297 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
298 | int tx_lpi_timer = priv->tx_lpi_timer; |
299 | ||
d765955d | 300 | /* Check if the PHY supports EEE */ |
d6d50c7e | 301 | if (phy_init_eee(ndev->phydev, 1)) { |
83bf79b6 GC |
302 | /* To manage at run-time if the EEE cannot be supported |
303 | * anymore (for example because the lp caps have been | |
304 | * changed). | |
305 | * In that case the driver disable own timers. | |
306 | */ | |
4741cf9c | 307 | spin_lock_irqsave(&priv->lock, flags); |
83bf79b6 | 308 | if (priv->eee_active) { |
38ddc59d | 309 | netdev_dbg(priv->dev, "disable EEE\n"); |
83bf79b6 | 310 | del_timer_sync(&priv->eee_ctrl_timer); |
7ed24bbe | 311 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
312 | tx_lpi_timer); |
313 | } | |
314 | priv->eee_active = 0; | |
4741cf9c | 315 | spin_unlock_irqrestore(&priv->lock, flags); |
d765955d | 316 | goto out; |
83bf79b6 GC |
317 | } |
318 | /* Activate the EEE and start timers */ | |
4741cf9c | 319 | spin_lock_irqsave(&priv->lock, flags); |
f5351ef7 GC |
320 | if (!priv->eee_active) { |
321 | priv->eee_active = 1; | |
ccb36da1 VT |
322 | setup_timer(&priv->eee_ctrl_timer, |
323 | stmmac_eee_ctrl_timer, | |
324 | (unsigned long)priv); | |
325 | mod_timer(&priv->eee_ctrl_timer, | |
326 | STMMAC_LPI_T(eee_timer)); | |
f5351ef7 | 327 | |
7ed24bbe | 328 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 329 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 330 | tx_lpi_timer); |
71965352 GC |
331 | } |
332 | /* Set HW EEE according to the speed */ | |
d6d50c7e | 333 | priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); |
d765955d | 334 | |
d765955d | 335 | ret = true; |
4741cf9c GC |
336 | spin_unlock_irqrestore(&priv->lock, flags); |
337 | ||
38ddc59d | 338 | netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); |
d765955d GC |
339 | } |
340 | out: | |
341 | return ret; | |
342 | } | |
343 | ||
732fdf0e | 344 | /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
32ceabca | 345 | * @priv: driver private structure |
ba1ffd74 | 346 | * @p : descriptor pointer |
891434b1 RK |
347 | * @skb : the socket buffer |
348 | * Description : | |
349 | * This function will read timestamp from the descriptor & pass it to stack. | |
350 | * and also perform some sanity checks. | |
351 | */ | |
352 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ba1ffd74 | 353 | struct dma_desc *p, struct sk_buff *skb) |
891434b1 RK |
354 | { |
355 | struct skb_shared_hwtstamps shhwtstamp; | |
356 | u64 ns; | |
891434b1 RK |
357 | |
358 | if (!priv->hwts_tx_en) | |
359 | return; | |
360 | ||
ceb69499 | 361 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 362 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
363 | return; |
364 | ||
891434b1 | 365 | /* check tx tstamp status */ |
ba1ffd74 GC |
366 | if (!priv->hw->desc->get_tx_timestamp_status(p)) { |
367 | /* get the valid tstamp */ | |
368 | ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); | |
891434b1 | 369 | |
ba1ffd74 GC |
370 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
371 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
891434b1 | 372 | |
ba1ffd74 GC |
373 | netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); |
374 | /* pass tstamp to stack */ | |
375 | skb_tstamp_tx(skb, &shhwtstamp); | |
376 | } | |
891434b1 RK |
377 | |
378 | return; | |
379 | } | |
380 | ||
732fdf0e | 381 | /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
32ceabca | 382 | * @priv: driver private structure |
ba1ffd74 GC |
383 | * @p : descriptor pointer |
384 | * @np : next descriptor pointer | |
891434b1 RK |
385 | * @skb : the socket buffer |
386 | * Description : | |
387 | * This function will read received packet's timestamp from the descriptor | |
388 | * and pass it to stack. It also perform some sanity checks. | |
389 | */ | |
ba1ffd74 GC |
390 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, |
391 | struct dma_desc *np, struct sk_buff *skb) | |
891434b1 RK |
392 | { |
393 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
394 | u64 ns; | |
891434b1 RK |
395 | |
396 | if (!priv->hwts_rx_en) | |
397 | return; | |
398 | ||
ba1ffd74 GC |
399 | /* Check if timestamp is available */ |
400 | if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { | |
401 | /* For GMAC4, the valid timestamp is from CTX next desc. */ | |
402 | if (priv->plat->has_gmac4) | |
403 | ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); | |
404 | else | |
405 | ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); | |
891434b1 | 406 | |
ba1ffd74 GC |
407 | netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); |
408 | shhwtstamp = skb_hwtstamps(skb); | |
409 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
410 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
411 | } else { | |
412 | netdev_err(priv->dev, "cannot get RX hw timestamp\n"); | |
413 | } | |
891434b1 RK |
414 | } |
415 | ||
416 | /** | |
417 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
418 | * @dev: device pointer. | |
419 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
420 | * a proprietary structure used to pass information to the driver. | |
421 | * Description: | |
422 | * This function configures the MAC to enable/disable both outgoing(TX) | |
423 | * and incoming(RX) packets time stamping based on user input. | |
424 | * Return Value: | |
425 | * 0 on success and an appropriate -ve integer on failure. | |
426 | */ | |
427 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
428 | { | |
429 | struct stmmac_priv *priv = netdev_priv(dev); | |
430 | struct hwtstamp_config config; | |
0a624155 | 431 | struct timespec64 now; |
891434b1 RK |
432 | u64 temp = 0; |
433 | u32 ptp_v2 = 0; | |
434 | u32 tstamp_all = 0; | |
435 | u32 ptp_over_ipv4_udp = 0; | |
436 | u32 ptp_over_ipv6_udp = 0; | |
437 | u32 ptp_over_ethernet = 0; | |
438 | u32 snap_type_sel = 0; | |
439 | u32 ts_master_en = 0; | |
440 | u32 ts_event_en = 0; | |
441 | u32 value = 0; | |
19d857c9 | 442 | u32 sec_inc; |
891434b1 RK |
443 | |
444 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
445 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
446 | priv->hwts_tx_en = 0; | |
447 | priv->hwts_rx_en = 0; | |
448 | ||
449 | return -EOPNOTSUPP; | |
450 | } | |
451 | ||
452 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 453 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
454 | return -EFAULT; |
455 | ||
38ddc59d LC |
456 | netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", |
457 | __func__, config.flags, config.tx_type, config.rx_filter); | |
891434b1 RK |
458 | |
459 | /* reserved for future extensions */ | |
460 | if (config.flags) | |
461 | return -EINVAL; | |
462 | ||
5f3da328 BH |
463 | if (config.tx_type != HWTSTAMP_TX_OFF && |
464 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 465 | return -ERANGE; |
891434b1 RK |
466 | |
467 | if (priv->adv_ts) { | |
468 | switch (config.rx_filter) { | |
891434b1 | 469 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 470 | /* time stamp no incoming packet at all */ |
891434b1 RK |
471 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
472 | break; | |
473 | ||
891434b1 | 474 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 475 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
476 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
477 | /* take time stamp for all event messages */ | |
478 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
479 | ||
480 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
481 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
482 | break; | |
483 | ||
891434b1 | 484 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 485 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
486 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
487 | /* take time stamp for SYNC messages only */ | |
488 | ts_event_en = PTP_TCR_TSEVNTENA; | |
489 | ||
490 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
491 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
492 | break; | |
493 | ||
891434b1 | 494 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 495 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
496 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
497 | /* take time stamp for Delay_Req messages only */ | |
498 | ts_master_en = PTP_TCR_TSMSTRENA; | |
499 | ts_event_en = PTP_TCR_TSEVNTENA; | |
500 | ||
501 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
502 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
503 | break; | |
504 | ||
891434b1 | 505 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 506 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
507 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
508 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
509 | /* take time stamp for all event messages */ | |
510 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
511 | ||
512 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
513 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
514 | break; | |
515 | ||
891434b1 | 516 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 517 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
518 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
519 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
520 | /* take time stamp for SYNC messages only */ | |
521 | ts_event_en = PTP_TCR_TSEVNTENA; | |
522 | ||
523 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
524 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
525 | break; | |
526 | ||
891434b1 | 527 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 528 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
529 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
530 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
531 | /* take time stamp for Delay_Req messages only */ | |
532 | ts_master_en = PTP_TCR_TSMSTRENA; | |
533 | ts_event_en = PTP_TCR_TSEVNTENA; | |
534 | ||
535 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
536 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
537 | break; | |
538 | ||
891434b1 | 539 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 540 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
541 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
542 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
543 | /* take time stamp for all event messages */ | |
544 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
545 | ||
546 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
547 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
548 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
549 | break; | |
550 | ||
891434b1 | 551 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 552 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
553 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
554 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
555 | /* take time stamp for SYNC messages only */ | |
556 | ts_event_en = PTP_TCR_TSEVNTENA; | |
557 | ||
558 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
559 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
560 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
561 | break; | |
562 | ||
891434b1 | 563 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 564 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
565 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
566 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
567 | /* take time stamp for Delay_Req messages only */ | |
568 | ts_master_en = PTP_TCR_TSMSTRENA; | |
569 | ts_event_en = PTP_TCR_TSEVNTENA; | |
570 | ||
571 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
572 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
573 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
574 | break; | |
575 | ||
891434b1 | 576 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 577 | /* time stamp any incoming packet */ |
891434b1 RK |
578 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
579 | tstamp_all = PTP_TCR_TSENALL; | |
580 | break; | |
581 | ||
582 | default: | |
583 | return -ERANGE; | |
584 | } | |
585 | } else { | |
586 | switch (config.rx_filter) { | |
587 | case HWTSTAMP_FILTER_NONE: | |
588 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
589 | break; | |
590 | default: | |
591 | /* PTP v1, UDP, any kind of event packet */ | |
592 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
593 | break; | |
594 | } | |
595 | } | |
596 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 597 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
598 | |
599 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
ba1ffd74 | 600 | priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); |
891434b1 RK |
601 | else { |
602 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
603 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
604 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
605 | ts_master_en | snap_type_sel); | |
ba1ffd74 | 606 | priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); |
891434b1 RK |
607 | |
608 | /* program Sub Second Increment reg */ | |
19d857c9 | 609 | sec_inc = priv->hw->ptp->config_sub_second_increment( |
ba1ffd74 GC |
610 | priv->ptpaddr, priv->clk_ptp_rate, |
611 | priv->plat->has_gmac4); | |
19d857c9 | 612 | temp = div_u64(1000000000ULL, sec_inc); |
891434b1 RK |
613 | |
614 | /* calculate default added value: | |
615 | * formula is : | |
616 | * addend = (2^32)/freq_div_ratio; | |
19d857c9 | 617 | * where, freq_div_ratio = 1e9ns/sec_inc |
891434b1 | 618 | */ |
19d857c9 | 619 | temp = (u64)(temp << 32); |
5566401f | 620 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
ba1ffd74 | 621 | priv->hw->ptp->config_addend(priv->ptpaddr, |
891434b1 RK |
622 | priv->default_addend); |
623 | ||
624 | /* initialize system time */ | |
0a624155 AB |
625 | ktime_get_real_ts64(&now); |
626 | ||
627 | /* lower 32 bits of tv_sec are safe until y2106 */ | |
ba1ffd74 | 628 | priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, |
891434b1 RK |
629 | now.tv_nsec); |
630 | } | |
631 | ||
632 | return copy_to_user(ifr->ifr_data, &config, | |
633 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
634 | } | |
635 | ||
32ceabca | 636 | /** |
732fdf0e | 637 | * stmmac_init_ptp - init PTP |
32ceabca | 638 | * @priv: driver private structure |
732fdf0e | 639 | * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
32ceabca | 640 | * This is done by looking at the HW cap. register. |
732fdf0e | 641 | * This function also registers the ptp driver. |
32ceabca | 642 | */ |
92ba6888 | 643 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 644 | { |
92ba6888 RK |
645 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
646 | return -EOPNOTSUPP; | |
647 | ||
5566401f GC |
648 | /* Fall-back to main clock in case of no PTP ref is passed */ |
649 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
650 | if (IS_ERR(priv->clk_ptp_ref)) { | |
651 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
652 | priv->clk_ptp_ref = NULL; | |
be9b3174 | 653 | netdev_dbg(priv->dev, "PTP uses main clock\n"); |
5566401f GC |
654 | } else { |
655 | clk_prepare_enable(priv->clk_ptp_ref); | |
656 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
be9b3174 | 657 | netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); |
5566401f GC |
658 | } |
659 | ||
7cd01399 | 660 | priv->adv_ts = 0; |
be9b3174 GC |
661 | /* Check if adv_ts can be enabled for dwmac 4.x core */ |
662 | if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) | |
663 | priv->adv_ts = 1; | |
664 | /* Dwmac 3.x core with extend_desc can support adv_ts */ | |
665 | else if (priv->extend_desc && priv->dma_cap.atime_stamp) | |
7cd01399 VB |
666 | priv->adv_ts = 1; |
667 | ||
be9b3174 GC |
668 | if (priv->dma_cap.time_stamp) |
669 | netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); | |
7cd01399 | 670 | |
be9b3174 GC |
671 | if (priv->adv_ts) |
672 | netdev_info(priv->dev, | |
673 | "IEEE 1588-2008 Advanced Timestamp supported\n"); | |
891434b1 RK |
674 | |
675 | priv->hw->ptp = &stmmac_ptp; | |
676 | priv->hwts_tx_en = 0; | |
677 | priv->hwts_rx_en = 0; | |
92ba6888 | 678 | |
c30a70d3 GC |
679 | stmmac_ptp_register(priv); |
680 | ||
681 | return 0; | |
92ba6888 RK |
682 | } |
683 | ||
684 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
685 | { | |
5566401f GC |
686 | if (priv->clk_ptp_ref) |
687 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 688 | stmmac_ptp_unregister(priv); |
891434b1 RK |
689 | } |
690 | ||
47dd7a54 | 691 | /** |
732fdf0e | 692 | * stmmac_adjust_link - adjusts the link parameters |
47dd7a54 | 693 | * @dev: net device structure |
732fdf0e GC |
694 | * Description: this is the helper called by the physical abstraction layer |
695 | * drivers to communicate the phy link status. According the speed and duplex | |
696 | * this driver can invoke registered glue-logic as well. | |
697 | * It also invoke the eee initialization because it could happen when switch | |
698 | * on different networks (that are eee capable). | |
47dd7a54 GC |
699 | */ |
700 | static void stmmac_adjust_link(struct net_device *dev) | |
701 | { | |
702 | struct stmmac_priv *priv = netdev_priv(dev); | |
d6d50c7e | 703 | struct phy_device *phydev = dev->phydev; |
47dd7a54 GC |
704 | unsigned long flags; |
705 | int new_state = 0; | |
706 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
707 | ||
708 | if (phydev == NULL) | |
709 | return; | |
710 | ||
47dd7a54 | 711 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 712 | |
47dd7a54 | 713 | if (phydev->link) { |
ad01b7d4 | 714 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
715 | |
716 | /* Now we make sure that we can be in full duplex mode. | |
717 | * If not, we operate in half-duplex mode. */ | |
718 | if (phydev->duplex != priv->oldduplex) { | |
719 | new_state = 1; | |
720 | if (!(phydev->duplex)) | |
db98a0b0 | 721 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 722 | else |
db98a0b0 | 723 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
724 | priv->oldduplex = phydev->duplex; |
725 | } | |
726 | /* Flow Control operation */ | |
727 | if (phydev->pause) | |
7ed24bbe | 728 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 729 | fc, pause_time); |
47dd7a54 GC |
730 | |
731 | if (phydev->speed != priv->speed) { | |
732 | new_state = 1; | |
733 | switch (phydev->speed) { | |
734 | case 1000: | |
f748be53 AT |
735 | if (likely((priv->plat->has_gmac) || |
736 | (priv->plat->has_gmac4))) | |
db98a0b0 | 737 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 738 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
739 | break; |
740 | case 100: | |
741 | case 10: | |
f748be53 AT |
742 | if (likely((priv->plat->has_gmac) || |
743 | (priv->plat->has_gmac4))) { | |
db98a0b0 | 744 | ctrl |= priv->hw->link.port; |
47dd7a54 | 745 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 746 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 747 | } else { |
db98a0b0 | 748 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
749 | } |
750 | } else { | |
db98a0b0 | 751 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 752 | } |
9dfeb4d9 | 753 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
754 | break; |
755 | default: | |
b3e51069 LC |
756 | netif_warn(priv, link, priv->dev, |
757 | "Speed (%d) not 10/100\n", | |
758 | phydev->speed); | |
47dd7a54 GC |
759 | break; |
760 | } | |
761 | ||
762 | priv->speed = phydev->speed; | |
763 | } | |
764 | ||
ad01b7d4 | 765 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
766 | |
767 | if (!priv->oldlink) { | |
768 | new_state = 1; | |
769 | priv->oldlink = 1; | |
770 | } | |
771 | } else if (priv->oldlink) { | |
772 | new_state = 1; | |
773 | priv->oldlink = 0; | |
774 | priv->speed = 0; | |
775 | priv->oldduplex = -1; | |
776 | } | |
777 | ||
778 | if (new_state && netif_msg_link(priv)) | |
779 | phy_print_status(phydev); | |
780 | ||
4741cf9c GC |
781 | spin_unlock_irqrestore(&priv->lock, flags); |
782 | ||
52f95bbf GC |
783 | if (phydev->is_pseudo_fixed_link) |
784 | /* Stop PHY layer to call the hook to adjust the link in case | |
785 | * of a switch is attached to the stmmac driver. | |
786 | */ | |
787 | phydev->irq = PHY_IGNORE_INTERRUPT; | |
788 | else | |
789 | /* At this stage, init the EEE if supported. | |
790 | * Never called in case of fixed_link. | |
791 | */ | |
792 | priv->eee_enabled = stmmac_eee_init(priv); | |
47dd7a54 GC |
793 | } |
794 | ||
32ceabca | 795 | /** |
732fdf0e | 796 | * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
32ceabca GC |
797 | * @priv: driver private structure |
798 | * Description: this is to verify if the HW supports the PCS. | |
799 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
800 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
801 | */ | |
e58bb43f GC |
802 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
803 | { | |
804 | int interface = priv->plat->interface; | |
805 | ||
806 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
807 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
808 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
809 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
810 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
38ddc59d | 811 | netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); |
3fe5cadb | 812 | priv->hw->pcs = STMMAC_PCS_RGMII; |
0d909dcd | 813 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
38ddc59d | 814 | netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); |
3fe5cadb | 815 | priv->hw->pcs = STMMAC_PCS_SGMII; |
e58bb43f GC |
816 | } |
817 | } | |
818 | } | |
819 | ||
47dd7a54 GC |
820 | /** |
821 | * stmmac_init_phy - PHY initialization | |
822 | * @dev: net device structure | |
823 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
824 | * to the mac driver. | |
825 | * Return value: | |
826 | * 0 on success | |
827 | */ | |
828 | static int stmmac_init_phy(struct net_device *dev) | |
829 | { | |
830 | struct stmmac_priv *priv = netdev_priv(dev); | |
831 | struct phy_device *phydev; | |
d765955d | 832 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 833 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 834 | int interface = priv->plat->interface; |
9cbadf09 | 835 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
836 | priv->oldlink = 0; |
837 | priv->speed = 0; | |
838 | priv->oldduplex = -1; | |
839 | ||
5790cf3c MO |
840 | if (priv->plat->phy_node) { |
841 | phydev = of_phy_connect(dev, priv->plat->phy_node, | |
842 | &stmmac_adjust_link, 0, interface); | |
843 | } else { | |
a7657f12 GC |
844 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", |
845 | priv->plat->bus_id); | |
5790cf3c MO |
846 | |
847 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, | |
848 | priv->plat->phy_addr); | |
de9a2165 | 849 | netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, |
38ddc59d | 850 | phy_id_fmt); |
5790cf3c MO |
851 | |
852 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, | |
853 | interface); | |
854 | } | |
47dd7a54 | 855 | |
dfc50fca | 856 | if (IS_ERR_OR_NULL(phydev)) { |
38ddc59d | 857 | netdev_err(priv->dev, "Could not attach to PHY\n"); |
dfc50fca AB |
858 | if (!phydev) |
859 | return -ENODEV; | |
860 | ||
47dd7a54 GC |
861 | return PTR_ERR(phydev); |
862 | } | |
863 | ||
79ee1dc3 | 864 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 865 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 866 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 867 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
868 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
869 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 870 | |
47dd7a54 GC |
871 | /* |
872 | * Broken HW is sometimes missing the pull-up resistor on the | |
873 | * MDIO line, which results in reads to non-existent devices returning | |
874 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
875 | * device as well. | |
876 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
877 | */ | |
27732381 | 878 | if (!priv->plat->phy_node && phydev->phy_id == 0) { |
47dd7a54 GC |
879 | phy_disconnect(phydev); |
880 | return -ENODEV; | |
881 | } | |
8e99fc5f | 882 | |
c51e424d FF |
883 | /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid |
884 | * subsequent PHY polling, make sure we force a link transition if | |
885 | * we have a UP/DOWN/UP transition | |
886 | */ | |
887 | if (phydev->is_pseudo_fixed_link) | |
888 | phydev->irq = PHY_POLL; | |
889 | ||
de9a2165 LC |
890 | netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n", |
891 | __func__, phydev->phy_id, phydev->link); | |
47dd7a54 | 892 | |
47dd7a54 GC |
893 | return 0; |
894 | } | |
895 | ||
c24602ef GC |
896 | static void stmmac_display_rings(struct stmmac_priv *priv) |
897 | { | |
d0225e7d AT |
898 | void *head_rx, *head_tx; |
899 | ||
c24602ef | 900 | if (priv->extend_desc) { |
d0225e7d AT |
901 | head_rx = (void *)priv->dma_erx; |
902 | head_tx = (void *)priv->dma_etx; | |
c24602ef | 903 | } else { |
d0225e7d AT |
904 | head_rx = (void *)priv->dma_rx; |
905 | head_tx = (void *)priv->dma_tx; | |
c24602ef | 906 | } |
d0225e7d AT |
907 | |
908 | /* Display Rx ring */ | |
909 | priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); | |
910 | /* Display Tx ring */ | |
911 | priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); | |
c24602ef GC |
912 | } |
913 | ||
286a8372 GC |
914 | static int stmmac_set_bfsize(int mtu, int bufsize) |
915 | { | |
916 | int ret = bufsize; | |
917 | ||
918 | if (mtu >= BUF_SIZE_4KiB) | |
919 | ret = BUF_SIZE_8KiB; | |
920 | else if (mtu >= BUF_SIZE_2KiB) | |
921 | ret = BUF_SIZE_4KiB; | |
d916701c | 922 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
923 | ret = BUF_SIZE_2KiB; |
924 | else | |
d916701c | 925 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
926 | |
927 | return ret; | |
928 | } | |
929 | ||
32ceabca | 930 | /** |
732fdf0e | 931 | * stmmac_clear_descriptors - clear descriptors |
32ceabca GC |
932 | * @priv: driver private structure |
933 | * Description: this function is called to clear the tx and rx descriptors | |
934 | * in case of both basic and extended descriptors are used. | |
935 | */ | |
c24602ef GC |
936 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
937 | { | |
938 | int i; | |
c24602ef GC |
939 | |
940 | /* Clear the Rx/Tx descriptors */ | |
e3ad57c9 | 941 | for (i = 0; i < DMA_RX_SIZE; i++) |
c24602ef GC |
942 | if (priv->extend_desc) |
943 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
944 | priv->use_riwt, priv->mode, | |
e3ad57c9 | 945 | (i == DMA_RX_SIZE - 1)); |
c24602ef GC |
946 | else |
947 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
948 | priv->use_riwt, priv->mode, | |
e3ad57c9 GC |
949 | (i == DMA_RX_SIZE - 1)); |
950 | for (i = 0; i < DMA_TX_SIZE; i++) | |
c24602ef GC |
951 | if (priv->extend_desc) |
952 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
953 | priv->mode, | |
e3ad57c9 | 954 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
955 | else |
956 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
957 | priv->mode, | |
e3ad57c9 | 958 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
959 | } |
960 | ||
732fdf0e GC |
961 | /** |
962 | * stmmac_init_rx_buffers - init the RX descriptor buffer. | |
963 | * @priv: driver private structure | |
964 | * @p: descriptor pointer | |
965 | * @i: descriptor index | |
966 | * @flags: gfp flag. | |
967 | * Description: this function is called to allocate a receive buffer, perform | |
968 | * the DMA mapping and init the descriptor. | |
969 | */ | |
c24602ef | 970 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
777da230 | 971 | int i, gfp_t flags) |
c24602ef GC |
972 | { |
973 | struct sk_buff *skb; | |
974 | ||
4ec49a37 | 975 | skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); |
56329137 | 976 | if (!skb) { |
38ddc59d LC |
977 | netdev_err(priv->dev, |
978 | "%s: Rx init fails; skb is NULL\n", __func__); | |
56329137 | 979 | return -ENOMEM; |
c24602ef | 980 | } |
c24602ef GC |
981 | priv->rx_skbuff[i] = skb; |
982 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
983 | priv->dma_buf_sz, | |
984 | DMA_FROM_DEVICE); | |
56329137 | 985 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
38ddc59d | 986 | netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); |
56329137 BZ |
987 | dev_kfree_skb_any(skb); |
988 | return -EINVAL; | |
989 | } | |
c24602ef | 990 | |
f748be53 | 991 | if (priv->synopsys_id >= DWMAC_CORE_4_00) |
f8be0d78 | 992 | p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]); |
f748be53 | 993 | else |
f8be0d78 | 994 | p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]); |
c24602ef | 995 | |
29896a67 | 996 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 997 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 998 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
999 | |
1000 | return 0; | |
1001 | } | |
1002 | ||
56329137 BZ |
1003 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
1004 | { | |
1005 | if (priv->rx_skbuff[i]) { | |
1006 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
1007 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1008 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1009 | } | |
1010 | priv->rx_skbuff[i] = NULL; | |
1011 | } | |
1012 | ||
47dd7a54 GC |
1013 | /** |
1014 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1015 | * @dev: net device structure | |
732fdf0e GC |
1016 | * @flags: gfp flag. |
1017 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1018 | * and allocates the socket buffers. It suppors the chained and ring |
1019 | * modes. | |
47dd7a54 | 1020 | */ |
777da230 | 1021 | static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
47dd7a54 GC |
1022 | { |
1023 | int i; | |
1024 | struct stmmac_priv *priv = netdev_priv(dev); | |
4a7d666a | 1025 | unsigned int bfsize = 0; |
56329137 | 1026 | int ret = -ENOMEM; |
47dd7a54 | 1027 | |
29896a67 GC |
1028 | if (priv->hw->mode->set_16kib_bfsize) |
1029 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1030 | |
4a7d666a | 1031 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1032 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1033 | |
2618abb7 VB |
1034 | priv->dma_buf_sz = bfsize; |
1035 | ||
b3e51069 LC |
1036 | netif_dbg(priv, probe, priv->dev, |
1037 | "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", | |
1038 | __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy); | |
1039 | ||
1040 | /* RX INITIALIZATION */ | |
1041 | netif_dbg(priv, probe, priv->dev, | |
1042 | "SKB addresses:\nskb\t\tskb data\tdma data\n"); | |
47dd7a54 | 1043 | |
e3ad57c9 | 1044 | for (i = 0; i < DMA_RX_SIZE; i++) { |
c24602ef GC |
1045 | struct dma_desc *p; |
1046 | if (priv->extend_desc) | |
1047 | p = &((priv->dma_erx + i)->basic); | |
1048 | else | |
1049 | p = priv->dma_rx + i; | |
47dd7a54 | 1050 | |
777da230 | 1051 | ret = stmmac_init_rx_buffers(priv, p, i, flags); |
56329137 BZ |
1052 | if (ret) |
1053 | goto err_init_rx_buffers; | |
286a8372 | 1054 | |
b3e51069 LC |
1055 | netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", |
1056 | priv->rx_skbuff[i], priv->rx_skbuff[i]->data, | |
1057 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1058 | } |
1059 | priv->cur_rx = 0; | |
e3ad57c9 | 1060 | priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); |
47dd7a54 GC |
1061 | buf_sz = bfsize; |
1062 | ||
c24602ef GC |
1063 | /* Setup the chained descriptor addresses */ |
1064 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1065 | if (priv->extend_desc) { | |
29896a67 | 1066 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
e3ad57c9 | 1067 | DMA_RX_SIZE, 1); |
29896a67 | 1068 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, |
e3ad57c9 | 1069 | DMA_TX_SIZE, 1); |
c24602ef | 1070 | } else { |
29896a67 | 1071 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
e3ad57c9 | 1072 | DMA_RX_SIZE, 0); |
29896a67 | 1073 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, |
e3ad57c9 | 1074 | DMA_TX_SIZE, 0); |
c24602ef GC |
1075 | } |
1076 | } | |
1077 | ||
47dd7a54 | 1078 | /* TX INITIALIZATION */ |
e3ad57c9 | 1079 | for (i = 0; i < DMA_TX_SIZE; i++) { |
c24602ef GC |
1080 | struct dma_desc *p; |
1081 | if (priv->extend_desc) | |
1082 | p = &((priv->dma_etx + i)->basic); | |
1083 | else | |
1084 | p = priv->dma_tx + i; | |
f748be53 AT |
1085 | |
1086 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { | |
1087 | p->des0 = 0; | |
1088 | p->des1 = 0; | |
1089 | p->des2 = 0; | |
1090 | p->des3 = 0; | |
1091 | } else { | |
1092 | p->des2 = 0; | |
1093 | } | |
1094 | ||
362b37be GC |
1095 | priv->tx_skbuff_dma[i].buf = 0; |
1096 | priv->tx_skbuff_dma[i].map_as_page = false; | |
553e2ab3 | 1097 | priv->tx_skbuff_dma[i].len = 0; |
2a6d8e17 | 1098 | priv->tx_skbuff_dma[i].last_segment = false; |
47dd7a54 | 1099 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1100 | } |
286a8372 | 1101 | |
47dd7a54 GC |
1102 | priv->dirty_tx = 0; |
1103 | priv->cur_tx = 0; | |
38979574 | 1104 | netdev_reset_queue(priv->dev); |
47dd7a54 | 1105 | |
c24602ef | 1106 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1107 | |
c24602ef GC |
1108 | if (netif_msg_hw(priv)) |
1109 | stmmac_display_rings(priv); | |
56329137 BZ |
1110 | |
1111 | return 0; | |
1112 | err_init_rx_buffers: | |
1113 | while (--i >= 0) | |
1114 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1115 | return ret; |
47dd7a54 GC |
1116 | } |
1117 | ||
1118 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1119 | { | |
1120 | int i; | |
1121 | ||
e3ad57c9 | 1122 | for (i = 0; i < DMA_RX_SIZE; i++) |
56329137 | 1123 | stmmac_free_rx_buffers(priv, i); |
47dd7a54 GC |
1124 | } |
1125 | ||
1126 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1127 | { | |
1128 | int i; | |
1129 | ||
e3ad57c9 | 1130 | for (i = 0; i < DMA_TX_SIZE; i++) { |
75e4364f | 1131 | struct dma_desc *p; |
1132 | ||
1133 | if (priv->extend_desc) | |
1134 | p = &((priv->dma_etx + i)->basic); | |
1135 | else | |
1136 | p = priv->dma_tx + i; | |
1137 | ||
362b37be GC |
1138 | if (priv->tx_skbuff_dma[i].buf) { |
1139 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1140 | dma_unmap_page(priv->device, | |
1141 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1142 | priv->tx_skbuff_dma[i].len, |
362b37be GC |
1143 | DMA_TO_DEVICE); |
1144 | else | |
1145 | dma_unmap_single(priv->device, | |
1146 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1147 | priv->tx_skbuff_dma[i].len, |
362b37be | 1148 | DMA_TO_DEVICE); |
75e4364f | 1149 | } |
c24602ef | 1150 | |
75e4364f | 1151 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1152 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1153 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1154 | priv->tx_skbuff_dma[i].buf = 0; |
1155 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1156 | } |
1157 | } | |
47dd7a54 GC |
1158 | } |
1159 | ||
732fdf0e GC |
1160 | /** |
1161 | * alloc_dma_desc_resources - alloc TX/RX resources. | |
1162 | * @priv: private structure | |
1163 | * Description: according to which descriptor can be used (extend or basic) | |
1164 | * this function allocates the resources for TX and RX paths. In case of | |
1165 | * reception, for example, it pre-allocated the RX socket buffer in order to | |
1166 | * allow zero-copy mechanism. | |
1167 | */ | |
09f8d696 SK |
1168 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1169 | { | |
09f8d696 SK |
1170 | int ret = -ENOMEM; |
1171 | ||
e3ad57c9 | 1172 | priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), |
09f8d696 SK |
1173 | GFP_KERNEL); |
1174 | if (!priv->rx_skbuff_dma) | |
1175 | return -ENOMEM; | |
1176 | ||
e3ad57c9 | 1177 | priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1178 | GFP_KERNEL); |
1179 | if (!priv->rx_skbuff) | |
1180 | goto err_rx_skbuff; | |
1181 | ||
e3ad57c9 | 1182 | priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, |
362b37be | 1183 | sizeof(*priv->tx_skbuff_dma), |
09f8d696 SK |
1184 | GFP_KERNEL); |
1185 | if (!priv->tx_skbuff_dma) | |
1186 | goto err_tx_skbuff_dma; | |
1187 | ||
e3ad57c9 | 1188 | priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1189 | GFP_KERNEL); |
1190 | if (!priv->tx_skbuff) | |
1191 | goto err_tx_skbuff; | |
1192 | ||
1193 | if (priv->extend_desc) { | |
e3ad57c9 | 1194 | priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1195 | sizeof(struct |
1196 | dma_extended_desc), | |
1197 | &priv->dma_rx_phy, | |
1198 | GFP_KERNEL); | |
09f8d696 SK |
1199 | if (!priv->dma_erx) |
1200 | goto err_dma; | |
1201 | ||
e3ad57c9 | 1202 | priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1203 | sizeof(struct |
1204 | dma_extended_desc), | |
1205 | &priv->dma_tx_phy, | |
1206 | GFP_KERNEL); | |
09f8d696 | 1207 | if (!priv->dma_etx) { |
e3ad57c9 | 1208 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1209 | sizeof(struct dma_extended_desc), |
1210 | priv->dma_erx, priv->dma_rx_phy); | |
09f8d696 SK |
1211 | goto err_dma; |
1212 | } | |
1213 | } else { | |
e3ad57c9 | 1214 | priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1215 | sizeof(struct dma_desc), |
1216 | &priv->dma_rx_phy, | |
1217 | GFP_KERNEL); | |
09f8d696 SK |
1218 | if (!priv->dma_rx) |
1219 | goto err_dma; | |
1220 | ||
e3ad57c9 | 1221 | priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1222 | sizeof(struct dma_desc), |
1223 | &priv->dma_tx_phy, | |
1224 | GFP_KERNEL); | |
09f8d696 | 1225 | if (!priv->dma_tx) { |
e3ad57c9 | 1226 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1227 | sizeof(struct dma_desc), |
1228 | priv->dma_rx, priv->dma_rx_phy); | |
09f8d696 SK |
1229 | goto err_dma; |
1230 | } | |
1231 | } | |
1232 | ||
1233 | return 0; | |
1234 | ||
1235 | err_dma: | |
1236 | kfree(priv->tx_skbuff); | |
1237 | err_tx_skbuff: | |
1238 | kfree(priv->tx_skbuff_dma); | |
1239 | err_tx_skbuff_dma: | |
1240 | kfree(priv->rx_skbuff); | |
1241 | err_rx_skbuff: | |
1242 | kfree(priv->rx_skbuff_dma); | |
1243 | return ret; | |
1244 | } | |
1245 | ||
47dd7a54 GC |
1246 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1247 | { | |
1248 | /* Release the DMA TX/RX socket buffers */ | |
1249 | dma_free_rx_skbufs(priv); | |
1250 | dma_free_tx_skbufs(priv); | |
1251 | ||
ceb69499 | 1252 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1253 | if (!priv->extend_desc) { |
1254 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1255 | DMA_TX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1256 | priv->dma_tx, priv->dma_tx_phy); |
1257 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1258 | DMA_RX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1259 | priv->dma_rx, priv->dma_rx_phy); |
1260 | } else { | |
e3ad57c9 | 1261 | dma_free_coherent(priv->device, DMA_TX_SIZE * |
c24602ef GC |
1262 | sizeof(struct dma_extended_desc), |
1263 | priv->dma_etx, priv->dma_tx_phy); | |
e3ad57c9 | 1264 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
c24602ef GC |
1265 | sizeof(struct dma_extended_desc), |
1266 | priv->dma_erx, priv->dma_rx_phy); | |
1267 | } | |
47dd7a54 GC |
1268 | kfree(priv->rx_skbuff_dma); |
1269 | kfree(priv->rx_skbuff); | |
cf32deec | 1270 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1271 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1272 | } |
1273 | ||
9eb12474 | 1274 | /** |
1275 | * stmmac_mac_enable_rx_queues - Enable MAC rx queues | |
1276 | * @priv: driver private structure | |
1277 | * Description: It is used for enabling the rx queues in the MAC | |
1278 | */ | |
1279 | static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) | |
1280 | { | |
1281 | int rx_count = priv->dma_cap.number_rx_queues; | |
1282 | int queue = 0; | |
1283 | ||
1284 | /* If GMAC does not have multiple queues, then this is not necessary*/ | |
1285 | if (rx_count == 1) | |
1286 | return; | |
1287 | ||
1288 | /** | |
1289 | * If the core is synthesized with multiple rx queues / multiple | |
1290 | * dma channels, then rx queues will be disabled by default. | |
1291 | * For now only rx queue 0 is enabled. | |
1292 | */ | |
1293 | priv->hw->mac->rx_queue_enable(priv->hw, queue); | |
1294 | } | |
1295 | ||
47dd7a54 GC |
1296 | /** |
1297 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1298 | * @priv: driver private structure |
732fdf0e GC |
1299 | * Description: it is used for configuring the DMA operation mode register in |
1300 | * order to program the tx/rx DMA thresholds or Store-And-Forward mode. | |
47dd7a54 GC |
1301 | */ |
1302 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1303 | { | |
f88203a2 VB |
1304 | int rxfifosz = priv->plat->rx_fifo_size; |
1305 | ||
e2a240c7 | 1306 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 | 1307 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); |
e2a240c7 | 1308 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
61b8013a SK |
1309 | /* |
1310 | * In case of GMAC, SF mode can be enabled | |
1311 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1312 | * 1) TX COE if actually supported |
1313 | * 2) There is no bugged Jumbo frame support | |
1314 | * that needs to not insert csum in the TDES. | |
1315 | */ | |
f88203a2 VB |
1316 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, |
1317 | rxfifosz); | |
b2dec116 | 1318 | priv->xstats.threshold = SF_DMA_MODE; |
ebbb293f | 1319 | } else |
f88203a2 VB |
1320 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, |
1321 | rxfifosz); | |
47dd7a54 GC |
1322 | } |
1323 | ||
47dd7a54 | 1324 | /** |
732fdf0e | 1325 | * stmmac_tx_clean - to manage the transmission completion |
32ceabca | 1326 | * @priv: driver private structure |
732fdf0e | 1327 | * Description: it reclaims the transmit resources after transmission completes. |
47dd7a54 | 1328 | */ |
9125cdd1 | 1329 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 | 1330 | { |
38979574 | 1331 | unsigned int bytes_compl = 0, pkts_compl = 0; |
e3ad57c9 | 1332 | unsigned int entry = priv->dirty_tx; |
47dd7a54 | 1333 | |
739c8e14 | 1334 | netif_tx_lock(priv->dev); |
a9097a96 | 1335 | |
9125cdd1 GC |
1336 | priv->xstats.tx_clean++; |
1337 | ||
e3ad57c9 | 1338 | while (entry != priv->cur_tx) { |
47dd7a54 | 1339 | struct sk_buff *skb = priv->tx_skbuff[entry]; |
c24602ef | 1340 | struct dma_desc *p; |
c363b658 | 1341 | int status; |
c24602ef GC |
1342 | |
1343 | if (priv->extend_desc) | |
ceb69499 | 1344 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1345 | else |
1346 | p = priv->dma_tx + entry; | |
47dd7a54 | 1347 | |
c363b658 | 1348 | status = priv->hw->desc->tx_status(&priv->dev->stats, |
ceb69499 GC |
1349 | &priv->xstats, p, |
1350 | priv->ioaddr); | |
c363b658 FG |
1351 | /* Check if the descriptor is owned by the DMA */ |
1352 | if (unlikely(status & tx_dma_own)) | |
1353 | break; | |
1354 | ||
1355 | /* Just consider the last segment and ...*/ | |
1356 | if (likely(!(status & tx_not_ls))) { | |
1357 | /* ... verify the status error condition */ | |
1358 | if (unlikely(status & tx_err)) { | |
1359 | priv->dev->stats.tx_errors++; | |
1360 | } else { | |
47dd7a54 GC |
1361 | priv->dev->stats.tx_packets++; |
1362 | priv->xstats.tx_pkt_n++; | |
c363b658 | 1363 | } |
ba1ffd74 | 1364 | stmmac_get_tx_hwtstamp(priv, p, skb); |
47dd7a54 | 1365 | } |
47dd7a54 | 1366 | |
362b37be GC |
1367 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1368 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1369 | dma_unmap_page(priv->device, | |
1370 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1371 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1372 | DMA_TO_DEVICE); |
1373 | else | |
1374 | dma_unmap_single(priv->device, | |
1375 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1376 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1377 | DMA_TO_DEVICE); |
1378 | priv->tx_skbuff_dma[entry].buf = 0; | |
f748be53 | 1379 | priv->tx_skbuff_dma[entry].len = 0; |
362b37be | 1380 | priv->tx_skbuff_dma[entry].map_as_page = false; |
cf32deec | 1381 | } |
f748be53 AT |
1382 | |
1383 | if (priv->hw->mode->clean_desc3) | |
1384 | priv->hw->mode->clean_desc3(priv, p); | |
1385 | ||
2a6d8e17 | 1386 | priv->tx_skbuff_dma[entry].last_segment = false; |
96951366 | 1387 | priv->tx_skbuff_dma[entry].is_jumbo = false; |
47dd7a54 GC |
1388 | |
1389 | if (likely(skb != NULL)) { | |
38979574 BG |
1390 | pkts_compl++; |
1391 | bytes_compl += skb->len; | |
7c565c33 | 1392 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1393 | priv->tx_skbuff[entry] = NULL; |
1394 | } | |
1395 | ||
4a7d666a | 1396 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1397 | |
e3ad57c9 | 1398 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
47dd7a54 | 1399 | } |
fbc80823 | 1400 | priv->dirty_tx = entry; |
38979574 BG |
1401 | |
1402 | netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); | |
1403 | ||
47dd7a54 | 1404 | if (unlikely(netif_queue_stopped(priv->dev) && |
739c8e14 LS |
1405 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { |
1406 | netif_dbg(priv, tx_done, priv->dev, | |
1407 | "%s: restart transmit\n", __func__); | |
1408 | netif_wake_queue(priv->dev); | |
47dd7a54 | 1409 | } |
d765955d GC |
1410 | |
1411 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1412 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1413 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1414 | } |
739c8e14 | 1415 | netif_tx_unlock(priv->dev); |
47dd7a54 GC |
1416 | } |
1417 | ||
9125cdd1 | 1418 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1419 | { |
7284a3f1 | 1420 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1421 | } |
1422 | ||
9125cdd1 | 1423 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1424 | { |
7284a3f1 | 1425 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1426 | } |
1427 | ||
47dd7a54 | 1428 | /** |
732fdf0e | 1429 | * stmmac_tx_err - to manage the tx error |
32ceabca | 1430 | * @priv: driver private structure |
47dd7a54 | 1431 | * Description: it cleans the descriptors and restarts the transmission |
732fdf0e | 1432 | * in case of transmission errors. |
47dd7a54 GC |
1433 | */ |
1434 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1435 | { | |
c24602ef | 1436 | int i; |
47dd7a54 GC |
1437 | netif_stop_queue(priv->dev); |
1438 | ||
ad01b7d4 | 1439 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1440 | dma_free_tx_skbufs(priv); |
e3ad57c9 | 1441 | for (i = 0; i < DMA_TX_SIZE; i++) |
c24602ef GC |
1442 | if (priv->extend_desc) |
1443 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1444 | priv->mode, | |
e3ad57c9 | 1445 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
1446 | else |
1447 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1448 | priv->mode, | |
e3ad57c9 | 1449 | (i == DMA_TX_SIZE - 1)); |
47dd7a54 GC |
1450 | priv->dirty_tx = 0; |
1451 | priv->cur_tx = 0; | |
38979574 | 1452 | netdev_reset_queue(priv->dev); |
ad01b7d4 | 1453 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1454 | |
1455 | priv->dev->stats.tx_errors++; | |
1456 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1457 | } |
1458 | ||
32ceabca | 1459 | /** |
732fdf0e | 1460 | * stmmac_dma_interrupt - DMA ISR |
32ceabca GC |
1461 | * @priv: driver private structure |
1462 | * Description: this is the DMA ISR. It is called by the main ISR. | |
732fdf0e GC |
1463 | * It calls the dwmac dma routine and schedule poll method in case of some |
1464 | * work can be done. | |
32ceabca | 1465 | */ |
aec7ff27 GC |
1466 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1467 | { | |
aec7ff27 | 1468 | int status; |
f88203a2 | 1469 | int rxfifosz = priv->plat->rx_fifo_size; |
aec7ff27 | 1470 | |
ad01b7d4 | 1471 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1472 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1473 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1474 | stmmac_disable_dma_irq(priv); | |
1475 | __napi_schedule(&priv->napi); | |
1476 | } | |
1477 | } | |
1478 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 | 1479 | /* Try to bump up the dma threshold on this failure */ |
b2dec116 SZ |
1480 | if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
1481 | (tc <= 256)) { | |
aec7ff27 | 1482 | tc += 64; |
c405abe2 | 1483 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 VB |
1484 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, |
1485 | rxfifosz); | |
c405abe2 SZ |
1486 | else |
1487 | priv->hw->dma->dma_mode(priv->ioaddr, tc, | |
f88203a2 | 1488 | SF_DMA_MODE, rxfifosz); |
aec7ff27 | 1489 | priv->xstats.threshold = tc; |
47dd7a54 | 1490 | } |
aec7ff27 GC |
1491 | } else if (unlikely(status == tx_hard_error)) |
1492 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1493 | } |
1494 | ||
32ceabca GC |
1495 | /** |
1496 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1497 | * @priv: driver private structure | |
1498 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1499 | */ | |
1c901a46 GC |
1500 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1501 | { | |
1502 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
36ff7c1e | 1503 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1504 | |
ba1ffd74 GC |
1505 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
1506 | priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; | |
f748be53 | 1507 | priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; |
ba1ffd74 GC |
1508 | } else { |
1509 | priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; | |
f748be53 | 1510 | priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; |
ba1ffd74 | 1511 | } |
36ff7c1e AT |
1512 | |
1513 | dwmac_mmc_intr_all_mask(priv->mmcaddr); | |
4f795b25 GC |
1514 | |
1515 | if (priv->dma_cap.rmon) { | |
36ff7c1e | 1516 | dwmac_mmc_ctrl(priv->mmcaddr, mode); |
4f795b25 GC |
1517 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); |
1518 | } else | |
38ddc59d | 1519 | netdev_info(priv->dev, "No MAC Management Counters available\n"); |
1c901a46 GC |
1520 | } |
1521 | ||
19e30c14 | 1522 | /** |
732fdf0e | 1523 | * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
32ceabca GC |
1524 | * @priv: driver private structure |
1525 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
732fdf0e GC |
1526 | * In case of Enhanced/Alternate, it checks if the extended descriptors are |
1527 | * supported by the HW capability register. | |
ff3dd78c | 1528 | */ |
19e30c14 GC |
1529 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1530 | { | |
1531 | if (priv->plat->enh_desc) { | |
38ddc59d | 1532 | dev_info(priv->device, "Enhanced/Alternate descriptors\n"); |
c24602ef GC |
1533 | |
1534 | /* GMAC older than 3.50 has no extended descriptors */ | |
1535 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
38ddc59d | 1536 | dev_info(priv->device, "Enabled extended descriptors\n"); |
c24602ef GC |
1537 | priv->extend_desc = 1; |
1538 | } else | |
38ddc59d | 1539 | dev_warn(priv->device, "Extended descriptors not supported\n"); |
c24602ef | 1540 | |
19e30c14 GC |
1541 | priv->hw->desc = &enh_desc_ops; |
1542 | } else { | |
38ddc59d | 1543 | dev_info(priv->device, "Normal descriptors\n"); |
19e30c14 GC |
1544 | priv->hw->desc = &ndesc_ops; |
1545 | } | |
1546 | } | |
1547 | ||
1548 | /** | |
732fdf0e | 1549 | * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
32ceabca | 1550 | * @priv: driver private structure |
19e30c14 GC |
1551 | * Description: |
1552 | * new GMAC chip generations have a new register to indicate the | |
1553 | * presence of the optional feature/functions. | |
1554 | * This can be also used to override the value passed through the | |
1555 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1556 | */ |
1557 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1558 | { | |
f10a6a35 | 1559 | u32 ret = 0; |
3c20f72f | 1560 | |
5e6efe88 | 1561 | if (priv->hw->dma->get_hw_feature) { |
f10a6a35 AT |
1562 | priv->hw->dma->get_hw_feature(priv->ioaddr, |
1563 | &priv->dma_cap); | |
1564 | ret = 1; | |
19e30c14 | 1565 | } |
e7434821 | 1566 | |
f10a6a35 | 1567 | return ret; |
e7434821 GC |
1568 | } |
1569 | ||
32ceabca | 1570 | /** |
732fdf0e | 1571 | * stmmac_check_ether_addr - check if the MAC addr is valid |
32ceabca GC |
1572 | * @priv: driver private structure |
1573 | * Description: | |
1574 | * it is to verify if the MAC address is valid, in case of failures it | |
1575 | * generates a random MAC address | |
1576 | */ | |
bfab27a1 GC |
1577 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1578 | { | |
bfab27a1 | 1579 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1580 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1581 | priv->dev->dev_addr, 0); |
ceb69499 | 1582 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1583 | eth_hw_addr_random(priv->dev); |
38ddc59d LC |
1584 | netdev_info(priv->dev, "device MAC address %pM\n", |
1585 | priv->dev->dev_addr); | |
bfab27a1 | 1586 | } |
bfab27a1 GC |
1587 | } |
1588 | ||
32ceabca | 1589 | /** |
732fdf0e | 1590 | * stmmac_init_dma_engine - DMA init. |
32ceabca GC |
1591 | * @priv: driver private structure |
1592 | * Description: | |
1593 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1594 | * Some DMA parameters can be passed from the platform; | |
1595 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1596 | */ | |
0f1f88a8 GC |
1597 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1598 | { | |
c24602ef | 1599 | int atds = 0; |
495db273 | 1600 | int ret = 0; |
0f1f88a8 | 1601 | |
a332e2fa NC |
1602 | if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { |
1603 | dev_err(priv->device, "Invalid DMA configuration\n"); | |
89ab75bf | 1604 | return -EINVAL; |
0f1f88a8 GC |
1605 | } |
1606 | ||
c24602ef GC |
1607 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1608 | atds = 1; | |
1609 | ||
495db273 GC |
1610 | ret = priv->hw->dma->reset(priv->ioaddr); |
1611 | if (ret) { | |
1612 | dev_err(priv->device, "Failed to reset the dma\n"); | |
1613 | return ret; | |
1614 | } | |
1615 | ||
50ca903a | 1616 | priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg, |
89ab75bf | 1617 | priv->dma_tx_phy, priv->dma_rx_phy, atds); |
afea0365 | 1618 | |
f748be53 AT |
1619 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
1620 | priv->rx_tail_addr = priv->dma_rx_phy + | |
1621 | (DMA_RX_SIZE * sizeof(struct dma_desc)); | |
1622 | priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, | |
1623 | STMMAC_CHAN0); | |
1624 | ||
1625 | priv->tx_tail_addr = priv->dma_tx_phy + | |
1626 | (DMA_TX_SIZE * sizeof(struct dma_desc)); | |
1627 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
1628 | STMMAC_CHAN0); | |
1629 | } | |
1630 | ||
1631 | if (priv->plat->axi && priv->hw->dma->axi) | |
afea0365 GC |
1632 | priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); |
1633 | ||
495db273 | 1634 | return ret; |
0f1f88a8 GC |
1635 | } |
1636 | ||
9125cdd1 | 1637 | /** |
732fdf0e | 1638 | * stmmac_tx_timer - mitigation sw timer for tx. |
9125cdd1 GC |
1639 | * @data: data pointer |
1640 | * Description: | |
1641 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1642 | */ | |
1643 | static void stmmac_tx_timer(unsigned long data) | |
1644 | { | |
1645 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1646 | ||
1647 | stmmac_tx_clean(priv); | |
1648 | } | |
1649 | ||
1650 | /** | |
732fdf0e | 1651 | * stmmac_init_tx_coalesce - init tx mitigation options. |
32ceabca | 1652 | * @priv: driver private structure |
9125cdd1 GC |
1653 | * Description: |
1654 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1655 | * timer handler and default threshold used for enabling the | |
1656 | * interrupt on completion bit. | |
1657 | */ | |
1658 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1659 | { | |
1660 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1661 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1662 | init_timer(&priv->txtimer); | |
1663 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1664 | priv->txtimer.data = (unsigned long)priv; | |
1665 | priv->txtimer.function = stmmac_tx_timer; | |
1666 | add_timer(&priv->txtimer); | |
1667 | } | |
1668 | ||
523f11b5 | 1669 | /** |
732fdf0e | 1670 | * stmmac_hw_setup - setup mac in a usable state. |
523f11b5 SK |
1671 | * @dev : pointer to the device structure. |
1672 | * Description: | |
732fdf0e GC |
1673 | * this is the main function to setup the HW in a usable state because the |
1674 | * dma engine is reset, the core registers are configured (e.g. AXI, | |
1675 | * Checksum features, timers). The DMA is ready to start receiving and | |
1676 | * transmitting. | |
523f11b5 SK |
1677 | * Return value: |
1678 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1679 | * file on failure. | |
1680 | */ | |
fe131929 | 1681 | static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
523f11b5 SK |
1682 | { |
1683 | struct stmmac_priv *priv = netdev_priv(dev); | |
1684 | int ret; | |
1685 | ||
523f11b5 SK |
1686 | /* DMA initialization and SW reset */ |
1687 | ret = stmmac_init_dma_engine(priv); | |
1688 | if (ret < 0) { | |
38ddc59d LC |
1689 | netdev_err(priv->dev, "%s: DMA engine initialization failed\n", |
1690 | __func__); | |
523f11b5 SK |
1691 | return ret; |
1692 | } | |
1693 | ||
1694 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1695 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1696 | |
1697 | /* If required, perform hw setup of the bus. */ | |
1698 | if (priv->plat->bus_setup) | |
1699 | priv->plat->bus_setup(priv->ioaddr); | |
1700 | ||
02e57b9d GC |
1701 | /* PS and related bits will be programmed according to the speed */ |
1702 | if (priv->hw->pcs) { | |
1703 | int speed = priv->plat->mac_port_sel_speed; | |
1704 | ||
1705 | if ((speed == SPEED_10) || (speed == SPEED_100) || | |
1706 | (speed == SPEED_1000)) { | |
1707 | priv->hw->ps = speed; | |
1708 | } else { | |
1709 | dev_warn(priv->device, "invalid port speed\n"); | |
1710 | priv->hw->ps = 0; | |
1711 | } | |
1712 | } | |
1713 | ||
523f11b5 | 1714 | /* Initialize the MAC Core */ |
7ed24bbe | 1715 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1716 | |
9eb12474 | 1717 | /* Initialize MAC RX Queues */ |
1718 | if (priv->hw->mac->rx_queue_enable) | |
1719 | stmmac_mac_enable_rx_queues(priv); | |
1720 | ||
978aded4 GC |
1721 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1722 | if (!ret) { | |
38ddc59d | 1723 | netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); |
978aded4 | 1724 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; |
d2afb5bd | 1725 | priv->hw->rx_csum = 0; |
978aded4 GC |
1726 | } |
1727 | ||
523f11b5 | 1728 | /* Enable the MAC Rx/Tx */ |
f748be53 AT |
1729 | if (priv->synopsys_id >= DWMAC_CORE_4_00) |
1730 | stmmac_dwmac4_set_mac(priv->ioaddr, true); | |
1731 | else | |
1732 | stmmac_set_mac(priv->ioaddr, true); | |
523f11b5 SK |
1733 | |
1734 | /* Set the HW DMA mode and the COE */ | |
1735 | stmmac_dma_operation_mode(priv); | |
1736 | ||
1737 | stmmac_mmc_setup(priv); | |
1738 | ||
fe131929 HC |
1739 | if (init_ptp) { |
1740 | ret = stmmac_init_ptp(priv); | |
7086605a | 1741 | if (ret) |
c30a70d3 | 1742 | netdev_warn(priv->dev, "fail to init PTP.\n"); |
fe131929 | 1743 | } |
523f11b5 | 1744 | |
50fb4f74 | 1745 | #ifdef CONFIG_DEBUG_FS |
523f11b5 SK |
1746 | ret = stmmac_init_fs(dev); |
1747 | if (ret < 0) | |
38ddc59d LC |
1748 | netdev_warn(priv->dev, "%s: failed debugFS registration\n", |
1749 | __func__); | |
523f11b5 SK |
1750 | #endif |
1751 | /* Start the ball rolling... */ | |
38ddc59d | 1752 | netdev_dbg(priv->dev, "DMA RX/TX processes started...\n"); |
523f11b5 SK |
1753 | priv->hw->dma->start_tx(priv->ioaddr); |
1754 | priv->hw->dma->start_rx(priv->ioaddr); | |
1755 | ||
1756 | /* Dump DMA/MAC registers */ | |
1757 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1758 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1759 | priv->hw->dma->dump_regs(priv->ioaddr); |
1760 | } | |
1761 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1762 | ||
523f11b5 SK |
1763 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
1764 | priv->rx_riwt = MAX_DMA_RIWT; | |
1765 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1766 | } | |
1767 | ||
3fe5cadb | 1768 | if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) |
02e57b9d | 1769 | priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); |
523f11b5 | 1770 | |
f748be53 AT |
1771 | /* set TX ring length */ |
1772 | if (priv->hw->dma->set_tx_ring_len) | |
1773 | priv->hw->dma->set_tx_ring_len(priv->ioaddr, | |
1774 | (DMA_TX_SIZE - 1)); | |
1775 | /* set RX ring length */ | |
1776 | if (priv->hw->dma->set_rx_ring_len) | |
1777 | priv->hw->dma->set_rx_ring_len(priv->ioaddr, | |
1778 | (DMA_RX_SIZE - 1)); | |
1779 | /* Enable TSO */ | |
1780 | if (priv->tso) | |
1781 | priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); | |
1782 | ||
523f11b5 SK |
1783 | return 0; |
1784 | } | |
1785 | ||
47dd7a54 GC |
1786 | /** |
1787 | * stmmac_open - open entry point of the driver | |
1788 | * @dev : pointer to the device structure. | |
1789 | * Description: | |
1790 | * This function is the open entry point of the driver. | |
1791 | * Return value: | |
1792 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1793 | * file on failure. | |
1794 | */ | |
1795 | static int stmmac_open(struct net_device *dev) | |
1796 | { | |
1797 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1798 | int ret; |
1799 | ||
4bfcbd7a FV |
1800 | stmmac_check_ether_addr(priv); |
1801 | ||
3fe5cadb GC |
1802 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
1803 | priv->hw->pcs != STMMAC_PCS_TBI && | |
1804 | priv->hw->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1805 | ret = stmmac_init_phy(dev); |
1806 | if (ret) { | |
38ddc59d LC |
1807 | netdev_err(priv->dev, |
1808 | "%s: Cannot attach to PHY (error: %d)\n", | |
1809 | __func__, ret); | |
89df20d9 | 1810 | return ret; |
e58bb43f | 1811 | } |
f66ffe28 | 1812 | } |
47dd7a54 | 1813 | |
523f11b5 SK |
1814 | /* Extra statistics */ |
1815 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1816 | priv->xstats.threshold = tc; | |
1817 | ||
47dd7a54 | 1818 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); |
22ad3838 | 1819 | priv->rx_copybreak = STMMAC_RX_COPYBREAK; |
56329137 | 1820 | |
7262b7b2 | 1821 | ret = alloc_dma_desc_resources(priv); |
09f8d696 | 1822 | if (ret < 0) { |
38ddc59d LC |
1823 | netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", |
1824 | __func__); | |
09f8d696 SK |
1825 | goto dma_desc_error; |
1826 | } | |
1827 | ||
777da230 GC |
1828 | ret = init_dma_desc_rings(dev, GFP_KERNEL); |
1829 | if (ret < 0) { | |
38ddc59d LC |
1830 | netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", |
1831 | __func__); | |
777da230 GC |
1832 | goto init_error; |
1833 | } | |
1834 | ||
fe131929 | 1835 | ret = stmmac_hw_setup(dev, true); |
56329137 | 1836 | if (ret < 0) { |
38ddc59d | 1837 | netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); |
c9324d18 | 1838 | goto init_error; |
47dd7a54 GC |
1839 | } |
1840 | ||
777da230 GC |
1841 | stmmac_init_tx_coalesce(priv); |
1842 | ||
d6d50c7e PR |
1843 | if (dev->phydev) |
1844 | phy_start(dev->phydev); | |
47dd7a54 | 1845 | |
f66ffe28 GC |
1846 | /* Request the IRQ lines */ |
1847 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1848 | IRQF_SHARED, dev->name, dev); |
f66ffe28 | 1849 | if (unlikely(ret < 0)) { |
38ddc59d LC |
1850 | netdev_err(priv->dev, |
1851 | "%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1852 | __func__, dev->irq, ret); | |
c9324d18 | 1853 | goto init_error; |
f66ffe28 GC |
1854 | } |
1855 | ||
7a13f8f5 FV |
1856 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1857 | if (priv->wol_irq != dev->irq) { | |
1858 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1859 | IRQF_SHARED, dev->name, dev); | |
1860 | if (unlikely(ret < 0)) { | |
38ddc59d LC |
1861 | netdev_err(priv->dev, |
1862 | "%s: ERROR: allocating the WoL IRQ %d (%d)\n", | |
1863 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1864 | goto wolirq_error; |
7a13f8f5 FV |
1865 | } |
1866 | } | |
1867 | ||
d765955d | 1868 | /* Request the IRQ lines */ |
d7ec8584 | 1869 | if (priv->lpi_irq > 0) { |
d765955d GC |
1870 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1871 | dev->name, dev); | |
1872 | if (unlikely(ret < 0)) { | |
38ddc59d LC |
1873 | netdev_err(priv->dev, |
1874 | "%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1875 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1876 | goto lpiirq_error; |
d765955d GC |
1877 | } |
1878 | } | |
1879 | ||
47dd7a54 | 1880 | napi_enable(&priv->napi); |
47dd7a54 | 1881 | netif_start_queue(dev); |
f66ffe28 | 1882 | |
47dd7a54 | 1883 | return 0; |
f66ffe28 | 1884 | |
c9324d18 | 1885 | lpiirq_error: |
d765955d GC |
1886 | if (priv->wol_irq != dev->irq) |
1887 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1888 | wolirq_error: |
7a13f8f5 FV |
1889 | free_irq(dev->irq, dev); |
1890 | ||
c9324d18 GC |
1891 | init_error: |
1892 | free_dma_desc_resources(priv); | |
56329137 | 1893 | dma_desc_error: |
d6d50c7e PR |
1894 | if (dev->phydev) |
1895 | phy_disconnect(dev->phydev); | |
4bfcbd7a | 1896 | |
f66ffe28 | 1897 | return ret; |
47dd7a54 GC |
1898 | } |
1899 | ||
1900 | /** | |
1901 | * stmmac_release - close entry point of the driver | |
1902 | * @dev : device pointer. | |
1903 | * Description: | |
1904 | * This is the stop entry point of the driver. | |
1905 | */ | |
1906 | static int stmmac_release(struct net_device *dev) | |
1907 | { | |
1908 | struct stmmac_priv *priv = netdev_priv(dev); | |
1909 | ||
d765955d GC |
1910 | if (priv->eee_enabled) |
1911 | del_timer_sync(&priv->eee_ctrl_timer); | |
1912 | ||
47dd7a54 | 1913 | /* Stop and disconnect the PHY */ |
d6d50c7e PR |
1914 | if (dev->phydev) { |
1915 | phy_stop(dev->phydev); | |
1916 | phy_disconnect(dev->phydev); | |
47dd7a54 GC |
1917 | } |
1918 | ||
1919 | netif_stop_queue(dev); | |
1920 | ||
47dd7a54 | 1921 | napi_disable(&priv->napi); |
47dd7a54 | 1922 | |
9125cdd1 GC |
1923 | del_timer_sync(&priv->txtimer); |
1924 | ||
47dd7a54 GC |
1925 | /* Free the IRQ lines */ |
1926 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1927 | if (priv->wol_irq != dev->irq) |
1928 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1929 | if (priv->lpi_irq > 0) |
d765955d | 1930 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1931 | |
1932 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1933 | priv->hw->dma->stop_tx(priv->ioaddr); |
1934 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1935 | |
1936 | /* Release and free the Rx/Tx resources */ | |
1937 | free_dma_desc_resources(priv); | |
1938 | ||
19449bfc | 1939 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1940 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1941 | |
1942 | netif_carrier_off(dev); | |
1943 | ||
50fb4f74 | 1944 | #ifdef CONFIG_DEBUG_FS |
466c5ac8 | 1945 | stmmac_exit_fs(dev); |
bfab27a1 | 1946 | #endif |
bfab27a1 | 1947 | |
92ba6888 RK |
1948 | stmmac_release_ptp(priv); |
1949 | ||
47dd7a54 GC |
1950 | return 0; |
1951 | } | |
1952 | ||
f748be53 AT |
1953 | /** |
1954 | * stmmac_tso_allocator - close entry point of the driver | |
1955 | * @priv: driver private structure | |
1956 | * @des: buffer start address | |
1957 | * @total_len: total length to fill in descriptors | |
1958 | * @last_segmant: condition for the last descriptor | |
1959 | * Description: | |
1960 | * This function fills descriptor and request new descriptors according to | |
1961 | * buffer length to fill | |
1962 | */ | |
1963 | static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, | |
1964 | int total_len, bool last_segment) | |
1965 | { | |
1966 | struct dma_desc *desc; | |
1967 | int tmp_len; | |
1968 | u32 buff_size; | |
1969 | ||
1970 | tmp_len = total_len; | |
1971 | ||
1972 | while (tmp_len > 0) { | |
1973 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
1974 | desc = priv->dma_tx + priv->cur_tx; | |
1975 | ||
f8be0d78 | 1976 | desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); |
f748be53 AT |
1977 | buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? |
1978 | TSO_MAX_BUFF_SIZE : tmp_len; | |
1979 | ||
1980 | priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, | |
1981 | 0, 1, | |
1982 | (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), | |
1983 | 0, 0); | |
1984 | ||
1985 | tmp_len -= TSO_MAX_BUFF_SIZE; | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | /** | |
1990 | * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) | |
1991 | * @skb : the socket buffer | |
1992 | * @dev : device pointer | |
1993 | * Description: this is the transmit function that is called on TSO frames | |
1994 | * (support available on GMAC4 and newer chips). | |
1995 | * Diagram below show the ring programming in case of TSO frames: | |
1996 | * | |
1997 | * First Descriptor | |
1998 | * -------- | |
1999 | * | DES0 |---> buffer1 = L2/L3/L4 header | |
2000 | * | DES1 |---> TCP Payload (can continue on next descr...) | |
2001 | * | DES2 |---> buffer 1 and 2 len | |
2002 | * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] | |
2003 | * -------- | |
2004 | * | | |
2005 | * ... | |
2006 | * | | |
2007 | * -------- | |
2008 | * | DES0 | --| Split TCP Payload on Buffers 1 and 2 | |
2009 | * | DES1 | --| | |
2010 | * | DES2 | --> buffer 1 and 2 len | |
2011 | * | DES3 | | |
2012 | * -------- | |
2013 | * | |
2014 | * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. | |
2015 | */ | |
2016 | static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) | |
2017 | { | |
2018 | u32 pay_len, mss; | |
2019 | int tmp_pay_len = 0; | |
2020 | struct stmmac_priv *priv = netdev_priv(dev); | |
2021 | int nfrags = skb_shinfo(skb)->nr_frags; | |
2022 | unsigned int first_entry, des; | |
2023 | struct dma_desc *desc, *first, *mss_desc = NULL; | |
2024 | u8 proto_hdr_len; | |
2025 | int i; | |
2026 | ||
f748be53 AT |
2027 | /* Compute header lengths */ |
2028 | proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2029 | ||
2030 | /* Desc availability based on threshold should be enough safe */ | |
2031 | if (unlikely(stmmac_tx_avail(priv) < | |
2032 | (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { | |
2033 | if (!netif_queue_stopped(dev)) { | |
2034 | netif_stop_queue(dev); | |
2035 | /* This is a hard error, log it. */ | |
38ddc59d LC |
2036 | netdev_err(priv->dev, |
2037 | "%s: Tx Ring full when queue awake\n", | |
2038 | __func__); | |
f748be53 | 2039 | } |
f748be53 AT |
2040 | return NETDEV_TX_BUSY; |
2041 | } | |
2042 | ||
2043 | pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ | |
2044 | ||
2045 | mss = skb_shinfo(skb)->gso_size; | |
2046 | ||
2047 | /* set new MSS value if needed */ | |
2048 | if (mss != priv->mss) { | |
2049 | mss_desc = priv->dma_tx + priv->cur_tx; | |
2050 | priv->hw->desc->set_mss(mss_desc, mss); | |
2051 | priv->mss = mss; | |
2052 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
2053 | } | |
2054 | ||
2055 | if (netif_msg_tx_queued(priv)) { | |
2056 | pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", | |
2057 | __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); | |
2058 | pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, | |
2059 | skb->data_len); | |
2060 | } | |
2061 | ||
2062 | first_entry = priv->cur_tx; | |
2063 | ||
2064 | desc = priv->dma_tx + first_entry; | |
2065 | first = desc; | |
2066 | ||
2067 | /* first descriptor: fill Headers on Buf1 */ | |
2068 | des = dma_map_single(priv->device, skb->data, skb_headlen(skb), | |
2069 | DMA_TO_DEVICE); | |
2070 | if (dma_mapping_error(priv->device, des)) | |
2071 | goto dma_map_err; | |
2072 | ||
2073 | priv->tx_skbuff_dma[first_entry].buf = des; | |
2074 | priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); | |
2075 | priv->tx_skbuff[first_entry] = skb; | |
2076 | ||
f8be0d78 | 2077 | first->des0 = cpu_to_le32(des); |
f748be53 AT |
2078 | |
2079 | /* Fill start of payload in buff2 of first descriptor */ | |
2080 | if (pay_len) | |
f8be0d78 | 2081 | first->des1 = cpu_to_le32(des + proto_hdr_len); |
f748be53 AT |
2082 | |
2083 | /* If needed take extra descriptors to fill the remaining payload */ | |
2084 | tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; | |
2085 | ||
2086 | stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); | |
2087 | ||
2088 | /* Prepare fragments */ | |
2089 | for (i = 0; i < nfrags; i++) { | |
2090 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2091 | ||
2092 | des = skb_frag_dma_map(priv->device, frag, 0, | |
2093 | skb_frag_size(frag), | |
2094 | DMA_TO_DEVICE); | |
2095 | ||
2096 | stmmac_tso_allocator(priv, des, skb_frag_size(frag), | |
2097 | (i == nfrags - 1)); | |
2098 | ||
2099 | priv->tx_skbuff_dma[priv->cur_tx].buf = des; | |
2100 | priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); | |
2101 | priv->tx_skbuff[priv->cur_tx] = NULL; | |
2102 | priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; | |
2103 | } | |
2104 | ||
2105 | priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; | |
2106 | ||
2107 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
2108 | ||
2109 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
b3e51069 LC |
2110 | netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
2111 | __func__); | |
f748be53 AT |
2112 | netif_stop_queue(dev); |
2113 | } | |
2114 | ||
2115 | dev->stats.tx_bytes += skb->len; | |
2116 | priv->xstats.tx_tso_frames++; | |
2117 | priv->xstats.tx_tso_nfrags += nfrags; | |
2118 | ||
2119 | /* Manage tx mitigation */ | |
2120 | priv->tx_count_frames += nfrags + 1; | |
2121 | if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { | |
2122 | mod_timer(&priv->txtimer, | |
2123 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2124 | } else { | |
2125 | priv->tx_count_frames = 0; | |
2126 | priv->hw->desc->set_tx_ic(desc); | |
2127 | priv->xstats.tx_set_ic_bit++; | |
2128 | } | |
2129 | ||
2130 | if (!priv->hwts_tx_en) | |
2131 | skb_tx_timestamp(skb); | |
2132 | ||
2133 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2134 | priv->hwts_tx_en)) { | |
2135 | /* declare that device is doing timestamping */ | |
2136 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2137 | priv->hw->desc->enable_tx_timestamp(first); | |
2138 | } | |
2139 | ||
2140 | /* Complete the first descriptor before granting the DMA */ | |
2141 | priv->hw->desc->prepare_tso_tx_desc(first, 1, | |
2142 | proto_hdr_len, | |
2143 | pay_len, | |
2144 | 1, priv->tx_skbuff_dma[first_entry].last_segment, | |
2145 | tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); | |
2146 | ||
2147 | /* If context desc is used to change MSS */ | |
2148 | if (mss_desc) | |
2149 | priv->hw->desc->set_tx_owner(mss_desc); | |
2150 | ||
2151 | /* The own bit must be the latest setting done when prepare the | |
2152 | * descriptor and then barrier is needed to make sure that | |
2153 | * all is coherent before granting the DMA engine. | |
2154 | */ | |
ad688cdb | 2155 | dma_wmb(); |
f748be53 AT |
2156 | |
2157 | if (netif_msg_pktdata(priv)) { | |
2158 | pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", | |
2159 | __func__, priv->cur_tx, priv->dirty_tx, first_entry, | |
2160 | priv->cur_tx, first, nfrags); | |
2161 | ||
2162 | priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, | |
2163 | 0); | |
2164 | ||
2165 | pr_info(">>> frame to be transmitted: "); | |
2166 | print_pkt(skb->data, skb_headlen(skb)); | |
2167 | } | |
2168 | ||
2169 | netdev_sent_queue(dev, skb->len); | |
2170 | ||
2171 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
2172 | STMMAC_CHAN0); | |
2173 | ||
f748be53 AT |
2174 | return NETDEV_TX_OK; |
2175 | ||
2176 | dma_map_err: | |
f748be53 AT |
2177 | dev_err(priv->device, "Tx dma map failed\n"); |
2178 | dev_kfree_skb(skb); | |
2179 | priv->dev->stats.tx_dropped++; | |
2180 | return NETDEV_TX_OK; | |
2181 | } | |
2182 | ||
47dd7a54 | 2183 | /** |
732fdf0e | 2184 | * stmmac_xmit - Tx entry point of the driver |
47dd7a54 GC |
2185 | * @skb : the socket buffer |
2186 | * @dev : device pointer | |
32ceabca GC |
2187 | * Description : this is the tx entry point of the driver. |
2188 | * It programs the chain or the ring and supports oversized frames | |
2189 | * and SG feature. | |
47dd7a54 GC |
2190 | */ |
2191 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
2192 | { | |
2193 | struct stmmac_priv *priv = netdev_priv(dev); | |
0e80bdc9 | 2194 | unsigned int nopaged_len = skb_headlen(skb); |
4a7d666a | 2195 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 | 2196 | int nfrags = skb_shinfo(skb)->nr_frags; |
0e80bdc9 | 2197 | unsigned int entry, first_entry; |
47dd7a54 | 2198 | struct dma_desc *desc, *first; |
0e80bdc9 | 2199 | unsigned int enh_desc; |
f748be53 AT |
2200 | unsigned int des; |
2201 | ||
2202 | /* Manage oversized TCP frames for GMAC4 device */ | |
2203 | if (skb_is_gso(skb) && priv->tso) { | |
2204 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) | |
2205 | return stmmac_tso_xmit(skb, dev); | |
2206 | } | |
47dd7a54 GC |
2207 | |
2208 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
2209 | if (!netif_queue_stopped(dev)) { | |
2210 | netif_stop_queue(dev); | |
2211 | /* This is a hard error, log it. */ | |
38ddc59d LC |
2212 | netdev_err(priv->dev, |
2213 | "%s: Tx Ring full when queue awake\n", | |
2214 | __func__); | |
47dd7a54 GC |
2215 | } |
2216 | return NETDEV_TX_BUSY; | |
2217 | } | |
2218 | ||
d765955d GC |
2219 | if (priv->tx_path_in_lpi_mode) |
2220 | stmmac_disable_eee_mode(priv); | |
2221 | ||
e3ad57c9 | 2222 | entry = priv->cur_tx; |
0e80bdc9 | 2223 | first_entry = entry; |
47dd7a54 | 2224 | |
5e982f3b | 2225 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 2226 | |
0e80bdc9 | 2227 | if (likely(priv->extend_desc)) |
ceb69499 | 2228 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2229 | else |
2230 | desc = priv->dma_tx + entry; | |
2231 | ||
47dd7a54 GC |
2232 | first = desc; |
2233 | ||
0e80bdc9 GC |
2234 | priv->tx_skbuff[first_entry] = skb; |
2235 | ||
2236 | enh_desc = priv->plat->enh_desc; | |
4a7d666a | 2237 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
2238 | if (enh_desc) |
2239 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
2240 | ||
f748be53 AT |
2241 | if (unlikely(is_jumbo) && likely(priv->synopsys_id < |
2242 | DWMAC_CORE_4_00)) { | |
29896a67 | 2243 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
2244 | if (unlikely(entry < 0)) |
2245 | goto dma_map_err; | |
29896a67 | 2246 | } |
47dd7a54 GC |
2247 | |
2248 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
2249 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2250 | int len = skb_frag_size(frag); | |
be434d50 | 2251 | bool last_segment = (i == (nfrags - 1)); |
47dd7a54 | 2252 | |
e3ad57c9 GC |
2253 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2254 | ||
0e80bdc9 | 2255 | if (likely(priv->extend_desc)) |
ceb69499 | 2256 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2257 | else |
2258 | desc = priv->dma_tx + entry; | |
47dd7a54 | 2259 | |
f748be53 AT |
2260 | des = skb_frag_dma_map(priv->device, frag, 0, len, |
2261 | DMA_TO_DEVICE); | |
2262 | if (dma_mapping_error(priv->device, des)) | |
362b37be GC |
2263 | goto dma_map_err; /* should reuse desc w/o issues */ |
2264 | ||
0e80bdc9 | 2265 | priv->tx_skbuff[entry] = NULL; |
f748be53 | 2266 | |
f8be0d78 MW |
2267 | priv->tx_skbuff_dma[entry].buf = des; |
2268 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2269 | desc->des0 = cpu_to_le32(des); | |
2270 | else | |
2271 | desc->des2 = cpu_to_le32(des); | |
f748be53 | 2272 | |
362b37be | 2273 | priv->tx_skbuff_dma[entry].map_as_page = true; |
553e2ab3 | 2274 | priv->tx_skbuff_dma[entry].len = len; |
0e80bdc9 GC |
2275 | priv->tx_skbuff_dma[entry].last_segment = last_segment; |
2276 | ||
2277 | /* Prepare the descriptor and set the own bit too */ | |
4a7d666a | 2278 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
be434d50 | 2279 | priv->mode, 1, last_segment); |
47dd7a54 GC |
2280 | } |
2281 | ||
e3ad57c9 GC |
2282 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2283 | ||
2284 | priv->cur_tx = entry; | |
47dd7a54 | 2285 | |
47dd7a54 | 2286 | if (netif_msg_pktdata(priv)) { |
d0225e7d AT |
2287 | void *tx_head; |
2288 | ||
38ddc59d LC |
2289 | netdev_dbg(priv->dev, |
2290 | "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", | |
2291 | __func__, priv->cur_tx, priv->dirty_tx, first_entry, | |
2292 | entry, first, nfrags); | |
83d7af64 | 2293 | |
c24602ef | 2294 | if (priv->extend_desc) |
d0225e7d | 2295 | tx_head = (void *)priv->dma_etx; |
c24602ef | 2296 | else |
d0225e7d AT |
2297 | tx_head = (void *)priv->dma_tx; |
2298 | ||
2299 | priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); | |
c24602ef | 2300 | |
38ddc59d | 2301 | netdev_dbg(priv->dev, ">>> frame to be transmitted: "); |
47dd7a54 GC |
2302 | print_pkt(skb->data, skb->len); |
2303 | } | |
0e80bdc9 | 2304 | |
47dd7a54 | 2305 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
b3e51069 LC |
2306 | netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
2307 | __func__); | |
47dd7a54 GC |
2308 | netif_stop_queue(dev); |
2309 | } | |
2310 | ||
2311 | dev->stats.tx_bytes += skb->len; | |
2312 | ||
0e80bdc9 GC |
2313 | /* According to the coalesce parameter the IC bit for the latest |
2314 | * segment is reset and the timer re-started to clean the tx status. | |
2315 | * This approach takes care about the fragments: desc is the first | |
2316 | * element in case of no SG. | |
2317 | */ | |
2318 | priv->tx_count_frames += nfrags + 1; | |
2319 | if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { | |
2320 | mod_timer(&priv->txtimer, | |
2321 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2322 | } else { | |
2323 | priv->tx_count_frames = 0; | |
2324 | priv->hw->desc->set_tx_ic(desc); | |
2325 | priv->xstats.tx_set_ic_bit++; | |
891434b1 RK |
2326 | } |
2327 | ||
2328 | if (!priv->hwts_tx_en) | |
2329 | skb_tx_timestamp(skb); | |
3e82ce12 | 2330 | |
0e80bdc9 GC |
2331 | /* Ready to fill the first descriptor and set the OWN bit w/o any |
2332 | * problems because all the descriptors are actually ready to be | |
2333 | * passed to the DMA engine. | |
2334 | */ | |
2335 | if (likely(!is_jumbo)) { | |
2336 | bool last_segment = (nfrags == 0); | |
2337 | ||
f748be53 AT |
2338 | des = dma_map_single(priv->device, skb->data, |
2339 | nopaged_len, DMA_TO_DEVICE); | |
2340 | if (dma_mapping_error(priv->device, des)) | |
0e80bdc9 GC |
2341 | goto dma_map_err; |
2342 | ||
f8be0d78 MW |
2343 | priv->tx_skbuff_dma[first_entry].buf = des; |
2344 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2345 | first->des0 = cpu_to_le32(des); | |
2346 | else | |
2347 | first->des2 = cpu_to_le32(des); | |
f748be53 | 2348 | |
0e80bdc9 GC |
2349 | priv->tx_skbuff_dma[first_entry].len = nopaged_len; |
2350 | priv->tx_skbuff_dma[first_entry].last_segment = last_segment; | |
2351 | ||
2352 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2353 | priv->hwts_tx_en)) { | |
2354 | /* declare that device is doing timestamping */ | |
2355 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2356 | priv->hw->desc->enable_tx_timestamp(first); | |
2357 | } | |
2358 | ||
2359 | /* Prepare the first descriptor setting the OWN bit too */ | |
2360 | priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, | |
2361 | csum_insertion, priv->mode, 1, | |
2362 | last_segment); | |
2363 | ||
2364 | /* The own bit must be the latest setting done when prepare the | |
2365 | * descriptor and then barrier is needed to make sure that | |
2366 | * all is coherent before granting the DMA engine. | |
2367 | */ | |
ad688cdb | 2368 | dma_wmb(); |
0e80bdc9 GC |
2369 | } |
2370 | ||
38979574 | 2371 | netdev_sent_queue(dev, skb->len); |
f748be53 AT |
2372 | |
2373 | if (priv->synopsys_id < DWMAC_CORE_4_00) | |
2374 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); | |
2375 | else | |
2376 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
2377 | STMMAC_CHAN0); | |
52f64fae | 2378 | |
362b37be | 2379 | return NETDEV_TX_OK; |
a9097a96 | 2380 | |
362b37be | 2381 | dma_map_err: |
38ddc59d | 2382 | netdev_err(priv->dev, "Tx DMA map failed\n"); |
362b37be GC |
2383 | dev_kfree_skb(skb); |
2384 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2385 | return NETDEV_TX_OK; |
2386 | } | |
2387 | ||
b9381985 VB |
2388 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2389 | { | |
2390 | struct ethhdr *ehdr; | |
2391 | u16 vlanid; | |
2392 | ||
2393 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2394 | NETIF_F_HW_VLAN_CTAG_RX && | |
2395 | !__vlan_get_tag(skb, &vlanid)) { | |
2396 | /* pop the vlan tag */ | |
2397 | ehdr = (struct ethhdr *)skb->data; | |
2398 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2399 | skb_pull(skb, VLAN_HLEN); | |
2400 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | ||
120e87f9 GC |
2405 | static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) |
2406 | { | |
2407 | if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) | |
2408 | return 0; | |
2409 | ||
2410 | return 1; | |
2411 | } | |
2412 | ||
32ceabca | 2413 | /** |
732fdf0e | 2414 | * stmmac_rx_refill - refill used skb preallocated buffers |
32ceabca GC |
2415 | * @priv: driver private structure |
2416 | * Description : this is to reallocate the skb for the reception process | |
2417 | * that is based on zero-copy. | |
2418 | */ | |
47dd7a54 GC |
2419 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2420 | { | |
47dd7a54 | 2421 | int bfsize = priv->dma_buf_sz; |
e3ad57c9 GC |
2422 | unsigned int entry = priv->dirty_rx; |
2423 | int dirty = stmmac_rx_dirty(priv); | |
47dd7a54 | 2424 | |
e3ad57c9 | 2425 | while (dirty-- > 0) { |
c24602ef GC |
2426 | struct dma_desc *p; |
2427 | ||
2428 | if (priv->extend_desc) | |
ceb69499 | 2429 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2430 | else |
2431 | p = priv->dma_rx + entry; | |
2432 | ||
47dd7a54 GC |
2433 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2434 | struct sk_buff *skb; | |
2435 | ||
acb600de | 2436 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
120e87f9 GC |
2437 | if (unlikely(!skb)) { |
2438 | /* so for a while no zero-copy! */ | |
2439 | priv->rx_zeroc_thresh = STMMAC_RX_THRESH; | |
2440 | if (unlikely(net_ratelimit())) | |
2441 | dev_err(priv->device, | |
2442 | "fail to alloc skb entry %d\n", | |
2443 | entry); | |
47dd7a54 | 2444 | break; |
120e87f9 | 2445 | } |
47dd7a54 GC |
2446 | |
2447 | priv->rx_skbuff[entry] = skb; | |
2448 | priv->rx_skbuff_dma[entry] = | |
2449 | dma_map_single(priv->device, skb->data, bfsize, | |
2450 | DMA_FROM_DEVICE); | |
362b37be GC |
2451 | if (dma_mapping_error(priv->device, |
2452 | priv->rx_skbuff_dma[entry])) { | |
38ddc59d | 2453 | netdev_err(priv->dev, "Rx DMA map failed\n"); |
362b37be GC |
2454 | dev_kfree_skb(skb); |
2455 | break; | |
2456 | } | |
286a8372 | 2457 | |
f748be53 | 2458 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { |
f8be0d78 | 2459 | p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]); |
f748be53 AT |
2460 | p->des1 = 0; |
2461 | } else { | |
f8be0d78 | 2462 | p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]); |
f748be53 AT |
2463 | } |
2464 | if (priv->hw->mode->refill_desc3) | |
2465 | priv->hw->mode->refill_desc3(priv, p); | |
286a8372 | 2466 | |
120e87f9 GC |
2467 | if (priv->rx_zeroc_thresh > 0) |
2468 | priv->rx_zeroc_thresh--; | |
2469 | ||
b3e51069 LC |
2470 | netif_dbg(priv, rx_status, priv->dev, |
2471 | "refill entry #%d\n", entry); | |
47dd7a54 | 2472 | } |
ad688cdb | 2473 | dma_wmb(); |
f748be53 AT |
2474 | |
2475 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2476 | priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); | |
2477 | else | |
2478 | priv->hw->desc->set_rx_owner(p); | |
2479 | ||
ad688cdb | 2480 | dma_wmb(); |
e3ad57c9 GC |
2481 | |
2482 | entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); | |
47dd7a54 | 2483 | } |
e3ad57c9 | 2484 | priv->dirty_rx = entry; |
47dd7a54 GC |
2485 | } |
2486 | ||
32ceabca | 2487 | /** |
732fdf0e | 2488 | * stmmac_rx - manage the receive process |
32ceabca GC |
2489 | * @priv: driver private structure |
2490 | * @limit: napi bugget. | |
2491 | * Description : this the function called by the napi poll method. | |
2492 | * It gets all the frames inside the ring. | |
2493 | */ | |
47dd7a54 GC |
2494 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2495 | { | |
e3ad57c9 | 2496 | unsigned int entry = priv->cur_rx; |
47dd7a54 GC |
2497 | unsigned int next_entry; |
2498 | unsigned int count = 0; | |
d2afb5bd | 2499 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2500 | |
83d7af64 | 2501 | if (netif_msg_rx_status(priv)) { |
d0225e7d AT |
2502 | void *rx_head; |
2503 | ||
38ddc59d | 2504 | netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); |
c24602ef | 2505 | if (priv->extend_desc) |
d0225e7d | 2506 | rx_head = (void *)priv->dma_erx; |
c24602ef | 2507 | else |
d0225e7d AT |
2508 | rx_head = (void *)priv->dma_rx; |
2509 | ||
2510 | priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); | |
47dd7a54 | 2511 | } |
c24602ef | 2512 | while (count < limit) { |
47dd7a54 | 2513 | int status; |
9401bb5c | 2514 | struct dma_desc *p; |
ba1ffd74 | 2515 | struct dma_desc *np; |
47dd7a54 | 2516 | |
c24602ef | 2517 | if (priv->extend_desc) |
ceb69499 | 2518 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2519 | else |
ceb69499 | 2520 | p = priv->dma_rx + entry; |
c24602ef | 2521 | |
c1fa3212 FG |
2522 | /* read the status of the incoming frame */ |
2523 | status = priv->hw->desc->rx_status(&priv->dev->stats, | |
2524 | &priv->xstats, p); | |
2525 | /* check if managed by the DMA otherwise go ahead */ | |
2526 | if (unlikely(status & dma_own)) | |
47dd7a54 GC |
2527 | break; |
2528 | ||
2529 | count++; | |
2530 | ||
e3ad57c9 GC |
2531 | priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); |
2532 | next_entry = priv->cur_rx; | |
2533 | ||
c24602ef | 2534 | if (priv->extend_desc) |
ba1ffd74 | 2535 | np = (struct dma_desc *)(priv->dma_erx + next_entry); |
c24602ef | 2536 | else |
ba1ffd74 GC |
2537 | np = priv->dma_rx + next_entry; |
2538 | ||
2539 | prefetch(np); | |
47dd7a54 | 2540 | |
c24602ef GC |
2541 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) |
2542 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2543 | &priv->xstats, | |
2544 | priv->dma_erx + | |
2545 | entry); | |
891434b1 | 2546 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2547 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2548 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2549 | /* DESC2 & DESC3 will be overwitten by device | |
2550 | * with timestamp value, hence reinitialize | |
2551 | * them in stmmac_rx_refill() function so that | |
2552 | * device can reuse it. | |
2553 | */ | |
2554 | priv->rx_skbuff[entry] = NULL; | |
2555 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2556 | priv->rx_skbuff_dma[entry], |
2557 | priv->dma_buf_sz, | |
2558 | DMA_FROM_DEVICE); | |
891434b1 RK |
2559 | } |
2560 | } else { | |
47dd7a54 | 2561 | struct sk_buff *skb; |
3eeb2997 | 2562 | int frame_len; |
f748be53 AT |
2563 | unsigned int des; |
2564 | ||
2565 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
f8be0d78 | 2566 | des = le32_to_cpu(p->des0); |
f748be53 | 2567 | else |
f8be0d78 | 2568 | des = le32_to_cpu(p->des2); |
47dd7a54 | 2569 | |
ceb69499 GC |
2570 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2571 | ||
f748be53 AT |
2572 | /* If frame length is greather than skb buffer size |
2573 | * (preallocated during init) then the packet is | |
2574 | * ignored | |
2575 | */ | |
e527c4a7 | 2576 | if (frame_len > priv->dma_buf_sz) { |
38ddc59d LC |
2577 | netdev_err(priv->dev, |
2578 | "len %d larger than size (%d)\n", | |
2579 | frame_len, priv->dma_buf_sz); | |
e527c4a7 GC |
2580 | priv->dev->stats.rx_length_errors++; |
2581 | break; | |
2582 | } | |
2583 | ||
3eeb2997 | 2584 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2585 | * Type frames (LLC/LLC-SNAP) |
2586 | */ | |
3eeb2997 GC |
2587 | if (unlikely(status != llc_snap)) |
2588 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2589 | |
83d7af64 | 2590 | if (netif_msg_rx_status(priv)) { |
38ddc59d LC |
2591 | netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", |
2592 | p, entry, des); | |
83d7af64 | 2593 | if (frame_len > ETH_FRAME_LEN) |
38ddc59d LC |
2594 | netdev_dbg(priv->dev, "frame size %d, COE: %d\n", |
2595 | frame_len, status); | |
83d7af64 | 2596 | } |
22ad3838 | 2597 | |
f748be53 AT |
2598 | /* The zero-copy is always used for all the sizes |
2599 | * in case of GMAC4 because it needs | |
2600 | * to refill the used descriptors, always. | |
2601 | */ | |
2602 | if (unlikely(!priv->plat->has_gmac4 && | |
2603 | ((frame_len < priv->rx_copybreak) || | |
2604 | stmmac_rx_threshold_count(priv)))) { | |
22ad3838 GC |
2605 | skb = netdev_alloc_skb_ip_align(priv->dev, |
2606 | frame_len); | |
2607 | if (unlikely(!skb)) { | |
2608 | if (net_ratelimit()) | |
2609 | dev_warn(priv->device, | |
2610 | "packet dropped\n"); | |
2611 | priv->dev->stats.rx_dropped++; | |
2612 | break; | |
2613 | } | |
2614 | ||
2615 | dma_sync_single_for_cpu(priv->device, | |
2616 | priv->rx_skbuff_dma | |
2617 | [entry], frame_len, | |
2618 | DMA_FROM_DEVICE); | |
2619 | skb_copy_to_linear_data(skb, | |
2620 | priv-> | |
2621 | rx_skbuff[entry]->data, | |
2622 | frame_len); | |
2623 | ||
2624 | skb_put(skb, frame_len); | |
2625 | dma_sync_single_for_device(priv->device, | |
2626 | priv->rx_skbuff_dma | |
2627 | [entry], frame_len, | |
2628 | DMA_FROM_DEVICE); | |
2629 | } else { | |
2630 | skb = priv->rx_skbuff[entry]; | |
2631 | if (unlikely(!skb)) { | |
38ddc59d LC |
2632 | netdev_err(priv->dev, |
2633 | "%s: Inconsistent Rx chain\n", | |
2634 | priv->dev->name); | |
22ad3838 GC |
2635 | priv->dev->stats.rx_dropped++; |
2636 | break; | |
2637 | } | |
2638 | prefetch(skb->data - NET_IP_ALIGN); | |
2639 | priv->rx_skbuff[entry] = NULL; | |
120e87f9 | 2640 | priv->rx_zeroc_thresh++; |
22ad3838 GC |
2641 | |
2642 | skb_put(skb, frame_len); | |
2643 | dma_unmap_single(priv->device, | |
2644 | priv->rx_skbuff_dma[entry], | |
2645 | priv->dma_buf_sz, | |
2646 | DMA_FROM_DEVICE); | |
47dd7a54 | 2647 | } |
47dd7a54 | 2648 | |
47dd7a54 | 2649 | if (netif_msg_pktdata(priv)) { |
38ddc59d LC |
2650 | netdev_dbg(priv->dev, "frame received (%dbytes)", |
2651 | frame_len); | |
47dd7a54 GC |
2652 | print_pkt(skb->data, frame_len); |
2653 | } | |
83d7af64 | 2654 | |
ba1ffd74 GC |
2655 | stmmac_get_rx_hwtstamp(priv, p, np, skb); |
2656 | ||
b9381985 VB |
2657 | stmmac_rx_vlan(priv->dev, skb); |
2658 | ||
47dd7a54 GC |
2659 | skb->protocol = eth_type_trans(skb, priv->dev); |
2660 | ||
ceb69499 | 2661 | if (unlikely(!coe)) |
bc8acf2c | 2662 | skb_checksum_none_assert(skb); |
62a2ab93 | 2663 | else |
47dd7a54 | 2664 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2665 | |
2666 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2667 | |
2668 | priv->dev->stats.rx_packets++; | |
2669 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2670 | } |
2671 | entry = next_entry; | |
47dd7a54 GC |
2672 | } |
2673 | ||
2674 | stmmac_rx_refill(priv); | |
2675 | ||
2676 | priv->xstats.rx_pkt_n += count; | |
2677 | ||
2678 | return count; | |
2679 | } | |
2680 | ||
2681 | /** | |
2682 | * stmmac_poll - stmmac poll method (NAPI) | |
2683 | * @napi : pointer to the napi structure. | |
2684 | * @budget : maximum number of packets that the current CPU can receive from | |
2685 | * all interfaces. | |
2686 | * Description : | |
9125cdd1 | 2687 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2688 | */ |
2689 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2690 | { | |
2691 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2692 | int work_done = 0; | |
2693 | ||
9125cdd1 GC |
2694 | priv->xstats.napi_poll++; |
2695 | stmmac_tx_clean(priv); | |
47dd7a54 | 2696 | |
9125cdd1 | 2697 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2698 | if (work_done < budget) { |
2699 | napi_complete(napi); | |
9125cdd1 | 2700 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2701 | } |
2702 | return work_done; | |
2703 | } | |
2704 | ||
2705 | /** | |
2706 | * stmmac_tx_timeout | |
2707 | * @dev : Pointer to net device structure | |
2708 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2709 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2710 | * netdev structure and arrange for the device to be reset to a sane state |
2711 | * in order to transmit a new packet. | |
2712 | */ | |
2713 | static void stmmac_tx_timeout(struct net_device *dev) | |
2714 | { | |
2715 | struct stmmac_priv *priv = netdev_priv(dev); | |
2716 | ||
2717 | /* Clear Tx resources and restart transmitting again */ | |
2718 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2719 | } |
2720 | ||
47dd7a54 | 2721 | /** |
01789349 | 2722 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2723 | * @dev : pointer to the device structure |
2724 | * Description: | |
2725 | * This function is a driver entry point which gets called by the kernel | |
2726 | * whenever multicast addresses must be enabled/disabled. | |
2727 | * Return value: | |
2728 | * void. | |
2729 | */ | |
01789349 | 2730 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2731 | { |
2732 | struct stmmac_priv *priv = netdev_priv(dev); | |
2733 | ||
3b57de95 | 2734 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 GC |
2735 | } |
2736 | ||
2737 | /** | |
2738 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2739 | * @dev : device pointer. | |
2740 | * @new_mtu : the new MTU size for the device. | |
2741 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2742 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2743 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2744 | * Return value: | |
2745 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2746 | * file on failure. | |
2747 | */ | |
2748 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2749 | { | |
38ddc59d LC |
2750 | struct stmmac_priv *priv = netdev_priv(dev); |
2751 | ||
47dd7a54 | 2752 | if (netif_running(dev)) { |
38ddc59d | 2753 | netdev_err(priv->dev, "must be stopped to change its MTU\n"); |
47dd7a54 GC |
2754 | return -EBUSY; |
2755 | } | |
2756 | ||
5e982f3b | 2757 | dev->mtu = new_mtu; |
f748be53 | 2758 | |
5e982f3b MM |
2759 | netdev_update_features(dev); |
2760 | ||
2761 | return 0; | |
2762 | } | |
2763 | ||
c8f44aff | 2764 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2765 | netdev_features_t features) |
5e982f3b MM |
2766 | { |
2767 | struct stmmac_priv *priv = netdev_priv(dev); | |
2768 | ||
38912bdb | 2769 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2770 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2771 | |
5e982f3b | 2772 | if (!priv->plat->tx_coe) |
a188222b | 2773 | features &= ~NETIF_F_CSUM_MASK; |
5e982f3b | 2774 | |
ebbb293f GC |
2775 | /* Some GMAC devices have a bugged Jumbo frame support that |
2776 | * needs to have the Tx COE disabled for oversized frames | |
2777 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2778 | * the TX csum insertionin the TDES and not use SF. |
2779 | */ | |
5e982f3b | 2780 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
a188222b | 2781 | features &= ~NETIF_F_CSUM_MASK; |
ebbb293f | 2782 | |
f748be53 AT |
2783 | /* Disable tso if asked by ethtool */ |
2784 | if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { | |
2785 | if (features & NETIF_F_TSO) | |
2786 | priv->tso = true; | |
2787 | else | |
2788 | priv->tso = false; | |
2789 | } | |
2790 | ||
5e982f3b | 2791 | return features; |
47dd7a54 GC |
2792 | } |
2793 | ||
d2afb5bd GC |
2794 | static int stmmac_set_features(struct net_device *netdev, |
2795 | netdev_features_t features) | |
2796 | { | |
2797 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2798 | ||
2799 | /* Keep the COE Type in case of csum is supporting */ | |
2800 | if (features & NETIF_F_RXCSUM) | |
2801 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2802 | else | |
2803 | priv->hw->rx_csum = 0; | |
2804 | /* No check needed because rx_coe has been set before and it will be | |
2805 | * fixed in case of issue. | |
2806 | */ | |
2807 | priv->hw->mac->rx_ipc(priv->hw); | |
2808 | ||
2809 | return 0; | |
2810 | } | |
2811 | ||
32ceabca GC |
2812 | /** |
2813 | * stmmac_interrupt - main ISR | |
2814 | * @irq: interrupt number. | |
2815 | * @dev_id: to pass the net device pointer. | |
2816 | * Description: this is the main driver interrupt service routine. | |
732fdf0e GC |
2817 | * It can call: |
2818 | * o DMA service routine (to manage incoming frame reception and transmission | |
2819 | * status) | |
2820 | * o Core interrupts to manage: remote wake-up, management counter, LPI | |
2821 | * interrupts. | |
32ceabca | 2822 | */ |
47dd7a54 GC |
2823 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2824 | { | |
2825 | struct net_device *dev = (struct net_device *)dev_id; | |
2826 | struct stmmac_priv *priv = netdev_priv(dev); | |
2827 | ||
89f7f2cf SK |
2828 | if (priv->irq_wake) |
2829 | pm_wakeup_event(priv->device, 0); | |
2830 | ||
47dd7a54 | 2831 | if (unlikely(!dev)) { |
38ddc59d | 2832 | netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); |
47dd7a54 GC |
2833 | return IRQ_NONE; |
2834 | } | |
2835 | ||
d765955d | 2836 | /* To handle GMAC own interrupts */ |
f748be53 | 2837 | if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { |
7ed24bbe | 2838 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2839 | &priv->xstats); |
d765955d | 2840 | if (unlikely(status)) { |
d765955d | 2841 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2842 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2843 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2844 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2845 | priv->tx_path_in_lpi_mode = false; |
a8b7d770 | 2846 | if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) |
f748be53 AT |
2847 | priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, |
2848 | priv->rx_tail_addr, | |
2849 | STMMAC_CHAN0); | |
d765955d | 2850 | } |
70523e63 GC |
2851 | |
2852 | /* PCS link status */ | |
3fe5cadb | 2853 | if (priv->hw->pcs) { |
70523e63 GC |
2854 | if (priv->xstats.pcs_link) |
2855 | netif_carrier_on(dev); | |
2856 | else | |
2857 | netif_carrier_off(dev); | |
2858 | } | |
d765955d | 2859 | } |
aec7ff27 | 2860 | |
d765955d | 2861 | /* To handle DMA interrupts */ |
aec7ff27 | 2862 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2863 | |
2864 | return IRQ_HANDLED; | |
2865 | } | |
2866 | ||
2867 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2868 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2869 | * to allow network I/O with interrupts disabled. |
2870 | */ | |
47dd7a54 GC |
2871 | static void stmmac_poll_controller(struct net_device *dev) |
2872 | { | |
2873 | disable_irq(dev->irq); | |
2874 | stmmac_interrupt(dev->irq, dev); | |
2875 | enable_irq(dev->irq); | |
2876 | } | |
2877 | #endif | |
2878 | ||
2879 | /** | |
2880 | * stmmac_ioctl - Entry point for the Ioctl | |
2881 | * @dev: Device pointer. | |
2882 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2883 | * a proprietary structure used to pass information to the driver. | |
2884 | * @cmd: IOCTL command | |
2885 | * Description: | |
32ceabca | 2886 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2887 | */ |
2888 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2889 | { | |
891434b1 | 2890 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2891 | |
2892 | if (!netif_running(dev)) | |
2893 | return -EINVAL; | |
2894 | ||
891434b1 RK |
2895 | switch (cmd) { |
2896 | case SIOCGMIIPHY: | |
2897 | case SIOCGMIIREG: | |
2898 | case SIOCSMIIREG: | |
d6d50c7e | 2899 | if (!dev->phydev) |
891434b1 | 2900 | return -EINVAL; |
d6d50c7e | 2901 | ret = phy_mii_ioctl(dev->phydev, rq, cmd); |
891434b1 RK |
2902 | break; |
2903 | case SIOCSHWTSTAMP: | |
2904 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2905 | break; | |
2906 | default: | |
2907 | break; | |
2908 | } | |
28b04113 | 2909 | |
47dd7a54 GC |
2910 | return ret; |
2911 | } | |
2912 | ||
50fb4f74 | 2913 | #ifdef CONFIG_DEBUG_FS |
7ac29055 | 2914 | static struct dentry *stmmac_fs_dir; |
7ac29055 | 2915 | |
c24602ef | 2916 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2917 | struct seq_file *seq) |
7ac29055 | 2918 | { |
7ac29055 | 2919 | int i; |
ceb69499 GC |
2920 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2921 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2922 | |
c24602ef GC |
2923 | for (i = 0; i < size; i++) { |
2924 | u64 x; | |
2925 | if (extend_desc) { | |
2926 | x = *(u64 *) ep; | |
2927 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 | 2928 | i, (unsigned int)virt_to_phys(ep), |
f8be0d78 MW |
2929 | le32_to_cpu(ep->basic.des0), |
2930 | le32_to_cpu(ep->basic.des1), | |
2931 | le32_to_cpu(ep->basic.des2), | |
2932 | le32_to_cpu(ep->basic.des3)); | |
c24602ef GC |
2933 | ep++; |
2934 | } else { | |
2935 | x = *(u64 *) p; | |
2936 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 | 2937 | i, (unsigned int)virt_to_phys(ep), |
f8be0d78 MW |
2938 | le32_to_cpu(p->des0), le32_to_cpu(p->des1), |
2939 | le32_to_cpu(p->des2), le32_to_cpu(p->des3)); | |
c24602ef GC |
2940 | p++; |
2941 | } | |
7ac29055 GC |
2942 | seq_printf(seq, "\n"); |
2943 | } | |
c24602ef | 2944 | } |
7ac29055 | 2945 | |
c24602ef GC |
2946 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2947 | { | |
2948 | struct net_device *dev = seq->private; | |
2949 | struct stmmac_priv *priv = netdev_priv(dev); | |
7ac29055 | 2950 | |
c24602ef GC |
2951 | if (priv->extend_desc) { |
2952 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
e3ad57c9 | 2953 | sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); |
c24602ef | 2954 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
e3ad57c9 | 2955 | sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); |
c24602ef GC |
2956 | } else { |
2957 | seq_printf(seq, "RX descriptor ring:\n"); | |
e3ad57c9 | 2958 | sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); |
c24602ef | 2959 | seq_printf(seq, "TX descriptor ring:\n"); |
e3ad57c9 | 2960 | sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); |
7ac29055 GC |
2961 | } |
2962 | ||
2963 | return 0; | |
2964 | } | |
2965 | ||
2966 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2967 | { | |
2968 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2969 | } | |
2970 | ||
22d3efe5 PM |
2971 | /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */ |
2972 | ||
7ac29055 GC |
2973 | static const struct file_operations stmmac_rings_status_fops = { |
2974 | .owner = THIS_MODULE, | |
2975 | .open = stmmac_sysfs_ring_open, | |
2976 | .read = seq_read, | |
2977 | .llseek = seq_lseek, | |
74863948 | 2978 | .release = single_release, |
7ac29055 GC |
2979 | }; |
2980 | ||
e7434821 GC |
2981 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2982 | { | |
2983 | struct net_device *dev = seq->private; | |
2984 | struct stmmac_priv *priv = netdev_priv(dev); | |
2985 | ||
19e30c14 | 2986 | if (!priv->hw_cap_support) { |
e7434821 GC |
2987 | seq_printf(seq, "DMA HW features not supported\n"); |
2988 | return 0; | |
2989 | } | |
2990 | ||
2991 | seq_printf(seq, "==============================\n"); | |
2992 | seq_printf(seq, "\tDMA HW features\n"); | |
2993 | seq_printf(seq, "==============================\n"); | |
2994 | ||
22d3efe5 | 2995 | seq_printf(seq, "\t10/100 Mbps: %s\n", |
e7434821 | 2996 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); |
22d3efe5 | 2997 | seq_printf(seq, "\t1000 Mbps: %s\n", |
e7434821 | 2998 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); |
22d3efe5 | 2999 | seq_printf(seq, "\tHalf duplex: %s\n", |
e7434821 GC |
3000 | (priv->dma_cap.half_duplex) ? "Y" : "N"); |
3001 | seq_printf(seq, "\tHash Filter: %s\n", | |
3002 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
3003 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
3004 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
3005 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
3006 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
3007 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
3008 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
3009 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
3010 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
3011 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
3012 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
3013 | seq_printf(seq, "\tRMON module: %s\n", | |
3014 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
3015 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
3016 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
22d3efe5 | 3017 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", |
e7434821 | 3018 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); |
22d3efe5 | 3019 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", |
e7434821 GC |
3020 | (priv->dma_cap.eee) ? "Y" : "N"); |
3021 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
3022 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
3023 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
f748be53 AT |
3024 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
3025 | seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", | |
3026 | (priv->dma_cap.rx_coe) ? "Y" : "N"); | |
3027 | } else { | |
3028 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
3029 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
3030 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
3031 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
3032 | } | |
e7434821 GC |
3033 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", |
3034 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
3035 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
3036 | priv->dma_cap.number_rx_channel); | |
3037 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
3038 | priv->dma_cap.number_tx_channel); | |
3039 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
3040 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
3041 | ||
3042 | return 0; | |
3043 | } | |
3044 | ||
3045 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
3046 | { | |
3047 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
3048 | } | |
3049 | ||
3050 | static const struct file_operations stmmac_dma_cap_fops = { | |
3051 | .owner = THIS_MODULE, | |
3052 | .open = stmmac_sysfs_dma_cap_open, | |
3053 | .read = seq_read, | |
3054 | .llseek = seq_lseek, | |
74863948 | 3055 | .release = single_release, |
e7434821 GC |
3056 | }; |
3057 | ||
7ac29055 GC |
3058 | static int stmmac_init_fs(struct net_device *dev) |
3059 | { | |
466c5ac8 MO |
3060 | struct stmmac_priv *priv = netdev_priv(dev); |
3061 | ||
3062 | /* Create per netdev entries */ | |
3063 | priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); | |
7ac29055 | 3064 | |
466c5ac8 | 3065 | if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { |
38ddc59d | 3066 | netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); |
7ac29055 GC |
3067 | |
3068 | return -ENOMEM; | |
3069 | } | |
3070 | ||
3071 | /* Entry to report DMA RX/TX rings */ | |
466c5ac8 MO |
3072 | priv->dbgfs_rings_status = |
3073 | debugfs_create_file("descriptors_status", S_IRUGO, | |
3074 | priv->dbgfs_dir, dev, | |
3075 | &stmmac_rings_status_fops); | |
7ac29055 | 3076 | |
466c5ac8 | 3077 | if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { |
38ddc59d | 3078 | netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); |
466c5ac8 | 3079 | debugfs_remove_recursive(priv->dbgfs_dir); |
7ac29055 GC |
3080 | |
3081 | return -ENOMEM; | |
3082 | } | |
3083 | ||
e7434821 | 3084 | /* Entry to report the DMA HW features */ |
466c5ac8 MO |
3085 | priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, |
3086 | priv->dbgfs_dir, | |
3087 | dev, &stmmac_dma_cap_fops); | |
e7434821 | 3088 | |
466c5ac8 | 3089 | if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { |
38ddc59d | 3090 | netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); |
466c5ac8 | 3091 | debugfs_remove_recursive(priv->dbgfs_dir); |
e7434821 GC |
3092 | |
3093 | return -ENOMEM; | |
3094 | } | |
3095 | ||
7ac29055 GC |
3096 | return 0; |
3097 | } | |
3098 | ||
466c5ac8 | 3099 | static void stmmac_exit_fs(struct net_device *dev) |
7ac29055 | 3100 | { |
466c5ac8 MO |
3101 | struct stmmac_priv *priv = netdev_priv(dev); |
3102 | ||
3103 | debugfs_remove_recursive(priv->dbgfs_dir); | |
7ac29055 | 3104 | } |
50fb4f74 | 3105 | #endif /* CONFIG_DEBUG_FS */ |
7ac29055 | 3106 | |
47dd7a54 GC |
3107 | static const struct net_device_ops stmmac_netdev_ops = { |
3108 | .ndo_open = stmmac_open, | |
3109 | .ndo_start_xmit = stmmac_xmit, | |
3110 | .ndo_stop = stmmac_release, | |
3111 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 3112 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 3113 | .ndo_set_features = stmmac_set_features, |
01789349 | 3114 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
3115 | .ndo_tx_timeout = stmmac_tx_timeout, |
3116 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
3117 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3118 | .ndo_poll_controller = stmmac_poll_controller, | |
3119 | #endif | |
3120 | .ndo_set_mac_address = eth_mac_addr, | |
3121 | }; | |
3122 | ||
cf3f047b GC |
3123 | /** |
3124 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 3125 | * @priv: driver private structure |
732fdf0e GC |
3126 | * Description: this function is to configure the MAC device according to |
3127 | * some platform parameters or the HW capability register. It prepares the | |
3128 | * driver to use either ring or chain modes and to setup either enhanced or | |
3129 | * normal descriptors. | |
cf3f047b GC |
3130 | */ |
3131 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
3132 | { | |
cf3f047b GC |
3133 | struct mac_device_info *mac; |
3134 | ||
3135 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
3136 | if (priv->plat->has_gmac) { |
3137 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
3138 | mac = dwmac1000_setup(priv->ioaddr, |
3139 | priv->plat->multicast_filter_bins, | |
c623d149 AT |
3140 | priv->plat->unicast_filter_entries, |
3141 | &priv->synopsys_id); | |
f748be53 AT |
3142 | } else if (priv->plat->has_gmac4) { |
3143 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3144 | mac = dwmac4_setup(priv->ioaddr, | |
3145 | priv->plat->multicast_filter_bins, | |
3146 | priv->plat->unicast_filter_entries, | |
3147 | &priv->synopsys_id); | |
03f2eecd | 3148 | } else { |
c623d149 | 3149 | mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); |
03f2eecd | 3150 | } |
cf3f047b GC |
3151 | if (!mac) |
3152 | return -ENOMEM; | |
3153 | ||
3154 | priv->hw = mac; | |
3155 | ||
4a7d666a | 3156 | /* To use the chained or ring mode */ |
f748be53 AT |
3157 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
3158 | priv->hw->mode = &dwmac4_ring_mode_ops; | |
4a7d666a | 3159 | } else { |
f748be53 AT |
3160 | if (chain_mode) { |
3161 | priv->hw->mode = &chain_mode_ops; | |
38ddc59d | 3162 | dev_info(priv->device, "Chain mode enabled\n"); |
f748be53 AT |
3163 | priv->mode = STMMAC_CHAIN_MODE; |
3164 | } else { | |
3165 | priv->hw->mode = &ring_mode_ops; | |
38ddc59d | 3166 | dev_info(priv->device, "Ring mode enabled\n"); |
f748be53 AT |
3167 | priv->mode = STMMAC_RING_MODE; |
3168 | } | |
4a7d666a GC |
3169 | } |
3170 | ||
cf3f047b GC |
3171 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
3172 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
3173 | if (priv->hw_cap_support) { | |
38ddc59d | 3174 | dev_info(priv->device, "DMA HW capability register supported\n"); |
cf3f047b GC |
3175 | |
3176 | /* We can override some gmac/dma configuration fields: e.g. | |
3177 | * enh_desc, tx_coe (e.g. that are passed through the | |
3178 | * platform) with the values from the HW capability | |
3179 | * register (if supported). | |
3180 | */ | |
3181 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 3182 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
3fe5cadb | 3183 | priv->hw->pmt = priv->plat->pmt; |
38912bdb | 3184 | |
a8df35d4 EG |
3185 | /* TXCOE doesn't work in thresh DMA mode */ |
3186 | if (priv->plat->force_thresh_dma_mode) | |
3187 | priv->plat->tx_coe = 0; | |
3188 | else | |
3189 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
3190 | ||
f748be53 AT |
3191 | /* In case of GMAC4 rx_coe is from HW cap register. */ |
3192 | priv->plat->rx_coe = priv->dma_cap.rx_coe; | |
38912bdb DS |
3193 | |
3194 | if (priv->dma_cap.rx_coe_type2) | |
3195 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
3196 | else if (priv->dma_cap.rx_coe_type1) | |
3197 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
3198 | ||
38ddc59d LC |
3199 | } else { |
3200 | dev_info(priv->device, "No HW DMA feature register supported\n"); | |
3201 | } | |
cf3f047b | 3202 | |
f748be53 AT |
3203 | /* To use alternate (extended), normal or GMAC4 descriptor structures */ |
3204 | if (priv->synopsys_id >= DWMAC_CORE_4_00) | |
3205 | priv->hw->desc = &dwmac4_desc_ops; | |
3206 | else | |
3207 | stmmac_selec_desc_mode(priv); | |
61369d02 | 3208 | |
d2afb5bd GC |
3209 | if (priv->plat->rx_coe) { |
3210 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38ddc59d | 3211 | dev_info(priv->device, "RX Checksum Offload Engine supported\n"); |
f748be53 | 3212 | if (priv->synopsys_id < DWMAC_CORE_4_00) |
38ddc59d | 3213 | dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); |
d2afb5bd | 3214 | } |
cf3f047b | 3215 | if (priv->plat->tx_coe) |
38ddc59d | 3216 | dev_info(priv->device, "TX Checksum insertion supported\n"); |
cf3f047b GC |
3217 | |
3218 | if (priv->plat->pmt) { | |
38ddc59d | 3219 | dev_info(priv->device, "Wake-Up On Lan supported\n"); |
cf3f047b GC |
3220 | device_set_wakeup_capable(priv->device, 1); |
3221 | } | |
3222 | ||
f748be53 | 3223 | if (priv->dma_cap.tsoen) |
38ddc59d | 3224 | dev_info(priv->device, "TSO supported\n"); |
f748be53 | 3225 | |
c24602ef | 3226 | return 0; |
cf3f047b GC |
3227 | } |
3228 | ||
47dd7a54 | 3229 | /** |
bfab27a1 GC |
3230 | * stmmac_dvr_probe |
3231 | * @device: device pointer | |
ff3dd78c | 3232 | * @plat_dat: platform data pointer |
e56788cf | 3233 | * @res: stmmac resource pointer |
bfab27a1 GC |
3234 | * Description: this is the main probe function used to |
3235 | * call the alloc_etherdev, allocate the priv structure. | |
9afec6ef | 3236 | * Return: |
15ffac73 | 3237 | * returns 0 on success, otherwise errno. |
47dd7a54 | 3238 | */ |
15ffac73 JE |
3239 | int stmmac_dvr_probe(struct device *device, |
3240 | struct plat_stmmacenet_data *plat_dat, | |
3241 | struct stmmac_resources *res) | |
47dd7a54 GC |
3242 | { |
3243 | int ret = 0; | |
bfab27a1 GC |
3244 | struct net_device *ndev = NULL; |
3245 | struct stmmac_priv *priv; | |
47dd7a54 | 3246 | |
bfab27a1 | 3247 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 3248 | if (!ndev) |
15ffac73 | 3249 | return -ENOMEM; |
bfab27a1 GC |
3250 | |
3251 | SET_NETDEV_DEV(ndev, device); | |
3252 | ||
3253 | priv = netdev_priv(ndev); | |
3254 | priv->device = device; | |
3255 | priv->dev = ndev; | |
47dd7a54 | 3256 | |
bfab27a1 | 3257 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
3258 | priv->pause = pause; |
3259 | priv->plat = plat_dat; | |
e56788cf JE |
3260 | priv->ioaddr = res->addr; |
3261 | priv->dev->base_addr = (unsigned long)res->addr; | |
3262 | ||
3263 | priv->dev->irq = res->irq; | |
3264 | priv->wol_irq = res->wol_irq; | |
3265 | priv->lpi_irq = res->lpi_irq; | |
3266 | ||
3267 | if (res->mac) | |
3268 | memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); | |
cf3f047b | 3269 | |
a7a62685 | 3270 | dev_set_drvdata(device, priv->dev); |
803f8fc4 | 3271 | |
cf3f047b GC |
3272 | /* Verify driver arguments */ |
3273 | stmmac_verify_args(); | |
bfab27a1 | 3274 | |
cf3f047b | 3275 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
3276 | * this needs to have multiple instances |
3277 | */ | |
cf3f047b GC |
3278 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
3279 | priv->plat->phy_addr = phyaddr; | |
3280 | ||
62866e98 CYT |
3281 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
3282 | if (IS_ERR(priv->stmmac_clk)) { | |
38ddc59d LC |
3283 | netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n", |
3284 | __func__); | |
c5bb86c3 KHL |
3285 | /* If failed to obtain stmmac_clk and specific clk_csr value |
3286 | * is NOT passed from the platform, probe fail. | |
3287 | */ | |
3288 | if (!priv->plat->clk_csr) { | |
3289 | ret = PTR_ERR(priv->stmmac_clk); | |
3290 | goto error_clk_get; | |
3291 | } else { | |
3292 | priv->stmmac_clk = NULL; | |
3293 | } | |
62866e98 CYT |
3294 | } |
3295 | clk_prepare_enable(priv->stmmac_clk); | |
3296 | ||
5f9755d2 AB |
3297 | priv->pclk = devm_clk_get(priv->device, "pclk"); |
3298 | if (IS_ERR(priv->pclk)) { | |
3299 | if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { | |
3300 | ret = -EPROBE_DEFER; | |
3301 | goto error_pclk_get; | |
3302 | } | |
3303 | priv->pclk = NULL; | |
3304 | } | |
3305 | clk_prepare_enable(priv->pclk); | |
3306 | ||
c5e4ddbd CYT |
3307 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
3308 | STMMAC_RESOURCE_NAME); | |
3309 | if (IS_ERR(priv->stmmac_rst)) { | |
3310 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
3311 | ret = -EPROBE_DEFER; | |
3312 | goto error_hw_init; | |
3313 | } | |
3314 | dev_info(priv->device, "no reset control found\n"); | |
3315 | priv->stmmac_rst = NULL; | |
3316 | } | |
3317 | if (priv->stmmac_rst) | |
3318 | reset_control_deassert(priv->stmmac_rst); | |
3319 | ||
cf3f047b | 3320 | /* Init MAC and get the capabilities */ |
c24602ef GC |
3321 | ret = stmmac_hw_init(priv); |
3322 | if (ret) | |
62866e98 | 3323 | goto error_hw_init; |
cf3f047b GC |
3324 | |
3325 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 3326 | |
cf3f047b GC |
3327 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
3328 | NETIF_F_RXCSUM; | |
f748be53 AT |
3329 | |
3330 | if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { | |
3331 | ndev->hw_features |= NETIF_F_TSO; | |
3332 | priv->tso = true; | |
38ddc59d | 3333 | dev_info(priv->device, "TSO feature enabled\n"); |
f748be53 | 3334 | } |
bfab27a1 GC |
3335 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
3336 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
3337 | #ifdef STMMAC_VLAN_TAG_USED |
3338 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 3339 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
3340 | #endif |
3341 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
3342 | ||
44770e11 JW |
3343 | /* MTU range: 46 - hw-specific max */ |
3344 | ndev->min_mtu = ETH_ZLEN - ETH_HLEN; | |
3345 | if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) | |
3346 | ndev->max_mtu = JUMBO_LEN; | |
3347 | else | |
3348 | ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); | |
3349 | if (priv->plat->maxmtu < ndev->max_mtu) | |
3350 | ndev->max_mtu = priv->plat->maxmtu; | |
3351 | ||
47dd7a54 GC |
3352 | if (flow_ctrl) |
3353 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
3354 | ||
62a2ab93 GC |
3355 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
3356 | * In some case, for example on bugged HW this feature | |
3357 | * has to be disable and this can be done by passing the | |
3358 | * riwt_off field from the platform. | |
3359 | */ | |
3360 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
3361 | priv->use_riwt = 1; | |
38ddc59d | 3362 | netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n"); |
62a2ab93 GC |
3363 | } |
3364 | ||
bfab27a1 | 3365 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 3366 | |
f8e96161 VL |
3367 | spin_lock_init(&priv->lock); |
3368 | ||
cd7201f4 GC |
3369 | /* If a specific clk_csr value is passed from the platform |
3370 | * this means that the CSR Clock Range selection cannot be | |
3371 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
3372 | * set the MDC clock dynamically according to the csr actual | |
3373 | * clock input. | |
3374 | */ | |
3375 | if (!priv->plat->clk_csr) | |
3376 | stmmac_clk_csr_set(priv); | |
3377 | else | |
3378 | priv->clk_csr = priv->plat->clk_csr; | |
3379 | ||
e58bb43f GC |
3380 | stmmac_check_pcs_mode(priv); |
3381 | ||
3fe5cadb GC |
3382 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3383 | priv->hw->pcs != STMMAC_PCS_TBI && | |
3384 | priv->hw->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
3385 | /* MDIO bus Registration */ |
3386 | ret = stmmac_mdio_register(ndev); | |
3387 | if (ret < 0) { | |
38ddc59d LC |
3388 | netdev_err(priv->dev, |
3389 | "%s: MDIO bus (id: %d) registration failed", | |
3390 | __func__, priv->plat->bus_id); | |
e58bb43f GC |
3391 | goto error_mdio_register; |
3392 | } | |
4bfcbd7a FV |
3393 | } |
3394 | ||
57016590 | 3395 | ret = register_netdev(ndev); |
b2eb09af | 3396 | if (ret) { |
57016590 FF |
3397 | netdev_err(priv->dev, "%s: ERROR %i registering the device\n", |
3398 | __func__, ret); | |
b2eb09af FF |
3399 | goto error_netdev_register; |
3400 | } | |
57016590 FF |
3401 | |
3402 | return ret; | |
47dd7a54 | 3403 | |
6a81c26f | 3404 | error_netdev_register: |
b2eb09af FF |
3405 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3406 | priv->hw->pcs != STMMAC_PCS_TBI && | |
3407 | priv->hw->pcs != STMMAC_PCS_RTBI) | |
3408 | stmmac_mdio_unregister(ndev); | |
6a81c26f | 3409 | error_mdio_register: |
6a81c26f | 3410 | netif_napi_del(&priv->napi); |
62866e98 | 3411 | error_hw_init: |
5f9755d2 AB |
3412 | clk_disable_unprepare(priv->pclk); |
3413 | error_pclk_get: | |
62866e98 CYT |
3414 | clk_disable_unprepare(priv->stmmac_clk); |
3415 | error_clk_get: | |
34a52f36 | 3416 | free_netdev(ndev); |
47dd7a54 | 3417 | |
15ffac73 | 3418 | return ret; |
47dd7a54 | 3419 | } |
b2e2f0c7 | 3420 | EXPORT_SYMBOL_GPL(stmmac_dvr_probe); |
47dd7a54 GC |
3421 | |
3422 | /** | |
3423 | * stmmac_dvr_remove | |
f4e7bd81 | 3424 | * @dev: device pointer |
47dd7a54 | 3425 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 3426 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 3427 | */ |
f4e7bd81 | 3428 | int stmmac_dvr_remove(struct device *dev) |
47dd7a54 | 3429 | { |
f4e7bd81 | 3430 | struct net_device *ndev = dev_get_drvdata(dev); |
aec7ff27 | 3431 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 | 3432 | |
38ddc59d | 3433 | netdev_info(priv->dev, "%s: removing driver", __func__); |
47dd7a54 | 3434 | |
ad01b7d4 GC |
3435 | priv->hw->dma->stop_rx(priv->ioaddr); |
3436 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 3437 | |
bfab27a1 | 3438 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 | 3439 | netif_carrier_off(ndev); |
47dd7a54 | 3440 | unregister_netdev(ndev); |
c5e4ddbd CYT |
3441 | if (priv->stmmac_rst) |
3442 | reset_control_assert(priv->stmmac_rst); | |
5f9755d2 | 3443 | clk_disable_unprepare(priv->pclk); |
62866e98 | 3444 | clk_disable_unprepare(priv->stmmac_clk); |
3fe5cadb GC |
3445 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3446 | priv->hw->pcs != STMMAC_PCS_TBI && | |
3447 | priv->hw->pcs != STMMAC_PCS_RTBI) | |
e743471f | 3448 | stmmac_mdio_unregister(ndev); |
47dd7a54 GC |
3449 | free_netdev(ndev); |
3450 | ||
3451 | return 0; | |
3452 | } | |
b2e2f0c7 | 3453 | EXPORT_SYMBOL_GPL(stmmac_dvr_remove); |
47dd7a54 | 3454 | |
732fdf0e GC |
3455 | /** |
3456 | * stmmac_suspend - suspend callback | |
f4e7bd81 | 3457 | * @dev: device pointer |
732fdf0e GC |
3458 | * Description: this is the function to suspend the device and it is called |
3459 | * by the platform driver to stop the network queue, release the resources, | |
3460 | * program the PMT register (for WoL), clean and release driver resources. | |
3461 | */ | |
f4e7bd81 | 3462 | int stmmac_suspend(struct device *dev) |
47dd7a54 | 3463 | { |
f4e7bd81 | 3464 | struct net_device *ndev = dev_get_drvdata(dev); |
874bd42d | 3465 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3466 | unsigned long flags; |
47dd7a54 | 3467 | |
874bd42d | 3468 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
3469 | return 0; |
3470 | ||
d6d50c7e PR |
3471 | if (ndev->phydev) |
3472 | phy_stop(ndev->phydev); | |
102463b1 | 3473 | |
f8c5a875 | 3474 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 3475 | |
874bd42d GC |
3476 | netif_device_detach(ndev); |
3477 | netif_stop_queue(ndev); | |
47dd7a54 | 3478 | |
874bd42d GC |
3479 | napi_disable(&priv->napi); |
3480 | ||
3481 | /* Stop TX/RX DMA */ | |
3482 | priv->hw->dma->stop_tx(priv->ioaddr); | |
3483 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef | 3484 | |
874bd42d | 3485 | /* Enable Power down mode by programming the PMT regs */ |
89f7f2cf | 3486 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3487 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
3488 | priv->irq_wake = 1; |
3489 | } else { | |
bfab27a1 | 3490 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 3491 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 3492 | /* Disable clock in case of PWM is off */ |
5f9755d2 | 3493 | clk_disable(priv->pclk); |
777da230 | 3494 | clk_disable(priv->stmmac_clk); |
ba1377ff | 3495 | } |
f8c5a875 | 3496 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
3497 | |
3498 | priv->oldlink = 0; | |
3499 | priv->speed = 0; | |
3500 | priv->oldduplex = -1; | |
47dd7a54 GC |
3501 | return 0; |
3502 | } | |
b2e2f0c7 | 3503 | EXPORT_SYMBOL_GPL(stmmac_suspend); |
47dd7a54 | 3504 | |
732fdf0e GC |
3505 | /** |
3506 | * stmmac_resume - resume callback | |
f4e7bd81 | 3507 | * @dev: device pointer |
732fdf0e GC |
3508 | * Description: when resume this function is invoked to setup the DMA and CORE |
3509 | * in a usable state. | |
3510 | */ | |
f4e7bd81 | 3511 | int stmmac_resume(struct device *dev) |
47dd7a54 | 3512 | { |
f4e7bd81 | 3513 | struct net_device *ndev = dev_get_drvdata(dev); |
874bd42d | 3514 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3515 | unsigned long flags; |
47dd7a54 | 3516 | |
874bd42d | 3517 | if (!netif_running(ndev)) |
47dd7a54 GC |
3518 | return 0; |
3519 | ||
47dd7a54 GC |
3520 | /* Power Down bit, into the PM register, is cleared |
3521 | * automatically as soon as a magic packet or a Wake-up frame | |
3522 | * is received. Anyway, it's better to manually clear | |
3523 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
3524 | * from another devices (e.g. serial console). |
3525 | */ | |
623997fb | 3526 | if (device_may_wakeup(priv->device)) { |
f55d84b0 | 3527 | spin_lock_irqsave(&priv->lock, flags); |
7ed24bbe | 3528 | priv->hw->mac->pmt(priv->hw, 0); |
f55d84b0 | 3529 | spin_unlock_irqrestore(&priv->lock, flags); |
89f7f2cf | 3530 | priv->irq_wake = 0; |
623997fb | 3531 | } else { |
db88f10a | 3532 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 3533 | /* enable the clk prevously disabled */ |
777da230 | 3534 | clk_enable(priv->stmmac_clk); |
5f9755d2 | 3535 | clk_enable(priv->pclk); |
623997fb SK |
3536 | /* reset the phy so that it's ready */ |
3537 | if (priv->mii) | |
3538 | stmmac_mdio_reset(priv->mii); | |
3539 | } | |
47dd7a54 | 3540 | |
874bd42d | 3541 | netif_device_attach(ndev); |
47dd7a54 | 3542 | |
f55d84b0 VP |
3543 | spin_lock_irqsave(&priv->lock, flags); |
3544 | ||
ae79a639 GC |
3545 | priv->cur_rx = 0; |
3546 | priv->dirty_rx = 0; | |
3547 | priv->dirty_tx = 0; | |
3548 | priv->cur_tx = 0; | |
f748be53 AT |
3549 | /* reset private mss value to force mss context settings at |
3550 | * next tso xmit (only used for gmac4). | |
3551 | */ | |
3552 | priv->mss = 0; | |
3553 | ||
ae79a639 GC |
3554 | stmmac_clear_descriptors(priv); |
3555 | ||
fe131929 | 3556 | stmmac_hw_setup(ndev, false); |
777da230 | 3557 | stmmac_init_tx_coalesce(priv); |
ac316c78 | 3558 | stmmac_set_rx_mode(ndev); |
47dd7a54 | 3559 | |
47dd7a54 GC |
3560 | napi_enable(&priv->napi); |
3561 | ||
874bd42d | 3562 | netif_start_queue(ndev); |
47dd7a54 | 3563 | |
f8c5a875 | 3564 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 | 3565 | |
d6d50c7e PR |
3566 | if (ndev->phydev) |
3567 | phy_start(ndev->phydev); | |
102463b1 | 3568 | |
47dd7a54 GC |
3569 | return 0; |
3570 | } | |
b2e2f0c7 | 3571 | EXPORT_SYMBOL_GPL(stmmac_resume); |
ba27ec66 | 3572 | |
47dd7a54 GC |
3573 | #ifndef MODULE |
3574 | static int __init stmmac_cmdline_opt(char *str) | |
3575 | { | |
3576 | char *opt; | |
3577 | ||
3578 | if (!str || !*str) | |
3579 | return -EINVAL; | |
3580 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3581 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3582 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3583 | goto err; |
3584 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3585 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 | 3586 | goto err; |
f3240e28 | 3587 | } else if (!strncmp(opt, "buf_sz:", 7)) { |
ea2ab871 | 3588 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3589 | goto err; |
3590 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3591 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3592 | goto err; |
3593 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3594 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3595 | goto err; |
3596 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3597 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3598 | goto err; |
3599 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3600 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3601 | goto err; |
506f669c | 3602 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3603 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3604 | goto err; | |
4a7d666a GC |
3605 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3606 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3607 | goto err; | |
f3240e28 | 3608 | } |
47dd7a54 GC |
3609 | } |
3610 | return 0; | |
f3240e28 GC |
3611 | |
3612 | err: | |
3613 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3614 | return -EINVAL; | |
47dd7a54 GC |
3615 | } |
3616 | ||
3617 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3618 | #endif /* MODULE */ |
6fc0d0f2 | 3619 | |
466c5ac8 MO |
3620 | static int __init stmmac_init(void) |
3621 | { | |
3622 | #ifdef CONFIG_DEBUG_FS | |
3623 | /* Create debugfs main directory if it doesn't exist yet */ | |
3624 | if (!stmmac_fs_dir) { | |
3625 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
3626 | ||
3627 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
3628 | pr_err("ERROR %s, debugfs create directory failed\n", | |
3629 | STMMAC_RESOURCE_NAME); | |
3630 | ||
3631 | return -ENOMEM; | |
3632 | } | |
3633 | } | |
3634 | #endif | |
3635 | ||
3636 | return 0; | |
3637 | } | |
3638 | ||
3639 | static void __exit stmmac_exit(void) | |
3640 | { | |
3641 | #ifdef CONFIG_DEBUG_FS | |
3642 | debugfs_remove_recursive(stmmac_fs_dir); | |
3643 | #endif | |
3644 | } | |
3645 | ||
3646 | module_init(stmmac_init) | |
3647 | module_exit(stmmac_exit) | |
3648 | ||
6fc0d0f2 GC |
3649 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); |
3650 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3651 | MODULE_LICENSE("GPL"); |