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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
50fb4f74 | 47 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
48 | #include <linux/debugfs.h> |
49 | #include <linux/seq_file.h> | |
50fb4f74 | 50 | #endif /* CONFIG_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
5790cf3c | 55 | #include <linux/of_mdio.h> |
19d857c9 | 56 | #include "dwmac1000.h" |
47dd7a54 | 57 | |
47dd7a54 | 58 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
47dd7a54 GC |
59 | |
60 | /* Module parameters */ | |
32ceabca | 61 | #define TX_TIMEO 5000 |
47dd7a54 GC |
62 | static int watchdog = TX_TIMEO; |
63 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 64 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 65 | |
32ceabca | 66 | static int debug = -1; |
47dd7a54 | 67 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 68 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 69 | |
47d1f71f | 70 | static int phyaddr = -1; |
47dd7a54 GC |
71 | module_param(phyaddr, int, S_IRUGO); |
72 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
73 | ||
74 | #define DMA_TX_SIZE 256 | |
75 | static int dma_txsize = DMA_TX_SIZE; | |
76 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
77 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
78 | ||
79 | #define DMA_RX_SIZE 256 | |
80 | static int dma_rxsize = DMA_RX_SIZE; | |
81 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
82 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
83 | ||
84 | static int flow_ctrl = FLOW_OFF; | |
85 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
86 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
87 | ||
88 | static int pause = PAUSE_TIME; | |
89 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
90 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
91 | ||
92 | #define TC_DEFAULT 64 | |
93 | static int tc = TC_DEFAULT; | |
94 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
95 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
96 | ||
d916701c GC |
97 | #define DEFAULT_BUFSIZE 1536 |
98 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
99 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
100 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
101 | ||
47dd7a54 GC |
102 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
103 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
104 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
105 | ||
d765955d GC |
106 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
107 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
108 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
109 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 110 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 111 | |
4a7d666a GC |
112 | /* By default the driver will use the ring mode to manage tx and rx descriptors |
113 | * but passing this value so user can force to use the chain instead of the ring | |
114 | */ | |
115 | static unsigned int chain_mode; | |
116 | module_param(chain_mode, int, S_IRUGO); | |
117 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
118 | ||
47dd7a54 | 119 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 120 | |
50fb4f74 | 121 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 | 122 | static int stmmac_init_fs(struct net_device *dev); |
466c5ac8 | 123 | static void stmmac_exit_fs(struct net_device *dev); |
bfab27a1 GC |
124 | #endif |
125 | ||
9125cdd1 GC |
126 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
127 | ||
47dd7a54 GC |
128 | /** |
129 | * stmmac_verify_args - verify the driver parameters. | |
732fdf0e GC |
130 | * Description: it checks the driver parameters and set a default in case of |
131 | * errors. | |
47dd7a54 GC |
132 | */ |
133 | static void stmmac_verify_args(void) | |
134 | { | |
135 | if (unlikely(watchdog < 0)) | |
136 | watchdog = TX_TIMEO; | |
137 | if (unlikely(dma_rxsize < 0)) | |
138 | dma_rxsize = DMA_RX_SIZE; | |
139 | if (unlikely(dma_txsize < 0)) | |
140 | dma_txsize = DMA_TX_SIZE; | |
d916701c GC |
141 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
142 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
143 | if (unlikely(flow_ctrl > 1)) |
144 | flow_ctrl = FLOW_AUTO; | |
145 | else if (likely(flow_ctrl < 0)) | |
146 | flow_ctrl = FLOW_OFF; | |
147 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
148 | pause = PAUSE_TIME; | |
d765955d GC |
149 | if (eee_timer < 0) |
150 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
151 | } |
152 | ||
32ceabca GC |
153 | /** |
154 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
155 | * @priv: driver private structure | |
156 | * Description: this is to dynamically set the MDC clock according to the csr | |
157 | * clock input. | |
158 | * Note: | |
159 | * If a specific clk_csr value is passed from the platform | |
160 | * this means that the CSR Clock Range selection cannot be | |
161 | * changed at run-time and it is fixed (as reported in the driver | |
162 | * documentation). Viceversa the driver will try to set the MDC | |
163 | * clock dynamically according to the actual clock input. | |
164 | */ | |
cd7201f4 GC |
165 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
166 | { | |
cd7201f4 GC |
167 | u32 clk_rate; |
168 | ||
169 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
170 | ||
171 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
172 | * for all other cases except for the below mentioned ones. |
173 | * For values higher than the IEEE 802.3 specified frequency | |
174 | * we can not estimate the proper divider as it is not known | |
175 | * the frequency of clk_csr_i. So we do not change the default | |
176 | * divider. | |
177 | */ | |
cd7201f4 GC |
178 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
179 | if (clk_rate < CSR_F_35M) | |
180 | priv->clk_csr = STMMAC_CSR_20_35M; | |
181 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
182 | priv->clk_csr = STMMAC_CSR_35_60M; | |
183 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
184 | priv->clk_csr = STMMAC_CSR_60_100M; | |
185 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
186 | priv->clk_csr = STMMAC_CSR_100_150M; | |
187 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
188 | priv->clk_csr = STMMAC_CSR_150_250M; | |
19d857c9 | 189 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
cd7201f4 | 190 | priv->clk_csr = STMMAC_CSR_250_300M; |
ceb69499 | 191 | } |
cd7201f4 GC |
192 | } |
193 | ||
47dd7a54 GC |
194 | static void print_pkt(unsigned char *buf, int len) |
195 | { | |
424c4f78 AS |
196 | pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
197 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); | |
47dd7a54 | 198 | } |
47dd7a54 GC |
199 | |
200 | /* minimum number of free TX descriptors required to wake up TX process */ | |
201 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
202 | ||
203 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
204 | { | |
205 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
206 | } | |
207 | ||
32ceabca | 208 | /** |
732fdf0e | 209 | * stmmac_hw_fix_mac_speed - callback for speed selection |
32ceabca GC |
210 | * @priv: driver private structure |
211 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
212 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
213 | */ |
214 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
215 | { | |
216 | struct phy_device *phydev = priv->phydev; | |
217 | ||
218 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 219 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
220 | } |
221 | ||
32ceabca | 222 | /** |
732fdf0e | 223 | * stmmac_enable_eee_mode - check and enter in LPI mode |
32ceabca | 224 | * @priv: driver private structure |
732fdf0e GC |
225 | * Description: this function is to verify and enter in LPI mode in case of |
226 | * EEE. | |
32ceabca | 227 | */ |
d765955d GC |
228 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
229 | { | |
230 | /* Check and enter in LPI mode */ | |
231 | if ((priv->dirty_tx == priv->cur_tx) && | |
232 | (priv->tx_path_in_lpi_mode == false)) | |
7ed24bbe | 233 | priv->hw->mac->set_eee_mode(priv->hw); |
d765955d GC |
234 | } |
235 | ||
32ceabca | 236 | /** |
732fdf0e | 237 | * stmmac_disable_eee_mode - disable and exit from LPI mode |
32ceabca GC |
238 | * @priv: driver private structure |
239 | * Description: this function is to exit and disable EEE in case of | |
240 | * LPI state is true. This is called by the xmit. | |
241 | */ | |
d765955d GC |
242 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
243 | { | |
7ed24bbe | 244 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
245 | del_timer_sync(&priv->eee_ctrl_timer); |
246 | priv->tx_path_in_lpi_mode = false; | |
247 | } | |
248 | ||
249 | /** | |
732fdf0e | 250 | * stmmac_eee_ctrl_timer - EEE TX SW timer. |
d765955d GC |
251 | * @arg : data hook |
252 | * Description: | |
32ceabca | 253 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
254 | * then MAC Transmitter can be moved to LPI state. |
255 | */ | |
256 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
257 | { | |
258 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
259 | ||
260 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 261 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
262 | } |
263 | ||
264 | /** | |
732fdf0e | 265 | * stmmac_eee_init - init EEE |
32ceabca | 266 | * @priv: driver private structure |
d765955d | 267 | * Description: |
732fdf0e GC |
268 | * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
269 | * can also manage EEE, this function enable the LPI state and start related | |
270 | * timer. | |
d765955d GC |
271 | */ |
272 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
273 | { | |
56b88c25 | 274 | char *phy_bus_name = priv->plat->phy_bus_name; |
4741cf9c | 275 | unsigned long flags; |
d765955d GC |
276 | bool ret = false; |
277 | ||
f5351ef7 GC |
278 | /* Using PCS we cannot dial with the phy registers at this stage |
279 | * so we do not support extra feature like EEE. | |
280 | */ | |
281 | if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || | |
282 | (priv->pcs == STMMAC_PCS_RTBI)) | |
283 | goto out; | |
284 | ||
56b88c25 GC |
285 | /* Never init EEE in case of a switch is attached */ |
286 | if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) | |
287 | goto out; | |
288 | ||
d765955d GC |
289 | /* MAC core supports the EEE feature. */ |
290 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
291 | int tx_lpi_timer = priv->tx_lpi_timer; |
292 | ||
d765955d | 293 | /* Check if the PHY supports EEE */ |
83bf79b6 GC |
294 | if (phy_init_eee(priv->phydev, 1)) { |
295 | /* To manage at run-time if the EEE cannot be supported | |
296 | * anymore (for example because the lp caps have been | |
297 | * changed). | |
298 | * In that case the driver disable own timers. | |
299 | */ | |
4741cf9c | 300 | spin_lock_irqsave(&priv->lock, flags); |
83bf79b6 GC |
301 | if (priv->eee_active) { |
302 | pr_debug("stmmac: disable EEE\n"); | |
303 | del_timer_sync(&priv->eee_ctrl_timer); | |
7ed24bbe | 304 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
305 | tx_lpi_timer); |
306 | } | |
307 | priv->eee_active = 0; | |
4741cf9c | 308 | spin_unlock_irqrestore(&priv->lock, flags); |
d765955d | 309 | goto out; |
83bf79b6 GC |
310 | } |
311 | /* Activate the EEE and start timers */ | |
4741cf9c | 312 | spin_lock_irqsave(&priv->lock, flags); |
f5351ef7 GC |
313 | if (!priv->eee_active) { |
314 | priv->eee_active = 1; | |
ccb36da1 VT |
315 | setup_timer(&priv->eee_ctrl_timer, |
316 | stmmac_eee_ctrl_timer, | |
317 | (unsigned long)priv); | |
318 | mod_timer(&priv->eee_ctrl_timer, | |
319 | STMMAC_LPI_T(eee_timer)); | |
f5351ef7 | 320 | |
7ed24bbe | 321 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 322 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 323 | tx_lpi_timer); |
71965352 GC |
324 | } |
325 | /* Set HW EEE according to the speed */ | |
326 | priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); | |
d765955d | 327 | |
d765955d | 328 | ret = true; |
4741cf9c GC |
329 | spin_unlock_irqrestore(&priv->lock, flags); |
330 | ||
331 | pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); | |
d765955d GC |
332 | } |
333 | out: | |
334 | return ret; | |
335 | } | |
336 | ||
732fdf0e | 337 | /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
32ceabca | 338 | * @priv: driver private structure |
891434b1 RK |
339 | * @entry : descriptor index to be used. |
340 | * @skb : the socket buffer | |
341 | * Description : | |
342 | * This function will read timestamp from the descriptor & pass it to stack. | |
343 | * and also perform some sanity checks. | |
344 | */ | |
345 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 346 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
347 | { |
348 | struct skb_shared_hwtstamps shhwtstamp; | |
349 | u64 ns; | |
350 | void *desc = NULL; | |
351 | ||
352 | if (!priv->hwts_tx_en) | |
353 | return; | |
354 | ||
ceb69499 | 355 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 356 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
357 | return; |
358 | ||
359 | if (priv->adv_ts) | |
360 | desc = (priv->dma_etx + entry); | |
361 | else | |
362 | desc = (priv->dma_tx + entry); | |
363 | ||
364 | /* check tx tstamp status */ | |
365 | if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) | |
366 | return; | |
367 | ||
368 | /* get the valid tstamp */ | |
369 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
370 | ||
371 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
372 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
373 | /* pass tstamp to stack */ | |
374 | skb_tstamp_tx(skb, &shhwtstamp); | |
375 | ||
376 | return; | |
377 | } | |
378 | ||
732fdf0e | 379 | /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
32ceabca | 380 | * @priv: driver private structure |
891434b1 RK |
381 | * @entry : descriptor index to be used. |
382 | * @skb : the socket buffer | |
383 | * Description : | |
384 | * This function will read received packet's timestamp from the descriptor | |
385 | * and pass it to stack. It also perform some sanity checks. | |
386 | */ | |
387 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 388 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
389 | { |
390 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
391 | u64 ns; | |
392 | void *desc = NULL; | |
393 | ||
394 | if (!priv->hwts_rx_en) | |
395 | return; | |
396 | ||
397 | if (priv->adv_ts) | |
398 | desc = (priv->dma_erx + entry); | |
399 | else | |
400 | desc = (priv->dma_rx + entry); | |
401 | ||
ceb69499 | 402 | /* exit if rx tstamp is not valid */ |
891434b1 RK |
403 | if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) |
404 | return; | |
405 | ||
406 | /* get valid tstamp */ | |
407 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
408 | shhwtstamp = skb_hwtstamps(skb); | |
409 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
410 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
411 | } | |
412 | ||
413 | /** | |
414 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
415 | * @dev: device pointer. | |
416 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
417 | * a proprietary structure used to pass information to the driver. | |
418 | * Description: | |
419 | * This function configures the MAC to enable/disable both outgoing(TX) | |
420 | * and incoming(RX) packets time stamping based on user input. | |
421 | * Return Value: | |
422 | * 0 on success and an appropriate -ve integer on failure. | |
423 | */ | |
424 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
425 | { | |
426 | struct stmmac_priv *priv = netdev_priv(dev); | |
427 | struct hwtstamp_config config; | |
0a624155 | 428 | struct timespec64 now; |
891434b1 RK |
429 | u64 temp = 0; |
430 | u32 ptp_v2 = 0; | |
431 | u32 tstamp_all = 0; | |
432 | u32 ptp_over_ipv4_udp = 0; | |
433 | u32 ptp_over_ipv6_udp = 0; | |
434 | u32 ptp_over_ethernet = 0; | |
435 | u32 snap_type_sel = 0; | |
436 | u32 ts_master_en = 0; | |
437 | u32 ts_event_en = 0; | |
438 | u32 value = 0; | |
19d857c9 | 439 | u32 sec_inc; |
891434b1 RK |
440 | |
441 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
442 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
443 | priv->hwts_tx_en = 0; | |
444 | priv->hwts_rx_en = 0; | |
445 | ||
446 | return -EOPNOTSUPP; | |
447 | } | |
448 | ||
449 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 450 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
451 | return -EFAULT; |
452 | ||
453 | pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
454 | __func__, config.flags, config.tx_type, config.rx_filter); | |
455 | ||
456 | /* reserved for future extensions */ | |
457 | if (config.flags) | |
458 | return -EINVAL; | |
459 | ||
5f3da328 BH |
460 | if (config.tx_type != HWTSTAMP_TX_OFF && |
461 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 462 | return -ERANGE; |
891434b1 RK |
463 | |
464 | if (priv->adv_ts) { | |
465 | switch (config.rx_filter) { | |
891434b1 | 466 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 467 | /* time stamp no incoming packet at all */ |
891434b1 RK |
468 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
469 | break; | |
470 | ||
891434b1 | 471 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 472 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
473 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
474 | /* take time stamp for all event messages */ | |
475 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
476 | ||
477 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
478 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
479 | break; | |
480 | ||
891434b1 | 481 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 482 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
483 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
484 | /* take time stamp for SYNC messages only */ | |
485 | ts_event_en = PTP_TCR_TSEVNTENA; | |
486 | ||
487 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
488 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
489 | break; | |
490 | ||
891434b1 | 491 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 492 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
493 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
494 | /* take time stamp for Delay_Req messages only */ | |
495 | ts_master_en = PTP_TCR_TSMSTRENA; | |
496 | ts_event_en = PTP_TCR_TSEVNTENA; | |
497 | ||
498 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
499 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
500 | break; | |
501 | ||
891434b1 | 502 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 503 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
504 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
505 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
506 | /* take time stamp for all event messages */ | |
507 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
508 | ||
509 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
510 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
511 | break; | |
512 | ||
891434b1 | 513 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 514 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
515 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
516 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
517 | /* take time stamp for SYNC messages only */ | |
518 | ts_event_en = PTP_TCR_TSEVNTENA; | |
519 | ||
520 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
521 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
522 | break; | |
523 | ||
891434b1 | 524 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 525 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
526 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
527 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
528 | /* take time stamp for Delay_Req messages only */ | |
529 | ts_master_en = PTP_TCR_TSMSTRENA; | |
530 | ts_event_en = PTP_TCR_TSEVNTENA; | |
531 | ||
532 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
533 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
534 | break; | |
535 | ||
891434b1 | 536 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 537 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
538 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
539 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
540 | /* take time stamp for all event messages */ | |
541 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
542 | ||
543 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
544 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
545 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
546 | break; | |
547 | ||
891434b1 | 548 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 549 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
550 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
551 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
552 | /* take time stamp for SYNC messages only */ | |
553 | ts_event_en = PTP_TCR_TSEVNTENA; | |
554 | ||
555 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
556 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
557 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
558 | break; | |
559 | ||
891434b1 | 560 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 561 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
562 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
563 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
564 | /* take time stamp for Delay_Req messages only */ | |
565 | ts_master_en = PTP_TCR_TSMSTRENA; | |
566 | ts_event_en = PTP_TCR_TSEVNTENA; | |
567 | ||
568 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
569 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
570 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
571 | break; | |
572 | ||
891434b1 | 573 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 574 | /* time stamp any incoming packet */ |
891434b1 RK |
575 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
576 | tstamp_all = PTP_TCR_TSENALL; | |
577 | break; | |
578 | ||
579 | default: | |
580 | return -ERANGE; | |
581 | } | |
582 | } else { | |
583 | switch (config.rx_filter) { | |
584 | case HWTSTAMP_FILTER_NONE: | |
585 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
586 | break; | |
587 | default: | |
588 | /* PTP v1, UDP, any kind of event packet */ | |
589 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
590 | break; | |
591 | } | |
592 | } | |
593 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 594 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
595 | |
596 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
597 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); | |
598 | else { | |
599 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
600 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
601 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
602 | ts_master_en | snap_type_sel); | |
891434b1 RK |
603 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); |
604 | ||
605 | /* program Sub Second Increment reg */ | |
19d857c9 PR |
606 | sec_inc = priv->hw->ptp->config_sub_second_increment( |
607 | priv->ioaddr, priv->clk_ptp_rate); | |
608 | temp = div_u64(1000000000ULL, sec_inc); | |
891434b1 RK |
609 | |
610 | /* calculate default added value: | |
611 | * formula is : | |
612 | * addend = (2^32)/freq_div_ratio; | |
19d857c9 | 613 | * where, freq_div_ratio = 1e9ns/sec_inc |
891434b1 | 614 | */ |
19d857c9 | 615 | temp = (u64)(temp << 32); |
5566401f | 616 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
891434b1 RK |
617 | priv->hw->ptp->config_addend(priv->ioaddr, |
618 | priv->default_addend); | |
619 | ||
620 | /* initialize system time */ | |
0a624155 AB |
621 | ktime_get_real_ts64(&now); |
622 | ||
623 | /* lower 32 bits of tv_sec are safe until y2106 */ | |
624 | priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec, | |
891434b1 RK |
625 | now.tv_nsec); |
626 | } | |
627 | ||
628 | return copy_to_user(ifr->ifr_data, &config, | |
629 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
630 | } | |
631 | ||
32ceabca | 632 | /** |
732fdf0e | 633 | * stmmac_init_ptp - init PTP |
32ceabca | 634 | * @priv: driver private structure |
732fdf0e | 635 | * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
32ceabca | 636 | * This is done by looking at the HW cap. register. |
732fdf0e | 637 | * This function also registers the ptp driver. |
32ceabca | 638 | */ |
92ba6888 | 639 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 640 | { |
92ba6888 RK |
641 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
642 | return -EOPNOTSUPP; | |
643 | ||
5566401f GC |
644 | /* Fall-back to main clock in case of no PTP ref is passed */ |
645 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
646 | if (IS_ERR(priv->clk_ptp_ref)) { | |
647 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
648 | priv->clk_ptp_ref = NULL; | |
649 | } else { | |
650 | clk_prepare_enable(priv->clk_ptp_ref); | |
651 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
652 | } | |
653 | ||
7cd01399 VB |
654 | priv->adv_ts = 0; |
655 | if (priv->dma_cap.atime_stamp && priv->extend_desc) | |
656 | priv->adv_ts = 1; | |
657 | ||
658 | if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) | |
659 | pr_debug("IEEE 1588-2002 Time Stamp supported\n"); | |
660 | ||
661 | if (netif_msg_hw(priv) && priv->adv_ts) | |
662 | pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); | |
891434b1 RK |
663 | |
664 | priv->hw->ptp = &stmmac_ptp; | |
665 | priv->hwts_tx_en = 0; | |
666 | priv->hwts_rx_en = 0; | |
92ba6888 RK |
667 | |
668 | return stmmac_ptp_register(priv); | |
669 | } | |
670 | ||
671 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
672 | { | |
5566401f GC |
673 | if (priv->clk_ptp_ref) |
674 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 675 | stmmac_ptp_unregister(priv); |
891434b1 RK |
676 | } |
677 | ||
47dd7a54 | 678 | /** |
732fdf0e | 679 | * stmmac_adjust_link - adjusts the link parameters |
47dd7a54 | 680 | * @dev: net device structure |
732fdf0e GC |
681 | * Description: this is the helper called by the physical abstraction layer |
682 | * drivers to communicate the phy link status. According the speed and duplex | |
683 | * this driver can invoke registered glue-logic as well. | |
684 | * It also invoke the eee initialization because it could happen when switch | |
685 | * on different networks (that are eee capable). | |
47dd7a54 GC |
686 | */ |
687 | static void stmmac_adjust_link(struct net_device *dev) | |
688 | { | |
689 | struct stmmac_priv *priv = netdev_priv(dev); | |
690 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
691 | unsigned long flags; |
692 | int new_state = 0; | |
693 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
694 | ||
695 | if (phydev == NULL) | |
696 | return; | |
697 | ||
47dd7a54 | 698 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 699 | |
47dd7a54 | 700 | if (phydev->link) { |
ad01b7d4 | 701 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
702 | |
703 | /* Now we make sure that we can be in full duplex mode. | |
704 | * If not, we operate in half-duplex mode. */ | |
705 | if (phydev->duplex != priv->oldduplex) { | |
706 | new_state = 1; | |
707 | if (!(phydev->duplex)) | |
db98a0b0 | 708 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 709 | else |
db98a0b0 | 710 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
711 | priv->oldduplex = phydev->duplex; |
712 | } | |
713 | /* Flow Control operation */ | |
714 | if (phydev->pause) | |
7ed24bbe | 715 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 716 | fc, pause_time); |
47dd7a54 GC |
717 | |
718 | if (phydev->speed != priv->speed) { | |
719 | new_state = 1; | |
720 | switch (phydev->speed) { | |
721 | case 1000: | |
9dfeb4d9 | 722 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 723 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 724 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
725 | break; |
726 | case 100: | |
727 | case 10: | |
9dfeb4d9 | 728 | if (priv->plat->has_gmac) { |
db98a0b0 | 729 | ctrl |= priv->hw->link.port; |
47dd7a54 | 730 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 731 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 732 | } else { |
db98a0b0 | 733 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
734 | } |
735 | } else { | |
db98a0b0 | 736 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 737 | } |
9dfeb4d9 | 738 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
739 | break; |
740 | default: | |
741 | if (netif_msg_link(priv)) | |
ceb69499 GC |
742 | pr_warn("%s: Speed (%d) not 10/100\n", |
743 | dev->name, phydev->speed); | |
47dd7a54 GC |
744 | break; |
745 | } | |
746 | ||
747 | priv->speed = phydev->speed; | |
748 | } | |
749 | ||
ad01b7d4 | 750 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
751 | |
752 | if (!priv->oldlink) { | |
753 | new_state = 1; | |
754 | priv->oldlink = 1; | |
755 | } | |
756 | } else if (priv->oldlink) { | |
757 | new_state = 1; | |
758 | priv->oldlink = 0; | |
759 | priv->speed = 0; | |
760 | priv->oldduplex = -1; | |
761 | } | |
762 | ||
763 | if (new_state && netif_msg_link(priv)) | |
764 | phy_print_status(phydev); | |
765 | ||
4741cf9c GC |
766 | spin_unlock_irqrestore(&priv->lock, flags); |
767 | ||
f5351ef7 GC |
768 | /* At this stage, it could be needed to setup the EEE or adjust some |
769 | * MAC related HW registers. | |
770 | */ | |
771 | priv->eee_enabled = stmmac_eee_init(priv); | |
47dd7a54 GC |
772 | } |
773 | ||
32ceabca | 774 | /** |
732fdf0e | 775 | * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
32ceabca GC |
776 | * @priv: driver private structure |
777 | * Description: this is to verify if the HW supports the PCS. | |
778 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
779 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
780 | */ | |
e58bb43f GC |
781 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
782 | { | |
783 | int interface = priv->plat->interface; | |
784 | ||
785 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
786 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
787 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
788 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
789 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
e58bb43f GC |
790 | pr_debug("STMMAC: PCS RGMII support enable\n"); |
791 | priv->pcs = STMMAC_PCS_RGMII; | |
0d909dcd | 792 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
e58bb43f GC |
793 | pr_debug("STMMAC: PCS SGMII support enable\n"); |
794 | priv->pcs = STMMAC_PCS_SGMII; | |
795 | } | |
796 | } | |
797 | } | |
798 | ||
47dd7a54 GC |
799 | /** |
800 | * stmmac_init_phy - PHY initialization | |
801 | * @dev: net device structure | |
802 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
803 | * to the mac driver. | |
804 | * Return value: | |
805 | * 0 on success | |
806 | */ | |
807 | static int stmmac_init_phy(struct net_device *dev) | |
808 | { | |
809 | struct stmmac_priv *priv = netdev_priv(dev); | |
810 | struct phy_device *phydev; | |
d765955d | 811 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 812 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 813 | int interface = priv->plat->interface; |
9cbadf09 | 814 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
815 | priv->oldlink = 0; |
816 | priv->speed = 0; | |
817 | priv->oldduplex = -1; | |
818 | ||
5790cf3c MO |
819 | if (priv->plat->phy_node) { |
820 | phydev = of_phy_connect(dev, priv->plat->phy_node, | |
821 | &stmmac_adjust_link, 0, interface); | |
822 | } else { | |
823 | if (priv->plat->phy_bus_name) | |
824 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
825 | priv->plat->phy_bus_name, priv->plat->bus_id); | |
826 | else | |
827 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
828 | priv->plat->bus_id); | |
829 | ||
830 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, | |
831 | priv->plat->phy_addr); | |
832 | pr_debug("stmmac_init_phy: trying to attach to %s\n", | |
833 | phy_id_fmt); | |
834 | ||
835 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, | |
836 | interface); | |
837 | } | |
47dd7a54 | 838 | |
dfc50fca | 839 | if (IS_ERR_OR_NULL(phydev)) { |
47dd7a54 | 840 | pr_err("%s: Could not attach to PHY\n", dev->name); |
dfc50fca AB |
841 | if (!phydev) |
842 | return -ENODEV; | |
843 | ||
47dd7a54 GC |
844 | return PTR_ERR(phydev); |
845 | } | |
846 | ||
79ee1dc3 | 847 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 848 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 849 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 850 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
851 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
852 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 853 | |
47dd7a54 GC |
854 | /* |
855 | * Broken HW is sometimes missing the pull-up resistor on the | |
856 | * MDIO line, which results in reads to non-existent devices returning | |
857 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
858 | * device as well. | |
859 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
860 | */ | |
27732381 | 861 | if (!priv->plat->phy_node && phydev->phy_id == 0) { |
47dd7a54 GC |
862 | phy_disconnect(phydev); |
863 | return -ENODEV; | |
864 | } | |
865 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 866 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
867 | |
868 | priv->phydev = phydev; | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
47dd7a54 | 873 | /** |
732fdf0e | 874 | * stmmac_display_ring - display ring |
32ceabca | 875 | * @head: pointer to the head of the ring passed. |
47dd7a54 | 876 | * @size: size of the ring. |
32ceabca | 877 | * @extend_desc: to verify if extended descriptors are used. |
c24602ef | 878 | * Description: display the control/status and buffer descriptors. |
47dd7a54 | 879 | */ |
c24602ef | 880 | static void stmmac_display_ring(void *head, int size, int extend_desc) |
47dd7a54 | 881 | { |
47dd7a54 | 882 | int i; |
ceb69499 GC |
883 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
884 | struct dma_desc *p = (struct dma_desc *)head; | |
c24602ef | 885 | |
47dd7a54 | 886 | for (i = 0; i < size; i++) { |
c24602ef GC |
887 | u64 x; |
888 | if (extend_desc) { | |
889 | x = *(u64 *) ep; | |
890 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
891 | i, (unsigned int)virt_to_phys(ep), |
892 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
893 | ep->basic.des2, ep->basic.des3); |
894 | ep++; | |
895 | } else { | |
896 | x = *(u64 *) p; | |
897 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", | |
ceb69499 GC |
898 | i, (unsigned int)virt_to_phys(p), |
899 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
900 | p->des2, p->des3); |
901 | p++; | |
902 | } | |
47dd7a54 GC |
903 | pr_info("\n"); |
904 | } | |
905 | } | |
906 | ||
c24602ef GC |
907 | static void stmmac_display_rings(struct stmmac_priv *priv) |
908 | { | |
909 | unsigned int txsize = priv->dma_tx_size; | |
910 | unsigned int rxsize = priv->dma_rx_size; | |
911 | ||
912 | if (priv->extend_desc) { | |
913 | pr_info("Extended RX descriptor ring:\n"); | |
ceb69499 | 914 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef | 915 | pr_info("Extended TX descriptor ring:\n"); |
ceb69499 | 916 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); |
c24602ef GC |
917 | } else { |
918 | pr_info("RX descriptor ring:\n"); | |
919 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
920 | pr_info("TX descriptor ring:\n"); | |
921 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
922 | } | |
923 | } | |
924 | ||
286a8372 GC |
925 | static int stmmac_set_bfsize(int mtu, int bufsize) |
926 | { | |
927 | int ret = bufsize; | |
928 | ||
929 | if (mtu >= BUF_SIZE_4KiB) | |
930 | ret = BUF_SIZE_8KiB; | |
931 | else if (mtu >= BUF_SIZE_2KiB) | |
932 | ret = BUF_SIZE_4KiB; | |
d916701c | 933 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
934 | ret = BUF_SIZE_2KiB; |
935 | else | |
d916701c | 936 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
937 | |
938 | return ret; | |
939 | } | |
940 | ||
32ceabca | 941 | /** |
732fdf0e | 942 | * stmmac_clear_descriptors - clear descriptors |
32ceabca GC |
943 | * @priv: driver private structure |
944 | * Description: this function is called to clear the tx and rx descriptors | |
945 | * in case of both basic and extended descriptors are used. | |
946 | */ | |
c24602ef GC |
947 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
948 | { | |
949 | int i; | |
950 | unsigned int txsize = priv->dma_tx_size; | |
951 | unsigned int rxsize = priv->dma_rx_size; | |
952 | ||
953 | /* Clear the Rx/Tx descriptors */ | |
954 | for (i = 0; i < rxsize; i++) | |
955 | if (priv->extend_desc) | |
956 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
957 | priv->use_riwt, priv->mode, | |
958 | (i == rxsize - 1)); | |
959 | else | |
960 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
961 | priv->use_riwt, priv->mode, | |
962 | (i == rxsize - 1)); | |
963 | for (i = 0; i < txsize; i++) | |
964 | if (priv->extend_desc) | |
965 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
966 | priv->mode, | |
967 | (i == txsize - 1)); | |
968 | else | |
969 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
970 | priv->mode, | |
971 | (i == txsize - 1)); | |
972 | } | |
973 | ||
732fdf0e GC |
974 | /** |
975 | * stmmac_init_rx_buffers - init the RX descriptor buffer. | |
976 | * @priv: driver private structure | |
977 | * @p: descriptor pointer | |
978 | * @i: descriptor index | |
979 | * @flags: gfp flag. | |
980 | * Description: this function is called to allocate a receive buffer, perform | |
981 | * the DMA mapping and init the descriptor. | |
982 | */ | |
c24602ef | 983 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
777da230 | 984 | int i, gfp_t flags) |
c24602ef GC |
985 | { |
986 | struct sk_buff *skb; | |
987 | ||
4ec49a37 | 988 | skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); |
56329137 | 989 | if (!skb) { |
c24602ef | 990 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); |
56329137 | 991 | return -ENOMEM; |
c24602ef | 992 | } |
c24602ef GC |
993 | priv->rx_skbuff[i] = skb; |
994 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
995 | priv->dma_buf_sz, | |
996 | DMA_FROM_DEVICE); | |
56329137 BZ |
997 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
998 | pr_err("%s: DMA mapping error\n", __func__); | |
999 | dev_kfree_skb_any(skb); | |
1000 | return -EINVAL; | |
1001 | } | |
c24602ef GC |
1002 | |
1003 | p->des2 = priv->rx_skbuff_dma[i]; | |
1004 | ||
29896a67 | 1005 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 1006 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 1007 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
1008 | |
1009 | return 0; | |
1010 | } | |
1011 | ||
56329137 BZ |
1012 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
1013 | { | |
1014 | if (priv->rx_skbuff[i]) { | |
1015 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
1016 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1017 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1018 | } | |
1019 | priv->rx_skbuff[i] = NULL; | |
1020 | } | |
1021 | ||
47dd7a54 GC |
1022 | /** |
1023 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1024 | * @dev: net device structure | |
732fdf0e GC |
1025 | * @flags: gfp flag. |
1026 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1027 | * and allocates the socket buffers. It suppors the chained and ring |
1028 | * modes. | |
47dd7a54 | 1029 | */ |
777da230 | 1030 | static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
47dd7a54 GC |
1031 | { |
1032 | int i; | |
1033 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1034 | unsigned int txsize = priv->dma_tx_size; |
1035 | unsigned int rxsize = priv->dma_rx_size; | |
4a7d666a | 1036 | unsigned int bfsize = 0; |
56329137 | 1037 | int ret = -ENOMEM; |
47dd7a54 | 1038 | |
29896a67 GC |
1039 | if (priv->hw->mode->set_16kib_bfsize) |
1040 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1041 | |
4a7d666a | 1042 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1043 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1044 | |
2618abb7 VB |
1045 | priv->dma_buf_sz = bfsize; |
1046 | ||
83d7af64 GC |
1047 | if (netif_msg_probe(priv)) |
1048 | pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, | |
1049 | txsize, rxsize, bfsize); | |
47dd7a54 | 1050 | |
83d7af64 | 1051 | if (netif_msg_probe(priv)) { |
c24602ef GC |
1052 | pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, |
1053 | (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); | |
47dd7a54 | 1054 | |
83d7af64 GC |
1055 | /* RX INITIALIZATION */ |
1056 | pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); | |
1057 | } | |
47dd7a54 | 1058 | for (i = 0; i < rxsize; i++) { |
c24602ef GC |
1059 | struct dma_desc *p; |
1060 | if (priv->extend_desc) | |
1061 | p = &((priv->dma_erx + i)->basic); | |
1062 | else | |
1063 | p = priv->dma_rx + i; | |
47dd7a54 | 1064 | |
777da230 | 1065 | ret = stmmac_init_rx_buffers(priv, p, i, flags); |
56329137 BZ |
1066 | if (ret) |
1067 | goto err_init_rx_buffers; | |
286a8372 | 1068 | |
83d7af64 GC |
1069 | if (netif_msg_probe(priv)) |
1070 | pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
1071 | priv->rx_skbuff[i]->data, | |
1072 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1073 | } |
1074 | priv->cur_rx = 0; | |
1075 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
47dd7a54 GC |
1076 | buf_sz = bfsize; |
1077 | ||
c24602ef GC |
1078 | /* Setup the chained descriptor addresses */ |
1079 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1080 | if (priv->extend_desc) { | |
29896a67 GC |
1081 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
1082 | rxsize, 1); | |
1083 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, | |
1084 | txsize, 1); | |
c24602ef | 1085 | } else { |
29896a67 GC |
1086 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
1087 | rxsize, 0); | |
1088 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, | |
1089 | txsize, 0); | |
c24602ef GC |
1090 | } |
1091 | } | |
1092 | ||
47dd7a54 GC |
1093 | /* TX INITIALIZATION */ |
1094 | for (i = 0; i < txsize; i++) { | |
c24602ef GC |
1095 | struct dma_desc *p; |
1096 | if (priv->extend_desc) | |
1097 | p = &((priv->dma_etx + i)->basic); | |
1098 | else | |
1099 | p = priv->dma_tx + i; | |
1100 | p->des2 = 0; | |
362b37be GC |
1101 | priv->tx_skbuff_dma[i].buf = 0; |
1102 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 | 1103 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1104 | } |
286a8372 | 1105 | |
47dd7a54 GC |
1106 | priv->dirty_tx = 0; |
1107 | priv->cur_tx = 0; | |
38979574 | 1108 | netdev_reset_queue(priv->dev); |
47dd7a54 | 1109 | |
c24602ef | 1110 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1111 | |
c24602ef GC |
1112 | if (netif_msg_hw(priv)) |
1113 | stmmac_display_rings(priv); | |
56329137 BZ |
1114 | |
1115 | return 0; | |
1116 | err_init_rx_buffers: | |
1117 | while (--i >= 0) | |
1118 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1119 | return ret; |
47dd7a54 GC |
1120 | } |
1121 | ||
1122 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1123 | { | |
1124 | int i; | |
1125 | ||
56329137 BZ |
1126 | for (i = 0; i < priv->dma_rx_size; i++) |
1127 | stmmac_free_rx_buffers(priv, i); | |
47dd7a54 GC |
1128 | } |
1129 | ||
1130 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1131 | { | |
1132 | int i; | |
1133 | ||
1134 | for (i = 0; i < priv->dma_tx_size; i++) { | |
75e4364f | 1135 | struct dma_desc *p; |
1136 | ||
1137 | if (priv->extend_desc) | |
1138 | p = &((priv->dma_etx + i)->basic); | |
1139 | else | |
1140 | p = priv->dma_tx + i; | |
1141 | ||
362b37be GC |
1142 | if (priv->tx_skbuff_dma[i].buf) { |
1143 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1144 | dma_unmap_page(priv->device, | |
1145 | priv->tx_skbuff_dma[i].buf, | |
1146 | priv->hw->desc->get_tx_len(p), | |
1147 | DMA_TO_DEVICE); | |
1148 | else | |
1149 | dma_unmap_single(priv->device, | |
1150 | priv->tx_skbuff_dma[i].buf, | |
1151 | priv->hw->desc->get_tx_len(p), | |
1152 | DMA_TO_DEVICE); | |
75e4364f | 1153 | } |
c24602ef | 1154 | |
75e4364f | 1155 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1156 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1157 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1158 | priv->tx_skbuff_dma[i].buf = 0; |
1159 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1160 | } |
1161 | } | |
47dd7a54 GC |
1162 | } |
1163 | ||
732fdf0e GC |
1164 | /** |
1165 | * alloc_dma_desc_resources - alloc TX/RX resources. | |
1166 | * @priv: private structure | |
1167 | * Description: according to which descriptor can be used (extend or basic) | |
1168 | * this function allocates the resources for TX and RX paths. In case of | |
1169 | * reception, for example, it pre-allocated the RX socket buffer in order to | |
1170 | * allow zero-copy mechanism. | |
1171 | */ | |
09f8d696 SK |
1172 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1173 | { | |
1174 | unsigned int txsize = priv->dma_tx_size; | |
1175 | unsigned int rxsize = priv->dma_rx_size; | |
1176 | int ret = -ENOMEM; | |
1177 | ||
1178 | priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), | |
1179 | GFP_KERNEL); | |
1180 | if (!priv->rx_skbuff_dma) | |
1181 | return -ENOMEM; | |
1182 | ||
1183 | priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), | |
1184 | GFP_KERNEL); | |
1185 | if (!priv->rx_skbuff) | |
1186 | goto err_rx_skbuff; | |
1187 | ||
362b37be GC |
1188 | priv->tx_skbuff_dma = kmalloc_array(txsize, |
1189 | sizeof(*priv->tx_skbuff_dma), | |
09f8d696 SK |
1190 | GFP_KERNEL); |
1191 | if (!priv->tx_skbuff_dma) | |
1192 | goto err_tx_skbuff_dma; | |
1193 | ||
1194 | priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), | |
1195 | GFP_KERNEL); | |
1196 | if (!priv->tx_skbuff) | |
1197 | goto err_tx_skbuff; | |
1198 | ||
1199 | if (priv->extend_desc) { | |
f1590670 AB |
1200 | priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize * |
1201 | sizeof(struct | |
1202 | dma_extended_desc), | |
1203 | &priv->dma_rx_phy, | |
1204 | GFP_KERNEL); | |
09f8d696 SK |
1205 | if (!priv->dma_erx) |
1206 | goto err_dma; | |
1207 | ||
f1590670 AB |
1208 | priv->dma_etx = dma_zalloc_coherent(priv->device, txsize * |
1209 | sizeof(struct | |
1210 | dma_extended_desc), | |
1211 | &priv->dma_tx_phy, | |
1212 | GFP_KERNEL); | |
09f8d696 SK |
1213 | if (!priv->dma_etx) { |
1214 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
f1590670 AB |
1215 | sizeof(struct dma_extended_desc), |
1216 | priv->dma_erx, priv->dma_rx_phy); | |
09f8d696 SK |
1217 | goto err_dma; |
1218 | } | |
1219 | } else { | |
f1590670 AB |
1220 | priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize * |
1221 | sizeof(struct dma_desc), | |
1222 | &priv->dma_rx_phy, | |
1223 | GFP_KERNEL); | |
09f8d696 SK |
1224 | if (!priv->dma_rx) |
1225 | goto err_dma; | |
1226 | ||
f1590670 AB |
1227 | priv->dma_tx = dma_zalloc_coherent(priv->device, txsize * |
1228 | sizeof(struct dma_desc), | |
1229 | &priv->dma_tx_phy, | |
1230 | GFP_KERNEL); | |
09f8d696 SK |
1231 | if (!priv->dma_tx) { |
1232 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
f1590670 AB |
1233 | sizeof(struct dma_desc), |
1234 | priv->dma_rx, priv->dma_rx_phy); | |
09f8d696 SK |
1235 | goto err_dma; |
1236 | } | |
1237 | } | |
1238 | ||
1239 | return 0; | |
1240 | ||
1241 | err_dma: | |
1242 | kfree(priv->tx_skbuff); | |
1243 | err_tx_skbuff: | |
1244 | kfree(priv->tx_skbuff_dma); | |
1245 | err_tx_skbuff_dma: | |
1246 | kfree(priv->rx_skbuff); | |
1247 | err_rx_skbuff: | |
1248 | kfree(priv->rx_skbuff_dma); | |
1249 | return ret; | |
1250 | } | |
1251 | ||
47dd7a54 GC |
1252 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1253 | { | |
1254 | /* Release the DMA TX/RX socket buffers */ | |
1255 | dma_free_rx_skbufs(priv); | |
1256 | dma_free_tx_skbufs(priv); | |
1257 | ||
ceb69499 | 1258 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1259 | if (!priv->extend_desc) { |
1260 | dma_free_coherent(priv->device, | |
1261 | priv->dma_tx_size * sizeof(struct dma_desc), | |
1262 | priv->dma_tx, priv->dma_tx_phy); | |
1263 | dma_free_coherent(priv->device, | |
1264 | priv->dma_rx_size * sizeof(struct dma_desc), | |
1265 | priv->dma_rx, priv->dma_rx_phy); | |
1266 | } else { | |
1267 | dma_free_coherent(priv->device, priv->dma_tx_size * | |
1268 | sizeof(struct dma_extended_desc), | |
1269 | priv->dma_etx, priv->dma_tx_phy); | |
1270 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1271 | sizeof(struct dma_extended_desc), | |
1272 | priv->dma_erx, priv->dma_rx_phy); | |
1273 | } | |
47dd7a54 GC |
1274 | kfree(priv->rx_skbuff_dma); |
1275 | kfree(priv->rx_skbuff); | |
cf32deec | 1276 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1277 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1278 | } |
1279 | ||
47dd7a54 GC |
1280 | /** |
1281 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1282 | * @priv: driver private structure |
732fdf0e GC |
1283 | * Description: it is used for configuring the DMA operation mode register in |
1284 | * order to program the tx/rx DMA thresholds or Store-And-Forward mode. | |
47dd7a54 GC |
1285 | */ |
1286 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1287 | { | |
f88203a2 VB |
1288 | int rxfifosz = priv->plat->rx_fifo_size; |
1289 | ||
e2a240c7 | 1290 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 | 1291 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); |
e2a240c7 | 1292 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
61b8013a SK |
1293 | /* |
1294 | * In case of GMAC, SF mode can be enabled | |
1295 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1296 | * 1) TX COE if actually supported |
1297 | * 2) There is no bugged Jumbo frame support | |
1298 | * that needs to not insert csum in the TDES. | |
1299 | */ | |
f88203a2 VB |
1300 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, |
1301 | rxfifosz); | |
b2dec116 | 1302 | priv->xstats.threshold = SF_DMA_MODE; |
ebbb293f | 1303 | } else |
f88203a2 VB |
1304 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, |
1305 | rxfifosz); | |
47dd7a54 GC |
1306 | } |
1307 | ||
47dd7a54 | 1308 | /** |
732fdf0e | 1309 | * stmmac_tx_clean - to manage the transmission completion |
32ceabca | 1310 | * @priv: driver private structure |
732fdf0e | 1311 | * Description: it reclaims the transmit resources after transmission completes. |
47dd7a54 | 1312 | */ |
9125cdd1 | 1313 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 GC |
1314 | { |
1315 | unsigned int txsize = priv->dma_tx_size; | |
38979574 | 1316 | unsigned int bytes_compl = 0, pkts_compl = 0; |
47dd7a54 | 1317 | |
a9097a96 GC |
1318 | spin_lock(&priv->tx_lock); |
1319 | ||
9125cdd1 GC |
1320 | priv->xstats.tx_clean++; |
1321 | ||
47dd7a54 GC |
1322 | while (priv->dirty_tx != priv->cur_tx) { |
1323 | int last; | |
1324 | unsigned int entry = priv->dirty_tx % txsize; | |
1325 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
c24602ef GC |
1326 | struct dma_desc *p; |
1327 | ||
1328 | if (priv->extend_desc) | |
ceb69499 | 1329 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1330 | else |
1331 | p = priv->dma_tx + entry; | |
47dd7a54 GC |
1332 | |
1333 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 1334 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
1335 | break; |
1336 | ||
c24602ef | 1337 | /* Verify tx error by looking at the last segment. */ |
db98a0b0 | 1338 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
1339 | if (likely(last)) { |
1340 | int tx_error = | |
ceb69499 GC |
1341 | priv->hw->desc->tx_status(&priv->dev->stats, |
1342 | &priv->xstats, p, | |
1343 | priv->ioaddr); | |
47dd7a54 GC |
1344 | if (likely(tx_error == 0)) { |
1345 | priv->dev->stats.tx_packets++; | |
1346 | priv->xstats.tx_pkt_n++; | |
1347 | } else | |
1348 | priv->dev->stats.tx_errors++; | |
891434b1 RK |
1349 | |
1350 | stmmac_get_tx_hwtstamp(priv, entry, skb); | |
47dd7a54 | 1351 | } |
83d7af64 GC |
1352 | if (netif_msg_tx_done(priv)) |
1353 | pr_debug("%s: curr %d, dirty %d\n", __func__, | |
1354 | priv->cur_tx, priv->dirty_tx); | |
47dd7a54 | 1355 | |
362b37be GC |
1356 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1357 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1358 | dma_unmap_page(priv->device, | |
1359 | priv->tx_skbuff_dma[entry].buf, | |
1360 | priv->hw->desc->get_tx_len(p), | |
1361 | DMA_TO_DEVICE); | |
1362 | else | |
1363 | dma_unmap_single(priv->device, | |
1364 | priv->tx_skbuff_dma[entry].buf, | |
1365 | priv->hw->desc->get_tx_len(p), | |
1366 | DMA_TO_DEVICE); | |
1367 | priv->tx_skbuff_dma[entry].buf = 0; | |
1368 | priv->tx_skbuff_dma[entry].map_as_page = false; | |
cf32deec | 1369 | } |
29896a67 | 1370 | priv->hw->mode->clean_desc3(priv, p); |
47dd7a54 GC |
1371 | |
1372 | if (likely(skb != NULL)) { | |
38979574 BG |
1373 | pkts_compl++; |
1374 | bytes_compl += skb->len; | |
7c565c33 | 1375 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1376 | priv->tx_skbuff[entry] = NULL; |
1377 | } | |
1378 | ||
4a7d666a | 1379 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1380 | |
13497f58 | 1381 | priv->dirty_tx++; |
47dd7a54 | 1382 | } |
38979574 BG |
1383 | |
1384 | netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); | |
1385 | ||
47dd7a54 GC |
1386 | if (unlikely(netif_queue_stopped(priv->dev) && |
1387 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
1388 | netif_tx_lock(priv->dev); | |
1389 | if (netif_queue_stopped(priv->dev) && | |
ceb69499 | 1390 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { |
83d7af64 GC |
1391 | if (netif_msg_tx_done(priv)) |
1392 | pr_debug("%s: restart transmit\n", __func__); | |
47dd7a54 GC |
1393 | netif_wake_queue(priv->dev); |
1394 | } | |
1395 | netif_tx_unlock(priv->dev); | |
1396 | } | |
d765955d GC |
1397 | |
1398 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1399 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1400 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1401 | } |
a9097a96 | 1402 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1403 | } |
1404 | ||
9125cdd1 | 1405 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1406 | { |
7284a3f1 | 1407 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1408 | } |
1409 | ||
9125cdd1 | 1410 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1411 | { |
7284a3f1 | 1412 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1413 | } |
1414 | ||
47dd7a54 | 1415 | /** |
732fdf0e | 1416 | * stmmac_tx_err - to manage the tx error |
32ceabca | 1417 | * @priv: driver private structure |
47dd7a54 | 1418 | * Description: it cleans the descriptors and restarts the transmission |
732fdf0e | 1419 | * in case of transmission errors. |
47dd7a54 GC |
1420 | */ |
1421 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1422 | { | |
c24602ef GC |
1423 | int i; |
1424 | int txsize = priv->dma_tx_size; | |
47dd7a54 GC |
1425 | netif_stop_queue(priv->dev); |
1426 | ||
ad01b7d4 | 1427 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1428 | dma_free_tx_skbufs(priv); |
c24602ef GC |
1429 | for (i = 0; i < txsize; i++) |
1430 | if (priv->extend_desc) | |
1431 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1432 | priv->mode, | |
1433 | (i == txsize - 1)); | |
1434 | else | |
1435 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1436 | priv->mode, | |
1437 | (i == txsize - 1)); | |
47dd7a54 GC |
1438 | priv->dirty_tx = 0; |
1439 | priv->cur_tx = 0; | |
38979574 | 1440 | netdev_reset_queue(priv->dev); |
ad01b7d4 | 1441 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1442 | |
1443 | priv->dev->stats.tx_errors++; | |
1444 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1445 | } |
1446 | ||
32ceabca | 1447 | /** |
732fdf0e | 1448 | * stmmac_dma_interrupt - DMA ISR |
32ceabca GC |
1449 | * @priv: driver private structure |
1450 | * Description: this is the DMA ISR. It is called by the main ISR. | |
732fdf0e GC |
1451 | * It calls the dwmac dma routine and schedule poll method in case of some |
1452 | * work can be done. | |
32ceabca | 1453 | */ |
aec7ff27 GC |
1454 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1455 | { | |
aec7ff27 | 1456 | int status; |
f88203a2 | 1457 | int rxfifosz = priv->plat->rx_fifo_size; |
aec7ff27 | 1458 | |
ad01b7d4 | 1459 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1460 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1461 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1462 | stmmac_disable_dma_irq(priv); | |
1463 | __napi_schedule(&priv->napi); | |
1464 | } | |
1465 | } | |
1466 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 | 1467 | /* Try to bump up the dma threshold on this failure */ |
b2dec116 SZ |
1468 | if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
1469 | (tc <= 256)) { | |
aec7ff27 | 1470 | tc += 64; |
c405abe2 | 1471 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 VB |
1472 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, |
1473 | rxfifosz); | |
c405abe2 SZ |
1474 | else |
1475 | priv->hw->dma->dma_mode(priv->ioaddr, tc, | |
f88203a2 | 1476 | SF_DMA_MODE, rxfifosz); |
aec7ff27 | 1477 | priv->xstats.threshold = tc; |
47dd7a54 | 1478 | } |
aec7ff27 GC |
1479 | } else if (unlikely(status == tx_hard_error)) |
1480 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1481 | } |
1482 | ||
32ceabca GC |
1483 | /** |
1484 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1485 | * @priv: driver private structure | |
1486 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1487 | */ | |
1c901a46 GC |
1488 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1489 | { | |
1490 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
ceb69499 | 1491 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1492 | |
1c901a46 | 1493 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
1494 | |
1495 | if (priv->dma_cap.rmon) { | |
1496 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
1497 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
1498 | } else | |
aae54cff | 1499 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
1500 | } |
1501 | ||
732fdf0e GC |
1502 | /** |
1503 | * stmmac_get_synopsys_id - return the SYINID. | |
1504 | * @priv: driver private structure | |
1505 | * Description: this simple function is to decode and return the SYINID | |
1506 | * starting from the HW core register. | |
1507 | */ | |
f0b9d786 GC |
1508 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
1509 | { | |
1510 | u32 hwid = priv->hw->synopsys_uid; | |
1511 | ||
ceb69499 | 1512 | /* Check Synopsys Id (not available on old chips) */ |
f0b9d786 GC |
1513 | if (likely(hwid)) { |
1514 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
1515 | u32 synid = (hwid & 0x000000ff); | |
1516 | ||
cf3f047b | 1517 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
1518 | uid, synid); |
1519 | ||
1520 | return synid; | |
1521 | } | |
1522 | return 0; | |
1523 | } | |
e7434821 | 1524 | |
19e30c14 | 1525 | /** |
732fdf0e | 1526 | * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
32ceabca GC |
1527 | * @priv: driver private structure |
1528 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
732fdf0e GC |
1529 | * In case of Enhanced/Alternate, it checks if the extended descriptors are |
1530 | * supported by the HW capability register. | |
ff3dd78c | 1531 | */ |
19e30c14 GC |
1532 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1533 | { | |
1534 | if (priv->plat->enh_desc) { | |
1535 | pr_info(" Enhanced/Alternate descriptors\n"); | |
c24602ef GC |
1536 | |
1537 | /* GMAC older than 3.50 has no extended descriptors */ | |
1538 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
1539 | pr_info("\tEnabled extended descriptors\n"); | |
1540 | priv->extend_desc = 1; | |
1541 | } else | |
1542 | pr_warn("Extended descriptors not supported\n"); | |
1543 | ||
19e30c14 GC |
1544 | priv->hw->desc = &enh_desc_ops; |
1545 | } else { | |
1546 | pr_info(" Normal descriptors\n"); | |
1547 | priv->hw->desc = &ndesc_ops; | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | /** | |
732fdf0e | 1552 | * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
32ceabca | 1553 | * @priv: driver private structure |
19e30c14 GC |
1554 | * Description: |
1555 | * new GMAC chip generations have a new register to indicate the | |
1556 | * presence of the optional feature/functions. | |
1557 | * This can be also used to override the value passed through the | |
1558 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1559 | */ |
1560 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1561 | { | |
5e6efe88 | 1562 | u32 hw_cap = 0; |
3c20f72f | 1563 | |
5e6efe88 GC |
1564 | if (priv->hw->dma->get_hw_feature) { |
1565 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 1566 | |
1db123fb RK |
1567 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
1568 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
1569 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
1570 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
ceb69499 | 1571 | priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; |
1db123fb RK |
1572 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; |
1573 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
1574 | priv->dma_cap.pmt_remote_wake_up = | |
ceb69499 | 1575 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; |
1db123fb | 1576 | priv->dma_cap.pmt_magic_frame = |
ceb69499 | 1577 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; |
19e30c14 | 1578 | /* MMC */ |
1db123fb | 1579 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
ceb69499 | 1580 | /* IEEE 1588-2002 */ |
1db123fb | 1581 | priv->dma_cap.time_stamp = |
ceb69499 GC |
1582 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; |
1583 | /* IEEE 1588-2008 */ | |
1db123fb | 1584 | priv->dma_cap.atime_stamp = |
ceb69499 | 1585 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; |
e7434821 | 1586 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
1587 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
1588 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 1589 | /* TX and RX csum */ |
1db123fb RK |
1590 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
1591 | priv->dma_cap.rx_coe_type1 = | |
ceb69499 | 1592 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; |
1db123fb | 1593 | priv->dma_cap.rx_coe_type2 = |
ceb69499 | 1594 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; |
1db123fb | 1595 | priv->dma_cap.rxfifo_over_2048 = |
ceb69499 | 1596 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; |
e7434821 | 1597 | /* TX and RX number of channels */ |
1db123fb | 1598 | priv->dma_cap.number_rx_channel = |
ceb69499 | 1599 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; |
1db123fb | 1600 | priv->dma_cap.number_tx_channel = |
ceb69499 GC |
1601 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; |
1602 | /* Alternate (enhanced) DESC mode */ | |
1603 | priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
19e30c14 | 1604 | } |
e7434821 GC |
1605 | |
1606 | return hw_cap; | |
1607 | } | |
1608 | ||
32ceabca | 1609 | /** |
732fdf0e | 1610 | * stmmac_check_ether_addr - check if the MAC addr is valid |
32ceabca GC |
1611 | * @priv: driver private structure |
1612 | * Description: | |
1613 | * it is to verify if the MAC address is valid, in case of failures it | |
1614 | * generates a random MAC address | |
1615 | */ | |
bfab27a1 GC |
1616 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1617 | { | |
bfab27a1 | 1618 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1619 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1620 | priv->dev->dev_addr, 0); |
ceb69499 | 1621 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1622 | eth_hw_addr_random(priv->dev); |
c88460b7 HG |
1623 | pr_info("%s: device MAC address %pM\n", priv->dev->name, |
1624 | priv->dev->dev_addr); | |
bfab27a1 | 1625 | } |
bfab27a1 GC |
1626 | } |
1627 | ||
32ceabca | 1628 | /** |
732fdf0e | 1629 | * stmmac_init_dma_engine - DMA init. |
32ceabca GC |
1630 | * @priv: driver private structure |
1631 | * Description: | |
1632 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1633 | * Some DMA parameters can be passed from the platform; | |
1634 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1635 | */ | |
0f1f88a8 GC |
1636 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1637 | { | |
1638 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; | |
b9cde0a8 | 1639 | int mixed_burst = 0; |
c24602ef | 1640 | int atds = 0; |
0f1f88a8 | 1641 | |
0f1f88a8 GC |
1642 | if (priv->plat->dma_cfg) { |
1643 | pbl = priv->plat->dma_cfg->pbl; | |
1644 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
b9cde0a8 | 1645 | mixed_burst = priv->plat->dma_cfg->mixed_burst; |
0f1f88a8 GC |
1646 | burst_len = priv->plat->dma_cfg->burst_len; |
1647 | } | |
1648 | ||
c24602ef GC |
1649 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1650 | atds = 1; | |
1651 | ||
b9cde0a8 | 1652 | return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, |
0f1f88a8 | 1653 | burst_len, priv->dma_tx_phy, |
c24602ef | 1654 | priv->dma_rx_phy, atds); |
0f1f88a8 GC |
1655 | } |
1656 | ||
9125cdd1 | 1657 | /** |
732fdf0e | 1658 | * stmmac_tx_timer - mitigation sw timer for tx. |
9125cdd1 GC |
1659 | * @data: data pointer |
1660 | * Description: | |
1661 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1662 | */ | |
1663 | static void stmmac_tx_timer(unsigned long data) | |
1664 | { | |
1665 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1666 | ||
1667 | stmmac_tx_clean(priv); | |
1668 | } | |
1669 | ||
1670 | /** | |
732fdf0e | 1671 | * stmmac_init_tx_coalesce - init tx mitigation options. |
32ceabca | 1672 | * @priv: driver private structure |
9125cdd1 GC |
1673 | * Description: |
1674 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1675 | * timer handler and default threshold used for enabling the | |
1676 | * interrupt on completion bit. | |
1677 | */ | |
1678 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1679 | { | |
1680 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1681 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1682 | init_timer(&priv->txtimer); | |
1683 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1684 | priv->txtimer.data = (unsigned long)priv; | |
1685 | priv->txtimer.function = stmmac_tx_timer; | |
1686 | add_timer(&priv->txtimer); | |
1687 | } | |
1688 | ||
523f11b5 | 1689 | /** |
732fdf0e | 1690 | * stmmac_hw_setup - setup mac in a usable state. |
523f11b5 SK |
1691 | * @dev : pointer to the device structure. |
1692 | * Description: | |
732fdf0e GC |
1693 | * this is the main function to setup the HW in a usable state because the |
1694 | * dma engine is reset, the core registers are configured (e.g. AXI, | |
1695 | * Checksum features, timers). The DMA is ready to start receiving and | |
1696 | * transmitting. | |
523f11b5 SK |
1697 | * Return value: |
1698 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1699 | * file on failure. | |
1700 | */ | |
fe131929 | 1701 | static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
523f11b5 SK |
1702 | { |
1703 | struct stmmac_priv *priv = netdev_priv(dev); | |
1704 | int ret; | |
1705 | ||
523f11b5 SK |
1706 | /* DMA initialization and SW reset */ |
1707 | ret = stmmac_init_dma_engine(priv); | |
1708 | if (ret < 0) { | |
1709 | pr_err("%s: DMA engine initialization failed\n", __func__); | |
1710 | return ret; | |
1711 | } | |
1712 | ||
1713 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1714 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1715 | |
1716 | /* If required, perform hw setup of the bus. */ | |
1717 | if (priv->plat->bus_setup) | |
1718 | priv->plat->bus_setup(priv->ioaddr); | |
1719 | ||
1720 | /* Initialize the MAC Core */ | |
7ed24bbe | 1721 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1722 | |
978aded4 GC |
1723 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1724 | if (!ret) { | |
1725 | pr_warn(" RX IPC Checksum Offload disabled\n"); | |
1726 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
d2afb5bd | 1727 | priv->hw->rx_csum = 0; |
978aded4 GC |
1728 | } |
1729 | ||
523f11b5 SK |
1730 | /* Enable the MAC Rx/Tx */ |
1731 | stmmac_set_mac(priv->ioaddr, true); | |
1732 | ||
1733 | /* Set the HW DMA mode and the COE */ | |
1734 | stmmac_dma_operation_mode(priv); | |
1735 | ||
1736 | stmmac_mmc_setup(priv); | |
1737 | ||
fe131929 HC |
1738 | if (init_ptp) { |
1739 | ret = stmmac_init_ptp(priv); | |
1740 | if (ret && ret != -EOPNOTSUPP) | |
1741 | pr_warn("%s: failed PTP initialisation\n", __func__); | |
1742 | } | |
523f11b5 | 1743 | |
50fb4f74 | 1744 | #ifdef CONFIG_DEBUG_FS |
523f11b5 SK |
1745 | ret = stmmac_init_fs(dev); |
1746 | if (ret < 0) | |
1747 | pr_warn("%s: failed debugFS registration\n", __func__); | |
1748 | #endif | |
1749 | /* Start the ball rolling... */ | |
1750 | pr_debug("%s: DMA RX/TX processes started...\n", dev->name); | |
1751 | priv->hw->dma->start_tx(priv->ioaddr); | |
1752 | priv->hw->dma->start_rx(priv->ioaddr); | |
1753 | ||
1754 | /* Dump DMA/MAC registers */ | |
1755 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1756 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1757 | priv->hw->dma->dump_regs(priv->ioaddr); |
1758 | } | |
1759 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1760 | ||
523f11b5 SK |
1761 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
1762 | priv->rx_riwt = MAX_DMA_RIWT; | |
1763 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1764 | } | |
1765 | ||
1766 | if (priv->pcs && priv->hw->mac->ctrl_ane) | |
7ed24bbe | 1767 | priv->hw->mac->ctrl_ane(priv->hw, 0); |
523f11b5 SK |
1768 | |
1769 | return 0; | |
1770 | } | |
1771 | ||
47dd7a54 GC |
1772 | /** |
1773 | * stmmac_open - open entry point of the driver | |
1774 | * @dev : pointer to the device structure. | |
1775 | * Description: | |
1776 | * This function is the open entry point of the driver. | |
1777 | * Return value: | |
1778 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1779 | * file on failure. | |
1780 | */ | |
1781 | static int stmmac_open(struct net_device *dev) | |
1782 | { | |
1783 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1784 | int ret; |
1785 | ||
4bfcbd7a FV |
1786 | stmmac_check_ether_addr(priv); |
1787 | ||
4d8f0825 BA |
1788 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
1789 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1790 | ret = stmmac_init_phy(dev); |
1791 | if (ret) { | |
1792 | pr_err("%s: Cannot attach to PHY (error: %d)\n", | |
1793 | __func__, ret); | |
89df20d9 | 1794 | return ret; |
e58bb43f | 1795 | } |
f66ffe28 | 1796 | } |
47dd7a54 | 1797 | |
523f11b5 SK |
1798 | /* Extra statistics */ |
1799 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1800 | priv->xstats.threshold = tc; | |
1801 | ||
47dd7a54 GC |
1802 | /* Create and initialize the TX/RX descriptors chains. */ |
1803 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
1804 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
1805 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
56329137 | 1806 | |
7262b7b2 | 1807 | ret = alloc_dma_desc_resources(priv); |
09f8d696 SK |
1808 | if (ret < 0) { |
1809 | pr_err("%s: DMA descriptors allocation failed\n", __func__); | |
1810 | goto dma_desc_error; | |
1811 | } | |
1812 | ||
777da230 GC |
1813 | ret = init_dma_desc_rings(dev, GFP_KERNEL); |
1814 | if (ret < 0) { | |
1815 | pr_err("%s: DMA descriptors initialization failed\n", __func__); | |
1816 | goto init_error; | |
1817 | } | |
1818 | ||
fe131929 | 1819 | ret = stmmac_hw_setup(dev, true); |
56329137 | 1820 | if (ret < 0) { |
523f11b5 | 1821 | pr_err("%s: Hw setup failed\n", __func__); |
c9324d18 | 1822 | goto init_error; |
47dd7a54 GC |
1823 | } |
1824 | ||
777da230 GC |
1825 | stmmac_init_tx_coalesce(priv); |
1826 | ||
523f11b5 SK |
1827 | if (priv->phydev) |
1828 | phy_start(priv->phydev); | |
47dd7a54 | 1829 | |
f66ffe28 GC |
1830 | /* Request the IRQ lines */ |
1831 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1832 | IRQF_SHARED, dev->name, dev); |
f66ffe28 GC |
1833 | if (unlikely(ret < 0)) { |
1834 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1835 | __func__, dev->irq, ret); | |
c9324d18 | 1836 | goto init_error; |
f66ffe28 GC |
1837 | } |
1838 | ||
7a13f8f5 FV |
1839 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1840 | if (priv->wol_irq != dev->irq) { | |
1841 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1842 | IRQF_SHARED, dev->name, dev); | |
1843 | if (unlikely(ret < 0)) { | |
ceb69499 GC |
1844 | pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
1845 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1846 | goto wolirq_error; |
7a13f8f5 FV |
1847 | } |
1848 | } | |
1849 | ||
d765955d | 1850 | /* Request the IRQ lines */ |
d7ec8584 | 1851 | if (priv->lpi_irq > 0) { |
d765955d GC |
1852 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1853 | dev->name, dev); | |
1854 | if (unlikely(ret < 0)) { | |
1855 | pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1856 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1857 | goto lpiirq_error; |
d765955d GC |
1858 | } |
1859 | } | |
1860 | ||
47dd7a54 | 1861 | napi_enable(&priv->napi); |
47dd7a54 | 1862 | netif_start_queue(dev); |
f66ffe28 | 1863 | |
47dd7a54 | 1864 | return 0; |
f66ffe28 | 1865 | |
c9324d18 | 1866 | lpiirq_error: |
d765955d GC |
1867 | if (priv->wol_irq != dev->irq) |
1868 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1869 | wolirq_error: |
7a13f8f5 FV |
1870 | free_irq(dev->irq, dev); |
1871 | ||
c9324d18 GC |
1872 | init_error: |
1873 | free_dma_desc_resources(priv); | |
56329137 | 1874 | dma_desc_error: |
f66ffe28 GC |
1875 | if (priv->phydev) |
1876 | phy_disconnect(priv->phydev); | |
4bfcbd7a | 1877 | |
f66ffe28 | 1878 | return ret; |
47dd7a54 GC |
1879 | } |
1880 | ||
1881 | /** | |
1882 | * stmmac_release - close entry point of the driver | |
1883 | * @dev : device pointer. | |
1884 | * Description: | |
1885 | * This is the stop entry point of the driver. | |
1886 | */ | |
1887 | static int stmmac_release(struct net_device *dev) | |
1888 | { | |
1889 | struct stmmac_priv *priv = netdev_priv(dev); | |
1890 | ||
d765955d GC |
1891 | if (priv->eee_enabled) |
1892 | del_timer_sync(&priv->eee_ctrl_timer); | |
1893 | ||
47dd7a54 GC |
1894 | /* Stop and disconnect the PHY */ |
1895 | if (priv->phydev) { | |
1896 | phy_stop(priv->phydev); | |
1897 | phy_disconnect(priv->phydev); | |
1898 | priv->phydev = NULL; | |
1899 | } | |
1900 | ||
1901 | netif_stop_queue(dev); | |
1902 | ||
47dd7a54 | 1903 | napi_disable(&priv->napi); |
47dd7a54 | 1904 | |
9125cdd1 GC |
1905 | del_timer_sync(&priv->txtimer); |
1906 | ||
47dd7a54 GC |
1907 | /* Free the IRQ lines */ |
1908 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1909 | if (priv->wol_irq != dev->irq) |
1910 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1911 | if (priv->lpi_irq > 0) |
d765955d | 1912 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1913 | |
1914 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1915 | priv->hw->dma->stop_tx(priv->ioaddr); |
1916 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1917 | |
1918 | /* Release and free the Rx/Tx resources */ | |
1919 | free_dma_desc_resources(priv); | |
1920 | ||
19449bfc | 1921 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1922 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1923 | |
1924 | netif_carrier_off(dev); | |
1925 | ||
50fb4f74 | 1926 | #ifdef CONFIG_DEBUG_FS |
466c5ac8 | 1927 | stmmac_exit_fs(dev); |
bfab27a1 | 1928 | #endif |
bfab27a1 | 1929 | |
92ba6888 RK |
1930 | stmmac_release_ptp(priv); |
1931 | ||
47dd7a54 GC |
1932 | return 0; |
1933 | } | |
1934 | ||
47dd7a54 | 1935 | /** |
732fdf0e | 1936 | * stmmac_xmit - Tx entry point of the driver |
47dd7a54 GC |
1937 | * @skb : the socket buffer |
1938 | * @dev : device pointer | |
32ceabca GC |
1939 | * Description : this is the tx entry point of the driver. |
1940 | * It programs the chain or the ring and supports oversized frames | |
1941 | * and SG feature. | |
47dd7a54 GC |
1942 | */ |
1943 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1944 | { | |
1945 | struct stmmac_priv *priv = netdev_priv(dev); | |
1946 | unsigned int txsize = priv->dma_tx_size; | |
23c2412d | 1947 | int entry; |
4a7d666a | 1948 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 GC |
1949 | int nfrags = skb_shinfo(skb)->nr_frags; |
1950 | struct dma_desc *desc, *first; | |
286a8372 | 1951 | unsigned int nopaged_len = skb_headlen(skb); |
29896a67 | 1952 | unsigned int enh_desc = priv->plat->enh_desc; |
47dd7a54 | 1953 | |
16ee817e FG |
1954 | spin_lock(&priv->tx_lock); |
1955 | ||
47dd7a54 | 1956 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { |
16ee817e | 1957 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1958 | if (!netif_queue_stopped(dev)) { |
1959 | netif_stop_queue(dev); | |
1960 | /* This is a hard error, log it. */ | |
ceb69499 | 1961 | pr_err("%s: Tx Ring full when queue awake\n", __func__); |
47dd7a54 GC |
1962 | } |
1963 | return NETDEV_TX_BUSY; | |
1964 | } | |
1965 | ||
d765955d GC |
1966 | if (priv->tx_path_in_lpi_mode) |
1967 | stmmac_disable_eee_mode(priv); | |
1968 | ||
47dd7a54 GC |
1969 | entry = priv->cur_tx % txsize; |
1970 | ||
5e982f3b | 1971 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 1972 | |
c24602ef | 1973 | if (priv->extend_desc) |
ceb69499 | 1974 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1975 | else |
1976 | desc = priv->dma_tx + entry; | |
1977 | ||
47dd7a54 GC |
1978 | first = desc; |
1979 | ||
4a7d666a | 1980 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
1981 | if (enh_desc) |
1982 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
1983 | ||
4a7d666a | 1984 | if (likely(!is_jumbo)) { |
47dd7a54 | 1985 | desc->des2 = dma_map_single(priv->device, skb->data, |
ceb69499 | 1986 | nopaged_len, DMA_TO_DEVICE); |
362b37be GC |
1987 | if (dma_mapping_error(priv->device, desc->des2)) |
1988 | goto dma_map_err; | |
1989 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
db98a0b0 | 1990 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
4a7d666a | 1991 | csum_insertion, priv->mode); |
29896a67 | 1992 | } else { |
c24602ef | 1993 | desc = first; |
29896a67 | 1994 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
1995 | if (unlikely(entry < 0)) |
1996 | goto dma_map_err; | |
29896a67 | 1997 | } |
47dd7a54 GC |
1998 | |
1999 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
2000 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2001 | int len = skb_frag_size(frag); | |
47dd7a54 | 2002 | |
75e4364f | 2003 | priv->tx_skbuff[entry] = NULL; |
47dd7a54 | 2004 | entry = (++priv->cur_tx) % txsize; |
c24602ef | 2005 | if (priv->extend_desc) |
ceb69499 | 2006 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2007 | else |
2008 | desc = priv->dma_tx + entry; | |
47dd7a54 | 2009 | |
f722380d IC |
2010 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
2011 | DMA_TO_DEVICE); | |
362b37be GC |
2012 | if (dma_mapping_error(priv->device, desc->des2)) |
2013 | goto dma_map_err; /* should reuse desc w/o issues */ | |
2014 | ||
2015 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
2016 | priv->tx_skbuff_dma[entry].map_as_page = true; | |
4a7d666a GC |
2017 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
2018 | priv->mode); | |
eb0dc4bb | 2019 | wmb(); |
db98a0b0 | 2020 | priv->hw->desc->set_tx_owner(desc); |
8e839891 | 2021 | wmb(); |
47dd7a54 GC |
2022 | } |
2023 | ||
75e4364f | 2024 | priv->tx_skbuff[entry] = skb; |
2025 | ||
9125cdd1 | 2026 | /* Finalize the latest segment. */ |
db98a0b0 | 2027 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 2028 | |
eb0dc4bb | 2029 | wmb(); |
9125cdd1 GC |
2030 | /* According to the coalesce parameter the IC bit for the latest |
2031 | * segment could be reset and the timer re-started to invoke the | |
2032 | * stmmac_tx function. This approach takes care about the fragments. | |
2033 | */ | |
2034 | priv->tx_count_frames += nfrags + 1; | |
2035 | if (priv->tx_coal_frames > priv->tx_count_frames) { | |
2036 | priv->hw->desc->clear_tx_ic(desc); | |
2037 | priv->xstats.tx_reset_ic_bit++; | |
9125cdd1 GC |
2038 | mod_timer(&priv->txtimer, |
2039 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2040 | } else | |
2041 | priv->tx_count_frames = 0; | |
eb0dc4bb | 2042 | |
47dd7a54 | 2043 | /* To avoid raise condition */ |
db98a0b0 | 2044 | priv->hw->desc->set_tx_owner(first); |
8e839891 | 2045 | wmb(); |
47dd7a54 GC |
2046 | |
2047 | priv->cur_tx++; | |
2048 | ||
47dd7a54 | 2049 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2050 | pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", |
ceb69499 GC |
2051 | __func__, (priv->cur_tx % txsize), |
2052 | (priv->dirty_tx % txsize), entry, first, nfrags); | |
83d7af64 | 2053 | |
c24602ef GC |
2054 | if (priv->extend_desc) |
2055 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); | |
2056 | else | |
2057 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
2058 | ||
83d7af64 | 2059 | pr_debug(">>> frame to be transmitted: "); |
47dd7a54 GC |
2060 | print_pkt(skb->data, skb->len); |
2061 | } | |
47dd7a54 | 2062 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
83d7af64 GC |
2063 | if (netif_msg_hw(priv)) |
2064 | pr_debug("%s: stop transmitted packets\n", __func__); | |
47dd7a54 GC |
2065 | netif_stop_queue(dev); |
2066 | } | |
2067 | ||
2068 | dev->stats.tx_bytes += skb->len; | |
2069 | ||
891434b1 RK |
2070 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
2071 | priv->hwts_tx_en)) { | |
2072 | /* declare that device is doing timestamping */ | |
2073 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2074 | priv->hw->desc->enable_tx_timestamp(first); | |
2075 | } | |
2076 | ||
2077 | if (!priv->hwts_tx_en) | |
2078 | skb_tx_timestamp(skb); | |
3e82ce12 | 2079 | |
38979574 | 2080 | netdev_sent_queue(dev, skb->len); |
52f64fae RC |
2081 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
2082 | ||
a9097a96 | 2083 | spin_unlock(&priv->tx_lock); |
362b37be | 2084 | return NETDEV_TX_OK; |
a9097a96 | 2085 | |
362b37be | 2086 | dma_map_err: |
758a0ab5 | 2087 | spin_unlock(&priv->tx_lock); |
362b37be GC |
2088 | dev_err(priv->device, "Tx dma map failed\n"); |
2089 | dev_kfree_skb(skb); | |
2090 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2091 | return NETDEV_TX_OK; |
2092 | } | |
2093 | ||
b9381985 VB |
2094 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2095 | { | |
2096 | struct ethhdr *ehdr; | |
2097 | u16 vlanid; | |
2098 | ||
2099 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2100 | NETIF_F_HW_VLAN_CTAG_RX && | |
2101 | !__vlan_get_tag(skb, &vlanid)) { | |
2102 | /* pop the vlan tag */ | |
2103 | ehdr = (struct ethhdr *)skb->data; | |
2104 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2105 | skb_pull(skb, VLAN_HLEN); | |
2106 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | ||
32ceabca | 2111 | /** |
732fdf0e | 2112 | * stmmac_rx_refill - refill used skb preallocated buffers |
32ceabca GC |
2113 | * @priv: driver private structure |
2114 | * Description : this is to reallocate the skb for the reception process | |
2115 | * that is based on zero-copy. | |
2116 | */ | |
47dd7a54 GC |
2117 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2118 | { | |
2119 | unsigned int rxsize = priv->dma_rx_size; | |
2120 | int bfsize = priv->dma_buf_sz; | |
47dd7a54 GC |
2121 | |
2122 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
2123 | unsigned int entry = priv->dirty_rx % rxsize; | |
c24602ef GC |
2124 | struct dma_desc *p; |
2125 | ||
2126 | if (priv->extend_desc) | |
ceb69499 | 2127 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2128 | else |
2129 | p = priv->dma_rx + entry; | |
2130 | ||
47dd7a54 GC |
2131 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2132 | struct sk_buff *skb; | |
2133 | ||
acb600de | 2134 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
47dd7a54 GC |
2135 | |
2136 | if (unlikely(skb == NULL)) | |
2137 | break; | |
2138 | ||
2139 | priv->rx_skbuff[entry] = skb; | |
2140 | priv->rx_skbuff_dma[entry] = | |
2141 | dma_map_single(priv->device, skb->data, bfsize, | |
2142 | DMA_FROM_DEVICE); | |
362b37be GC |
2143 | if (dma_mapping_error(priv->device, |
2144 | priv->rx_skbuff_dma[entry])) { | |
2145 | dev_err(priv->device, "Rx dma map failed\n"); | |
2146 | dev_kfree_skb(skb); | |
2147 | break; | |
2148 | } | |
c24602ef | 2149 | p->des2 = priv->rx_skbuff_dma[entry]; |
286a8372 | 2150 | |
29896a67 | 2151 | priv->hw->mode->refill_desc3(priv, p); |
286a8372 | 2152 | |
83d7af64 GC |
2153 | if (netif_msg_rx_status(priv)) |
2154 | pr_debug("\trefill entry #%d\n", entry); | |
47dd7a54 | 2155 | } |
eb0dc4bb | 2156 | wmb(); |
c24602ef | 2157 | priv->hw->desc->set_rx_owner(p); |
8e839891 | 2158 | wmb(); |
47dd7a54 | 2159 | } |
47dd7a54 GC |
2160 | } |
2161 | ||
32ceabca | 2162 | /** |
732fdf0e | 2163 | * stmmac_rx - manage the receive process |
32ceabca GC |
2164 | * @priv: driver private structure |
2165 | * @limit: napi bugget. | |
2166 | * Description : this the function called by the napi poll method. | |
2167 | * It gets all the frames inside the ring. | |
2168 | */ | |
47dd7a54 GC |
2169 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2170 | { | |
2171 | unsigned int rxsize = priv->dma_rx_size; | |
2172 | unsigned int entry = priv->cur_rx % rxsize; | |
2173 | unsigned int next_entry; | |
2174 | unsigned int count = 0; | |
d2afb5bd | 2175 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2176 | |
83d7af64 GC |
2177 | if (netif_msg_rx_status(priv)) { |
2178 | pr_debug("%s: descriptor ring:\n", __func__); | |
c24602ef | 2179 | if (priv->extend_desc) |
ceb69499 | 2180 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef GC |
2181 | else |
2182 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
47dd7a54 | 2183 | } |
c24602ef | 2184 | while (count < limit) { |
47dd7a54 | 2185 | int status; |
9401bb5c | 2186 | struct dma_desc *p; |
47dd7a54 | 2187 | |
c24602ef | 2188 | if (priv->extend_desc) |
ceb69499 | 2189 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2190 | else |
ceb69499 | 2191 | p = priv->dma_rx + entry; |
c24602ef GC |
2192 | |
2193 | if (priv->hw->desc->get_rx_owner(p)) | |
47dd7a54 GC |
2194 | break; |
2195 | ||
2196 | count++; | |
2197 | ||
2198 | next_entry = (++priv->cur_rx) % rxsize; | |
c24602ef | 2199 | if (priv->extend_desc) |
9401bb5c | 2200 | prefetch(priv->dma_erx + next_entry); |
c24602ef | 2201 | else |
9401bb5c | 2202 | prefetch(priv->dma_rx + next_entry); |
47dd7a54 GC |
2203 | |
2204 | /* read the status of the incoming frame */ | |
c24602ef GC |
2205 | status = priv->hw->desc->rx_status(&priv->dev->stats, |
2206 | &priv->xstats, p); | |
2207 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) | |
2208 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2209 | &priv->xstats, | |
2210 | priv->dma_erx + | |
2211 | entry); | |
891434b1 | 2212 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2213 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2214 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2215 | /* DESC2 & DESC3 will be overwitten by device | |
2216 | * with timestamp value, hence reinitialize | |
2217 | * them in stmmac_rx_refill() function so that | |
2218 | * device can reuse it. | |
2219 | */ | |
2220 | priv->rx_skbuff[entry] = NULL; | |
2221 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2222 | priv->rx_skbuff_dma[entry], |
2223 | priv->dma_buf_sz, | |
2224 | DMA_FROM_DEVICE); | |
891434b1 RK |
2225 | } |
2226 | } else { | |
47dd7a54 | 2227 | struct sk_buff *skb; |
3eeb2997 | 2228 | int frame_len; |
47dd7a54 | 2229 | |
ceb69499 GC |
2230 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2231 | ||
e527c4a7 GC |
2232 | /* check if frame_len fits the preallocated memory */ |
2233 | if (frame_len > priv->dma_buf_sz) { | |
2234 | priv->dev->stats.rx_length_errors++; | |
2235 | break; | |
2236 | } | |
2237 | ||
3eeb2997 | 2238 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2239 | * Type frames (LLC/LLC-SNAP) |
2240 | */ | |
3eeb2997 GC |
2241 | if (unlikely(status != llc_snap)) |
2242 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2243 | |
83d7af64 | 2244 | if (netif_msg_rx_status(priv)) { |
47dd7a54 | 2245 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", |
ceb69499 | 2246 | p, entry, p->des2); |
83d7af64 GC |
2247 | if (frame_len > ETH_FRAME_LEN) |
2248 | pr_debug("\tframe size %d, COE: %d\n", | |
2249 | frame_len, status); | |
2250 | } | |
47dd7a54 GC |
2251 | skb = priv->rx_skbuff[entry]; |
2252 | if (unlikely(!skb)) { | |
2253 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
ceb69499 | 2254 | priv->dev->name); |
47dd7a54 GC |
2255 | priv->dev->stats.rx_dropped++; |
2256 | break; | |
2257 | } | |
2258 | prefetch(skb->data - NET_IP_ALIGN); | |
2259 | priv->rx_skbuff[entry] = NULL; | |
2260 | ||
891434b1 RK |
2261 | stmmac_get_rx_hwtstamp(priv, entry, skb); |
2262 | ||
47dd7a54 GC |
2263 | skb_put(skb, frame_len); |
2264 | dma_unmap_single(priv->device, | |
2265 | priv->rx_skbuff_dma[entry], | |
2266 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
83d7af64 | 2267 | |
47dd7a54 | 2268 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2269 | pr_debug("frame received (%dbytes)", frame_len); |
47dd7a54 GC |
2270 | print_pkt(skb->data, frame_len); |
2271 | } | |
83d7af64 | 2272 | |
b9381985 VB |
2273 | stmmac_rx_vlan(priv->dev, skb); |
2274 | ||
47dd7a54 GC |
2275 | skb->protocol = eth_type_trans(skb, priv->dev); |
2276 | ||
ceb69499 | 2277 | if (unlikely(!coe)) |
bc8acf2c | 2278 | skb_checksum_none_assert(skb); |
62a2ab93 | 2279 | else |
47dd7a54 | 2280 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2281 | |
2282 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2283 | |
2284 | priv->dev->stats.rx_packets++; | |
2285 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2286 | } |
2287 | entry = next_entry; | |
47dd7a54 GC |
2288 | } |
2289 | ||
2290 | stmmac_rx_refill(priv); | |
2291 | ||
2292 | priv->xstats.rx_pkt_n += count; | |
2293 | ||
2294 | return count; | |
2295 | } | |
2296 | ||
2297 | /** | |
2298 | * stmmac_poll - stmmac poll method (NAPI) | |
2299 | * @napi : pointer to the napi structure. | |
2300 | * @budget : maximum number of packets that the current CPU can receive from | |
2301 | * all interfaces. | |
2302 | * Description : | |
9125cdd1 | 2303 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2304 | */ |
2305 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2306 | { | |
2307 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2308 | int work_done = 0; | |
2309 | ||
9125cdd1 GC |
2310 | priv->xstats.napi_poll++; |
2311 | stmmac_tx_clean(priv); | |
47dd7a54 | 2312 | |
9125cdd1 | 2313 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2314 | if (work_done < budget) { |
2315 | napi_complete(napi); | |
9125cdd1 | 2316 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2317 | } |
2318 | return work_done; | |
2319 | } | |
2320 | ||
2321 | /** | |
2322 | * stmmac_tx_timeout | |
2323 | * @dev : Pointer to net device structure | |
2324 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2325 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2326 | * netdev structure and arrange for the device to be reset to a sane state |
2327 | * in order to transmit a new packet. | |
2328 | */ | |
2329 | static void stmmac_tx_timeout(struct net_device *dev) | |
2330 | { | |
2331 | struct stmmac_priv *priv = netdev_priv(dev); | |
2332 | ||
2333 | /* Clear Tx resources and restart transmitting again */ | |
2334 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2335 | } |
2336 | ||
47dd7a54 | 2337 | /** |
01789349 | 2338 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2339 | * @dev : pointer to the device structure |
2340 | * Description: | |
2341 | * This function is a driver entry point which gets called by the kernel | |
2342 | * whenever multicast addresses must be enabled/disabled. | |
2343 | * Return value: | |
2344 | * void. | |
2345 | */ | |
01789349 | 2346 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2347 | { |
2348 | struct stmmac_priv *priv = netdev_priv(dev); | |
2349 | ||
3b57de95 | 2350 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 GC |
2351 | } |
2352 | ||
2353 | /** | |
2354 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2355 | * @dev : device pointer. | |
2356 | * @new_mtu : the new MTU size for the device. | |
2357 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2358 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2359 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2360 | * Return value: | |
2361 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2362 | * file on failure. | |
2363 | */ | |
2364 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2365 | { | |
2366 | struct stmmac_priv *priv = netdev_priv(dev); | |
2367 | int max_mtu; | |
2368 | ||
2369 | if (netif_running(dev)) { | |
2370 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
2371 | return -EBUSY; | |
2372 | } | |
2373 | ||
48febf7e | 2374 | if (priv->plat->enh_desc) |
47dd7a54 GC |
2375 | max_mtu = JUMBO_LEN; |
2376 | else | |
45db81e1 | 2377 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 | 2378 | |
2618abb7 VB |
2379 | if (priv->plat->maxmtu < max_mtu) |
2380 | max_mtu = priv->plat->maxmtu; | |
2381 | ||
47dd7a54 GC |
2382 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { |
2383 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
2384 | return -EINVAL; | |
2385 | } | |
2386 | ||
5e982f3b MM |
2387 | dev->mtu = new_mtu; |
2388 | netdev_update_features(dev); | |
2389 | ||
2390 | return 0; | |
2391 | } | |
2392 | ||
c8f44aff | 2393 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2394 | netdev_features_t features) |
5e982f3b MM |
2395 | { |
2396 | struct stmmac_priv *priv = netdev_priv(dev); | |
2397 | ||
38912bdb | 2398 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2399 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2400 | |
5e982f3b | 2401 | if (!priv->plat->tx_coe) |
a188222b | 2402 | features &= ~NETIF_F_CSUM_MASK; |
5e982f3b | 2403 | |
ebbb293f GC |
2404 | /* Some GMAC devices have a bugged Jumbo frame support that |
2405 | * needs to have the Tx COE disabled for oversized frames | |
2406 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2407 | * the TX csum insertionin the TDES and not use SF. |
2408 | */ | |
5e982f3b | 2409 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
a188222b | 2410 | features &= ~NETIF_F_CSUM_MASK; |
ebbb293f | 2411 | |
5e982f3b | 2412 | return features; |
47dd7a54 GC |
2413 | } |
2414 | ||
d2afb5bd GC |
2415 | static int stmmac_set_features(struct net_device *netdev, |
2416 | netdev_features_t features) | |
2417 | { | |
2418 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2419 | ||
2420 | /* Keep the COE Type in case of csum is supporting */ | |
2421 | if (features & NETIF_F_RXCSUM) | |
2422 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2423 | else | |
2424 | priv->hw->rx_csum = 0; | |
2425 | /* No check needed because rx_coe has been set before and it will be | |
2426 | * fixed in case of issue. | |
2427 | */ | |
2428 | priv->hw->mac->rx_ipc(priv->hw); | |
2429 | ||
2430 | return 0; | |
2431 | } | |
2432 | ||
32ceabca GC |
2433 | /** |
2434 | * stmmac_interrupt - main ISR | |
2435 | * @irq: interrupt number. | |
2436 | * @dev_id: to pass the net device pointer. | |
2437 | * Description: this is the main driver interrupt service routine. | |
732fdf0e GC |
2438 | * It can call: |
2439 | * o DMA service routine (to manage incoming frame reception and transmission | |
2440 | * status) | |
2441 | * o Core interrupts to manage: remote wake-up, management counter, LPI | |
2442 | * interrupts. | |
32ceabca | 2443 | */ |
47dd7a54 GC |
2444 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2445 | { | |
2446 | struct net_device *dev = (struct net_device *)dev_id; | |
2447 | struct stmmac_priv *priv = netdev_priv(dev); | |
2448 | ||
89f7f2cf SK |
2449 | if (priv->irq_wake) |
2450 | pm_wakeup_event(priv->device, 0); | |
2451 | ||
47dd7a54 GC |
2452 | if (unlikely(!dev)) { |
2453 | pr_err("%s: invalid dev pointer\n", __func__); | |
2454 | return IRQ_NONE; | |
2455 | } | |
2456 | ||
d765955d GC |
2457 | /* To handle GMAC own interrupts */ |
2458 | if (priv->plat->has_gmac) { | |
7ed24bbe | 2459 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2460 | &priv->xstats); |
d765955d | 2461 | if (unlikely(status)) { |
d765955d | 2462 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2463 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2464 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2465 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2466 | priv->tx_path_in_lpi_mode = false; |
d765955d GC |
2467 | } |
2468 | } | |
aec7ff27 | 2469 | |
d765955d | 2470 | /* To handle DMA interrupts */ |
aec7ff27 | 2471 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2472 | |
2473 | return IRQ_HANDLED; | |
2474 | } | |
2475 | ||
2476 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2477 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2478 | * to allow network I/O with interrupts disabled. |
2479 | */ | |
47dd7a54 GC |
2480 | static void stmmac_poll_controller(struct net_device *dev) |
2481 | { | |
2482 | disable_irq(dev->irq); | |
2483 | stmmac_interrupt(dev->irq, dev); | |
2484 | enable_irq(dev->irq); | |
2485 | } | |
2486 | #endif | |
2487 | ||
2488 | /** | |
2489 | * stmmac_ioctl - Entry point for the Ioctl | |
2490 | * @dev: Device pointer. | |
2491 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2492 | * a proprietary structure used to pass information to the driver. | |
2493 | * @cmd: IOCTL command | |
2494 | * Description: | |
32ceabca | 2495 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2496 | */ |
2497 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2498 | { | |
2499 | struct stmmac_priv *priv = netdev_priv(dev); | |
891434b1 | 2500 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2501 | |
2502 | if (!netif_running(dev)) | |
2503 | return -EINVAL; | |
2504 | ||
891434b1 RK |
2505 | switch (cmd) { |
2506 | case SIOCGMIIPHY: | |
2507 | case SIOCGMIIREG: | |
2508 | case SIOCSMIIREG: | |
2509 | if (!priv->phydev) | |
2510 | return -EINVAL; | |
2511 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
2512 | break; | |
2513 | case SIOCSHWTSTAMP: | |
2514 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2515 | break; | |
2516 | default: | |
2517 | break; | |
2518 | } | |
28b04113 | 2519 | |
47dd7a54 GC |
2520 | return ret; |
2521 | } | |
2522 | ||
50fb4f74 | 2523 | #ifdef CONFIG_DEBUG_FS |
7ac29055 | 2524 | static struct dentry *stmmac_fs_dir; |
7ac29055 | 2525 | |
c24602ef | 2526 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2527 | struct seq_file *seq) |
7ac29055 | 2528 | { |
7ac29055 | 2529 | int i; |
ceb69499 GC |
2530 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2531 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2532 | |
c24602ef GC |
2533 | for (i = 0; i < size; i++) { |
2534 | u64 x; | |
2535 | if (extend_desc) { | |
2536 | x = *(u64 *) ep; | |
2537 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2538 | i, (unsigned int)virt_to_phys(ep), |
2539 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2540 | ep->basic.des2, ep->basic.des3); |
2541 | ep++; | |
2542 | } else { | |
2543 | x = *(u64 *) p; | |
2544 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2545 | i, (unsigned int)virt_to_phys(ep), |
2546 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2547 | p->des2, p->des3); |
2548 | p++; | |
2549 | } | |
7ac29055 GC |
2550 | seq_printf(seq, "\n"); |
2551 | } | |
c24602ef | 2552 | } |
7ac29055 | 2553 | |
c24602ef GC |
2554 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2555 | { | |
2556 | struct net_device *dev = seq->private; | |
2557 | struct stmmac_priv *priv = netdev_priv(dev); | |
2558 | unsigned int txsize = priv->dma_tx_size; | |
2559 | unsigned int rxsize = priv->dma_rx_size; | |
7ac29055 | 2560 | |
c24602ef GC |
2561 | if (priv->extend_desc) { |
2562 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
ceb69499 | 2563 | sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); |
c24602ef | 2564 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
ceb69499 | 2565 | sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); |
c24602ef GC |
2566 | } else { |
2567 | seq_printf(seq, "RX descriptor ring:\n"); | |
2568 | sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); | |
2569 | seq_printf(seq, "TX descriptor ring:\n"); | |
2570 | sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); | |
7ac29055 GC |
2571 | } |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2577 | { | |
2578 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2579 | } | |
2580 | ||
2581 | static const struct file_operations stmmac_rings_status_fops = { | |
2582 | .owner = THIS_MODULE, | |
2583 | .open = stmmac_sysfs_ring_open, | |
2584 | .read = seq_read, | |
2585 | .llseek = seq_lseek, | |
74863948 | 2586 | .release = single_release, |
7ac29055 GC |
2587 | }; |
2588 | ||
e7434821 GC |
2589 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2590 | { | |
2591 | struct net_device *dev = seq->private; | |
2592 | struct stmmac_priv *priv = netdev_priv(dev); | |
2593 | ||
19e30c14 | 2594 | if (!priv->hw_cap_support) { |
e7434821 GC |
2595 | seq_printf(seq, "DMA HW features not supported\n"); |
2596 | return 0; | |
2597 | } | |
2598 | ||
2599 | seq_printf(seq, "==============================\n"); | |
2600 | seq_printf(seq, "\tDMA HW features\n"); | |
2601 | seq_printf(seq, "==============================\n"); | |
2602 | ||
2603 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
2604 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
2605 | seq_printf(seq, "\t1000 Mbps %s\n", | |
2606 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
2607 | seq_printf(seq, "\tHalf duple %s\n", | |
2608 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
2609 | seq_printf(seq, "\tHash Filter: %s\n", | |
2610 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
2611 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
2612 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
2613 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
2614 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
2615 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
2616 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
2617 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
2618 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
2619 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
2620 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
2621 | seq_printf(seq, "\tRMON module: %s\n", | |
2622 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
2623 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
2624 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
2625 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
2626 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
2627 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
2628 | (priv->dma_cap.eee) ? "Y" : "N"); | |
2629 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
2630 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
2631 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
2632 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
2633 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
2634 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
2635 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
2636 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
2637 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
2638 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
2639 | priv->dma_cap.number_rx_channel); | |
2640 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
2641 | priv->dma_cap.number_tx_channel); | |
2642 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
2643 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
2644 | ||
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
2649 | { | |
2650 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
2651 | } | |
2652 | ||
2653 | static const struct file_operations stmmac_dma_cap_fops = { | |
2654 | .owner = THIS_MODULE, | |
2655 | .open = stmmac_sysfs_dma_cap_open, | |
2656 | .read = seq_read, | |
2657 | .llseek = seq_lseek, | |
74863948 | 2658 | .release = single_release, |
e7434821 GC |
2659 | }; |
2660 | ||
7ac29055 GC |
2661 | static int stmmac_init_fs(struct net_device *dev) |
2662 | { | |
466c5ac8 MO |
2663 | struct stmmac_priv *priv = netdev_priv(dev); |
2664 | ||
2665 | /* Create per netdev entries */ | |
2666 | priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); | |
7ac29055 | 2667 | |
466c5ac8 MO |
2668 | if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { |
2669 | pr_err("ERROR %s/%s, debugfs create directory failed\n", | |
2670 | STMMAC_RESOURCE_NAME, dev->name); | |
7ac29055 GC |
2671 | |
2672 | return -ENOMEM; | |
2673 | } | |
2674 | ||
2675 | /* Entry to report DMA RX/TX rings */ | |
466c5ac8 MO |
2676 | priv->dbgfs_rings_status = |
2677 | debugfs_create_file("descriptors_status", S_IRUGO, | |
2678 | priv->dbgfs_dir, dev, | |
2679 | &stmmac_rings_status_fops); | |
7ac29055 | 2680 | |
466c5ac8 | 2681 | if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { |
7ac29055 | 2682 | pr_info("ERROR creating stmmac ring debugfs file\n"); |
466c5ac8 | 2683 | debugfs_remove_recursive(priv->dbgfs_dir); |
7ac29055 GC |
2684 | |
2685 | return -ENOMEM; | |
2686 | } | |
2687 | ||
e7434821 | 2688 | /* Entry to report the DMA HW features */ |
466c5ac8 MO |
2689 | priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, |
2690 | priv->dbgfs_dir, | |
2691 | dev, &stmmac_dma_cap_fops); | |
e7434821 | 2692 | |
466c5ac8 | 2693 | if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { |
e7434821 | 2694 | pr_info("ERROR creating stmmac MMC debugfs file\n"); |
466c5ac8 | 2695 | debugfs_remove_recursive(priv->dbgfs_dir); |
e7434821 GC |
2696 | |
2697 | return -ENOMEM; | |
2698 | } | |
2699 | ||
7ac29055 GC |
2700 | return 0; |
2701 | } | |
2702 | ||
466c5ac8 | 2703 | static void stmmac_exit_fs(struct net_device *dev) |
7ac29055 | 2704 | { |
466c5ac8 MO |
2705 | struct stmmac_priv *priv = netdev_priv(dev); |
2706 | ||
2707 | debugfs_remove_recursive(priv->dbgfs_dir); | |
7ac29055 | 2708 | } |
50fb4f74 | 2709 | #endif /* CONFIG_DEBUG_FS */ |
7ac29055 | 2710 | |
47dd7a54 GC |
2711 | static const struct net_device_ops stmmac_netdev_ops = { |
2712 | .ndo_open = stmmac_open, | |
2713 | .ndo_start_xmit = stmmac_xmit, | |
2714 | .ndo_stop = stmmac_release, | |
2715 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 2716 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 2717 | .ndo_set_features = stmmac_set_features, |
01789349 | 2718 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
2719 | .ndo_tx_timeout = stmmac_tx_timeout, |
2720 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
2721 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2722 | .ndo_poll_controller = stmmac_poll_controller, | |
2723 | #endif | |
2724 | .ndo_set_mac_address = eth_mac_addr, | |
2725 | }; | |
2726 | ||
cf3f047b GC |
2727 | /** |
2728 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 2729 | * @priv: driver private structure |
732fdf0e GC |
2730 | * Description: this function is to configure the MAC device according to |
2731 | * some platform parameters or the HW capability register. It prepares the | |
2732 | * driver to use either ring or chain modes and to setup either enhanced or | |
2733 | * normal descriptors. | |
cf3f047b GC |
2734 | */ |
2735 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
2736 | { | |
cf3f047b GC |
2737 | struct mac_device_info *mac; |
2738 | ||
2739 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
2740 | if (priv->plat->has_gmac) { |
2741 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
2742 | mac = dwmac1000_setup(priv->ioaddr, |
2743 | priv->plat->multicast_filter_bins, | |
2744 | priv->plat->unicast_filter_entries); | |
03f2eecd | 2745 | } else { |
cf3f047b | 2746 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 2747 | } |
cf3f047b GC |
2748 | if (!mac) |
2749 | return -ENOMEM; | |
2750 | ||
2751 | priv->hw = mac; | |
2752 | ||
cf3f047b | 2753 | /* Get and dump the chip ID */ |
cffb13f4 | 2754 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b | 2755 | |
4a7d666a | 2756 | /* To use the chained or ring mode */ |
ceb69499 | 2757 | if (chain_mode) { |
29896a67 | 2758 | priv->hw->mode = &chain_mode_ops; |
4a7d666a GC |
2759 | pr_info(" Chain mode enabled\n"); |
2760 | priv->mode = STMMAC_CHAIN_MODE; | |
2761 | } else { | |
29896a67 | 2762 | priv->hw->mode = &ring_mode_ops; |
4a7d666a GC |
2763 | pr_info(" Ring mode enabled\n"); |
2764 | priv->mode = STMMAC_RING_MODE; | |
2765 | } | |
2766 | ||
cf3f047b GC |
2767 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
2768 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
2769 | if (priv->hw_cap_support) { | |
2770 | pr_info(" DMA HW capability register supported"); | |
2771 | ||
2772 | /* We can override some gmac/dma configuration fields: e.g. | |
2773 | * enh_desc, tx_coe (e.g. that are passed through the | |
2774 | * platform) with the values from the HW capability | |
2775 | * register (if supported). | |
2776 | */ | |
2777 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 2778 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb | 2779 | |
dec2165f SZ |
2780 | /* TXCOE doesn't work in thresh DMA mode */ |
2781 | if (priv->plat->force_thresh_dma_mode) | |
2782 | priv->plat->tx_coe = 0; | |
2783 | else | |
2784 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
38912bdb DS |
2785 | |
2786 | if (priv->dma_cap.rx_coe_type2) | |
2787 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
2788 | else if (priv->dma_cap.rx_coe_type1) | |
2789 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
2790 | ||
cf3f047b GC |
2791 | } else |
2792 | pr_info(" No HW DMA feature register supported"); | |
2793 | ||
61369d02 BA |
2794 | /* To use alternate (extended) or normal descriptor structures */ |
2795 | stmmac_selec_desc_mode(priv); | |
2796 | ||
d2afb5bd GC |
2797 | if (priv->plat->rx_coe) { |
2798 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38912bdb DS |
2799 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", |
2800 | priv->plat->rx_coe); | |
d2afb5bd | 2801 | } |
cf3f047b GC |
2802 | if (priv->plat->tx_coe) |
2803 | pr_info(" TX Checksum insertion supported\n"); | |
2804 | ||
2805 | if (priv->plat->pmt) { | |
2806 | pr_info(" Wake-Up On Lan supported\n"); | |
2807 | device_set_wakeup_capable(priv->device, 1); | |
2808 | } | |
2809 | ||
c24602ef | 2810 | return 0; |
cf3f047b GC |
2811 | } |
2812 | ||
47dd7a54 | 2813 | /** |
bfab27a1 GC |
2814 | * stmmac_dvr_probe |
2815 | * @device: device pointer | |
ff3dd78c | 2816 | * @plat_dat: platform data pointer |
e56788cf | 2817 | * @res: stmmac resource pointer |
bfab27a1 GC |
2818 | * Description: this is the main probe function used to |
2819 | * call the alloc_etherdev, allocate the priv structure. | |
9afec6ef | 2820 | * Return: |
15ffac73 | 2821 | * returns 0 on success, otherwise errno. |
47dd7a54 | 2822 | */ |
15ffac73 JE |
2823 | int stmmac_dvr_probe(struct device *device, |
2824 | struct plat_stmmacenet_data *plat_dat, | |
2825 | struct stmmac_resources *res) | |
47dd7a54 GC |
2826 | { |
2827 | int ret = 0; | |
bfab27a1 GC |
2828 | struct net_device *ndev = NULL; |
2829 | struct stmmac_priv *priv; | |
47dd7a54 | 2830 | |
bfab27a1 | 2831 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 2832 | if (!ndev) |
15ffac73 | 2833 | return -ENOMEM; |
bfab27a1 GC |
2834 | |
2835 | SET_NETDEV_DEV(ndev, device); | |
2836 | ||
2837 | priv = netdev_priv(ndev); | |
2838 | priv->device = device; | |
2839 | priv->dev = ndev; | |
47dd7a54 | 2840 | |
bfab27a1 | 2841 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
2842 | priv->pause = pause; |
2843 | priv->plat = plat_dat; | |
e56788cf JE |
2844 | priv->ioaddr = res->addr; |
2845 | priv->dev->base_addr = (unsigned long)res->addr; | |
2846 | ||
2847 | priv->dev->irq = res->irq; | |
2848 | priv->wol_irq = res->wol_irq; | |
2849 | priv->lpi_irq = res->lpi_irq; | |
2850 | ||
2851 | if (res->mac) | |
2852 | memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); | |
cf3f047b | 2853 | |
a7a62685 | 2854 | dev_set_drvdata(device, priv->dev); |
803f8fc4 | 2855 | |
cf3f047b GC |
2856 | /* Verify driver arguments */ |
2857 | stmmac_verify_args(); | |
bfab27a1 | 2858 | |
cf3f047b | 2859 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
2860 | * this needs to have multiple instances |
2861 | */ | |
cf3f047b GC |
2862 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
2863 | priv->plat->phy_addr = phyaddr; | |
2864 | ||
62866e98 CYT |
2865 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
2866 | if (IS_ERR(priv->stmmac_clk)) { | |
2867 | dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", | |
2868 | __func__); | |
c5bb86c3 KHL |
2869 | /* If failed to obtain stmmac_clk and specific clk_csr value |
2870 | * is NOT passed from the platform, probe fail. | |
2871 | */ | |
2872 | if (!priv->plat->clk_csr) { | |
2873 | ret = PTR_ERR(priv->stmmac_clk); | |
2874 | goto error_clk_get; | |
2875 | } else { | |
2876 | priv->stmmac_clk = NULL; | |
2877 | } | |
62866e98 CYT |
2878 | } |
2879 | clk_prepare_enable(priv->stmmac_clk); | |
2880 | ||
5f9755d2 AB |
2881 | priv->pclk = devm_clk_get(priv->device, "pclk"); |
2882 | if (IS_ERR(priv->pclk)) { | |
2883 | if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { | |
2884 | ret = -EPROBE_DEFER; | |
2885 | goto error_pclk_get; | |
2886 | } | |
2887 | priv->pclk = NULL; | |
2888 | } | |
2889 | clk_prepare_enable(priv->pclk); | |
2890 | ||
c5e4ddbd CYT |
2891 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
2892 | STMMAC_RESOURCE_NAME); | |
2893 | if (IS_ERR(priv->stmmac_rst)) { | |
2894 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
2895 | ret = -EPROBE_DEFER; | |
2896 | goto error_hw_init; | |
2897 | } | |
2898 | dev_info(priv->device, "no reset control found\n"); | |
2899 | priv->stmmac_rst = NULL; | |
2900 | } | |
2901 | if (priv->stmmac_rst) | |
2902 | reset_control_deassert(priv->stmmac_rst); | |
2903 | ||
cf3f047b | 2904 | /* Init MAC and get the capabilities */ |
c24602ef GC |
2905 | ret = stmmac_hw_init(priv); |
2906 | if (ret) | |
62866e98 | 2907 | goto error_hw_init; |
cf3f047b GC |
2908 | |
2909 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 2910 | |
cf3f047b GC |
2911 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2912 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
2913 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
2914 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
2915 | #ifdef STMMAC_VLAN_TAG_USED |
2916 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 2917 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
2918 | #endif |
2919 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
2920 | ||
47dd7a54 GC |
2921 | if (flow_ctrl) |
2922 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
2923 | ||
62a2ab93 GC |
2924 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
2925 | * In some case, for example on bugged HW this feature | |
2926 | * has to be disable and this can be done by passing the | |
2927 | * riwt_off field from the platform. | |
2928 | */ | |
2929 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
2930 | priv->use_riwt = 1; | |
2931 | pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); | |
2932 | } | |
2933 | ||
bfab27a1 | 2934 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 2935 | |
f8e96161 | 2936 | spin_lock_init(&priv->lock); |
a9097a96 | 2937 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 2938 | |
bfab27a1 | 2939 | ret = register_netdev(ndev); |
47dd7a54 | 2940 | if (ret) { |
cf3f047b | 2941 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
6a81c26f | 2942 | goto error_netdev_register; |
47dd7a54 GC |
2943 | } |
2944 | ||
cd7201f4 GC |
2945 | /* If a specific clk_csr value is passed from the platform |
2946 | * this means that the CSR Clock Range selection cannot be | |
2947 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
2948 | * set the MDC clock dynamically according to the csr actual | |
2949 | * clock input. | |
2950 | */ | |
2951 | if (!priv->plat->clk_csr) | |
2952 | stmmac_clk_csr_set(priv); | |
2953 | else | |
2954 | priv->clk_csr = priv->plat->clk_csr; | |
2955 | ||
e58bb43f GC |
2956 | stmmac_check_pcs_mode(priv); |
2957 | ||
4d8f0825 BA |
2958 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2959 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
2960 | /* MDIO bus Registration */ |
2961 | ret = stmmac_mdio_register(ndev); | |
2962 | if (ret < 0) { | |
2963 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
2964 | __func__, priv->plat->bus_id); | |
2965 | goto error_mdio_register; | |
2966 | } | |
4bfcbd7a FV |
2967 | } |
2968 | ||
15ffac73 | 2969 | return 0; |
47dd7a54 | 2970 | |
6a81c26f | 2971 | error_mdio_register: |
34a52f36 | 2972 | unregister_netdev(ndev); |
6a81c26f VK |
2973 | error_netdev_register: |
2974 | netif_napi_del(&priv->napi); | |
62866e98 | 2975 | error_hw_init: |
5f9755d2 AB |
2976 | clk_disable_unprepare(priv->pclk); |
2977 | error_pclk_get: | |
62866e98 CYT |
2978 | clk_disable_unprepare(priv->stmmac_clk); |
2979 | error_clk_get: | |
34a52f36 | 2980 | free_netdev(ndev); |
47dd7a54 | 2981 | |
15ffac73 | 2982 | return ret; |
47dd7a54 | 2983 | } |
b2e2f0c7 | 2984 | EXPORT_SYMBOL_GPL(stmmac_dvr_probe); |
47dd7a54 GC |
2985 | |
2986 | /** | |
2987 | * stmmac_dvr_remove | |
bfab27a1 | 2988 | * @ndev: net device pointer |
47dd7a54 | 2989 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 2990 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 2991 | */ |
bfab27a1 | 2992 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 2993 | { |
aec7ff27 | 2994 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
2995 | |
2996 | pr_info("%s:\n\tremoving driver", __func__); | |
2997 | ||
ad01b7d4 GC |
2998 | priv->hw->dma->stop_rx(priv->ioaddr); |
2999 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 3000 | |
bfab27a1 | 3001 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 | 3002 | netif_carrier_off(ndev); |
47dd7a54 | 3003 | unregister_netdev(ndev); |
c5e4ddbd CYT |
3004 | if (priv->stmmac_rst) |
3005 | reset_control_assert(priv->stmmac_rst); | |
5f9755d2 | 3006 | clk_disable_unprepare(priv->pclk); |
62866e98 | 3007 | clk_disable_unprepare(priv->stmmac_clk); |
e743471f BD |
3008 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
3009 | priv->pcs != STMMAC_PCS_RTBI) | |
3010 | stmmac_mdio_unregister(ndev); | |
47dd7a54 GC |
3011 | free_netdev(ndev); |
3012 | ||
3013 | return 0; | |
3014 | } | |
b2e2f0c7 | 3015 | EXPORT_SYMBOL_GPL(stmmac_dvr_remove); |
47dd7a54 | 3016 | |
732fdf0e GC |
3017 | /** |
3018 | * stmmac_suspend - suspend callback | |
3019 | * @ndev: net device pointer | |
3020 | * Description: this is the function to suspend the device and it is called | |
3021 | * by the platform driver to stop the network queue, release the resources, | |
3022 | * program the PMT register (for WoL), clean and release driver resources. | |
3023 | */ | |
bfab27a1 | 3024 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 3025 | { |
874bd42d | 3026 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3027 | unsigned long flags; |
47dd7a54 | 3028 | |
874bd42d | 3029 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
3030 | return 0; |
3031 | ||
102463b1 FV |
3032 | if (priv->phydev) |
3033 | phy_stop(priv->phydev); | |
3034 | ||
f8c5a875 | 3035 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 3036 | |
874bd42d GC |
3037 | netif_device_detach(ndev); |
3038 | netif_stop_queue(ndev); | |
47dd7a54 | 3039 | |
874bd42d GC |
3040 | napi_disable(&priv->napi); |
3041 | ||
3042 | /* Stop TX/RX DMA */ | |
3043 | priv->hw->dma->stop_tx(priv->ioaddr); | |
3044 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef | 3045 | |
874bd42d | 3046 | /* Enable Power down mode by programming the PMT regs */ |
89f7f2cf | 3047 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3048 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
3049 | priv->irq_wake = 1; |
3050 | } else { | |
bfab27a1 | 3051 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 3052 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 3053 | /* Disable clock in case of PWM is off */ |
5f9755d2 | 3054 | clk_disable(priv->pclk); |
777da230 | 3055 | clk_disable(priv->stmmac_clk); |
ba1377ff | 3056 | } |
f8c5a875 | 3057 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
3058 | |
3059 | priv->oldlink = 0; | |
3060 | priv->speed = 0; | |
3061 | priv->oldduplex = -1; | |
47dd7a54 GC |
3062 | return 0; |
3063 | } | |
b2e2f0c7 | 3064 | EXPORT_SYMBOL_GPL(stmmac_suspend); |
47dd7a54 | 3065 | |
732fdf0e GC |
3066 | /** |
3067 | * stmmac_resume - resume callback | |
3068 | * @ndev: net device pointer | |
3069 | * Description: when resume this function is invoked to setup the DMA and CORE | |
3070 | * in a usable state. | |
3071 | */ | |
bfab27a1 | 3072 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 3073 | { |
874bd42d | 3074 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3075 | unsigned long flags; |
47dd7a54 | 3076 | |
874bd42d | 3077 | if (!netif_running(ndev)) |
47dd7a54 GC |
3078 | return 0; |
3079 | ||
f8c5a875 | 3080 | spin_lock_irqsave(&priv->lock, flags); |
c4433be6 | 3081 | |
47dd7a54 GC |
3082 | /* Power Down bit, into the PM register, is cleared |
3083 | * automatically as soon as a magic packet or a Wake-up frame | |
3084 | * is received. Anyway, it's better to manually clear | |
3085 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
3086 | * from another devices (e.g. serial console). |
3087 | */ | |
623997fb | 3088 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3089 | priv->hw->mac->pmt(priv->hw, 0); |
89f7f2cf | 3090 | priv->irq_wake = 0; |
623997fb | 3091 | } else { |
db88f10a | 3092 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 3093 | /* enable the clk prevously disabled */ |
777da230 | 3094 | clk_enable(priv->stmmac_clk); |
5f9755d2 | 3095 | clk_enable(priv->pclk); |
623997fb SK |
3096 | /* reset the phy so that it's ready */ |
3097 | if (priv->mii) | |
3098 | stmmac_mdio_reset(priv->mii); | |
3099 | } | |
47dd7a54 | 3100 | |
874bd42d | 3101 | netif_device_attach(ndev); |
47dd7a54 | 3102 | |
ae79a639 GC |
3103 | priv->cur_rx = 0; |
3104 | priv->dirty_rx = 0; | |
3105 | priv->dirty_tx = 0; | |
3106 | priv->cur_tx = 0; | |
3107 | stmmac_clear_descriptors(priv); | |
3108 | ||
fe131929 | 3109 | stmmac_hw_setup(ndev, false); |
777da230 | 3110 | stmmac_init_tx_coalesce(priv); |
ac316c78 | 3111 | stmmac_set_rx_mode(ndev); |
47dd7a54 | 3112 | |
47dd7a54 GC |
3113 | napi_enable(&priv->napi); |
3114 | ||
874bd42d | 3115 | netif_start_queue(ndev); |
47dd7a54 | 3116 | |
f8c5a875 | 3117 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 FV |
3118 | |
3119 | if (priv->phydev) | |
3120 | phy_start(priv->phydev); | |
3121 | ||
47dd7a54 GC |
3122 | return 0; |
3123 | } | |
b2e2f0c7 | 3124 | EXPORT_SYMBOL_GPL(stmmac_resume); |
ba27ec66 | 3125 | |
47dd7a54 GC |
3126 | #ifndef MODULE |
3127 | static int __init stmmac_cmdline_opt(char *str) | |
3128 | { | |
3129 | char *opt; | |
3130 | ||
3131 | if (!str || !*str) | |
3132 | return -EINVAL; | |
3133 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3134 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3135 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3136 | goto err; |
3137 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3138 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 GC |
3139 | goto err; |
3140 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
ea2ab871 | 3141 | if (kstrtoint(opt + 11, 0, &dma_txsize)) |
f3240e28 GC |
3142 | goto err; |
3143 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
ea2ab871 | 3144 | if (kstrtoint(opt + 11, 0, &dma_rxsize)) |
f3240e28 GC |
3145 | goto err; |
3146 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
ea2ab871 | 3147 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3148 | goto err; |
3149 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3150 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3151 | goto err; |
3152 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3153 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3154 | goto err; |
3155 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3156 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3157 | goto err; |
3158 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3159 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3160 | goto err; |
506f669c | 3161 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3162 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3163 | goto err; | |
4a7d666a GC |
3164 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3165 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3166 | goto err; | |
f3240e28 | 3167 | } |
47dd7a54 GC |
3168 | } |
3169 | return 0; | |
f3240e28 GC |
3170 | |
3171 | err: | |
3172 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3173 | return -EINVAL; | |
47dd7a54 GC |
3174 | } |
3175 | ||
3176 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3177 | #endif /* MODULE */ |
6fc0d0f2 | 3178 | |
466c5ac8 MO |
3179 | static int __init stmmac_init(void) |
3180 | { | |
3181 | #ifdef CONFIG_DEBUG_FS | |
3182 | /* Create debugfs main directory if it doesn't exist yet */ | |
3183 | if (!stmmac_fs_dir) { | |
3184 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
3185 | ||
3186 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
3187 | pr_err("ERROR %s, debugfs create directory failed\n", | |
3188 | STMMAC_RESOURCE_NAME); | |
3189 | ||
3190 | return -ENOMEM; | |
3191 | } | |
3192 | } | |
3193 | #endif | |
3194 | ||
3195 | return 0; | |
3196 | } | |
3197 | ||
3198 | static void __exit stmmac_exit(void) | |
3199 | { | |
3200 | #ifdef CONFIG_DEBUG_FS | |
3201 | debugfs_remove_recursive(stmmac_fs_dir); | |
3202 | #endif | |
3203 | } | |
3204 | ||
3205 | module_init(stmmac_init) | |
3206 | module_exit(stmmac_exit) | |
3207 | ||
6fc0d0f2 GC |
3208 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); |
3209 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3210 | MODULE_LICENSE("GPL"); |