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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
7ac29055 GC |
47 | #ifdef CONFIG_STMMAC_DEBUG_FS |
48 | #include <linux/debugfs.h> | |
49 | #include <linux/seq_file.h> | |
ceb69499 | 50 | #endif /* CONFIG_STMMAC_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
47dd7a54 | 55 | |
47dd7a54 | 56 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
47dd7a54 GC |
57 | |
58 | /* Module parameters */ | |
32ceabca | 59 | #define TX_TIMEO 5000 |
47dd7a54 GC |
60 | static int watchdog = TX_TIMEO; |
61 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 62 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 63 | |
32ceabca | 64 | static int debug = -1; |
47dd7a54 | 65 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 66 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 67 | |
47d1f71f | 68 | static int phyaddr = -1; |
47dd7a54 GC |
69 | module_param(phyaddr, int, S_IRUGO); |
70 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
71 | ||
72 | #define DMA_TX_SIZE 256 | |
73 | static int dma_txsize = DMA_TX_SIZE; | |
74 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
75 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
76 | ||
77 | #define DMA_RX_SIZE 256 | |
78 | static int dma_rxsize = DMA_RX_SIZE; | |
79 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
80 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
81 | ||
82 | static int flow_ctrl = FLOW_OFF; | |
83 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
85 | ||
86 | static int pause = PAUSE_TIME; | |
87 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
88 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
89 | ||
90 | #define TC_DEFAULT 64 | |
91 | static int tc = TC_DEFAULT; | |
92 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
93 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
94 | ||
d916701c GC |
95 | #define DEFAULT_BUFSIZE 1536 |
96 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
97 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
98 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
99 | ||
47dd7a54 GC |
100 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
101 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
102 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
103 | ||
d765955d GC |
104 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
105 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
106 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
107 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 108 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 109 | |
4a7d666a GC |
110 | /* By default the driver will use the ring mode to manage tx and rx descriptors |
111 | * but passing this value so user can force to use the chain instead of the ring | |
112 | */ | |
113 | static unsigned int chain_mode; | |
114 | module_param(chain_mode, int, S_IRUGO); | |
115 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
116 | ||
47dd7a54 | 117 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 118 | |
bfab27a1 GC |
119 | #ifdef CONFIG_STMMAC_DEBUG_FS |
120 | static int stmmac_init_fs(struct net_device *dev); | |
121 | static void stmmac_exit_fs(void); | |
122 | #endif | |
123 | ||
9125cdd1 GC |
124 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
125 | ||
47dd7a54 GC |
126 | /** |
127 | * stmmac_verify_args - verify the driver parameters. | |
128 | * Description: it verifies if some wrong parameter is passed to the driver. | |
129 | * Note that wrong parameters are replaced with the default values. | |
130 | */ | |
131 | static void stmmac_verify_args(void) | |
132 | { | |
133 | if (unlikely(watchdog < 0)) | |
134 | watchdog = TX_TIMEO; | |
135 | if (unlikely(dma_rxsize < 0)) | |
136 | dma_rxsize = DMA_RX_SIZE; | |
137 | if (unlikely(dma_txsize < 0)) | |
138 | dma_txsize = DMA_TX_SIZE; | |
d916701c GC |
139 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
140 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
141 | if (unlikely(flow_ctrl > 1)) |
142 | flow_ctrl = FLOW_AUTO; | |
143 | else if (likely(flow_ctrl < 0)) | |
144 | flow_ctrl = FLOW_OFF; | |
145 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
146 | pause = PAUSE_TIME; | |
d765955d GC |
147 | if (eee_timer < 0) |
148 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
149 | } |
150 | ||
32ceabca GC |
151 | /** |
152 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
153 | * @priv: driver private structure | |
154 | * Description: this is to dynamically set the MDC clock according to the csr | |
155 | * clock input. | |
156 | * Note: | |
157 | * If a specific clk_csr value is passed from the platform | |
158 | * this means that the CSR Clock Range selection cannot be | |
159 | * changed at run-time and it is fixed (as reported in the driver | |
160 | * documentation). Viceversa the driver will try to set the MDC | |
161 | * clock dynamically according to the actual clock input. | |
162 | */ | |
cd7201f4 GC |
163 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
164 | { | |
cd7201f4 GC |
165 | u32 clk_rate; |
166 | ||
167 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
168 | ||
169 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
170 | * for all other cases except for the below mentioned ones. |
171 | * For values higher than the IEEE 802.3 specified frequency | |
172 | * we can not estimate the proper divider as it is not known | |
173 | * the frequency of clk_csr_i. So we do not change the default | |
174 | * divider. | |
175 | */ | |
cd7201f4 GC |
176 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
177 | if (clk_rate < CSR_F_35M) | |
178 | priv->clk_csr = STMMAC_CSR_20_35M; | |
179 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
180 | priv->clk_csr = STMMAC_CSR_35_60M; | |
181 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
182 | priv->clk_csr = STMMAC_CSR_60_100M; | |
183 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
184 | priv->clk_csr = STMMAC_CSR_100_150M; | |
185 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
186 | priv->clk_csr = STMMAC_CSR_150_250M; | |
187 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) | |
188 | priv->clk_csr = STMMAC_CSR_250_300M; | |
ceb69499 | 189 | } |
cd7201f4 GC |
190 | } |
191 | ||
47dd7a54 GC |
192 | static void print_pkt(unsigned char *buf, int len) |
193 | { | |
194 | int j; | |
83d7af64 | 195 | pr_debug("len = %d byte, buf addr: 0x%p", len, buf); |
47dd7a54 GC |
196 | for (j = 0; j < len; j++) { |
197 | if ((j % 16) == 0) | |
83d7af64 GC |
198 | pr_debug("\n %03x:", j); |
199 | pr_debug(" %02x", buf[j]); | |
47dd7a54 | 200 | } |
83d7af64 | 201 | pr_debug("\n"); |
47dd7a54 | 202 | } |
47dd7a54 GC |
203 | |
204 | /* minimum number of free TX descriptors required to wake up TX process */ | |
205 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
206 | ||
207 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
208 | { | |
209 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
210 | } | |
211 | ||
32ceabca GC |
212 | /** |
213 | * stmmac_hw_fix_mac_speed: callback for speed selection | |
214 | * @priv: driver private structure | |
215 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
216 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
217 | */ |
218 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
219 | { | |
220 | struct phy_device *phydev = priv->phydev; | |
221 | ||
222 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 223 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
224 | } |
225 | ||
32ceabca GC |
226 | /** |
227 | * stmmac_enable_eee_mode: Check and enter in LPI mode | |
228 | * @priv: driver private structure | |
229 | * Description: this function is to verify and enter in LPI mode for EEE. | |
230 | */ | |
d765955d GC |
231 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
232 | { | |
233 | /* Check and enter in LPI mode */ | |
234 | if ((priv->dirty_tx == priv->cur_tx) && | |
235 | (priv->tx_path_in_lpi_mode == false)) | |
7ed24bbe | 236 | priv->hw->mac->set_eee_mode(priv->hw); |
d765955d GC |
237 | } |
238 | ||
32ceabca GC |
239 | /** |
240 | * stmmac_disable_eee_mode: disable/exit from EEE | |
241 | * @priv: driver private structure | |
242 | * Description: this function is to exit and disable EEE in case of | |
243 | * LPI state is true. This is called by the xmit. | |
244 | */ | |
d765955d GC |
245 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
246 | { | |
7ed24bbe | 247 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
248 | del_timer_sync(&priv->eee_ctrl_timer); |
249 | priv->tx_path_in_lpi_mode = false; | |
250 | } | |
251 | ||
252 | /** | |
32ceabca | 253 | * stmmac_eee_ctrl_timer: EEE TX SW timer. |
d765955d GC |
254 | * @arg : data hook |
255 | * Description: | |
32ceabca | 256 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
257 | * then MAC Transmitter can be moved to LPI state. |
258 | */ | |
259 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
260 | { | |
261 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
262 | ||
263 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 264 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
265 | } |
266 | ||
267 | /** | |
32ceabca GC |
268 | * stmmac_eee_init: init EEE |
269 | * @priv: driver private structure | |
d765955d GC |
270 | * Description: |
271 | * If the EEE support has been enabled while configuring the driver, | |
272 | * if the GMAC actually supports the EEE (from the HW cap reg) and the | |
273 | * phy can also manage EEE, so enable the LPI state and start the timer | |
274 | * to verify if the tx path can enter in LPI state. | |
275 | */ | |
276 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
277 | { | |
56b88c25 | 278 | char *phy_bus_name = priv->plat->phy_bus_name; |
d765955d GC |
279 | bool ret = false; |
280 | ||
f5351ef7 GC |
281 | /* Using PCS we cannot dial with the phy registers at this stage |
282 | * so we do not support extra feature like EEE. | |
283 | */ | |
284 | if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || | |
285 | (priv->pcs == STMMAC_PCS_RTBI)) | |
286 | goto out; | |
287 | ||
56b88c25 GC |
288 | /* Never init EEE in case of a switch is attached */ |
289 | if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) | |
290 | goto out; | |
291 | ||
d765955d GC |
292 | /* MAC core supports the EEE feature. */ |
293 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
294 | int tx_lpi_timer = priv->tx_lpi_timer; |
295 | ||
d765955d | 296 | /* Check if the PHY supports EEE */ |
83bf79b6 GC |
297 | if (phy_init_eee(priv->phydev, 1)) { |
298 | /* To manage at run-time if the EEE cannot be supported | |
299 | * anymore (for example because the lp caps have been | |
300 | * changed). | |
301 | * In that case the driver disable own timers. | |
302 | */ | |
303 | if (priv->eee_active) { | |
304 | pr_debug("stmmac: disable EEE\n"); | |
305 | del_timer_sync(&priv->eee_ctrl_timer); | |
7ed24bbe | 306 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
307 | tx_lpi_timer); |
308 | } | |
309 | priv->eee_active = 0; | |
d765955d | 310 | goto out; |
83bf79b6 GC |
311 | } |
312 | /* Activate the EEE and start timers */ | |
f5351ef7 GC |
313 | if (!priv->eee_active) { |
314 | priv->eee_active = 1; | |
315 | init_timer(&priv->eee_ctrl_timer); | |
316 | priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; | |
317 | priv->eee_ctrl_timer.data = (unsigned long)priv; | |
318 | priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); | |
319 | add_timer(&priv->eee_ctrl_timer); | |
320 | ||
7ed24bbe | 321 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 322 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 323 | tx_lpi_timer); |
71965352 GC |
324 | } |
325 | /* Set HW EEE according to the speed */ | |
326 | priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); | |
d765955d | 327 | |
83bf79b6 | 328 | pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); |
d765955d GC |
329 | |
330 | ret = true; | |
331 | } | |
332 | out: | |
333 | return ret; | |
334 | } | |
335 | ||
32ceabca GC |
336 | /* stmmac_get_tx_hwtstamp: get HW TX timestamps |
337 | * @priv: driver private structure | |
891434b1 RK |
338 | * @entry : descriptor index to be used. |
339 | * @skb : the socket buffer | |
340 | * Description : | |
341 | * This function will read timestamp from the descriptor & pass it to stack. | |
342 | * and also perform some sanity checks. | |
343 | */ | |
344 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 345 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
346 | { |
347 | struct skb_shared_hwtstamps shhwtstamp; | |
348 | u64 ns; | |
349 | void *desc = NULL; | |
350 | ||
351 | if (!priv->hwts_tx_en) | |
352 | return; | |
353 | ||
ceb69499 | 354 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 355 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
356 | return; |
357 | ||
358 | if (priv->adv_ts) | |
359 | desc = (priv->dma_etx + entry); | |
360 | else | |
361 | desc = (priv->dma_tx + entry); | |
362 | ||
363 | /* check tx tstamp status */ | |
364 | if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) | |
365 | return; | |
366 | ||
367 | /* get the valid tstamp */ | |
368 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
369 | ||
370 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
371 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
372 | /* pass tstamp to stack */ | |
373 | skb_tstamp_tx(skb, &shhwtstamp); | |
374 | ||
375 | return; | |
376 | } | |
377 | ||
32ceabca GC |
378 | /* stmmac_get_rx_hwtstamp: get HW RX timestamps |
379 | * @priv: driver private structure | |
891434b1 RK |
380 | * @entry : descriptor index to be used. |
381 | * @skb : the socket buffer | |
382 | * Description : | |
383 | * This function will read received packet's timestamp from the descriptor | |
384 | * and pass it to stack. It also perform some sanity checks. | |
385 | */ | |
386 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 387 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
388 | { |
389 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
390 | u64 ns; | |
391 | void *desc = NULL; | |
392 | ||
393 | if (!priv->hwts_rx_en) | |
394 | return; | |
395 | ||
396 | if (priv->adv_ts) | |
397 | desc = (priv->dma_erx + entry); | |
398 | else | |
399 | desc = (priv->dma_rx + entry); | |
400 | ||
ceb69499 | 401 | /* exit if rx tstamp is not valid */ |
891434b1 RK |
402 | if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) |
403 | return; | |
404 | ||
405 | /* get valid tstamp */ | |
406 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
407 | shhwtstamp = skb_hwtstamps(skb); | |
408 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
409 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
410 | } | |
411 | ||
412 | /** | |
413 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
414 | * @dev: device pointer. | |
415 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
416 | * a proprietary structure used to pass information to the driver. | |
417 | * Description: | |
418 | * This function configures the MAC to enable/disable both outgoing(TX) | |
419 | * and incoming(RX) packets time stamping based on user input. | |
420 | * Return Value: | |
421 | * 0 on success and an appropriate -ve integer on failure. | |
422 | */ | |
423 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
424 | { | |
425 | struct stmmac_priv *priv = netdev_priv(dev); | |
426 | struct hwtstamp_config config; | |
427 | struct timespec now; | |
428 | u64 temp = 0; | |
429 | u32 ptp_v2 = 0; | |
430 | u32 tstamp_all = 0; | |
431 | u32 ptp_over_ipv4_udp = 0; | |
432 | u32 ptp_over_ipv6_udp = 0; | |
433 | u32 ptp_over_ethernet = 0; | |
434 | u32 snap_type_sel = 0; | |
435 | u32 ts_master_en = 0; | |
436 | u32 ts_event_en = 0; | |
437 | u32 value = 0; | |
438 | ||
439 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
440 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
441 | priv->hwts_tx_en = 0; | |
442 | priv->hwts_rx_en = 0; | |
443 | ||
444 | return -EOPNOTSUPP; | |
445 | } | |
446 | ||
447 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 448 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
449 | return -EFAULT; |
450 | ||
451 | pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
452 | __func__, config.flags, config.tx_type, config.rx_filter); | |
453 | ||
454 | /* reserved for future extensions */ | |
455 | if (config.flags) | |
456 | return -EINVAL; | |
457 | ||
5f3da328 BH |
458 | if (config.tx_type != HWTSTAMP_TX_OFF && |
459 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 460 | return -ERANGE; |
891434b1 RK |
461 | |
462 | if (priv->adv_ts) { | |
463 | switch (config.rx_filter) { | |
891434b1 | 464 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 465 | /* time stamp no incoming packet at all */ |
891434b1 RK |
466 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
467 | break; | |
468 | ||
891434b1 | 469 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 470 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
471 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
472 | /* take time stamp for all event messages */ | |
473 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
474 | ||
475 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
476 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
477 | break; | |
478 | ||
891434b1 | 479 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 480 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
481 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
482 | /* take time stamp for SYNC messages only */ | |
483 | ts_event_en = PTP_TCR_TSEVNTENA; | |
484 | ||
485 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
486 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
487 | break; | |
488 | ||
891434b1 | 489 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 490 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
491 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
492 | /* take time stamp for Delay_Req messages only */ | |
493 | ts_master_en = PTP_TCR_TSMSTRENA; | |
494 | ts_event_en = PTP_TCR_TSEVNTENA; | |
495 | ||
496 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
497 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
498 | break; | |
499 | ||
891434b1 | 500 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 501 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
502 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
503 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
504 | /* take time stamp for all event messages */ | |
505 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
506 | ||
507 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
508 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
509 | break; | |
510 | ||
891434b1 | 511 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 512 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
513 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
514 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
515 | /* take time stamp for SYNC messages only */ | |
516 | ts_event_en = PTP_TCR_TSEVNTENA; | |
517 | ||
518 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
519 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
520 | break; | |
521 | ||
891434b1 | 522 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 523 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
524 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
525 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
526 | /* take time stamp for Delay_Req messages only */ | |
527 | ts_master_en = PTP_TCR_TSMSTRENA; | |
528 | ts_event_en = PTP_TCR_TSEVNTENA; | |
529 | ||
530 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
531 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
532 | break; | |
533 | ||
891434b1 | 534 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 535 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
536 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
537 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
538 | /* take time stamp for all event messages */ | |
539 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
540 | ||
541 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
542 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
543 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
544 | break; | |
545 | ||
891434b1 | 546 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 547 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
548 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
549 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
550 | /* take time stamp for SYNC messages only */ | |
551 | ts_event_en = PTP_TCR_TSEVNTENA; | |
552 | ||
553 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
554 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
555 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
556 | break; | |
557 | ||
891434b1 | 558 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 559 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
560 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
561 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
562 | /* take time stamp for Delay_Req messages only */ | |
563 | ts_master_en = PTP_TCR_TSMSTRENA; | |
564 | ts_event_en = PTP_TCR_TSEVNTENA; | |
565 | ||
566 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
567 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
568 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
569 | break; | |
570 | ||
891434b1 | 571 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 572 | /* time stamp any incoming packet */ |
891434b1 RK |
573 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
574 | tstamp_all = PTP_TCR_TSENALL; | |
575 | break; | |
576 | ||
577 | default: | |
578 | return -ERANGE; | |
579 | } | |
580 | } else { | |
581 | switch (config.rx_filter) { | |
582 | case HWTSTAMP_FILTER_NONE: | |
583 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
584 | break; | |
585 | default: | |
586 | /* PTP v1, UDP, any kind of event packet */ | |
587 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
588 | break; | |
589 | } | |
590 | } | |
591 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 592 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
593 | |
594 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
595 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); | |
596 | else { | |
597 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
598 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
599 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
600 | ts_master_en | snap_type_sel); | |
891434b1 RK |
601 | |
602 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); | |
603 | ||
604 | /* program Sub Second Increment reg */ | |
605 | priv->hw->ptp->config_sub_second_increment(priv->ioaddr); | |
606 | ||
607 | /* calculate default added value: | |
608 | * formula is : | |
609 | * addend = (2^32)/freq_div_ratio; | |
5566401f GC |
610 | * where, freq_div_ratio = clk_ptp_ref_i/50MHz |
611 | * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; | |
612 | * NOTE: clk_ptp_ref_i should be >= 50MHz to | |
891434b1 RK |
613 | * achive 20ns accuracy. |
614 | * | |
615 | * 2^x * y == (y << x), hence | |
616 | * 2^32 * 50000000 ==> (50000000 << 32) | |
617 | */ | |
ceb69499 | 618 | temp = (u64) (50000000ULL << 32); |
5566401f | 619 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
891434b1 RK |
620 | priv->hw->ptp->config_addend(priv->ioaddr, |
621 | priv->default_addend); | |
622 | ||
623 | /* initialize system time */ | |
624 | getnstimeofday(&now); | |
625 | priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, | |
626 | now.tv_nsec); | |
627 | } | |
628 | ||
629 | return copy_to_user(ifr->ifr_data, &config, | |
630 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
631 | } | |
632 | ||
32ceabca GC |
633 | /** |
634 | * stmmac_init_ptp: init PTP | |
635 | * @priv: driver private structure | |
636 | * Description: this is to verify if the HW supports the PTPv1 or v2. | |
637 | * This is done by looking at the HW cap. register. | |
638 | * Also it registers the ptp driver. | |
639 | */ | |
92ba6888 | 640 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 641 | { |
92ba6888 RK |
642 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
643 | return -EOPNOTSUPP; | |
644 | ||
5566401f GC |
645 | /* Fall-back to main clock in case of no PTP ref is passed */ |
646 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
647 | if (IS_ERR(priv->clk_ptp_ref)) { | |
648 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
649 | priv->clk_ptp_ref = NULL; | |
650 | } else { | |
651 | clk_prepare_enable(priv->clk_ptp_ref); | |
652 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
653 | } | |
654 | ||
7cd01399 VB |
655 | priv->adv_ts = 0; |
656 | if (priv->dma_cap.atime_stamp && priv->extend_desc) | |
657 | priv->adv_ts = 1; | |
658 | ||
659 | if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) | |
660 | pr_debug("IEEE 1588-2002 Time Stamp supported\n"); | |
661 | ||
662 | if (netif_msg_hw(priv) && priv->adv_ts) | |
663 | pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); | |
891434b1 RK |
664 | |
665 | priv->hw->ptp = &stmmac_ptp; | |
666 | priv->hwts_tx_en = 0; | |
667 | priv->hwts_rx_en = 0; | |
92ba6888 RK |
668 | |
669 | return stmmac_ptp_register(priv); | |
670 | } | |
671 | ||
672 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
673 | { | |
5566401f GC |
674 | if (priv->clk_ptp_ref) |
675 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 676 | stmmac_ptp_unregister(priv); |
891434b1 RK |
677 | } |
678 | ||
47dd7a54 GC |
679 | /** |
680 | * stmmac_adjust_link | |
681 | * @dev: net device structure | |
682 | * Description: it adjusts the link parameters. | |
683 | */ | |
684 | static void stmmac_adjust_link(struct net_device *dev) | |
685 | { | |
686 | struct stmmac_priv *priv = netdev_priv(dev); | |
687 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
688 | unsigned long flags; |
689 | int new_state = 0; | |
690 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
691 | ||
692 | if (phydev == NULL) | |
693 | return; | |
694 | ||
47dd7a54 | 695 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 696 | |
47dd7a54 | 697 | if (phydev->link) { |
ad01b7d4 | 698 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
699 | |
700 | /* Now we make sure that we can be in full duplex mode. | |
701 | * If not, we operate in half-duplex mode. */ | |
702 | if (phydev->duplex != priv->oldduplex) { | |
703 | new_state = 1; | |
704 | if (!(phydev->duplex)) | |
db98a0b0 | 705 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 706 | else |
db98a0b0 | 707 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
708 | priv->oldduplex = phydev->duplex; |
709 | } | |
710 | /* Flow Control operation */ | |
711 | if (phydev->pause) | |
7ed24bbe | 712 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 713 | fc, pause_time); |
47dd7a54 GC |
714 | |
715 | if (phydev->speed != priv->speed) { | |
716 | new_state = 1; | |
717 | switch (phydev->speed) { | |
718 | case 1000: | |
9dfeb4d9 | 719 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 720 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 721 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
722 | break; |
723 | case 100: | |
724 | case 10: | |
9dfeb4d9 | 725 | if (priv->plat->has_gmac) { |
db98a0b0 | 726 | ctrl |= priv->hw->link.port; |
47dd7a54 | 727 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 728 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 729 | } else { |
db98a0b0 | 730 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
731 | } |
732 | } else { | |
db98a0b0 | 733 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 734 | } |
9dfeb4d9 | 735 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
736 | break; |
737 | default: | |
738 | if (netif_msg_link(priv)) | |
ceb69499 GC |
739 | pr_warn("%s: Speed (%d) not 10/100\n", |
740 | dev->name, phydev->speed); | |
47dd7a54 GC |
741 | break; |
742 | } | |
743 | ||
744 | priv->speed = phydev->speed; | |
745 | } | |
746 | ||
ad01b7d4 | 747 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
748 | |
749 | if (!priv->oldlink) { | |
750 | new_state = 1; | |
751 | priv->oldlink = 1; | |
752 | } | |
753 | } else if (priv->oldlink) { | |
754 | new_state = 1; | |
755 | priv->oldlink = 0; | |
756 | priv->speed = 0; | |
757 | priv->oldduplex = -1; | |
758 | } | |
759 | ||
760 | if (new_state && netif_msg_link(priv)) | |
761 | phy_print_status(phydev); | |
762 | ||
f5351ef7 GC |
763 | /* At this stage, it could be needed to setup the EEE or adjust some |
764 | * MAC related HW registers. | |
765 | */ | |
766 | priv->eee_enabled = stmmac_eee_init(priv); | |
d765955d | 767 | |
47dd7a54 | 768 | spin_unlock_irqrestore(&priv->lock, flags); |
47dd7a54 GC |
769 | } |
770 | ||
32ceabca GC |
771 | /** |
772 | * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported | |
773 | * @priv: driver private structure | |
774 | * Description: this is to verify if the HW supports the PCS. | |
775 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
776 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
777 | */ | |
e58bb43f GC |
778 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
779 | { | |
780 | int interface = priv->plat->interface; | |
781 | ||
782 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
783 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
784 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
785 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
786 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
e58bb43f GC |
787 | pr_debug("STMMAC: PCS RGMII support enable\n"); |
788 | priv->pcs = STMMAC_PCS_RGMII; | |
0d909dcd | 789 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
e58bb43f GC |
790 | pr_debug("STMMAC: PCS SGMII support enable\n"); |
791 | priv->pcs = STMMAC_PCS_SGMII; | |
792 | } | |
793 | } | |
794 | } | |
795 | ||
47dd7a54 GC |
796 | /** |
797 | * stmmac_init_phy - PHY initialization | |
798 | * @dev: net device structure | |
799 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
800 | * to the mac driver. | |
801 | * Return value: | |
802 | * 0 on success | |
803 | */ | |
804 | static int stmmac_init_phy(struct net_device *dev) | |
805 | { | |
806 | struct stmmac_priv *priv = netdev_priv(dev); | |
807 | struct phy_device *phydev; | |
d765955d | 808 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 809 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 810 | int interface = priv->plat->interface; |
9cbadf09 | 811 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
812 | priv->oldlink = 0; |
813 | priv->speed = 0; | |
814 | priv->oldduplex = -1; | |
815 | ||
f142af2e SK |
816 | if (priv->plat->phy_bus_name) |
817 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
ceb69499 | 818 | priv->plat->phy_bus_name, priv->plat->bus_id); |
f142af2e SK |
819 | else |
820 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
ceb69499 | 821 | priv->plat->bus_id); |
f142af2e | 822 | |
d765955d | 823 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 824 | priv->plat->phy_addr); |
d765955d | 825 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); |
47dd7a54 | 826 | |
f9a8f83b | 827 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); |
47dd7a54 GC |
828 | |
829 | if (IS_ERR(phydev)) { | |
830 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
831 | return PTR_ERR(phydev); | |
832 | } | |
833 | ||
79ee1dc3 | 834 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 835 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 836 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 837 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
838 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
839 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 840 | |
47dd7a54 GC |
841 | /* |
842 | * Broken HW is sometimes missing the pull-up resistor on the | |
843 | * MDIO line, which results in reads to non-existent devices returning | |
844 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
845 | * device as well. | |
846 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
847 | */ | |
848 | if (phydev->phy_id == 0) { | |
849 | phy_disconnect(phydev); | |
850 | return -ENODEV; | |
851 | } | |
852 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 853 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
854 | |
855 | priv->phydev = phydev; | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
47dd7a54 | 860 | /** |
32ceabca GC |
861 | * stmmac_display_ring: display ring |
862 | * @head: pointer to the head of the ring passed. | |
47dd7a54 | 863 | * @size: size of the ring. |
32ceabca | 864 | * @extend_desc: to verify if extended descriptors are used. |
c24602ef | 865 | * Description: display the control/status and buffer descriptors. |
47dd7a54 | 866 | */ |
c24602ef | 867 | static void stmmac_display_ring(void *head, int size, int extend_desc) |
47dd7a54 | 868 | { |
47dd7a54 | 869 | int i; |
ceb69499 GC |
870 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
871 | struct dma_desc *p = (struct dma_desc *)head; | |
c24602ef | 872 | |
47dd7a54 | 873 | for (i = 0; i < size; i++) { |
c24602ef GC |
874 | u64 x; |
875 | if (extend_desc) { | |
876 | x = *(u64 *) ep; | |
877 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
878 | i, (unsigned int)virt_to_phys(ep), |
879 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
880 | ep->basic.des2, ep->basic.des3); |
881 | ep++; | |
882 | } else { | |
883 | x = *(u64 *) p; | |
884 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", | |
ceb69499 GC |
885 | i, (unsigned int)virt_to_phys(p), |
886 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
887 | p->des2, p->des3); |
888 | p++; | |
889 | } | |
47dd7a54 GC |
890 | pr_info("\n"); |
891 | } | |
892 | } | |
893 | ||
c24602ef GC |
894 | static void stmmac_display_rings(struct stmmac_priv *priv) |
895 | { | |
896 | unsigned int txsize = priv->dma_tx_size; | |
897 | unsigned int rxsize = priv->dma_rx_size; | |
898 | ||
899 | if (priv->extend_desc) { | |
900 | pr_info("Extended RX descriptor ring:\n"); | |
ceb69499 | 901 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef | 902 | pr_info("Extended TX descriptor ring:\n"); |
ceb69499 | 903 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); |
c24602ef GC |
904 | } else { |
905 | pr_info("RX descriptor ring:\n"); | |
906 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
907 | pr_info("TX descriptor ring:\n"); | |
908 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
909 | } | |
910 | } | |
911 | ||
286a8372 GC |
912 | static int stmmac_set_bfsize(int mtu, int bufsize) |
913 | { | |
914 | int ret = bufsize; | |
915 | ||
916 | if (mtu >= BUF_SIZE_4KiB) | |
917 | ret = BUF_SIZE_8KiB; | |
918 | else if (mtu >= BUF_SIZE_2KiB) | |
919 | ret = BUF_SIZE_4KiB; | |
d916701c | 920 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
921 | ret = BUF_SIZE_2KiB; |
922 | else | |
d916701c | 923 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
924 | |
925 | return ret; | |
926 | } | |
927 | ||
32ceabca GC |
928 | /** |
929 | * stmmac_clear_descriptors: clear descriptors | |
930 | * @priv: driver private structure | |
931 | * Description: this function is called to clear the tx and rx descriptors | |
932 | * in case of both basic and extended descriptors are used. | |
933 | */ | |
c24602ef GC |
934 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
935 | { | |
936 | int i; | |
937 | unsigned int txsize = priv->dma_tx_size; | |
938 | unsigned int rxsize = priv->dma_rx_size; | |
939 | ||
940 | /* Clear the Rx/Tx descriptors */ | |
941 | for (i = 0; i < rxsize; i++) | |
942 | if (priv->extend_desc) | |
943 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
944 | priv->use_riwt, priv->mode, | |
945 | (i == rxsize - 1)); | |
946 | else | |
947 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
948 | priv->use_riwt, priv->mode, | |
949 | (i == rxsize - 1)); | |
950 | for (i = 0; i < txsize; i++) | |
951 | if (priv->extend_desc) | |
952 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
953 | priv->mode, | |
954 | (i == txsize - 1)); | |
955 | else | |
956 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
957 | priv->mode, | |
958 | (i == txsize - 1)); | |
959 | } | |
960 | ||
961 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, | |
962 | int i) | |
963 | { | |
964 | struct sk_buff *skb; | |
965 | ||
966 | skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, | |
967 | GFP_KERNEL); | |
56329137 | 968 | if (!skb) { |
c24602ef | 969 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); |
56329137 | 970 | return -ENOMEM; |
c24602ef GC |
971 | } |
972 | skb_reserve(skb, NET_IP_ALIGN); | |
973 | priv->rx_skbuff[i] = skb; | |
974 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
975 | priv->dma_buf_sz, | |
976 | DMA_FROM_DEVICE); | |
56329137 BZ |
977 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
978 | pr_err("%s: DMA mapping error\n", __func__); | |
979 | dev_kfree_skb_any(skb); | |
980 | return -EINVAL; | |
981 | } | |
c24602ef GC |
982 | |
983 | p->des2 = priv->rx_skbuff_dma[i]; | |
984 | ||
29896a67 | 985 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 986 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 987 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
988 | |
989 | return 0; | |
990 | } | |
991 | ||
56329137 BZ |
992 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
993 | { | |
994 | if (priv->rx_skbuff[i]) { | |
995 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
996 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
997 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
998 | } | |
999 | priv->rx_skbuff[i] = NULL; | |
1000 | } | |
1001 | ||
47dd7a54 GC |
1002 | /** |
1003 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1004 | * @dev: net device structure | |
1005 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1006 | * and allocates the socket buffers. It suppors the chained and ring |
1007 | * modes. | |
47dd7a54 | 1008 | */ |
56329137 | 1009 | static int init_dma_desc_rings(struct net_device *dev) |
47dd7a54 GC |
1010 | { |
1011 | int i; | |
1012 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1013 | unsigned int txsize = priv->dma_tx_size; |
1014 | unsigned int rxsize = priv->dma_rx_size; | |
4a7d666a | 1015 | unsigned int bfsize = 0; |
56329137 | 1016 | int ret = -ENOMEM; |
47dd7a54 | 1017 | |
29896a67 GC |
1018 | if (priv->hw->mode->set_16kib_bfsize) |
1019 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1020 | |
4a7d666a | 1021 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1022 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1023 | |
2618abb7 VB |
1024 | priv->dma_buf_sz = bfsize; |
1025 | ||
83d7af64 GC |
1026 | if (netif_msg_probe(priv)) |
1027 | pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, | |
1028 | txsize, rxsize, bfsize); | |
47dd7a54 | 1029 | |
83d7af64 | 1030 | if (netif_msg_probe(priv)) { |
c24602ef GC |
1031 | pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, |
1032 | (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); | |
47dd7a54 | 1033 | |
83d7af64 GC |
1034 | /* RX INITIALIZATION */ |
1035 | pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); | |
1036 | } | |
47dd7a54 | 1037 | for (i = 0; i < rxsize; i++) { |
c24602ef GC |
1038 | struct dma_desc *p; |
1039 | if (priv->extend_desc) | |
1040 | p = &((priv->dma_erx + i)->basic); | |
1041 | else | |
1042 | p = priv->dma_rx + i; | |
47dd7a54 | 1043 | |
56329137 BZ |
1044 | ret = stmmac_init_rx_buffers(priv, p, i); |
1045 | if (ret) | |
1046 | goto err_init_rx_buffers; | |
286a8372 | 1047 | |
83d7af64 GC |
1048 | if (netif_msg_probe(priv)) |
1049 | pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
1050 | priv->rx_skbuff[i]->data, | |
1051 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1052 | } |
1053 | priv->cur_rx = 0; | |
1054 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
47dd7a54 GC |
1055 | buf_sz = bfsize; |
1056 | ||
c24602ef GC |
1057 | /* Setup the chained descriptor addresses */ |
1058 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1059 | if (priv->extend_desc) { | |
29896a67 GC |
1060 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
1061 | rxsize, 1); | |
1062 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, | |
1063 | txsize, 1); | |
c24602ef | 1064 | } else { |
29896a67 GC |
1065 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
1066 | rxsize, 0); | |
1067 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, | |
1068 | txsize, 0); | |
c24602ef GC |
1069 | } |
1070 | } | |
1071 | ||
47dd7a54 GC |
1072 | /* TX INITIALIZATION */ |
1073 | for (i = 0; i < txsize; i++) { | |
c24602ef GC |
1074 | struct dma_desc *p; |
1075 | if (priv->extend_desc) | |
1076 | p = &((priv->dma_etx + i)->basic); | |
1077 | else | |
1078 | p = priv->dma_tx + i; | |
1079 | p->des2 = 0; | |
362b37be GC |
1080 | priv->tx_skbuff_dma[i].buf = 0; |
1081 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 | 1082 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1083 | } |
286a8372 | 1084 | |
47dd7a54 GC |
1085 | priv->dirty_tx = 0; |
1086 | priv->cur_tx = 0; | |
1087 | ||
c24602ef | 1088 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1089 | |
c24602ef GC |
1090 | if (netif_msg_hw(priv)) |
1091 | stmmac_display_rings(priv); | |
56329137 BZ |
1092 | |
1093 | return 0; | |
1094 | err_init_rx_buffers: | |
1095 | while (--i >= 0) | |
1096 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1097 | return ret; |
47dd7a54 GC |
1098 | } |
1099 | ||
1100 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1101 | { | |
1102 | int i; | |
1103 | ||
56329137 BZ |
1104 | for (i = 0; i < priv->dma_rx_size; i++) |
1105 | stmmac_free_rx_buffers(priv, i); | |
47dd7a54 GC |
1106 | } |
1107 | ||
1108 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1109 | { | |
1110 | int i; | |
1111 | ||
1112 | for (i = 0; i < priv->dma_tx_size; i++) { | |
75e4364f | 1113 | struct dma_desc *p; |
1114 | ||
1115 | if (priv->extend_desc) | |
1116 | p = &((priv->dma_etx + i)->basic); | |
1117 | else | |
1118 | p = priv->dma_tx + i; | |
1119 | ||
362b37be GC |
1120 | if (priv->tx_skbuff_dma[i].buf) { |
1121 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1122 | dma_unmap_page(priv->device, | |
1123 | priv->tx_skbuff_dma[i].buf, | |
1124 | priv->hw->desc->get_tx_len(p), | |
1125 | DMA_TO_DEVICE); | |
1126 | else | |
1127 | dma_unmap_single(priv->device, | |
1128 | priv->tx_skbuff_dma[i].buf, | |
1129 | priv->hw->desc->get_tx_len(p), | |
1130 | DMA_TO_DEVICE); | |
75e4364f | 1131 | } |
c24602ef | 1132 | |
75e4364f | 1133 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1134 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1135 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1136 | priv->tx_skbuff_dma[i].buf = 0; |
1137 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1138 | } |
1139 | } | |
47dd7a54 GC |
1140 | } |
1141 | ||
09f8d696 SK |
1142 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1143 | { | |
1144 | unsigned int txsize = priv->dma_tx_size; | |
1145 | unsigned int rxsize = priv->dma_rx_size; | |
1146 | int ret = -ENOMEM; | |
1147 | ||
1148 | priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), | |
1149 | GFP_KERNEL); | |
1150 | if (!priv->rx_skbuff_dma) | |
1151 | return -ENOMEM; | |
1152 | ||
1153 | priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), | |
1154 | GFP_KERNEL); | |
1155 | if (!priv->rx_skbuff) | |
1156 | goto err_rx_skbuff; | |
1157 | ||
362b37be GC |
1158 | priv->tx_skbuff_dma = kmalloc_array(txsize, |
1159 | sizeof(*priv->tx_skbuff_dma), | |
09f8d696 SK |
1160 | GFP_KERNEL); |
1161 | if (!priv->tx_skbuff_dma) | |
1162 | goto err_tx_skbuff_dma; | |
1163 | ||
1164 | priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), | |
1165 | GFP_KERNEL); | |
1166 | if (!priv->tx_skbuff) | |
1167 | goto err_tx_skbuff; | |
1168 | ||
1169 | if (priv->extend_desc) { | |
1170 | priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * | |
1171 | sizeof(struct | |
1172 | dma_extended_desc), | |
1173 | &priv->dma_rx_phy, | |
1174 | GFP_KERNEL); | |
1175 | if (!priv->dma_erx) | |
1176 | goto err_dma; | |
1177 | ||
1178 | priv->dma_etx = dma_alloc_coherent(priv->device, txsize * | |
1179 | sizeof(struct | |
1180 | dma_extended_desc), | |
1181 | &priv->dma_tx_phy, | |
1182 | GFP_KERNEL); | |
1183 | if (!priv->dma_etx) { | |
1184 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1185 | sizeof(struct dma_extended_desc), | |
1186 | priv->dma_erx, priv->dma_rx_phy); | |
1187 | goto err_dma; | |
1188 | } | |
1189 | } else { | |
1190 | priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * | |
1191 | sizeof(struct dma_desc), | |
1192 | &priv->dma_rx_phy, | |
1193 | GFP_KERNEL); | |
1194 | if (!priv->dma_rx) | |
1195 | goto err_dma; | |
1196 | ||
1197 | priv->dma_tx = dma_alloc_coherent(priv->device, txsize * | |
1198 | sizeof(struct dma_desc), | |
1199 | &priv->dma_tx_phy, | |
1200 | GFP_KERNEL); | |
1201 | if (!priv->dma_tx) { | |
1202 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1203 | sizeof(struct dma_desc), | |
1204 | priv->dma_rx, priv->dma_rx_phy); | |
1205 | goto err_dma; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | ||
1211 | err_dma: | |
1212 | kfree(priv->tx_skbuff); | |
1213 | err_tx_skbuff: | |
1214 | kfree(priv->tx_skbuff_dma); | |
1215 | err_tx_skbuff_dma: | |
1216 | kfree(priv->rx_skbuff); | |
1217 | err_rx_skbuff: | |
1218 | kfree(priv->rx_skbuff_dma); | |
1219 | return ret; | |
1220 | } | |
1221 | ||
47dd7a54 GC |
1222 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1223 | { | |
1224 | /* Release the DMA TX/RX socket buffers */ | |
1225 | dma_free_rx_skbufs(priv); | |
1226 | dma_free_tx_skbufs(priv); | |
1227 | ||
ceb69499 | 1228 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1229 | if (!priv->extend_desc) { |
1230 | dma_free_coherent(priv->device, | |
1231 | priv->dma_tx_size * sizeof(struct dma_desc), | |
1232 | priv->dma_tx, priv->dma_tx_phy); | |
1233 | dma_free_coherent(priv->device, | |
1234 | priv->dma_rx_size * sizeof(struct dma_desc), | |
1235 | priv->dma_rx, priv->dma_rx_phy); | |
1236 | } else { | |
1237 | dma_free_coherent(priv->device, priv->dma_tx_size * | |
1238 | sizeof(struct dma_extended_desc), | |
1239 | priv->dma_etx, priv->dma_tx_phy); | |
1240 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1241 | sizeof(struct dma_extended_desc), | |
1242 | priv->dma_erx, priv->dma_rx_phy); | |
1243 | } | |
47dd7a54 GC |
1244 | kfree(priv->rx_skbuff_dma); |
1245 | kfree(priv->rx_skbuff); | |
cf32deec | 1246 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1247 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1248 | } |
1249 | ||
47dd7a54 GC |
1250 | /** |
1251 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1252 | * @priv: driver private structure |
47dd7a54 | 1253 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds |
ebbb293f | 1254 | * or Store-And-Forward capability. |
47dd7a54 GC |
1255 | */ |
1256 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1257 | { | |
e2a240c7 SZ |
1258 | if (priv->plat->force_thresh_dma_mode) |
1259 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); | |
1260 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { | |
61b8013a SK |
1261 | /* |
1262 | * In case of GMAC, SF mode can be enabled | |
1263 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1264 | * 1) TX COE if actually supported |
1265 | * 2) There is no bugged Jumbo frame support | |
1266 | * that needs to not insert csum in the TDES. | |
1267 | */ | |
ceb69499 | 1268 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); |
ebbb293f GC |
1269 | tc = SF_DMA_MODE; |
1270 | } else | |
1271 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
1272 | } |
1273 | ||
47dd7a54 | 1274 | /** |
9125cdd1 | 1275 | * stmmac_tx_clean: |
32ceabca | 1276 | * @priv: driver private structure |
47dd7a54 GC |
1277 | * Description: it reclaims resources after transmission completes. |
1278 | */ | |
9125cdd1 | 1279 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 GC |
1280 | { |
1281 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 1282 | |
a9097a96 GC |
1283 | spin_lock(&priv->tx_lock); |
1284 | ||
9125cdd1 GC |
1285 | priv->xstats.tx_clean++; |
1286 | ||
47dd7a54 GC |
1287 | while (priv->dirty_tx != priv->cur_tx) { |
1288 | int last; | |
1289 | unsigned int entry = priv->dirty_tx % txsize; | |
1290 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
c24602ef GC |
1291 | struct dma_desc *p; |
1292 | ||
1293 | if (priv->extend_desc) | |
ceb69499 | 1294 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1295 | else |
1296 | p = priv->dma_tx + entry; | |
47dd7a54 GC |
1297 | |
1298 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 1299 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
1300 | break; |
1301 | ||
c24602ef | 1302 | /* Verify tx error by looking at the last segment. */ |
db98a0b0 | 1303 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
1304 | if (likely(last)) { |
1305 | int tx_error = | |
ceb69499 GC |
1306 | priv->hw->desc->tx_status(&priv->dev->stats, |
1307 | &priv->xstats, p, | |
1308 | priv->ioaddr); | |
47dd7a54 GC |
1309 | if (likely(tx_error == 0)) { |
1310 | priv->dev->stats.tx_packets++; | |
1311 | priv->xstats.tx_pkt_n++; | |
1312 | } else | |
1313 | priv->dev->stats.tx_errors++; | |
891434b1 RK |
1314 | |
1315 | stmmac_get_tx_hwtstamp(priv, entry, skb); | |
47dd7a54 | 1316 | } |
83d7af64 GC |
1317 | if (netif_msg_tx_done(priv)) |
1318 | pr_debug("%s: curr %d, dirty %d\n", __func__, | |
1319 | priv->cur_tx, priv->dirty_tx); | |
47dd7a54 | 1320 | |
362b37be GC |
1321 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1322 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1323 | dma_unmap_page(priv->device, | |
1324 | priv->tx_skbuff_dma[entry].buf, | |
1325 | priv->hw->desc->get_tx_len(p), | |
1326 | DMA_TO_DEVICE); | |
1327 | else | |
1328 | dma_unmap_single(priv->device, | |
1329 | priv->tx_skbuff_dma[entry].buf, | |
1330 | priv->hw->desc->get_tx_len(p), | |
1331 | DMA_TO_DEVICE); | |
1332 | priv->tx_skbuff_dma[entry].buf = 0; | |
1333 | priv->tx_skbuff_dma[entry].map_as_page = false; | |
cf32deec | 1334 | } |
29896a67 | 1335 | priv->hw->mode->clean_desc3(priv, p); |
47dd7a54 GC |
1336 | |
1337 | if (likely(skb != NULL)) { | |
7c565c33 | 1338 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1339 | priv->tx_skbuff[entry] = NULL; |
1340 | } | |
1341 | ||
4a7d666a | 1342 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1343 | |
13497f58 | 1344 | priv->dirty_tx++; |
47dd7a54 GC |
1345 | } |
1346 | if (unlikely(netif_queue_stopped(priv->dev) && | |
1347 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
1348 | netif_tx_lock(priv->dev); | |
1349 | if (netif_queue_stopped(priv->dev) && | |
ceb69499 | 1350 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { |
83d7af64 GC |
1351 | if (netif_msg_tx_done(priv)) |
1352 | pr_debug("%s: restart transmit\n", __func__); | |
47dd7a54 GC |
1353 | netif_wake_queue(priv->dev); |
1354 | } | |
1355 | netif_tx_unlock(priv->dev); | |
1356 | } | |
d765955d GC |
1357 | |
1358 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1359 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1360 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1361 | } |
a9097a96 | 1362 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1363 | } |
1364 | ||
9125cdd1 | 1365 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1366 | { |
7284a3f1 | 1367 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1368 | } |
1369 | ||
9125cdd1 | 1370 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1371 | { |
7284a3f1 | 1372 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1373 | } |
1374 | ||
47dd7a54 | 1375 | /** |
32ceabca GC |
1376 | * stmmac_tx_err: irq tx error mng function |
1377 | * @priv: driver private structure | |
47dd7a54 GC |
1378 | * Description: it cleans the descriptors and restarts the transmission |
1379 | * in case of errors. | |
1380 | */ | |
1381 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1382 | { | |
c24602ef GC |
1383 | int i; |
1384 | int txsize = priv->dma_tx_size; | |
47dd7a54 GC |
1385 | netif_stop_queue(priv->dev); |
1386 | ||
ad01b7d4 | 1387 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1388 | dma_free_tx_skbufs(priv); |
c24602ef GC |
1389 | for (i = 0; i < txsize; i++) |
1390 | if (priv->extend_desc) | |
1391 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1392 | priv->mode, | |
1393 | (i == txsize - 1)); | |
1394 | else | |
1395 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1396 | priv->mode, | |
1397 | (i == txsize - 1)); | |
47dd7a54 GC |
1398 | priv->dirty_tx = 0; |
1399 | priv->cur_tx = 0; | |
ad01b7d4 | 1400 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1401 | |
1402 | priv->dev->stats.tx_errors++; | |
1403 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1404 | } |
1405 | ||
32ceabca GC |
1406 | /** |
1407 | * stmmac_dma_interrupt: DMA ISR | |
1408 | * @priv: driver private structure | |
1409 | * Description: this is the DMA ISR. It is called by the main ISR. | |
1410 | * It calls the dwmac dma routine to understand which type of interrupt | |
1411 | * happened. In case of there is a Normal interrupt and either TX or RX | |
1412 | * interrupt happened so the NAPI is scheduled. | |
1413 | */ | |
aec7ff27 GC |
1414 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1415 | { | |
aec7ff27 GC |
1416 | int status; |
1417 | ||
ad01b7d4 | 1418 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1419 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1420 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1421 | stmmac_disable_dma_irq(priv); | |
1422 | __napi_schedule(&priv->napi); | |
1423 | } | |
1424 | } | |
1425 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 GC |
1426 | /* Try to bump up the dma threshold on this failure */ |
1427 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
1428 | tc += 64; | |
ad01b7d4 | 1429 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 1430 | priv->xstats.threshold = tc; |
47dd7a54 | 1431 | } |
aec7ff27 GC |
1432 | } else if (unlikely(status == tx_hard_error)) |
1433 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1434 | } |
1435 | ||
32ceabca GC |
1436 | /** |
1437 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1438 | * @priv: driver private structure | |
1439 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1440 | */ | |
1c901a46 GC |
1441 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1442 | { | |
1443 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
ceb69499 | 1444 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1445 | |
1c901a46 | 1446 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
1447 | |
1448 | if (priv->dma_cap.rmon) { | |
1449 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
1450 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
1451 | } else | |
aae54cff | 1452 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
1453 | } |
1454 | ||
f0b9d786 GC |
1455 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
1456 | { | |
1457 | u32 hwid = priv->hw->synopsys_uid; | |
1458 | ||
ceb69499 | 1459 | /* Check Synopsys Id (not available on old chips) */ |
f0b9d786 GC |
1460 | if (likely(hwid)) { |
1461 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
1462 | u32 synid = (hwid & 0x000000ff); | |
1463 | ||
cf3f047b | 1464 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
1465 | uid, synid); |
1466 | ||
1467 | return synid; | |
1468 | } | |
1469 | return 0; | |
1470 | } | |
e7434821 | 1471 | |
19e30c14 | 1472 | /** |
32ceabca GC |
1473 | * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors |
1474 | * @priv: driver private structure | |
1475 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
1476 | * In case of Enhanced/Alternate, it looks at the extended descriptors are | |
1477 | * supported by the HW cap. register. | |
ff3dd78c | 1478 | */ |
19e30c14 GC |
1479 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1480 | { | |
1481 | if (priv->plat->enh_desc) { | |
1482 | pr_info(" Enhanced/Alternate descriptors\n"); | |
c24602ef GC |
1483 | |
1484 | /* GMAC older than 3.50 has no extended descriptors */ | |
1485 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
1486 | pr_info("\tEnabled extended descriptors\n"); | |
1487 | priv->extend_desc = 1; | |
1488 | } else | |
1489 | pr_warn("Extended descriptors not supported\n"); | |
1490 | ||
19e30c14 GC |
1491 | priv->hw->desc = &enh_desc_ops; |
1492 | } else { | |
1493 | pr_info(" Normal descriptors\n"); | |
1494 | priv->hw->desc = &ndesc_ops; | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | /** | |
32ceabca GC |
1499 | * stmmac_get_hw_features: get MAC capabilities from the HW cap. register. |
1500 | * @priv: driver private structure | |
19e30c14 GC |
1501 | * Description: |
1502 | * new GMAC chip generations have a new register to indicate the | |
1503 | * presence of the optional feature/functions. | |
1504 | * This can be also used to override the value passed through the | |
1505 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1506 | */ |
1507 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1508 | { | |
5e6efe88 | 1509 | u32 hw_cap = 0; |
3c20f72f | 1510 | |
5e6efe88 GC |
1511 | if (priv->hw->dma->get_hw_feature) { |
1512 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 1513 | |
1db123fb RK |
1514 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
1515 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
1516 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
1517 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
ceb69499 | 1518 | priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; |
1db123fb RK |
1519 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; |
1520 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
1521 | priv->dma_cap.pmt_remote_wake_up = | |
ceb69499 | 1522 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; |
1db123fb | 1523 | priv->dma_cap.pmt_magic_frame = |
ceb69499 | 1524 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; |
19e30c14 | 1525 | /* MMC */ |
1db123fb | 1526 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
ceb69499 | 1527 | /* IEEE 1588-2002 */ |
1db123fb | 1528 | priv->dma_cap.time_stamp = |
ceb69499 GC |
1529 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; |
1530 | /* IEEE 1588-2008 */ | |
1db123fb | 1531 | priv->dma_cap.atime_stamp = |
ceb69499 | 1532 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; |
e7434821 | 1533 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
1534 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
1535 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 1536 | /* TX and RX csum */ |
1db123fb RK |
1537 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
1538 | priv->dma_cap.rx_coe_type1 = | |
ceb69499 | 1539 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; |
1db123fb | 1540 | priv->dma_cap.rx_coe_type2 = |
ceb69499 | 1541 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; |
1db123fb | 1542 | priv->dma_cap.rxfifo_over_2048 = |
ceb69499 | 1543 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; |
e7434821 | 1544 | /* TX and RX number of channels */ |
1db123fb | 1545 | priv->dma_cap.number_rx_channel = |
ceb69499 | 1546 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; |
1db123fb | 1547 | priv->dma_cap.number_tx_channel = |
ceb69499 GC |
1548 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; |
1549 | /* Alternate (enhanced) DESC mode */ | |
1550 | priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
19e30c14 | 1551 | } |
e7434821 GC |
1552 | |
1553 | return hw_cap; | |
1554 | } | |
1555 | ||
32ceabca GC |
1556 | /** |
1557 | * stmmac_check_ether_addr: check if the MAC addr is valid | |
1558 | * @priv: driver private structure | |
1559 | * Description: | |
1560 | * it is to verify if the MAC address is valid, in case of failures it | |
1561 | * generates a random MAC address | |
1562 | */ | |
bfab27a1 GC |
1563 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1564 | { | |
bfab27a1 | 1565 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1566 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1567 | priv->dev->dev_addr, 0); |
ceb69499 | 1568 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1569 | eth_hw_addr_random(priv->dev); |
c88460b7 HG |
1570 | pr_info("%s: device MAC address %pM\n", priv->dev->name, |
1571 | priv->dev->dev_addr); | |
bfab27a1 | 1572 | } |
bfab27a1 GC |
1573 | } |
1574 | ||
32ceabca GC |
1575 | /** |
1576 | * stmmac_init_dma_engine: DMA init. | |
1577 | * @priv: driver private structure | |
1578 | * Description: | |
1579 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1580 | * Some DMA parameters can be passed from the platform; | |
1581 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1582 | */ | |
0f1f88a8 GC |
1583 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1584 | { | |
1585 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; | |
b9cde0a8 | 1586 | int mixed_burst = 0; |
c24602ef | 1587 | int atds = 0; |
0f1f88a8 | 1588 | |
0f1f88a8 GC |
1589 | if (priv->plat->dma_cfg) { |
1590 | pbl = priv->plat->dma_cfg->pbl; | |
1591 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
b9cde0a8 | 1592 | mixed_burst = priv->plat->dma_cfg->mixed_burst; |
0f1f88a8 GC |
1593 | burst_len = priv->plat->dma_cfg->burst_len; |
1594 | } | |
1595 | ||
c24602ef GC |
1596 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1597 | atds = 1; | |
1598 | ||
b9cde0a8 | 1599 | return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, |
0f1f88a8 | 1600 | burst_len, priv->dma_tx_phy, |
c24602ef | 1601 | priv->dma_rx_phy, atds); |
0f1f88a8 GC |
1602 | } |
1603 | ||
9125cdd1 | 1604 | /** |
32ceabca | 1605 | * stmmac_tx_timer: mitigation sw timer for tx. |
9125cdd1 GC |
1606 | * @data: data pointer |
1607 | * Description: | |
1608 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1609 | */ | |
1610 | static void stmmac_tx_timer(unsigned long data) | |
1611 | { | |
1612 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1613 | ||
1614 | stmmac_tx_clean(priv); | |
1615 | } | |
1616 | ||
1617 | /** | |
32ceabca GC |
1618 | * stmmac_init_tx_coalesce: init tx mitigation options. |
1619 | * @priv: driver private structure | |
9125cdd1 GC |
1620 | * Description: |
1621 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1622 | * timer handler and default threshold used for enabling the | |
1623 | * interrupt on completion bit. | |
1624 | */ | |
1625 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1626 | { | |
1627 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1628 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1629 | init_timer(&priv->txtimer); | |
1630 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1631 | priv->txtimer.data = (unsigned long)priv; | |
1632 | priv->txtimer.function = stmmac_tx_timer; | |
1633 | add_timer(&priv->txtimer); | |
1634 | } | |
1635 | ||
523f11b5 SK |
1636 | /** |
1637 | * stmmac_hw_setup: setup mac in a usable state. | |
1638 | * @dev : pointer to the device structure. | |
1639 | * Description: | |
1640 | * This function sets up the ip in a usable state. | |
1641 | * Return value: | |
1642 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1643 | * file on failure. | |
1644 | */ | |
1645 | static int stmmac_hw_setup(struct net_device *dev) | |
1646 | { | |
1647 | struct stmmac_priv *priv = netdev_priv(dev); | |
1648 | int ret; | |
1649 | ||
1650 | ret = init_dma_desc_rings(dev); | |
1651 | if (ret < 0) { | |
1652 | pr_err("%s: DMA descriptors initialization failed\n", __func__); | |
1653 | return ret; | |
1654 | } | |
1655 | /* DMA initialization and SW reset */ | |
1656 | ret = stmmac_init_dma_engine(priv); | |
1657 | if (ret < 0) { | |
1658 | pr_err("%s: DMA engine initialization failed\n", __func__); | |
1659 | return ret; | |
1660 | } | |
1661 | ||
1662 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1663 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1664 | |
1665 | /* If required, perform hw setup of the bus. */ | |
1666 | if (priv->plat->bus_setup) | |
1667 | priv->plat->bus_setup(priv->ioaddr); | |
1668 | ||
1669 | /* Initialize the MAC Core */ | |
7ed24bbe | 1670 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1671 | |
978aded4 GC |
1672 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1673 | if (!ret) { | |
1674 | pr_warn(" RX IPC Checksum Offload disabled\n"); | |
1675 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
d2afb5bd | 1676 | priv->hw->rx_csum = 0; |
978aded4 GC |
1677 | } |
1678 | ||
523f11b5 SK |
1679 | /* Enable the MAC Rx/Tx */ |
1680 | stmmac_set_mac(priv->ioaddr, true); | |
1681 | ||
1682 | /* Set the HW DMA mode and the COE */ | |
1683 | stmmac_dma_operation_mode(priv); | |
1684 | ||
1685 | stmmac_mmc_setup(priv); | |
1686 | ||
1687 | ret = stmmac_init_ptp(priv); | |
7509edd6 | 1688 | if (ret && ret != -EOPNOTSUPP) |
523f11b5 SK |
1689 | pr_warn("%s: failed PTP initialisation\n", __func__); |
1690 | ||
1691 | #ifdef CONFIG_STMMAC_DEBUG_FS | |
1692 | ret = stmmac_init_fs(dev); | |
1693 | if (ret < 0) | |
1694 | pr_warn("%s: failed debugFS registration\n", __func__); | |
1695 | #endif | |
1696 | /* Start the ball rolling... */ | |
1697 | pr_debug("%s: DMA RX/TX processes started...\n", dev->name); | |
1698 | priv->hw->dma->start_tx(priv->ioaddr); | |
1699 | priv->hw->dma->start_rx(priv->ioaddr); | |
1700 | ||
1701 | /* Dump DMA/MAC registers */ | |
1702 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1703 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1704 | priv->hw->dma->dump_regs(priv->ioaddr); |
1705 | } | |
1706 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1707 | ||
1708 | priv->eee_enabled = stmmac_eee_init(priv); | |
1709 | ||
1710 | stmmac_init_tx_coalesce(priv); | |
1711 | ||
1712 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { | |
1713 | priv->rx_riwt = MAX_DMA_RIWT; | |
1714 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1715 | } | |
1716 | ||
1717 | if (priv->pcs && priv->hw->mac->ctrl_ane) | |
7ed24bbe | 1718 | priv->hw->mac->ctrl_ane(priv->hw, 0); |
523f11b5 SK |
1719 | |
1720 | return 0; | |
1721 | } | |
1722 | ||
47dd7a54 GC |
1723 | /** |
1724 | * stmmac_open - open entry point of the driver | |
1725 | * @dev : pointer to the device structure. | |
1726 | * Description: | |
1727 | * This function is the open entry point of the driver. | |
1728 | * Return value: | |
1729 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1730 | * file on failure. | |
1731 | */ | |
1732 | static int stmmac_open(struct net_device *dev) | |
1733 | { | |
1734 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1735 | int ret; |
1736 | ||
4bfcbd7a FV |
1737 | stmmac_check_ether_addr(priv); |
1738 | ||
4d8f0825 BA |
1739 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
1740 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1741 | ret = stmmac_init_phy(dev); |
1742 | if (ret) { | |
1743 | pr_err("%s: Cannot attach to PHY (error: %d)\n", | |
1744 | __func__, ret); | |
89df20d9 | 1745 | return ret; |
e58bb43f | 1746 | } |
f66ffe28 | 1747 | } |
47dd7a54 | 1748 | |
523f11b5 SK |
1749 | /* Extra statistics */ |
1750 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1751 | priv->xstats.threshold = tc; | |
1752 | ||
47dd7a54 GC |
1753 | /* Create and initialize the TX/RX descriptors chains. */ |
1754 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
1755 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
1756 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
56329137 | 1757 | |
7262b7b2 | 1758 | ret = alloc_dma_desc_resources(priv); |
09f8d696 SK |
1759 | if (ret < 0) { |
1760 | pr_err("%s: DMA descriptors allocation failed\n", __func__); | |
1761 | goto dma_desc_error; | |
1762 | } | |
1763 | ||
523f11b5 | 1764 | ret = stmmac_hw_setup(dev); |
56329137 | 1765 | if (ret < 0) { |
523f11b5 | 1766 | pr_err("%s: Hw setup failed\n", __func__); |
c9324d18 | 1767 | goto init_error; |
47dd7a54 GC |
1768 | } |
1769 | ||
523f11b5 SK |
1770 | if (priv->phydev) |
1771 | phy_start(priv->phydev); | |
47dd7a54 | 1772 | |
f66ffe28 GC |
1773 | /* Request the IRQ lines */ |
1774 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1775 | IRQF_SHARED, dev->name, dev); |
f66ffe28 GC |
1776 | if (unlikely(ret < 0)) { |
1777 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1778 | __func__, dev->irq, ret); | |
c9324d18 | 1779 | goto init_error; |
f66ffe28 GC |
1780 | } |
1781 | ||
7a13f8f5 FV |
1782 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1783 | if (priv->wol_irq != dev->irq) { | |
1784 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1785 | IRQF_SHARED, dev->name, dev); | |
1786 | if (unlikely(ret < 0)) { | |
ceb69499 GC |
1787 | pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
1788 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1789 | goto wolirq_error; |
7a13f8f5 FV |
1790 | } |
1791 | } | |
1792 | ||
d765955d | 1793 | /* Request the IRQ lines */ |
d7ec8584 | 1794 | if (priv->lpi_irq > 0) { |
d765955d GC |
1795 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1796 | dev->name, dev); | |
1797 | if (unlikely(ret < 0)) { | |
1798 | pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1799 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1800 | goto lpiirq_error; |
d765955d GC |
1801 | } |
1802 | } | |
1803 | ||
47dd7a54 | 1804 | napi_enable(&priv->napi); |
47dd7a54 | 1805 | netif_start_queue(dev); |
f66ffe28 | 1806 | |
47dd7a54 | 1807 | return 0; |
f66ffe28 | 1808 | |
c9324d18 | 1809 | lpiirq_error: |
d765955d GC |
1810 | if (priv->wol_irq != dev->irq) |
1811 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1812 | wolirq_error: |
7a13f8f5 FV |
1813 | free_irq(dev->irq, dev); |
1814 | ||
c9324d18 GC |
1815 | init_error: |
1816 | free_dma_desc_resources(priv); | |
56329137 | 1817 | dma_desc_error: |
f66ffe28 GC |
1818 | if (priv->phydev) |
1819 | phy_disconnect(priv->phydev); | |
4bfcbd7a | 1820 | |
f66ffe28 | 1821 | return ret; |
47dd7a54 GC |
1822 | } |
1823 | ||
1824 | /** | |
1825 | * stmmac_release - close entry point of the driver | |
1826 | * @dev : device pointer. | |
1827 | * Description: | |
1828 | * This is the stop entry point of the driver. | |
1829 | */ | |
1830 | static int stmmac_release(struct net_device *dev) | |
1831 | { | |
1832 | struct stmmac_priv *priv = netdev_priv(dev); | |
1833 | ||
d765955d GC |
1834 | if (priv->eee_enabled) |
1835 | del_timer_sync(&priv->eee_ctrl_timer); | |
1836 | ||
47dd7a54 GC |
1837 | /* Stop and disconnect the PHY */ |
1838 | if (priv->phydev) { | |
1839 | phy_stop(priv->phydev); | |
1840 | phy_disconnect(priv->phydev); | |
1841 | priv->phydev = NULL; | |
1842 | } | |
1843 | ||
1844 | netif_stop_queue(dev); | |
1845 | ||
47dd7a54 | 1846 | napi_disable(&priv->napi); |
47dd7a54 | 1847 | |
9125cdd1 GC |
1848 | del_timer_sync(&priv->txtimer); |
1849 | ||
47dd7a54 GC |
1850 | /* Free the IRQ lines */ |
1851 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1852 | if (priv->wol_irq != dev->irq) |
1853 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1854 | if (priv->lpi_irq > 0) |
d765955d | 1855 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1856 | |
1857 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1858 | priv->hw->dma->stop_tx(priv->ioaddr); |
1859 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1860 | |
1861 | /* Release and free the Rx/Tx resources */ | |
1862 | free_dma_desc_resources(priv); | |
1863 | ||
19449bfc | 1864 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1865 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1866 | |
1867 | netif_carrier_off(dev); | |
1868 | ||
bfab27a1 GC |
1869 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1870 | stmmac_exit_fs(); | |
1871 | #endif | |
bfab27a1 | 1872 | |
92ba6888 RK |
1873 | stmmac_release_ptp(priv); |
1874 | ||
47dd7a54 GC |
1875 | return 0; |
1876 | } | |
1877 | ||
47dd7a54 | 1878 | /** |
32ceabca | 1879 | * stmmac_xmit: Tx entry point of the driver |
47dd7a54 GC |
1880 | * @skb : the socket buffer |
1881 | * @dev : device pointer | |
32ceabca GC |
1882 | * Description : this is the tx entry point of the driver. |
1883 | * It programs the chain or the ring and supports oversized frames | |
1884 | * and SG feature. | |
47dd7a54 GC |
1885 | */ |
1886 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1887 | { | |
1888 | struct stmmac_priv *priv = netdev_priv(dev); | |
1889 | unsigned int txsize = priv->dma_tx_size; | |
1890 | unsigned int entry; | |
4a7d666a | 1891 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 GC |
1892 | int nfrags = skb_shinfo(skb)->nr_frags; |
1893 | struct dma_desc *desc, *first; | |
286a8372 | 1894 | unsigned int nopaged_len = skb_headlen(skb); |
29896a67 | 1895 | unsigned int enh_desc = priv->plat->enh_desc; |
47dd7a54 GC |
1896 | |
1897 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1898 | if (!netif_queue_stopped(dev)) { | |
1899 | netif_stop_queue(dev); | |
1900 | /* This is a hard error, log it. */ | |
ceb69499 | 1901 | pr_err("%s: Tx Ring full when queue awake\n", __func__); |
47dd7a54 GC |
1902 | } |
1903 | return NETDEV_TX_BUSY; | |
1904 | } | |
1905 | ||
a9097a96 GC |
1906 | spin_lock(&priv->tx_lock); |
1907 | ||
d765955d GC |
1908 | if (priv->tx_path_in_lpi_mode) |
1909 | stmmac_disable_eee_mode(priv); | |
1910 | ||
47dd7a54 GC |
1911 | entry = priv->cur_tx % txsize; |
1912 | ||
5e982f3b | 1913 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 1914 | |
c24602ef | 1915 | if (priv->extend_desc) |
ceb69499 | 1916 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1917 | else |
1918 | desc = priv->dma_tx + entry; | |
1919 | ||
47dd7a54 GC |
1920 | first = desc; |
1921 | ||
4a7d666a | 1922 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
1923 | if (enh_desc) |
1924 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
1925 | ||
4a7d666a | 1926 | if (likely(!is_jumbo)) { |
47dd7a54 | 1927 | desc->des2 = dma_map_single(priv->device, skb->data, |
ceb69499 | 1928 | nopaged_len, DMA_TO_DEVICE); |
362b37be GC |
1929 | if (dma_mapping_error(priv->device, desc->des2)) |
1930 | goto dma_map_err; | |
1931 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
db98a0b0 | 1932 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
4a7d666a | 1933 | csum_insertion, priv->mode); |
29896a67 | 1934 | } else { |
c24602ef | 1935 | desc = first; |
29896a67 | 1936 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
1937 | if (unlikely(entry < 0)) |
1938 | goto dma_map_err; | |
29896a67 | 1939 | } |
47dd7a54 GC |
1940 | |
1941 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1942 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1943 | int len = skb_frag_size(frag); | |
47dd7a54 | 1944 | |
75e4364f | 1945 | priv->tx_skbuff[entry] = NULL; |
47dd7a54 | 1946 | entry = (++priv->cur_tx) % txsize; |
c24602ef | 1947 | if (priv->extend_desc) |
ceb69499 | 1948 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1949 | else |
1950 | desc = priv->dma_tx + entry; | |
47dd7a54 | 1951 | |
f722380d IC |
1952 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1953 | DMA_TO_DEVICE); | |
362b37be GC |
1954 | if (dma_mapping_error(priv->device, desc->des2)) |
1955 | goto dma_map_err; /* should reuse desc w/o issues */ | |
1956 | ||
1957 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
1958 | priv->tx_skbuff_dma[entry].map_as_page = true; | |
4a7d666a GC |
1959 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
1960 | priv->mode); | |
eb0dc4bb | 1961 | wmb(); |
db98a0b0 | 1962 | priv->hw->desc->set_tx_owner(desc); |
8e839891 | 1963 | wmb(); |
47dd7a54 GC |
1964 | } |
1965 | ||
75e4364f | 1966 | priv->tx_skbuff[entry] = skb; |
1967 | ||
9125cdd1 | 1968 | /* Finalize the latest segment. */ |
db98a0b0 | 1969 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1970 | |
eb0dc4bb | 1971 | wmb(); |
9125cdd1 GC |
1972 | /* According to the coalesce parameter the IC bit for the latest |
1973 | * segment could be reset and the timer re-started to invoke the | |
1974 | * stmmac_tx function. This approach takes care about the fragments. | |
1975 | */ | |
1976 | priv->tx_count_frames += nfrags + 1; | |
1977 | if (priv->tx_coal_frames > priv->tx_count_frames) { | |
1978 | priv->hw->desc->clear_tx_ic(desc); | |
1979 | priv->xstats.tx_reset_ic_bit++; | |
9125cdd1 GC |
1980 | mod_timer(&priv->txtimer, |
1981 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
1982 | } else | |
1983 | priv->tx_count_frames = 0; | |
eb0dc4bb | 1984 | |
47dd7a54 | 1985 | /* To avoid raise condition */ |
db98a0b0 | 1986 | priv->hw->desc->set_tx_owner(first); |
8e839891 | 1987 | wmb(); |
47dd7a54 GC |
1988 | |
1989 | priv->cur_tx++; | |
1990 | ||
47dd7a54 | 1991 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 1992 | pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", |
ceb69499 GC |
1993 | __func__, (priv->cur_tx % txsize), |
1994 | (priv->dirty_tx % txsize), entry, first, nfrags); | |
83d7af64 | 1995 | |
c24602ef GC |
1996 | if (priv->extend_desc) |
1997 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); | |
1998 | else | |
1999 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
2000 | ||
83d7af64 | 2001 | pr_debug(">>> frame to be transmitted: "); |
47dd7a54 GC |
2002 | print_pkt(skb->data, skb->len); |
2003 | } | |
47dd7a54 | 2004 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
83d7af64 GC |
2005 | if (netif_msg_hw(priv)) |
2006 | pr_debug("%s: stop transmitted packets\n", __func__); | |
47dd7a54 GC |
2007 | netif_stop_queue(dev); |
2008 | } | |
2009 | ||
2010 | dev->stats.tx_bytes += skb->len; | |
2011 | ||
891434b1 RK |
2012 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
2013 | priv->hwts_tx_en)) { | |
2014 | /* declare that device is doing timestamping */ | |
2015 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2016 | priv->hw->desc->enable_tx_timestamp(first); | |
2017 | } | |
2018 | ||
2019 | if (!priv->hwts_tx_en) | |
2020 | skb_tx_timestamp(skb); | |
3e82ce12 | 2021 | |
52f64fae RC |
2022 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
2023 | ||
a9097a96 | 2024 | spin_unlock(&priv->tx_lock); |
362b37be | 2025 | return NETDEV_TX_OK; |
a9097a96 | 2026 | |
362b37be GC |
2027 | dma_map_err: |
2028 | dev_err(priv->device, "Tx dma map failed\n"); | |
2029 | dev_kfree_skb(skb); | |
2030 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2031 | return NETDEV_TX_OK; |
2032 | } | |
2033 | ||
b9381985 VB |
2034 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2035 | { | |
2036 | struct ethhdr *ehdr; | |
2037 | u16 vlanid; | |
2038 | ||
2039 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2040 | NETIF_F_HW_VLAN_CTAG_RX && | |
2041 | !__vlan_get_tag(skb, &vlanid)) { | |
2042 | /* pop the vlan tag */ | |
2043 | ehdr = (struct ethhdr *)skb->data; | |
2044 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2045 | skb_pull(skb, VLAN_HLEN); | |
2046 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | ||
32ceabca GC |
2051 | /** |
2052 | * stmmac_rx_refill: refill used skb preallocated buffers | |
2053 | * @priv: driver private structure | |
2054 | * Description : this is to reallocate the skb for the reception process | |
2055 | * that is based on zero-copy. | |
2056 | */ | |
47dd7a54 GC |
2057 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2058 | { | |
2059 | unsigned int rxsize = priv->dma_rx_size; | |
2060 | int bfsize = priv->dma_buf_sz; | |
47dd7a54 GC |
2061 | |
2062 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
2063 | unsigned int entry = priv->dirty_rx % rxsize; | |
c24602ef GC |
2064 | struct dma_desc *p; |
2065 | ||
2066 | if (priv->extend_desc) | |
ceb69499 | 2067 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2068 | else |
2069 | p = priv->dma_rx + entry; | |
2070 | ||
47dd7a54 GC |
2071 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2072 | struct sk_buff *skb; | |
2073 | ||
acb600de | 2074 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
47dd7a54 GC |
2075 | |
2076 | if (unlikely(skb == NULL)) | |
2077 | break; | |
2078 | ||
2079 | priv->rx_skbuff[entry] = skb; | |
2080 | priv->rx_skbuff_dma[entry] = | |
2081 | dma_map_single(priv->device, skb->data, bfsize, | |
2082 | DMA_FROM_DEVICE); | |
362b37be GC |
2083 | if (dma_mapping_error(priv->device, |
2084 | priv->rx_skbuff_dma[entry])) { | |
2085 | dev_err(priv->device, "Rx dma map failed\n"); | |
2086 | dev_kfree_skb(skb); | |
2087 | break; | |
2088 | } | |
c24602ef | 2089 | p->des2 = priv->rx_skbuff_dma[entry]; |
286a8372 | 2090 | |
29896a67 | 2091 | priv->hw->mode->refill_desc3(priv, p); |
286a8372 | 2092 | |
83d7af64 GC |
2093 | if (netif_msg_rx_status(priv)) |
2094 | pr_debug("\trefill entry #%d\n", entry); | |
47dd7a54 | 2095 | } |
eb0dc4bb | 2096 | wmb(); |
c24602ef | 2097 | priv->hw->desc->set_rx_owner(p); |
8e839891 | 2098 | wmb(); |
47dd7a54 | 2099 | } |
47dd7a54 GC |
2100 | } |
2101 | ||
32ceabca GC |
2102 | /** |
2103 | * stmmac_rx_refill: refill used skb preallocated buffers | |
2104 | * @priv: driver private structure | |
2105 | * @limit: napi bugget. | |
2106 | * Description : this the function called by the napi poll method. | |
2107 | * It gets all the frames inside the ring. | |
2108 | */ | |
47dd7a54 GC |
2109 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2110 | { | |
2111 | unsigned int rxsize = priv->dma_rx_size; | |
2112 | unsigned int entry = priv->cur_rx % rxsize; | |
2113 | unsigned int next_entry; | |
2114 | unsigned int count = 0; | |
d2afb5bd | 2115 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2116 | |
83d7af64 GC |
2117 | if (netif_msg_rx_status(priv)) { |
2118 | pr_debug("%s: descriptor ring:\n", __func__); | |
c24602ef | 2119 | if (priv->extend_desc) |
ceb69499 | 2120 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef GC |
2121 | else |
2122 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
47dd7a54 | 2123 | } |
c24602ef | 2124 | while (count < limit) { |
47dd7a54 | 2125 | int status; |
9401bb5c | 2126 | struct dma_desc *p; |
47dd7a54 | 2127 | |
c24602ef | 2128 | if (priv->extend_desc) |
ceb69499 | 2129 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2130 | else |
ceb69499 | 2131 | p = priv->dma_rx + entry; |
c24602ef GC |
2132 | |
2133 | if (priv->hw->desc->get_rx_owner(p)) | |
47dd7a54 GC |
2134 | break; |
2135 | ||
2136 | count++; | |
2137 | ||
2138 | next_entry = (++priv->cur_rx) % rxsize; | |
c24602ef | 2139 | if (priv->extend_desc) |
9401bb5c | 2140 | prefetch(priv->dma_erx + next_entry); |
c24602ef | 2141 | else |
9401bb5c | 2142 | prefetch(priv->dma_rx + next_entry); |
47dd7a54 GC |
2143 | |
2144 | /* read the status of the incoming frame */ | |
c24602ef GC |
2145 | status = priv->hw->desc->rx_status(&priv->dev->stats, |
2146 | &priv->xstats, p); | |
2147 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) | |
2148 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2149 | &priv->xstats, | |
2150 | priv->dma_erx + | |
2151 | entry); | |
891434b1 | 2152 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2153 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2154 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2155 | /* DESC2 & DESC3 will be overwitten by device | |
2156 | * with timestamp value, hence reinitialize | |
2157 | * them in stmmac_rx_refill() function so that | |
2158 | * device can reuse it. | |
2159 | */ | |
2160 | priv->rx_skbuff[entry] = NULL; | |
2161 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2162 | priv->rx_skbuff_dma[entry], |
2163 | priv->dma_buf_sz, | |
2164 | DMA_FROM_DEVICE); | |
891434b1 RK |
2165 | } |
2166 | } else { | |
47dd7a54 | 2167 | struct sk_buff *skb; |
3eeb2997 | 2168 | int frame_len; |
47dd7a54 | 2169 | |
ceb69499 GC |
2170 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2171 | ||
3eeb2997 | 2172 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2173 | * Type frames (LLC/LLC-SNAP) |
2174 | */ | |
3eeb2997 GC |
2175 | if (unlikely(status != llc_snap)) |
2176 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2177 | |
83d7af64 | 2178 | if (netif_msg_rx_status(priv)) { |
47dd7a54 | 2179 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", |
ceb69499 | 2180 | p, entry, p->des2); |
83d7af64 GC |
2181 | if (frame_len > ETH_FRAME_LEN) |
2182 | pr_debug("\tframe size %d, COE: %d\n", | |
2183 | frame_len, status); | |
2184 | } | |
47dd7a54 GC |
2185 | skb = priv->rx_skbuff[entry]; |
2186 | if (unlikely(!skb)) { | |
2187 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
ceb69499 | 2188 | priv->dev->name); |
47dd7a54 GC |
2189 | priv->dev->stats.rx_dropped++; |
2190 | break; | |
2191 | } | |
2192 | prefetch(skb->data - NET_IP_ALIGN); | |
2193 | priv->rx_skbuff[entry] = NULL; | |
2194 | ||
891434b1 RK |
2195 | stmmac_get_rx_hwtstamp(priv, entry, skb); |
2196 | ||
47dd7a54 GC |
2197 | skb_put(skb, frame_len); |
2198 | dma_unmap_single(priv->device, | |
2199 | priv->rx_skbuff_dma[entry], | |
2200 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
83d7af64 | 2201 | |
47dd7a54 | 2202 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2203 | pr_debug("frame received (%dbytes)", frame_len); |
47dd7a54 GC |
2204 | print_pkt(skb->data, frame_len); |
2205 | } | |
83d7af64 | 2206 | |
b9381985 VB |
2207 | stmmac_rx_vlan(priv->dev, skb); |
2208 | ||
47dd7a54 GC |
2209 | skb->protocol = eth_type_trans(skb, priv->dev); |
2210 | ||
ceb69499 | 2211 | if (unlikely(!coe)) |
bc8acf2c | 2212 | skb_checksum_none_assert(skb); |
62a2ab93 | 2213 | else |
47dd7a54 | 2214 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2215 | |
2216 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2217 | |
2218 | priv->dev->stats.rx_packets++; | |
2219 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2220 | } |
2221 | entry = next_entry; | |
47dd7a54 GC |
2222 | } |
2223 | ||
2224 | stmmac_rx_refill(priv); | |
2225 | ||
2226 | priv->xstats.rx_pkt_n += count; | |
2227 | ||
2228 | return count; | |
2229 | } | |
2230 | ||
2231 | /** | |
2232 | * stmmac_poll - stmmac poll method (NAPI) | |
2233 | * @napi : pointer to the napi structure. | |
2234 | * @budget : maximum number of packets that the current CPU can receive from | |
2235 | * all interfaces. | |
2236 | * Description : | |
9125cdd1 | 2237 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2238 | */ |
2239 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2240 | { | |
2241 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2242 | int work_done = 0; | |
2243 | ||
9125cdd1 GC |
2244 | priv->xstats.napi_poll++; |
2245 | stmmac_tx_clean(priv); | |
47dd7a54 | 2246 | |
9125cdd1 | 2247 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2248 | if (work_done < budget) { |
2249 | napi_complete(napi); | |
9125cdd1 | 2250 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2251 | } |
2252 | return work_done; | |
2253 | } | |
2254 | ||
2255 | /** | |
2256 | * stmmac_tx_timeout | |
2257 | * @dev : Pointer to net device structure | |
2258 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2259 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2260 | * netdev structure and arrange for the device to be reset to a sane state |
2261 | * in order to transmit a new packet. | |
2262 | */ | |
2263 | static void stmmac_tx_timeout(struct net_device *dev) | |
2264 | { | |
2265 | struct stmmac_priv *priv = netdev_priv(dev); | |
2266 | ||
2267 | /* Clear Tx resources and restart transmitting again */ | |
2268 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2269 | } |
2270 | ||
47dd7a54 | 2271 | /** |
01789349 | 2272 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2273 | * @dev : pointer to the device structure |
2274 | * Description: | |
2275 | * This function is a driver entry point which gets called by the kernel | |
2276 | * whenever multicast addresses must be enabled/disabled. | |
2277 | * Return value: | |
2278 | * void. | |
2279 | */ | |
01789349 | 2280 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2281 | { |
2282 | struct stmmac_priv *priv = netdev_priv(dev); | |
2283 | ||
2284 | spin_lock(&priv->lock); | |
3b57de95 | 2285 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 | 2286 | spin_unlock(&priv->lock); |
47dd7a54 GC |
2287 | } |
2288 | ||
2289 | /** | |
2290 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2291 | * @dev : device pointer. | |
2292 | * @new_mtu : the new MTU size for the device. | |
2293 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2294 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2295 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2296 | * Return value: | |
2297 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2298 | * file on failure. | |
2299 | */ | |
2300 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2301 | { | |
2302 | struct stmmac_priv *priv = netdev_priv(dev); | |
2303 | int max_mtu; | |
2304 | ||
2305 | if (netif_running(dev)) { | |
2306 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
2307 | return -EBUSY; | |
2308 | } | |
2309 | ||
48febf7e | 2310 | if (priv->plat->enh_desc) |
47dd7a54 GC |
2311 | max_mtu = JUMBO_LEN; |
2312 | else | |
45db81e1 | 2313 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 | 2314 | |
2618abb7 VB |
2315 | if (priv->plat->maxmtu < max_mtu) |
2316 | max_mtu = priv->plat->maxmtu; | |
2317 | ||
47dd7a54 GC |
2318 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { |
2319 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
2320 | return -EINVAL; | |
2321 | } | |
2322 | ||
5e982f3b MM |
2323 | dev->mtu = new_mtu; |
2324 | netdev_update_features(dev); | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
c8f44aff | 2329 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2330 | netdev_features_t features) |
5e982f3b MM |
2331 | { |
2332 | struct stmmac_priv *priv = netdev_priv(dev); | |
2333 | ||
38912bdb | 2334 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2335 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2336 | |
5e982f3b MM |
2337 | if (!priv->plat->tx_coe) |
2338 | features &= ~NETIF_F_ALL_CSUM; | |
2339 | ||
ebbb293f GC |
2340 | /* Some GMAC devices have a bugged Jumbo frame support that |
2341 | * needs to have the Tx COE disabled for oversized frames | |
2342 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2343 | * the TX csum insertionin the TDES and not use SF. |
2344 | */ | |
5e982f3b MM |
2345 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
2346 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 2347 | |
5e982f3b | 2348 | return features; |
47dd7a54 GC |
2349 | } |
2350 | ||
d2afb5bd GC |
2351 | static int stmmac_set_features(struct net_device *netdev, |
2352 | netdev_features_t features) | |
2353 | { | |
2354 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2355 | ||
2356 | /* Keep the COE Type in case of csum is supporting */ | |
2357 | if (features & NETIF_F_RXCSUM) | |
2358 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2359 | else | |
2360 | priv->hw->rx_csum = 0; | |
2361 | /* No check needed because rx_coe has been set before and it will be | |
2362 | * fixed in case of issue. | |
2363 | */ | |
2364 | priv->hw->mac->rx_ipc(priv->hw); | |
2365 | ||
2366 | return 0; | |
2367 | } | |
2368 | ||
32ceabca GC |
2369 | /** |
2370 | * stmmac_interrupt - main ISR | |
2371 | * @irq: interrupt number. | |
2372 | * @dev_id: to pass the net device pointer. | |
2373 | * Description: this is the main driver interrupt service routine. | |
2374 | * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI | |
2375 | * interrupts. | |
2376 | */ | |
47dd7a54 GC |
2377 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2378 | { | |
2379 | struct net_device *dev = (struct net_device *)dev_id; | |
2380 | struct stmmac_priv *priv = netdev_priv(dev); | |
2381 | ||
89f7f2cf SK |
2382 | if (priv->irq_wake) |
2383 | pm_wakeup_event(priv->device, 0); | |
2384 | ||
47dd7a54 GC |
2385 | if (unlikely(!dev)) { |
2386 | pr_err("%s: invalid dev pointer\n", __func__); | |
2387 | return IRQ_NONE; | |
2388 | } | |
2389 | ||
d765955d GC |
2390 | /* To handle GMAC own interrupts */ |
2391 | if (priv->plat->has_gmac) { | |
7ed24bbe | 2392 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2393 | &priv->xstats); |
d765955d | 2394 | if (unlikely(status)) { |
d765955d | 2395 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2396 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2397 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2398 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2399 | priv->tx_path_in_lpi_mode = false; |
d765955d GC |
2400 | } |
2401 | } | |
aec7ff27 | 2402 | |
d765955d | 2403 | /* To handle DMA interrupts */ |
aec7ff27 | 2404 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2405 | |
2406 | return IRQ_HANDLED; | |
2407 | } | |
2408 | ||
2409 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2410 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2411 | * to allow network I/O with interrupts disabled. |
2412 | */ | |
47dd7a54 GC |
2413 | static void stmmac_poll_controller(struct net_device *dev) |
2414 | { | |
2415 | disable_irq(dev->irq); | |
2416 | stmmac_interrupt(dev->irq, dev); | |
2417 | enable_irq(dev->irq); | |
2418 | } | |
2419 | #endif | |
2420 | ||
2421 | /** | |
2422 | * stmmac_ioctl - Entry point for the Ioctl | |
2423 | * @dev: Device pointer. | |
2424 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2425 | * a proprietary structure used to pass information to the driver. | |
2426 | * @cmd: IOCTL command | |
2427 | * Description: | |
32ceabca | 2428 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2429 | */ |
2430 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2431 | { | |
2432 | struct stmmac_priv *priv = netdev_priv(dev); | |
891434b1 | 2433 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2434 | |
2435 | if (!netif_running(dev)) | |
2436 | return -EINVAL; | |
2437 | ||
891434b1 RK |
2438 | switch (cmd) { |
2439 | case SIOCGMIIPHY: | |
2440 | case SIOCGMIIREG: | |
2441 | case SIOCSMIIREG: | |
2442 | if (!priv->phydev) | |
2443 | return -EINVAL; | |
2444 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
2445 | break; | |
2446 | case SIOCSHWTSTAMP: | |
2447 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2448 | break; | |
2449 | default: | |
2450 | break; | |
2451 | } | |
28b04113 | 2452 | |
47dd7a54 GC |
2453 | return ret; |
2454 | } | |
2455 | ||
7ac29055 GC |
2456 | #ifdef CONFIG_STMMAC_DEBUG_FS |
2457 | static struct dentry *stmmac_fs_dir; | |
2458 | static struct dentry *stmmac_rings_status; | |
e7434821 | 2459 | static struct dentry *stmmac_dma_cap; |
7ac29055 | 2460 | |
c24602ef | 2461 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2462 | struct seq_file *seq) |
7ac29055 | 2463 | { |
7ac29055 | 2464 | int i; |
ceb69499 GC |
2465 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2466 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2467 | |
c24602ef GC |
2468 | for (i = 0; i < size; i++) { |
2469 | u64 x; | |
2470 | if (extend_desc) { | |
2471 | x = *(u64 *) ep; | |
2472 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2473 | i, (unsigned int)virt_to_phys(ep), |
2474 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2475 | ep->basic.des2, ep->basic.des3); |
2476 | ep++; | |
2477 | } else { | |
2478 | x = *(u64 *) p; | |
2479 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2480 | i, (unsigned int)virt_to_phys(ep), |
2481 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2482 | p->des2, p->des3); |
2483 | p++; | |
2484 | } | |
7ac29055 GC |
2485 | seq_printf(seq, "\n"); |
2486 | } | |
c24602ef | 2487 | } |
7ac29055 | 2488 | |
c24602ef GC |
2489 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2490 | { | |
2491 | struct net_device *dev = seq->private; | |
2492 | struct stmmac_priv *priv = netdev_priv(dev); | |
2493 | unsigned int txsize = priv->dma_tx_size; | |
2494 | unsigned int rxsize = priv->dma_rx_size; | |
7ac29055 | 2495 | |
c24602ef GC |
2496 | if (priv->extend_desc) { |
2497 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
ceb69499 | 2498 | sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); |
c24602ef | 2499 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
ceb69499 | 2500 | sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); |
c24602ef GC |
2501 | } else { |
2502 | seq_printf(seq, "RX descriptor ring:\n"); | |
2503 | sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); | |
2504 | seq_printf(seq, "TX descriptor ring:\n"); | |
2505 | sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); | |
7ac29055 GC |
2506 | } |
2507 | ||
2508 | return 0; | |
2509 | } | |
2510 | ||
2511 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2512 | { | |
2513 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2514 | } | |
2515 | ||
2516 | static const struct file_operations stmmac_rings_status_fops = { | |
2517 | .owner = THIS_MODULE, | |
2518 | .open = stmmac_sysfs_ring_open, | |
2519 | .read = seq_read, | |
2520 | .llseek = seq_lseek, | |
74863948 | 2521 | .release = single_release, |
7ac29055 GC |
2522 | }; |
2523 | ||
e7434821 GC |
2524 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2525 | { | |
2526 | struct net_device *dev = seq->private; | |
2527 | struct stmmac_priv *priv = netdev_priv(dev); | |
2528 | ||
19e30c14 | 2529 | if (!priv->hw_cap_support) { |
e7434821 GC |
2530 | seq_printf(seq, "DMA HW features not supported\n"); |
2531 | return 0; | |
2532 | } | |
2533 | ||
2534 | seq_printf(seq, "==============================\n"); | |
2535 | seq_printf(seq, "\tDMA HW features\n"); | |
2536 | seq_printf(seq, "==============================\n"); | |
2537 | ||
2538 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
2539 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
2540 | seq_printf(seq, "\t1000 Mbps %s\n", | |
2541 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
2542 | seq_printf(seq, "\tHalf duple %s\n", | |
2543 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
2544 | seq_printf(seq, "\tHash Filter: %s\n", | |
2545 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
2546 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
2547 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
2548 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
2549 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
2550 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
2551 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
2552 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
2553 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
2554 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
2555 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
2556 | seq_printf(seq, "\tRMON module: %s\n", | |
2557 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
2558 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
2559 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
2560 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
2561 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
2562 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
2563 | (priv->dma_cap.eee) ? "Y" : "N"); | |
2564 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
2565 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
2566 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
2567 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
2568 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
2569 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
2570 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
2571 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
2572 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
2573 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
2574 | priv->dma_cap.number_rx_channel); | |
2575 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
2576 | priv->dma_cap.number_tx_channel); | |
2577 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
2578 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
2579 | ||
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
2584 | { | |
2585 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
2586 | } | |
2587 | ||
2588 | static const struct file_operations stmmac_dma_cap_fops = { | |
2589 | .owner = THIS_MODULE, | |
2590 | .open = stmmac_sysfs_dma_cap_open, | |
2591 | .read = seq_read, | |
2592 | .llseek = seq_lseek, | |
74863948 | 2593 | .release = single_release, |
e7434821 GC |
2594 | }; |
2595 | ||
7ac29055 GC |
2596 | static int stmmac_init_fs(struct net_device *dev) |
2597 | { | |
2598 | /* Create debugfs entries */ | |
2599 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
2600 | ||
2601 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
2602 | pr_err("ERROR %s, debugfs create directory failed\n", | |
2603 | STMMAC_RESOURCE_NAME); | |
2604 | ||
2605 | return -ENOMEM; | |
2606 | } | |
2607 | ||
2608 | /* Entry to report DMA RX/TX rings */ | |
2609 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
ceb69499 GC |
2610 | S_IRUGO, stmmac_fs_dir, dev, |
2611 | &stmmac_rings_status_fops); | |
7ac29055 GC |
2612 | |
2613 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
2614 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
2615 | debugfs_remove(stmmac_fs_dir); | |
2616 | ||
2617 | return -ENOMEM; | |
2618 | } | |
2619 | ||
e7434821 GC |
2620 | /* Entry to report the DMA HW features */ |
2621 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
2622 | dev, &stmmac_dma_cap_fops); | |
2623 | ||
2624 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
2625 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
2626 | debugfs_remove(stmmac_rings_status); | |
2627 | debugfs_remove(stmmac_fs_dir); | |
2628 | ||
2629 | return -ENOMEM; | |
2630 | } | |
2631 | ||
7ac29055 GC |
2632 | return 0; |
2633 | } | |
2634 | ||
2635 | static void stmmac_exit_fs(void) | |
2636 | { | |
2637 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 2638 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
2639 | debugfs_remove(stmmac_fs_dir); |
2640 | } | |
2641 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
2642 | ||
47dd7a54 GC |
2643 | static const struct net_device_ops stmmac_netdev_ops = { |
2644 | .ndo_open = stmmac_open, | |
2645 | .ndo_start_xmit = stmmac_xmit, | |
2646 | .ndo_stop = stmmac_release, | |
2647 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 2648 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 2649 | .ndo_set_features = stmmac_set_features, |
01789349 | 2650 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
2651 | .ndo_tx_timeout = stmmac_tx_timeout, |
2652 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
2653 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2654 | .ndo_poll_controller = stmmac_poll_controller, | |
2655 | #endif | |
2656 | .ndo_set_mac_address = eth_mac_addr, | |
2657 | }; | |
2658 | ||
cf3f047b GC |
2659 | /** |
2660 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 2661 | * @priv: driver private structure |
cf3f047b GC |
2662 | * Description: this function detects which MAC device |
2663 | * (GMAC/MAC10-100) has to attached, checks the HW capability | |
2664 | * (if supported) and sets the driver's features (for example | |
2665 | * to use the ring or chaine mode or support the normal/enh | |
2666 | * descriptor structure). | |
2667 | */ | |
2668 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
2669 | { | |
cf3f047b GC |
2670 | struct mac_device_info *mac; |
2671 | ||
2672 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
2673 | if (priv->plat->has_gmac) { |
2674 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
2675 | mac = dwmac1000_setup(priv->ioaddr, |
2676 | priv->plat->multicast_filter_bins, | |
2677 | priv->plat->unicast_filter_entries); | |
03f2eecd | 2678 | } else { |
cf3f047b | 2679 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 2680 | } |
cf3f047b GC |
2681 | if (!mac) |
2682 | return -ENOMEM; | |
2683 | ||
2684 | priv->hw = mac; | |
2685 | ||
cf3f047b | 2686 | /* Get and dump the chip ID */ |
cffb13f4 | 2687 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b | 2688 | |
4a7d666a | 2689 | /* To use the chained or ring mode */ |
ceb69499 | 2690 | if (chain_mode) { |
29896a67 | 2691 | priv->hw->mode = &chain_mode_ops; |
4a7d666a GC |
2692 | pr_info(" Chain mode enabled\n"); |
2693 | priv->mode = STMMAC_CHAIN_MODE; | |
2694 | } else { | |
29896a67 | 2695 | priv->hw->mode = &ring_mode_ops; |
4a7d666a GC |
2696 | pr_info(" Ring mode enabled\n"); |
2697 | priv->mode = STMMAC_RING_MODE; | |
2698 | } | |
2699 | ||
cf3f047b GC |
2700 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
2701 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
2702 | if (priv->hw_cap_support) { | |
2703 | pr_info(" DMA HW capability register supported"); | |
2704 | ||
2705 | /* We can override some gmac/dma configuration fields: e.g. | |
2706 | * enh_desc, tx_coe (e.g. that are passed through the | |
2707 | * platform) with the values from the HW capability | |
2708 | * register (if supported). | |
2709 | */ | |
2710 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 2711 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb DS |
2712 | |
2713 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
2714 | ||
2715 | if (priv->dma_cap.rx_coe_type2) | |
2716 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
2717 | else if (priv->dma_cap.rx_coe_type1) | |
2718 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
2719 | ||
cf3f047b GC |
2720 | } else |
2721 | pr_info(" No HW DMA feature register supported"); | |
2722 | ||
61369d02 BA |
2723 | /* To use alternate (extended) or normal descriptor structures */ |
2724 | stmmac_selec_desc_mode(priv); | |
2725 | ||
d2afb5bd GC |
2726 | if (priv->plat->rx_coe) { |
2727 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38912bdb DS |
2728 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", |
2729 | priv->plat->rx_coe); | |
d2afb5bd | 2730 | } |
cf3f047b GC |
2731 | if (priv->plat->tx_coe) |
2732 | pr_info(" TX Checksum insertion supported\n"); | |
2733 | ||
2734 | if (priv->plat->pmt) { | |
2735 | pr_info(" Wake-Up On Lan supported\n"); | |
2736 | device_set_wakeup_capable(priv->device, 1); | |
2737 | } | |
2738 | ||
c24602ef | 2739 | return 0; |
cf3f047b GC |
2740 | } |
2741 | ||
47dd7a54 | 2742 | /** |
bfab27a1 GC |
2743 | * stmmac_dvr_probe |
2744 | * @device: device pointer | |
ff3dd78c GC |
2745 | * @plat_dat: platform data pointer |
2746 | * @addr: iobase memory address | |
bfab27a1 GC |
2747 | * Description: this is the main probe function used to |
2748 | * call the alloc_etherdev, allocate the priv structure. | |
47dd7a54 | 2749 | */ |
bfab27a1 | 2750 | struct stmmac_priv *stmmac_dvr_probe(struct device *device, |
cf3f047b GC |
2751 | struct plat_stmmacenet_data *plat_dat, |
2752 | void __iomem *addr) | |
47dd7a54 GC |
2753 | { |
2754 | int ret = 0; | |
bfab27a1 GC |
2755 | struct net_device *ndev = NULL; |
2756 | struct stmmac_priv *priv; | |
47dd7a54 | 2757 | |
bfab27a1 | 2758 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 2759 | if (!ndev) |
bfab27a1 | 2760 | return NULL; |
bfab27a1 GC |
2761 | |
2762 | SET_NETDEV_DEV(ndev, device); | |
2763 | ||
2764 | priv = netdev_priv(ndev); | |
2765 | priv->device = device; | |
2766 | priv->dev = ndev; | |
47dd7a54 | 2767 | |
bfab27a1 | 2768 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
2769 | priv->pause = pause; |
2770 | priv->plat = plat_dat; | |
2771 | priv->ioaddr = addr; | |
2772 | priv->dev->base_addr = (unsigned long)addr; | |
2773 | ||
2774 | /* Verify driver arguments */ | |
2775 | stmmac_verify_args(); | |
bfab27a1 | 2776 | |
cf3f047b | 2777 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
2778 | * this needs to have multiple instances |
2779 | */ | |
cf3f047b GC |
2780 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
2781 | priv->plat->phy_addr = phyaddr; | |
2782 | ||
62866e98 CYT |
2783 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
2784 | if (IS_ERR(priv->stmmac_clk)) { | |
2785 | dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", | |
2786 | __func__); | |
c5bb86c3 KHL |
2787 | /* If failed to obtain stmmac_clk and specific clk_csr value |
2788 | * is NOT passed from the platform, probe fail. | |
2789 | */ | |
2790 | if (!priv->plat->clk_csr) { | |
2791 | ret = PTR_ERR(priv->stmmac_clk); | |
2792 | goto error_clk_get; | |
2793 | } else { | |
2794 | priv->stmmac_clk = NULL; | |
2795 | } | |
62866e98 CYT |
2796 | } |
2797 | clk_prepare_enable(priv->stmmac_clk); | |
2798 | ||
c5e4ddbd CYT |
2799 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
2800 | STMMAC_RESOURCE_NAME); | |
2801 | if (IS_ERR(priv->stmmac_rst)) { | |
2802 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
2803 | ret = -EPROBE_DEFER; | |
2804 | goto error_hw_init; | |
2805 | } | |
2806 | dev_info(priv->device, "no reset control found\n"); | |
2807 | priv->stmmac_rst = NULL; | |
2808 | } | |
2809 | if (priv->stmmac_rst) | |
2810 | reset_control_deassert(priv->stmmac_rst); | |
2811 | ||
cf3f047b | 2812 | /* Init MAC and get the capabilities */ |
c24602ef GC |
2813 | ret = stmmac_hw_init(priv); |
2814 | if (ret) | |
62866e98 | 2815 | goto error_hw_init; |
cf3f047b GC |
2816 | |
2817 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 2818 | |
cf3f047b GC |
2819 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2820 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
2821 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
2822 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
2823 | #ifdef STMMAC_VLAN_TAG_USED |
2824 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 2825 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
2826 | #endif |
2827 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
2828 | ||
47dd7a54 GC |
2829 | if (flow_ctrl) |
2830 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
2831 | ||
62a2ab93 GC |
2832 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
2833 | * In some case, for example on bugged HW this feature | |
2834 | * has to be disable and this can be done by passing the | |
2835 | * riwt_off field from the platform. | |
2836 | */ | |
2837 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
2838 | priv->use_riwt = 1; | |
2839 | pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); | |
2840 | } | |
2841 | ||
bfab27a1 | 2842 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 2843 | |
f8e96161 | 2844 | spin_lock_init(&priv->lock); |
a9097a96 | 2845 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 2846 | |
bfab27a1 | 2847 | ret = register_netdev(ndev); |
47dd7a54 | 2848 | if (ret) { |
cf3f047b | 2849 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
6a81c26f | 2850 | goto error_netdev_register; |
47dd7a54 GC |
2851 | } |
2852 | ||
cd7201f4 GC |
2853 | /* If a specific clk_csr value is passed from the platform |
2854 | * this means that the CSR Clock Range selection cannot be | |
2855 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
2856 | * set the MDC clock dynamically according to the csr actual | |
2857 | * clock input. | |
2858 | */ | |
2859 | if (!priv->plat->clk_csr) | |
2860 | stmmac_clk_csr_set(priv); | |
2861 | else | |
2862 | priv->clk_csr = priv->plat->clk_csr; | |
2863 | ||
e58bb43f GC |
2864 | stmmac_check_pcs_mode(priv); |
2865 | ||
4d8f0825 BA |
2866 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2867 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
2868 | /* MDIO bus Registration */ |
2869 | ret = stmmac_mdio_register(ndev); | |
2870 | if (ret < 0) { | |
2871 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
2872 | __func__, priv->plat->bus_id); | |
2873 | goto error_mdio_register; | |
2874 | } | |
4bfcbd7a FV |
2875 | } |
2876 | ||
bfab27a1 | 2877 | return priv; |
47dd7a54 | 2878 | |
6a81c26f | 2879 | error_mdio_register: |
34a52f36 | 2880 | unregister_netdev(ndev); |
6a81c26f VK |
2881 | error_netdev_register: |
2882 | netif_napi_del(&priv->napi); | |
62866e98 CYT |
2883 | error_hw_init: |
2884 | clk_disable_unprepare(priv->stmmac_clk); | |
2885 | error_clk_get: | |
34a52f36 | 2886 | free_netdev(ndev); |
47dd7a54 | 2887 | |
c5e4ddbd | 2888 | return ERR_PTR(ret); |
47dd7a54 GC |
2889 | } |
2890 | ||
2891 | /** | |
2892 | * stmmac_dvr_remove | |
bfab27a1 | 2893 | * @ndev: net device pointer |
47dd7a54 | 2894 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 2895 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 2896 | */ |
bfab27a1 | 2897 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 2898 | { |
aec7ff27 | 2899 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
2900 | |
2901 | pr_info("%s:\n\tremoving driver", __func__); | |
2902 | ||
ad01b7d4 GC |
2903 | priv->hw->dma->stop_rx(priv->ioaddr); |
2904 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 2905 | |
bfab27a1 | 2906 | stmmac_set_mac(priv->ioaddr, false); |
4d8f0825 BA |
2907 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2908 | priv->pcs != STMMAC_PCS_RTBI) | |
e58bb43f | 2909 | stmmac_mdio_unregister(ndev); |
47dd7a54 | 2910 | netif_carrier_off(ndev); |
47dd7a54 | 2911 | unregister_netdev(ndev); |
c5e4ddbd CYT |
2912 | if (priv->stmmac_rst) |
2913 | reset_control_assert(priv->stmmac_rst); | |
62866e98 | 2914 | clk_disable_unprepare(priv->stmmac_clk); |
47dd7a54 GC |
2915 | free_netdev(ndev); |
2916 | ||
2917 | return 0; | |
2918 | } | |
2919 | ||
2920 | #ifdef CONFIG_PM | |
bfab27a1 | 2921 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 2922 | { |
874bd42d | 2923 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 2924 | unsigned long flags; |
47dd7a54 | 2925 | |
874bd42d | 2926 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
2927 | return 0; |
2928 | ||
102463b1 FV |
2929 | if (priv->phydev) |
2930 | phy_stop(priv->phydev); | |
2931 | ||
f8c5a875 | 2932 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 2933 | |
874bd42d GC |
2934 | netif_device_detach(ndev); |
2935 | netif_stop_queue(ndev); | |
47dd7a54 | 2936 | |
874bd42d GC |
2937 | napi_disable(&priv->napi); |
2938 | ||
2939 | /* Stop TX/RX DMA */ | |
2940 | priv->hw->dma->stop_tx(priv->ioaddr); | |
2941 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef GC |
2942 | |
2943 | stmmac_clear_descriptors(priv); | |
874bd42d GC |
2944 | |
2945 | /* Enable Power down mode by programming the PMT regs */ | |
89f7f2cf | 2946 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 2947 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
2948 | priv->irq_wake = 1; |
2949 | } else { | |
bfab27a1 | 2950 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 2951 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 2952 | /* Disable clock in case of PWM is off */ |
a630844d | 2953 | clk_disable_unprepare(priv->stmmac_clk); |
ba1377ff | 2954 | } |
f8c5a875 | 2955 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
2956 | |
2957 | priv->oldlink = 0; | |
2958 | priv->speed = 0; | |
2959 | priv->oldduplex = -1; | |
47dd7a54 GC |
2960 | return 0; |
2961 | } | |
2962 | ||
bfab27a1 | 2963 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 2964 | { |
874bd42d | 2965 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 2966 | unsigned long flags; |
47dd7a54 | 2967 | |
874bd42d | 2968 | if (!netif_running(ndev)) |
47dd7a54 GC |
2969 | return 0; |
2970 | ||
f8c5a875 | 2971 | spin_lock_irqsave(&priv->lock, flags); |
c4433be6 | 2972 | |
47dd7a54 GC |
2973 | /* Power Down bit, into the PM register, is cleared |
2974 | * automatically as soon as a magic packet or a Wake-up frame | |
2975 | * is received. Anyway, it's better to manually clear | |
2976 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
2977 | * from another devices (e.g. serial console). |
2978 | */ | |
623997fb | 2979 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 2980 | priv->hw->mac->pmt(priv->hw, 0); |
89f7f2cf | 2981 | priv->irq_wake = 0; |
623997fb | 2982 | } else { |
db88f10a | 2983 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 2984 | /* enable the clk prevously disabled */ |
a630844d | 2985 | clk_prepare_enable(priv->stmmac_clk); |
623997fb SK |
2986 | /* reset the phy so that it's ready */ |
2987 | if (priv->mii) | |
2988 | stmmac_mdio_reset(priv->mii); | |
2989 | } | |
47dd7a54 | 2990 | |
874bd42d | 2991 | netif_device_attach(ndev); |
47dd7a54 | 2992 | |
623997fb | 2993 | stmmac_hw_setup(ndev); |
47dd7a54 | 2994 | |
47dd7a54 GC |
2995 | napi_enable(&priv->napi); |
2996 | ||
874bd42d | 2997 | netif_start_queue(ndev); |
47dd7a54 | 2998 | |
f8c5a875 | 2999 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 FV |
3000 | |
3001 | if (priv->phydev) | |
3002 | phy_start(priv->phydev); | |
3003 | ||
47dd7a54 GC |
3004 | return 0; |
3005 | } | |
874bd42d | 3006 | #endif /* CONFIG_PM */ |
47dd7a54 | 3007 | |
33d5e332 GC |
3008 | /* Driver can be configured w/ and w/ both PCI and Platf drivers |
3009 | * depending on the configuration selected. | |
3010 | */ | |
ba27ec66 GC |
3011 | static int __init stmmac_init(void) |
3012 | { | |
493682b8 | 3013 | int ret; |
ba27ec66 | 3014 | |
493682b8 KK |
3015 | ret = stmmac_register_platform(); |
3016 | if (ret) | |
3017 | goto err; | |
3018 | ret = stmmac_register_pci(); | |
3019 | if (ret) | |
3020 | goto err_pci; | |
33d5e332 | 3021 | return 0; |
493682b8 KK |
3022 | err_pci: |
3023 | stmmac_unregister_platform(); | |
3024 | err: | |
3025 | pr_err("stmmac: driver registration failed\n"); | |
3026 | return ret; | |
ba27ec66 GC |
3027 | } |
3028 | ||
3029 | static void __exit stmmac_exit(void) | |
3030 | { | |
33d5e332 GC |
3031 | stmmac_unregister_platform(); |
3032 | stmmac_unregister_pci(); | |
ba27ec66 GC |
3033 | } |
3034 | ||
3035 | module_init(stmmac_init); | |
3036 | module_exit(stmmac_exit); | |
3037 | ||
47dd7a54 GC |
3038 | #ifndef MODULE |
3039 | static int __init stmmac_cmdline_opt(char *str) | |
3040 | { | |
3041 | char *opt; | |
3042 | ||
3043 | if (!str || !*str) | |
3044 | return -EINVAL; | |
3045 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3046 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3047 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3048 | goto err; |
3049 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3050 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 GC |
3051 | goto err; |
3052 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
ea2ab871 | 3053 | if (kstrtoint(opt + 11, 0, &dma_txsize)) |
f3240e28 GC |
3054 | goto err; |
3055 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
ea2ab871 | 3056 | if (kstrtoint(opt + 11, 0, &dma_rxsize)) |
f3240e28 GC |
3057 | goto err; |
3058 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
ea2ab871 | 3059 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3060 | goto err; |
3061 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3062 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3063 | goto err; |
3064 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3065 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3066 | goto err; |
3067 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3068 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3069 | goto err; |
3070 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3071 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3072 | goto err; |
506f669c | 3073 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3074 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3075 | goto err; | |
4a7d666a GC |
3076 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3077 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3078 | goto err; | |
f3240e28 | 3079 | } |
47dd7a54 GC |
3080 | } |
3081 | return 0; | |
f3240e28 GC |
3082 | |
3083 | err: | |
3084 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3085 | return -EINVAL; | |
47dd7a54 GC |
3086 | } |
3087 | ||
3088 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3089 | #endif /* MODULE */ |
6fc0d0f2 GC |
3090 | |
3091 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); | |
3092 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3093 | MODULE_LICENSE("GPL"); |