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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
50fb4f74 | 47 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
48 | #include <linux/debugfs.h> |
49 | #include <linux/seq_file.h> | |
50fb4f74 | 50 | #endif /* CONFIG_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
47dd7a54 | 55 | |
47dd7a54 | 56 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
47dd7a54 GC |
57 | |
58 | /* Module parameters */ | |
32ceabca | 59 | #define TX_TIMEO 5000 |
47dd7a54 GC |
60 | static int watchdog = TX_TIMEO; |
61 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 62 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 63 | |
32ceabca | 64 | static int debug = -1; |
47dd7a54 | 65 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 66 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 67 | |
47d1f71f | 68 | static int phyaddr = -1; |
47dd7a54 GC |
69 | module_param(phyaddr, int, S_IRUGO); |
70 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
71 | ||
72 | #define DMA_TX_SIZE 256 | |
73 | static int dma_txsize = DMA_TX_SIZE; | |
74 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
75 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
76 | ||
77 | #define DMA_RX_SIZE 256 | |
78 | static int dma_rxsize = DMA_RX_SIZE; | |
79 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
80 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
81 | ||
82 | static int flow_ctrl = FLOW_OFF; | |
83 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
85 | ||
86 | static int pause = PAUSE_TIME; | |
87 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
88 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
89 | ||
90 | #define TC_DEFAULT 64 | |
91 | static int tc = TC_DEFAULT; | |
92 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
93 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
94 | ||
d916701c GC |
95 | #define DEFAULT_BUFSIZE 1536 |
96 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
97 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
98 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
99 | ||
47dd7a54 GC |
100 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
101 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
102 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
103 | ||
d765955d GC |
104 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
105 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
106 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
107 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 108 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 109 | |
4a7d666a GC |
110 | /* By default the driver will use the ring mode to manage tx and rx descriptors |
111 | * but passing this value so user can force to use the chain instead of the ring | |
112 | */ | |
113 | static unsigned int chain_mode; | |
114 | module_param(chain_mode, int, S_IRUGO); | |
115 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
116 | ||
47dd7a54 | 117 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 118 | |
50fb4f74 | 119 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 GC |
120 | static int stmmac_init_fs(struct net_device *dev); |
121 | static void stmmac_exit_fs(void); | |
122 | #endif | |
123 | ||
9125cdd1 GC |
124 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
125 | ||
47dd7a54 GC |
126 | /** |
127 | * stmmac_verify_args - verify the driver parameters. | |
732fdf0e GC |
128 | * Description: it checks the driver parameters and set a default in case of |
129 | * errors. | |
47dd7a54 GC |
130 | */ |
131 | static void stmmac_verify_args(void) | |
132 | { | |
133 | if (unlikely(watchdog < 0)) | |
134 | watchdog = TX_TIMEO; | |
135 | if (unlikely(dma_rxsize < 0)) | |
136 | dma_rxsize = DMA_RX_SIZE; | |
137 | if (unlikely(dma_txsize < 0)) | |
138 | dma_txsize = DMA_TX_SIZE; | |
d916701c GC |
139 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
140 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
141 | if (unlikely(flow_ctrl > 1)) |
142 | flow_ctrl = FLOW_AUTO; | |
143 | else if (likely(flow_ctrl < 0)) | |
144 | flow_ctrl = FLOW_OFF; | |
145 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
146 | pause = PAUSE_TIME; | |
d765955d GC |
147 | if (eee_timer < 0) |
148 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
149 | } |
150 | ||
32ceabca GC |
151 | /** |
152 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
153 | * @priv: driver private structure | |
154 | * Description: this is to dynamically set the MDC clock according to the csr | |
155 | * clock input. | |
156 | * Note: | |
157 | * If a specific clk_csr value is passed from the platform | |
158 | * this means that the CSR Clock Range selection cannot be | |
159 | * changed at run-time and it is fixed (as reported in the driver | |
160 | * documentation). Viceversa the driver will try to set the MDC | |
161 | * clock dynamically according to the actual clock input. | |
162 | */ | |
cd7201f4 GC |
163 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
164 | { | |
cd7201f4 GC |
165 | u32 clk_rate; |
166 | ||
167 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
168 | ||
169 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
170 | * for all other cases except for the below mentioned ones. |
171 | * For values higher than the IEEE 802.3 specified frequency | |
172 | * we can not estimate the proper divider as it is not known | |
173 | * the frequency of clk_csr_i. So we do not change the default | |
174 | * divider. | |
175 | */ | |
cd7201f4 GC |
176 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
177 | if (clk_rate < CSR_F_35M) | |
178 | priv->clk_csr = STMMAC_CSR_20_35M; | |
179 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
180 | priv->clk_csr = STMMAC_CSR_35_60M; | |
181 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
182 | priv->clk_csr = STMMAC_CSR_60_100M; | |
183 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
184 | priv->clk_csr = STMMAC_CSR_100_150M; | |
185 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
186 | priv->clk_csr = STMMAC_CSR_150_250M; | |
187 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) | |
188 | priv->clk_csr = STMMAC_CSR_250_300M; | |
ceb69499 | 189 | } |
cd7201f4 GC |
190 | } |
191 | ||
47dd7a54 GC |
192 | static void print_pkt(unsigned char *buf, int len) |
193 | { | |
424c4f78 AS |
194 | pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
195 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); | |
47dd7a54 | 196 | } |
47dd7a54 GC |
197 | |
198 | /* minimum number of free TX descriptors required to wake up TX process */ | |
199 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
200 | ||
201 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
202 | { | |
203 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
204 | } | |
205 | ||
32ceabca | 206 | /** |
732fdf0e | 207 | * stmmac_hw_fix_mac_speed - callback for speed selection |
32ceabca GC |
208 | * @priv: driver private structure |
209 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
210 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
211 | */ |
212 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
213 | { | |
214 | struct phy_device *phydev = priv->phydev; | |
215 | ||
216 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 217 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
218 | } |
219 | ||
32ceabca | 220 | /** |
732fdf0e | 221 | * stmmac_enable_eee_mode - check and enter in LPI mode |
32ceabca | 222 | * @priv: driver private structure |
732fdf0e GC |
223 | * Description: this function is to verify and enter in LPI mode in case of |
224 | * EEE. | |
32ceabca | 225 | */ |
d765955d GC |
226 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
227 | { | |
228 | /* Check and enter in LPI mode */ | |
229 | if ((priv->dirty_tx == priv->cur_tx) && | |
230 | (priv->tx_path_in_lpi_mode == false)) | |
7ed24bbe | 231 | priv->hw->mac->set_eee_mode(priv->hw); |
d765955d GC |
232 | } |
233 | ||
32ceabca | 234 | /** |
732fdf0e | 235 | * stmmac_disable_eee_mode - disable and exit from LPI mode |
32ceabca GC |
236 | * @priv: driver private structure |
237 | * Description: this function is to exit and disable EEE in case of | |
238 | * LPI state is true. This is called by the xmit. | |
239 | */ | |
d765955d GC |
240 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
241 | { | |
7ed24bbe | 242 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
243 | del_timer_sync(&priv->eee_ctrl_timer); |
244 | priv->tx_path_in_lpi_mode = false; | |
245 | } | |
246 | ||
247 | /** | |
732fdf0e | 248 | * stmmac_eee_ctrl_timer - EEE TX SW timer. |
d765955d GC |
249 | * @arg : data hook |
250 | * Description: | |
32ceabca | 251 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
252 | * then MAC Transmitter can be moved to LPI state. |
253 | */ | |
254 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
255 | { | |
256 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
257 | ||
258 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 259 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
260 | } |
261 | ||
262 | /** | |
732fdf0e | 263 | * stmmac_eee_init - init EEE |
32ceabca | 264 | * @priv: driver private structure |
d765955d | 265 | * Description: |
732fdf0e GC |
266 | * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
267 | * can also manage EEE, this function enable the LPI state and start related | |
268 | * timer. | |
d765955d GC |
269 | */ |
270 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
271 | { | |
56b88c25 | 272 | char *phy_bus_name = priv->plat->phy_bus_name; |
4741cf9c | 273 | unsigned long flags; |
d765955d GC |
274 | bool ret = false; |
275 | ||
f5351ef7 GC |
276 | /* Using PCS we cannot dial with the phy registers at this stage |
277 | * so we do not support extra feature like EEE. | |
278 | */ | |
279 | if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || | |
280 | (priv->pcs == STMMAC_PCS_RTBI)) | |
281 | goto out; | |
282 | ||
56b88c25 GC |
283 | /* Never init EEE in case of a switch is attached */ |
284 | if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) | |
285 | goto out; | |
286 | ||
d765955d GC |
287 | /* MAC core supports the EEE feature. */ |
288 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
289 | int tx_lpi_timer = priv->tx_lpi_timer; |
290 | ||
d765955d | 291 | /* Check if the PHY supports EEE */ |
83bf79b6 GC |
292 | if (phy_init_eee(priv->phydev, 1)) { |
293 | /* To manage at run-time if the EEE cannot be supported | |
294 | * anymore (for example because the lp caps have been | |
295 | * changed). | |
296 | * In that case the driver disable own timers. | |
297 | */ | |
4741cf9c | 298 | spin_lock_irqsave(&priv->lock, flags); |
83bf79b6 GC |
299 | if (priv->eee_active) { |
300 | pr_debug("stmmac: disable EEE\n"); | |
301 | del_timer_sync(&priv->eee_ctrl_timer); | |
7ed24bbe | 302 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
303 | tx_lpi_timer); |
304 | } | |
305 | priv->eee_active = 0; | |
4741cf9c | 306 | spin_unlock_irqrestore(&priv->lock, flags); |
d765955d | 307 | goto out; |
83bf79b6 GC |
308 | } |
309 | /* Activate the EEE and start timers */ | |
4741cf9c | 310 | spin_lock_irqsave(&priv->lock, flags); |
f5351ef7 GC |
311 | if (!priv->eee_active) { |
312 | priv->eee_active = 1; | |
313 | init_timer(&priv->eee_ctrl_timer); | |
314 | priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; | |
315 | priv->eee_ctrl_timer.data = (unsigned long)priv; | |
316 | priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer); | |
317 | add_timer(&priv->eee_ctrl_timer); | |
318 | ||
7ed24bbe | 319 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 320 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 321 | tx_lpi_timer); |
71965352 GC |
322 | } |
323 | /* Set HW EEE according to the speed */ | |
324 | priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); | |
d765955d | 325 | |
d765955d | 326 | ret = true; |
4741cf9c GC |
327 | spin_unlock_irqrestore(&priv->lock, flags); |
328 | ||
329 | pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); | |
d765955d GC |
330 | } |
331 | out: | |
332 | return ret; | |
333 | } | |
334 | ||
732fdf0e | 335 | /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
32ceabca | 336 | * @priv: driver private structure |
891434b1 RK |
337 | * @entry : descriptor index to be used. |
338 | * @skb : the socket buffer | |
339 | * Description : | |
340 | * This function will read timestamp from the descriptor & pass it to stack. | |
341 | * and also perform some sanity checks. | |
342 | */ | |
343 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 344 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
345 | { |
346 | struct skb_shared_hwtstamps shhwtstamp; | |
347 | u64 ns; | |
348 | void *desc = NULL; | |
349 | ||
350 | if (!priv->hwts_tx_en) | |
351 | return; | |
352 | ||
ceb69499 | 353 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 354 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
355 | return; |
356 | ||
357 | if (priv->adv_ts) | |
358 | desc = (priv->dma_etx + entry); | |
359 | else | |
360 | desc = (priv->dma_tx + entry); | |
361 | ||
362 | /* check tx tstamp status */ | |
363 | if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) | |
364 | return; | |
365 | ||
366 | /* get the valid tstamp */ | |
367 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
368 | ||
369 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
370 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
371 | /* pass tstamp to stack */ | |
372 | skb_tstamp_tx(skb, &shhwtstamp); | |
373 | ||
374 | return; | |
375 | } | |
376 | ||
732fdf0e | 377 | /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
32ceabca | 378 | * @priv: driver private structure |
891434b1 RK |
379 | * @entry : descriptor index to be used. |
380 | * @skb : the socket buffer | |
381 | * Description : | |
382 | * This function will read received packet's timestamp from the descriptor | |
383 | * and pass it to stack. It also perform some sanity checks. | |
384 | */ | |
385 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, | |
ceb69499 | 386 | unsigned int entry, struct sk_buff *skb) |
891434b1 RK |
387 | { |
388 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
389 | u64 ns; | |
390 | void *desc = NULL; | |
391 | ||
392 | if (!priv->hwts_rx_en) | |
393 | return; | |
394 | ||
395 | if (priv->adv_ts) | |
396 | desc = (priv->dma_erx + entry); | |
397 | else | |
398 | desc = (priv->dma_rx + entry); | |
399 | ||
ceb69499 | 400 | /* exit if rx tstamp is not valid */ |
891434b1 RK |
401 | if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) |
402 | return; | |
403 | ||
404 | /* get valid tstamp */ | |
405 | ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); | |
406 | shhwtstamp = skb_hwtstamps(skb); | |
407 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
408 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
409 | } | |
410 | ||
411 | /** | |
412 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
413 | * @dev: device pointer. | |
414 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
415 | * a proprietary structure used to pass information to the driver. | |
416 | * Description: | |
417 | * This function configures the MAC to enable/disable both outgoing(TX) | |
418 | * and incoming(RX) packets time stamping based on user input. | |
419 | * Return Value: | |
420 | * 0 on success and an appropriate -ve integer on failure. | |
421 | */ | |
422 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
423 | { | |
424 | struct stmmac_priv *priv = netdev_priv(dev); | |
425 | struct hwtstamp_config config; | |
426 | struct timespec now; | |
427 | u64 temp = 0; | |
428 | u32 ptp_v2 = 0; | |
429 | u32 tstamp_all = 0; | |
430 | u32 ptp_over_ipv4_udp = 0; | |
431 | u32 ptp_over_ipv6_udp = 0; | |
432 | u32 ptp_over_ethernet = 0; | |
433 | u32 snap_type_sel = 0; | |
434 | u32 ts_master_en = 0; | |
435 | u32 ts_event_en = 0; | |
436 | u32 value = 0; | |
437 | ||
438 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
439 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
440 | priv->hwts_tx_en = 0; | |
441 | priv->hwts_rx_en = 0; | |
442 | ||
443 | return -EOPNOTSUPP; | |
444 | } | |
445 | ||
446 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 447 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
448 | return -EFAULT; |
449 | ||
450 | pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
451 | __func__, config.flags, config.tx_type, config.rx_filter); | |
452 | ||
453 | /* reserved for future extensions */ | |
454 | if (config.flags) | |
455 | return -EINVAL; | |
456 | ||
5f3da328 BH |
457 | if (config.tx_type != HWTSTAMP_TX_OFF && |
458 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 459 | return -ERANGE; |
891434b1 RK |
460 | |
461 | if (priv->adv_ts) { | |
462 | switch (config.rx_filter) { | |
891434b1 | 463 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 464 | /* time stamp no incoming packet at all */ |
891434b1 RK |
465 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
466 | break; | |
467 | ||
891434b1 | 468 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 469 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
470 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
471 | /* take time stamp for all event messages */ | |
472 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
473 | ||
474 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
475 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
476 | break; | |
477 | ||
891434b1 | 478 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 479 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
480 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
481 | /* take time stamp for SYNC messages only */ | |
482 | ts_event_en = PTP_TCR_TSEVNTENA; | |
483 | ||
484 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
485 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
486 | break; | |
487 | ||
891434b1 | 488 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 489 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
490 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
491 | /* take time stamp for Delay_Req messages only */ | |
492 | ts_master_en = PTP_TCR_TSMSTRENA; | |
493 | ts_event_en = PTP_TCR_TSEVNTENA; | |
494 | ||
495 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
496 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
497 | break; | |
498 | ||
891434b1 | 499 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 500 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
501 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
502 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
503 | /* take time stamp for all event messages */ | |
504 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
505 | ||
506 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
507 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
508 | break; | |
509 | ||
891434b1 | 510 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 511 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
512 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
513 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
514 | /* take time stamp for SYNC messages only */ | |
515 | ts_event_en = PTP_TCR_TSEVNTENA; | |
516 | ||
517 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
518 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
519 | break; | |
520 | ||
891434b1 | 521 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 522 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
523 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
524 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
525 | /* take time stamp for Delay_Req messages only */ | |
526 | ts_master_en = PTP_TCR_TSMSTRENA; | |
527 | ts_event_en = PTP_TCR_TSEVNTENA; | |
528 | ||
529 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
530 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
531 | break; | |
532 | ||
891434b1 | 533 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 534 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
535 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
536 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
537 | /* take time stamp for all event messages */ | |
538 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
539 | ||
540 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
541 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
542 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
543 | break; | |
544 | ||
891434b1 | 545 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 546 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
547 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
548 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
549 | /* take time stamp for SYNC messages only */ | |
550 | ts_event_en = PTP_TCR_TSEVNTENA; | |
551 | ||
552 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
553 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
554 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
555 | break; | |
556 | ||
891434b1 | 557 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 558 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
559 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
560 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
561 | /* take time stamp for Delay_Req messages only */ | |
562 | ts_master_en = PTP_TCR_TSMSTRENA; | |
563 | ts_event_en = PTP_TCR_TSEVNTENA; | |
564 | ||
565 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
566 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
567 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
568 | break; | |
569 | ||
891434b1 | 570 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 571 | /* time stamp any incoming packet */ |
891434b1 RK |
572 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
573 | tstamp_all = PTP_TCR_TSENALL; | |
574 | break; | |
575 | ||
576 | default: | |
577 | return -ERANGE; | |
578 | } | |
579 | } else { | |
580 | switch (config.rx_filter) { | |
581 | case HWTSTAMP_FILTER_NONE: | |
582 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
583 | break; | |
584 | default: | |
585 | /* PTP v1, UDP, any kind of event packet */ | |
586 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
587 | break; | |
588 | } | |
589 | } | |
590 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 591 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
592 | |
593 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
594 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); | |
595 | else { | |
596 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
597 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
598 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
599 | ts_master_en | snap_type_sel); | |
891434b1 RK |
600 | |
601 | priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); | |
602 | ||
603 | /* program Sub Second Increment reg */ | |
604 | priv->hw->ptp->config_sub_second_increment(priv->ioaddr); | |
605 | ||
606 | /* calculate default added value: | |
607 | * formula is : | |
608 | * addend = (2^32)/freq_div_ratio; | |
5566401f GC |
609 | * where, freq_div_ratio = clk_ptp_ref_i/50MHz |
610 | * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; | |
611 | * NOTE: clk_ptp_ref_i should be >= 50MHz to | |
891434b1 RK |
612 | * achive 20ns accuracy. |
613 | * | |
614 | * 2^x * y == (y << x), hence | |
615 | * 2^32 * 50000000 ==> (50000000 << 32) | |
616 | */ | |
ceb69499 | 617 | temp = (u64) (50000000ULL << 32); |
5566401f | 618 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
891434b1 RK |
619 | priv->hw->ptp->config_addend(priv->ioaddr, |
620 | priv->default_addend); | |
621 | ||
622 | /* initialize system time */ | |
623 | getnstimeofday(&now); | |
624 | priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, | |
625 | now.tv_nsec); | |
626 | } | |
627 | ||
628 | return copy_to_user(ifr->ifr_data, &config, | |
629 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
630 | } | |
631 | ||
32ceabca | 632 | /** |
732fdf0e | 633 | * stmmac_init_ptp - init PTP |
32ceabca | 634 | * @priv: driver private structure |
732fdf0e | 635 | * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
32ceabca | 636 | * This is done by looking at the HW cap. register. |
732fdf0e | 637 | * This function also registers the ptp driver. |
32ceabca | 638 | */ |
92ba6888 | 639 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 640 | { |
92ba6888 RK |
641 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
642 | return -EOPNOTSUPP; | |
643 | ||
5566401f GC |
644 | /* Fall-back to main clock in case of no PTP ref is passed */ |
645 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
646 | if (IS_ERR(priv->clk_ptp_ref)) { | |
647 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
648 | priv->clk_ptp_ref = NULL; | |
649 | } else { | |
650 | clk_prepare_enable(priv->clk_ptp_ref); | |
651 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
652 | } | |
653 | ||
7cd01399 VB |
654 | priv->adv_ts = 0; |
655 | if (priv->dma_cap.atime_stamp && priv->extend_desc) | |
656 | priv->adv_ts = 1; | |
657 | ||
658 | if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) | |
659 | pr_debug("IEEE 1588-2002 Time Stamp supported\n"); | |
660 | ||
661 | if (netif_msg_hw(priv) && priv->adv_ts) | |
662 | pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); | |
891434b1 RK |
663 | |
664 | priv->hw->ptp = &stmmac_ptp; | |
665 | priv->hwts_tx_en = 0; | |
666 | priv->hwts_rx_en = 0; | |
92ba6888 RK |
667 | |
668 | return stmmac_ptp_register(priv); | |
669 | } | |
670 | ||
671 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
672 | { | |
5566401f GC |
673 | if (priv->clk_ptp_ref) |
674 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 675 | stmmac_ptp_unregister(priv); |
891434b1 RK |
676 | } |
677 | ||
47dd7a54 | 678 | /** |
732fdf0e | 679 | * stmmac_adjust_link - adjusts the link parameters |
47dd7a54 | 680 | * @dev: net device structure |
732fdf0e GC |
681 | * Description: this is the helper called by the physical abstraction layer |
682 | * drivers to communicate the phy link status. According the speed and duplex | |
683 | * this driver can invoke registered glue-logic as well. | |
684 | * It also invoke the eee initialization because it could happen when switch | |
685 | * on different networks (that are eee capable). | |
47dd7a54 GC |
686 | */ |
687 | static void stmmac_adjust_link(struct net_device *dev) | |
688 | { | |
689 | struct stmmac_priv *priv = netdev_priv(dev); | |
690 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
691 | unsigned long flags; |
692 | int new_state = 0; | |
693 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
694 | ||
695 | if (phydev == NULL) | |
696 | return; | |
697 | ||
47dd7a54 | 698 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 699 | |
47dd7a54 | 700 | if (phydev->link) { |
ad01b7d4 | 701 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
702 | |
703 | /* Now we make sure that we can be in full duplex mode. | |
704 | * If not, we operate in half-duplex mode. */ | |
705 | if (phydev->duplex != priv->oldduplex) { | |
706 | new_state = 1; | |
707 | if (!(phydev->duplex)) | |
db98a0b0 | 708 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 709 | else |
db98a0b0 | 710 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
711 | priv->oldduplex = phydev->duplex; |
712 | } | |
713 | /* Flow Control operation */ | |
714 | if (phydev->pause) | |
7ed24bbe | 715 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 716 | fc, pause_time); |
47dd7a54 GC |
717 | |
718 | if (phydev->speed != priv->speed) { | |
719 | new_state = 1; | |
720 | switch (phydev->speed) { | |
721 | case 1000: | |
9dfeb4d9 | 722 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 723 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 724 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
725 | break; |
726 | case 100: | |
727 | case 10: | |
9dfeb4d9 | 728 | if (priv->plat->has_gmac) { |
db98a0b0 | 729 | ctrl |= priv->hw->link.port; |
47dd7a54 | 730 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 731 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 732 | } else { |
db98a0b0 | 733 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
734 | } |
735 | } else { | |
db98a0b0 | 736 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 737 | } |
9dfeb4d9 | 738 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
739 | break; |
740 | default: | |
741 | if (netif_msg_link(priv)) | |
ceb69499 GC |
742 | pr_warn("%s: Speed (%d) not 10/100\n", |
743 | dev->name, phydev->speed); | |
47dd7a54 GC |
744 | break; |
745 | } | |
746 | ||
747 | priv->speed = phydev->speed; | |
748 | } | |
749 | ||
ad01b7d4 | 750 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
751 | |
752 | if (!priv->oldlink) { | |
753 | new_state = 1; | |
754 | priv->oldlink = 1; | |
755 | } | |
756 | } else if (priv->oldlink) { | |
757 | new_state = 1; | |
758 | priv->oldlink = 0; | |
759 | priv->speed = 0; | |
760 | priv->oldduplex = -1; | |
761 | } | |
762 | ||
763 | if (new_state && netif_msg_link(priv)) | |
764 | phy_print_status(phydev); | |
765 | ||
4741cf9c GC |
766 | spin_unlock_irqrestore(&priv->lock, flags); |
767 | ||
f5351ef7 GC |
768 | /* At this stage, it could be needed to setup the EEE or adjust some |
769 | * MAC related HW registers. | |
770 | */ | |
771 | priv->eee_enabled = stmmac_eee_init(priv); | |
47dd7a54 GC |
772 | } |
773 | ||
32ceabca | 774 | /** |
732fdf0e | 775 | * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
32ceabca GC |
776 | * @priv: driver private structure |
777 | * Description: this is to verify if the HW supports the PCS. | |
778 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
779 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
780 | */ | |
e58bb43f GC |
781 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
782 | { | |
783 | int interface = priv->plat->interface; | |
784 | ||
785 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
786 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
787 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
788 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
789 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
e58bb43f GC |
790 | pr_debug("STMMAC: PCS RGMII support enable\n"); |
791 | priv->pcs = STMMAC_PCS_RGMII; | |
0d909dcd | 792 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
e58bb43f GC |
793 | pr_debug("STMMAC: PCS SGMII support enable\n"); |
794 | priv->pcs = STMMAC_PCS_SGMII; | |
795 | } | |
796 | } | |
797 | } | |
798 | ||
47dd7a54 GC |
799 | /** |
800 | * stmmac_init_phy - PHY initialization | |
801 | * @dev: net device structure | |
802 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
803 | * to the mac driver. | |
804 | * Return value: | |
805 | * 0 on success | |
806 | */ | |
807 | static int stmmac_init_phy(struct net_device *dev) | |
808 | { | |
809 | struct stmmac_priv *priv = netdev_priv(dev); | |
810 | struct phy_device *phydev; | |
d765955d | 811 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 812 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 813 | int interface = priv->plat->interface; |
9cbadf09 | 814 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
815 | priv->oldlink = 0; |
816 | priv->speed = 0; | |
817 | priv->oldduplex = -1; | |
818 | ||
f142af2e SK |
819 | if (priv->plat->phy_bus_name) |
820 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
ceb69499 | 821 | priv->plat->phy_bus_name, priv->plat->bus_id); |
f142af2e SK |
822 | else |
823 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
ceb69499 | 824 | priv->plat->bus_id); |
f142af2e | 825 | |
d765955d | 826 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 827 | priv->plat->phy_addr); |
d765955d | 828 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); |
47dd7a54 | 829 | |
f9a8f83b | 830 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); |
47dd7a54 GC |
831 | |
832 | if (IS_ERR(phydev)) { | |
833 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
834 | return PTR_ERR(phydev); | |
835 | } | |
836 | ||
79ee1dc3 | 837 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 838 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 839 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 840 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
841 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
842 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 843 | |
47dd7a54 GC |
844 | /* |
845 | * Broken HW is sometimes missing the pull-up resistor on the | |
846 | * MDIO line, which results in reads to non-existent devices returning | |
847 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
848 | * device as well. | |
849 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
850 | */ | |
851 | if (phydev->phy_id == 0) { | |
852 | phy_disconnect(phydev); | |
853 | return -ENODEV; | |
854 | } | |
855 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 856 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
857 | |
858 | priv->phydev = phydev; | |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
47dd7a54 | 863 | /** |
732fdf0e | 864 | * stmmac_display_ring - display ring |
32ceabca | 865 | * @head: pointer to the head of the ring passed. |
47dd7a54 | 866 | * @size: size of the ring. |
32ceabca | 867 | * @extend_desc: to verify if extended descriptors are used. |
c24602ef | 868 | * Description: display the control/status and buffer descriptors. |
47dd7a54 | 869 | */ |
c24602ef | 870 | static void stmmac_display_ring(void *head, int size, int extend_desc) |
47dd7a54 | 871 | { |
47dd7a54 | 872 | int i; |
ceb69499 GC |
873 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
874 | struct dma_desc *p = (struct dma_desc *)head; | |
c24602ef | 875 | |
47dd7a54 | 876 | for (i = 0; i < size; i++) { |
c24602ef GC |
877 | u64 x; |
878 | if (extend_desc) { | |
879 | x = *(u64 *) ep; | |
880 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
881 | i, (unsigned int)virt_to_phys(ep), |
882 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
883 | ep->basic.des2, ep->basic.des3); |
884 | ep++; | |
885 | } else { | |
886 | x = *(u64 *) p; | |
887 | pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", | |
ceb69499 GC |
888 | i, (unsigned int)virt_to_phys(p), |
889 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
890 | p->des2, p->des3); |
891 | p++; | |
892 | } | |
47dd7a54 GC |
893 | pr_info("\n"); |
894 | } | |
895 | } | |
896 | ||
c24602ef GC |
897 | static void stmmac_display_rings(struct stmmac_priv *priv) |
898 | { | |
899 | unsigned int txsize = priv->dma_tx_size; | |
900 | unsigned int rxsize = priv->dma_rx_size; | |
901 | ||
902 | if (priv->extend_desc) { | |
903 | pr_info("Extended RX descriptor ring:\n"); | |
ceb69499 | 904 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef | 905 | pr_info("Extended TX descriptor ring:\n"); |
ceb69499 | 906 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); |
c24602ef GC |
907 | } else { |
908 | pr_info("RX descriptor ring:\n"); | |
909 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
910 | pr_info("TX descriptor ring:\n"); | |
911 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
912 | } | |
913 | } | |
914 | ||
286a8372 GC |
915 | static int stmmac_set_bfsize(int mtu, int bufsize) |
916 | { | |
917 | int ret = bufsize; | |
918 | ||
919 | if (mtu >= BUF_SIZE_4KiB) | |
920 | ret = BUF_SIZE_8KiB; | |
921 | else if (mtu >= BUF_SIZE_2KiB) | |
922 | ret = BUF_SIZE_4KiB; | |
d916701c | 923 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
924 | ret = BUF_SIZE_2KiB; |
925 | else | |
d916701c | 926 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
927 | |
928 | return ret; | |
929 | } | |
930 | ||
32ceabca | 931 | /** |
732fdf0e | 932 | * stmmac_clear_descriptors - clear descriptors |
32ceabca GC |
933 | * @priv: driver private structure |
934 | * Description: this function is called to clear the tx and rx descriptors | |
935 | * in case of both basic and extended descriptors are used. | |
936 | */ | |
c24602ef GC |
937 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
938 | { | |
939 | int i; | |
940 | unsigned int txsize = priv->dma_tx_size; | |
941 | unsigned int rxsize = priv->dma_rx_size; | |
942 | ||
943 | /* Clear the Rx/Tx descriptors */ | |
944 | for (i = 0; i < rxsize; i++) | |
945 | if (priv->extend_desc) | |
946 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
947 | priv->use_riwt, priv->mode, | |
948 | (i == rxsize - 1)); | |
949 | else | |
950 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
951 | priv->use_riwt, priv->mode, | |
952 | (i == rxsize - 1)); | |
953 | for (i = 0; i < txsize; i++) | |
954 | if (priv->extend_desc) | |
955 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
956 | priv->mode, | |
957 | (i == txsize - 1)); | |
958 | else | |
959 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
960 | priv->mode, | |
961 | (i == txsize - 1)); | |
962 | } | |
963 | ||
732fdf0e GC |
964 | /** |
965 | * stmmac_init_rx_buffers - init the RX descriptor buffer. | |
966 | * @priv: driver private structure | |
967 | * @p: descriptor pointer | |
968 | * @i: descriptor index | |
969 | * @flags: gfp flag. | |
970 | * Description: this function is called to allocate a receive buffer, perform | |
971 | * the DMA mapping and init the descriptor. | |
972 | */ | |
c24602ef | 973 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
777da230 | 974 | int i, gfp_t flags) |
c24602ef GC |
975 | { |
976 | struct sk_buff *skb; | |
977 | ||
978 | skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN, | |
777da230 | 979 | flags); |
56329137 | 980 | if (!skb) { |
c24602ef | 981 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); |
56329137 | 982 | return -ENOMEM; |
c24602ef GC |
983 | } |
984 | skb_reserve(skb, NET_IP_ALIGN); | |
985 | priv->rx_skbuff[i] = skb; | |
986 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
987 | priv->dma_buf_sz, | |
988 | DMA_FROM_DEVICE); | |
56329137 BZ |
989 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
990 | pr_err("%s: DMA mapping error\n", __func__); | |
991 | dev_kfree_skb_any(skb); | |
992 | return -EINVAL; | |
993 | } | |
c24602ef GC |
994 | |
995 | p->des2 = priv->rx_skbuff_dma[i]; | |
996 | ||
29896a67 | 997 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 998 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 999 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
1000 | |
1001 | return 0; | |
1002 | } | |
1003 | ||
56329137 BZ |
1004 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
1005 | { | |
1006 | if (priv->rx_skbuff[i]) { | |
1007 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
1008 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1009 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1010 | } | |
1011 | priv->rx_skbuff[i] = NULL; | |
1012 | } | |
1013 | ||
47dd7a54 GC |
1014 | /** |
1015 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1016 | * @dev: net device structure | |
732fdf0e GC |
1017 | * @flags: gfp flag. |
1018 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1019 | * and allocates the socket buffers. It suppors the chained and ring |
1020 | * modes. | |
47dd7a54 | 1021 | */ |
777da230 | 1022 | static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
47dd7a54 GC |
1023 | { |
1024 | int i; | |
1025 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1026 | unsigned int txsize = priv->dma_tx_size; |
1027 | unsigned int rxsize = priv->dma_rx_size; | |
4a7d666a | 1028 | unsigned int bfsize = 0; |
56329137 | 1029 | int ret = -ENOMEM; |
47dd7a54 | 1030 | |
29896a67 GC |
1031 | if (priv->hw->mode->set_16kib_bfsize) |
1032 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1033 | |
4a7d666a | 1034 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1035 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1036 | |
2618abb7 VB |
1037 | priv->dma_buf_sz = bfsize; |
1038 | ||
83d7af64 GC |
1039 | if (netif_msg_probe(priv)) |
1040 | pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, | |
1041 | txsize, rxsize, bfsize); | |
47dd7a54 | 1042 | |
83d7af64 | 1043 | if (netif_msg_probe(priv)) { |
c24602ef GC |
1044 | pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, |
1045 | (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); | |
47dd7a54 | 1046 | |
83d7af64 GC |
1047 | /* RX INITIALIZATION */ |
1048 | pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); | |
1049 | } | |
47dd7a54 | 1050 | for (i = 0; i < rxsize; i++) { |
c24602ef GC |
1051 | struct dma_desc *p; |
1052 | if (priv->extend_desc) | |
1053 | p = &((priv->dma_erx + i)->basic); | |
1054 | else | |
1055 | p = priv->dma_rx + i; | |
47dd7a54 | 1056 | |
777da230 | 1057 | ret = stmmac_init_rx_buffers(priv, p, i, flags); |
56329137 BZ |
1058 | if (ret) |
1059 | goto err_init_rx_buffers; | |
286a8372 | 1060 | |
83d7af64 GC |
1061 | if (netif_msg_probe(priv)) |
1062 | pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], | |
1063 | priv->rx_skbuff[i]->data, | |
1064 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1065 | } |
1066 | priv->cur_rx = 0; | |
1067 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
47dd7a54 GC |
1068 | buf_sz = bfsize; |
1069 | ||
c24602ef GC |
1070 | /* Setup the chained descriptor addresses */ |
1071 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1072 | if (priv->extend_desc) { | |
29896a67 GC |
1073 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
1074 | rxsize, 1); | |
1075 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, | |
1076 | txsize, 1); | |
c24602ef | 1077 | } else { |
29896a67 GC |
1078 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
1079 | rxsize, 0); | |
1080 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, | |
1081 | txsize, 0); | |
c24602ef GC |
1082 | } |
1083 | } | |
1084 | ||
47dd7a54 GC |
1085 | /* TX INITIALIZATION */ |
1086 | for (i = 0; i < txsize; i++) { | |
c24602ef GC |
1087 | struct dma_desc *p; |
1088 | if (priv->extend_desc) | |
1089 | p = &((priv->dma_etx + i)->basic); | |
1090 | else | |
1091 | p = priv->dma_tx + i; | |
1092 | p->des2 = 0; | |
362b37be GC |
1093 | priv->tx_skbuff_dma[i].buf = 0; |
1094 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 | 1095 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1096 | } |
286a8372 | 1097 | |
47dd7a54 GC |
1098 | priv->dirty_tx = 0; |
1099 | priv->cur_tx = 0; | |
38979574 | 1100 | netdev_reset_queue(priv->dev); |
47dd7a54 | 1101 | |
c24602ef | 1102 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1103 | |
c24602ef GC |
1104 | if (netif_msg_hw(priv)) |
1105 | stmmac_display_rings(priv); | |
56329137 BZ |
1106 | |
1107 | return 0; | |
1108 | err_init_rx_buffers: | |
1109 | while (--i >= 0) | |
1110 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1111 | return ret; |
47dd7a54 GC |
1112 | } |
1113 | ||
1114 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1115 | { | |
1116 | int i; | |
1117 | ||
56329137 BZ |
1118 | for (i = 0; i < priv->dma_rx_size; i++) |
1119 | stmmac_free_rx_buffers(priv, i); | |
47dd7a54 GC |
1120 | } |
1121 | ||
1122 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1123 | { | |
1124 | int i; | |
1125 | ||
1126 | for (i = 0; i < priv->dma_tx_size; i++) { | |
75e4364f | 1127 | struct dma_desc *p; |
1128 | ||
1129 | if (priv->extend_desc) | |
1130 | p = &((priv->dma_etx + i)->basic); | |
1131 | else | |
1132 | p = priv->dma_tx + i; | |
1133 | ||
362b37be GC |
1134 | if (priv->tx_skbuff_dma[i].buf) { |
1135 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1136 | dma_unmap_page(priv->device, | |
1137 | priv->tx_skbuff_dma[i].buf, | |
1138 | priv->hw->desc->get_tx_len(p), | |
1139 | DMA_TO_DEVICE); | |
1140 | else | |
1141 | dma_unmap_single(priv->device, | |
1142 | priv->tx_skbuff_dma[i].buf, | |
1143 | priv->hw->desc->get_tx_len(p), | |
1144 | DMA_TO_DEVICE); | |
75e4364f | 1145 | } |
c24602ef | 1146 | |
75e4364f | 1147 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1148 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1149 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1150 | priv->tx_skbuff_dma[i].buf = 0; |
1151 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1152 | } |
1153 | } | |
47dd7a54 GC |
1154 | } |
1155 | ||
732fdf0e GC |
1156 | /** |
1157 | * alloc_dma_desc_resources - alloc TX/RX resources. | |
1158 | * @priv: private structure | |
1159 | * Description: according to which descriptor can be used (extend or basic) | |
1160 | * this function allocates the resources for TX and RX paths. In case of | |
1161 | * reception, for example, it pre-allocated the RX socket buffer in order to | |
1162 | * allow zero-copy mechanism. | |
1163 | */ | |
09f8d696 SK |
1164 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1165 | { | |
1166 | unsigned int txsize = priv->dma_tx_size; | |
1167 | unsigned int rxsize = priv->dma_rx_size; | |
1168 | int ret = -ENOMEM; | |
1169 | ||
1170 | priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), | |
1171 | GFP_KERNEL); | |
1172 | if (!priv->rx_skbuff_dma) | |
1173 | return -ENOMEM; | |
1174 | ||
1175 | priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), | |
1176 | GFP_KERNEL); | |
1177 | if (!priv->rx_skbuff) | |
1178 | goto err_rx_skbuff; | |
1179 | ||
362b37be GC |
1180 | priv->tx_skbuff_dma = kmalloc_array(txsize, |
1181 | sizeof(*priv->tx_skbuff_dma), | |
09f8d696 SK |
1182 | GFP_KERNEL); |
1183 | if (!priv->tx_skbuff_dma) | |
1184 | goto err_tx_skbuff_dma; | |
1185 | ||
1186 | priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), | |
1187 | GFP_KERNEL); | |
1188 | if (!priv->tx_skbuff) | |
1189 | goto err_tx_skbuff; | |
1190 | ||
1191 | if (priv->extend_desc) { | |
1192 | priv->dma_erx = dma_alloc_coherent(priv->device, rxsize * | |
1193 | sizeof(struct | |
1194 | dma_extended_desc), | |
1195 | &priv->dma_rx_phy, | |
1196 | GFP_KERNEL); | |
1197 | if (!priv->dma_erx) | |
1198 | goto err_dma; | |
1199 | ||
1200 | priv->dma_etx = dma_alloc_coherent(priv->device, txsize * | |
1201 | sizeof(struct | |
1202 | dma_extended_desc), | |
1203 | &priv->dma_tx_phy, | |
1204 | GFP_KERNEL); | |
1205 | if (!priv->dma_etx) { | |
1206 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1207 | sizeof(struct dma_extended_desc), | |
1208 | priv->dma_erx, priv->dma_rx_phy); | |
1209 | goto err_dma; | |
1210 | } | |
1211 | } else { | |
1212 | priv->dma_rx = dma_alloc_coherent(priv->device, rxsize * | |
1213 | sizeof(struct dma_desc), | |
1214 | &priv->dma_rx_phy, | |
1215 | GFP_KERNEL); | |
1216 | if (!priv->dma_rx) | |
1217 | goto err_dma; | |
1218 | ||
1219 | priv->dma_tx = dma_alloc_coherent(priv->device, txsize * | |
1220 | sizeof(struct dma_desc), | |
1221 | &priv->dma_tx_phy, | |
1222 | GFP_KERNEL); | |
1223 | if (!priv->dma_tx) { | |
1224 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1225 | sizeof(struct dma_desc), | |
1226 | priv->dma_rx, priv->dma_rx_phy); | |
1227 | goto err_dma; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | return 0; | |
1232 | ||
1233 | err_dma: | |
1234 | kfree(priv->tx_skbuff); | |
1235 | err_tx_skbuff: | |
1236 | kfree(priv->tx_skbuff_dma); | |
1237 | err_tx_skbuff_dma: | |
1238 | kfree(priv->rx_skbuff); | |
1239 | err_rx_skbuff: | |
1240 | kfree(priv->rx_skbuff_dma); | |
1241 | return ret; | |
1242 | } | |
1243 | ||
47dd7a54 GC |
1244 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1245 | { | |
1246 | /* Release the DMA TX/RX socket buffers */ | |
1247 | dma_free_rx_skbufs(priv); | |
1248 | dma_free_tx_skbufs(priv); | |
1249 | ||
ceb69499 | 1250 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1251 | if (!priv->extend_desc) { |
1252 | dma_free_coherent(priv->device, | |
1253 | priv->dma_tx_size * sizeof(struct dma_desc), | |
1254 | priv->dma_tx, priv->dma_tx_phy); | |
1255 | dma_free_coherent(priv->device, | |
1256 | priv->dma_rx_size * sizeof(struct dma_desc), | |
1257 | priv->dma_rx, priv->dma_rx_phy); | |
1258 | } else { | |
1259 | dma_free_coherent(priv->device, priv->dma_tx_size * | |
1260 | sizeof(struct dma_extended_desc), | |
1261 | priv->dma_etx, priv->dma_tx_phy); | |
1262 | dma_free_coherent(priv->device, priv->dma_rx_size * | |
1263 | sizeof(struct dma_extended_desc), | |
1264 | priv->dma_erx, priv->dma_rx_phy); | |
1265 | } | |
47dd7a54 GC |
1266 | kfree(priv->rx_skbuff_dma); |
1267 | kfree(priv->rx_skbuff); | |
cf32deec | 1268 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1269 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1270 | } |
1271 | ||
47dd7a54 GC |
1272 | /** |
1273 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1274 | * @priv: driver private structure |
732fdf0e GC |
1275 | * Description: it is used for configuring the DMA operation mode register in |
1276 | * order to program the tx/rx DMA thresholds or Store-And-Forward mode. | |
47dd7a54 GC |
1277 | */ |
1278 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1279 | { | |
e2a240c7 SZ |
1280 | if (priv->plat->force_thresh_dma_mode) |
1281 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); | |
1282 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { | |
61b8013a SK |
1283 | /* |
1284 | * In case of GMAC, SF mode can be enabled | |
1285 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1286 | * 1) TX COE if actually supported |
1287 | * 2) There is no bugged Jumbo frame support | |
1288 | * that needs to not insert csum in the TDES. | |
1289 | */ | |
ceb69499 | 1290 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE); |
ebbb293f GC |
1291 | tc = SF_DMA_MODE; |
1292 | } else | |
1293 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
1294 | } |
1295 | ||
47dd7a54 | 1296 | /** |
732fdf0e | 1297 | * stmmac_tx_clean - to manage the transmission completion |
32ceabca | 1298 | * @priv: driver private structure |
732fdf0e | 1299 | * Description: it reclaims the transmit resources after transmission completes. |
47dd7a54 | 1300 | */ |
9125cdd1 | 1301 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 GC |
1302 | { |
1303 | unsigned int txsize = priv->dma_tx_size; | |
38979574 | 1304 | unsigned int bytes_compl = 0, pkts_compl = 0; |
47dd7a54 | 1305 | |
a9097a96 GC |
1306 | spin_lock(&priv->tx_lock); |
1307 | ||
9125cdd1 GC |
1308 | priv->xstats.tx_clean++; |
1309 | ||
47dd7a54 GC |
1310 | while (priv->dirty_tx != priv->cur_tx) { |
1311 | int last; | |
1312 | unsigned int entry = priv->dirty_tx % txsize; | |
1313 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
c24602ef GC |
1314 | struct dma_desc *p; |
1315 | ||
1316 | if (priv->extend_desc) | |
ceb69499 | 1317 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1318 | else |
1319 | p = priv->dma_tx + entry; | |
47dd7a54 GC |
1320 | |
1321 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 1322 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
1323 | break; |
1324 | ||
c24602ef | 1325 | /* Verify tx error by looking at the last segment. */ |
db98a0b0 | 1326 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
1327 | if (likely(last)) { |
1328 | int tx_error = | |
ceb69499 GC |
1329 | priv->hw->desc->tx_status(&priv->dev->stats, |
1330 | &priv->xstats, p, | |
1331 | priv->ioaddr); | |
47dd7a54 GC |
1332 | if (likely(tx_error == 0)) { |
1333 | priv->dev->stats.tx_packets++; | |
1334 | priv->xstats.tx_pkt_n++; | |
1335 | } else | |
1336 | priv->dev->stats.tx_errors++; | |
891434b1 RK |
1337 | |
1338 | stmmac_get_tx_hwtstamp(priv, entry, skb); | |
47dd7a54 | 1339 | } |
83d7af64 GC |
1340 | if (netif_msg_tx_done(priv)) |
1341 | pr_debug("%s: curr %d, dirty %d\n", __func__, | |
1342 | priv->cur_tx, priv->dirty_tx); | |
47dd7a54 | 1343 | |
362b37be GC |
1344 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1345 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1346 | dma_unmap_page(priv->device, | |
1347 | priv->tx_skbuff_dma[entry].buf, | |
1348 | priv->hw->desc->get_tx_len(p), | |
1349 | DMA_TO_DEVICE); | |
1350 | else | |
1351 | dma_unmap_single(priv->device, | |
1352 | priv->tx_skbuff_dma[entry].buf, | |
1353 | priv->hw->desc->get_tx_len(p), | |
1354 | DMA_TO_DEVICE); | |
1355 | priv->tx_skbuff_dma[entry].buf = 0; | |
1356 | priv->tx_skbuff_dma[entry].map_as_page = false; | |
cf32deec | 1357 | } |
29896a67 | 1358 | priv->hw->mode->clean_desc3(priv, p); |
47dd7a54 GC |
1359 | |
1360 | if (likely(skb != NULL)) { | |
38979574 BG |
1361 | pkts_compl++; |
1362 | bytes_compl += skb->len; | |
7c565c33 | 1363 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1364 | priv->tx_skbuff[entry] = NULL; |
1365 | } | |
1366 | ||
4a7d666a | 1367 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1368 | |
13497f58 | 1369 | priv->dirty_tx++; |
47dd7a54 | 1370 | } |
38979574 BG |
1371 | |
1372 | netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); | |
1373 | ||
47dd7a54 GC |
1374 | if (unlikely(netif_queue_stopped(priv->dev) && |
1375 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
1376 | netif_tx_lock(priv->dev); | |
1377 | if (netif_queue_stopped(priv->dev) && | |
ceb69499 | 1378 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { |
83d7af64 GC |
1379 | if (netif_msg_tx_done(priv)) |
1380 | pr_debug("%s: restart transmit\n", __func__); | |
47dd7a54 GC |
1381 | netif_wake_queue(priv->dev); |
1382 | } | |
1383 | netif_tx_unlock(priv->dev); | |
1384 | } | |
d765955d GC |
1385 | |
1386 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1387 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1388 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1389 | } |
a9097a96 | 1390 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1391 | } |
1392 | ||
9125cdd1 | 1393 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1394 | { |
7284a3f1 | 1395 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1396 | } |
1397 | ||
9125cdd1 | 1398 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1399 | { |
7284a3f1 | 1400 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1401 | } |
1402 | ||
47dd7a54 | 1403 | /** |
732fdf0e | 1404 | * stmmac_tx_err - to manage the tx error |
32ceabca | 1405 | * @priv: driver private structure |
47dd7a54 | 1406 | * Description: it cleans the descriptors and restarts the transmission |
732fdf0e | 1407 | * in case of transmission errors. |
47dd7a54 GC |
1408 | */ |
1409 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1410 | { | |
c24602ef GC |
1411 | int i; |
1412 | int txsize = priv->dma_tx_size; | |
47dd7a54 GC |
1413 | netif_stop_queue(priv->dev); |
1414 | ||
ad01b7d4 | 1415 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1416 | dma_free_tx_skbufs(priv); |
c24602ef GC |
1417 | for (i = 0; i < txsize; i++) |
1418 | if (priv->extend_desc) | |
1419 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1420 | priv->mode, | |
1421 | (i == txsize - 1)); | |
1422 | else | |
1423 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1424 | priv->mode, | |
1425 | (i == txsize - 1)); | |
47dd7a54 GC |
1426 | priv->dirty_tx = 0; |
1427 | priv->cur_tx = 0; | |
38979574 | 1428 | netdev_reset_queue(priv->dev); |
ad01b7d4 | 1429 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1430 | |
1431 | priv->dev->stats.tx_errors++; | |
1432 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1433 | } |
1434 | ||
32ceabca | 1435 | /** |
732fdf0e | 1436 | * stmmac_dma_interrupt - DMA ISR |
32ceabca GC |
1437 | * @priv: driver private structure |
1438 | * Description: this is the DMA ISR. It is called by the main ISR. | |
732fdf0e GC |
1439 | * It calls the dwmac dma routine and schedule poll method in case of some |
1440 | * work can be done. | |
32ceabca | 1441 | */ |
aec7ff27 GC |
1442 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1443 | { | |
aec7ff27 GC |
1444 | int status; |
1445 | ||
ad01b7d4 | 1446 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1447 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1448 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1449 | stmmac_disable_dma_irq(priv); | |
1450 | __napi_schedule(&priv->napi); | |
1451 | } | |
1452 | } | |
1453 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 GC |
1454 | /* Try to bump up the dma threshold on this failure */ |
1455 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
1456 | tc += 64; | |
c405abe2 SZ |
1457 | if (priv->plat->force_thresh_dma_mode) |
1458 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc); | |
1459 | else | |
1460 | priv->hw->dma->dma_mode(priv->ioaddr, tc, | |
1461 | SF_DMA_MODE); | |
aec7ff27 | 1462 | priv->xstats.threshold = tc; |
47dd7a54 | 1463 | } |
aec7ff27 GC |
1464 | } else if (unlikely(status == tx_hard_error)) |
1465 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1466 | } |
1467 | ||
32ceabca GC |
1468 | /** |
1469 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1470 | * @priv: driver private structure | |
1471 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1472 | */ | |
1c901a46 GC |
1473 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1474 | { | |
1475 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
ceb69499 | 1476 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1477 | |
1c901a46 | 1478 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
1479 | |
1480 | if (priv->dma_cap.rmon) { | |
1481 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
1482 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
1483 | } else | |
aae54cff | 1484 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
1485 | } |
1486 | ||
732fdf0e GC |
1487 | /** |
1488 | * stmmac_get_synopsys_id - return the SYINID. | |
1489 | * @priv: driver private structure | |
1490 | * Description: this simple function is to decode and return the SYINID | |
1491 | * starting from the HW core register. | |
1492 | */ | |
f0b9d786 GC |
1493 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
1494 | { | |
1495 | u32 hwid = priv->hw->synopsys_uid; | |
1496 | ||
ceb69499 | 1497 | /* Check Synopsys Id (not available on old chips) */ |
f0b9d786 GC |
1498 | if (likely(hwid)) { |
1499 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
1500 | u32 synid = (hwid & 0x000000ff); | |
1501 | ||
cf3f047b | 1502 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
1503 | uid, synid); |
1504 | ||
1505 | return synid; | |
1506 | } | |
1507 | return 0; | |
1508 | } | |
e7434821 | 1509 | |
19e30c14 | 1510 | /** |
732fdf0e | 1511 | * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
32ceabca GC |
1512 | * @priv: driver private structure |
1513 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
732fdf0e GC |
1514 | * In case of Enhanced/Alternate, it checks if the extended descriptors are |
1515 | * supported by the HW capability register. | |
ff3dd78c | 1516 | */ |
19e30c14 GC |
1517 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1518 | { | |
1519 | if (priv->plat->enh_desc) { | |
1520 | pr_info(" Enhanced/Alternate descriptors\n"); | |
c24602ef GC |
1521 | |
1522 | /* GMAC older than 3.50 has no extended descriptors */ | |
1523 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
1524 | pr_info("\tEnabled extended descriptors\n"); | |
1525 | priv->extend_desc = 1; | |
1526 | } else | |
1527 | pr_warn("Extended descriptors not supported\n"); | |
1528 | ||
19e30c14 GC |
1529 | priv->hw->desc = &enh_desc_ops; |
1530 | } else { | |
1531 | pr_info(" Normal descriptors\n"); | |
1532 | priv->hw->desc = &ndesc_ops; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | /** | |
732fdf0e | 1537 | * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
32ceabca | 1538 | * @priv: driver private structure |
19e30c14 GC |
1539 | * Description: |
1540 | * new GMAC chip generations have a new register to indicate the | |
1541 | * presence of the optional feature/functions. | |
1542 | * This can be also used to override the value passed through the | |
1543 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1544 | */ |
1545 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1546 | { | |
5e6efe88 | 1547 | u32 hw_cap = 0; |
3c20f72f | 1548 | |
5e6efe88 GC |
1549 | if (priv->hw->dma->get_hw_feature) { |
1550 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 1551 | |
1db123fb RK |
1552 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
1553 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
1554 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
1555 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
ceb69499 | 1556 | priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; |
1db123fb RK |
1557 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; |
1558 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
1559 | priv->dma_cap.pmt_remote_wake_up = | |
ceb69499 | 1560 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; |
1db123fb | 1561 | priv->dma_cap.pmt_magic_frame = |
ceb69499 | 1562 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; |
19e30c14 | 1563 | /* MMC */ |
1db123fb | 1564 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
ceb69499 | 1565 | /* IEEE 1588-2002 */ |
1db123fb | 1566 | priv->dma_cap.time_stamp = |
ceb69499 GC |
1567 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; |
1568 | /* IEEE 1588-2008 */ | |
1db123fb | 1569 | priv->dma_cap.atime_stamp = |
ceb69499 | 1570 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; |
e7434821 | 1571 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
1572 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
1573 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 1574 | /* TX and RX csum */ |
1db123fb RK |
1575 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
1576 | priv->dma_cap.rx_coe_type1 = | |
ceb69499 | 1577 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; |
1db123fb | 1578 | priv->dma_cap.rx_coe_type2 = |
ceb69499 | 1579 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; |
1db123fb | 1580 | priv->dma_cap.rxfifo_over_2048 = |
ceb69499 | 1581 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; |
e7434821 | 1582 | /* TX and RX number of channels */ |
1db123fb | 1583 | priv->dma_cap.number_rx_channel = |
ceb69499 | 1584 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; |
1db123fb | 1585 | priv->dma_cap.number_tx_channel = |
ceb69499 GC |
1586 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; |
1587 | /* Alternate (enhanced) DESC mode */ | |
1588 | priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
19e30c14 | 1589 | } |
e7434821 GC |
1590 | |
1591 | return hw_cap; | |
1592 | } | |
1593 | ||
32ceabca | 1594 | /** |
732fdf0e | 1595 | * stmmac_check_ether_addr - check if the MAC addr is valid |
32ceabca GC |
1596 | * @priv: driver private structure |
1597 | * Description: | |
1598 | * it is to verify if the MAC address is valid, in case of failures it | |
1599 | * generates a random MAC address | |
1600 | */ | |
bfab27a1 GC |
1601 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1602 | { | |
bfab27a1 | 1603 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1604 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1605 | priv->dev->dev_addr, 0); |
ceb69499 | 1606 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1607 | eth_hw_addr_random(priv->dev); |
c88460b7 HG |
1608 | pr_info("%s: device MAC address %pM\n", priv->dev->name, |
1609 | priv->dev->dev_addr); | |
bfab27a1 | 1610 | } |
bfab27a1 GC |
1611 | } |
1612 | ||
32ceabca | 1613 | /** |
732fdf0e | 1614 | * stmmac_init_dma_engine - DMA init. |
32ceabca GC |
1615 | * @priv: driver private structure |
1616 | * Description: | |
1617 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1618 | * Some DMA parameters can be passed from the platform; | |
1619 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1620 | */ | |
0f1f88a8 GC |
1621 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1622 | { | |
1623 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; | |
b9cde0a8 | 1624 | int mixed_burst = 0; |
c24602ef | 1625 | int atds = 0; |
0f1f88a8 | 1626 | |
0f1f88a8 GC |
1627 | if (priv->plat->dma_cfg) { |
1628 | pbl = priv->plat->dma_cfg->pbl; | |
1629 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
b9cde0a8 | 1630 | mixed_burst = priv->plat->dma_cfg->mixed_burst; |
0f1f88a8 GC |
1631 | burst_len = priv->plat->dma_cfg->burst_len; |
1632 | } | |
1633 | ||
c24602ef GC |
1634 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1635 | atds = 1; | |
1636 | ||
b9cde0a8 | 1637 | return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, |
0f1f88a8 | 1638 | burst_len, priv->dma_tx_phy, |
c24602ef | 1639 | priv->dma_rx_phy, atds); |
0f1f88a8 GC |
1640 | } |
1641 | ||
9125cdd1 | 1642 | /** |
732fdf0e | 1643 | * stmmac_tx_timer - mitigation sw timer for tx. |
9125cdd1 GC |
1644 | * @data: data pointer |
1645 | * Description: | |
1646 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1647 | */ | |
1648 | static void stmmac_tx_timer(unsigned long data) | |
1649 | { | |
1650 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1651 | ||
1652 | stmmac_tx_clean(priv); | |
1653 | } | |
1654 | ||
1655 | /** | |
732fdf0e | 1656 | * stmmac_init_tx_coalesce - init tx mitigation options. |
32ceabca | 1657 | * @priv: driver private structure |
9125cdd1 GC |
1658 | * Description: |
1659 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1660 | * timer handler and default threshold used for enabling the | |
1661 | * interrupt on completion bit. | |
1662 | */ | |
1663 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1664 | { | |
1665 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1666 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1667 | init_timer(&priv->txtimer); | |
1668 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1669 | priv->txtimer.data = (unsigned long)priv; | |
1670 | priv->txtimer.function = stmmac_tx_timer; | |
1671 | add_timer(&priv->txtimer); | |
1672 | } | |
1673 | ||
523f11b5 | 1674 | /** |
732fdf0e | 1675 | * stmmac_hw_setup - setup mac in a usable state. |
523f11b5 SK |
1676 | * @dev : pointer to the device structure. |
1677 | * Description: | |
732fdf0e GC |
1678 | * this is the main function to setup the HW in a usable state because the |
1679 | * dma engine is reset, the core registers are configured (e.g. AXI, | |
1680 | * Checksum features, timers). The DMA is ready to start receiving and | |
1681 | * transmitting. | |
523f11b5 SK |
1682 | * Return value: |
1683 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1684 | * file on failure. | |
1685 | */ | |
fe131929 | 1686 | static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
523f11b5 SK |
1687 | { |
1688 | struct stmmac_priv *priv = netdev_priv(dev); | |
1689 | int ret; | |
1690 | ||
523f11b5 SK |
1691 | /* DMA initialization and SW reset */ |
1692 | ret = stmmac_init_dma_engine(priv); | |
1693 | if (ret < 0) { | |
1694 | pr_err("%s: DMA engine initialization failed\n", __func__); | |
1695 | return ret; | |
1696 | } | |
1697 | ||
1698 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1699 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1700 | |
1701 | /* If required, perform hw setup of the bus. */ | |
1702 | if (priv->plat->bus_setup) | |
1703 | priv->plat->bus_setup(priv->ioaddr); | |
1704 | ||
1705 | /* Initialize the MAC Core */ | |
7ed24bbe | 1706 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1707 | |
978aded4 GC |
1708 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1709 | if (!ret) { | |
1710 | pr_warn(" RX IPC Checksum Offload disabled\n"); | |
1711 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
d2afb5bd | 1712 | priv->hw->rx_csum = 0; |
978aded4 GC |
1713 | } |
1714 | ||
523f11b5 SK |
1715 | /* Enable the MAC Rx/Tx */ |
1716 | stmmac_set_mac(priv->ioaddr, true); | |
1717 | ||
1718 | /* Set the HW DMA mode and the COE */ | |
1719 | stmmac_dma_operation_mode(priv); | |
1720 | ||
1721 | stmmac_mmc_setup(priv); | |
1722 | ||
fe131929 HC |
1723 | if (init_ptp) { |
1724 | ret = stmmac_init_ptp(priv); | |
1725 | if (ret && ret != -EOPNOTSUPP) | |
1726 | pr_warn("%s: failed PTP initialisation\n", __func__); | |
1727 | } | |
523f11b5 | 1728 | |
50fb4f74 | 1729 | #ifdef CONFIG_DEBUG_FS |
523f11b5 SK |
1730 | ret = stmmac_init_fs(dev); |
1731 | if (ret < 0) | |
1732 | pr_warn("%s: failed debugFS registration\n", __func__); | |
1733 | #endif | |
1734 | /* Start the ball rolling... */ | |
1735 | pr_debug("%s: DMA RX/TX processes started...\n", dev->name); | |
1736 | priv->hw->dma->start_tx(priv->ioaddr); | |
1737 | priv->hw->dma->start_rx(priv->ioaddr); | |
1738 | ||
1739 | /* Dump DMA/MAC registers */ | |
1740 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1741 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1742 | priv->hw->dma->dump_regs(priv->ioaddr); |
1743 | } | |
1744 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1745 | ||
523f11b5 SK |
1746 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
1747 | priv->rx_riwt = MAX_DMA_RIWT; | |
1748 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1749 | } | |
1750 | ||
1751 | if (priv->pcs && priv->hw->mac->ctrl_ane) | |
7ed24bbe | 1752 | priv->hw->mac->ctrl_ane(priv->hw, 0); |
523f11b5 SK |
1753 | |
1754 | return 0; | |
1755 | } | |
1756 | ||
47dd7a54 GC |
1757 | /** |
1758 | * stmmac_open - open entry point of the driver | |
1759 | * @dev : pointer to the device structure. | |
1760 | * Description: | |
1761 | * This function is the open entry point of the driver. | |
1762 | * Return value: | |
1763 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1764 | * file on failure. | |
1765 | */ | |
1766 | static int stmmac_open(struct net_device *dev) | |
1767 | { | |
1768 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1769 | int ret; |
1770 | ||
4bfcbd7a FV |
1771 | stmmac_check_ether_addr(priv); |
1772 | ||
4d8f0825 BA |
1773 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
1774 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1775 | ret = stmmac_init_phy(dev); |
1776 | if (ret) { | |
1777 | pr_err("%s: Cannot attach to PHY (error: %d)\n", | |
1778 | __func__, ret); | |
89df20d9 | 1779 | return ret; |
e58bb43f | 1780 | } |
f66ffe28 | 1781 | } |
47dd7a54 | 1782 | |
523f11b5 SK |
1783 | /* Extra statistics */ |
1784 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1785 | priv->xstats.threshold = tc; | |
1786 | ||
47dd7a54 GC |
1787 | /* Create and initialize the TX/RX descriptors chains. */ |
1788 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
1789 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
1790 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
56329137 | 1791 | |
7262b7b2 | 1792 | ret = alloc_dma_desc_resources(priv); |
09f8d696 SK |
1793 | if (ret < 0) { |
1794 | pr_err("%s: DMA descriptors allocation failed\n", __func__); | |
1795 | goto dma_desc_error; | |
1796 | } | |
1797 | ||
777da230 GC |
1798 | ret = init_dma_desc_rings(dev, GFP_KERNEL); |
1799 | if (ret < 0) { | |
1800 | pr_err("%s: DMA descriptors initialization failed\n", __func__); | |
1801 | goto init_error; | |
1802 | } | |
1803 | ||
fe131929 | 1804 | ret = stmmac_hw_setup(dev, true); |
56329137 | 1805 | if (ret < 0) { |
523f11b5 | 1806 | pr_err("%s: Hw setup failed\n", __func__); |
c9324d18 | 1807 | goto init_error; |
47dd7a54 GC |
1808 | } |
1809 | ||
777da230 GC |
1810 | stmmac_init_tx_coalesce(priv); |
1811 | ||
523f11b5 SK |
1812 | if (priv->phydev) |
1813 | phy_start(priv->phydev); | |
47dd7a54 | 1814 | |
f66ffe28 GC |
1815 | /* Request the IRQ lines */ |
1816 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1817 | IRQF_SHARED, dev->name, dev); |
f66ffe28 GC |
1818 | if (unlikely(ret < 0)) { |
1819 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1820 | __func__, dev->irq, ret); | |
c9324d18 | 1821 | goto init_error; |
f66ffe28 GC |
1822 | } |
1823 | ||
7a13f8f5 FV |
1824 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1825 | if (priv->wol_irq != dev->irq) { | |
1826 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1827 | IRQF_SHARED, dev->name, dev); | |
1828 | if (unlikely(ret < 0)) { | |
ceb69499 GC |
1829 | pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", |
1830 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1831 | goto wolirq_error; |
7a13f8f5 FV |
1832 | } |
1833 | } | |
1834 | ||
d765955d | 1835 | /* Request the IRQ lines */ |
d7ec8584 | 1836 | if (priv->lpi_irq > 0) { |
d765955d GC |
1837 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1838 | dev->name, dev); | |
1839 | if (unlikely(ret < 0)) { | |
1840 | pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1841 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1842 | goto lpiirq_error; |
d765955d GC |
1843 | } |
1844 | } | |
1845 | ||
47dd7a54 | 1846 | napi_enable(&priv->napi); |
47dd7a54 | 1847 | netif_start_queue(dev); |
f66ffe28 | 1848 | |
47dd7a54 | 1849 | return 0; |
f66ffe28 | 1850 | |
c9324d18 | 1851 | lpiirq_error: |
d765955d GC |
1852 | if (priv->wol_irq != dev->irq) |
1853 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1854 | wolirq_error: |
7a13f8f5 FV |
1855 | free_irq(dev->irq, dev); |
1856 | ||
c9324d18 GC |
1857 | init_error: |
1858 | free_dma_desc_resources(priv); | |
56329137 | 1859 | dma_desc_error: |
f66ffe28 GC |
1860 | if (priv->phydev) |
1861 | phy_disconnect(priv->phydev); | |
4bfcbd7a | 1862 | |
f66ffe28 | 1863 | return ret; |
47dd7a54 GC |
1864 | } |
1865 | ||
1866 | /** | |
1867 | * stmmac_release - close entry point of the driver | |
1868 | * @dev : device pointer. | |
1869 | * Description: | |
1870 | * This is the stop entry point of the driver. | |
1871 | */ | |
1872 | static int stmmac_release(struct net_device *dev) | |
1873 | { | |
1874 | struct stmmac_priv *priv = netdev_priv(dev); | |
1875 | ||
d765955d GC |
1876 | if (priv->eee_enabled) |
1877 | del_timer_sync(&priv->eee_ctrl_timer); | |
1878 | ||
47dd7a54 GC |
1879 | /* Stop and disconnect the PHY */ |
1880 | if (priv->phydev) { | |
1881 | phy_stop(priv->phydev); | |
1882 | phy_disconnect(priv->phydev); | |
1883 | priv->phydev = NULL; | |
1884 | } | |
1885 | ||
1886 | netif_stop_queue(dev); | |
1887 | ||
47dd7a54 | 1888 | napi_disable(&priv->napi); |
47dd7a54 | 1889 | |
9125cdd1 GC |
1890 | del_timer_sync(&priv->txtimer); |
1891 | ||
47dd7a54 GC |
1892 | /* Free the IRQ lines */ |
1893 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1894 | if (priv->wol_irq != dev->irq) |
1895 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1896 | if (priv->lpi_irq > 0) |
d765955d | 1897 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1898 | |
1899 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1900 | priv->hw->dma->stop_tx(priv->ioaddr); |
1901 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1902 | |
1903 | /* Release and free the Rx/Tx resources */ | |
1904 | free_dma_desc_resources(priv); | |
1905 | ||
19449bfc | 1906 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1907 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1908 | |
1909 | netif_carrier_off(dev); | |
1910 | ||
50fb4f74 | 1911 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 GC |
1912 | stmmac_exit_fs(); |
1913 | #endif | |
bfab27a1 | 1914 | |
92ba6888 RK |
1915 | stmmac_release_ptp(priv); |
1916 | ||
47dd7a54 GC |
1917 | return 0; |
1918 | } | |
1919 | ||
47dd7a54 | 1920 | /** |
732fdf0e | 1921 | * stmmac_xmit - Tx entry point of the driver |
47dd7a54 GC |
1922 | * @skb : the socket buffer |
1923 | * @dev : device pointer | |
32ceabca GC |
1924 | * Description : this is the tx entry point of the driver. |
1925 | * It programs the chain or the ring and supports oversized frames | |
1926 | * and SG feature. | |
47dd7a54 GC |
1927 | */ |
1928 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1929 | { | |
1930 | struct stmmac_priv *priv = netdev_priv(dev); | |
1931 | unsigned int txsize = priv->dma_tx_size; | |
1932 | unsigned int entry; | |
4a7d666a | 1933 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 GC |
1934 | int nfrags = skb_shinfo(skb)->nr_frags; |
1935 | struct dma_desc *desc, *first; | |
286a8372 | 1936 | unsigned int nopaged_len = skb_headlen(skb); |
29896a67 | 1937 | unsigned int enh_desc = priv->plat->enh_desc; |
47dd7a54 | 1938 | |
16ee817e FG |
1939 | spin_lock(&priv->tx_lock); |
1940 | ||
47dd7a54 | 1941 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { |
16ee817e | 1942 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
1943 | if (!netif_queue_stopped(dev)) { |
1944 | netif_stop_queue(dev); | |
1945 | /* This is a hard error, log it. */ | |
ceb69499 | 1946 | pr_err("%s: Tx Ring full when queue awake\n", __func__); |
47dd7a54 GC |
1947 | } |
1948 | return NETDEV_TX_BUSY; | |
1949 | } | |
1950 | ||
d765955d GC |
1951 | if (priv->tx_path_in_lpi_mode) |
1952 | stmmac_disable_eee_mode(priv); | |
1953 | ||
47dd7a54 GC |
1954 | entry = priv->cur_tx % txsize; |
1955 | ||
5e982f3b | 1956 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 1957 | |
c24602ef | 1958 | if (priv->extend_desc) |
ceb69499 | 1959 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1960 | else |
1961 | desc = priv->dma_tx + entry; | |
1962 | ||
47dd7a54 GC |
1963 | first = desc; |
1964 | ||
4a7d666a | 1965 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
1966 | if (enh_desc) |
1967 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
1968 | ||
4a7d666a | 1969 | if (likely(!is_jumbo)) { |
47dd7a54 | 1970 | desc->des2 = dma_map_single(priv->device, skb->data, |
ceb69499 | 1971 | nopaged_len, DMA_TO_DEVICE); |
362b37be GC |
1972 | if (dma_mapping_error(priv->device, desc->des2)) |
1973 | goto dma_map_err; | |
1974 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
db98a0b0 | 1975 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
4a7d666a | 1976 | csum_insertion, priv->mode); |
29896a67 | 1977 | } else { |
c24602ef | 1978 | desc = first; |
29896a67 | 1979 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
1980 | if (unlikely(entry < 0)) |
1981 | goto dma_map_err; | |
29896a67 | 1982 | } |
47dd7a54 GC |
1983 | |
1984 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1985 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1986 | int len = skb_frag_size(frag); | |
47dd7a54 | 1987 | |
75e4364f | 1988 | priv->tx_skbuff[entry] = NULL; |
47dd7a54 | 1989 | entry = (++priv->cur_tx) % txsize; |
c24602ef | 1990 | if (priv->extend_desc) |
ceb69499 | 1991 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1992 | else |
1993 | desc = priv->dma_tx + entry; | |
47dd7a54 | 1994 | |
f722380d IC |
1995 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1996 | DMA_TO_DEVICE); | |
362b37be GC |
1997 | if (dma_mapping_error(priv->device, desc->des2)) |
1998 | goto dma_map_err; /* should reuse desc w/o issues */ | |
1999 | ||
2000 | priv->tx_skbuff_dma[entry].buf = desc->des2; | |
2001 | priv->tx_skbuff_dma[entry].map_as_page = true; | |
4a7d666a GC |
2002 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
2003 | priv->mode); | |
eb0dc4bb | 2004 | wmb(); |
db98a0b0 | 2005 | priv->hw->desc->set_tx_owner(desc); |
8e839891 | 2006 | wmb(); |
47dd7a54 GC |
2007 | } |
2008 | ||
75e4364f | 2009 | priv->tx_skbuff[entry] = skb; |
2010 | ||
9125cdd1 | 2011 | /* Finalize the latest segment. */ |
db98a0b0 | 2012 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 2013 | |
eb0dc4bb | 2014 | wmb(); |
9125cdd1 GC |
2015 | /* According to the coalesce parameter the IC bit for the latest |
2016 | * segment could be reset and the timer re-started to invoke the | |
2017 | * stmmac_tx function. This approach takes care about the fragments. | |
2018 | */ | |
2019 | priv->tx_count_frames += nfrags + 1; | |
2020 | if (priv->tx_coal_frames > priv->tx_count_frames) { | |
2021 | priv->hw->desc->clear_tx_ic(desc); | |
2022 | priv->xstats.tx_reset_ic_bit++; | |
9125cdd1 GC |
2023 | mod_timer(&priv->txtimer, |
2024 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2025 | } else | |
2026 | priv->tx_count_frames = 0; | |
eb0dc4bb | 2027 | |
47dd7a54 | 2028 | /* To avoid raise condition */ |
db98a0b0 | 2029 | priv->hw->desc->set_tx_owner(first); |
8e839891 | 2030 | wmb(); |
47dd7a54 GC |
2031 | |
2032 | priv->cur_tx++; | |
2033 | ||
47dd7a54 | 2034 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2035 | pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", |
ceb69499 GC |
2036 | __func__, (priv->cur_tx % txsize), |
2037 | (priv->dirty_tx % txsize), entry, first, nfrags); | |
83d7af64 | 2038 | |
c24602ef GC |
2039 | if (priv->extend_desc) |
2040 | stmmac_display_ring((void *)priv->dma_etx, txsize, 1); | |
2041 | else | |
2042 | stmmac_display_ring((void *)priv->dma_tx, txsize, 0); | |
2043 | ||
83d7af64 | 2044 | pr_debug(">>> frame to be transmitted: "); |
47dd7a54 GC |
2045 | print_pkt(skb->data, skb->len); |
2046 | } | |
47dd7a54 | 2047 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
83d7af64 GC |
2048 | if (netif_msg_hw(priv)) |
2049 | pr_debug("%s: stop transmitted packets\n", __func__); | |
47dd7a54 GC |
2050 | netif_stop_queue(dev); |
2051 | } | |
2052 | ||
2053 | dev->stats.tx_bytes += skb->len; | |
2054 | ||
891434b1 RK |
2055 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
2056 | priv->hwts_tx_en)) { | |
2057 | /* declare that device is doing timestamping */ | |
2058 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2059 | priv->hw->desc->enable_tx_timestamp(first); | |
2060 | } | |
2061 | ||
2062 | if (!priv->hwts_tx_en) | |
2063 | skb_tx_timestamp(skb); | |
3e82ce12 | 2064 | |
38979574 | 2065 | netdev_sent_queue(dev, skb->len); |
52f64fae RC |
2066 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
2067 | ||
a9097a96 | 2068 | spin_unlock(&priv->tx_lock); |
362b37be | 2069 | return NETDEV_TX_OK; |
a9097a96 | 2070 | |
362b37be | 2071 | dma_map_err: |
758a0ab5 | 2072 | spin_unlock(&priv->tx_lock); |
362b37be GC |
2073 | dev_err(priv->device, "Tx dma map failed\n"); |
2074 | dev_kfree_skb(skb); | |
2075 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2076 | return NETDEV_TX_OK; |
2077 | } | |
2078 | ||
b9381985 VB |
2079 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2080 | { | |
2081 | struct ethhdr *ehdr; | |
2082 | u16 vlanid; | |
2083 | ||
2084 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2085 | NETIF_F_HW_VLAN_CTAG_RX && | |
2086 | !__vlan_get_tag(skb, &vlanid)) { | |
2087 | /* pop the vlan tag */ | |
2088 | ehdr = (struct ethhdr *)skb->data; | |
2089 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2090 | skb_pull(skb, VLAN_HLEN); | |
2091 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | ||
32ceabca | 2096 | /** |
732fdf0e | 2097 | * stmmac_rx_refill - refill used skb preallocated buffers |
32ceabca GC |
2098 | * @priv: driver private structure |
2099 | * Description : this is to reallocate the skb for the reception process | |
2100 | * that is based on zero-copy. | |
2101 | */ | |
47dd7a54 GC |
2102 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2103 | { | |
2104 | unsigned int rxsize = priv->dma_rx_size; | |
2105 | int bfsize = priv->dma_buf_sz; | |
47dd7a54 GC |
2106 | |
2107 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
2108 | unsigned int entry = priv->dirty_rx % rxsize; | |
c24602ef GC |
2109 | struct dma_desc *p; |
2110 | ||
2111 | if (priv->extend_desc) | |
ceb69499 | 2112 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2113 | else |
2114 | p = priv->dma_rx + entry; | |
2115 | ||
47dd7a54 GC |
2116 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2117 | struct sk_buff *skb; | |
2118 | ||
acb600de | 2119 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
47dd7a54 GC |
2120 | |
2121 | if (unlikely(skb == NULL)) | |
2122 | break; | |
2123 | ||
2124 | priv->rx_skbuff[entry] = skb; | |
2125 | priv->rx_skbuff_dma[entry] = | |
2126 | dma_map_single(priv->device, skb->data, bfsize, | |
2127 | DMA_FROM_DEVICE); | |
362b37be GC |
2128 | if (dma_mapping_error(priv->device, |
2129 | priv->rx_skbuff_dma[entry])) { | |
2130 | dev_err(priv->device, "Rx dma map failed\n"); | |
2131 | dev_kfree_skb(skb); | |
2132 | break; | |
2133 | } | |
c24602ef | 2134 | p->des2 = priv->rx_skbuff_dma[entry]; |
286a8372 | 2135 | |
29896a67 | 2136 | priv->hw->mode->refill_desc3(priv, p); |
286a8372 | 2137 | |
83d7af64 GC |
2138 | if (netif_msg_rx_status(priv)) |
2139 | pr_debug("\trefill entry #%d\n", entry); | |
47dd7a54 | 2140 | } |
eb0dc4bb | 2141 | wmb(); |
c24602ef | 2142 | priv->hw->desc->set_rx_owner(p); |
8e839891 | 2143 | wmb(); |
47dd7a54 | 2144 | } |
47dd7a54 GC |
2145 | } |
2146 | ||
32ceabca | 2147 | /** |
732fdf0e | 2148 | * stmmac_rx - manage the receive process |
32ceabca GC |
2149 | * @priv: driver private structure |
2150 | * @limit: napi bugget. | |
2151 | * Description : this the function called by the napi poll method. | |
2152 | * It gets all the frames inside the ring. | |
2153 | */ | |
47dd7a54 GC |
2154 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2155 | { | |
2156 | unsigned int rxsize = priv->dma_rx_size; | |
2157 | unsigned int entry = priv->cur_rx % rxsize; | |
2158 | unsigned int next_entry; | |
2159 | unsigned int count = 0; | |
d2afb5bd | 2160 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2161 | |
83d7af64 GC |
2162 | if (netif_msg_rx_status(priv)) { |
2163 | pr_debug("%s: descriptor ring:\n", __func__); | |
c24602ef | 2164 | if (priv->extend_desc) |
ceb69499 | 2165 | stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); |
c24602ef GC |
2166 | else |
2167 | stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); | |
47dd7a54 | 2168 | } |
c24602ef | 2169 | while (count < limit) { |
47dd7a54 | 2170 | int status; |
9401bb5c | 2171 | struct dma_desc *p; |
47dd7a54 | 2172 | |
c24602ef | 2173 | if (priv->extend_desc) |
ceb69499 | 2174 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2175 | else |
ceb69499 | 2176 | p = priv->dma_rx + entry; |
c24602ef GC |
2177 | |
2178 | if (priv->hw->desc->get_rx_owner(p)) | |
47dd7a54 GC |
2179 | break; |
2180 | ||
2181 | count++; | |
2182 | ||
2183 | next_entry = (++priv->cur_rx) % rxsize; | |
c24602ef | 2184 | if (priv->extend_desc) |
9401bb5c | 2185 | prefetch(priv->dma_erx + next_entry); |
c24602ef | 2186 | else |
9401bb5c | 2187 | prefetch(priv->dma_rx + next_entry); |
47dd7a54 GC |
2188 | |
2189 | /* read the status of the incoming frame */ | |
c24602ef GC |
2190 | status = priv->hw->desc->rx_status(&priv->dev->stats, |
2191 | &priv->xstats, p); | |
2192 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) | |
2193 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2194 | &priv->xstats, | |
2195 | priv->dma_erx + | |
2196 | entry); | |
891434b1 | 2197 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2198 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2199 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2200 | /* DESC2 & DESC3 will be overwitten by device | |
2201 | * with timestamp value, hence reinitialize | |
2202 | * them in stmmac_rx_refill() function so that | |
2203 | * device can reuse it. | |
2204 | */ | |
2205 | priv->rx_skbuff[entry] = NULL; | |
2206 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2207 | priv->rx_skbuff_dma[entry], |
2208 | priv->dma_buf_sz, | |
2209 | DMA_FROM_DEVICE); | |
891434b1 RK |
2210 | } |
2211 | } else { | |
47dd7a54 | 2212 | struct sk_buff *skb; |
3eeb2997 | 2213 | int frame_len; |
47dd7a54 | 2214 | |
ceb69499 GC |
2215 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2216 | ||
3eeb2997 | 2217 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2218 | * Type frames (LLC/LLC-SNAP) |
2219 | */ | |
3eeb2997 GC |
2220 | if (unlikely(status != llc_snap)) |
2221 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2222 | |
83d7af64 | 2223 | if (netif_msg_rx_status(priv)) { |
47dd7a54 | 2224 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", |
ceb69499 | 2225 | p, entry, p->des2); |
83d7af64 GC |
2226 | if (frame_len > ETH_FRAME_LEN) |
2227 | pr_debug("\tframe size %d, COE: %d\n", | |
2228 | frame_len, status); | |
2229 | } | |
47dd7a54 GC |
2230 | skb = priv->rx_skbuff[entry]; |
2231 | if (unlikely(!skb)) { | |
2232 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
ceb69499 | 2233 | priv->dev->name); |
47dd7a54 GC |
2234 | priv->dev->stats.rx_dropped++; |
2235 | break; | |
2236 | } | |
2237 | prefetch(skb->data - NET_IP_ALIGN); | |
2238 | priv->rx_skbuff[entry] = NULL; | |
2239 | ||
891434b1 RK |
2240 | stmmac_get_rx_hwtstamp(priv, entry, skb); |
2241 | ||
47dd7a54 GC |
2242 | skb_put(skb, frame_len); |
2243 | dma_unmap_single(priv->device, | |
2244 | priv->rx_skbuff_dma[entry], | |
2245 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
83d7af64 | 2246 | |
47dd7a54 | 2247 | if (netif_msg_pktdata(priv)) { |
83d7af64 | 2248 | pr_debug("frame received (%dbytes)", frame_len); |
47dd7a54 GC |
2249 | print_pkt(skb->data, frame_len); |
2250 | } | |
83d7af64 | 2251 | |
b9381985 VB |
2252 | stmmac_rx_vlan(priv->dev, skb); |
2253 | ||
47dd7a54 GC |
2254 | skb->protocol = eth_type_trans(skb, priv->dev); |
2255 | ||
ceb69499 | 2256 | if (unlikely(!coe)) |
bc8acf2c | 2257 | skb_checksum_none_assert(skb); |
62a2ab93 | 2258 | else |
47dd7a54 | 2259 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2260 | |
2261 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2262 | |
2263 | priv->dev->stats.rx_packets++; | |
2264 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2265 | } |
2266 | entry = next_entry; | |
47dd7a54 GC |
2267 | } |
2268 | ||
2269 | stmmac_rx_refill(priv); | |
2270 | ||
2271 | priv->xstats.rx_pkt_n += count; | |
2272 | ||
2273 | return count; | |
2274 | } | |
2275 | ||
2276 | /** | |
2277 | * stmmac_poll - stmmac poll method (NAPI) | |
2278 | * @napi : pointer to the napi structure. | |
2279 | * @budget : maximum number of packets that the current CPU can receive from | |
2280 | * all interfaces. | |
2281 | * Description : | |
9125cdd1 | 2282 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2283 | */ |
2284 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2285 | { | |
2286 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2287 | int work_done = 0; | |
2288 | ||
9125cdd1 GC |
2289 | priv->xstats.napi_poll++; |
2290 | stmmac_tx_clean(priv); | |
47dd7a54 | 2291 | |
9125cdd1 | 2292 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2293 | if (work_done < budget) { |
2294 | napi_complete(napi); | |
9125cdd1 | 2295 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2296 | } |
2297 | return work_done; | |
2298 | } | |
2299 | ||
2300 | /** | |
2301 | * stmmac_tx_timeout | |
2302 | * @dev : Pointer to net device structure | |
2303 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2304 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2305 | * netdev structure and arrange for the device to be reset to a sane state |
2306 | * in order to transmit a new packet. | |
2307 | */ | |
2308 | static void stmmac_tx_timeout(struct net_device *dev) | |
2309 | { | |
2310 | struct stmmac_priv *priv = netdev_priv(dev); | |
2311 | ||
2312 | /* Clear Tx resources and restart transmitting again */ | |
2313 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2314 | } |
2315 | ||
47dd7a54 | 2316 | /** |
01789349 | 2317 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2318 | * @dev : pointer to the device structure |
2319 | * Description: | |
2320 | * This function is a driver entry point which gets called by the kernel | |
2321 | * whenever multicast addresses must be enabled/disabled. | |
2322 | * Return value: | |
2323 | * void. | |
2324 | */ | |
01789349 | 2325 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2326 | { |
2327 | struct stmmac_priv *priv = netdev_priv(dev); | |
2328 | ||
3b57de95 | 2329 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 GC |
2330 | } |
2331 | ||
2332 | /** | |
2333 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2334 | * @dev : device pointer. | |
2335 | * @new_mtu : the new MTU size for the device. | |
2336 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2337 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2338 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2339 | * Return value: | |
2340 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2341 | * file on failure. | |
2342 | */ | |
2343 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2344 | { | |
2345 | struct stmmac_priv *priv = netdev_priv(dev); | |
2346 | int max_mtu; | |
2347 | ||
2348 | if (netif_running(dev)) { | |
2349 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
2350 | return -EBUSY; | |
2351 | } | |
2352 | ||
48febf7e | 2353 | if (priv->plat->enh_desc) |
47dd7a54 GC |
2354 | max_mtu = JUMBO_LEN; |
2355 | else | |
45db81e1 | 2356 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 | 2357 | |
2618abb7 VB |
2358 | if (priv->plat->maxmtu < max_mtu) |
2359 | max_mtu = priv->plat->maxmtu; | |
2360 | ||
47dd7a54 GC |
2361 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { |
2362 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
2363 | return -EINVAL; | |
2364 | } | |
2365 | ||
5e982f3b MM |
2366 | dev->mtu = new_mtu; |
2367 | netdev_update_features(dev); | |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
c8f44aff | 2372 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2373 | netdev_features_t features) |
5e982f3b MM |
2374 | { |
2375 | struct stmmac_priv *priv = netdev_priv(dev); | |
2376 | ||
38912bdb | 2377 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2378 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2379 | |
5e982f3b MM |
2380 | if (!priv->plat->tx_coe) |
2381 | features &= ~NETIF_F_ALL_CSUM; | |
2382 | ||
ebbb293f GC |
2383 | /* Some GMAC devices have a bugged Jumbo frame support that |
2384 | * needs to have the Tx COE disabled for oversized frames | |
2385 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2386 | * the TX csum insertionin the TDES and not use SF. |
2387 | */ | |
5e982f3b MM |
2388 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
2389 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 2390 | |
5e982f3b | 2391 | return features; |
47dd7a54 GC |
2392 | } |
2393 | ||
d2afb5bd GC |
2394 | static int stmmac_set_features(struct net_device *netdev, |
2395 | netdev_features_t features) | |
2396 | { | |
2397 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2398 | ||
2399 | /* Keep the COE Type in case of csum is supporting */ | |
2400 | if (features & NETIF_F_RXCSUM) | |
2401 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2402 | else | |
2403 | priv->hw->rx_csum = 0; | |
2404 | /* No check needed because rx_coe has been set before and it will be | |
2405 | * fixed in case of issue. | |
2406 | */ | |
2407 | priv->hw->mac->rx_ipc(priv->hw); | |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
32ceabca GC |
2412 | /** |
2413 | * stmmac_interrupt - main ISR | |
2414 | * @irq: interrupt number. | |
2415 | * @dev_id: to pass the net device pointer. | |
2416 | * Description: this is the main driver interrupt service routine. | |
732fdf0e GC |
2417 | * It can call: |
2418 | * o DMA service routine (to manage incoming frame reception and transmission | |
2419 | * status) | |
2420 | * o Core interrupts to manage: remote wake-up, management counter, LPI | |
2421 | * interrupts. | |
32ceabca | 2422 | */ |
47dd7a54 GC |
2423 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2424 | { | |
2425 | struct net_device *dev = (struct net_device *)dev_id; | |
2426 | struct stmmac_priv *priv = netdev_priv(dev); | |
2427 | ||
89f7f2cf SK |
2428 | if (priv->irq_wake) |
2429 | pm_wakeup_event(priv->device, 0); | |
2430 | ||
47dd7a54 GC |
2431 | if (unlikely(!dev)) { |
2432 | pr_err("%s: invalid dev pointer\n", __func__); | |
2433 | return IRQ_NONE; | |
2434 | } | |
2435 | ||
d765955d GC |
2436 | /* To handle GMAC own interrupts */ |
2437 | if (priv->plat->has_gmac) { | |
7ed24bbe | 2438 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2439 | &priv->xstats); |
d765955d | 2440 | if (unlikely(status)) { |
d765955d | 2441 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2442 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2443 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2444 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2445 | priv->tx_path_in_lpi_mode = false; |
d765955d GC |
2446 | } |
2447 | } | |
aec7ff27 | 2448 | |
d765955d | 2449 | /* To handle DMA interrupts */ |
aec7ff27 | 2450 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2451 | |
2452 | return IRQ_HANDLED; | |
2453 | } | |
2454 | ||
2455 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2456 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2457 | * to allow network I/O with interrupts disabled. |
2458 | */ | |
47dd7a54 GC |
2459 | static void stmmac_poll_controller(struct net_device *dev) |
2460 | { | |
2461 | disable_irq(dev->irq); | |
2462 | stmmac_interrupt(dev->irq, dev); | |
2463 | enable_irq(dev->irq); | |
2464 | } | |
2465 | #endif | |
2466 | ||
2467 | /** | |
2468 | * stmmac_ioctl - Entry point for the Ioctl | |
2469 | * @dev: Device pointer. | |
2470 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2471 | * a proprietary structure used to pass information to the driver. | |
2472 | * @cmd: IOCTL command | |
2473 | * Description: | |
32ceabca | 2474 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2475 | */ |
2476 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2477 | { | |
2478 | struct stmmac_priv *priv = netdev_priv(dev); | |
891434b1 | 2479 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2480 | |
2481 | if (!netif_running(dev)) | |
2482 | return -EINVAL; | |
2483 | ||
891434b1 RK |
2484 | switch (cmd) { |
2485 | case SIOCGMIIPHY: | |
2486 | case SIOCGMIIREG: | |
2487 | case SIOCSMIIREG: | |
2488 | if (!priv->phydev) | |
2489 | return -EINVAL; | |
2490 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
2491 | break; | |
2492 | case SIOCSHWTSTAMP: | |
2493 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2494 | break; | |
2495 | default: | |
2496 | break; | |
2497 | } | |
28b04113 | 2498 | |
47dd7a54 GC |
2499 | return ret; |
2500 | } | |
2501 | ||
50fb4f74 | 2502 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
2503 | static struct dentry *stmmac_fs_dir; |
2504 | static struct dentry *stmmac_rings_status; | |
e7434821 | 2505 | static struct dentry *stmmac_dma_cap; |
7ac29055 | 2506 | |
c24602ef | 2507 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2508 | struct seq_file *seq) |
7ac29055 | 2509 | { |
7ac29055 | 2510 | int i; |
ceb69499 GC |
2511 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2512 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2513 | |
c24602ef GC |
2514 | for (i = 0; i < size; i++) { |
2515 | u64 x; | |
2516 | if (extend_desc) { | |
2517 | x = *(u64 *) ep; | |
2518 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2519 | i, (unsigned int)virt_to_phys(ep), |
2520 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2521 | ep->basic.des2, ep->basic.des3); |
2522 | ep++; | |
2523 | } else { | |
2524 | x = *(u64 *) p; | |
2525 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 GC |
2526 | i, (unsigned int)virt_to_phys(ep), |
2527 | (unsigned int)x, (unsigned int)(x >> 32), | |
c24602ef GC |
2528 | p->des2, p->des3); |
2529 | p++; | |
2530 | } | |
7ac29055 GC |
2531 | seq_printf(seq, "\n"); |
2532 | } | |
c24602ef | 2533 | } |
7ac29055 | 2534 | |
c24602ef GC |
2535 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2536 | { | |
2537 | struct net_device *dev = seq->private; | |
2538 | struct stmmac_priv *priv = netdev_priv(dev); | |
2539 | unsigned int txsize = priv->dma_tx_size; | |
2540 | unsigned int rxsize = priv->dma_rx_size; | |
7ac29055 | 2541 | |
c24602ef GC |
2542 | if (priv->extend_desc) { |
2543 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
ceb69499 | 2544 | sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); |
c24602ef | 2545 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
ceb69499 | 2546 | sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); |
c24602ef GC |
2547 | } else { |
2548 | seq_printf(seq, "RX descriptor ring:\n"); | |
2549 | sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); | |
2550 | seq_printf(seq, "TX descriptor ring:\n"); | |
2551 | sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); | |
7ac29055 GC |
2552 | } |
2553 | ||
2554 | return 0; | |
2555 | } | |
2556 | ||
2557 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2558 | { | |
2559 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2560 | } | |
2561 | ||
2562 | static const struct file_operations stmmac_rings_status_fops = { | |
2563 | .owner = THIS_MODULE, | |
2564 | .open = stmmac_sysfs_ring_open, | |
2565 | .read = seq_read, | |
2566 | .llseek = seq_lseek, | |
74863948 | 2567 | .release = single_release, |
7ac29055 GC |
2568 | }; |
2569 | ||
e7434821 GC |
2570 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2571 | { | |
2572 | struct net_device *dev = seq->private; | |
2573 | struct stmmac_priv *priv = netdev_priv(dev); | |
2574 | ||
19e30c14 | 2575 | if (!priv->hw_cap_support) { |
e7434821 GC |
2576 | seq_printf(seq, "DMA HW features not supported\n"); |
2577 | return 0; | |
2578 | } | |
2579 | ||
2580 | seq_printf(seq, "==============================\n"); | |
2581 | seq_printf(seq, "\tDMA HW features\n"); | |
2582 | seq_printf(seq, "==============================\n"); | |
2583 | ||
2584 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
2585 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
2586 | seq_printf(seq, "\t1000 Mbps %s\n", | |
2587 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
2588 | seq_printf(seq, "\tHalf duple %s\n", | |
2589 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
2590 | seq_printf(seq, "\tHash Filter: %s\n", | |
2591 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
2592 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
2593 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
2594 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
2595 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
2596 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
2597 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
2598 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
2599 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
2600 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
2601 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
2602 | seq_printf(seq, "\tRMON module: %s\n", | |
2603 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
2604 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
2605 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
2606 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
2607 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
2608 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
2609 | (priv->dma_cap.eee) ? "Y" : "N"); | |
2610 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
2611 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
2612 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
2613 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
2614 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
2615 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
2616 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
2617 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
2618 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
2619 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
2620 | priv->dma_cap.number_rx_channel); | |
2621 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
2622 | priv->dma_cap.number_tx_channel); | |
2623 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
2624 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
2625 | ||
2626 | return 0; | |
2627 | } | |
2628 | ||
2629 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
2630 | { | |
2631 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
2632 | } | |
2633 | ||
2634 | static const struct file_operations stmmac_dma_cap_fops = { | |
2635 | .owner = THIS_MODULE, | |
2636 | .open = stmmac_sysfs_dma_cap_open, | |
2637 | .read = seq_read, | |
2638 | .llseek = seq_lseek, | |
74863948 | 2639 | .release = single_release, |
e7434821 GC |
2640 | }; |
2641 | ||
7ac29055 GC |
2642 | static int stmmac_init_fs(struct net_device *dev) |
2643 | { | |
2644 | /* Create debugfs entries */ | |
2645 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
2646 | ||
2647 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
2648 | pr_err("ERROR %s, debugfs create directory failed\n", | |
2649 | STMMAC_RESOURCE_NAME); | |
2650 | ||
2651 | return -ENOMEM; | |
2652 | } | |
2653 | ||
2654 | /* Entry to report DMA RX/TX rings */ | |
2655 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
ceb69499 GC |
2656 | S_IRUGO, stmmac_fs_dir, dev, |
2657 | &stmmac_rings_status_fops); | |
7ac29055 GC |
2658 | |
2659 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
2660 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
2661 | debugfs_remove(stmmac_fs_dir); | |
2662 | ||
2663 | return -ENOMEM; | |
2664 | } | |
2665 | ||
e7434821 GC |
2666 | /* Entry to report the DMA HW features */ |
2667 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
2668 | dev, &stmmac_dma_cap_fops); | |
2669 | ||
2670 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
2671 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
2672 | debugfs_remove(stmmac_rings_status); | |
2673 | debugfs_remove(stmmac_fs_dir); | |
2674 | ||
2675 | return -ENOMEM; | |
2676 | } | |
2677 | ||
7ac29055 GC |
2678 | return 0; |
2679 | } | |
2680 | ||
2681 | static void stmmac_exit_fs(void) | |
2682 | { | |
2683 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 2684 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
2685 | debugfs_remove(stmmac_fs_dir); |
2686 | } | |
50fb4f74 | 2687 | #endif /* CONFIG_DEBUG_FS */ |
7ac29055 | 2688 | |
47dd7a54 GC |
2689 | static const struct net_device_ops stmmac_netdev_ops = { |
2690 | .ndo_open = stmmac_open, | |
2691 | .ndo_start_xmit = stmmac_xmit, | |
2692 | .ndo_stop = stmmac_release, | |
2693 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 2694 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 2695 | .ndo_set_features = stmmac_set_features, |
01789349 | 2696 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
2697 | .ndo_tx_timeout = stmmac_tx_timeout, |
2698 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
2699 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2700 | .ndo_poll_controller = stmmac_poll_controller, | |
2701 | #endif | |
2702 | .ndo_set_mac_address = eth_mac_addr, | |
2703 | }; | |
2704 | ||
cf3f047b GC |
2705 | /** |
2706 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 2707 | * @priv: driver private structure |
732fdf0e GC |
2708 | * Description: this function is to configure the MAC device according to |
2709 | * some platform parameters or the HW capability register. It prepares the | |
2710 | * driver to use either ring or chain modes and to setup either enhanced or | |
2711 | * normal descriptors. | |
cf3f047b GC |
2712 | */ |
2713 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
2714 | { | |
cf3f047b GC |
2715 | struct mac_device_info *mac; |
2716 | ||
2717 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
2718 | if (priv->plat->has_gmac) { |
2719 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
2720 | mac = dwmac1000_setup(priv->ioaddr, |
2721 | priv->plat->multicast_filter_bins, | |
2722 | priv->plat->unicast_filter_entries); | |
03f2eecd | 2723 | } else { |
cf3f047b | 2724 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 2725 | } |
cf3f047b GC |
2726 | if (!mac) |
2727 | return -ENOMEM; | |
2728 | ||
2729 | priv->hw = mac; | |
2730 | ||
cf3f047b | 2731 | /* Get and dump the chip ID */ |
cffb13f4 | 2732 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b | 2733 | |
4a7d666a | 2734 | /* To use the chained or ring mode */ |
ceb69499 | 2735 | if (chain_mode) { |
29896a67 | 2736 | priv->hw->mode = &chain_mode_ops; |
4a7d666a GC |
2737 | pr_info(" Chain mode enabled\n"); |
2738 | priv->mode = STMMAC_CHAIN_MODE; | |
2739 | } else { | |
29896a67 | 2740 | priv->hw->mode = &ring_mode_ops; |
4a7d666a GC |
2741 | pr_info(" Ring mode enabled\n"); |
2742 | priv->mode = STMMAC_RING_MODE; | |
2743 | } | |
2744 | ||
cf3f047b GC |
2745 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
2746 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
2747 | if (priv->hw_cap_support) { | |
2748 | pr_info(" DMA HW capability register supported"); | |
2749 | ||
2750 | /* We can override some gmac/dma configuration fields: e.g. | |
2751 | * enh_desc, tx_coe (e.g. that are passed through the | |
2752 | * platform) with the values from the HW capability | |
2753 | * register (if supported). | |
2754 | */ | |
2755 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 2756 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb DS |
2757 | |
2758 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
2759 | ||
2760 | if (priv->dma_cap.rx_coe_type2) | |
2761 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
2762 | else if (priv->dma_cap.rx_coe_type1) | |
2763 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
2764 | ||
cf3f047b GC |
2765 | } else |
2766 | pr_info(" No HW DMA feature register supported"); | |
2767 | ||
61369d02 BA |
2768 | /* To use alternate (extended) or normal descriptor structures */ |
2769 | stmmac_selec_desc_mode(priv); | |
2770 | ||
d2afb5bd GC |
2771 | if (priv->plat->rx_coe) { |
2772 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38912bdb DS |
2773 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", |
2774 | priv->plat->rx_coe); | |
d2afb5bd | 2775 | } |
cf3f047b GC |
2776 | if (priv->plat->tx_coe) |
2777 | pr_info(" TX Checksum insertion supported\n"); | |
2778 | ||
2779 | if (priv->plat->pmt) { | |
2780 | pr_info(" Wake-Up On Lan supported\n"); | |
2781 | device_set_wakeup_capable(priv->device, 1); | |
2782 | } | |
2783 | ||
c24602ef | 2784 | return 0; |
cf3f047b GC |
2785 | } |
2786 | ||
47dd7a54 | 2787 | /** |
bfab27a1 GC |
2788 | * stmmac_dvr_probe |
2789 | * @device: device pointer | |
ff3dd78c GC |
2790 | * @plat_dat: platform data pointer |
2791 | * @addr: iobase memory address | |
bfab27a1 GC |
2792 | * Description: this is the main probe function used to |
2793 | * call the alloc_etherdev, allocate the priv structure. | |
47dd7a54 | 2794 | */ |
bfab27a1 | 2795 | struct stmmac_priv *stmmac_dvr_probe(struct device *device, |
cf3f047b GC |
2796 | struct plat_stmmacenet_data *plat_dat, |
2797 | void __iomem *addr) | |
47dd7a54 GC |
2798 | { |
2799 | int ret = 0; | |
bfab27a1 GC |
2800 | struct net_device *ndev = NULL; |
2801 | struct stmmac_priv *priv; | |
47dd7a54 | 2802 | |
bfab27a1 | 2803 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 2804 | if (!ndev) |
bfab27a1 | 2805 | return NULL; |
bfab27a1 GC |
2806 | |
2807 | SET_NETDEV_DEV(ndev, device); | |
2808 | ||
2809 | priv = netdev_priv(ndev); | |
2810 | priv->device = device; | |
2811 | priv->dev = ndev; | |
47dd7a54 | 2812 | |
bfab27a1 | 2813 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
2814 | priv->pause = pause; |
2815 | priv->plat = plat_dat; | |
2816 | priv->ioaddr = addr; | |
2817 | priv->dev->base_addr = (unsigned long)addr; | |
2818 | ||
2819 | /* Verify driver arguments */ | |
2820 | stmmac_verify_args(); | |
bfab27a1 | 2821 | |
cf3f047b | 2822 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
2823 | * this needs to have multiple instances |
2824 | */ | |
cf3f047b GC |
2825 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
2826 | priv->plat->phy_addr = phyaddr; | |
2827 | ||
62866e98 CYT |
2828 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
2829 | if (IS_ERR(priv->stmmac_clk)) { | |
2830 | dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", | |
2831 | __func__); | |
c5bb86c3 KHL |
2832 | /* If failed to obtain stmmac_clk and specific clk_csr value |
2833 | * is NOT passed from the platform, probe fail. | |
2834 | */ | |
2835 | if (!priv->plat->clk_csr) { | |
2836 | ret = PTR_ERR(priv->stmmac_clk); | |
2837 | goto error_clk_get; | |
2838 | } else { | |
2839 | priv->stmmac_clk = NULL; | |
2840 | } | |
62866e98 CYT |
2841 | } |
2842 | clk_prepare_enable(priv->stmmac_clk); | |
2843 | ||
c5e4ddbd CYT |
2844 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
2845 | STMMAC_RESOURCE_NAME); | |
2846 | if (IS_ERR(priv->stmmac_rst)) { | |
2847 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
2848 | ret = -EPROBE_DEFER; | |
2849 | goto error_hw_init; | |
2850 | } | |
2851 | dev_info(priv->device, "no reset control found\n"); | |
2852 | priv->stmmac_rst = NULL; | |
2853 | } | |
2854 | if (priv->stmmac_rst) | |
2855 | reset_control_deassert(priv->stmmac_rst); | |
2856 | ||
cf3f047b | 2857 | /* Init MAC and get the capabilities */ |
c24602ef GC |
2858 | ret = stmmac_hw_init(priv); |
2859 | if (ret) | |
62866e98 | 2860 | goto error_hw_init; |
cf3f047b GC |
2861 | |
2862 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 2863 | |
cf3f047b GC |
2864 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
2865 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
2866 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
2867 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
2868 | #ifdef STMMAC_VLAN_TAG_USED |
2869 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 2870 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
2871 | #endif |
2872 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
2873 | ||
47dd7a54 GC |
2874 | if (flow_ctrl) |
2875 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
2876 | ||
62a2ab93 GC |
2877 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
2878 | * In some case, for example on bugged HW this feature | |
2879 | * has to be disable and this can be done by passing the | |
2880 | * riwt_off field from the platform. | |
2881 | */ | |
2882 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
2883 | priv->use_riwt = 1; | |
2884 | pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); | |
2885 | } | |
2886 | ||
bfab27a1 | 2887 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 2888 | |
f8e96161 | 2889 | spin_lock_init(&priv->lock); |
a9097a96 | 2890 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 2891 | |
bfab27a1 | 2892 | ret = register_netdev(ndev); |
47dd7a54 | 2893 | if (ret) { |
cf3f047b | 2894 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
6a81c26f | 2895 | goto error_netdev_register; |
47dd7a54 GC |
2896 | } |
2897 | ||
cd7201f4 GC |
2898 | /* If a specific clk_csr value is passed from the platform |
2899 | * this means that the CSR Clock Range selection cannot be | |
2900 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
2901 | * set the MDC clock dynamically according to the csr actual | |
2902 | * clock input. | |
2903 | */ | |
2904 | if (!priv->plat->clk_csr) | |
2905 | stmmac_clk_csr_set(priv); | |
2906 | else | |
2907 | priv->clk_csr = priv->plat->clk_csr; | |
2908 | ||
e58bb43f GC |
2909 | stmmac_check_pcs_mode(priv); |
2910 | ||
4d8f0825 BA |
2911 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2912 | priv->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
2913 | /* MDIO bus Registration */ |
2914 | ret = stmmac_mdio_register(ndev); | |
2915 | if (ret < 0) { | |
2916 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
2917 | __func__, priv->plat->bus_id); | |
2918 | goto error_mdio_register; | |
2919 | } | |
4bfcbd7a FV |
2920 | } |
2921 | ||
bfab27a1 | 2922 | return priv; |
47dd7a54 | 2923 | |
6a81c26f | 2924 | error_mdio_register: |
34a52f36 | 2925 | unregister_netdev(ndev); |
6a81c26f VK |
2926 | error_netdev_register: |
2927 | netif_napi_del(&priv->napi); | |
62866e98 CYT |
2928 | error_hw_init: |
2929 | clk_disable_unprepare(priv->stmmac_clk); | |
2930 | error_clk_get: | |
34a52f36 | 2931 | free_netdev(ndev); |
47dd7a54 | 2932 | |
c5e4ddbd | 2933 | return ERR_PTR(ret); |
47dd7a54 | 2934 | } |
b2e2f0c7 | 2935 | EXPORT_SYMBOL_GPL(stmmac_dvr_probe); |
47dd7a54 GC |
2936 | |
2937 | /** | |
2938 | * stmmac_dvr_remove | |
bfab27a1 | 2939 | * @ndev: net device pointer |
47dd7a54 | 2940 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 2941 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 2942 | */ |
bfab27a1 | 2943 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 2944 | { |
aec7ff27 | 2945 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
2946 | |
2947 | pr_info("%s:\n\tremoving driver", __func__); | |
2948 | ||
ad01b7d4 GC |
2949 | priv->hw->dma->stop_rx(priv->ioaddr); |
2950 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 2951 | |
bfab27a1 | 2952 | stmmac_set_mac(priv->ioaddr, false); |
4d8f0825 BA |
2953 | if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && |
2954 | priv->pcs != STMMAC_PCS_RTBI) | |
e58bb43f | 2955 | stmmac_mdio_unregister(ndev); |
47dd7a54 | 2956 | netif_carrier_off(ndev); |
47dd7a54 | 2957 | unregister_netdev(ndev); |
c5e4ddbd CYT |
2958 | if (priv->stmmac_rst) |
2959 | reset_control_assert(priv->stmmac_rst); | |
62866e98 | 2960 | clk_disable_unprepare(priv->stmmac_clk); |
47dd7a54 GC |
2961 | free_netdev(ndev); |
2962 | ||
2963 | return 0; | |
2964 | } | |
b2e2f0c7 | 2965 | EXPORT_SYMBOL_GPL(stmmac_dvr_remove); |
47dd7a54 | 2966 | |
732fdf0e GC |
2967 | /** |
2968 | * stmmac_suspend - suspend callback | |
2969 | * @ndev: net device pointer | |
2970 | * Description: this is the function to suspend the device and it is called | |
2971 | * by the platform driver to stop the network queue, release the resources, | |
2972 | * program the PMT register (for WoL), clean and release driver resources. | |
2973 | */ | |
bfab27a1 | 2974 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 2975 | { |
874bd42d | 2976 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 2977 | unsigned long flags; |
47dd7a54 | 2978 | |
874bd42d | 2979 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
2980 | return 0; |
2981 | ||
102463b1 FV |
2982 | if (priv->phydev) |
2983 | phy_stop(priv->phydev); | |
2984 | ||
f8c5a875 | 2985 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 2986 | |
874bd42d GC |
2987 | netif_device_detach(ndev); |
2988 | netif_stop_queue(ndev); | |
47dd7a54 | 2989 | |
874bd42d GC |
2990 | napi_disable(&priv->napi); |
2991 | ||
2992 | /* Stop TX/RX DMA */ | |
2993 | priv->hw->dma->stop_tx(priv->ioaddr); | |
2994 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef GC |
2995 | |
2996 | stmmac_clear_descriptors(priv); | |
874bd42d GC |
2997 | |
2998 | /* Enable Power down mode by programming the PMT regs */ | |
89f7f2cf | 2999 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3000 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
3001 | priv->irq_wake = 1; |
3002 | } else { | |
bfab27a1 | 3003 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 3004 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 3005 | /* Disable clock in case of PWM is off */ |
777da230 | 3006 | clk_disable(priv->stmmac_clk); |
ba1377ff | 3007 | } |
f8c5a875 | 3008 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
3009 | |
3010 | priv->oldlink = 0; | |
3011 | priv->speed = 0; | |
3012 | priv->oldduplex = -1; | |
47dd7a54 GC |
3013 | return 0; |
3014 | } | |
b2e2f0c7 | 3015 | EXPORT_SYMBOL_GPL(stmmac_suspend); |
47dd7a54 | 3016 | |
732fdf0e GC |
3017 | /** |
3018 | * stmmac_resume - resume callback | |
3019 | * @ndev: net device pointer | |
3020 | * Description: when resume this function is invoked to setup the DMA and CORE | |
3021 | * in a usable state. | |
3022 | */ | |
bfab27a1 | 3023 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 3024 | { |
874bd42d | 3025 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3026 | unsigned long flags; |
47dd7a54 | 3027 | |
874bd42d | 3028 | if (!netif_running(ndev)) |
47dd7a54 GC |
3029 | return 0; |
3030 | ||
f8c5a875 | 3031 | spin_lock_irqsave(&priv->lock, flags); |
c4433be6 | 3032 | |
47dd7a54 GC |
3033 | /* Power Down bit, into the PM register, is cleared |
3034 | * automatically as soon as a magic packet or a Wake-up frame | |
3035 | * is received. Anyway, it's better to manually clear | |
3036 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
3037 | * from another devices (e.g. serial console). |
3038 | */ | |
623997fb | 3039 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3040 | priv->hw->mac->pmt(priv->hw, 0); |
89f7f2cf | 3041 | priv->irq_wake = 0; |
623997fb | 3042 | } else { |
db88f10a | 3043 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 3044 | /* enable the clk prevously disabled */ |
777da230 | 3045 | clk_enable(priv->stmmac_clk); |
623997fb SK |
3046 | /* reset the phy so that it's ready */ |
3047 | if (priv->mii) | |
3048 | stmmac_mdio_reset(priv->mii); | |
3049 | } | |
47dd7a54 | 3050 | |
874bd42d | 3051 | netif_device_attach(ndev); |
47dd7a54 | 3052 | |
777da230 | 3053 | init_dma_desc_rings(ndev, GFP_ATOMIC); |
fe131929 | 3054 | stmmac_hw_setup(ndev, false); |
777da230 | 3055 | stmmac_init_tx_coalesce(priv); |
47dd7a54 | 3056 | |
47dd7a54 GC |
3057 | napi_enable(&priv->napi); |
3058 | ||
874bd42d | 3059 | netif_start_queue(ndev); |
47dd7a54 | 3060 | |
f8c5a875 | 3061 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 FV |
3062 | |
3063 | if (priv->phydev) | |
3064 | phy_start(priv->phydev); | |
3065 | ||
47dd7a54 GC |
3066 | return 0; |
3067 | } | |
b2e2f0c7 | 3068 | EXPORT_SYMBOL_GPL(stmmac_resume); |
ba27ec66 | 3069 | |
47dd7a54 GC |
3070 | #ifndef MODULE |
3071 | static int __init stmmac_cmdline_opt(char *str) | |
3072 | { | |
3073 | char *opt; | |
3074 | ||
3075 | if (!str || !*str) | |
3076 | return -EINVAL; | |
3077 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3078 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3079 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3080 | goto err; |
3081 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3082 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 GC |
3083 | goto err; |
3084 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
ea2ab871 | 3085 | if (kstrtoint(opt + 11, 0, &dma_txsize)) |
f3240e28 GC |
3086 | goto err; |
3087 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
ea2ab871 | 3088 | if (kstrtoint(opt + 11, 0, &dma_rxsize)) |
f3240e28 GC |
3089 | goto err; |
3090 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
ea2ab871 | 3091 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3092 | goto err; |
3093 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3094 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3095 | goto err; |
3096 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3097 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3098 | goto err; |
3099 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3100 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3101 | goto err; |
3102 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3103 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3104 | goto err; |
506f669c | 3105 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3106 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3107 | goto err; | |
4a7d666a GC |
3108 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3109 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3110 | goto err; | |
f3240e28 | 3111 | } |
47dd7a54 GC |
3112 | } |
3113 | return 0; | |
f3240e28 GC |
3114 | |
3115 | err: | |
3116 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3117 | return -EINVAL; | |
47dd7a54 GC |
3118 | } |
3119 | ||
3120 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3121 | #endif /* MODULE */ |
6fc0d0f2 GC |
3122 | |
3123 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); | |
3124 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3125 | MODULE_LICENSE("GPL"); |