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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
47dd7a54 GC |
31 | #include <linux/kernel.h> |
32 | #include <linux/interrupt.h> | |
47dd7a54 GC |
33 | #include <linux/ip.h> |
34 | #include <linux/tcp.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/ethtool.h> | |
37 | #include <linux/if_ether.h> | |
38 | #include <linux/crc32.h> | |
39 | #include <linux/mii.h> | |
01789349 | 40 | #include <linux/if.h> |
47dd7a54 GC |
41 | #include <linux/if_vlan.h> |
42 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
70c71606 | 44 | #include <linux/prefetch.h> |
7ac29055 GC |
45 | #ifdef CONFIG_STMMAC_DEBUG_FS |
46 | #include <linux/debugfs.h> | |
47 | #include <linux/seq_file.h> | |
48 | #endif | |
286a8372 | 49 | #include "stmmac.h" |
47dd7a54 | 50 | |
47dd7a54 GC |
51 | #undef STMMAC_DEBUG |
52 | /*#define STMMAC_DEBUG*/ | |
53 | #ifdef STMMAC_DEBUG | |
54 | #define DBG(nlevel, klevel, fmt, args...) \ | |
55 | ((void)(netif_msg_##nlevel(priv) && \ | |
56 | printk(KERN_##klevel fmt, ## args))) | |
57 | #else | |
58 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
59 | #endif | |
60 | ||
61 | #undef STMMAC_RX_DEBUG | |
62 | /*#define STMMAC_RX_DEBUG*/ | |
63 | #ifdef STMMAC_RX_DEBUG | |
64 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
65 | #else | |
66 | #define RX_DBG(fmt, args...) do { } while (0) | |
67 | #endif | |
68 | ||
69 | #undef STMMAC_XMIT_DEBUG | |
70 | /*#define STMMAC_XMIT_DEBUG*/ | |
71 | #ifdef STMMAC_TX_DEBUG | |
72 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
73 | #else | |
74 | #define TX_DBG(fmt, args...) do { } while (0) | |
75 | #endif | |
76 | ||
77 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
78 | #define JUMBO_LEN 9000 | |
79 | ||
80 | /* Module parameters */ | |
81 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
82 | static int watchdog = TX_TIMEO; | |
83 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
85 | ||
86 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
87 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
88 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
89 | ||
bfab27a1 | 90 | int phyaddr = -1; |
47dd7a54 GC |
91 | module_param(phyaddr, int, S_IRUGO); |
92 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
93 | ||
94 | #define DMA_TX_SIZE 256 | |
95 | static int dma_txsize = DMA_TX_SIZE; | |
96 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
97 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
98 | ||
99 | #define DMA_RX_SIZE 256 | |
100 | static int dma_rxsize = DMA_RX_SIZE; | |
101 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
102 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
103 | ||
104 | static int flow_ctrl = FLOW_OFF; | |
105 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
106 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
107 | ||
108 | static int pause = PAUSE_TIME; | |
109 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
110 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
111 | ||
112 | #define TC_DEFAULT 64 | |
113 | static int tc = TC_DEFAULT; | |
114 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
115 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
116 | ||
47dd7a54 GC |
117 | /* Pay attention to tune this parameter; take care of both |
118 | * hardware capability and network stabitily/performance impact. | |
119 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
120 | #ifdef CONFIG_STMMAC_TIMER | |
121 | #define DEFAULT_PERIODIC_RATE 256 | |
122 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
123 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
124 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
125 | #endif | |
126 | ||
127 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
128 | static int buf_sz = DMA_BUFFER_SIZE; | |
129 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
130 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
131 | ||
47dd7a54 GC |
132 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
133 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
134 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
135 | ||
136 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 | 137 | |
bfab27a1 GC |
138 | #ifdef CONFIG_STMMAC_DEBUG_FS |
139 | static int stmmac_init_fs(struct net_device *dev); | |
140 | static void stmmac_exit_fs(void); | |
141 | #endif | |
142 | ||
47dd7a54 GC |
143 | /** |
144 | * stmmac_verify_args - verify the driver parameters. | |
145 | * Description: it verifies if some wrong parameter is passed to the driver. | |
146 | * Note that wrong parameters are replaced with the default values. | |
147 | */ | |
148 | static void stmmac_verify_args(void) | |
149 | { | |
150 | if (unlikely(watchdog < 0)) | |
151 | watchdog = TX_TIMEO; | |
152 | if (unlikely(dma_rxsize < 0)) | |
153 | dma_rxsize = DMA_RX_SIZE; | |
154 | if (unlikely(dma_txsize < 0)) | |
155 | dma_txsize = DMA_TX_SIZE; | |
156 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
157 | buf_sz = DMA_BUFFER_SIZE; | |
158 | if (unlikely(flow_ctrl > 1)) | |
159 | flow_ctrl = FLOW_AUTO; | |
160 | else if (likely(flow_ctrl < 0)) | |
161 | flow_ctrl = FLOW_OFF; | |
162 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
163 | pause = PAUSE_TIME; | |
47dd7a54 GC |
164 | } |
165 | ||
cd7201f4 GC |
166 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
167 | { | |
168 | #ifdef CONFIG_HAVE_CLK | |
169 | u32 clk_rate; | |
170 | ||
31ea38ee GC |
171 | if (IS_ERR(priv->stmmac_clk)) |
172 | return; | |
173 | ||
cd7201f4 GC |
174 | clk_rate = clk_get_rate(priv->stmmac_clk); |
175 | ||
176 | /* Platform provided default clk_csr would be assumed valid | |
177 | * for all other cases except for the below mentioned ones. */ | |
178 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { | |
179 | if (clk_rate < CSR_F_35M) | |
180 | priv->clk_csr = STMMAC_CSR_20_35M; | |
181 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
182 | priv->clk_csr = STMMAC_CSR_35_60M; | |
183 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
184 | priv->clk_csr = STMMAC_CSR_60_100M; | |
185 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
186 | priv->clk_csr = STMMAC_CSR_100_150M; | |
187 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
188 | priv->clk_csr = STMMAC_CSR_150_250M; | |
189 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) | |
190 | priv->clk_csr = STMMAC_CSR_250_300M; | |
191 | } /* For values higher than the IEEE 802.3 specified frequency | |
192 | * we can not estimate the proper divider as it is not known | |
193 | * the frequency of clk_csr_i. So we do not change the default | |
194 | * divider. */ | |
195 | #endif | |
196 | } | |
197 | ||
47dd7a54 GC |
198 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) |
199 | static void print_pkt(unsigned char *buf, int len) | |
200 | { | |
201 | int j; | |
202 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
203 | for (j = 0; j < len; j++) { | |
204 | if ((j % 16) == 0) | |
205 | pr_info("\n %03x:", j); | |
206 | pr_info(" %02x", buf[j]); | |
207 | } | |
208 | pr_info("\n"); | |
47dd7a54 GC |
209 | } |
210 | #endif | |
211 | ||
212 | /* minimum number of free TX descriptors required to wake up TX process */ | |
213 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
214 | ||
215 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
216 | { | |
217 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
218 | } | |
219 | ||
9dfeb4d9 GC |
220 | /* On some ST platforms, some HW system configuraton registers have to be |
221 | * set according to the link speed negotiated. | |
222 | */ | |
223 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
224 | { | |
225 | struct phy_device *phydev = priv->phydev; | |
226 | ||
227 | if (likely(priv->plat->fix_mac_speed)) | |
228 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
229 | phydev->speed); | |
230 | } | |
231 | ||
47dd7a54 GC |
232 | /** |
233 | * stmmac_adjust_link | |
234 | * @dev: net device structure | |
235 | * Description: it adjusts the link parameters. | |
236 | */ | |
237 | static void stmmac_adjust_link(struct net_device *dev) | |
238 | { | |
239 | struct stmmac_priv *priv = netdev_priv(dev); | |
240 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
241 | unsigned long flags; |
242 | int new_state = 0; | |
243 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
244 | ||
245 | if (phydev == NULL) | |
246 | return; | |
247 | ||
248 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
249 | phydev->addr, phydev->link); | |
250 | ||
251 | spin_lock_irqsave(&priv->lock, flags); | |
252 | if (phydev->link) { | |
ad01b7d4 | 253 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
254 | |
255 | /* Now we make sure that we can be in full duplex mode. | |
256 | * If not, we operate in half-duplex mode. */ | |
257 | if (phydev->duplex != priv->oldduplex) { | |
258 | new_state = 1; | |
259 | if (!(phydev->duplex)) | |
db98a0b0 | 260 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 261 | else |
db98a0b0 | 262 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
263 | priv->oldduplex = phydev->duplex; |
264 | } | |
265 | /* Flow Control operation */ | |
266 | if (phydev->pause) | |
ad01b7d4 | 267 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 268 | fc, pause_time); |
47dd7a54 GC |
269 | |
270 | if (phydev->speed != priv->speed) { | |
271 | new_state = 1; | |
272 | switch (phydev->speed) { | |
273 | case 1000: | |
9dfeb4d9 | 274 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 275 | ctrl &= ~priv->hw->link.port; |
cf3f047b | 276 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
277 | break; |
278 | case 100: | |
279 | case 10: | |
9dfeb4d9 | 280 | if (priv->plat->has_gmac) { |
db98a0b0 | 281 | ctrl |= priv->hw->link.port; |
47dd7a54 | 282 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 283 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 284 | } else { |
db98a0b0 | 285 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
286 | } |
287 | } else { | |
db98a0b0 | 288 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 289 | } |
9dfeb4d9 | 290 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
291 | break; |
292 | default: | |
293 | if (netif_msg_link(priv)) | |
294 | pr_warning("%s: Speed (%d) is not 10" | |
295 | " or 100!\n", dev->name, phydev->speed); | |
296 | break; | |
297 | } | |
298 | ||
299 | priv->speed = phydev->speed; | |
300 | } | |
301 | ||
ad01b7d4 | 302 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
303 | |
304 | if (!priv->oldlink) { | |
305 | new_state = 1; | |
306 | priv->oldlink = 1; | |
307 | } | |
308 | } else if (priv->oldlink) { | |
309 | new_state = 1; | |
310 | priv->oldlink = 0; | |
311 | priv->speed = 0; | |
312 | priv->oldduplex = -1; | |
313 | } | |
314 | ||
315 | if (new_state && netif_msg_link(priv)) | |
316 | phy_print_status(phydev); | |
317 | ||
318 | spin_unlock_irqrestore(&priv->lock, flags); | |
319 | ||
320 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
321 | } | |
322 | ||
323 | /** | |
324 | * stmmac_init_phy - PHY initialization | |
325 | * @dev: net device structure | |
326 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
327 | * to the mac driver. | |
328 | * Return value: | |
329 | * 0 on success | |
330 | */ | |
331 | static int stmmac_init_phy(struct net_device *dev) | |
332 | { | |
333 | struct stmmac_priv *priv = netdev_priv(dev); | |
334 | struct phy_device *phydev; | |
109cdd66 GC |
335 | char phy_id[MII_BUS_ID_SIZE + 3]; |
336 | char bus_id[MII_BUS_ID_SIZE]; | |
79ee1dc3 | 337 | int interface = priv->plat->interface; |
47dd7a54 GC |
338 | priv->oldlink = 0; |
339 | priv->speed = 0; | |
340 | priv->oldduplex = -1; | |
341 | ||
f142af2e SK |
342 | if (priv->plat->phy_bus_name) |
343 | snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", | |
344 | priv->plat->phy_bus_name, priv->plat->bus_id); | |
345 | else | |
346 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", | |
347 | priv->plat->bus_id); | |
348 | ||
109cdd66 | 349 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 350 | priv->plat->phy_addr); |
47dd7a54 GC |
351 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
352 | ||
79ee1dc3 | 353 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); |
47dd7a54 GC |
354 | |
355 | if (IS_ERR(phydev)) { | |
356 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
357 | return PTR_ERR(phydev); | |
358 | } | |
359 | ||
79ee1dc3 | 360 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 SK |
361 | if ((interface == PHY_INTERFACE_MODE_MII) || |
362 | (interface == PHY_INTERFACE_MODE_RMII)) | |
363 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | | |
364 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 365 | |
47dd7a54 GC |
366 | /* |
367 | * Broken HW is sometimes missing the pull-up resistor on the | |
368 | * MDIO line, which results in reads to non-existent devices returning | |
369 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
370 | * device as well. | |
371 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
372 | */ | |
373 | if (phydev->phy_id == 0) { | |
374 | phy_disconnect(phydev); | |
375 | return -ENODEV; | |
376 | } | |
377 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 378 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
379 | |
380 | priv->phydev = phydev; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
47dd7a54 GC |
385 | /** |
386 | * display_ring | |
387 | * @p: pointer to the ring. | |
388 | * @size: size of the ring. | |
389 | * Description: display all the descriptors within the ring. | |
390 | */ | |
391 | static void display_ring(struct dma_desc *p, int size) | |
392 | { | |
393 | struct tmp_s { | |
394 | u64 a; | |
395 | unsigned int b; | |
396 | unsigned int c; | |
397 | }; | |
398 | int i; | |
399 | for (i = 0; i < size; i++) { | |
400 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
401 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
402 | i, (unsigned int)virt_to_phys(&p[i]), | |
403 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
404 | x->b, x->c); | |
405 | pr_info("\n"); | |
406 | } | |
407 | } | |
408 | ||
286a8372 GC |
409 | static int stmmac_set_bfsize(int mtu, int bufsize) |
410 | { | |
411 | int ret = bufsize; | |
412 | ||
413 | if (mtu >= BUF_SIZE_4KiB) | |
414 | ret = BUF_SIZE_8KiB; | |
415 | else if (mtu >= BUF_SIZE_2KiB) | |
416 | ret = BUF_SIZE_4KiB; | |
417 | else if (mtu >= DMA_BUFFER_SIZE) | |
418 | ret = BUF_SIZE_2KiB; | |
419 | else | |
420 | ret = DMA_BUFFER_SIZE; | |
421 | ||
422 | return ret; | |
423 | } | |
424 | ||
47dd7a54 GC |
425 | /** |
426 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
427 | * @dev: net device structure | |
428 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
429 | * and allocates the socket buffers. It suppors the chained and ring |
430 | * modes. | |
47dd7a54 GC |
431 | */ |
432 | static void init_dma_desc_rings(struct net_device *dev) | |
433 | { | |
434 | int i; | |
435 | struct stmmac_priv *priv = netdev_priv(dev); | |
436 | struct sk_buff *skb; | |
437 | unsigned int txsize = priv->dma_tx_size; | |
438 | unsigned int rxsize = priv->dma_rx_size; | |
286a8372 GC |
439 | unsigned int bfsize; |
440 | int dis_ic = 0; | |
441 | int des3_as_data_buf = 0; | |
47dd7a54 | 442 | |
286a8372 GC |
443 | /* Set the max buffer size according to the DESC mode |
444 | * and the MTU. Note that RING mode allows 16KiB bsize. */ | |
445 | bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); | |
446 | ||
447 | if (bfsize == BUF_SIZE_16KiB) | |
448 | des3_as_data_buf = 1; | |
47dd7a54 | 449 | else |
286a8372 | 450 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 451 | |
73cfe264 GC |
452 | #ifdef CONFIG_STMMAC_TIMER |
453 | /* Disable interrupts on completion for the reception if timer is on */ | |
454 | if (likely(priv->tm->enable)) | |
455 | dis_ic = 1; | |
456 | #endif | |
47dd7a54 GC |
457 | |
458 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
459 | txsize, rxsize, bfsize); | |
460 | ||
461 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
462 | priv->rx_skbuff = | |
463 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
464 | priv->dma_rx = | |
465 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
466 | rxsize * | |
467 | sizeof(struct dma_desc), | |
468 | &priv->dma_rx_phy, | |
469 | GFP_KERNEL); | |
470 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
471 | GFP_KERNEL); | |
472 | priv->dma_tx = | |
473 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
474 | txsize * | |
475 | sizeof(struct dma_desc), | |
476 | &priv->dma_tx_phy, | |
477 | GFP_KERNEL); | |
478 | ||
479 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
480 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
481 | return; | |
482 | } | |
483 | ||
286a8372 | 484 | DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " |
47dd7a54 GC |
485 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", |
486 | dev->name, priv->dma_rx, priv->dma_tx, | |
487 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
488 | ||
489 | /* RX INITIALIZATION */ | |
490 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
491 | "skb\t\tskb data\tdma data\n"); | |
492 | ||
493 | for (i = 0; i < rxsize; i++) { | |
494 | struct dma_desc *p = priv->dma_rx + i; | |
495 | ||
45db81e1 GC |
496 | skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, |
497 | GFP_KERNEL); | |
47dd7a54 GC |
498 | if (unlikely(skb == NULL)) { |
499 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
500 | break; | |
501 | } | |
45db81e1 | 502 | skb_reserve(skb, NET_IP_ALIGN); |
47dd7a54 GC |
503 | priv->rx_skbuff[i] = skb; |
504 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
505 | bfsize, DMA_FROM_DEVICE); | |
506 | ||
507 | p->des2 = priv->rx_skbuff_dma[i]; | |
286a8372 GC |
508 | |
509 | priv->hw->ring->init_desc3(des3_as_data_buf, p); | |
510 | ||
47dd7a54 GC |
511 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], |
512 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
513 | } | |
514 | priv->cur_rx = 0; | |
515 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
516 | priv->dma_buf_sz = bfsize; | |
517 | buf_sz = bfsize; | |
518 | ||
519 | /* TX INITIALIZATION */ | |
520 | for (i = 0; i < txsize; i++) { | |
521 | priv->tx_skbuff[i] = NULL; | |
522 | priv->dma_tx[i].des2 = 0; | |
523 | } | |
286a8372 GC |
524 | |
525 | /* In case of Chained mode this sets the des3 to the next | |
526 | * element in the chain */ | |
527 | priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); | |
528 | priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); | |
529 | ||
47dd7a54 GC |
530 | priv->dirty_tx = 0; |
531 | priv->cur_tx = 0; | |
532 | ||
533 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
534 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
535 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
536 | |
537 | if (netif_msg_hw(priv)) { | |
538 | pr_info("RX descriptor ring:\n"); | |
539 | display_ring(priv->dma_rx, rxsize); | |
540 | pr_info("TX descriptor ring:\n"); | |
541 | display_ring(priv->dma_tx, txsize); | |
542 | } | |
47dd7a54 GC |
543 | } |
544 | ||
545 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
546 | { | |
547 | int i; | |
548 | ||
549 | for (i = 0; i < priv->dma_rx_size; i++) { | |
550 | if (priv->rx_skbuff[i]) { | |
551 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
552 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
553 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
554 | } | |
555 | priv->rx_skbuff[i] = NULL; | |
556 | } | |
47dd7a54 GC |
557 | } |
558 | ||
559 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
560 | { | |
561 | int i; | |
562 | ||
563 | for (i = 0; i < priv->dma_tx_size; i++) { | |
564 | if (priv->tx_skbuff[i] != NULL) { | |
565 | struct dma_desc *p = priv->dma_tx + i; | |
566 | if (p->des2) | |
567 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
568 | priv->hw->desc->get_tx_len(p), |
569 | DMA_TO_DEVICE); | |
47dd7a54 GC |
570 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
571 | priv->tx_skbuff[i] = NULL; | |
572 | } | |
573 | } | |
47dd7a54 GC |
574 | } |
575 | ||
576 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
577 | { | |
578 | /* Release the DMA TX/RX socket buffers */ | |
579 | dma_free_rx_skbufs(priv); | |
580 | dma_free_tx_skbufs(priv); | |
581 | ||
582 | /* Free the region of consistent memory previously allocated for | |
583 | * the DMA */ | |
584 | dma_free_coherent(priv->device, | |
585 | priv->dma_tx_size * sizeof(struct dma_desc), | |
586 | priv->dma_tx, priv->dma_tx_phy); | |
587 | dma_free_coherent(priv->device, | |
588 | priv->dma_rx_size * sizeof(struct dma_desc), | |
589 | priv->dma_rx, priv->dma_rx_phy); | |
590 | kfree(priv->rx_skbuff_dma); | |
591 | kfree(priv->rx_skbuff); | |
592 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
593 | } |
594 | ||
47dd7a54 GC |
595 | /** |
596 | * stmmac_dma_operation_mode - HW DMA operation mode | |
597 | * @priv : pointer to the private device structure. | |
598 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 599 | * or Store-And-Forward capability. |
47dd7a54 GC |
600 | */ |
601 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
602 | { | |
61b8013a SK |
603 | if (likely(priv->plat->force_sf_dma_mode || |
604 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
605 | /* | |
606 | * In case of GMAC, SF mode can be enabled | |
607 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
608 | * 1) TX COE if actually supported |
609 | * 2) There is no bugged Jumbo frame support | |
610 | * that needs to not insert csum in the TDES. | |
611 | */ | |
612 | priv->hw->dma->dma_mode(priv->ioaddr, | |
613 | SF_DMA_MODE, SF_DMA_MODE); | |
614 | tc = SF_DMA_MODE; | |
615 | } else | |
616 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
617 | } |
618 | ||
47dd7a54 GC |
619 | /** |
620 | * stmmac_tx: | |
621 | * @priv: private driver structure | |
622 | * Description: it reclaims resources after transmission completes. | |
623 | */ | |
624 | static void stmmac_tx(struct stmmac_priv *priv) | |
625 | { | |
626 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 627 | |
a9097a96 GC |
628 | spin_lock(&priv->tx_lock); |
629 | ||
47dd7a54 GC |
630 | while (priv->dirty_tx != priv->cur_tx) { |
631 | int last; | |
632 | unsigned int entry = priv->dirty_tx % txsize; | |
633 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
634 | struct dma_desc *p = priv->dma_tx + entry; | |
635 | ||
636 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 637 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
638 | break; |
639 | ||
640 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 641 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
642 | if (likely(last)) { |
643 | int tx_error = | |
db98a0b0 GC |
644 | priv->hw->desc->tx_status(&priv->dev->stats, |
645 | &priv->xstats, p, | |
ad01b7d4 | 646 | priv->ioaddr); |
47dd7a54 GC |
647 | if (likely(tx_error == 0)) { |
648 | priv->dev->stats.tx_packets++; | |
649 | priv->xstats.tx_pkt_n++; | |
650 | } else | |
651 | priv->dev->stats.tx_errors++; | |
652 | } | |
653 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
654 | priv->cur_tx, priv->dirty_tx); | |
655 | ||
656 | if (likely(p->des2)) | |
657 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 658 | priv->hw->desc->get_tx_len(p), |
47dd7a54 | 659 | DMA_TO_DEVICE); |
286a8372 | 660 | priv->hw->ring->clean_desc3(p); |
47dd7a54 GC |
661 | |
662 | if (likely(skb != NULL)) { | |
663 | /* | |
664 | * If there's room in the queue (limit it to size) | |
665 | * we add this skb back into the pool, | |
666 | * if it's the right size. | |
667 | */ | |
668 | if ((skb_queue_len(&priv->rx_recycle) < | |
669 | priv->dma_rx_size) && | |
670 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
671 | __skb_queue_head(&priv->rx_recycle, skb); | |
672 | else | |
673 | dev_kfree_skb(skb); | |
674 | ||
675 | priv->tx_skbuff[entry] = NULL; | |
676 | } | |
677 | ||
db98a0b0 | 678 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 | 679 | |
13497f58 | 680 | priv->dirty_tx++; |
47dd7a54 GC |
681 | } |
682 | if (unlikely(netif_queue_stopped(priv->dev) && | |
683 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
684 | netif_tx_lock(priv->dev); | |
685 | if (netif_queue_stopped(priv->dev) && | |
686 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
687 | TX_DBG("%s: restart transmit\n", __func__); | |
688 | netif_wake_queue(priv->dev); | |
689 | } | |
690 | netif_tx_unlock(priv->dev); | |
691 | } | |
a9097a96 | 692 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
693 | } |
694 | ||
695 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
696 | { | |
73cfe264 GC |
697 | #ifdef CONFIG_STMMAC_TIMER |
698 | if (likely(priv->tm->enable)) | |
699 | priv->tm->timer_start(tmrate); | |
700 | else | |
47dd7a54 | 701 | #endif |
ad01b7d4 | 702 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
703 | } |
704 | ||
705 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
706 | { | |
73cfe264 GC |
707 | #ifdef CONFIG_STMMAC_TIMER |
708 | if (likely(priv->tm->enable)) | |
709 | priv->tm->timer_stop(); | |
710 | else | |
47dd7a54 | 711 | #endif |
ad01b7d4 | 712 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
713 | } |
714 | ||
715 | static int stmmac_has_work(struct stmmac_priv *priv) | |
716 | { | |
717 | unsigned int has_work = 0; | |
718 | int rxret, tx_work = 0; | |
719 | ||
db98a0b0 | 720 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
721 | (priv->cur_rx % priv->dma_rx_size)); |
722 | ||
723 | if (priv->dirty_tx != priv->cur_tx) | |
724 | tx_work = 1; | |
725 | ||
726 | if (likely(!rxret || tx_work)) | |
727 | has_work = 1; | |
728 | ||
729 | return has_work; | |
730 | } | |
731 | ||
732 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
733 | { | |
734 | if (likely(stmmac_has_work(priv))) { | |
735 | stmmac_disable_irq(priv); | |
736 | napi_schedule(&priv->napi); | |
737 | } | |
738 | } | |
739 | ||
740 | #ifdef CONFIG_STMMAC_TIMER | |
741 | void stmmac_schedule(struct net_device *dev) | |
742 | { | |
743 | struct stmmac_priv *priv = netdev_priv(dev); | |
744 | ||
745 | priv->xstats.sched_timer_n++; | |
746 | ||
747 | _stmmac_schedule(priv); | |
47dd7a54 GC |
748 | } |
749 | ||
750 | static void stmmac_no_timer_started(unsigned int x) | |
751 | {; | |
752 | }; | |
753 | ||
754 | static void stmmac_no_timer_stopped(void) | |
755 | {; | |
756 | }; | |
757 | #endif | |
758 | ||
759 | /** | |
760 | * stmmac_tx_err: | |
761 | * @priv: pointer to the private device structure | |
762 | * Description: it cleans the descriptors and restarts the transmission | |
763 | * in case of errors. | |
764 | */ | |
765 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
766 | { | |
767 | netif_stop_queue(priv->dev); | |
768 | ||
ad01b7d4 | 769 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 770 | dma_free_tx_skbufs(priv); |
db98a0b0 | 771 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
772 | priv->dirty_tx = 0; |
773 | priv->cur_tx = 0; | |
ad01b7d4 | 774 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
775 | |
776 | priv->dev->stats.tx_errors++; | |
777 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
778 | } |
779 | ||
47dd7a54 | 780 | |
aec7ff27 GC |
781 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
782 | { | |
aec7ff27 GC |
783 | int status; |
784 | ||
ad01b7d4 | 785 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
786 | if (likely(status == handle_tx_rx)) |
787 | _stmmac_schedule(priv); | |
788 | ||
789 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
790 | /* Try to bump up the dma threshold on this failure */ | |
791 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
792 | tc += 64; | |
ad01b7d4 | 793 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 794 | priv->xstats.threshold = tc; |
47dd7a54 | 795 | } |
aec7ff27 GC |
796 | } else if (unlikely(status == tx_hard_error)) |
797 | stmmac_tx_err(priv); | |
47dd7a54 GC |
798 | } |
799 | ||
1c901a46 GC |
800 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
801 | { | |
802 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
803 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
804 | ||
4f795b25 GC |
805 | /* Mask MMC irq, counters are managed in SW and registers |
806 | * are cleared on each READ eventually. */ | |
1c901a46 | 807 | dwmac_mmc_intr_all_mask(priv->ioaddr); |
4f795b25 GC |
808 | |
809 | if (priv->dma_cap.rmon) { | |
810 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
811 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
812 | } else | |
aae54cff | 813 | pr_info(" No MAC Management Counters available\n"); |
1c901a46 GC |
814 | } |
815 | ||
f0b9d786 GC |
816 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
817 | { | |
818 | u32 hwid = priv->hw->synopsys_uid; | |
819 | ||
820 | /* Only check valid Synopsys Id because old MAC chips | |
821 | * have no HW registers where get the ID */ | |
822 | if (likely(hwid)) { | |
823 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
824 | u32 synid = (hwid & 0x000000ff); | |
825 | ||
cf3f047b | 826 | pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", |
f0b9d786 GC |
827 | uid, synid); |
828 | ||
829 | return synid; | |
830 | } | |
831 | return 0; | |
832 | } | |
e7434821 | 833 | |
19e30c14 GC |
834 | /** |
835 | * stmmac_selec_desc_mode | |
ff3dd78c GC |
836 | * @priv : private structure |
837 | * Description: select the Enhanced/Alternate or Normal descriptors | |
838 | */ | |
19e30c14 GC |
839 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
840 | { | |
841 | if (priv->plat->enh_desc) { | |
842 | pr_info(" Enhanced/Alternate descriptors\n"); | |
843 | priv->hw->desc = &enh_desc_ops; | |
844 | } else { | |
845 | pr_info(" Normal descriptors\n"); | |
846 | priv->hw->desc = &ndesc_ops; | |
847 | } | |
848 | } | |
849 | ||
850 | /** | |
851 | * stmmac_get_hw_features | |
852 | * @priv : private device pointer | |
853 | * Description: | |
854 | * new GMAC chip generations have a new register to indicate the | |
855 | * presence of the optional feature/functions. | |
856 | * This can be also used to override the value passed through the | |
857 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
858 | */ |
859 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
860 | { | |
5e6efe88 | 861 | u32 hw_cap = 0; |
3c20f72f | 862 | |
5e6efe88 GC |
863 | if (priv->hw->dma->get_hw_feature) { |
864 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 865 | |
1db123fb RK |
866 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
867 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
868 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
869 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
870 | priv->dma_cap.multi_addr = | |
871 | (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; | |
872 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; | |
873 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
874 | priv->dma_cap.pmt_remote_wake_up = | |
875 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; | |
876 | priv->dma_cap.pmt_magic_frame = | |
877 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; | |
19e30c14 | 878 | /* MMC */ |
1db123fb | 879 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
e7434821 | 880 | /* IEEE 1588-2002*/ |
1db123fb RK |
881 | priv->dma_cap.time_stamp = |
882 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; | |
e7434821 | 883 | /* IEEE 1588-2008*/ |
1db123fb RK |
884 | priv->dma_cap.atime_stamp = |
885 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; | |
e7434821 | 886 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
887 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
888 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 889 | /* TX and RX csum */ |
1db123fb RK |
890 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
891 | priv->dma_cap.rx_coe_type1 = | |
892 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; | |
893 | priv->dma_cap.rx_coe_type2 = | |
894 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; | |
895 | priv->dma_cap.rxfifo_over_2048 = | |
896 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; | |
e7434821 | 897 | /* TX and RX number of channels */ |
1db123fb RK |
898 | priv->dma_cap.number_rx_channel = |
899 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; | |
900 | priv->dma_cap.number_tx_channel = | |
901 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; | |
e7434821 | 902 | /* Alternate (enhanced) DESC mode*/ |
1db123fb RK |
903 | priv->dma_cap.enh_desc = |
904 | (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
e7434821 | 905 | |
19e30c14 | 906 | } |
e7434821 GC |
907 | |
908 | return hw_cap; | |
909 | } | |
910 | ||
bfab27a1 GC |
911 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
912 | { | |
913 | /* verify if the MAC address is valid, in case of failures it | |
914 | * generates a random MAC address */ | |
915 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { | |
916 | priv->hw->mac->get_umac_addr((void __iomem *) | |
917 | priv->dev->base_addr, | |
918 | priv->dev->dev_addr, 0); | |
919 | if (!is_valid_ether_addr(priv->dev->dev_addr)) | |
f2cedb63 | 920 | eth_hw_addr_random(priv->dev); |
bfab27a1 GC |
921 | } |
922 | pr_warning("%s: device MAC address %pM\n", priv->dev->name, | |
923 | priv->dev->dev_addr); | |
924 | } | |
925 | ||
0f1f88a8 GC |
926 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
927 | { | |
928 | int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; | |
b9cde0a8 | 929 | int mixed_burst = 0; |
0f1f88a8 GC |
930 | |
931 | /* Some DMA parameters can be passed from the platform; | |
932 | * in case of these are not passed we keep a default | |
933 | * (good for all the chips) and init the DMA! */ | |
934 | if (priv->plat->dma_cfg) { | |
935 | pbl = priv->plat->dma_cfg->pbl; | |
936 | fixed_burst = priv->plat->dma_cfg->fixed_burst; | |
b9cde0a8 | 937 | mixed_burst = priv->plat->dma_cfg->mixed_burst; |
0f1f88a8 GC |
938 | burst_len = priv->plat->dma_cfg->burst_len; |
939 | } | |
940 | ||
b9cde0a8 | 941 | return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, |
0f1f88a8 GC |
942 | burst_len, priv->dma_tx_phy, |
943 | priv->dma_rx_phy); | |
944 | } | |
945 | ||
47dd7a54 GC |
946 | /** |
947 | * stmmac_open - open entry point of the driver | |
948 | * @dev : pointer to the device structure. | |
949 | * Description: | |
950 | * This function is the open entry point of the driver. | |
951 | * Return value: | |
952 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
953 | * file on failure. | |
954 | */ | |
955 | static int stmmac_open(struct net_device *dev) | |
956 | { | |
957 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
958 | int ret; |
959 | ||
47dd7a54 | 960 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 961 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
4bfcbd7a FV |
962 | if (unlikely(priv->tm == NULL)) |
963 | return -ENOMEM; | |
e404decb | 964 | |
47dd7a54 GC |
965 | priv->tm->freq = tmrate; |
966 | ||
73cfe264 GC |
967 | /* Test if the external timer can be actually used. |
968 | * In case of failure continue without timer. */ | |
47dd7a54 | 969 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 970 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
971 | priv->tm->freq = 0; |
972 | priv->tm->timer_start = stmmac_no_timer_started; | |
973 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
974 | } else |
975 | priv->tm->enable = 1; | |
47dd7a54 | 976 | #endif |
4bfcbd7a FV |
977 | stmmac_clk_enable(priv); |
978 | ||
979 | stmmac_check_ether_addr(priv); | |
980 | ||
f66ffe28 GC |
981 | ret = stmmac_init_phy(dev); |
982 | if (unlikely(ret)) { | |
983 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
984 | goto open_error; | |
985 | } | |
47dd7a54 GC |
986 | |
987 | /* Create and initialize the TX/RX descriptors chains. */ | |
988 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
989 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
990 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
991 | init_dma_desc_rings(dev); | |
992 | ||
993 | /* DMA initialization and SW reset */ | |
0f1f88a8 | 994 | ret = stmmac_init_dma_engine(priv); |
f66ffe28 | 995 | if (ret < 0) { |
47dd7a54 | 996 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 997 | goto open_error; |
47dd7a54 GC |
998 | } |
999 | ||
1000 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 1001 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
cf3f047b | 1002 | |
ca5f12c1 | 1003 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
1004 | if (priv->plat->bus_setup) |
1005 | priv->plat->bus_setup(priv->ioaddr); | |
cf3f047b | 1006 | |
47dd7a54 | 1007 | /* Initialize the MAC Core */ |
ad01b7d4 | 1008 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 1009 | |
f66ffe28 GC |
1010 | /* Request the IRQ lines */ |
1011 | ret = request_irq(dev->irq, stmmac_interrupt, | |
1012 | IRQF_SHARED, dev->name, dev); | |
1013 | if (unlikely(ret < 0)) { | |
1014 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1015 | __func__, dev->irq, ret); | |
1016 | goto open_error; | |
1017 | } | |
1018 | ||
7a13f8f5 FV |
1019 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1020 | if (priv->wol_irq != dev->irq) { | |
1021 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1022 | IRQF_SHARED, dev->name, dev); | |
1023 | if (unlikely(ret < 0)) { | |
1024 | pr_err("%s: ERROR: allocating the ext WoL IRQ %d " | |
1025 | "(error: %d)\n", __func__, priv->wol_irq, ret); | |
1026 | goto open_error_wolirq; | |
1027 | } | |
1028 | } | |
1029 | ||
47dd7a54 | 1030 | /* Enable the MAC Rx/Tx */ |
bfab27a1 | 1031 | stmmac_set_mac(priv->ioaddr, true); |
47dd7a54 GC |
1032 | |
1033 | /* Set the HW DMA mode and the COE */ | |
1034 | stmmac_dma_operation_mode(priv); | |
1035 | ||
1036 | /* Extra statistics */ | |
1037 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1038 | priv->xstats.threshold = tc; | |
1039 | ||
4f795b25 | 1040 | stmmac_mmc_setup(priv); |
1c901a46 | 1041 | |
bfab27a1 GC |
1042 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1043 | ret = stmmac_init_fs(dev); | |
1044 | if (ret < 0) | |
cf3f047b | 1045 | pr_warning("%s: failed debugFS registration\n", __func__); |
bfab27a1 | 1046 | #endif |
47dd7a54 GC |
1047 | /* Start the ball rolling... */ |
1048 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
1049 | priv->hw->dma->start_tx(priv->ioaddr); |
1050 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
1051 | |
1052 | #ifdef CONFIG_STMMAC_TIMER | |
1053 | priv->tm->timer_start(tmrate); | |
1054 | #endif | |
cf3f047b | 1055 | |
47dd7a54 GC |
1056 | /* Dump DMA/MAC registers */ |
1057 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
1058 | priv->hw->mac->dump_regs(priv->ioaddr); |
1059 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
1060 | } |
1061 | ||
1062 | if (priv->phydev) | |
1063 | phy_start(priv->phydev); | |
1064 | ||
1065 | napi_enable(&priv->napi); | |
1066 | skb_queue_head_init(&priv->rx_recycle); | |
1067 | netif_start_queue(dev); | |
f66ffe28 | 1068 | |
47dd7a54 | 1069 | return 0; |
f66ffe28 | 1070 | |
7a13f8f5 FV |
1071 | open_error_wolirq: |
1072 | free_irq(dev->irq, dev); | |
1073 | ||
f66ffe28 GC |
1074 | open_error: |
1075 | #ifdef CONFIG_STMMAC_TIMER | |
1076 | kfree(priv->tm); | |
1077 | #endif | |
1078 | if (priv->phydev) | |
1079 | phy_disconnect(priv->phydev); | |
1080 | ||
ba1377ff | 1081 | stmmac_clk_disable(priv); |
4bfcbd7a | 1082 | |
f66ffe28 | 1083 | return ret; |
47dd7a54 GC |
1084 | } |
1085 | ||
1086 | /** | |
1087 | * stmmac_release - close entry point of the driver | |
1088 | * @dev : device pointer. | |
1089 | * Description: | |
1090 | * This is the stop entry point of the driver. | |
1091 | */ | |
1092 | static int stmmac_release(struct net_device *dev) | |
1093 | { | |
1094 | struct stmmac_priv *priv = netdev_priv(dev); | |
1095 | ||
1096 | /* Stop and disconnect the PHY */ | |
1097 | if (priv->phydev) { | |
1098 | phy_stop(priv->phydev); | |
1099 | phy_disconnect(priv->phydev); | |
1100 | priv->phydev = NULL; | |
1101 | } | |
1102 | ||
1103 | netif_stop_queue(dev); | |
1104 | ||
1105 | #ifdef CONFIG_STMMAC_TIMER | |
1106 | /* Stop and release the timer */ | |
1107 | stmmac_close_ext_timer(); | |
1108 | if (priv->tm != NULL) | |
1109 | kfree(priv->tm); | |
1110 | #endif | |
1111 | napi_disable(&priv->napi); | |
1112 | skb_queue_purge(&priv->rx_recycle); | |
1113 | ||
1114 | /* Free the IRQ lines */ | |
1115 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1116 | if (priv->wol_irq != dev->irq) |
1117 | free_irq(priv->wol_irq, dev); | |
47dd7a54 GC |
1118 | |
1119 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1120 | priv->hw->dma->stop_tx(priv->ioaddr); |
1121 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1122 | |
1123 | /* Release and free the Rx/Tx resources */ | |
1124 | free_dma_desc_resources(priv); | |
1125 | ||
19449bfc | 1126 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1127 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1128 | |
1129 | netif_carrier_off(dev); | |
1130 | ||
bfab27a1 GC |
1131 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1132 | stmmac_exit_fs(); | |
1133 | #endif | |
ba1377ff | 1134 | stmmac_clk_disable(priv); |
bfab27a1 | 1135 | |
47dd7a54 GC |
1136 | return 0; |
1137 | } | |
1138 | ||
47dd7a54 GC |
1139 | /** |
1140 | * stmmac_xmit: | |
1141 | * @skb : the socket buffer | |
1142 | * @dev : device pointer | |
1143 | * Description : Tx entry point of the driver. | |
1144 | */ | |
1145 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1146 | { | |
1147 | struct stmmac_priv *priv = netdev_priv(dev); | |
1148 | unsigned int txsize = priv->dma_tx_size; | |
1149 | unsigned int entry; | |
1150 | int i, csum_insertion = 0; | |
1151 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1152 | struct dma_desc *desc, *first; | |
286a8372 | 1153 | unsigned int nopaged_len = skb_headlen(skb); |
47dd7a54 GC |
1154 | |
1155 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1156 | if (!netif_queue_stopped(dev)) { | |
1157 | netif_stop_queue(dev); | |
1158 | /* This is a hard error, log it. */ | |
1159 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1160 | __func__); | |
1161 | } | |
1162 | return NETDEV_TX_BUSY; | |
1163 | } | |
1164 | ||
a9097a96 GC |
1165 | spin_lock(&priv->tx_lock); |
1166 | ||
47dd7a54 GC |
1167 | entry = priv->cur_tx % txsize; |
1168 | ||
1169 | #ifdef STMMAC_XMIT_DEBUG | |
1170 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1171 | pr_info("stmmac xmit:\n" | |
1172 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1173 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
286a8372 | 1174 | skb, skb->len, nopaged_len, nfrags, skb->ip_summed, |
47dd7a54 GC |
1175 | !skb_is_gso(skb) ? "isn't" : "is"); |
1176 | #endif | |
1177 | ||
5e982f3b | 1178 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1179 | |
1180 | desc = priv->dma_tx + entry; | |
1181 | first = desc; | |
1182 | ||
1183 | #ifdef STMMAC_XMIT_DEBUG | |
1184 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1185 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1186 | "\t\tn_frags: %d, ip_summed: %d\n", | |
286a8372 | 1187 | skb->len, nopaged_len, nfrags, skb->ip_summed); |
47dd7a54 GC |
1188 | #endif |
1189 | priv->tx_skbuff[entry] = skb; | |
286a8372 GC |
1190 | |
1191 | if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { | |
1192 | entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); | |
47dd7a54 GC |
1193 | desc = priv->dma_tx + entry; |
1194 | } else { | |
47dd7a54 GC |
1195 | desc->des2 = dma_map_single(priv->device, skb->data, |
1196 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1197 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1198 | csum_insertion); | |
47dd7a54 GC |
1199 | } |
1200 | ||
1201 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1202 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1203 | int len = skb_frag_size(frag); | |
47dd7a54 GC |
1204 | |
1205 | entry = (++priv->cur_tx) % txsize; | |
1206 | desc = priv->dma_tx + entry; | |
1207 | ||
1208 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
f722380d IC |
1209 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1210 | DMA_TO_DEVICE); | |
47dd7a54 | 1211 | priv->tx_skbuff[entry] = NULL; |
db98a0b0 | 1212 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1213 | wmb(); |
db98a0b0 | 1214 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1215 | } |
1216 | ||
1217 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1218 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1219 | |
47dd7a54 | 1220 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1221 | /* Clean IC while using timer */ |
1222 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1223 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1224 | #endif |
eb0dc4bb SH |
1225 | |
1226 | wmb(); | |
1227 | ||
47dd7a54 | 1228 | /* To avoid raise condition */ |
db98a0b0 | 1229 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1230 | |
1231 | priv->cur_tx++; | |
1232 | ||
1233 | #ifdef STMMAC_XMIT_DEBUG | |
1234 | if (netif_msg_pktdata(priv)) { | |
1235 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1236 | "first=%p, nfrags=%d\n", | |
1237 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1238 | entry, first, nfrags); | |
1239 | display_ring(priv->dma_tx, txsize); | |
1240 | pr_info(">>> frame to be transmitted: "); | |
1241 | print_pkt(skb->data, skb->len); | |
1242 | } | |
1243 | #endif | |
1244 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1245 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1246 | netif_stop_queue(dev); | |
1247 | } | |
1248 | ||
1249 | dev->stats.tx_bytes += skb->len; | |
1250 | ||
3e82ce12 RC |
1251 | skb_tx_timestamp(skb); |
1252 | ||
52f64fae RC |
1253 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1254 | ||
a9097a96 GC |
1255 | spin_unlock(&priv->tx_lock); |
1256 | ||
47dd7a54 GC |
1257 | return NETDEV_TX_OK; |
1258 | } | |
1259 | ||
1260 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1261 | { | |
1262 | unsigned int rxsize = priv->dma_rx_size; | |
1263 | int bfsize = priv->dma_buf_sz; | |
1264 | struct dma_desc *p = priv->dma_rx; | |
1265 | ||
1266 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1267 | unsigned int entry = priv->dirty_rx % rxsize; | |
1268 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1269 | struct sk_buff *skb; | |
1270 | ||
1271 | skb = __skb_dequeue(&priv->rx_recycle); | |
1272 | if (skb == NULL) | |
1273 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1274 | bfsize); | |
1275 | ||
1276 | if (unlikely(skb == NULL)) | |
1277 | break; | |
1278 | ||
1279 | priv->rx_skbuff[entry] = skb; | |
1280 | priv->rx_skbuff_dma[entry] = | |
1281 | dma_map_single(priv->device, skb->data, bfsize, | |
1282 | DMA_FROM_DEVICE); | |
1283 | ||
1284 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
286a8372 GC |
1285 | |
1286 | if (unlikely(priv->plat->has_gmac)) | |
1287 | priv->hw->ring->refill_desc3(bfsize, p + entry); | |
1288 | ||
47dd7a54 GC |
1289 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); |
1290 | } | |
eb0dc4bb | 1291 | wmb(); |
db98a0b0 | 1292 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1293 | } |
47dd7a54 GC |
1294 | } |
1295 | ||
1296 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1297 | { | |
1298 | unsigned int rxsize = priv->dma_rx_size; | |
1299 | unsigned int entry = priv->cur_rx % rxsize; | |
1300 | unsigned int next_entry; | |
1301 | unsigned int count = 0; | |
1302 | struct dma_desc *p = priv->dma_rx + entry; | |
1303 | struct dma_desc *p_next; | |
1304 | ||
1305 | #ifdef STMMAC_RX_DEBUG | |
1306 | if (netif_msg_hw(priv)) { | |
1307 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1308 | display_ring(priv->dma_rx, rxsize); | |
1309 | } | |
1310 | #endif | |
db98a0b0 | 1311 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1312 | int status; |
1313 | ||
1314 | if (count >= limit) | |
1315 | break; | |
1316 | ||
1317 | count++; | |
1318 | ||
1319 | next_entry = (++priv->cur_rx) % rxsize; | |
1320 | p_next = priv->dma_rx + next_entry; | |
1321 | prefetch(p_next); | |
1322 | ||
1323 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1324 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1325 | &priv->xstats, p)); | |
47dd7a54 GC |
1326 | if (unlikely(status == discard_frame)) |
1327 | priv->dev->stats.rx_errors++; | |
1328 | else { | |
1329 | struct sk_buff *skb; | |
3eeb2997 | 1330 | int frame_len; |
47dd7a54 | 1331 | |
38912bdb DS |
1332 | frame_len = priv->hw->desc->get_rx_frame_len(p, |
1333 | priv->plat->rx_coe); | |
3eeb2997 GC |
1334 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
1335 | * Type frames (LLC/LLC-SNAP) */ | |
1336 | if (unlikely(status != llc_snap)) | |
1337 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1338 | #ifdef STMMAC_RX_DEBUG |
1339 | if (frame_len > ETH_FRAME_LEN) | |
1340 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1341 | frame_len, status); | |
1342 | ||
1343 | if (netif_msg_hw(priv)) | |
1344 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1345 | p, entry, p->des2); | |
1346 | #endif | |
1347 | skb = priv->rx_skbuff[entry]; | |
1348 | if (unlikely(!skb)) { | |
1349 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1350 | priv->dev->name); | |
1351 | priv->dev->stats.rx_dropped++; | |
1352 | break; | |
1353 | } | |
1354 | prefetch(skb->data - NET_IP_ALIGN); | |
1355 | priv->rx_skbuff[entry] = NULL; | |
1356 | ||
1357 | skb_put(skb, frame_len); | |
1358 | dma_unmap_single(priv->device, | |
1359 | priv->rx_skbuff_dma[entry], | |
1360 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1361 | #ifdef STMMAC_RX_DEBUG | |
1362 | if (netif_msg_pktdata(priv)) { | |
1363 | pr_info(" frame received (%dbytes)", frame_len); | |
1364 | print_pkt(skb->data, frame_len); | |
1365 | } | |
1366 | #endif | |
1367 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1368 | ||
38912bdb | 1369 | if (unlikely(!priv->plat->rx_coe)) { |
3c20f72f | 1370 | /* No RX COE for old mac10/100 devices */ |
bc8acf2c | 1371 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1372 | netif_receive_skb(skb); |
1373 | } else { | |
1374 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1375 | napi_gro_receive(&priv->napi, skb); | |
1376 | } | |
1377 | ||
1378 | priv->dev->stats.rx_packets++; | |
1379 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1380 | } |
1381 | entry = next_entry; | |
1382 | p = p_next; /* use prefetched values */ | |
1383 | } | |
1384 | ||
1385 | stmmac_rx_refill(priv); | |
1386 | ||
1387 | priv->xstats.rx_pkt_n += count; | |
1388 | ||
1389 | return count; | |
1390 | } | |
1391 | ||
1392 | /** | |
1393 | * stmmac_poll - stmmac poll method (NAPI) | |
1394 | * @napi : pointer to the napi structure. | |
1395 | * @budget : maximum number of packets that the current CPU can receive from | |
1396 | * all interfaces. | |
1397 | * Description : | |
1398 | * This function implements the the reception process. | |
1399 | * Also it runs the TX completion thread | |
1400 | */ | |
1401 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1402 | { | |
1403 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1404 | int work_done = 0; | |
1405 | ||
1406 | priv->xstats.poll_n++; | |
1407 | stmmac_tx(priv); | |
1408 | work_done = stmmac_rx(priv, budget); | |
1409 | ||
1410 | if (work_done < budget) { | |
1411 | napi_complete(napi); | |
1412 | stmmac_enable_irq(priv); | |
1413 | } | |
1414 | return work_done; | |
1415 | } | |
1416 | ||
1417 | /** | |
1418 | * stmmac_tx_timeout | |
1419 | * @dev : Pointer to net device structure | |
1420 | * Description: this function is called when a packet transmission fails to | |
1421 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1422 | * netdev structure and arrange for the device to be reset to a sane state | |
1423 | * in order to transmit a new packet. | |
1424 | */ | |
1425 | static void stmmac_tx_timeout(struct net_device *dev) | |
1426 | { | |
1427 | struct stmmac_priv *priv = netdev_priv(dev); | |
1428 | ||
1429 | /* Clear Tx resources and restart transmitting again */ | |
1430 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1431 | } |
1432 | ||
1433 | /* Configuration changes (passed on by ifconfig) */ | |
1434 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1435 | { | |
1436 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1437 | return -EBUSY; | |
1438 | ||
1439 | /* Don't allow changing the I/O address */ | |
1440 | if (map->base_addr != dev->base_addr) { | |
1441 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1442 | return -EOPNOTSUPP; | |
1443 | } | |
1444 | ||
1445 | /* Don't allow changing the IRQ */ | |
1446 | if (map->irq != dev->irq) { | |
1447 | pr_warning("%s: can't change IRQ number %d\n", | |
1448 | dev->name, dev->irq); | |
1449 | return -EOPNOTSUPP; | |
1450 | } | |
1451 | ||
1452 | /* ignore other fields */ | |
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | /** | |
01789349 | 1457 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1458 | * @dev : pointer to the device structure |
1459 | * Description: | |
1460 | * This function is a driver entry point which gets called by the kernel | |
1461 | * whenever multicast addresses must be enabled/disabled. | |
1462 | * Return value: | |
1463 | * void. | |
1464 | */ | |
01789349 | 1465 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1466 | { |
1467 | struct stmmac_priv *priv = netdev_priv(dev); | |
1468 | ||
1469 | spin_lock(&priv->lock); | |
cffb13f4 | 1470 | priv->hw->mac->set_filter(dev, priv->synopsys_id); |
47dd7a54 | 1471 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1472 | } |
1473 | ||
1474 | /** | |
1475 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1476 | * @dev : device pointer. | |
1477 | * @new_mtu : the new MTU size for the device. | |
1478 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1479 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1480 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1481 | * Return value: | |
1482 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1483 | * file on failure. | |
1484 | */ | |
1485 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1486 | { | |
1487 | struct stmmac_priv *priv = netdev_priv(dev); | |
1488 | int max_mtu; | |
1489 | ||
1490 | if (netif_running(dev)) { | |
1491 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1492 | return -EBUSY; | |
1493 | } | |
1494 | ||
48febf7e | 1495 | if (priv->plat->enh_desc) |
47dd7a54 GC |
1496 | max_mtu = JUMBO_LEN; |
1497 | else | |
45db81e1 | 1498 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 GC |
1499 | |
1500 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1501 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1502 | return -EINVAL; | |
1503 | } | |
1504 | ||
5e982f3b MM |
1505 | dev->mtu = new_mtu; |
1506 | netdev_update_features(dev); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
c8f44aff MM |
1511 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
1512 | netdev_features_t features) | |
5e982f3b MM |
1513 | { |
1514 | struct stmmac_priv *priv = netdev_priv(dev); | |
1515 | ||
38912bdb | 1516 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 1517 | features &= ~NETIF_F_RXCSUM; |
38912bdb DS |
1518 | else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) |
1519 | features &= ~NETIF_F_IPV6_CSUM; | |
5e982f3b MM |
1520 | if (!priv->plat->tx_coe) |
1521 | features &= ~NETIF_F_ALL_CSUM; | |
1522 | ||
ebbb293f GC |
1523 | /* Some GMAC devices have a bugged Jumbo frame support that |
1524 | * needs to have the Tx COE disabled for oversized frames | |
1525 | * (due to limited buffer sizes). In this case we disable | |
1526 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1527 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1528 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1529 | |
5e982f3b | 1530 | return features; |
47dd7a54 GC |
1531 | } |
1532 | ||
1533 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1534 | { | |
1535 | struct net_device *dev = (struct net_device *)dev_id; | |
1536 | struct stmmac_priv *priv = netdev_priv(dev); | |
1537 | ||
1538 | if (unlikely(!dev)) { | |
1539 | pr_err("%s: invalid dev pointer\n", __func__); | |
1540 | return IRQ_NONE; | |
1541 | } | |
1542 | ||
9dfeb4d9 | 1543 | if (priv->plat->has_gmac) |
47dd7a54 | 1544 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1545 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1546 | |
1547 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1548 | |
1549 | return IRQ_HANDLED; | |
1550 | } | |
1551 | ||
1552 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1553 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1554 | * to allow network I/O with interrupts disabled. */ | |
1555 | static void stmmac_poll_controller(struct net_device *dev) | |
1556 | { | |
1557 | disable_irq(dev->irq); | |
1558 | stmmac_interrupt(dev->irq, dev); | |
1559 | enable_irq(dev->irq); | |
1560 | } | |
1561 | #endif | |
1562 | ||
1563 | /** | |
1564 | * stmmac_ioctl - Entry point for the Ioctl | |
1565 | * @dev: Device pointer. | |
1566 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1567 | * a proprietary structure used to pass information to the driver. | |
1568 | * @cmd: IOCTL command | |
1569 | * Description: | |
1570 | * Currently there are no special functionality supported in IOCTL, just the | |
1571 | * phy_mii_ioctl(...) can be invoked. | |
1572 | */ | |
1573 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1574 | { | |
1575 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1576 | int ret; |
47dd7a54 GC |
1577 | |
1578 | if (!netif_running(dev)) | |
1579 | return -EINVAL; | |
1580 | ||
28b04113 RC |
1581 | if (!priv->phydev) |
1582 | return -EINVAL; | |
1583 | ||
28b04113 | 1584 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); |
28b04113 | 1585 | |
47dd7a54 GC |
1586 | return ret; |
1587 | } | |
1588 | ||
7ac29055 GC |
1589 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1590 | static struct dentry *stmmac_fs_dir; | |
1591 | static struct dentry *stmmac_rings_status; | |
e7434821 | 1592 | static struct dentry *stmmac_dma_cap; |
7ac29055 GC |
1593 | |
1594 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1595 | { | |
1596 | struct tmp_s { | |
1597 | u64 a; | |
1598 | unsigned int b; | |
1599 | unsigned int c; | |
1600 | }; | |
1601 | int i; | |
1602 | struct net_device *dev = seq->private; | |
1603 | struct stmmac_priv *priv = netdev_priv(dev); | |
1604 | ||
1605 | seq_printf(seq, "=======================\n"); | |
1606 | seq_printf(seq, " RX descriptor ring\n"); | |
1607 | seq_printf(seq, "=======================\n"); | |
1608 | ||
1609 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1610 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1611 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1612 | i, (unsigned int)(x->a), | |
1613 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1614 | seq_printf(seq, "\n"); | |
1615 | } | |
1616 | ||
1617 | seq_printf(seq, "\n"); | |
1618 | seq_printf(seq, "=======================\n"); | |
1619 | seq_printf(seq, " TX descriptor ring\n"); | |
1620 | seq_printf(seq, "=======================\n"); | |
1621 | ||
1622 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1623 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1624 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1625 | i, (unsigned int)(x->a), | |
1626 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1627 | seq_printf(seq, "\n"); | |
1628 | } | |
1629 | ||
1630 | return 0; | |
1631 | } | |
1632 | ||
1633 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1634 | { | |
1635 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1636 | } | |
1637 | ||
1638 | static const struct file_operations stmmac_rings_status_fops = { | |
1639 | .owner = THIS_MODULE, | |
1640 | .open = stmmac_sysfs_ring_open, | |
1641 | .read = seq_read, | |
1642 | .llseek = seq_lseek, | |
74863948 | 1643 | .release = single_release, |
7ac29055 GC |
1644 | }; |
1645 | ||
e7434821 GC |
1646 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
1647 | { | |
1648 | struct net_device *dev = seq->private; | |
1649 | struct stmmac_priv *priv = netdev_priv(dev); | |
1650 | ||
19e30c14 | 1651 | if (!priv->hw_cap_support) { |
e7434821 GC |
1652 | seq_printf(seq, "DMA HW features not supported\n"); |
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | seq_printf(seq, "==============================\n"); | |
1657 | seq_printf(seq, "\tDMA HW features\n"); | |
1658 | seq_printf(seq, "==============================\n"); | |
1659 | ||
1660 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
1661 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
1662 | seq_printf(seq, "\t1000 Mbps %s\n", | |
1663 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
1664 | seq_printf(seq, "\tHalf duple %s\n", | |
1665 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
1666 | seq_printf(seq, "\tHash Filter: %s\n", | |
1667 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
1668 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
1669 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
1670 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
1671 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
1672 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
1673 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
1674 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
1675 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
1676 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
1677 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
1678 | seq_printf(seq, "\tRMON module: %s\n", | |
1679 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
1680 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
1681 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
1682 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
1683 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
1684 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
1685 | (priv->dma_cap.eee) ? "Y" : "N"); | |
1686 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
1687 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
1688 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
1689 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
1690 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
1691 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
1692 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
1693 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
1694 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
1695 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
1696 | priv->dma_cap.number_rx_channel); | |
1697 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
1698 | priv->dma_cap.number_tx_channel); | |
1699 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
1700 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
1706 | { | |
1707 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
1708 | } | |
1709 | ||
1710 | static const struct file_operations stmmac_dma_cap_fops = { | |
1711 | .owner = THIS_MODULE, | |
1712 | .open = stmmac_sysfs_dma_cap_open, | |
1713 | .read = seq_read, | |
1714 | .llseek = seq_lseek, | |
74863948 | 1715 | .release = single_release, |
e7434821 GC |
1716 | }; |
1717 | ||
7ac29055 GC |
1718 | static int stmmac_init_fs(struct net_device *dev) |
1719 | { | |
1720 | /* Create debugfs entries */ | |
1721 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1722 | ||
1723 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1724 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1725 | STMMAC_RESOURCE_NAME); | |
1726 | ||
1727 | return -ENOMEM; | |
1728 | } | |
1729 | ||
1730 | /* Entry to report DMA RX/TX rings */ | |
1731 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1732 | S_IRUGO, stmmac_fs_dir, dev, | |
1733 | &stmmac_rings_status_fops); | |
1734 | ||
1735 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1736 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1737 | debugfs_remove(stmmac_fs_dir); | |
1738 | ||
1739 | return -ENOMEM; | |
1740 | } | |
1741 | ||
e7434821 GC |
1742 | /* Entry to report the DMA HW features */ |
1743 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
1744 | dev, &stmmac_dma_cap_fops); | |
1745 | ||
1746 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
1747 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
1748 | debugfs_remove(stmmac_rings_status); | |
1749 | debugfs_remove(stmmac_fs_dir); | |
1750 | ||
1751 | return -ENOMEM; | |
1752 | } | |
1753 | ||
7ac29055 GC |
1754 | return 0; |
1755 | } | |
1756 | ||
1757 | static void stmmac_exit_fs(void) | |
1758 | { | |
1759 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 1760 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
1761 | debugfs_remove(stmmac_fs_dir); |
1762 | } | |
1763 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1764 | ||
47dd7a54 GC |
1765 | static const struct net_device_ops stmmac_netdev_ops = { |
1766 | .ndo_open = stmmac_open, | |
1767 | .ndo_start_xmit = stmmac_xmit, | |
1768 | .ndo_stop = stmmac_release, | |
1769 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1770 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1771 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1772 | .ndo_tx_timeout = stmmac_tx_timeout, |
1773 | .ndo_do_ioctl = stmmac_ioctl, | |
1774 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1775 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1776 | .ndo_poll_controller = stmmac_poll_controller, | |
1777 | #endif | |
1778 | .ndo_set_mac_address = eth_mac_addr, | |
1779 | }; | |
1780 | ||
cf3f047b GC |
1781 | /** |
1782 | * stmmac_hw_init - Init the MAC device | |
1783 | * @priv : pointer to the private device structure. | |
1784 | * Description: this function detects which MAC device | |
1785 | * (GMAC/MAC10-100) has to attached, checks the HW capability | |
1786 | * (if supported) and sets the driver's features (for example | |
1787 | * to use the ring or chaine mode or support the normal/enh | |
1788 | * descriptor structure). | |
1789 | */ | |
1790 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
1791 | { | |
1792 | int ret = 0; | |
1793 | struct mac_device_info *mac; | |
1794 | ||
1795 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
1796 | if (priv->plat->has_gmac) { |
1797 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
cf3f047b | 1798 | mac = dwmac1000_setup(priv->ioaddr); |
03f2eecd | 1799 | } else { |
cf3f047b | 1800 | mac = dwmac100_setup(priv->ioaddr); |
03f2eecd | 1801 | } |
cf3f047b GC |
1802 | if (!mac) |
1803 | return -ENOMEM; | |
1804 | ||
1805 | priv->hw = mac; | |
1806 | ||
1807 | /* To use the chained or ring mode */ | |
1808 | priv->hw->ring = &ring_mode_ops; | |
1809 | ||
1810 | /* Get and dump the chip ID */ | |
cffb13f4 | 1811 | priv->synopsys_id = stmmac_get_synopsys_id(priv); |
cf3f047b GC |
1812 | |
1813 | /* Get the HW capability (new GMAC newer than 3.50a) */ | |
1814 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
1815 | if (priv->hw_cap_support) { | |
1816 | pr_info(" DMA HW capability register supported"); | |
1817 | ||
1818 | /* We can override some gmac/dma configuration fields: e.g. | |
1819 | * enh_desc, tx_coe (e.g. that are passed through the | |
1820 | * platform) with the values from the HW capability | |
1821 | * register (if supported). | |
1822 | */ | |
1823 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 1824 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
38912bdb DS |
1825 | |
1826 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
1827 | ||
1828 | if (priv->dma_cap.rx_coe_type2) | |
1829 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
1830 | else if (priv->dma_cap.rx_coe_type1) | |
1831 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
1832 | ||
cf3f047b GC |
1833 | } else |
1834 | pr_info(" No HW DMA feature register supported"); | |
1835 | ||
1836 | /* Select the enhnaced/normal descriptor structures */ | |
1837 | stmmac_selec_desc_mode(priv); | |
1838 | ||
38912bdb DS |
1839 | /* Enable the IPC (Checksum Offload) and check if the feature has been |
1840 | * enabled during the core configuration. */ | |
1841 | ret = priv->hw->mac->rx_ipc(priv->ioaddr); | |
1842 | if (!ret) { | |
1843 | pr_warning(" RX IPC Checksum Offload not configured.\n"); | |
1844 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; | |
1845 | } | |
1846 | ||
1847 | if (priv->plat->rx_coe) | |
1848 | pr_info(" RX Checksum Offload Engine supported (type %d)\n", | |
1849 | priv->plat->rx_coe); | |
cf3f047b GC |
1850 | if (priv->plat->tx_coe) |
1851 | pr_info(" TX Checksum insertion supported\n"); | |
1852 | ||
1853 | if (priv->plat->pmt) { | |
1854 | pr_info(" Wake-Up On Lan supported\n"); | |
1855 | device_set_wakeup_capable(priv->device, 1); | |
1856 | } | |
1857 | ||
1858 | return ret; | |
1859 | } | |
1860 | ||
47dd7a54 | 1861 | /** |
bfab27a1 GC |
1862 | * stmmac_dvr_probe |
1863 | * @device: device pointer | |
ff3dd78c GC |
1864 | * @plat_dat: platform data pointer |
1865 | * @addr: iobase memory address | |
bfab27a1 GC |
1866 | * Description: this is the main probe function used to |
1867 | * call the alloc_etherdev, allocate the priv structure. | |
47dd7a54 | 1868 | */ |
bfab27a1 | 1869 | struct stmmac_priv *stmmac_dvr_probe(struct device *device, |
cf3f047b GC |
1870 | struct plat_stmmacenet_data *plat_dat, |
1871 | void __iomem *addr) | |
47dd7a54 GC |
1872 | { |
1873 | int ret = 0; | |
bfab27a1 GC |
1874 | struct net_device *ndev = NULL; |
1875 | struct stmmac_priv *priv; | |
47dd7a54 | 1876 | |
bfab27a1 | 1877 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 1878 | if (!ndev) |
bfab27a1 | 1879 | return NULL; |
bfab27a1 GC |
1880 | |
1881 | SET_NETDEV_DEV(ndev, device); | |
1882 | ||
1883 | priv = netdev_priv(ndev); | |
1884 | priv->device = device; | |
1885 | priv->dev = ndev; | |
47dd7a54 | 1886 | |
bfab27a1 | 1887 | ether_setup(ndev); |
47dd7a54 | 1888 | |
bfab27a1 | 1889 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
1890 | priv->pause = pause; |
1891 | priv->plat = plat_dat; | |
1892 | priv->ioaddr = addr; | |
1893 | priv->dev->base_addr = (unsigned long)addr; | |
1894 | ||
1895 | /* Verify driver arguments */ | |
1896 | stmmac_verify_args(); | |
bfab27a1 | 1897 | |
cf3f047b GC |
1898 | /* Override with kernel parameters if supplied XXX CRS XXX |
1899 | * this needs to have multiple instances */ | |
1900 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1901 | priv->plat->phy_addr = phyaddr; | |
1902 | ||
1903 | /* Init MAC and get the capabilities */ | |
1904 | stmmac_hw_init(priv); | |
1905 | ||
1906 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 1907 | |
cf3f047b GC |
1908 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1909 | NETIF_F_RXCSUM; | |
bfab27a1 GC |
1910 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
1911 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
1912 | #ifdef STMMAC_VLAN_TAG_USED |
1913 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
bfab27a1 | 1914 | ndev->features |= NETIF_F_HW_VLAN_RX; |
47dd7a54 GC |
1915 | #endif |
1916 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1917 | ||
47dd7a54 GC |
1918 | if (flow_ctrl) |
1919 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1920 | ||
bfab27a1 | 1921 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 1922 | |
f8e96161 | 1923 | spin_lock_init(&priv->lock); |
a9097a96 | 1924 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 1925 | |
bfab27a1 | 1926 | ret = register_netdev(ndev); |
47dd7a54 | 1927 | if (ret) { |
cf3f047b | 1928 | pr_err("%s: ERROR %i registering the device\n", __func__, ret); |
bfab27a1 | 1929 | goto error; |
47dd7a54 GC |
1930 | } |
1931 | ||
ba1377ff | 1932 | if (stmmac_clk_get(priv)) |
31ea38ee | 1933 | pr_warning("%s: warning: cannot get CSR clock\n", __func__); |
ba1377ff | 1934 | |
cd7201f4 GC |
1935 | /* If a specific clk_csr value is passed from the platform |
1936 | * this means that the CSR Clock Range selection cannot be | |
1937 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
1938 | * set the MDC clock dynamically according to the csr actual | |
1939 | * clock input. | |
1940 | */ | |
1941 | if (!priv->plat->clk_csr) | |
1942 | stmmac_clk_csr_set(priv); | |
1943 | else | |
1944 | priv->clk_csr = priv->plat->clk_csr; | |
1945 | ||
4bfcbd7a FV |
1946 | /* MDIO bus Registration */ |
1947 | ret = stmmac_mdio_register(ndev); | |
1948 | if (ret < 0) { | |
1949 | pr_debug("%s: MDIO bus (id: %d) registration failed", | |
1950 | __func__, priv->plat->bus_id); | |
1951 | goto error; | |
1952 | } | |
1953 | ||
bfab27a1 | 1954 | return priv; |
47dd7a54 | 1955 | |
bfab27a1 GC |
1956 | error: |
1957 | netif_napi_del(&priv->napi); | |
47dd7a54 | 1958 | |
34a52f36 | 1959 | unregister_netdev(ndev); |
34a52f36 | 1960 | free_netdev(ndev); |
47dd7a54 | 1961 | |
bfab27a1 | 1962 | return NULL; |
47dd7a54 GC |
1963 | } |
1964 | ||
1965 | /** | |
1966 | * stmmac_dvr_remove | |
bfab27a1 | 1967 | * @ndev: net device pointer |
47dd7a54 | 1968 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 1969 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 1970 | */ |
bfab27a1 | 1971 | int stmmac_dvr_remove(struct net_device *ndev) |
47dd7a54 | 1972 | { |
aec7ff27 | 1973 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1974 | |
1975 | pr_info("%s:\n\tremoving driver", __func__); | |
1976 | ||
ad01b7d4 GC |
1977 | priv->hw->dma->stop_rx(priv->ioaddr); |
1978 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1979 | |
bfab27a1 | 1980 | stmmac_set_mac(priv->ioaddr, false); |
4bfcbd7a | 1981 | stmmac_mdio_unregister(ndev); |
47dd7a54 | 1982 | netif_carrier_off(ndev); |
47dd7a54 | 1983 | unregister_netdev(ndev); |
47dd7a54 GC |
1984 | free_netdev(ndev); |
1985 | ||
1986 | return 0; | |
1987 | } | |
1988 | ||
1989 | #ifdef CONFIG_PM | |
bfab27a1 | 1990 | int stmmac_suspend(struct net_device *ndev) |
47dd7a54 | 1991 | { |
874bd42d | 1992 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 | 1993 | int dis_ic = 0; |
f8c5a875 | 1994 | unsigned long flags; |
47dd7a54 | 1995 | |
874bd42d | 1996 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1997 | return 0; |
1998 | ||
102463b1 FV |
1999 | if (priv->phydev) |
2000 | phy_stop(priv->phydev); | |
2001 | ||
f8c5a875 | 2002 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 2003 | |
874bd42d GC |
2004 | netif_device_detach(ndev); |
2005 | netif_stop_queue(ndev); | |
47dd7a54 GC |
2006 | |
2007 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2008 | priv->tm->timer_stop(); |
2009 | if (likely(priv->tm->enable)) | |
2010 | dis_ic = 1; | |
47dd7a54 | 2011 | #endif |
874bd42d GC |
2012 | napi_disable(&priv->napi); |
2013 | ||
2014 | /* Stop TX/RX DMA */ | |
2015 | priv->hw->dma->stop_tx(priv->ioaddr); | |
2016 | priv->hw->dma->stop_rx(priv->ioaddr); | |
2017 | /* Clear the Rx/Tx descriptors */ | |
2018 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
2019 | dis_ic); | |
2020 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
2021 | ||
2022 | /* Enable Power down mode by programming the PMT regs */ | |
2023 | if (device_may_wakeup(priv->device)) | |
2024 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
ba1377ff | 2025 | else { |
bfab27a1 | 2026 | stmmac_set_mac(priv->ioaddr, false); |
ba1377ff GC |
2027 | /* Disable clock in case of PWM is off */ |
2028 | stmmac_clk_disable(priv); | |
2029 | } | |
f8c5a875 | 2030 | spin_unlock_irqrestore(&priv->lock, flags); |
47dd7a54 GC |
2031 | return 0; |
2032 | } | |
2033 | ||
bfab27a1 | 2034 | int stmmac_resume(struct net_device *ndev) |
47dd7a54 | 2035 | { |
874bd42d | 2036 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 2037 | unsigned long flags; |
47dd7a54 | 2038 | |
874bd42d | 2039 | if (!netif_running(ndev)) |
47dd7a54 GC |
2040 | return 0; |
2041 | ||
f8c5a875 | 2042 | spin_lock_irqsave(&priv->lock, flags); |
c4433be6 | 2043 | |
47dd7a54 GC |
2044 | /* Power Down bit, into the PM register, is cleared |
2045 | * automatically as soon as a magic packet or a Wake-up frame | |
2046 | * is received. Anyway, it's better to manually clear | |
2047 | * this bit because it can generate problems while resuming | |
2048 | * from another devices (e.g. serial console). */ | |
874bd42d | 2049 | if (device_may_wakeup(priv->device)) |
543876c9 | 2050 | priv->hw->mac->pmt(priv->ioaddr, 0); |
ba1377ff GC |
2051 | else |
2052 | /* enable the clk prevously disabled */ | |
2053 | stmmac_clk_enable(priv); | |
47dd7a54 | 2054 | |
874bd42d | 2055 | netif_device_attach(ndev); |
47dd7a54 GC |
2056 | |
2057 | /* Enable the MAC and DMA */ | |
bfab27a1 | 2058 | stmmac_set_mac(priv->ioaddr, true); |
ad01b7d4 GC |
2059 | priv->hw->dma->start_tx(priv->ioaddr); |
2060 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
2061 | |
2062 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2063 | if (likely(priv->tm->enable)) |
2064 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
2065 | #endif |
2066 | napi_enable(&priv->napi); | |
2067 | ||
874bd42d | 2068 | netif_start_queue(ndev); |
47dd7a54 | 2069 | |
f8c5a875 | 2070 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 FV |
2071 | |
2072 | if (priv->phydev) | |
2073 | phy_start(priv->phydev); | |
2074 | ||
47dd7a54 GC |
2075 | return 0; |
2076 | } | |
47dd7a54 | 2077 | |
bfab27a1 | 2078 | int stmmac_freeze(struct net_device *ndev) |
874bd42d | 2079 | { |
874bd42d GC |
2080 | if (!ndev || !netif_running(ndev)) |
2081 | return 0; | |
2082 | ||
2083 | return stmmac_release(ndev); | |
2084 | } | |
2085 | ||
bfab27a1 | 2086 | int stmmac_restore(struct net_device *ndev) |
874bd42d | 2087 | { |
874bd42d GC |
2088 | if (!ndev || !netif_running(ndev)) |
2089 | return 0; | |
2090 | ||
2091 | return stmmac_open(ndev); | |
2092 | } | |
874bd42d | 2093 | #endif /* CONFIG_PM */ |
47dd7a54 | 2094 | |
33d5e332 GC |
2095 | /* Driver can be configured w/ and w/ both PCI and Platf drivers |
2096 | * depending on the configuration selected. | |
2097 | */ | |
ba27ec66 GC |
2098 | static int __init stmmac_init(void) |
2099 | { | |
33d5e332 GC |
2100 | int err_plt = 0; |
2101 | int err_pci = 0; | |
ba27ec66 | 2102 | |
33d5e332 GC |
2103 | err_plt = stmmac_register_platform(); |
2104 | err_pci = stmmac_register_pci(); | |
ba27ec66 | 2105 | |
33d5e332 GC |
2106 | if ((err_pci) && (err_plt)) { |
2107 | pr_err("stmmac: driver registration failed\n"); | |
2108 | return -EINVAL; | |
ba27ec66 GC |
2109 | } |
2110 | ||
33d5e332 | 2111 | return 0; |
ba27ec66 GC |
2112 | } |
2113 | ||
2114 | static void __exit stmmac_exit(void) | |
2115 | { | |
33d5e332 GC |
2116 | stmmac_unregister_platform(); |
2117 | stmmac_unregister_pci(); | |
ba27ec66 GC |
2118 | } |
2119 | ||
2120 | module_init(stmmac_init); | |
2121 | module_exit(stmmac_exit); | |
2122 | ||
47dd7a54 GC |
2123 | #ifndef MODULE |
2124 | static int __init stmmac_cmdline_opt(char *str) | |
2125 | { | |
2126 | char *opt; | |
2127 | ||
2128 | if (!str || !*str) | |
2129 | return -EINVAL; | |
2130 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
2131 | if (!strncmp(opt, "debug:", 6)) { |
2132 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
2133 | goto err; | |
2134 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
2135 | if (strict_strtoul(opt + 8, 0, | |
2136 | (unsigned long *)&phyaddr)) | |
2137 | goto err; | |
2138 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
2139 | if (strict_strtoul(opt + 11, 0, | |
2140 | (unsigned long *)&dma_txsize)) | |
2141 | goto err; | |
2142 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
2143 | if (strict_strtoul(opt + 11, 0, | |
2144 | (unsigned long *)&dma_rxsize)) | |
2145 | goto err; | |
2146 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
2147 | if (strict_strtoul(opt + 7, 0, | |
2148 | (unsigned long *)&buf_sz)) | |
2149 | goto err; | |
2150 | } else if (!strncmp(opt, "tc:", 3)) { | |
2151 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
2152 | goto err; | |
2153 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
2154 | if (strict_strtoul(opt + 9, 0, | |
2155 | (unsigned long *)&watchdog)) | |
2156 | goto err; | |
2157 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
2158 | if (strict_strtoul(opt + 10, 0, | |
2159 | (unsigned long *)&flow_ctrl)) | |
2160 | goto err; | |
2161 | } else if (!strncmp(opt, "pause:", 6)) { | |
2162 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2163 | goto err; | |
47dd7a54 | 2164 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2165 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2166 | if (strict_strtoul(opt + 7, 0, | |
2167 | (unsigned long *)&tmrate)) | |
2168 | goto err; | |
47dd7a54 | 2169 | #endif |
f3240e28 | 2170 | } |
47dd7a54 GC |
2171 | } |
2172 | return 0; | |
f3240e28 GC |
2173 | |
2174 | err: | |
2175 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2176 | return -EINVAL; | |
47dd7a54 GC |
2177 | } |
2178 | ||
2179 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2180 | #endif | |
6fc0d0f2 GC |
2181 | |
2182 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); | |
2183 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2184 | MODULE_LICENSE("GPL"); |