]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
stmmac: fix and better tune the default buffer sizes
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
286a8372 5 Copyright(C) 2007-2011 STMicroelectronics Ltd
47dd7a54
GC		 6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29*******************************************************************************/
30
6a81c26f 31#include <linux/clk.h>
47dd7a54
GC		 32#include <linux/kernel.h>
33#include <linux/interrupt.h>
47dd7a54
GC		 34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/skbuff.h>
37#include <linux/ethtool.h>
38#include <linux/if_ether.h>
39#include <linux/crc32.h>
40#include <linux/mii.h>
01789349 41#include <linux/if.h>
47dd7a54
GC		 42#include <linux/if_vlan.h>
43#include <linux/dma-mapping.h>
5a0e3ad6 44#include <linux/slab.h>
70c71606 45#include <linux/prefetch.h>
db88f10a 46#include <linux/pinctrl/consumer.h>
7ac29055
GC		 47#ifdef CONFIG_STMMAC_DEBUG_FS
48#include <linux/debugfs.h>
49#include <linux/seq_file.h>
ceb69499 50#endif /* CONFIG_STMMAC_DEBUG_FS */
891434b1
RK		 51#include <linux/net_tstamp.h>
52#include "stmmac_ptp.h"
286a8372 53#include "stmmac.h"
c5e4ddbd 54#include <linux/reset.h>
47dd7a54 55
47dd7a54 56#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
47dd7a54
GC		 57
58/* Module parameters */
32ceabca 59#define TX_TIMEO 5000
47dd7a54
GC		 60static int watchdog = TX_TIMEO;
61module_param(watchdog, int, S_IRUGO | S_IWUSR);
32ceabca 62MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
47dd7a54 63
32ceabca 64static int debug = -1;
47dd7a54 65module_param(debug, int, S_IRUGO | S_IWUSR);
32ceabca 66MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
47dd7a54 67
47d1f71f 68static int phyaddr = -1;
47dd7a54
GC		 69module_param(phyaddr, int, S_IRUGO);
70MODULE_PARM_DESC(phyaddr, "Physical device address");
71
72#define DMA_TX_SIZE 256
73static int dma_txsize = DMA_TX_SIZE;
74module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
75MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
76
77#define DMA_RX_SIZE 256
78static int dma_rxsize = DMA_RX_SIZE;
79module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
80MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
81
82static int flow_ctrl = FLOW_OFF;
83module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
84MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
85
86static int pause = PAUSE_TIME;
87module_param(pause, int, S_IRUGO | S_IWUSR);
88MODULE_PARM_DESC(pause, "Flow Control Pause Time");
89
90#define TC_DEFAULT 64
91static int tc = TC_DEFAULT;
92module_param(tc, int, S_IRUGO | S_IWUSR);
93MODULE_PARM_DESC(tc, "DMA threshold control value");
94
d916701c
GC		 95#define DEFAULT_BUFSIZE 1536
96static int buf_sz = DEFAULT_BUFSIZE;
47dd7a54
GC		 97module_param(buf_sz, int, S_IRUGO | S_IWUSR);
98MODULE_PARM_DESC(buf_sz, "DMA buffer size");
99
47dd7a54
GC		 100static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
101 NETIF_MSG_LINK | NETIF_MSG_IFUP |
102 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
103
d765955d
GC		 104#define STMMAC_DEFAULT_LPI_TIMER 1000
105static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
106module_param(eee_timer, int, S_IRUGO | S_IWUSR);
107MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
f5351ef7 108#define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
d765955d 109
4a7d666a
GC		 110/* By default the driver will use the ring mode to manage tx and rx descriptors
111 * but passing this value so user can force to use the chain instead of the ring
112 */
113static unsigned int chain_mode;
114module_param(chain_mode, int, S_IRUGO);
115MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
116
47dd7a54 117static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
47dd7a54 118
bfab27a1
GC		 119#ifdef CONFIG_STMMAC_DEBUG_FS
120static int stmmac_init_fs(struct net_device *dev);
121static void stmmac_exit_fs(void);
122#endif
123
9125cdd1
GC		 124#define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125
47dd7a54
GC		 126/**
127 * stmmac_verify_args - verify the driver parameters.
128 * Description: it verifies if some wrong parameter is passed to the driver.
129 * Note that wrong parameters are replaced with the default values.
130 */
131static void stmmac_verify_args(void)
132{
133 if (unlikely(watchdog < 0))
134 watchdog = TX_TIMEO;
135 if (unlikely(dma_rxsize < 0))
136 dma_rxsize = DMA_RX_SIZE;
137 if (unlikely(dma_txsize < 0))
138 dma_txsize = DMA_TX_SIZE;
d916701c
GC		 139 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
140 buf_sz = DEFAULT_BUFSIZE;
47dd7a54
GC		 141 if (unlikely(flow_ctrl > 1))
142 flow_ctrl = FLOW_AUTO;
143 else if (likely(flow_ctrl < 0))
144 flow_ctrl = FLOW_OFF;
145 if (unlikely((pause < 0) || (pause > 0xffff)))
146 pause = PAUSE_TIME;
d765955d
GC		 147 if (eee_timer < 0)
148 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
47dd7a54
GC		 149}
150
32ceabca
GC		 151/**
152 * stmmac_clk_csr_set - dynamically set the MDC clock
153 * @priv: driver private structure
154 * Description: this is to dynamically set the MDC clock according to the csr
155 * clock input.
156 * Note:
157 * If a specific clk_csr value is passed from the platform
158 * this means that the CSR Clock Range selection cannot be
159 * changed at run-time and it is fixed (as reported in the driver
160 * documentation). Viceversa the driver will try to set the MDC
161 * clock dynamically according to the actual clock input.
162 */
cd7201f4
GC		 163static void stmmac_clk_csr_set(struct stmmac_priv *priv)
164{
cd7201f4
GC		 165 u32 clk_rate;
166
167 clk_rate = clk_get_rate(priv->stmmac_clk);
168
169 /* Platform provided default clk_csr would be assumed valid
ceb69499
GC		 170 * for all other cases except for the below mentioned ones.
171 * For values higher than the IEEE 802.3 specified frequency
172 * we can not estimate the proper divider as it is not known
173 * the frequency of clk_csr_i. So we do not change the default
174 * divider.
175 */
cd7201f4
GC		 176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
177 if (clk_rate < CSR_F_35M)
178 priv->clk_csr = STMMAC_CSR_20_35M;
179 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
180 priv->clk_csr = STMMAC_CSR_35_60M;
181 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
182 priv->clk_csr = STMMAC_CSR_60_100M;
183 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
184 priv->clk_csr = STMMAC_CSR_100_150M;
185 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
186 priv->clk_csr = STMMAC_CSR_150_250M;
187 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
188 priv->clk_csr = STMMAC_CSR_250_300M;
ceb69499 189 }
cd7201f4
GC		 190}
191
47dd7a54
GC		 192static void print_pkt(unsigned char *buf, int len)
193{
194 int j;
83d7af64 195 pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
47dd7a54
GC		 196 for (j = 0; j < len; j++) {
197 if ((j % 16) == 0)
83d7af64
GC		 198 pr_debug("\n %03x:", j);
199 pr_debug(" %02x", buf[j]);
47dd7a54 200 }
83d7af64 201 pr_debug("\n");
47dd7a54 202}
47dd7a54
GC		 203
204/* minimum number of free TX descriptors required to wake up TX process */
205#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
206
207static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
208{
209 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
210}
211
32ceabca
GC		 212/**
213 * stmmac_hw_fix_mac_speed: callback for speed selection
214 * @priv: driver private structure
215 * Description: on some platforms (e.g. ST), some HW system configuraton
216 * registers have to be set according to the link speed negotiated.
9dfeb4d9
GC		 217 */
218static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
219{
220 struct phy_device *phydev = priv->phydev;
221
222 if (likely(priv->plat->fix_mac_speed))
ceb69499 223 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
9dfeb4d9
GC		 224}
225
32ceabca
GC		 226/**
227 * stmmac_enable_eee_mode: Check and enter in LPI mode
228 * @priv: driver private structure
229 * Description: this function is to verify and enter in LPI mode for EEE.
230 */
d765955d
GC		 231static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
232{
233 /* Check and enter in LPI mode */
234 if ((priv->dirty_tx == priv->cur_tx) &&
235 (priv->tx_path_in_lpi_mode == false))
236 priv->hw->mac->set_eee_mode(priv->ioaddr);
237}
238
32ceabca
GC		 239/**
240 * stmmac_disable_eee_mode: disable/exit from EEE
241 * @priv: driver private structure
242 * Description: this function is to exit and disable EEE in case of
243 * LPI state is true. This is called by the xmit.
244 */
d765955d
GC		 245void stmmac_disable_eee_mode(struct stmmac_priv *priv)
246{
d765955d
GC		 247 priv->hw->mac->reset_eee_mode(priv->ioaddr);
248 del_timer_sync(&priv->eee_ctrl_timer);
249 priv->tx_path_in_lpi_mode = false;
250}
251
252/**
32ceabca 253 * stmmac_eee_ctrl_timer: EEE TX SW timer.
d765955d
GC		 254 * @arg : data hook
255 * Description:
32ceabca 256 * if there is no data transfer and if we are not in LPI state,
d765955d
GC		 257 * then MAC Transmitter can be moved to LPI state.
258 */
259static void stmmac_eee_ctrl_timer(unsigned long arg)
260{
261 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
262
263 stmmac_enable_eee_mode(priv);
f5351ef7 264 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d
GC		 265}
266
267/**
32ceabca
GC		 268 * stmmac_eee_init: init EEE
269 * @priv: driver private structure
d765955d
GC		 270 * Description:
271 * If the EEE support has been enabled while configuring the driver,
272 * if the GMAC actually supports the EEE (from the HW cap reg) and the
273 * phy can also manage EEE, so enable the LPI state and start the timer
274 * to verify if the tx path can enter in LPI state.
275 */
276bool stmmac_eee_init(struct stmmac_priv *priv)
277{
278 bool ret = false;
279
f5351ef7
GC		 280 /* Using PCS we cannot dial with the phy registers at this stage
281 * so we do not support extra feature like EEE.
282 */
283 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
284 (priv->pcs == STMMAC_PCS_RTBI))
285 goto out;
286
d765955d
GC		 287 /* MAC core supports the EEE feature. */
288 if (priv->dma_cap.eee) {
83bf79b6
GC		 289 int tx_lpi_timer = priv->tx_lpi_timer;
290
d765955d 291 /* Check if the PHY supports EEE */
83bf79b6
GC		 292 if (phy_init_eee(priv->phydev, 1)) {
293 /* To manage at run-time if the EEE cannot be supported
294 * anymore (for example because the lp caps have been
295 * changed).
296 * In that case the driver disable own timers.
297 */
298 if (priv->eee_active) {
299 pr_debug("stmmac: disable EEE\n");
300 del_timer_sync(&priv->eee_ctrl_timer);
301 priv->hw->mac->set_eee_timer(priv->ioaddr, 0,
302 tx_lpi_timer);
303 }
304 priv->eee_active = 0;
d765955d 305 goto out;
83bf79b6
GC		 306 }
307 /* Activate the EEE and start timers */
f5351ef7
GC		 308 if (!priv->eee_active) {
309 priv->eee_active = 1;
310 init_timer(&priv->eee_ctrl_timer);
311 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
312 priv->eee_ctrl_timer.data = (unsigned long)priv;
313 priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
314 add_timer(&priv->eee_ctrl_timer);
315
316 priv->hw->mac->set_eee_timer(priv->ioaddr,
317 STMMAC_DEFAULT_LIT_LS,
83bf79b6 318 tx_lpi_timer);
f5351ef7
GC		 319 } else
320 /* Set HW EEE according to the speed */
321 priv->hw->mac->set_eee_pls(priv->ioaddr,
322 priv->phydev->link);
d765955d 323
83bf79b6 324 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
d765955d
GC		 325
326 ret = true;
327 }
328out:
329 return ret;
330}
331
32ceabca
GC		 332/* stmmac_get_tx_hwtstamp: get HW TX timestamps
333 * @priv: driver private structure
891434b1
RK		 334 * @entry : descriptor index to be used.
335 * @skb : the socket buffer
336 * Description :
337 * This function will read timestamp from the descriptor & pass it to stack.
338 * and also perform some sanity checks.
339 */
340static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
ceb69499 341 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 342{
343 struct skb_shared_hwtstamps shhwtstamp;
344 u64 ns;
345 void *desc = NULL;
346
347 if (!priv->hwts_tx_en)
348 return;
349
ceb69499 350 /* exit if skb doesn't support hw tstamp */
75e4364f 351 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
891434b1
RK		 352 return;
353
354 if (priv->adv_ts)
355 desc = (priv->dma_etx + entry);
356 else
357 desc = (priv->dma_tx + entry);
358
359 /* check tx tstamp status */
360 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
361 return;
362
363 /* get the valid tstamp */
364 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
365
366 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
367 shhwtstamp.hwtstamp = ns_to_ktime(ns);
368 /* pass tstamp to stack */
369 skb_tstamp_tx(skb, &shhwtstamp);
370
371 return;
372}
373
32ceabca
GC		 374/* stmmac_get_rx_hwtstamp: get HW RX timestamps
375 * @priv: driver private structure
891434b1
RK		 376 * @entry : descriptor index to be used.
377 * @skb : the socket buffer
378 * Description :
379 * This function will read received packet's timestamp from the descriptor
380 * and pass it to stack. It also perform some sanity checks.
381 */
382static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
ceb69499 383 unsigned int entry, struct sk_buff *skb)
891434b1
RK		 384{
385 struct skb_shared_hwtstamps *shhwtstamp = NULL;
386 u64 ns;
387 void *desc = NULL;
388
389 if (!priv->hwts_rx_en)
390 return;
391
392 if (priv->adv_ts)
393 desc = (priv->dma_erx + entry);
394 else
395 desc = (priv->dma_rx + entry);
396
ceb69499 397 /* exit if rx tstamp is not valid */
891434b1
RK		 398 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
399 return;
400
401 /* get valid tstamp */
402 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
403 shhwtstamp = skb_hwtstamps(skb);
404 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
405 shhwtstamp->hwtstamp = ns_to_ktime(ns);
406}
407
408/**
409 * stmmac_hwtstamp_ioctl - control hardware timestamping.
410 * @dev: device pointer.
411 * @ifr: An IOCTL specefic structure, that can contain a pointer to
412 * a proprietary structure used to pass information to the driver.
413 * Description:
414 * This function configures the MAC to enable/disable both outgoing(TX)
415 * and incoming(RX) packets time stamping based on user input.
416 * Return Value:
417 * 0 on success and an appropriate -ve integer on failure.
418 */
419static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
420{
421 struct stmmac_priv *priv = netdev_priv(dev);
422 struct hwtstamp_config config;
423 struct timespec now;
424 u64 temp = 0;
425 u32 ptp_v2 = 0;
426 u32 tstamp_all = 0;
427 u32 ptp_over_ipv4_udp = 0;
428 u32 ptp_over_ipv6_udp = 0;
429 u32 ptp_over_ethernet = 0;
430 u32 snap_type_sel = 0;
431 u32 ts_master_en = 0;
432 u32 ts_event_en = 0;
433 u32 value = 0;
434
435 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
436 netdev_alert(priv->dev, "No support for HW time stamping\n");
437 priv->hwts_tx_en = 0;
438 priv->hwts_rx_en = 0;
439
440 return -EOPNOTSUPP;
441 }
442
443 if (copy_from_user(&config, ifr->ifr_data,
ceb69499 444 sizeof(struct hwtstamp_config)))
891434b1
RK		 445 return -EFAULT;
446
447 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
448 __func__, config.flags, config.tx_type, config.rx_filter);
449
450 /* reserved for future extensions */
451 if (config.flags)
452 return -EINVAL;
453
5f3da328
BH		 454 if (config.tx_type != HWTSTAMP_TX_OFF &&
455 config.tx_type != HWTSTAMP_TX_ON)
891434b1 456 return -ERANGE;
891434b1
RK		 457
458 if (priv->adv_ts) {
459 switch (config.rx_filter) {
891434b1 460 case HWTSTAMP_FILTER_NONE:
ceb69499 461 /* time stamp no incoming packet at all */
891434b1
RK		 462 config.rx_filter = HWTSTAMP_FILTER_NONE;
463 break;
464
891434b1 465 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
ceb69499 466 /* PTP v1, UDP, any kind of event packet */
891434b1
RK		 467 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
468 /* take time stamp for all event messages */
469 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
470
471 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
472 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
473 break;
474
891434b1 475 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
ceb69499 476 /* PTP v1, UDP, Sync packet */
891434b1
RK		 477 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
478 /* take time stamp for SYNC messages only */
479 ts_event_en = PTP_TCR_TSEVNTENA;
480
481 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
482 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
483 break;
484
891434b1 485 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
ceb69499 486 /* PTP v1, UDP, Delay_req packet */
891434b1
RK		 487 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
488 /* take time stamp for Delay_Req messages only */
489 ts_master_en = PTP_TCR_TSMSTRENA;
490 ts_event_en = PTP_TCR_TSEVNTENA;
491
492 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
493 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
494 break;
495
891434b1 496 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
ceb69499 497 /* PTP v2, UDP, any kind of event packet */
891434b1
RK		 498 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
499 ptp_v2 = PTP_TCR_TSVER2ENA;
500 /* take time stamp for all event messages */
501 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
502
503 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
504 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
505 break;
506
891434b1 507 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
ceb69499 508 /* PTP v2, UDP, Sync packet */
891434b1
RK		 509 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
510 ptp_v2 = PTP_TCR_TSVER2ENA;
511 /* take time stamp for SYNC messages only */
512 ts_event_en = PTP_TCR_TSEVNTENA;
513
514 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
515 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
516 break;
517
891434b1 518 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
ceb69499 519 /* PTP v2, UDP, Delay_req packet */
891434b1
RK		 520 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
521 ptp_v2 = PTP_TCR_TSVER2ENA;
522 /* take time stamp for Delay_Req messages only */
523 ts_master_en = PTP_TCR_TSMSTRENA;
524 ts_event_en = PTP_TCR_TSEVNTENA;
525
526 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
527 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
528 break;
529
891434b1 530 case HWTSTAMP_FILTER_PTP_V2_EVENT:
ceb69499 531 /* PTP v2/802.AS1 any layer, any kind of event packet */
891434b1
RK		 532 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
533 ptp_v2 = PTP_TCR_TSVER2ENA;
534 /* take time stamp for all event messages */
535 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
536
537 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
538 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
539 ptp_over_ethernet = PTP_TCR_TSIPENA;
540 break;
541
891434b1 542 case HWTSTAMP_FILTER_PTP_V2_SYNC:
ceb69499 543 /* PTP v2/802.AS1, any layer, Sync packet */
891434b1
RK		 544 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
545 ptp_v2 = PTP_TCR_TSVER2ENA;
546 /* take time stamp for SYNC messages only */
547 ts_event_en = PTP_TCR_TSEVNTENA;
548
549 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
550 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
551 ptp_over_ethernet = PTP_TCR_TSIPENA;
552 break;
553
891434b1 554 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
ceb69499 555 /* PTP v2/802.AS1, any layer, Delay_req packet */
891434b1
RK		 556 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
557 ptp_v2 = PTP_TCR_TSVER2ENA;
558 /* take time stamp for Delay_Req messages only */
559 ts_master_en = PTP_TCR_TSMSTRENA;
560 ts_event_en = PTP_TCR_TSEVNTENA;
561
562 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
563 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
564 ptp_over_ethernet = PTP_TCR_TSIPENA;
565 break;
566
891434b1 567 case HWTSTAMP_FILTER_ALL:
ceb69499 568 /* time stamp any incoming packet */
891434b1
RK		 569 config.rx_filter = HWTSTAMP_FILTER_ALL;
570 tstamp_all = PTP_TCR_TSENALL;
571 break;
572
573 default:
574 return -ERANGE;
575 }
576 } else {
577 switch (config.rx_filter) {
578 case HWTSTAMP_FILTER_NONE:
579 config.rx_filter = HWTSTAMP_FILTER_NONE;
580 break;
581 default:
582 /* PTP v1, UDP, any kind of event packet */
583 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
584 break;
585 }
586 }
587 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
5f3da328 588 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
891434b1
RK		 589
590 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
591 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
592 else {
593 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
ceb69499
GC		 594 tstamp_all | ptp_v2 | ptp_over_ethernet |
595 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
596 ts_master_en | snap_type_sel);
891434b1
RK		 597
598 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
599
600 /* program Sub Second Increment reg */
601 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
602
603 /* calculate default added value:
604 * formula is :
605 * addend = (2^32)/freq_div_ratio;
606 * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
607 * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
608 * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
609 * achive 20ns accuracy.
610 *
611 * 2^x * y == (y << x), hence
612 * 2^32 * 50000000 ==> (50000000 << 32)
613 */
ceb69499 614 temp = (u64) (50000000ULL << 32);
891434b1
RK		 615 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
616 priv->hw->ptp->config_addend(priv->ioaddr,
617 priv->default_addend);
618
619 /* initialize system time */
620 getnstimeofday(&now);
621 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
622 now.tv_nsec);
623 }
624
625 return copy_to_user(ifr->ifr_data, &config,
626 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
627}
628
32ceabca
GC		 629/**
630 * stmmac_init_ptp: init PTP
631 * @priv: driver private structure
632 * Description: this is to verify if the HW supports the PTPv1 or v2.
633 * This is done by looking at the HW cap. register.
634 * Also it registers the ptp driver.
635 */
92ba6888 636static int stmmac_init_ptp(struct stmmac_priv *priv)
891434b1 637{
92ba6888
RK		 638 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
639 return -EOPNOTSUPP;
640
7cd01399
VB		 641 priv->adv_ts = 0;
642 if (priv->dma_cap.atime_stamp && priv->extend_desc)
643 priv->adv_ts = 1;
644
645 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
646 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
647
648 if (netif_msg_hw(priv) && priv->adv_ts)
649 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
891434b1
RK		 650
651 priv->hw->ptp = &stmmac_ptp;
652 priv->hwts_tx_en = 0;
653 priv->hwts_rx_en = 0;
92ba6888
RK		 654
655 return stmmac_ptp_register(priv);
656}
657
658static void stmmac_release_ptp(struct stmmac_priv *priv)
659{
660 stmmac_ptp_unregister(priv);
891434b1
RK		 661}
662
47dd7a54
GC		 663/**
664 * stmmac_adjust_link
665 * @dev: net device structure
666 * Description: it adjusts the link parameters.
667 */
668static void stmmac_adjust_link(struct net_device *dev)
669{
670 struct stmmac_priv *priv = netdev_priv(dev);
671 struct phy_device *phydev = priv->phydev;
47dd7a54
GC		 672 unsigned long flags;
673 int new_state = 0;
674 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
675
676 if (phydev == NULL)
677 return;
678
47dd7a54 679 spin_lock_irqsave(&priv->lock, flags);
d765955d 680
47dd7a54 681 if (phydev->link) {
ad01b7d4 682 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 683
684 /* Now we make sure that we can be in full duplex mode.
685 * If not, we operate in half-duplex mode. */
686 if (phydev->duplex != priv->oldduplex) {
687 new_state = 1;
688 if (!(phydev->duplex))
db98a0b0 689 ctrl &= ~priv->hw->link.duplex;
47dd7a54 690 else
db98a0b0 691 ctrl |= priv->hw->link.duplex;
47dd7a54
GC		 692 priv->oldduplex = phydev->duplex;
693 }
694 /* Flow Control operation */
695 if (phydev->pause)
ad01b7d4 696 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
db98a0b0 697 fc, pause_time);
47dd7a54
GC		 698
699 if (phydev->speed != priv->speed) {
700 new_state = 1;
701 switch (phydev->speed) {
702 case 1000:
9dfeb4d9 703 if (likely(priv->plat->has_gmac))
db98a0b0 704 ctrl &= ~priv->hw->link.port;
ceb69499 705 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 706 break;
707 case 100:
708 case 10:
9dfeb4d9 709 if (priv->plat->has_gmac) {
db98a0b0 710 ctrl |= priv->hw->link.port;
47dd7a54 711 if (phydev->speed == SPEED_100) {
db98a0b0 712 ctrl |= priv->hw->link.speed;
47dd7a54 713 } else {
db98a0b0 714 ctrl &= ~(priv->hw->link.speed);
47dd7a54
GC		 715 }
716 } else {
db98a0b0 717 ctrl &= ~priv->hw->link.port;
47dd7a54 718 }
9dfeb4d9 719 stmmac_hw_fix_mac_speed(priv);
47dd7a54
GC		 720 break;
721 default:
722 if (netif_msg_link(priv))
ceb69499
GC		 723 pr_warn("%s: Speed (%d) not 10/100\n",
724 dev->name, phydev->speed);
47dd7a54
GC		 725 break;
726 }
727
728 priv->speed = phydev->speed;
729 }
730
ad01b7d4 731 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
47dd7a54
GC		 732
733 if (!priv->oldlink) {
734 new_state = 1;
735 priv->oldlink = 1;
736 }
737 } else if (priv->oldlink) {
738 new_state = 1;
739 priv->oldlink = 0;
740 priv->speed = 0;
741 priv->oldduplex = -1;
742 }
743
744 if (new_state && netif_msg_link(priv))
745 phy_print_status(phydev);
746
f5351ef7
GC		 747 /* At this stage, it could be needed to setup the EEE or adjust some
748 * MAC related HW registers.
749 */
750 priv->eee_enabled = stmmac_eee_init(priv);
d765955d 751
47dd7a54 752 spin_unlock_irqrestore(&priv->lock, flags);
47dd7a54
GC		 753}
754
32ceabca
GC		 755/**
756 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
757 * @priv: driver private structure
758 * Description: this is to verify if the HW supports the PCS.
759 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
760 * configured for the TBI, RTBI, or SGMII PHY interface.
761 */
e58bb43f
GC		 762static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
763{
764 int interface = priv->plat->interface;
765
766 if (priv->dma_cap.pcs) {
0d909dcd
BA		 767 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
768 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
769 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
770 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
e58bb43f
GC		 771 pr_debug("STMMAC: PCS RGMII support enable\n");
772 priv->pcs = STMMAC_PCS_RGMII;
0d909dcd 773 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
e58bb43f
GC		 774 pr_debug("STMMAC: PCS SGMII support enable\n");
775 priv->pcs = STMMAC_PCS_SGMII;
776 }
777 }
778}
779
47dd7a54
GC		 780/**
781 * stmmac_init_phy - PHY initialization
782 * @dev: net device structure
783 * Description: it initializes the driver's PHY state, and attaches the PHY
784 * to the mac driver.
785 * Return value:
786 * 0 on success
787 */
788static int stmmac_init_phy(struct net_device *dev)
789{
790 struct stmmac_priv *priv = netdev_priv(dev);
791 struct phy_device *phydev;
d765955d 792 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
109cdd66 793 char bus_id[MII_BUS_ID_SIZE];
79ee1dc3 794 int interface = priv->plat->interface;
9cbadf09 795 int max_speed = priv->plat->max_speed;
47dd7a54
GC		 796 priv->oldlink = 0;
797 priv->speed = 0;
798 priv->oldduplex = -1;
799
f142af2e
SK		 800 if (priv->plat->phy_bus_name)
801 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
ceb69499 802 priv->plat->phy_bus_name, priv->plat->bus_id);
f142af2e
SK		 803 else
804 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
ceb69499 805 priv->plat->bus_id);
f142af2e 806
d765955d 807 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
36bcfe7d 808 priv->plat->phy_addr);
d765955d 809 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt);
47dd7a54 810
f9a8f83b 811 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
47dd7a54
GC		 812
813 if (IS_ERR(phydev)) {
814 pr_err("%s: Could not attach to PHY\n", dev->name);
815 return PTR_ERR(phydev);
816 }
817
79ee1dc3 818 /* Stop Advertising 1000BASE Capability if interface is not GMII */
c5b9b4e4 819 if ((interface == PHY_INTERFACE_MODE_MII) ||
9cbadf09
SK		 820 (interface == PHY_INTERFACE_MODE_RMII) ||
821 (max_speed < 1000 && max_speed > 0))
c5b9b4e4
SK		 822 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
823 SUPPORTED_1000baseT_Full);
79ee1dc3 824
47dd7a54
GC		 825 /*
826 * Broken HW is sometimes missing the pull-up resistor on the
827 * MDIO line, which results in reads to non-existent devices returning
828 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
829 * device as well.
830 * Note: phydev->phy_id is the result of reading the UID PHY registers.
831 */
832 if (phydev->phy_id == 0) {
833 phy_disconnect(phydev);
834 return -ENODEV;
835 }
836 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
36bcfe7d 837 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
47dd7a54
GC		 838
839 priv->phydev = phydev;
840
841 return 0;
842}
843
47dd7a54 844/**
32ceabca
GC		 845 * stmmac_display_ring: display ring
846 * @head: pointer to the head of the ring passed.
47dd7a54 847 * @size: size of the ring.
32ceabca 848 * @extend_desc: to verify if extended descriptors are used.
c24602ef 849 * Description: display the control/status and buffer descriptors.
47dd7a54 850 */
c24602ef 851static void stmmac_display_ring(void *head, int size, int extend_desc)
47dd7a54 852{
47dd7a54 853 int i;
ceb69499
GC		 854 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
855 struct dma_desc *p = (struct dma_desc *)head;
c24602ef 856
47dd7a54 857 for (i = 0; i < size; i++) {
c24602ef
GC		 858 u64 x;
859 if (extend_desc) {
860 x = *(u64 *) ep;
861 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 862 i, (unsigned int)virt_to_phys(ep),
863 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 864 ep->basic.des2, ep->basic.des3);
865 ep++;
866 } else {
867 x = *(u64 *) p;
868 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
ceb69499
GC		 869 i, (unsigned int)virt_to_phys(p),
870 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 871 p->des2, p->des3);
872 p++;
873 }
47dd7a54
GC		 874 pr_info("\n");
875 }
876}
877
c24602ef
GC		 878static void stmmac_display_rings(struct stmmac_priv *priv)
879{
880 unsigned int txsize = priv->dma_tx_size;
881 unsigned int rxsize = priv->dma_rx_size;
882
883 if (priv->extend_desc) {
884 pr_info("Extended RX descriptor ring:\n");
ceb69499 885 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef 886 pr_info("Extended TX descriptor ring:\n");
ceb69499 887 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
c24602ef
GC		 888 } else {
889 pr_info("RX descriptor ring:\n");
890 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
891 pr_info("TX descriptor ring:\n");
892 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
893 }
894}
895
286a8372
GC		 896static int stmmac_set_bfsize(int mtu, int bufsize)
897{
898 int ret = bufsize;
899
900 if (mtu >= BUF_SIZE_4KiB)
901 ret = BUF_SIZE_8KiB;
902 else if (mtu >= BUF_SIZE_2KiB)
903 ret = BUF_SIZE_4KiB;
d916701c 904 else if (mtu > DEFAULT_BUFSIZE)
286a8372
GC		 905 ret = BUF_SIZE_2KiB;
906 else
d916701c 907 ret = DEFAULT_BUFSIZE;
286a8372
GC		 908
909 return ret;
910}
911
32ceabca
GC		 912/**
913 * stmmac_clear_descriptors: clear descriptors
914 * @priv: driver private structure
915 * Description: this function is called to clear the tx and rx descriptors
916 * in case of both basic and extended descriptors are used.
917 */
c24602ef
GC		 918static void stmmac_clear_descriptors(struct stmmac_priv *priv)
919{
920 int i;
921 unsigned int txsize = priv->dma_tx_size;
922 unsigned int rxsize = priv->dma_rx_size;
923
924 /* Clear the Rx/Tx descriptors */
925 for (i = 0; i < rxsize; i++)
926 if (priv->extend_desc)
927 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
928 priv->use_riwt, priv->mode,
929 (i == rxsize - 1));
930 else
931 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
932 priv->use_riwt, priv->mode,
933 (i == rxsize - 1));
934 for (i = 0; i < txsize; i++)
935 if (priv->extend_desc)
936 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
937 priv->mode,
938 (i == txsize - 1));
939 else
940 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
941 priv->mode,
942 (i == txsize - 1));
943}
944
945static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
946 int i)
947{
948 struct sk_buff *skb;
949
950 skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
951 GFP_KERNEL);
56329137 952 if (!skb) {
c24602ef 953 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
56329137 954 return -ENOMEM;
c24602ef
GC		 955 }
956 skb_reserve(skb, NET_IP_ALIGN);
957 priv->rx_skbuff[i] = skb;
958 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
959 priv->dma_buf_sz,
960 DMA_FROM_DEVICE);
56329137
BZ		 961 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
962 pr_err("%s: DMA mapping error\n", __func__);
963 dev_kfree_skb_any(skb);
964 return -EINVAL;
965 }
c24602ef
GC		 966
967 p->des2 = priv->rx_skbuff_dma[i];
968
969 if ((priv->mode == STMMAC_RING_MODE) &&
970 (priv->dma_buf_sz == BUF_SIZE_16KiB))
971 priv->hw->ring->init_desc3(p);
972
973 return 0;
974}
975
56329137
BZ		 976static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
977{
978 if (priv->rx_skbuff[i]) {
979 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
980 priv->dma_buf_sz, DMA_FROM_DEVICE);
981 dev_kfree_skb_any(priv->rx_skbuff[i]);
982 }
983 priv->rx_skbuff[i] = NULL;
984}
985
47dd7a54
GC		 986/**
987 * init_dma_desc_rings - init the RX/TX descriptor rings
988 * @dev: net device structure
989 * Description: this function initializes the DMA RX/TX descriptors
286a8372
GC		 990 * and allocates the socket buffers. It suppors the chained and ring
991 * modes.
47dd7a54 992 */
56329137 993static int init_dma_desc_rings(struct net_device *dev)
47dd7a54
GC		 994{
995 int i;
996 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 997 unsigned int txsize = priv->dma_tx_size;
998 unsigned int rxsize = priv->dma_rx_size;
4a7d666a 999 unsigned int bfsize = 0;
56329137 1000 int ret = -ENOMEM;
47dd7a54 1001
286a8372 1002 /* Set the max buffer size according to the DESC mode
ceb69499
GC		 1003 * and the MTU. Note that RING mode allows 16KiB bsize.
1004 */
4a7d666a
GC		 1005 if (priv->mode == STMMAC_RING_MODE)
1006 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
286a8372 1007
4a7d666a 1008 if (bfsize < BUF_SIZE_16KiB)
286a8372 1009 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
47dd7a54 1010
2618abb7
VB		 1011 priv->dma_buf_sz = bfsize;
1012
83d7af64
GC		 1013 if (netif_msg_probe(priv))
1014 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1015 txsize, rxsize, bfsize);
47dd7a54 1016
83d7af64 1017 if (netif_msg_probe(priv)) {
c24602ef
GC		 1018 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1019 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
47dd7a54 1020
83d7af64
GC		 1021 /* RX INITIALIZATION */
1022 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1023 }
47dd7a54 1024 for (i = 0; i < rxsize; i++) {
c24602ef
GC		 1025 struct dma_desc *p;
1026 if (priv->extend_desc)
1027 p = &((priv->dma_erx + i)->basic);
1028 else
1029 p = priv->dma_rx + i;
47dd7a54 1030
56329137
BZ		 1031 ret = stmmac_init_rx_buffers(priv, p, i);
1032 if (ret)
1033 goto err_init_rx_buffers;
286a8372 1034
83d7af64
GC		 1035 if (netif_msg_probe(priv))
1036 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1037 priv->rx_skbuff[i]->data,
1038 (unsigned int)priv->rx_skbuff_dma[i]);
47dd7a54
GC		 1039 }
1040 priv->cur_rx = 0;
1041 priv->dirty_rx = (unsigned int)(i - rxsize);
47dd7a54
GC		 1042 buf_sz = bfsize;
1043
c24602ef
GC		 1044 /* Setup the chained descriptor addresses */
1045 if (priv->mode == STMMAC_CHAIN_MODE) {
1046 if (priv->extend_desc) {
1047 priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1048 rxsize, 1);
1049 priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1050 txsize, 1);
1051 } else {
1052 priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1053 rxsize, 0);
1054 priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1055 txsize, 0);
1056 }
1057 }
1058
47dd7a54
GC		 1059 /* TX INITIALIZATION */
1060 for (i = 0; i < txsize; i++) {
c24602ef
GC		 1061 struct dma_desc *p;
1062 if (priv->extend_desc)
1063 p = &((priv->dma_etx + i)->basic);
1064 else
1065 p = priv->dma_tx + i;
1066 p->des2 = 0;
cf32deec 1067 priv->tx_skbuff_dma[i] = 0;
47dd7a54 1068 priv->tx_skbuff[i] = NULL;
47dd7a54 1069 }
286a8372 1070
47dd7a54
GC		 1071 priv->dirty_tx = 0;
1072 priv->cur_tx = 0;
1073
c24602ef 1074 stmmac_clear_descriptors(priv);
47dd7a54 1075
c24602ef
GC		 1076 if (netif_msg_hw(priv))
1077 stmmac_display_rings(priv);
56329137
BZ		 1078
1079 return 0;
1080err_init_rx_buffers:
1081 while (--i >= 0)
1082 stmmac_free_rx_buffers(priv, i);
56329137 1083 return ret;
47dd7a54
GC		 1084}
1085
1086static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1087{
1088 int i;
1089
56329137
BZ		 1090 for (i = 0; i < priv->dma_rx_size; i++)
1091 stmmac_free_rx_buffers(priv, i);
47dd7a54
GC		 1092}
1093
1094static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1095{
1096 int i;
1097
1098 for (i = 0; i < priv->dma_tx_size; i++) {
75e4364f 1099 struct dma_desc *p;
1100
1101 if (priv->extend_desc)
1102 p = &((priv->dma_etx + i)->basic);
1103 else
1104 p = priv->dma_tx + i;
1105
1106 if (priv->tx_skbuff_dma[i]) {
1107 dma_unmap_single(priv->device,
1108 priv->tx_skbuff_dma[i],
1109 priv->hw->desc->get_tx_len(p),
1110 DMA_TO_DEVICE);
1111 priv->tx_skbuff_dma[i] = 0;
1112 }
c24602ef 1113
75e4364f 1114 if (priv->tx_skbuff[i] != NULL) {
47dd7a54
GC		 1115 dev_kfree_skb_any(priv->tx_skbuff[i]);
1116 priv->tx_skbuff[i] = NULL;
1117 }
1118 }
47dd7a54
GC		 1119}
1120
09f8d696
SK		 1121static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1122{
1123 unsigned int txsize = priv->dma_tx_size;
1124 unsigned int rxsize = priv->dma_rx_size;
1125 int ret = -ENOMEM;
1126
1127 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1128 GFP_KERNEL);
1129 if (!priv->rx_skbuff_dma)
1130 return -ENOMEM;
1131
1132 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1133 GFP_KERNEL);
1134 if (!priv->rx_skbuff)
1135 goto err_rx_skbuff;
1136
1137 priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1138 GFP_KERNEL);
1139 if (!priv->tx_skbuff_dma)
1140 goto err_tx_skbuff_dma;
1141
1142 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1143 GFP_KERNEL);
1144 if (!priv->tx_skbuff)
1145 goto err_tx_skbuff;
1146
1147 if (priv->extend_desc) {
1148 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1149 sizeof(struct
1150 dma_extended_desc),
1151 &priv->dma_rx_phy,
1152 GFP_KERNEL);
1153 if (!priv->dma_erx)
1154 goto err_dma;
1155
1156 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1157 sizeof(struct
1158 dma_extended_desc),
1159 &priv->dma_tx_phy,
1160 GFP_KERNEL);
1161 if (!priv->dma_etx) {
1162 dma_free_coherent(priv->device, priv->dma_rx_size *
1163 sizeof(struct dma_extended_desc),
1164 priv->dma_erx, priv->dma_rx_phy);
1165 goto err_dma;
1166 }
1167 } else {
1168 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1169 sizeof(struct dma_desc),
1170 &priv->dma_rx_phy,
1171 GFP_KERNEL);
1172 if (!priv->dma_rx)
1173 goto err_dma;
1174
1175 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1176 sizeof(struct dma_desc),
1177 &priv->dma_tx_phy,
1178 GFP_KERNEL);
1179 if (!priv->dma_tx) {
1180 dma_free_coherent(priv->device, priv->dma_rx_size *
1181 sizeof(struct dma_desc),
1182 priv->dma_rx, priv->dma_rx_phy);
1183 goto err_dma;
1184 }
1185 }
1186
1187 return 0;
1188
1189err_dma:
1190 kfree(priv->tx_skbuff);
1191err_tx_skbuff:
1192 kfree(priv->tx_skbuff_dma);
1193err_tx_skbuff_dma:
1194 kfree(priv->rx_skbuff);
1195err_rx_skbuff:
1196 kfree(priv->rx_skbuff_dma);
1197 return ret;
1198}
1199
47dd7a54
GC		 1200static void free_dma_desc_resources(struct stmmac_priv *priv)
1201{
1202 /* Release the DMA TX/RX socket buffers */
1203 dma_free_rx_skbufs(priv);
1204 dma_free_tx_skbufs(priv);
1205
ceb69499 1206 /* Free DMA regions of consistent memory previously allocated */
c24602ef
GC		 1207 if (!priv->extend_desc) {
1208 dma_free_coherent(priv->device,
1209 priv->dma_tx_size * sizeof(struct dma_desc),
1210 priv->dma_tx, priv->dma_tx_phy);
1211 dma_free_coherent(priv->device,
1212 priv->dma_rx_size * sizeof(struct dma_desc),
1213 priv->dma_rx, priv->dma_rx_phy);
1214 } else {
1215 dma_free_coherent(priv->device, priv->dma_tx_size *
1216 sizeof(struct dma_extended_desc),
1217 priv->dma_etx, priv->dma_tx_phy);
1218 dma_free_coherent(priv->device, priv->dma_rx_size *
1219 sizeof(struct dma_extended_desc),
1220 priv->dma_erx, priv->dma_rx_phy);
1221 }
47dd7a54
GC		 1222 kfree(priv->rx_skbuff_dma);
1223 kfree(priv->rx_skbuff);
cf32deec 1224 kfree(priv->tx_skbuff_dma);
47dd7a54 1225 kfree(priv->tx_skbuff);
47dd7a54
GC		 1226}
1227
47dd7a54
GC		 1228/**
1229 * stmmac_dma_operation_mode - HW DMA operation mode
32ceabca 1230 * @priv: driver private structure
47dd7a54 1231 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
ebbb293f 1232 * or Store-And-Forward capability.
47dd7a54
GC		 1233 */
1234static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1235{
e2a240c7
SZ		 1236 if (priv->plat->force_thresh_dma_mode)
1237 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1238 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
61b8013a
SK		 1239 /*
1240 * In case of GMAC, SF mode can be enabled
1241 * to perform the TX COE in HW. This depends on:
ebbb293f
GC		 1242 * 1) TX COE if actually supported
1243 * 2) There is no bugged Jumbo frame support
1244 * that needs to not insert csum in the TDES.
1245 */
ceb69499 1246 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
ebbb293f
GC		 1247 tc = SF_DMA_MODE;
1248 } else
1249 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
47dd7a54
GC		 1250}
1251
47dd7a54 1252/**
9125cdd1 1253 * stmmac_tx_clean:
32ceabca 1254 * @priv: driver private structure
47dd7a54
GC		 1255 * Description: it reclaims resources after transmission completes.
1256 */
9125cdd1 1257static void stmmac_tx_clean(struct stmmac_priv *priv)
47dd7a54
GC		 1258{
1259 unsigned int txsize = priv->dma_tx_size;
47dd7a54 1260
a9097a96
GC		 1261 spin_lock(&priv->tx_lock);
1262
9125cdd1
GC		 1263 priv->xstats.tx_clean++;
1264
47dd7a54
GC		 1265 while (priv->dirty_tx != priv->cur_tx) {
1266 int last;
1267 unsigned int entry = priv->dirty_tx % txsize;
1268 struct sk_buff *skb = priv->tx_skbuff[entry];
c24602ef
GC		 1269 struct dma_desc *p;
1270
1271 if (priv->extend_desc)
ceb69499 1272 p = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1273 else
1274 p = priv->dma_tx + entry;
47dd7a54
GC		 1275
1276 /* Check if the descriptor is owned by the DMA. */
db98a0b0 1277 if (priv->hw->desc->get_tx_owner(p))
47dd7a54
GC		 1278 break;
1279
c24602ef 1280 /* Verify tx error by looking at the last segment. */
db98a0b0 1281 last = priv->hw->desc->get_tx_ls(p);
47dd7a54
GC		 1282 if (likely(last)) {
1283 int tx_error =
ceb69499
GC		 1284 priv->hw->desc->tx_status(&priv->dev->stats,
1285 &priv->xstats, p,
1286 priv->ioaddr);
47dd7a54
GC		 1287 if (likely(tx_error == 0)) {
1288 priv->dev->stats.tx_packets++;
1289 priv->xstats.tx_pkt_n++;
1290 } else
1291 priv->dev->stats.tx_errors++;
891434b1
RK		 1292
1293 stmmac_get_tx_hwtstamp(priv, entry, skb);
47dd7a54 1294 }
83d7af64
GC		 1295 if (netif_msg_tx_done(priv))
1296 pr_debug("%s: curr %d, dirty %d\n", __func__,
1297 priv->cur_tx, priv->dirty_tx);
47dd7a54 1298
cf32deec
RK		 1299 if (likely(priv->tx_skbuff_dma[entry])) {
1300 dma_unmap_single(priv->device,
1301 priv->tx_skbuff_dma[entry],
db98a0b0 1302 priv->hw->desc->get_tx_len(p),
47dd7a54 1303 DMA_TO_DEVICE);
cf32deec
RK		 1304 priv->tx_skbuff_dma[entry] = 0;
1305 }
891434b1 1306 priv->hw->ring->clean_desc3(priv, p);
47dd7a54
GC		 1307
1308 if (likely(skb != NULL)) {
acb600de 1309 dev_kfree_skb(skb);
47dd7a54
GC		 1310 priv->tx_skbuff[entry] = NULL;
1311 }
1312
4a7d666a 1313 priv->hw->desc->release_tx_desc(p, priv->mode);
47dd7a54 1314
13497f58 1315 priv->dirty_tx++;
47dd7a54
GC		 1316 }
1317 if (unlikely(netif_queue_stopped(priv->dev) &&
1318 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1319 netif_tx_lock(priv->dev);
1320 if (netif_queue_stopped(priv->dev) &&
ceb69499 1321 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
83d7af64
GC		 1322 if (netif_msg_tx_done(priv))
1323 pr_debug("%s: restart transmit\n", __func__);
47dd7a54
GC		 1324 netif_wake_queue(priv->dev);
1325 }
1326 netif_tx_unlock(priv->dev);
1327 }
d765955d
GC		 1328
1329 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1330 stmmac_enable_eee_mode(priv);
f5351ef7 1331 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
d765955d 1332 }
a9097a96 1333 spin_unlock(&priv->tx_lock);
47dd7a54
GC		 1334}
1335
9125cdd1 1336static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1337{
7284a3f1 1338 priv->hw->dma->enable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1339}
1340
9125cdd1 1341static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
47dd7a54 1342{
7284a3f1 1343 priv->hw->dma->disable_dma_irq(priv->ioaddr);
47dd7a54
GC		 1344}
1345
47dd7a54 1346/**
32ceabca
GC		 1347 * stmmac_tx_err: irq tx error mng function
1348 * @priv: driver private structure
47dd7a54
GC		 1349 * Description: it cleans the descriptors and restarts the transmission
1350 * in case of errors.
1351 */
1352static void stmmac_tx_err(struct stmmac_priv *priv)
1353{
c24602ef
GC		 1354 int i;
1355 int txsize = priv->dma_tx_size;
47dd7a54
GC		 1356 netif_stop_queue(priv->dev);
1357
ad01b7d4 1358 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 1359 dma_free_tx_skbufs(priv);
c24602ef
GC		 1360 for (i = 0; i < txsize; i++)
1361 if (priv->extend_desc)
1362 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1363 priv->mode,
1364 (i == txsize - 1));
1365 else
1366 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1367 priv->mode,
1368 (i == txsize - 1));
47dd7a54
GC		 1369 priv->dirty_tx = 0;
1370 priv->cur_tx = 0;
ad01b7d4 1371 priv->hw->dma->start_tx(priv->ioaddr);
47dd7a54
GC		 1372
1373 priv->dev->stats.tx_errors++;
1374 netif_wake_queue(priv->dev);
47dd7a54
GC		 1375}
1376
32ceabca
GC		 1377/**
1378 * stmmac_dma_interrupt: DMA ISR
1379 * @priv: driver private structure
1380 * Description: this is the DMA ISR. It is called by the main ISR.
1381 * It calls the dwmac dma routine to understand which type of interrupt
1382 * happened. In case of there is a Normal interrupt and either TX or RX
1383 * interrupt happened so the NAPI is scheduled.
1384 */
aec7ff27
GC		 1385static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1386{
aec7ff27
GC		 1387 int status;
1388
ad01b7d4 1389 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
9125cdd1
GC		 1390 if (likely((status & handle_rx)) || (status & handle_tx)) {
1391 if (likely(napi_schedule_prep(&priv->napi))) {
1392 stmmac_disable_dma_irq(priv);
1393 __napi_schedule(&priv->napi);
1394 }
1395 }
1396 if (unlikely(status & tx_hard_error_bump_tc)) {
aec7ff27
GC		 1397 /* Try to bump up the dma threshold on this failure */
1398 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1399 tc += 64;
ad01b7d4 1400 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
aec7ff27 1401 priv->xstats.threshold = tc;
47dd7a54 1402 }
aec7ff27
GC		 1403 } else if (unlikely(status == tx_hard_error))
1404 stmmac_tx_err(priv);
47dd7a54
GC		 1405}
1406
32ceabca
GC		 1407/**
1408 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1409 * @priv: driver private structure
1410 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1411 */
1c901a46
GC		 1412static void stmmac_mmc_setup(struct stmmac_priv *priv)
1413{
1414 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
ceb69499 1415 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1c901a46 1416
1c901a46 1417 dwmac_mmc_intr_all_mask(priv->ioaddr);
4f795b25
GC		 1418
1419 if (priv->dma_cap.rmon) {
1420 dwmac_mmc_ctrl(priv->ioaddr, mode);
1421 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1422 } else
aae54cff 1423 pr_info(" No MAC Management Counters available\n");
1c901a46
GC		 1424}
1425
f0b9d786
GC		 1426static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1427{
1428 u32 hwid = priv->hw->synopsys_uid;
1429
ceb69499 1430 /* Check Synopsys Id (not available on old chips) */
f0b9d786
GC		 1431 if (likely(hwid)) {
1432 u32 uid = ((hwid & 0x0000ff00) >> 8);
1433 u32 synid = (hwid & 0x000000ff);
1434
cf3f047b 1435 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
f0b9d786
GC		 1436 uid, synid);
1437
1438 return synid;
1439 }
1440 return 0;
1441}
e7434821 1442
19e30c14 1443/**
32ceabca
GC		 1444 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1445 * @priv: driver private structure
1446 * Description: select the Enhanced/Alternate or Normal descriptors.
1447 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1448 * supported by the HW cap. register.
ff3dd78c 1449 */
19e30c14
GC		 1450static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1451{
1452 if (priv->plat->enh_desc) {
1453 pr_info(" Enhanced/Alternate descriptors\n");
c24602ef
GC		 1454
1455 /* GMAC older than 3.50 has no extended descriptors */
1456 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1457 pr_info("\tEnabled extended descriptors\n");
1458 priv->extend_desc = 1;
1459 } else
1460 pr_warn("Extended descriptors not supported\n");
1461
19e30c14
GC		 1462 priv->hw->desc = &enh_desc_ops;
1463 } else {
1464 pr_info(" Normal descriptors\n");
1465 priv->hw->desc = &ndesc_ops;
1466 }
1467}
1468
1469/**
32ceabca
GC		 1470 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1471 * @priv: driver private structure
19e30c14
GC		 1472 * Description:
1473 * new GMAC chip generations have a new register to indicate the
1474 * presence of the optional feature/functions.
1475 * This can be also used to override the value passed through the
1476 * platform and necessary for old MAC10/100 and GMAC chips.
e7434821
GC		 1477 */
1478static int stmmac_get_hw_features(struct stmmac_priv *priv)
1479{
5e6efe88 1480 u32 hw_cap = 0;
3c20f72f 1481
5e6efe88
GC		 1482 if (priv->hw->dma->get_hw_feature) {
1483 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
e7434821 1484
1db123fb
RK		 1485 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1486 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1487 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1488 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
ceb69499 1489 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1db123fb
RK		 1490 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1491 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1492 priv->dma_cap.pmt_remote_wake_up =
ceb69499 1493 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1db123fb 1494 priv->dma_cap.pmt_magic_frame =
ceb69499 1495 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
19e30c14 1496 /* MMC */
1db123fb 1497 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
ceb69499 1498 /* IEEE 1588-2002 */
1db123fb 1499 priv->dma_cap.time_stamp =
ceb69499
GC		 1500 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1501 /* IEEE 1588-2008 */
1db123fb 1502 priv->dma_cap.atime_stamp =
ceb69499 1503 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
e7434821 1504 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1db123fb
RK		 1505 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1506 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
e7434821 1507 /* TX and RX csum */
1db123fb
RK		 1508 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1509 priv->dma_cap.rx_coe_type1 =
ceb69499 1510 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1db123fb 1511 priv->dma_cap.rx_coe_type2 =
ceb69499 1512 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1db123fb 1513 priv->dma_cap.rxfifo_over_2048 =
ceb69499 1514 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
e7434821 1515 /* TX and RX number of channels */
1db123fb 1516 priv->dma_cap.number_rx_channel =
ceb69499 1517 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1db123fb 1518 priv->dma_cap.number_tx_channel =
ceb69499
GC		 1519 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1520 /* Alternate (enhanced) DESC mode */
1521 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
19e30c14 1522 }
e7434821
GC		 1523
1524 return hw_cap;
1525}
1526
32ceabca
GC		 1527/**
1528 * stmmac_check_ether_addr: check if the MAC addr is valid
1529 * @priv: driver private structure
1530 * Description:
1531 * it is to verify if the MAC address is valid, in case of failures it
1532 * generates a random MAC address
1533 */
bfab27a1
GC		 1534static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1535{
bfab27a1
GC		 1536 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1537 priv->hw->mac->get_umac_addr((void __iomem *)
1538 priv->dev->base_addr,
1539 priv->dev->dev_addr, 0);
ceb69499 1540 if (!is_valid_ether_addr(priv->dev->dev_addr))
f2cedb63 1541 eth_hw_addr_random(priv->dev);
c88460b7
HG		 1542 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1543 priv->dev->dev_addr);
bfab27a1 1544 }
bfab27a1
GC		 1545}
1546
32ceabca
GC		 1547/**
1548 * stmmac_init_dma_engine: DMA init.
1549 * @priv: driver private structure
1550 * Description:
1551 * It inits the DMA invoking the specific MAC/GMAC callback.
1552 * Some DMA parameters can be passed from the platform;
1553 * in case of these are not passed a default is kept for the MAC or GMAC.
1554 */
0f1f88a8
GC		 1555static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1556{
1557 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
b9cde0a8 1558 int mixed_burst = 0;
c24602ef 1559 int atds = 0;
0f1f88a8 1560
0f1f88a8
GC		 1561 if (priv->plat->dma_cfg) {
1562 pbl = priv->plat->dma_cfg->pbl;
1563 fixed_burst = priv->plat->dma_cfg->fixed_burst;
b9cde0a8 1564 mixed_burst = priv->plat->dma_cfg->mixed_burst;
0f1f88a8
GC		 1565 burst_len = priv->plat->dma_cfg->burst_len;
1566 }
1567
c24602ef
GC		 1568 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1569 atds = 1;
1570
b9cde0a8 1571 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
0f1f88a8 1572 burst_len, priv->dma_tx_phy,
c24602ef 1573 priv->dma_rx_phy, atds);
0f1f88a8
GC		 1574}
1575
9125cdd1 1576/**
32ceabca 1577 * stmmac_tx_timer: mitigation sw timer for tx.
9125cdd1
GC		 1578 * @data: data pointer
1579 * Description:
1580 * This is the timer handler to directly invoke the stmmac_tx_clean.
1581 */
1582static void stmmac_tx_timer(unsigned long data)
1583{
1584 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1585
1586 stmmac_tx_clean(priv);
1587}
1588
1589/**
32ceabca
GC		 1590 * stmmac_init_tx_coalesce: init tx mitigation options.
1591 * @priv: driver private structure
9125cdd1
GC		 1592 * Description:
1593 * This inits the transmit coalesce parameters: i.e. timer rate,
1594 * timer handler and default threshold used for enabling the
1595 * interrupt on completion bit.
1596 */
1597static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1598{
1599 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1600 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1601 init_timer(&priv->txtimer);
1602 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1603 priv->txtimer.data = (unsigned long)priv;
1604 priv->txtimer.function = stmmac_tx_timer;
1605 add_timer(&priv->txtimer);
1606}
1607
523f11b5
SK		 1608/**
1609 * stmmac_hw_setup: setup mac in a usable state.
1610 * @dev : pointer to the device structure.
1611 * Description:
1612 * This function sets up the ip in a usable state.
1613 * Return value:
1614 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1615 * file on failure.
1616 */
1617static int stmmac_hw_setup(struct net_device *dev)
1618{
1619 struct stmmac_priv *priv = netdev_priv(dev);
1620 int ret;
1621
1622 ret = init_dma_desc_rings(dev);
1623 if (ret < 0) {
1624 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1625 return ret;
1626 }
1627 /* DMA initialization and SW reset */
1628 ret = stmmac_init_dma_engine(priv);
1629 if (ret < 0) {
1630 pr_err("%s: DMA engine initialization failed\n", __func__);
1631 return ret;
1632 }
1633
1634 /* Copy the MAC addr into the HW */
1635 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1636
1637 /* If required, perform hw setup of the bus. */
1638 if (priv->plat->bus_setup)
1639 priv->plat->bus_setup(priv->ioaddr);
1640
1641 /* Initialize the MAC Core */
2618abb7 1642 priv->hw->mac->core_init(priv->ioaddr, dev->mtu);
523f11b5
SK		 1643
1644 /* Enable the MAC Rx/Tx */
1645 stmmac_set_mac(priv->ioaddr, true);
1646
1647 /* Set the HW DMA mode and the COE */
1648 stmmac_dma_operation_mode(priv);
1649
1650 stmmac_mmc_setup(priv);
1651
1652 ret = stmmac_init_ptp(priv);
7509edd6 1653 if (ret && ret != -EOPNOTSUPP)
523f11b5
SK		 1654 pr_warn("%s: failed PTP initialisation\n", __func__);
1655
1656#ifdef CONFIG_STMMAC_DEBUG_FS
1657 ret = stmmac_init_fs(dev);
1658 if (ret < 0)
1659 pr_warn("%s: failed debugFS registration\n", __func__);
1660#endif
1661 /* Start the ball rolling... */
1662 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1663 priv->hw->dma->start_tx(priv->ioaddr);
1664 priv->hw->dma->start_rx(priv->ioaddr);
1665
1666 /* Dump DMA/MAC registers */
1667 if (netif_msg_hw(priv)) {
1668 priv->hw->mac->dump_regs(priv->ioaddr);
1669 priv->hw->dma->dump_regs(priv->ioaddr);
1670 }
1671 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1672
1673 priv->eee_enabled = stmmac_eee_init(priv);
1674
1675 stmmac_init_tx_coalesce(priv);
1676
1677 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1678 priv->rx_riwt = MAX_DMA_RIWT;
1679 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1680 }
1681
1682 if (priv->pcs && priv->hw->mac->ctrl_ane)
1683 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1684
1685 return 0;
1686}
1687
47dd7a54
GC		 1688/**
1689 * stmmac_open - open entry point of the driver
1690 * @dev : pointer to the device structure.
1691 * Description:
1692 * This function is the open entry point of the driver.
1693 * Return value:
1694 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1695 * file on failure.
1696 */
1697static int stmmac_open(struct net_device *dev)
1698{
1699 struct stmmac_priv *priv = netdev_priv(dev);
47dd7a54
GC		 1700 int ret;
1701
4bfcbd7a
FV		 1702 stmmac_check_ether_addr(priv);
1703
4d8f0825
BA		 1704 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1705 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 1706 ret = stmmac_init_phy(dev);
1707 if (ret) {
1708 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1709 __func__, ret);
c9324d18 1710 goto phy_error;
e58bb43f 1711 }
f66ffe28 1712 }
47dd7a54 1713
523f11b5
SK		 1714 /* Extra statistics */
1715 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1716 priv->xstats.threshold = tc;
1717
47dd7a54
GC		 1718 /* Create and initialize the TX/RX descriptors chains. */
1719 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1720 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1721 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
56329137 1722
7262b7b2 1723 ret = alloc_dma_desc_resources(priv);
09f8d696
SK		 1724 if (ret < 0) {
1725 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1726 goto dma_desc_error;
1727 }
1728
523f11b5 1729 ret = stmmac_hw_setup(dev);
56329137 1730 if (ret < 0) {
523f11b5 1731 pr_err("%s: Hw setup failed\n", __func__);
c9324d18 1732 goto init_error;
47dd7a54
GC		 1733 }
1734
523f11b5
SK		 1735 if (priv->phydev)
1736 phy_start(priv->phydev);
47dd7a54 1737
f66ffe28
GC		 1738 /* Request the IRQ lines */
1739 ret = request_irq(dev->irq, stmmac_interrupt,
ceb69499 1740 IRQF_SHARED, dev->name, dev);
f66ffe28
GC		 1741 if (unlikely(ret < 0)) {
1742 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1743 __func__, dev->irq, ret);
c9324d18 1744 goto init_error;
f66ffe28
GC		 1745 }
1746
7a13f8f5
FV		 1747 /* Request the Wake IRQ in case of another line is used for WoL */
1748 if (priv->wol_irq != dev->irq) {
1749 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1750 IRQF_SHARED, dev->name, dev);
1751 if (unlikely(ret < 0)) {
ceb69499
GC		 1752 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1753 __func__, priv->wol_irq, ret);
c9324d18 1754 goto wolirq_error;
7a13f8f5
FV		 1755 }
1756 }
1757
d765955d
GC		 1758 /* Request the IRQ lines */
1759 if (priv->lpi_irq != -ENXIO) {
1760 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1761 dev->name, dev);
1762 if (unlikely(ret < 0)) {
1763 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1764 __func__, priv->lpi_irq, ret);
c9324d18 1765 goto lpiirq_error;
d765955d
GC		 1766 }
1767 }
1768
47dd7a54 1769 napi_enable(&priv->napi);
47dd7a54 1770 netif_start_queue(dev);
f66ffe28 1771
47dd7a54 1772 return 0;
f66ffe28 1773
c9324d18 1774lpiirq_error:
d765955d
GC		 1775 if (priv->wol_irq != dev->irq)
1776 free_irq(priv->wol_irq, dev);
c9324d18 1777wolirq_error:
7a13f8f5
FV		 1778 free_irq(dev->irq, dev);
1779
c9324d18
GC		 1780init_error:
1781 free_dma_desc_resources(priv);
56329137 1782dma_desc_error:
f66ffe28
GC		 1783 if (priv->phydev)
1784 phy_disconnect(priv->phydev);
c9324d18 1785phy_error:
a630844d 1786 clk_disable_unprepare(priv->stmmac_clk);
4bfcbd7a 1787
f66ffe28 1788 return ret;
47dd7a54
GC		 1789}
1790
1791/**
1792 * stmmac_release - close entry point of the driver
1793 * @dev : device pointer.
1794 * Description:
1795 * This is the stop entry point of the driver.
1796 */
1797static int stmmac_release(struct net_device *dev)
1798{
1799 struct stmmac_priv *priv = netdev_priv(dev);
1800
d765955d
GC		 1801 if (priv->eee_enabled)
1802 del_timer_sync(&priv->eee_ctrl_timer);
1803
47dd7a54
GC		 1804 /* Stop and disconnect the PHY */
1805 if (priv->phydev) {
1806 phy_stop(priv->phydev);
1807 phy_disconnect(priv->phydev);
1808 priv->phydev = NULL;
1809 }
1810
1811 netif_stop_queue(dev);
1812
47dd7a54 1813 napi_disable(&priv->napi);
47dd7a54 1814
9125cdd1
GC		 1815 del_timer_sync(&priv->txtimer);
1816
47dd7a54
GC		 1817 /* Free the IRQ lines */
1818 free_irq(dev->irq, dev);
7a13f8f5
FV		 1819 if (priv->wol_irq != dev->irq)
1820 free_irq(priv->wol_irq, dev);
d765955d
GC		 1821 if (priv->lpi_irq != -ENXIO)
1822 free_irq(priv->lpi_irq, dev);
47dd7a54
GC		 1823
1824 /* Stop TX/RX DMA and clear the descriptors */
ad01b7d4
GC		 1825 priv->hw->dma->stop_tx(priv->ioaddr);
1826 priv->hw->dma->stop_rx(priv->ioaddr);
47dd7a54
GC		 1827
1828 /* Release and free the Rx/Tx resources */
1829 free_dma_desc_resources(priv);
1830
19449bfc 1831 /* Disable the MAC Rx/Tx */
bfab27a1 1832 stmmac_set_mac(priv->ioaddr, false);
47dd7a54
GC		 1833
1834 netif_carrier_off(dev);
1835
bfab27a1
GC		 1836#ifdef CONFIG_STMMAC_DEBUG_FS
1837 stmmac_exit_fs();
1838#endif
bfab27a1 1839
92ba6888
RK		 1840 stmmac_release_ptp(priv);
1841
47dd7a54
GC		 1842 return 0;
1843}
1844
47dd7a54 1845/**
32ceabca 1846 * stmmac_xmit: Tx entry point of the driver
47dd7a54
GC		 1847 * @skb : the socket buffer
1848 * @dev : device pointer
32ceabca
GC		 1849 * Description : this is the tx entry point of the driver.
1850 * It programs the chain or the ring and supports oversized frames
1851 * and SG feature.
47dd7a54
GC		 1852 */
1853static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1854{
1855 struct stmmac_priv *priv = netdev_priv(dev);
1856 unsigned int txsize = priv->dma_tx_size;
1857 unsigned int entry;
4a7d666a 1858 int i, csum_insertion = 0, is_jumbo = 0;
47dd7a54
GC		 1859 int nfrags = skb_shinfo(skb)->nr_frags;
1860 struct dma_desc *desc, *first;
286a8372 1861 unsigned int nopaged_len = skb_headlen(skb);
47dd7a54
GC		 1862
1863 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1864 if (!netif_queue_stopped(dev)) {
1865 netif_stop_queue(dev);
1866 /* This is a hard error, log it. */
ceb69499 1867 pr_err("%s: Tx Ring full when queue awake\n", __func__);
47dd7a54
GC		 1868 }
1869 return NETDEV_TX_BUSY;
1870 }
1871
a9097a96
GC		 1872 spin_lock(&priv->tx_lock);
1873
d765955d
GC		 1874 if (priv->tx_path_in_lpi_mode)
1875 stmmac_disable_eee_mode(priv);
1876
47dd7a54
GC		 1877 entry = priv->cur_tx % txsize;
1878
5e982f3b 1879 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
47dd7a54 1880
c24602ef 1881 if (priv->extend_desc)
ceb69499 1882 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1883 else
1884 desc = priv->dma_tx + entry;
1885
47dd7a54
GC		 1886 first = desc;
1887
4a7d666a
GC		 1888 /* To program the descriptors according to the size of the frame */
1889 if (priv->mode == STMMAC_RING_MODE) {
1890 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1891 priv->plat->enh_desc);
1892 if (unlikely(is_jumbo))
1893 entry = priv->hw->ring->jumbo_frm(priv, skb,
1894 csum_insertion);
47dd7a54 1895 } else {
4a7d666a 1896 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
ceb69499 1897 priv->plat->enh_desc);
4a7d666a
GC		 1898 if (unlikely(is_jumbo))
1899 entry = priv->hw->chain->jumbo_frm(priv, skb,
1900 csum_insertion);
1901 }
1902 if (likely(!is_jumbo)) {
47dd7a54 1903 desc->des2 = dma_map_single(priv->device, skb->data,
ceb69499 1904 nopaged_len, DMA_TO_DEVICE);
cf32deec 1905 priv->tx_skbuff_dma[entry] = desc->des2;
db98a0b0 1906 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
4a7d666a
GC		 1907 csum_insertion, priv->mode);
1908 } else
c24602ef 1909 desc = first;
47dd7a54
GC		 1910
1911 for (i = 0; i < nfrags; i++) {
9e903e08
ED		 1912 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1913 int len = skb_frag_size(frag);
47dd7a54 1914
75e4364f 1915 priv->tx_skbuff[entry] = NULL;
47dd7a54 1916 entry = (++priv->cur_tx) % txsize;
c24602ef 1917 if (priv->extend_desc)
ceb69499 1918 desc = (struct dma_desc *)(priv->dma_etx + entry);
c24602ef
GC		 1919 else
1920 desc = priv->dma_tx + entry;
47dd7a54 1921
f722380d
IC		 1922 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1923 DMA_TO_DEVICE);
cf32deec 1924 priv->tx_skbuff_dma[entry] = desc->des2;
4a7d666a
GC		 1925 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1926 priv->mode);
eb0dc4bb 1927 wmb();
db98a0b0 1928 priv->hw->desc->set_tx_owner(desc);
8e839891 1929 wmb();
47dd7a54
GC		 1930 }
1931
75e4364f 1932 priv->tx_skbuff[entry] = skb;
1933
9125cdd1 1934 /* Finalize the latest segment. */
db98a0b0 1935 priv->hw->desc->close_tx_desc(desc);
73cfe264 1936
eb0dc4bb 1937 wmb();
9125cdd1
GC		 1938 /* According to the coalesce parameter the IC bit for the latest
1939 * segment could be reset and the timer re-started to invoke the
1940 * stmmac_tx function. This approach takes care about the fragments.
1941 */
1942 priv->tx_count_frames += nfrags + 1;
1943 if (priv->tx_coal_frames > priv->tx_count_frames) {
1944 priv->hw->desc->clear_tx_ic(desc);
1945 priv->xstats.tx_reset_ic_bit++;
9125cdd1
GC		 1946 mod_timer(&priv->txtimer,
1947 STMMAC_COAL_TIMER(priv->tx_coal_timer));
1948 } else
1949 priv->tx_count_frames = 0;
eb0dc4bb 1950
47dd7a54 1951 /* To avoid raise condition */
db98a0b0 1952 priv->hw->desc->set_tx_owner(first);
8e839891 1953 wmb();
47dd7a54
GC		 1954
1955 priv->cur_tx++;
1956
47dd7a54 1957 if (netif_msg_pktdata(priv)) {
83d7af64 1958 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
ceb69499
GC		 1959 __func__, (priv->cur_tx % txsize),
1960 (priv->dirty_tx % txsize), entry, first, nfrags);
83d7af64 1961
c24602ef
GC		 1962 if (priv->extend_desc)
1963 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1964 else
1965 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1966
83d7af64 1967 pr_debug(">>> frame to be transmitted: ");
47dd7a54
GC		 1968 print_pkt(skb->data, skb->len);
1969 }
47dd7a54 1970 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
83d7af64
GC		 1971 if (netif_msg_hw(priv))
1972 pr_debug("%s: stop transmitted packets\n", __func__);
47dd7a54
GC		 1973 netif_stop_queue(dev);
1974 }
1975
1976 dev->stats.tx_bytes += skb->len;
1977
891434b1
RK		 1978 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1979 priv->hwts_tx_en)) {
1980 /* declare that device is doing timestamping */
1981 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1982 priv->hw->desc->enable_tx_timestamp(first);
1983 }
1984
1985 if (!priv->hwts_tx_en)
1986 skb_tx_timestamp(skb);
3e82ce12 1987
52f64fae
RC		 1988 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1989
a9097a96
GC		 1990 spin_unlock(&priv->tx_lock);
1991
47dd7a54
GC		 1992 return NETDEV_TX_OK;
1993}
1994
b9381985
VB		 1995static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
1996{
1997 struct ethhdr *ehdr;
1998 u16 vlanid;
1999
2000 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2001 NETIF_F_HW_VLAN_CTAG_RX &&
2002 !__vlan_get_tag(skb, &vlanid)) {
2003 /* pop the vlan tag */
2004 ehdr = (struct ethhdr *)skb->data;
2005 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2006 skb_pull(skb, VLAN_HLEN);
2007 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2008 }
2009}
2010
2011
32ceabca
GC		 2012/**
2013 * stmmac_rx_refill: refill used skb preallocated buffers
2014 * @priv: driver private structure
2015 * Description : this is to reallocate the skb for the reception process
2016 * that is based on zero-copy.
2017 */
47dd7a54
GC		 2018static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2019{
2020 unsigned int rxsize = priv->dma_rx_size;
2021 int bfsize = priv->dma_buf_sz;
47dd7a54
GC		 2022
2023 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2024 unsigned int entry = priv->dirty_rx % rxsize;
c24602ef
GC		 2025 struct dma_desc *p;
2026
2027 if (priv->extend_desc)
ceb69499 2028 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef
GC		 2029 else
2030 p = priv->dma_rx + entry;
2031
47dd7a54
GC		 2032 if (likely(priv->rx_skbuff[entry] == NULL)) {
2033 struct sk_buff *skb;
2034
acb600de 2035 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
47dd7a54
GC		 2036
2037 if (unlikely(skb == NULL))
2038 break;
2039
2040 priv->rx_skbuff[entry] = skb;
2041 priv->rx_skbuff_dma[entry] =
2042 dma_map_single(priv->device, skb->data, bfsize,
2043 DMA_FROM_DEVICE);
2044
c24602ef 2045 p->des2 = priv->rx_skbuff_dma[entry];
286a8372 2046
891434b1 2047 priv->hw->ring->refill_desc3(priv, p);
286a8372 2048
83d7af64
GC		 2049 if (netif_msg_rx_status(priv))
2050 pr_debug("\trefill entry #%d\n", entry);
47dd7a54 2051 }
eb0dc4bb 2052 wmb();
c24602ef 2053 priv->hw->desc->set_rx_owner(p);
8e839891 2054 wmb();
47dd7a54 2055 }
47dd7a54
GC		 2056}
2057
32ceabca
GC		 2058/**
2059 * stmmac_rx_refill: refill used skb preallocated buffers
2060 * @priv: driver private structure
2061 * @limit: napi bugget.
2062 * Description : this the function called by the napi poll method.
2063 * It gets all the frames inside the ring.
2064 */
47dd7a54
GC		 2065static int stmmac_rx(struct stmmac_priv *priv, int limit)
2066{
2067 unsigned int rxsize = priv->dma_rx_size;
2068 unsigned int entry = priv->cur_rx % rxsize;
2069 unsigned int next_entry;
2070 unsigned int count = 0;
ceb69499 2071 int coe = priv->plat->rx_coe;
47dd7a54 2072
83d7af64
GC		 2073 if (netif_msg_rx_status(priv)) {
2074 pr_debug("%s: descriptor ring:\n", __func__);
c24602ef 2075 if (priv->extend_desc)
ceb69499 2076 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
c24602ef
GC		 2077 else
2078 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
47dd7a54 2079 }
c24602ef 2080 while (count < limit) {
47dd7a54 2081 int status;
9401bb5c 2082 struct dma_desc *p;
47dd7a54 2083
c24602ef 2084 if (priv->extend_desc)
ceb69499 2085 p = (struct dma_desc *)(priv->dma_erx + entry);
c24602ef 2086 else
ceb69499 2087 p = priv->dma_rx + entry;
c24602ef
GC		 2088
2089 if (priv->hw->desc->get_rx_owner(p))
47dd7a54
GC		 2090 break;
2091
2092 count++;
2093
2094 next_entry = (++priv->cur_rx) % rxsize;
c24602ef 2095 if (priv->extend_desc)
9401bb5c 2096 prefetch(priv->dma_erx + next_entry);
c24602ef 2097 else
9401bb5c 2098 prefetch(priv->dma_rx + next_entry);
47dd7a54
GC		 2099
2100 /* read the status of the incoming frame */
c24602ef
GC		 2101 status = priv->hw->desc->rx_status(&priv->dev->stats,
2102 &priv->xstats, p);
2103 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2104 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2105 &priv->xstats,
2106 priv->dma_erx +
2107 entry);
891434b1 2108 if (unlikely(status == discard_frame)) {
47dd7a54 2109 priv->dev->stats.rx_errors++;
891434b1
RK		 2110 if (priv->hwts_rx_en && !priv->extend_desc) {
2111 /* DESC2 & DESC3 will be overwitten by device
2112 * with timestamp value, hence reinitialize
2113 * them in stmmac_rx_refill() function so that
2114 * device can reuse it.
2115 */
2116 priv->rx_skbuff[entry] = NULL;
2117 dma_unmap_single(priv->device,
ceb69499
GC		 2118 priv->rx_skbuff_dma[entry],
2119 priv->dma_buf_sz,
2120 DMA_FROM_DEVICE);
891434b1
RK		 2121 }
2122 } else {
47dd7a54 2123 struct sk_buff *skb;
3eeb2997 2124 int frame_len;
47dd7a54 2125
ceb69499
GC		 2126 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2127
3eeb2997 2128 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
ceb69499
GC		 2129 * Type frames (LLC/LLC-SNAP)
2130 */
3eeb2997
GC		 2131 if (unlikely(status != llc_snap))
2132 frame_len -= ETH_FCS_LEN;
47dd7a54 2133
83d7af64 2134 if (netif_msg_rx_status(priv)) {
47dd7a54 2135 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
ceb69499 2136 p, entry, p->des2);
83d7af64
GC		 2137 if (frame_len > ETH_FRAME_LEN)
2138 pr_debug("\tframe size %d, COE: %d\n",
2139 frame_len, status);
2140 }
47dd7a54
GC		 2141 skb = priv->rx_skbuff[entry];
2142 if (unlikely(!skb)) {
2143 pr_err("%s: Inconsistent Rx descriptor chain\n",
ceb69499 2144 priv->dev->name);
47dd7a54
GC		 2145 priv->dev->stats.rx_dropped++;
2146 break;
2147 }
2148 prefetch(skb->data - NET_IP_ALIGN);
2149 priv->rx_skbuff[entry] = NULL;
2150
891434b1
RK		 2151 stmmac_get_rx_hwtstamp(priv, entry, skb);
2152
47dd7a54
GC		 2153 skb_put(skb, frame_len);
2154 dma_unmap_single(priv->device,
2155 priv->rx_skbuff_dma[entry],
2156 priv->dma_buf_sz, DMA_FROM_DEVICE);
83d7af64 2157
47dd7a54 2158 if (netif_msg_pktdata(priv)) {
83d7af64 2159 pr_debug("frame received (%dbytes)", frame_len);
47dd7a54
GC		 2160 print_pkt(skb->data, frame_len);
2161 }
83d7af64 2162
b9381985
VB		 2163 stmmac_rx_vlan(priv->dev, skb);
2164
47dd7a54
GC		 2165 skb->protocol = eth_type_trans(skb, priv->dev);
2166
ceb69499 2167 if (unlikely(!coe))
bc8acf2c 2168 skb_checksum_none_assert(skb);
62a2ab93 2169 else
47dd7a54 2170 skb->ip_summed = CHECKSUM_UNNECESSARY;
62a2ab93
GC		 2171
2172 napi_gro_receive(&priv->napi, skb);
47dd7a54
GC		 2173
2174 priv->dev->stats.rx_packets++;
2175 priv->dev->stats.rx_bytes += frame_len;
47dd7a54
GC		 2176 }
2177 entry = next_entry;
47dd7a54
GC		 2178 }
2179
2180 stmmac_rx_refill(priv);
2181
2182 priv->xstats.rx_pkt_n += count;
2183
2184 return count;
2185}
2186
2187/**
2188 * stmmac_poll - stmmac poll method (NAPI)
2189 * @napi : pointer to the napi structure.
2190 * @budget : maximum number of packets that the current CPU can receive from
2191 * all interfaces.
2192 * Description :
9125cdd1 2193 * To look at the incoming frames and clear the tx resources.
47dd7a54
GC		 2194 */
2195static int stmmac_poll(struct napi_struct *napi, int budget)
2196{
2197 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2198 int work_done = 0;
2199
9125cdd1
GC		 2200 priv->xstats.napi_poll++;
2201 stmmac_tx_clean(priv);
47dd7a54 2202
9125cdd1 2203 work_done = stmmac_rx(priv, budget);
47dd7a54
GC		 2204 if (work_done < budget) {
2205 napi_complete(napi);
9125cdd1 2206 stmmac_enable_dma_irq(priv);
47dd7a54
GC		 2207 }
2208 return work_done;
2209}
2210
2211/**
2212 * stmmac_tx_timeout
2213 * @dev : Pointer to net device structure
2214 * Description: this function is called when a packet transmission fails to
7284a3f1 2215 * complete within a reasonable time. The driver will mark the error in the
47dd7a54
GC		 2216 * netdev structure and arrange for the device to be reset to a sane state
2217 * in order to transmit a new packet.
2218 */
2219static void stmmac_tx_timeout(struct net_device *dev)
2220{
2221 struct stmmac_priv *priv = netdev_priv(dev);
2222
2223 /* Clear Tx resources and restart transmitting again */
2224 stmmac_tx_err(priv);
47dd7a54
GC		 2225}
2226
2227/* Configuration changes (passed on by ifconfig) */
2228static int stmmac_config(struct net_device *dev, struct ifmap *map)
2229{
2230 if (dev->flags & IFF_UP) /* can't act on a running interface */
2231 return -EBUSY;
2232
2233 /* Don't allow changing the I/O address */
2234 if (map->base_addr != dev->base_addr) {
ceb69499 2235 pr_warn("%s: can't change I/O address\n", dev->name);
47dd7a54
GC		 2236 return -EOPNOTSUPP;
2237 }
2238
2239 /* Don't allow changing the IRQ */
2240 if (map->irq != dev->irq) {
ceb69499 2241 pr_warn("%s: not change IRQ number %d\n", dev->name, dev->irq);
47dd7a54
GC		 2242 return -EOPNOTSUPP;
2243 }
2244
47dd7a54
GC		 2245 return 0;
2246}
2247
2248/**
01789349 2249 * stmmac_set_rx_mode - entry point for multicast addressing
47dd7a54
GC		 2250 * @dev : pointer to the device structure
2251 * Description:
2252 * This function is a driver entry point which gets called by the kernel
2253 * whenever multicast addresses must be enabled/disabled.
2254 * Return value:
2255 * void.
2256 */
01789349 2257static void stmmac_set_rx_mode(struct net_device *dev)
47dd7a54
GC		 2258{
2259 struct stmmac_priv *priv = netdev_priv(dev);
2260
2261 spin_lock(&priv->lock);
cffb13f4 2262 priv->hw->mac->set_filter(dev, priv->synopsys_id);
47dd7a54 2263 spin_unlock(&priv->lock);
47dd7a54
GC		 2264}
2265
2266/**
2267 * stmmac_change_mtu - entry point to change MTU size for the device.
2268 * @dev : device pointer.
2269 * @new_mtu : the new MTU size for the device.
2270 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2271 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2272 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2273 * Return value:
2274 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2275 * file on failure.
2276 */
2277static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2278{
2279 struct stmmac_priv *priv = netdev_priv(dev);
2280 int max_mtu;
2281
2282 if (netif_running(dev)) {
2283 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2284 return -EBUSY;
2285 }
2286
48febf7e 2287 if (priv->plat->enh_desc)
47dd7a54
GC		 2288 max_mtu = JUMBO_LEN;
2289 else
45db81e1 2290 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
47dd7a54 2291
2618abb7
VB		 2292 if (priv->plat->maxmtu < max_mtu)
2293 max_mtu = priv->plat->maxmtu;
2294
47dd7a54
GC		 2295 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2296 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2297 return -EINVAL;
2298 }
2299
5e982f3b
MM		 2300 dev->mtu = new_mtu;
2301 netdev_update_features(dev);
2302
2303 return 0;
2304}
2305
c8f44aff 2306static netdev_features_t stmmac_fix_features(struct net_device *dev,
ceb69499 2307 netdev_features_t features)
5e982f3b
MM		 2308{
2309 struct stmmac_priv *priv = netdev_priv(dev);
2310
38912bdb 2311 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5e982f3b 2312 features &= ~NETIF_F_RXCSUM;
38912bdb
DS		 2313 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2314 features &= ~NETIF_F_IPV6_CSUM;
5e982f3b
MM		 2315 if (!priv->plat->tx_coe)
2316 features &= ~NETIF_F_ALL_CSUM;
2317
ebbb293f
GC		 2318 /* Some GMAC devices have a bugged Jumbo frame support that
2319 * needs to have the Tx COE disabled for oversized frames
2320 * (due to limited buffer sizes). In this case we disable
ceb69499
GC		 2321 * the TX csum insertionin the TDES and not use SF.
2322 */
5e982f3b
MM		 2323 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2324 features &= ~NETIF_F_ALL_CSUM;
ebbb293f 2325
5e982f3b 2326 return features;
47dd7a54
GC		 2327}
2328
32ceabca
GC		 2329/**
2330 * stmmac_interrupt - main ISR
2331 * @irq: interrupt number.
2332 * @dev_id: to pass the net device pointer.
2333 * Description: this is the main driver interrupt service routine.
2334 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2335 * interrupts.
2336 */
47dd7a54
GC		 2337static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2338{
2339 struct net_device *dev = (struct net_device *)dev_id;
2340 struct stmmac_priv *priv = netdev_priv(dev);
2341
89f7f2cf
SK		 2342 if (priv->irq_wake)
2343 pm_wakeup_event(priv->device, 0);
2344
47dd7a54
GC		 2345 if (unlikely(!dev)) {
2346 pr_err("%s: invalid dev pointer\n", __func__);
2347 return IRQ_NONE;
2348 }
2349
d765955d
GC		 2350 /* To handle GMAC own interrupts */
2351 if (priv->plat->has_gmac) {
2352 int status = priv->hw->mac->host_irq_status((void __iomem *)
0982a0f6
GC		 2353 dev->base_addr,
2354 &priv->xstats);
d765955d 2355 if (unlikely(status)) {
d765955d 2356 /* For LPI we need to save the tx status */
0982a0f6 2357 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
d765955d 2358 priv->tx_path_in_lpi_mode = true;
0982a0f6 2359 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
d765955d 2360 priv->tx_path_in_lpi_mode = false;
d765955d
GC		 2361 }
2362 }
aec7ff27 2363
d765955d 2364 /* To handle DMA interrupts */
aec7ff27 2365 stmmac_dma_interrupt(priv);
47dd7a54
GC		 2366
2367 return IRQ_HANDLED;
2368}
2369
2370#ifdef CONFIG_NET_POLL_CONTROLLER
2371/* Polling receive - used by NETCONSOLE and other diagnostic tools
ceb69499
GC		 2372 * to allow network I/O with interrupts disabled.
2373 */
47dd7a54
GC		 2374static void stmmac_poll_controller(struct net_device *dev)
2375{
2376 disable_irq(dev->irq);
2377 stmmac_interrupt(dev->irq, dev);
2378 enable_irq(dev->irq);
2379}
2380#endif
2381
2382/**
2383 * stmmac_ioctl - Entry point for the Ioctl
2384 * @dev: Device pointer.
2385 * @rq: An IOCTL specefic structure, that can contain a pointer to
2386 * a proprietary structure used to pass information to the driver.
2387 * @cmd: IOCTL command
2388 * Description:
32ceabca 2389 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
47dd7a54
GC		 2390 */
2391static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2392{
2393 struct stmmac_priv *priv = netdev_priv(dev);
891434b1 2394 int ret = -EOPNOTSUPP;
47dd7a54
GC		 2395
2396 if (!netif_running(dev))
2397 return -EINVAL;
2398
891434b1
RK		 2399 switch (cmd) {
2400 case SIOCGMIIPHY:
2401 case SIOCGMIIREG:
2402 case SIOCSMIIREG:
2403 if (!priv->phydev)
2404 return -EINVAL;
2405 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2406 break;
2407 case SIOCSHWTSTAMP:
2408 ret = stmmac_hwtstamp_ioctl(dev, rq);
2409 break;
2410 default:
2411 break;
2412 }
28b04113 2413
47dd7a54
GC		 2414 return ret;
2415}
2416
7ac29055
GC		 2417#ifdef CONFIG_STMMAC_DEBUG_FS
2418static struct dentry *stmmac_fs_dir;
2419static struct dentry *stmmac_rings_status;
e7434821 2420static struct dentry *stmmac_dma_cap;
7ac29055 2421
c24602ef 2422static void sysfs_display_ring(void *head, int size, int extend_desc,
ceb69499 2423 struct seq_file *seq)
7ac29055 2424{
7ac29055 2425 int i;
ceb69499
GC		 2426 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2427 struct dma_desc *p = (struct dma_desc *)head;
7ac29055 2428
c24602ef
GC		 2429 for (i = 0; i < size; i++) {
2430 u64 x;
2431 if (extend_desc) {
2432 x = *(u64 *) ep;
2433 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2434 i, (unsigned int)virt_to_phys(ep),
2435 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2436 ep->basic.des2, ep->basic.des3);
2437 ep++;
2438 } else {
2439 x = *(u64 *) p;
2440 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
ceb69499
GC		 2441 i, (unsigned int)virt_to_phys(ep),
2442 (unsigned int)x, (unsigned int)(x >> 32),
c24602ef
GC		 2443 p->des2, p->des3);
2444 p++;
2445 }
7ac29055
GC		 2446 seq_printf(seq, "\n");
2447 }
c24602ef 2448}
7ac29055 2449
c24602ef
GC		 2450static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2451{
2452 struct net_device *dev = seq->private;
2453 struct stmmac_priv *priv = netdev_priv(dev);
2454 unsigned int txsize = priv->dma_tx_size;
2455 unsigned int rxsize = priv->dma_rx_size;
7ac29055 2456
c24602ef
GC		 2457 if (priv->extend_desc) {
2458 seq_printf(seq, "Extended RX descriptor ring:\n");
ceb69499 2459 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
c24602ef 2460 seq_printf(seq, "Extended TX descriptor ring:\n");
ceb69499 2461 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
c24602ef
GC		 2462 } else {
2463 seq_printf(seq, "RX descriptor ring:\n");
2464 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2465 seq_printf(seq, "TX descriptor ring:\n");
2466 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
7ac29055
GC		 2467 }
2468
2469 return 0;
2470}
2471
2472static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2473{
2474 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2475}
2476
2477static const struct file_operations stmmac_rings_status_fops = {
2478 .owner = THIS_MODULE,
2479 .open = stmmac_sysfs_ring_open,
2480 .read = seq_read,
2481 .llseek = seq_lseek,
74863948 2482 .release = single_release,
7ac29055
GC		 2483};
2484
e7434821
GC		 2485static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2486{
2487 struct net_device *dev = seq->private;
2488 struct stmmac_priv *priv = netdev_priv(dev);
2489
19e30c14 2490 if (!priv->hw_cap_support) {
e7434821
GC		 2491 seq_printf(seq, "DMA HW features not supported\n");
2492 return 0;
2493 }
2494
2495 seq_printf(seq, "==============================\n");
2496 seq_printf(seq, "\tDMA HW features\n");
2497 seq_printf(seq, "==============================\n");
2498
2499 seq_printf(seq, "\t10/100 Mbps %s\n",
2500 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2501 seq_printf(seq, "\t1000 Mbps %s\n",
2502 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2503 seq_printf(seq, "\tHalf duple %s\n",
2504 (priv->dma_cap.half_duplex) ? "Y" : "N");
2505 seq_printf(seq, "\tHash Filter: %s\n",
2506 (priv->dma_cap.hash_filter) ? "Y" : "N");
2507 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2508 (priv->dma_cap.multi_addr) ? "Y" : "N");
2509 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2510 (priv->dma_cap.pcs) ? "Y" : "N");
2511 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2512 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2513 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2514 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2515 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2516 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2517 seq_printf(seq, "\tRMON module: %s\n",
2518 (priv->dma_cap.rmon) ? "Y" : "N");
2519 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2520 (priv->dma_cap.time_stamp) ? "Y" : "N");
2521 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2522 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2523 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2524 (priv->dma_cap.eee) ? "Y" : "N");
2525 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2526 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2527 (priv->dma_cap.tx_coe) ? "Y" : "N");
2528 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2529 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2530 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2531 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2532 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2533 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2534 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2535 priv->dma_cap.number_rx_channel);
2536 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2537 priv->dma_cap.number_tx_channel);
2538 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2539 (priv->dma_cap.enh_desc) ? "Y" : "N");
2540
2541 return 0;
2542}
2543
2544static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2545{
2546 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2547}
2548
2549static const struct file_operations stmmac_dma_cap_fops = {
2550 .owner = THIS_MODULE,
2551 .open = stmmac_sysfs_dma_cap_open,
2552 .read = seq_read,
2553 .llseek = seq_lseek,
74863948 2554 .release = single_release,
e7434821
GC		 2555};
2556
7ac29055
GC		 2557static int stmmac_init_fs(struct net_device *dev)
2558{
2559 /* Create debugfs entries */
2560 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2561
2562 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2563 pr_err("ERROR %s, debugfs create directory failed\n",
2564 STMMAC_RESOURCE_NAME);
2565
2566 return -ENOMEM;
2567 }
2568
2569 /* Entry to report DMA RX/TX rings */
2570 stmmac_rings_status = debugfs_create_file("descriptors_status",
ceb69499
GC		 2571 S_IRUGO, stmmac_fs_dir, dev,
2572 &stmmac_rings_status_fops);
7ac29055
GC		 2573
2574 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2575 pr_info("ERROR creating stmmac ring debugfs file\n");
2576 debugfs_remove(stmmac_fs_dir);
2577
2578 return -ENOMEM;
2579 }
2580
e7434821
GC		 2581 /* Entry to report the DMA HW features */
2582 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2583 dev, &stmmac_dma_cap_fops);
2584
2585 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2586 pr_info("ERROR creating stmmac MMC debugfs file\n");
2587 debugfs_remove(stmmac_rings_status);
2588 debugfs_remove(stmmac_fs_dir);
2589
2590 return -ENOMEM;
2591 }
2592
7ac29055
GC		 2593 return 0;
2594}
2595
2596static void stmmac_exit_fs(void)
2597{
2598 debugfs_remove(stmmac_rings_status);
e7434821 2599 debugfs_remove(stmmac_dma_cap);
7ac29055
GC		 2600 debugfs_remove(stmmac_fs_dir);
2601}
2602#endif /* CONFIG_STMMAC_DEBUG_FS */
2603
47dd7a54
GC		 2604static const struct net_device_ops stmmac_netdev_ops = {
2605 .ndo_open = stmmac_open,
2606 .ndo_start_xmit = stmmac_xmit,
2607 .ndo_stop = stmmac_release,
2608 .ndo_change_mtu = stmmac_change_mtu,
5e982f3b 2609 .ndo_fix_features = stmmac_fix_features,
01789349 2610 .ndo_set_rx_mode = stmmac_set_rx_mode,
47dd7a54
GC		 2611 .ndo_tx_timeout = stmmac_tx_timeout,
2612 .ndo_do_ioctl = stmmac_ioctl,
2613 .ndo_set_config = stmmac_config,
47dd7a54
GC		 2614#ifdef CONFIG_NET_POLL_CONTROLLER
2615 .ndo_poll_controller = stmmac_poll_controller,
2616#endif
2617 .ndo_set_mac_address = eth_mac_addr,
2618};
2619
cf3f047b
GC		 2620/**
2621 * stmmac_hw_init - Init the MAC device
32ceabca 2622 * @priv: driver private structure
cf3f047b
GC		 2623 * Description: this function detects which MAC device
2624 * (GMAC/MAC10-100) has to attached, checks the HW capability
2625 * (if supported) and sets the driver's features (for example
2626 * to use the ring or chaine mode or support the normal/enh
2627 * descriptor structure).
2628 */
2629static int stmmac_hw_init(struct stmmac_priv *priv)
2630{
c24602ef 2631 int ret;
cf3f047b
GC		 2632 struct mac_device_info *mac;
2633
2634 /* Identify the MAC HW device */
03f2eecd
MKB		 2635 if (priv->plat->has_gmac) {
2636 priv->dev->priv_flags |= IFF_UNICAST_FLT;
cf3f047b 2637 mac = dwmac1000_setup(priv->ioaddr);
03f2eecd 2638 } else {
cf3f047b 2639 mac = dwmac100_setup(priv->ioaddr);
03f2eecd 2640 }
cf3f047b
GC		 2641 if (!mac)
2642 return -ENOMEM;
2643
2644 priv->hw = mac;
2645
cf3f047b 2646 /* Get and dump the chip ID */
cffb13f4 2647 priv->synopsys_id = stmmac_get_synopsys_id(priv);
cf3f047b 2648
4a7d666a 2649 /* To use the chained or ring mode */
ceb69499 2650 if (chain_mode) {
4a7d666a
GC		 2651 priv->hw->chain = &chain_mode_ops;
2652 pr_info(" Chain mode enabled\n");
2653 priv->mode = STMMAC_CHAIN_MODE;
2654 } else {
2655 priv->hw->ring = &ring_mode_ops;
2656 pr_info(" Ring mode enabled\n");
2657 priv->mode = STMMAC_RING_MODE;
2658 }
2659
cf3f047b
GC		 2660 /* Get the HW capability (new GMAC newer than 3.50a) */
2661 priv->hw_cap_support = stmmac_get_hw_features(priv);
2662 if (priv->hw_cap_support) {
2663 pr_info(" DMA HW capability register supported");
2664
2665 /* We can override some gmac/dma configuration fields: e.g.
2666 * enh_desc, tx_coe (e.g. that are passed through the
2667 * platform) with the values from the HW capability
2668 * register (if supported).
2669 */
2670 priv->plat->enh_desc = priv->dma_cap.enh_desc;
cf3f047b 2671 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
38912bdb
DS		 2672
2673 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2674
2675 if (priv->dma_cap.rx_coe_type2)
2676 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2677 else if (priv->dma_cap.rx_coe_type1)
2678 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2679
cf3f047b
GC		 2680 } else
2681 pr_info(" No HW DMA feature register supported");
2682
61369d02
BA		 2683 /* To use alternate (extended) or normal descriptor structures */
2684 stmmac_selec_desc_mode(priv);
2685
38912bdb
DS		 2686 ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2687 if (!ret) {
ceb69499 2688 pr_warn(" RX IPC Checksum Offload not configured.\n");
38912bdb
DS		 2689 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2690 }
2691
2692 if (priv->plat->rx_coe)
2693 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2694 priv->plat->rx_coe);
cf3f047b
GC		 2695 if (priv->plat->tx_coe)
2696 pr_info(" TX Checksum insertion supported\n");
2697
2698 if (priv->plat->pmt) {
2699 pr_info(" Wake-Up On Lan supported\n");
2700 device_set_wakeup_capable(priv->device, 1);
2701 }
2702
c24602ef 2703 return 0;
cf3f047b
GC		 2704}
2705
47dd7a54 2706/**
bfab27a1
GC		 2707 * stmmac_dvr_probe
2708 * @device: device pointer
ff3dd78c
GC		 2709 * @plat_dat: platform data pointer
2710 * @addr: iobase memory address
bfab27a1
GC		 2711 * Description: this is the main probe function used to
2712 * call the alloc_etherdev, allocate the priv structure.
47dd7a54 2713 */
bfab27a1 2714struct stmmac_priv *stmmac_dvr_probe(struct device *device,
cf3f047b
GC		 2715 struct plat_stmmacenet_data *plat_dat,
2716 void __iomem *addr)
47dd7a54
GC		 2717{
2718 int ret = 0;
bfab27a1
GC		 2719 struct net_device *ndev = NULL;
2720 struct stmmac_priv *priv;
47dd7a54 2721
bfab27a1 2722 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
41de8d4c 2723 if (!ndev)
bfab27a1 2724 return NULL;
bfab27a1
GC		 2725
2726 SET_NETDEV_DEV(ndev, device);
2727
2728 priv = netdev_priv(ndev);
2729 priv->device = device;
2730 priv->dev = ndev;
47dd7a54 2731
bfab27a1 2732 ether_setup(ndev);
47dd7a54 2733
bfab27a1 2734 stmmac_set_ethtool_ops(ndev);
cf3f047b
GC		 2735 priv->pause = pause;
2736 priv->plat = plat_dat;
2737 priv->ioaddr = addr;
2738 priv->dev->base_addr = (unsigned long)addr;
2739
2740 /* Verify driver arguments */
2741 stmmac_verify_args();
bfab27a1 2742
cf3f047b 2743 /* Override with kernel parameters if supplied XXX CRS XXX
ceb69499
GC		 2744 * this needs to have multiple instances
2745 */
cf3f047b
GC		 2746 if ((phyaddr >= 0) && (phyaddr <= 31))
2747 priv->plat->phy_addr = phyaddr;
2748
62866e98
CYT		 2749 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2750 if (IS_ERR(priv->stmmac_clk)) {
2751 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2752 __func__);
c5e4ddbd 2753 ret = PTR_ERR(priv->stmmac_clk);
62866e98
CYT		 2754 goto error_clk_get;
2755 }
2756 clk_prepare_enable(priv->stmmac_clk);
2757
c5e4ddbd
CYT		 2758 priv->stmmac_rst = devm_reset_control_get(priv->device,
2759 STMMAC_RESOURCE_NAME);
2760 if (IS_ERR(priv->stmmac_rst)) {
2761 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2762 ret = -EPROBE_DEFER;
2763 goto error_hw_init;
2764 }
2765 dev_info(priv->device, "no reset control found\n");
2766 priv->stmmac_rst = NULL;
2767 }
2768 if (priv->stmmac_rst)
2769 reset_control_deassert(priv->stmmac_rst);
2770
cf3f047b 2771 /* Init MAC and get the capabilities */
c24602ef
GC		 2772 ret = stmmac_hw_init(priv);
2773 if (ret)
62866e98 2774 goto error_hw_init;
cf3f047b
GC		 2775
2776 ndev->netdev_ops = &stmmac_netdev_ops;
bfab27a1 2777
cf3f047b
GC		 2778 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2779 NETIF_F_RXCSUM;
bfab27a1
GC		 2780 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2781 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
47dd7a54
GC		 2782#ifdef STMMAC_VLAN_TAG_USED
2783 /* Both mac100 and gmac support receive VLAN tag detection */
f646968f 2784 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
47dd7a54
GC		 2785#endif
2786 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2787
47dd7a54
GC		 2788 if (flow_ctrl)
2789 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2790
62a2ab93
GC		 2791 /* Rx Watchdog is available in the COREs newer than the 3.40.
2792 * In some case, for example on bugged HW this feature
2793 * has to be disable and this can be done by passing the
2794 * riwt_off field from the platform.
2795 */
2796 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2797 priv->use_riwt = 1;
2798 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2799 }
2800
bfab27a1 2801 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
47dd7a54 2802
f8e96161 2803 spin_lock_init(&priv->lock);
a9097a96 2804 spin_lock_init(&priv->tx_lock);
f8e96161 2805
bfab27a1 2806 ret = register_netdev(ndev);
47dd7a54 2807 if (ret) {
cf3f047b 2808 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
6a81c26f 2809 goto error_netdev_register;
47dd7a54
GC		 2810 }
2811
cd7201f4
GC		 2812 /* If a specific clk_csr value is passed from the platform
2813 * this means that the CSR Clock Range selection cannot be
2814 * changed at run-time and it is fixed. Viceversa the driver'll try to
2815 * set the MDC clock dynamically according to the csr actual
2816 * clock input.
2817 */
2818 if (!priv->plat->clk_csr)
2819 stmmac_clk_csr_set(priv);
2820 else
2821 priv->clk_csr = priv->plat->clk_csr;
2822
e58bb43f
GC		 2823 stmmac_check_pcs_mode(priv);
2824
4d8f0825
BA		 2825 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2826 priv->pcs != STMMAC_PCS_RTBI) {
e58bb43f
GC		 2827 /* MDIO bus Registration */
2828 ret = stmmac_mdio_register(ndev);
2829 if (ret < 0) {
2830 pr_debug("%s: MDIO bus (id: %d) registration failed",
2831 __func__, priv->plat->bus_id);
2832 goto error_mdio_register;
2833 }
4bfcbd7a
FV		 2834 }
2835
bfab27a1 2836 return priv;
47dd7a54 2837
6a81c26f 2838error_mdio_register:
34a52f36 2839 unregister_netdev(ndev);
6a81c26f
VK		 2840error_netdev_register:
2841 netif_napi_del(&priv->napi);
62866e98
CYT		 2842error_hw_init:
2843 clk_disable_unprepare(priv->stmmac_clk);
2844error_clk_get:
34a52f36 2845 free_netdev(ndev);
47dd7a54 2846
c5e4ddbd 2847 return ERR_PTR(ret);
47dd7a54
GC		 2848}
2849
2850/**
2851 * stmmac_dvr_remove
bfab27a1 2852 * @ndev: net device pointer
47dd7a54 2853 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
bfab27a1 2854 * changes the link status, releases the DMA descriptor rings.
47dd7a54 2855 */
bfab27a1 2856int stmmac_dvr_remove(struct net_device *ndev)
47dd7a54 2857{
aec7ff27 2858 struct stmmac_priv *priv = netdev_priv(ndev);
47dd7a54
GC		 2859
2860 pr_info("%s:\n\tremoving driver", __func__);
2861
ad01b7d4
GC		 2862 priv->hw->dma->stop_rx(priv->ioaddr);
2863 priv->hw->dma->stop_tx(priv->ioaddr);
47dd7a54 2864
bfab27a1 2865 stmmac_set_mac(priv->ioaddr, false);
4d8f0825
BA		 2866 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2867 priv->pcs != STMMAC_PCS_RTBI)
e58bb43f 2868 stmmac_mdio_unregister(ndev);
47dd7a54 2869 netif_carrier_off(ndev);
47dd7a54 2870 unregister_netdev(ndev);
c5e4ddbd
CYT		 2871 if (priv->stmmac_rst)
2872 reset_control_assert(priv->stmmac_rst);
62866e98 2873 clk_disable_unprepare(priv->stmmac_clk);
47dd7a54
GC		 2874 free_netdev(ndev);
2875
2876 return 0;
2877}
2878
2879#ifdef CONFIG_PM
bfab27a1 2880int stmmac_suspend(struct net_device *ndev)
47dd7a54 2881{
874bd42d 2882 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2883 unsigned long flags;
47dd7a54 2884
874bd42d 2885 if (!ndev || !netif_running(ndev))
47dd7a54
GC		 2886 return 0;
2887
102463b1
FV		 2888 if (priv->phydev)
2889 phy_stop(priv->phydev);
2890
f8c5a875 2891 spin_lock_irqsave(&priv->lock, flags);
47dd7a54 2892
874bd42d
GC		 2893 netif_device_detach(ndev);
2894 netif_stop_queue(ndev);
47dd7a54 2895
874bd42d
GC		 2896 napi_disable(&priv->napi);
2897
2898 /* Stop TX/RX DMA */
2899 priv->hw->dma->stop_tx(priv->ioaddr);
2900 priv->hw->dma->stop_rx(priv->ioaddr);
c24602ef
GC		 2901
2902 stmmac_clear_descriptors(priv);
874bd42d
GC		 2903
2904 /* Enable Power down mode by programming the PMT regs */
89f7f2cf 2905 if (device_may_wakeup(priv->device)) {
874bd42d 2906 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
89f7f2cf
SK		 2907 priv->irq_wake = 1;
2908 } else {
bfab27a1 2909 stmmac_set_mac(priv->ioaddr, false);
db88f10a 2910 pinctrl_pm_select_sleep_state(priv->device);
ba1377ff 2911 /* Disable clock in case of PWM is off */
a630844d 2912 clk_disable_unprepare(priv->stmmac_clk);
ba1377ff 2913 }
f8c5a875 2914 spin_unlock_irqrestore(&priv->lock, flags);
47dd7a54
GC		 2915 return 0;
2916}
2917
bfab27a1 2918int stmmac_resume(struct net_device *ndev)
47dd7a54 2919{
874bd42d 2920 struct stmmac_priv *priv = netdev_priv(ndev);
f8c5a875 2921 unsigned long flags;
47dd7a54 2922
874bd42d 2923 if (!netif_running(ndev))
47dd7a54
GC		 2924 return 0;
2925
f8c5a875 2926 spin_lock_irqsave(&priv->lock, flags);
c4433be6 2927
47dd7a54
GC		 2928 /* Power Down bit, into the PM register, is cleared
2929 * automatically as soon as a magic packet or a Wake-up frame
2930 * is received. Anyway, it's better to manually clear
2931 * this bit because it can generate problems while resuming
ceb69499
GC		 2932 * from another devices (e.g. serial console).
2933 */
623997fb 2934 if (device_may_wakeup(priv->device)) {
543876c9 2935 priv->hw->mac->pmt(priv->ioaddr, 0);
89f7f2cf 2936 priv->irq_wake = 0;
623997fb 2937 } else {
db88f10a 2938 pinctrl_pm_select_default_state(priv->device);
ba1377ff 2939 /* enable the clk prevously disabled */
a630844d 2940 clk_prepare_enable(priv->stmmac_clk);
623997fb
SK		 2941 /* reset the phy so that it's ready */
2942 if (priv->mii)
2943 stmmac_mdio_reset(priv->mii);
2944 }
47dd7a54 2945
874bd42d 2946 netif_device_attach(ndev);
47dd7a54 2947
623997fb 2948 stmmac_hw_setup(ndev);
47dd7a54 2949
47dd7a54
GC		 2950 napi_enable(&priv->napi);
2951
874bd42d 2952 netif_start_queue(ndev);
47dd7a54 2953
f8c5a875 2954 spin_unlock_irqrestore(&priv->lock, flags);
102463b1
FV		 2955
2956 if (priv->phydev)
2957 phy_start(priv->phydev);
2958
47dd7a54
GC		 2959 return 0;
2960}
874bd42d 2961#endif /* CONFIG_PM */
47dd7a54 2962
33d5e332
GC		 2963/* Driver can be configured w/ and w/ both PCI and Platf drivers
2964 * depending on the configuration selected.
2965 */
ba27ec66
GC		 2966static int __init stmmac_init(void)
2967{
493682b8 2968 int ret;
ba27ec66 2969
493682b8
KK		 2970 ret = stmmac_register_platform();
2971 if (ret)
2972 goto err;
2973 ret = stmmac_register_pci();
2974 if (ret)
2975 goto err_pci;
33d5e332 2976 return 0;
493682b8
KK		 2977err_pci:
2978 stmmac_unregister_platform();
2979err:
2980 pr_err("stmmac: driver registration failed\n");
2981 return ret;
ba27ec66
GC		 2982}
2983
2984static void __exit stmmac_exit(void)
2985{
33d5e332
GC		 2986 stmmac_unregister_platform();
2987 stmmac_unregister_pci();
ba27ec66
GC		 2988}
2989
2990module_init(stmmac_init);
2991module_exit(stmmac_exit);
2992
47dd7a54
GC		 2993#ifndef MODULE
2994static int __init stmmac_cmdline_opt(char *str)
2995{
2996 char *opt;
2997
2998 if (!str || !*str)
2999 return -EINVAL;
3000 while ((opt = strsep(&str, ",")) != NULL) {
f3240e28 3001 if (!strncmp(opt, "debug:", 6)) {
ea2ab871 3002 if (kstrtoint(opt + 6, 0, &debug))
f3240e28
GC		 3003 goto err;
3004 } else if (!strncmp(opt, "phyaddr:", 8)) {
ea2ab871 3005 if (kstrtoint(opt + 8, 0, &phyaddr))
f3240e28
GC		 3006 goto err;
3007 } else if (!strncmp(opt, "dma_txsize:", 11)) {
ea2ab871 3008 if (kstrtoint(opt + 11, 0, &dma_txsize))
f3240e28
GC		 3009 goto err;
3010 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
ea2ab871 3011 if (kstrtoint(opt + 11, 0, &dma_rxsize))
f3240e28
GC		 3012 goto err;
3013 } else if (!strncmp(opt, "buf_sz:", 7)) {
ea2ab871 3014 if (kstrtoint(opt + 7, 0, &buf_sz))
f3240e28
GC		 3015 goto err;
3016 } else if (!strncmp(opt, "tc:", 3)) {
ea2ab871 3017 if (kstrtoint(opt + 3, 0, &tc))
f3240e28
GC		 3018 goto err;
3019 } else if (!strncmp(opt, "watchdog:", 9)) {
ea2ab871 3020 if (kstrtoint(opt + 9, 0, &watchdog))
f3240e28
GC		 3021 goto err;
3022 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
ea2ab871 3023 if (kstrtoint(opt + 10, 0, &flow_ctrl))
f3240e28
GC		 3024 goto err;
3025 } else if (!strncmp(opt, "pause:", 6)) {
ea2ab871 3026 if (kstrtoint(opt + 6, 0, &pause))
f3240e28 3027 goto err;
506f669c 3028 } else if (!strncmp(opt, "eee_timer:", 10)) {
d765955d
GC		 3029 if (kstrtoint(opt + 10, 0, &eee_timer))
3030 goto err;
4a7d666a
GC		 3031 } else if (!strncmp(opt, "chain_mode:", 11)) {
3032 if (kstrtoint(opt + 11, 0, &chain_mode))
3033 goto err;
f3240e28 3034 }
47dd7a54
GC		 3035 }
3036 return 0;
f3240e28
GC		 3037
3038err:
3039 pr_err("%s: ERROR broken module parameter conversion", __func__);
3040 return -EINVAL;
47dd7a54
GC		 3041}
3042
3043__setup("stmmaceth=", stmmac_cmdline_opt);
ceb69499 3044#endif /* MODULE */
6fc0d0f2
GC		 3045
3046MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3047MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3048MODULE_LICENSE("GPL");
ubuntu-bionic-kernel mirror