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1da177e4 LT |
1 | /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $ |
2 | * sungem.c: Sun GEM ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com) | |
6aa20a22 | 5 | * |
1da177e4 LT |
6 | * Support for Apple GMAC and assorted PHYs, WOL, Power Management |
7 | * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org) | |
8 | * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp. | |
9 | * | |
10 | * NAPI and NETPOLL support | |
11 | * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com) | |
6aa20a22 | 12 | * |
1da177e4 LT |
13 | */ |
14 | ||
c6c75988 JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/fcntl.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/in.h> | |
d43c36dc | 24 | #include <linux/sched.h> |
1da177e4 LT |
25 | #include <linux/string.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/pci.h> | |
1e7f0bd8 | 30 | #include <linux/dma-mapping.h> |
1da177e4 LT |
31 | #include <linux/netdevice.h> |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/crc32.h> | |
37 | #include <linux/random.h> | |
38 | #include <linux/workqueue.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/bitops.h> | |
d7fe0f24 | 41 | #include <linux/mm.h> |
5a0e3ad6 | 42 | #include <linux/gfp.h> |
1da177e4 LT |
43 | |
44 | #include <asm/system.h> | |
45 | #include <asm/io.h> | |
46 | #include <asm/byteorder.h> | |
47 | #include <asm/uaccess.h> | |
48 | #include <asm/irq.h> | |
49 | ||
dadb830d | 50 | #ifdef CONFIG_SPARC |
1da177e4 | 51 | #include <asm/idprom.h> |
5903417c | 52 | #include <asm/prom.h> |
1da177e4 LT |
53 | #endif |
54 | ||
55 | #ifdef CONFIG_PPC_PMAC | |
56 | #include <asm/pci-bridge.h> | |
5903417c | 57 | #include <asm/prom.h> |
1da177e4 LT |
58 | #include <asm/machdep.h> |
59 | #include <asm/pmac_feature.h> | |
60 | #endif | |
61 | ||
2bb69841 | 62 | #include <linux/sungem_phy.h> |
1da177e4 LT |
63 | #include "sungem.h" |
64 | ||
65 | /* Stripping FCS is causing problems, disabled for now */ | |
66 | #undef STRIP_FCS | |
67 | ||
68 | #define DEFAULT_MSG (NETIF_MSG_DRV | \ | |
69 | NETIF_MSG_PROBE | \ | |
70 | NETIF_MSG_LINK) | |
71 | ||
72 | #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \ | |
73 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \ | |
63ea998a BH |
74 | SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \ |
75 | SUPPORTED_Pause | SUPPORTED_Autoneg) | |
1da177e4 LT |
76 | |
77 | #define DRV_NAME "sungem" | |
fe09bb61 BH |
78 | #define DRV_VERSION "1.0" |
79 | #define DRV_AUTHOR "David S. Miller <davem@redhat.com>" | |
1da177e4 LT |
80 | |
81 | static char version[] __devinitdata = | |
fe09bb61 | 82 | DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n"; |
1da177e4 LT |
83 | |
84 | MODULE_AUTHOR(DRV_AUTHOR); | |
85 | MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver"); | |
86 | MODULE_LICENSE("GPL"); | |
87 | ||
88 | #define GEM_MODULE_NAME "gem" | |
1da177e4 | 89 | |
a3aa1884 | 90 | static DEFINE_PCI_DEVICE_TABLE(gem_pci_tbl) = { |
1da177e4 LT |
91 | { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM, |
92 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
93 | ||
94 | /* These models only differ from the original GEM in | |
95 | * that their tx/rx fifos are of a different size and | |
96 | * they only support 10/100 speeds. -DaveM | |
6aa20a22 | 97 | * |
1da177e4 LT |
98 | * Apple's GMAC does support gigabit on machines with |
99 | * the BCM54xx PHYs. -BenH | |
100 | */ | |
101 | { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM, | |
102 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
103 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC, | |
104 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
105 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP, | |
106 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
107 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2, | |
108 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
109 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC, | |
110 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
111 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM, | |
112 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
7fce260a OJ |
113 | { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC, |
114 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
1da177e4 LT |
115 | {0, } |
116 | }; | |
117 | ||
118 | MODULE_DEVICE_TABLE(pci, gem_pci_tbl); | |
119 | ||
120 | static u16 __phy_read(struct gem *gp, int phy_addr, int reg) | |
121 | { | |
122 | u32 cmd; | |
123 | int limit = 10000; | |
124 | ||
125 | cmd = (1 << 30); | |
126 | cmd |= (2 << 28); | |
127 | cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; | |
128 | cmd |= (reg << 18) & MIF_FRAME_REGAD; | |
129 | cmd |= (MIF_FRAME_TAMSB); | |
130 | writel(cmd, gp->regs + MIF_FRAME); | |
131 | ||
46578a69 | 132 | while (--limit) { |
1da177e4 LT |
133 | cmd = readl(gp->regs + MIF_FRAME); |
134 | if (cmd & MIF_FRAME_TALSB) | |
135 | break; | |
136 | ||
137 | udelay(10); | |
138 | } | |
139 | ||
140 | if (!limit) | |
141 | cmd = 0xffff; | |
142 | ||
143 | return cmd & MIF_FRAME_DATA; | |
144 | } | |
145 | ||
146 | static inline int _phy_read(struct net_device *dev, int mii_id, int reg) | |
147 | { | |
8f15ea42 | 148 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
149 | return __phy_read(gp, mii_id, reg); |
150 | } | |
151 | ||
152 | static inline u16 phy_read(struct gem *gp, int reg) | |
153 | { | |
154 | return __phy_read(gp, gp->mii_phy_addr, reg); | |
155 | } | |
156 | ||
157 | static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val) | |
158 | { | |
159 | u32 cmd; | |
160 | int limit = 10000; | |
161 | ||
162 | cmd = (1 << 30); | |
163 | cmd |= (1 << 28); | |
164 | cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD; | |
165 | cmd |= (reg << 18) & MIF_FRAME_REGAD; | |
166 | cmd |= (MIF_FRAME_TAMSB); | |
167 | cmd |= (val & MIF_FRAME_DATA); | |
168 | writel(cmd, gp->regs + MIF_FRAME); | |
169 | ||
170 | while (limit--) { | |
171 | cmd = readl(gp->regs + MIF_FRAME); | |
172 | if (cmd & MIF_FRAME_TALSB) | |
173 | break; | |
174 | ||
175 | udelay(10); | |
176 | } | |
177 | } | |
178 | ||
179 | static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val) | |
180 | { | |
8f15ea42 | 181 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
182 | __phy_write(gp, mii_id, reg, val & 0xffff); |
183 | } | |
184 | ||
185 | static inline void phy_write(struct gem *gp, int reg, u16 val) | |
186 | { | |
187 | __phy_write(gp, gp->mii_phy_addr, reg, val); | |
188 | } | |
189 | ||
190 | static inline void gem_enable_ints(struct gem *gp) | |
191 | { | |
192 | /* Enable all interrupts but TXDONE */ | |
193 | writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); | |
194 | } | |
195 | ||
196 | static inline void gem_disable_ints(struct gem *gp) | |
197 | { | |
198 | /* Disable all interrupts, including TXDONE */ | |
199 | writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); | |
fe09bb61 | 200 | (void)readl(gp->regs + GREG_IMASK); /* write posting */ |
1da177e4 LT |
201 | } |
202 | ||
203 | static void gem_get_cell(struct gem *gp) | |
204 | { | |
205 | BUG_ON(gp->cell_enabled < 0); | |
206 | gp->cell_enabled++; | |
207 | #ifdef CONFIG_PPC_PMAC | |
208 | if (gp->cell_enabled == 1) { | |
209 | mb(); | |
210 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1); | |
211 | udelay(10); | |
212 | } | |
213 | #endif /* CONFIG_PPC_PMAC */ | |
214 | } | |
215 | ||
216 | /* Turn off the chip's clock */ | |
217 | static void gem_put_cell(struct gem *gp) | |
218 | { | |
219 | BUG_ON(gp->cell_enabled <= 0); | |
220 | gp->cell_enabled--; | |
221 | #ifdef CONFIG_PPC_PMAC | |
222 | if (gp->cell_enabled == 0) { | |
223 | mb(); | |
224 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0); | |
225 | udelay(10); | |
226 | } | |
227 | #endif /* CONFIG_PPC_PMAC */ | |
228 | } | |
229 | ||
fe09bb61 BH |
230 | static inline void gem_netif_stop(struct gem *gp) |
231 | { | |
232 | gp->dev->trans_start = jiffies; /* prevent tx timeout */ | |
233 | napi_disable(&gp->napi); | |
234 | netif_tx_disable(gp->dev); | |
235 | } | |
236 | ||
237 | static inline void gem_netif_start(struct gem *gp) | |
238 | { | |
239 | /* NOTE: unconditional netif_wake_queue is only | |
240 | * appropriate so long as all callers are assured to | |
241 | * have free tx slots. | |
242 | */ | |
243 | netif_wake_queue(gp->dev); | |
244 | napi_enable(&gp->napi); | |
245 | } | |
246 | ||
247 | static void gem_schedule_reset(struct gem *gp) | |
248 | { | |
249 | gp->reset_task_pending = 1; | |
250 | schedule_work(&gp->reset_task); | |
251 | } | |
252 | ||
1da177e4 LT |
253 | static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) |
254 | { | |
255 | if (netif_msg_intr(gp)) | |
256 | printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name); | |
257 | } | |
258 | ||
259 | static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
260 | { | |
261 | u32 pcs_istat = readl(gp->regs + PCS_ISTAT); | |
262 | u32 pcs_miistat; | |
263 | ||
264 | if (netif_msg_intr(gp)) | |
265 | printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n", | |
266 | gp->dev->name, pcs_istat); | |
267 | ||
268 | if (!(pcs_istat & PCS_ISTAT_LSC)) { | |
c6c75988 | 269 | netdev_err(dev, "PCS irq but no link status change???\n"); |
1da177e4 LT |
270 | return 0; |
271 | } | |
272 | ||
273 | /* The link status bit latches on zero, so you must | |
274 | * read it twice in such a case to see a transition | |
275 | * to the link being up. | |
276 | */ | |
277 | pcs_miistat = readl(gp->regs + PCS_MIISTAT); | |
278 | if (!(pcs_miistat & PCS_MIISTAT_LS)) | |
279 | pcs_miistat |= | |
280 | (readl(gp->regs + PCS_MIISTAT) & | |
281 | PCS_MIISTAT_LS); | |
282 | ||
283 | if (pcs_miistat & PCS_MIISTAT_ANC) { | |
284 | /* The remote-fault indication is only valid | |
285 | * when autoneg has completed. | |
286 | */ | |
287 | if (pcs_miistat & PCS_MIISTAT_RF) | |
c6c75988 | 288 | netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n"); |
1da177e4 | 289 | else |
c6c75988 | 290 | netdev_info(dev, "PCS AutoNEG complete\n"); |
1da177e4 LT |
291 | } |
292 | ||
293 | if (pcs_miistat & PCS_MIISTAT_LS) { | |
c6c75988 | 294 | netdev_info(dev, "PCS link is now up\n"); |
1da177e4 LT |
295 | netif_carrier_on(gp->dev); |
296 | } else { | |
c6c75988 | 297 | netdev_info(dev, "PCS link is now down\n"); |
1da177e4 LT |
298 | netif_carrier_off(gp->dev); |
299 | /* If this happens and the link timer is not running, | |
300 | * reset so we re-negotiate. | |
301 | */ | |
302 | if (!timer_pending(&gp->link_timer)) | |
303 | return 1; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
310 | { | |
311 | u32 txmac_stat = readl(gp->regs + MAC_TXSTAT); | |
312 | ||
313 | if (netif_msg_intr(gp)) | |
314 | printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n", | |
315 | gp->dev->name, txmac_stat); | |
316 | ||
317 | /* Defer timer expiration is quite normal, | |
318 | * don't even log the event. | |
319 | */ | |
320 | if ((txmac_stat & MAC_TXSTAT_DTE) && | |
321 | !(txmac_stat & ~MAC_TXSTAT_DTE)) | |
322 | return 0; | |
323 | ||
324 | if (txmac_stat & MAC_TXSTAT_URUN) { | |
c6c75988 | 325 | netdev_err(dev, "TX MAC xmit underrun\n"); |
aae7c473 | 326 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
327 | } |
328 | ||
329 | if (txmac_stat & MAC_TXSTAT_MPE) { | |
c6c75988 | 330 | netdev_err(dev, "TX MAC max packet size error\n"); |
aae7c473 | 331 | dev->stats.tx_errors++; |
1da177e4 LT |
332 | } |
333 | ||
334 | /* The rest are all cases of one of the 16-bit TX | |
335 | * counters expiring. | |
336 | */ | |
337 | if (txmac_stat & MAC_TXSTAT_NCE) | |
aae7c473 | 338 | dev->stats.collisions += 0x10000; |
1da177e4 LT |
339 | |
340 | if (txmac_stat & MAC_TXSTAT_ECE) { | |
aae7c473 DK |
341 | dev->stats.tx_aborted_errors += 0x10000; |
342 | dev->stats.collisions += 0x10000; | |
1da177e4 LT |
343 | } |
344 | ||
345 | if (txmac_stat & MAC_TXSTAT_LCE) { | |
aae7c473 DK |
346 | dev->stats.tx_aborted_errors += 0x10000; |
347 | dev->stats.collisions += 0x10000; | |
1da177e4 LT |
348 | } |
349 | ||
350 | /* We do not keep track of MAC_TXSTAT_FCE and | |
351 | * MAC_TXSTAT_PCE events. | |
352 | */ | |
353 | return 0; | |
354 | } | |
355 | ||
356 | /* When we get a RX fifo overflow, the RX unit in GEM is probably hung | |
357 | * so we do the following. | |
358 | * | |
359 | * If any part of the reset goes wrong, we return 1 and that causes the | |
360 | * whole chip to be reset. | |
361 | */ | |
362 | static int gem_rxmac_reset(struct gem *gp) | |
363 | { | |
364 | struct net_device *dev = gp->dev; | |
365 | int limit, i; | |
366 | u64 desc_dma; | |
367 | u32 val; | |
368 | ||
369 | /* First, reset & disable MAC RX. */ | |
370 | writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); | |
371 | for (limit = 0; limit < 5000; limit++) { | |
372 | if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD)) | |
373 | break; | |
374 | udelay(10); | |
375 | } | |
376 | if (limit == 5000) { | |
c6c75988 | 377 | netdev_err(dev, "RX MAC will not reset, resetting whole chip\n"); |
1da177e4 LT |
378 | return 1; |
379 | } | |
380 | ||
381 | writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, | |
382 | gp->regs + MAC_RXCFG); | |
383 | for (limit = 0; limit < 5000; limit++) { | |
384 | if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB)) | |
385 | break; | |
386 | udelay(10); | |
387 | } | |
388 | if (limit == 5000) { | |
c6c75988 | 389 | netdev_err(dev, "RX MAC will not disable, resetting whole chip\n"); |
1da177e4 LT |
390 | return 1; |
391 | } | |
392 | ||
393 | /* Second, disable RX DMA. */ | |
394 | writel(0, gp->regs + RXDMA_CFG); | |
395 | for (limit = 0; limit < 5000; limit++) { | |
396 | if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE)) | |
397 | break; | |
398 | udelay(10); | |
399 | } | |
400 | if (limit == 5000) { | |
c6c75988 | 401 | netdev_err(dev, "RX DMA will not disable, resetting whole chip\n"); |
1da177e4 LT |
402 | return 1; |
403 | } | |
404 | ||
405 | udelay(5000); | |
406 | ||
407 | /* Execute RX reset command. */ | |
408 | writel(gp->swrst_base | GREG_SWRST_RXRST, | |
409 | gp->regs + GREG_SWRST); | |
410 | for (limit = 0; limit < 5000; limit++) { | |
411 | if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST)) | |
412 | break; | |
413 | udelay(10); | |
414 | } | |
415 | if (limit == 5000) { | |
c6c75988 | 416 | netdev_err(dev, "RX reset command will not execute, resetting whole chip\n"); |
1da177e4 LT |
417 | return 1; |
418 | } | |
419 | ||
420 | /* Refresh the RX ring. */ | |
421 | for (i = 0; i < RX_RING_SIZE; i++) { | |
422 | struct gem_rxd *rxd = &gp->init_block->rxd[i]; | |
423 | ||
424 | if (gp->rx_skbs[i] == NULL) { | |
c6c75988 | 425 | netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n"); |
1da177e4 LT |
426 | return 1; |
427 | } | |
428 | ||
429 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
430 | } | |
431 | gp->rx_new = gp->rx_old = 0; | |
432 | ||
433 | /* Now we must reprogram the rest of RX unit. */ | |
434 | desc_dma = (u64) gp->gblock_dvma; | |
435 | desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); | |
436 | writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); | |
437 | writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); | |
438 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
439 | val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | | |
440 | ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128); | |
441 | writel(val, gp->regs + RXDMA_CFG); | |
442 | if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) | |
443 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
444 | ((8 << 12) & RXDMA_BLANK_ITIME)), | |
445 | gp->regs + RXDMA_BLANK); | |
446 | else | |
447 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
448 | ((4 << 12) & RXDMA_BLANK_ITIME)), | |
449 | gp->regs + RXDMA_BLANK); | |
450 | val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); | |
451 | val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); | |
452 | writel(val, gp->regs + RXDMA_PTHRESH); | |
453 | val = readl(gp->regs + RXDMA_CFG); | |
454 | writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
455 | writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); | |
456 | val = readl(gp->regs + MAC_RXCFG); | |
457 | writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
463 | { | |
464 | u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT); | |
465 | int ret = 0; | |
466 | ||
467 | if (netif_msg_intr(gp)) | |
468 | printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n", | |
469 | gp->dev->name, rxmac_stat); | |
470 | ||
471 | if (rxmac_stat & MAC_RXSTAT_OFLW) { | |
472 | u32 smac = readl(gp->regs + MAC_SMACHINE); | |
473 | ||
c6c75988 | 474 | netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac); |
aae7c473 DK |
475 | dev->stats.rx_over_errors++; |
476 | dev->stats.rx_fifo_errors++; | |
1da177e4 LT |
477 | |
478 | ret = gem_rxmac_reset(gp); | |
479 | } | |
480 | ||
481 | if (rxmac_stat & MAC_RXSTAT_ACE) | |
aae7c473 | 482 | dev->stats.rx_frame_errors += 0x10000; |
1da177e4 LT |
483 | |
484 | if (rxmac_stat & MAC_RXSTAT_CCE) | |
aae7c473 | 485 | dev->stats.rx_crc_errors += 0x10000; |
1da177e4 LT |
486 | |
487 | if (rxmac_stat & MAC_RXSTAT_LCE) | |
aae7c473 | 488 | dev->stats.rx_length_errors += 0x10000; |
1da177e4 LT |
489 | |
490 | /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE | |
491 | * events. | |
492 | */ | |
493 | return ret; | |
494 | } | |
495 | ||
496 | static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
497 | { | |
498 | u32 mac_cstat = readl(gp->regs + MAC_CSTAT); | |
499 | ||
500 | if (netif_msg_intr(gp)) | |
501 | printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n", | |
502 | gp->dev->name, mac_cstat); | |
503 | ||
504 | /* This interrupt is just for pause frame and pause | |
505 | * tracking. It is useful for diagnostics and debug | |
506 | * but probably by default we will mask these events. | |
507 | */ | |
508 | if (mac_cstat & MAC_CSTAT_PS) | |
509 | gp->pause_entered++; | |
510 | ||
511 | if (mac_cstat & MAC_CSTAT_PRCV) | |
512 | gp->pause_last_time_recvd = (mac_cstat >> 16); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
518 | { | |
519 | u32 mif_status = readl(gp->regs + MIF_STATUS); | |
520 | u32 reg_val, changed_bits; | |
521 | ||
522 | reg_val = (mif_status & MIF_STATUS_DATA) >> 16; | |
523 | changed_bits = (mif_status & MIF_STATUS_STAT); | |
524 | ||
525 | gem_handle_mif_event(gp, reg_val, changed_bits); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status) | |
531 | { | |
532 | u32 pci_estat = readl(gp->regs + GREG_PCIESTAT); | |
533 | ||
534 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && | |
535 | gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
c6c75988 | 536 | netdev_err(dev, "PCI error [%04x]", pci_estat); |
1da177e4 LT |
537 | |
538 | if (pci_estat & GREG_PCIESTAT_BADACK) | |
c6c75988 | 539 | pr_cont(" <No ACK64# during ABS64 cycle>"); |
1da177e4 | 540 | if (pci_estat & GREG_PCIESTAT_DTRTO) |
c6c75988 | 541 | pr_cont(" <Delayed transaction timeout>"); |
1da177e4 | 542 | if (pci_estat & GREG_PCIESTAT_OTHER) |
c6c75988 JP |
543 | pr_cont(" <other>"); |
544 | pr_cont("\n"); | |
1da177e4 LT |
545 | } else { |
546 | pci_estat |= GREG_PCIESTAT_OTHER; | |
c6c75988 | 547 | netdev_err(dev, "PCI error\n"); |
1da177e4 LT |
548 | } |
549 | ||
550 | if (pci_estat & GREG_PCIESTAT_OTHER) { | |
551 | u16 pci_cfg_stat; | |
552 | ||
553 | /* Interrogate PCI config space for the | |
554 | * true cause. | |
555 | */ | |
556 | pci_read_config_word(gp->pdev, PCI_STATUS, | |
557 | &pci_cfg_stat); | |
c6c75988 JP |
558 | netdev_err(dev, "Read PCI cfg space status [%04x]\n", |
559 | pci_cfg_stat); | |
1da177e4 | 560 | if (pci_cfg_stat & PCI_STATUS_PARITY) |
c6c75988 | 561 | netdev_err(dev, "PCI parity error detected\n"); |
1da177e4 | 562 | if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT) |
c6c75988 | 563 | netdev_err(dev, "PCI target abort\n"); |
1da177e4 | 564 | if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT) |
c6c75988 | 565 | netdev_err(dev, "PCI master acks target abort\n"); |
1da177e4 | 566 | if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT) |
c6c75988 | 567 | netdev_err(dev, "PCI master abort\n"); |
1da177e4 | 568 | if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR) |
c6c75988 | 569 | netdev_err(dev, "PCI system error SERR#\n"); |
1da177e4 | 570 | if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY) |
c6c75988 | 571 | netdev_err(dev, "PCI parity error\n"); |
1da177e4 LT |
572 | |
573 | /* Write the error bits back to clear them. */ | |
574 | pci_cfg_stat &= (PCI_STATUS_PARITY | | |
575 | PCI_STATUS_SIG_TARGET_ABORT | | |
576 | PCI_STATUS_REC_TARGET_ABORT | | |
577 | PCI_STATUS_REC_MASTER_ABORT | | |
578 | PCI_STATUS_SIG_SYSTEM_ERROR | | |
579 | PCI_STATUS_DETECTED_PARITY); | |
580 | pci_write_config_word(gp->pdev, | |
581 | PCI_STATUS, pci_cfg_stat); | |
582 | } | |
583 | ||
584 | /* For all PCI errors, we should reset the chip. */ | |
585 | return 1; | |
586 | } | |
587 | ||
588 | /* All non-normal interrupt conditions get serviced here. | |
589 | * Returns non-zero if we should just exit the interrupt | |
590 | * handler right now (ie. if we reset the card which invalidates | |
591 | * all of the other original irq status bits). | |
592 | */ | |
593 | static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status) | |
594 | { | |
595 | if (gem_status & GREG_STAT_RXNOBUF) { | |
596 | /* Frame arrived, no free RX buffers available. */ | |
597 | if (netif_msg_rx_err(gp)) | |
598 | printk(KERN_DEBUG "%s: no buffer for rx frame\n", | |
599 | gp->dev->name); | |
aae7c473 | 600 | dev->stats.rx_dropped++; |
1da177e4 LT |
601 | } |
602 | ||
603 | if (gem_status & GREG_STAT_RXTAGERR) { | |
604 | /* corrupt RX tag framing */ | |
605 | if (netif_msg_rx_err(gp)) | |
606 | printk(KERN_DEBUG "%s: corrupt rx tag framing\n", | |
607 | gp->dev->name); | |
aae7c473 | 608 | dev->stats.rx_errors++; |
1da177e4 | 609 | |
fe09bb61 | 610 | return 1; |
1da177e4 LT |
611 | } |
612 | ||
613 | if (gem_status & GREG_STAT_PCS) { | |
614 | if (gem_pcs_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 615 | return 1; |
1da177e4 LT |
616 | } |
617 | ||
618 | if (gem_status & GREG_STAT_TXMAC) { | |
619 | if (gem_txmac_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 620 | return 1; |
1da177e4 LT |
621 | } |
622 | ||
623 | if (gem_status & GREG_STAT_RXMAC) { | |
624 | if (gem_rxmac_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 625 | return 1; |
1da177e4 LT |
626 | } |
627 | ||
628 | if (gem_status & GREG_STAT_MAC) { | |
629 | if (gem_mac_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 630 | return 1; |
1da177e4 LT |
631 | } |
632 | ||
633 | if (gem_status & GREG_STAT_MIF) { | |
634 | if (gem_mif_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 635 | return 1; |
1da177e4 LT |
636 | } |
637 | ||
638 | if (gem_status & GREG_STAT_PCIERR) { | |
639 | if (gem_pci_interrupt(dev, gp, gem_status)) | |
fe09bb61 | 640 | return 1; |
1da177e4 LT |
641 | } |
642 | ||
643 | return 0; | |
1da177e4 LT |
644 | } |
645 | ||
646 | static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status) | |
647 | { | |
648 | int entry, limit; | |
649 | ||
1da177e4 LT |
650 | entry = gp->tx_old; |
651 | limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT); | |
652 | while (entry != limit) { | |
653 | struct sk_buff *skb; | |
654 | struct gem_txd *txd; | |
655 | dma_addr_t dma_addr; | |
656 | u32 dma_len; | |
657 | int frag; | |
658 | ||
659 | if (netif_msg_tx_done(gp)) | |
660 | printk(KERN_DEBUG "%s: tx done, slot %d\n", | |
661 | gp->dev->name, entry); | |
662 | skb = gp->tx_skbs[entry]; | |
663 | if (skb_shinfo(skb)->nr_frags) { | |
664 | int last = entry + skb_shinfo(skb)->nr_frags; | |
665 | int walk = entry; | |
666 | int incomplete = 0; | |
667 | ||
668 | last &= (TX_RING_SIZE - 1); | |
669 | for (;;) { | |
670 | walk = NEXT_TX(walk); | |
671 | if (walk == limit) | |
672 | incomplete = 1; | |
673 | if (walk == last) | |
674 | break; | |
675 | } | |
676 | if (incomplete) | |
677 | break; | |
678 | } | |
679 | gp->tx_skbs[entry] = NULL; | |
aae7c473 | 680 | dev->stats.tx_bytes += skb->len; |
1da177e4 LT |
681 | |
682 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { | |
683 | txd = &gp->init_block->txd[entry]; | |
684 | ||
685 | dma_addr = le64_to_cpu(txd->buffer); | |
686 | dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ; | |
687 | ||
688 | pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); | |
689 | entry = NEXT_TX(entry); | |
690 | } | |
691 | ||
aae7c473 | 692 | dev->stats.tx_packets++; |
fe09bb61 | 693 | dev_kfree_skb(skb); |
1da177e4 LT |
694 | } |
695 | gp->tx_old = entry; | |
696 | ||
fe09bb61 BH |
697 | /* Need to make the tx_old update visible to gem_start_xmit() |
698 | * before checking for netif_queue_stopped(). Without the | |
699 | * memory barrier, there is a small possibility that gem_start_xmit() | |
700 | * will miss it and cause the queue to be stopped forever. | |
701 | */ | |
702 | smp_mb(); | |
703 | ||
704 | if (unlikely(netif_queue_stopped(dev) && | |
705 | TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) { | |
706 | struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); | |
707 | ||
708 | __netif_tx_lock(txq, smp_processor_id()); | |
709 | if (netif_queue_stopped(dev) && | |
710 | TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) | |
711 | netif_wake_queue(dev); | |
712 | __netif_tx_unlock(txq); | |
713 | } | |
1da177e4 LT |
714 | } |
715 | ||
716 | static __inline__ void gem_post_rxds(struct gem *gp, int limit) | |
717 | { | |
718 | int cluster_start, curr, count, kick; | |
719 | ||
720 | cluster_start = curr = (gp->rx_new & ~(4 - 1)); | |
721 | count = 0; | |
722 | kick = -1; | |
723 | wmb(); | |
724 | while (curr != limit) { | |
725 | curr = NEXT_RX(curr); | |
726 | if (++count == 4) { | |
727 | struct gem_rxd *rxd = | |
728 | &gp->init_block->rxd[cluster_start]; | |
729 | for (;;) { | |
730 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
731 | rxd++; | |
732 | cluster_start = NEXT_RX(cluster_start); | |
733 | if (cluster_start == curr) | |
734 | break; | |
735 | } | |
736 | kick = curr; | |
737 | count = 0; | |
738 | } | |
739 | } | |
740 | if (kick >= 0) { | |
741 | mb(); | |
742 | writel(kick, gp->regs + RXDMA_KICK); | |
743 | } | |
744 | } | |
745 | ||
fe09bb61 BH |
746 | #define ALIGNED_RX_SKB_ADDR(addr) \ |
747 | ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr)) | |
748 | static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size, | |
749 | gfp_t gfp_flags) | |
750 | { | |
751 | struct sk_buff *skb = alloc_skb(size + 64, gfp_flags); | |
752 | ||
753 | if (likely(skb)) { | |
754 | unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data); | |
755 | skb_reserve(skb, offset); | |
756 | skb->dev = dev; | |
757 | } | |
758 | return skb; | |
759 | } | |
760 | ||
1da177e4 LT |
761 | static int gem_rx(struct gem *gp, int work_to_do) |
762 | { | |
aae7c473 | 763 | struct net_device *dev = gp->dev; |
1da177e4 LT |
764 | int entry, drops, work_done = 0; |
765 | u32 done; | |
439104b3 | 766 | __sum16 csum; |
1da177e4 LT |
767 | |
768 | if (netif_msg_rx_status(gp)) | |
769 | printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n", | |
770 | gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new); | |
771 | ||
772 | entry = gp->rx_new; | |
773 | drops = 0; | |
774 | done = readl(gp->regs + RXDMA_DONE); | |
775 | for (;;) { | |
776 | struct gem_rxd *rxd = &gp->init_block->rxd[entry]; | |
777 | struct sk_buff *skb; | |
439104b3 | 778 | u64 status = le64_to_cpu(rxd->status_word); |
1da177e4 LT |
779 | dma_addr_t dma_addr; |
780 | int len; | |
781 | ||
782 | if ((status & RXDCTRL_OWN) != 0) | |
783 | break; | |
784 | ||
785 | if (work_done >= RX_RING_SIZE || work_done >= work_to_do) | |
786 | break; | |
787 | ||
788 | /* When writing back RX descriptor, GEM writes status | |
3ad2f3fb | 789 | * then buffer address, possibly in separate transactions. |
1da177e4 LT |
790 | * If we don't wait for the chip to write both, we could |
791 | * post a new buffer to this descriptor then have GEM spam | |
792 | * on the buffer address. We sync on the RX completion | |
793 | * register to prevent this from happening. | |
794 | */ | |
795 | if (entry == done) { | |
796 | done = readl(gp->regs + RXDMA_DONE); | |
797 | if (entry == done) | |
798 | break; | |
799 | } | |
800 | ||
801 | /* We can now account for the work we're about to do */ | |
802 | work_done++; | |
803 | ||
804 | skb = gp->rx_skbs[entry]; | |
805 | ||
806 | len = (status & RXDCTRL_BUFSZ) >> 16; | |
807 | if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) { | |
aae7c473 | 808 | dev->stats.rx_errors++; |
1da177e4 | 809 | if (len < ETH_ZLEN) |
aae7c473 | 810 | dev->stats.rx_length_errors++; |
1da177e4 | 811 | if (len & RXDCTRL_BAD) |
aae7c473 | 812 | dev->stats.rx_crc_errors++; |
1da177e4 LT |
813 | |
814 | /* We'll just return it to GEM. */ | |
815 | drop_it: | |
aae7c473 | 816 | dev->stats.rx_dropped++; |
1da177e4 LT |
817 | goto next; |
818 | } | |
819 | ||
439104b3 | 820 | dma_addr = le64_to_cpu(rxd->buffer); |
1da177e4 LT |
821 | if (len > RX_COPY_THRESHOLD) { |
822 | struct sk_buff *new_skb; | |
823 | ||
fe09bb61 | 824 | new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC); |
1da177e4 LT |
825 | if (new_skb == NULL) { |
826 | drops++; | |
827 | goto drop_it; | |
828 | } | |
829 | pci_unmap_page(gp->pdev, dma_addr, | |
830 | RX_BUF_ALLOC_SIZE(gp), | |
831 | PCI_DMA_FROMDEVICE); | |
832 | gp->rx_skbs[entry] = new_skb; | |
1da177e4 LT |
833 | skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET)); |
834 | rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev, | |
835 | virt_to_page(new_skb->data), | |
836 | offset_in_page(new_skb->data), | |
837 | RX_BUF_ALLOC_SIZE(gp), | |
838 | PCI_DMA_FROMDEVICE)); | |
839 | skb_reserve(new_skb, RX_OFFSET); | |
840 | ||
841 | /* Trim the original skb for the netif. */ | |
842 | skb_trim(skb, len); | |
843 | } else { | |
fe09bb61 | 844 | struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2); |
1da177e4 LT |
845 | |
846 | if (copy_skb == NULL) { | |
847 | drops++; | |
848 | goto drop_it; | |
849 | } | |
850 | ||
1da177e4 LT |
851 | skb_reserve(copy_skb, 2); |
852 | skb_put(copy_skb, len); | |
853 | pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 854 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
855 | pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
856 | ||
857 | /* We'll reuse the original ring buffer. */ | |
858 | skb = copy_skb; | |
859 | } | |
860 | ||
439104b3 AV |
861 | csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff); |
862 | skb->csum = csum_unfold(csum); | |
84fa7933 | 863 | skb->ip_summed = CHECKSUM_COMPLETE; |
1da177e4 LT |
864 | skb->protocol = eth_type_trans(skb, gp->dev); |
865 | ||
fe09bb61 | 866 | napi_gro_receive(&gp->napi, skb); |
1da177e4 | 867 | |
aae7c473 DK |
868 | dev->stats.rx_packets++; |
869 | dev->stats.rx_bytes += len; | |
1da177e4 LT |
870 | |
871 | next: | |
872 | entry = NEXT_RX(entry); | |
873 | } | |
874 | ||
875 | gem_post_rxds(gp, entry); | |
876 | ||
877 | gp->rx_new = entry; | |
878 | ||
879 | if (drops) | |
c6c75988 | 880 | netdev_info(gp->dev, "Memory squeeze, deferring packet\n"); |
1da177e4 LT |
881 | |
882 | return work_done; | |
883 | } | |
884 | ||
bea3348e | 885 | static int gem_poll(struct napi_struct *napi, int budget) |
1da177e4 | 886 | { |
bea3348e SH |
887 | struct gem *gp = container_of(napi, struct gem, napi); |
888 | struct net_device *dev = gp->dev; | |
bea3348e | 889 | int work_done; |
1da177e4 | 890 | |
bea3348e | 891 | work_done = 0; |
1da177e4 | 892 | do { |
1da177e4 | 893 | /* Handle anomalies */ |
fe09bb61 BH |
894 | if (unlikely(gp->status & GREG_STAT_ABNORMAL)) { |
895 | struct netdev_queue *txq = netdev_get_tx_queue(dev, 0); | |
896 | int reset; | |
897 | ||
898 | /* We run the abnormal interrupt handling code with | |
899 | * the Tx lock. It only resets the Rx portion of the | |
900 | * chip, but we need to guard it against DMA being | |
901 | * restarted by the link poll timer | |
902 | */ | |
903 | __netif_tx_lock(txq, smp_processor_id()); | |
904 | reset = gem_abnormal_irq(dev, gp, gp->status); | |
905 | __netif_tx_unlock(txq); | |
906 | if (reset) { | |
907 | gem_schedule_reset(gp); | |
908 | napi_complete(napi); | |
909 | return work_done; | |
910 | } | |
1da177e4 LT |
911 | } |
912 | ||
913 | /* Run TX completion thread */ | |
1da177e4 | 914 | gem_tx(dev, gp, gp->status); |
1da177e4 | 915 | |
6aa20a22 JG |
916 | /* Run RX thread. We don't use any locking here, |
917 | * code willing to do bad things - like cleaning the | |
bea3348e | 918 | * rx ring - must call napi_disable(), which |
1da177e4 LT |
919 | * schedule_timeout()'s if polling is already disabled. |
920 | */ | |
da990a24 | 921 | work_done += gem_rx(gp, budget - work_done); |
1da177e4 | 922 | |
bea3348e SH |
923 | if (work_done >= budget) |
924 | return work_done; | |
1da177e4 | 925 | |
1da177e4 LT |
926 | gp->status = readl(gp->regs + GREG_STAT); |
927 | } while (gp->status & GREG_STAT_NAPI); | |
928 | ||
fe09bb61 | 929 | napi_complete(napi); |
1da177e4 LT |
930 | gem_enable_ints(gp); |
931 | ||
bea3348e | 932 | return work_done; |
1da177e4 LT |
933 | } |
934 | ||
7d12e780 | 935 | static irqreturn_t gem_interrupt(int irq, void *dev_id) |
1da177e4 LT |
936 | { |
937 | struct net_device *dev = dev_id; | |
8f15ea42 | 938 | struct gem *gp = netdev_priv(dev); |
6aa20a22 | 939 | |
288379f0 | 940 | if (napi_schedule_prep(&gp->napi)) { |
1da177e4 LT |
941 | u32 gem_status = readl(gp->regs + GREG_STAT); |
942 | ||
fe09bb61 | 943 | if (unlikely(gem_status == 0)) { |
bea3348e | 944 | napi_enable(&gp->napi); |
1da177e4 LT |
945 | return IRQ_NONE; |
946 | } | |
fe09bb61 BH |
947 | if (netif_msg_intr(gp)) |
948 | printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n", | |
949 | gp->dev->name, gem_status); | |
950 | ||
1da177e4 LT |
951 | gp->status = gem_status; |
952 | gem_disable_ints(gp); | |
288379f0 | 953 | __napi_schedule(&gp->napi); |
1da177e4 LT |
954 | } |
955 | ||
1da177e4 | 956 | /* If polling was disabled at the time we received that |
6aa20a22 | 957 | * interrupt, we may return IRQ_HANDLED here while we |
1da177e4 LT |
958 | * should return IRQ_NONE. No big deal... |
959 | */ | |
960 | return IRQ_HANDLED; | |
961 | } | |
962 | ||
963 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
964 | static void gem_poll_controller(struct net_device *dev) | |
965 | { | |
fe09bb61 BH |
966 | struct gem *gp = netdev_priv(dev); |
967 | ||
968 | disable_irq(gp->pdev->irq); | |
969 | gem_interrupt(gp->pdev->irq, dev); | |
970 | enable_irq(gp->pdev->irq); | |
1da177e4 LT |
971 | } |
972 | #endif | |
973 | ||
974 | static void gem_tx_timeout(struct net_device *dev) | |
975 | { | |
8f15ea42 | 976 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 977 | |
c6c75988 | 978 | netdev_err(dev, "transmit timed out, resetting\n"); |
fe09bb61 | 979 | |
c6c75988 JP |
980 | netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n", |
981 | readl(gp->regs + TXDMA_CFG), | |
982 | readl(gp->regs + MAC_TXSTAT), | |
983 | readl(gp->regs + MAC_TXCFG)); | |
984 | netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n", | |
985 | readl(gp->regs + RXDMA_CFG), | |
986 | readl(gp->regs + MAC_RXSTAT), | |
987 | readl(gp->regs + MAC_RXCFG)); | |
1da177e4 | 988 | |
fe09bb61 | 989 | gem_schedule_reset(gp); |
1da177e4 LT |
990 | } |
991 | ||
992 | static __inline__ int gem_intme(int entry) | |
993 | { | |
994 | /* Algorithm: IRQ every 1/2 of descriptors. */ | |
995 | if (!(entry & ((TX_RING_SIZE>>1)-1))) | |
996 | return 1; | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
61357325 SH |
1001 | static netdev_tx_t gem_start_xmit(struct sk_buff *skb, |
1002 | struct net_device *dev) | |
1da177e4 | 1003 | { |
8f15ea42 | 1004 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
1005 | int entry; |
1006 | u64 ctrl; | |
1da177e4 LT |
1007 | |
1008 | ctrl = 0; | |
84fa7933 | 1009 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
0d0b1672 | 1010 | const u64 csum_start_off = skb_checksum_start_offset(skb); |
ea2ae17d | 1011 | const u64 csum_stuff_off = csum_start_off + skb->csum_offset; |
1da177e4 LT |
1012 | |
1013 | ctrl = (TXDCTRL_CENAB | | |
1014 | (csum_start_off << 15) | | |
1015 | (csum_stuff_off << 21)); | |
1016 | } | |
1017 | ||
fe09bb61 BH |
1018 | if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) { |
1019 | /* This is a hard error, log it. */ | |
1020 | if (!netif_queue_stopped(dev)) { | |
1021 | netif_stop_queue(dev); | |
1022 | netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); | |
1023 | } | |
1da177e4 LT |
1024 | return NETDEV_TX_BUSY; |
1025 | } | |
1026 | ||
1027 | entry = gp->tx_new; | |
1028 | gp->tx_skbs[entry] = skb; | |
1029 | ||
1030 | if (skb_shinfo(skb)->nr_frags == 0) { | |
1031 | struct gem_txd *txd = &gp->init_block->txd[entry]; | |
1032 | dma_addr_t mapping; | |
1033 | u32 len; | |
1034 | ||
1035 | len = skb->len; | |
1036 | mapping = pci_map_page(gp->pdev, | |
1037 | virt_to_page(skb->data), | |
1038 | offset_in_page(skb->data), | |
1039 | len, PCI_DMA_TODEVICE); | |
1040 | ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len; | |
1041 | if (gem_intme(entry)) | |
1042 | ctrl |= TXDCTRL_INTME; | |
1043 | txd->buffer = cpu_to_le64(mapping); | |
1044 | wmb(); | |
1045 | txd->control_word = cpu_to_le64(ctrl); | |
1046 | entry = NEXT_TX(entry); | |
1047 | } else { | |
1048 | struct gem_txd *txd; | |
1049 | u32 first_len; | |
1050 | u64 intme; | |
1051 | dma_addr_t first_mapping; | |
1052 | int frag, first_entry = entry; | |
1053 | ||
1054 | intme = 0; | |
1055 | if (gem_intme(entry)) | |
1056 | intme |= TXDCTRL_INTME; | |
1057 | ||
1058 | /* We must give this initial chunk to the device last. | |
1059 | * Otherwise we could race with the device. | |
1060 | */ | |
1061 | first_len = skb_headlen(skb); | |
1062 | first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data), | |
1063 | offset_in_page(skb->data), | |
1064 | first_len, PCI_DMA_TODEVICE); | |
1065 | entry = NEXT_TX(entry); | |
1066 | ||
1067 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
9e903e08 | 1068 | const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; |
1da177e4 LT |
1069 | u32 len; |
1070 | dma_addr_t mapping; | |
1071 | u64 this_ctrl; | |
1072 | ||
9e903e08 | 1073 | len = skb_frag_size(this_frag); |
4fee78b4 | 1074 | mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag, |
5d6bcdfe | 1075 | 0, len, DMA_TO_DEVICE); |
1da177e4 LT |
1076 | this_ctrl = ctrl; |
1077 | if (frag == skb_shinfo(skb)->nr_frags - 1) | |
1078 | this_ctrl |= TXDCTRL_EOF; | |
6aa20a22 | 1079 | |
1da177e4 LT |
1080 | txd = &gp->init_block->txd[entry]; |
1081 | txd->buffer = cpu_to_le64(mapping); | |
1082 | wmb(); | |
1083 | txd->control_word = cpu_to_le64(this_ctrl | len); | |
1084 | ||
1085 | if (gem_intme(entry)) | |
1086 | intme |= TXDCTRL_INTME; | |
1087 | ||
1088 | entry = NEXT_TX(entry); | |
1089 | } | |
1090 | txd = &gp->init_block->txd[first_entry]; | |
1091 | txd->buffer = cpu_to_le64(first_mapping); | |
1092 | wmb(); | |
1093 | txd->control_word = | |
1094 | cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len); | |
1095 | } | |
1096 | ||
1097 | gp->tx_new = entry; | |
fe09bb61 | 1098 | if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) { |
1da177e4 LT |
1099 | netif_stop_queue(dev); |
1100 | ||
fe09bb61 BH |
1101 | /* netif_stop_queue() must be done before checking |
1102 | * checking tx index in TX_BUFFS_AVAIL() below, because | |
1103 | * in gem_tx(), we update tx_old before checking for | |
1104 | * netif_queue_stopped(). | |
1105 | */ | |
1106 | smp_mb(); | |
1107 | if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1)) | |
1108 | netif_wake_queue(dev); | |
1109 | } | |
1da177e4 LT |
1110 | if (netif_msg_tx_queued(gp)) |
1111 | printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n", | |
1112 | dev->name, entry, skb->len); | |
1113 | mb(); | |
1114 | writel(gp->tx_new, gp->regs + TXDMA_KICK); | |
1da177e4 LT |
1115 | |
1116 | return NETDEV_TX_OK; | |
1117 | } | |
1118 | ||
8c83f80b DM |
1119 | static void gem_pcs_reset(struct gem *gp) |
1120 | { | |
1121 | int limit; | |
1122 | u32 val; | |
1123 | ||
1124 | /* Reset PCS unit. */ | |
1125 | val = readl(gp->regs + PCS_MIICTRL); | |
1126 | val |= PCS_MIICTRL_RST; | |
1127 | writel(val, gp->regs + PCS_MIICTRL); | |
1128 | ||
1129 | limit = 32; | |
1130 | while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) { | |
1131 | udelay(100); | |
1132 | if (limit-- <= 0) | |
1133 | break; | |
1134 | } | |
d13c11f6 | 1135 | if (limit < 0) |
c6c75988 | 1136 | netdev_warn(gp->dev, "PCS reset bit would not clear\n"); |
8c83f80b DM |
1137 | } |
1138 | ||
1139 | static void gem_pcs_reinit_adv(struct gem *gp) | |
1140 | { | |
1141 | u32 val; | |
1142 | ||
1143 | /* Make sure PCS is disabled while changing advertisement | |
1144 | * configuration. | |
1145 | */ | |
1146 | val = readl(gp->regs + PCS_CFG); | |
1147 | val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO); | |
1148 | writel(val, gp->regs + PCS_CFG); | |
1149 | ||
25985edc | 1150 | /* Advertise all capabilities except asymmetric |
8c83f80b DM |
1151 | * pause. |
1152 | */ | |
1153 | val = readl(gp->regs + PCS_MIIADV); | |
1154 | val |= (PCS_MIIADV_FD | PCS_MIIADV_HD | | |
1155 | PCS_MIIADV_SP | PCS_MIIADV_AP); | |
1156 | writel(val, gp->regs + PCS_MIIADV); | |
1157 | ||
1158 | /* Enable and restart auto-negotiation, disable wrapback/loopback, | |
1159 | * and re-enable PCS. | |
1160 | */ | |
1161 | val = readl(gp->regs + PCS_MIICTRL); | |
1162 | val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE); | |
1163 | val &= ~PCS_MIICTRL_WB; | |
1164 | writel(val, gp->regs + PCS_MIICTRL); | |
1165 | ||
1166 | val = readl(gp->regs + PCS_CFG); | |
1167 | val |= PCS_CFG_ENABLE; | |
1168 | writel(val, gp->regs + PCS_CFG); | |
1169 | ||
1170 | /* Make sure serialink loopback is off. The meaning | |
1171 | * of this bit is logically inverted based upon whether | |
1172 | * you are in Serialink or SERDES mode. | |
1173 | */ | |
1174 | val = readl(gp->regs + PCS_SCTRL); | |
1175 | if (gp->phy_type == phy_serialink) | |
1176 | val &= ~PCS_SCTRL_LOOP; | |
1177 | else | |
1178 | val |= PCS_SCTRL_LOOP; | |
1179 | writel(val, gp->regs + PCS_SCTRL); | |
1180 | } | |
1181 | ||
1da177e4 LT |
1182 | #define STOP_TRIES 32 |
1183 | ||
1da177e4 LT |
1184 | static void gem_reset(struct gem *gp) |
1185 | { | |
1186 | int limit; | |
1187 | u32 val; | |
1188 | ||
1189 | /* Make sure we won't get any more interrupts */ | |
1190 | writel(0xffffffff, gp->regs + GREG_IMASK); | |
1191 | ||
1192 | /* Reset the chip */ | |
1193 | writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, | |
1194 | gp->regs + GREG_SWRST); | |
1195 | ||
1196 | limit = STOP_TRIES; | |
1197 | ||
1198 | do { | |
1199 | udelay(20); | |
1200 | val = readl(gp->regs + GREG_SWRST); | |
1201 | if (limit-- <= 0) | |
1202 | break; | |
1203 | } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); | |
1204 | ||
4a8fd2cf | 1205 | if (limit < 0) |
c6c75988 | 1206 | netdev_err(gp->dev, "SW reset is ghetto\n"); |
8c83f80b DM |
1207 | |
1208 | if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) | |
1209 | gem_pcs_reinit_adv(gp); | |
1da177e4 LT |
1210 | } |
1211 | ||
1da177e4 LT |
1212 | static void gem_start_dma(struct gem *gp) |
1213 | { | |
1214 | u32 val; | |
6aa20a22 | 1215 | |
1da177e4 LT |
1216 | /* We are ready to rock, turn everything on. */ |
1217 | val = readl(gp->regs + TXDMA_CFG); | |
1218 | writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); | |
1219 | val = readl(gp->regs + RXDMA_CFG); | |
1220 | writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
1221 | val = readl(gp->regs + MAC_TXCFG); | |
1222 | writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); | |
1223 | val = readl(gp->regs + MAC_RXCFG); | |
1224 | writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
1225 | ||
1226 | (void) readl(gp->regs + MAC_RXCFG); | |
1227 | udelay(100); | |
1228 | ||
1229 | gem_enable_ints(gp); | |
1230 | ||
1231 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
1232 | } | |
1233 | ||
fe09bb61 | 1234 | /* DMA won't be actually stopped before about 4ms tho ... |
1da177e4 LT |
1235 | */ |
1236 | static void gem_stop_dma(struct gem *gp) | |
1237 | { | |
1238 | u32 val; | |
1239 | ||
1240 | /* We are done rocking, turn everything off. */ | |
1241 | val = readl(gp->regs + TXDMA_CFG); | |
1242 | writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); | |
1243 | val = readl(gp->regs + RXDMA_CFG); | |
1244 | writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); | |
1245 | val = readl(gp->regs + MAC_TXCFG); | |
1246 | writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); | |
1247 | val = readl(gp->regs + MAC_RXCFG); | |
1248 | writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); | |
1249 | ||
1250 | (void) readl(gp->regs + MAC_RXCFG); | |
1251 | ||
1252 | /* Need to wait a bit ... done by the caller */ | |
1253 | } | |
1254 | ||
1255 | ||
1da177e4 LT |
1256 | // XXX dbl check what that function should do when called on PCS PHY |
1257 | static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep) | |
1258 | { | |
1259 | u32 advertise, features; | |
1260 | int autoneg; | |
1261 | int speed; | |
1262 | int duplex; | |
1263 | ||
1264 | if (gp->phy_type != phy_mii_mdio0 && | |
1265 | gp->phy_type != phy_mii_mdio1) | |
1266 | goto non_mii; | |
1267 | ||
1268 | /* Setup advertise */ | |
1269 | if (found_mii_phy(gp)) | |
1270 | features = gp->phy_mii.def->features; | |
1271 | else | |
1272 | features = 0; | |
1273 | ||
1274 | advertise = features & ADVERTISE_MASK; | |
1275 | if (gp->phy_mii.advertising != 0) | |
1276 | advertise &= gp->phy_mii.advertising; | |
1277 | ||
1278 | autoneg = gp->want_autoneg; | |
1279 | speed = gp->phy_mii.speed; | |
1280 | duplex = gp->phy_mii.duplex; | |
6aa20a22 | 1281 | |
1da177e4 LT |
1282 | /* Setup link parameters */ |
1283 | if (!ep) | |
1284 | goto start_aneg; | |
1285 | if (ep->autoneg == AUTONEG_ENABLE) { | |
1286 | advertise = ep->advertising; | |
1287 | autoneg = 1; | |
1288 | } else { | |
1289 | autoneg = 0; | |
25db0338 | 1290 | speed = ethtool_cmd_speed(ep); |
1da177e4 LT |
1291 | duplex = ep->duplex; |
1292 | } | |
1293 | ||
1294 | start_aneg: | |
1295 | /* Sanitize settings based on PHY capabilities */ | |
1296 | if ((features & SUPPORTED_Autoneg) == 0) | |
1297 | autoneg = 0; | |
1298 | if (speed == SPEED_1000 && | |
1299 | !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full))) | |
1300 | speed = SPEED_100; | |
1301 | if (speed == SPEED_100 && | |
1302 | !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full))) | |
1303 | speed = SPEED_10; | |
1304 | if (duplex == DUPLEX_FULL && | |
1305 | !(features & (SUPPORTED_1000baseT_Full | | |
1306 | SUPPORTED_100baseT_Full | | |
1307 | SUPPORTED_10baseT_Full))) | |
1308 | duplex = DUPLEX_HALF; | |
1309 | if (speed == 0) | |
1310 | speed = SPEED_10; | |
6aa20a22 | 1311 | |
1da177e4 LT |
1312 | /* If we are asleep, we don't try to actually setup the PHY, we |
1313 | * just store the settings | |
1314 | */ | |
fe09bb61 | 1315 | if (!netif_device_present(gp->dev)) { |
1da177e4 LT |
1316 | gp->phy_mii.autoneg = gp->want_autoneg = autoneg; |
1317 | gp->phy_mii.speed = speed; | |
1318 | gp->phy_mii.duplex = duplex; | |
1319 | return; | |
1320 | } | |
1321 | ||
1322 | /* Configure PHY & start aneg */ | |
1323 | gp->want_autoneg = autoneg; | |
1324 | if (autoneg) { | |
1325 | if (found_mii_phy(gp)) | |
1326 | gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise); | |
1327 | gp->lstate = link_aneg; | |
1328 | } else { | |
1329 | if (found_mii_phy(gp)) | |
1330 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex); | |
1331 | gp->lstate = link_force_ok; | |
1332 | } | |
1333 | ||
1334 | non_mii: | |
1335 | gp->timer_ticks = 0; | |
1336 | mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); | |
1337 | } | |
1338 | ||
1339 | /* A link-up condition has occurred, initialize and enable the | |
1340 | * rest of the chip. | |
1da177e4 LT |
1341 | */ |
1342 | static int gem_set_link_modes(struct gem *gp) | |
1343 | { | |
fe09bb61 | 1344 | struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0); |
1da177e4 | 1345 | int full_duplex, speed, pause; |
fe09bb61 | 1346 | u32 val; |
1da177e4 LT |
1347 | |
1348 | full_duplex = 0; | |
1349 | speed = SPEED_10; | |
1350 | pause = 0; | |
1351 | ||
1352 | if (found_mii_phy(gp)) { | |
1353 | if (gp->phy_mii.def->ops->read_link(&gp->phy_mii)) | |
1354 | return 1; | |
1355 | full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL); | |
1356 | speed = gp->phy_mii.speed; | |
1357 | pause = gp->phy_mii.pause; | |
1358 | } else if (gp->phy_type == phy_serialink || | |
1359 | gp->phy_type == phy_serdes) { | |
1360 | u32 pcs_lpa = readl(gp->regs + PCS_MIILP); | |
1361 | ||
8c83f80b | 1362 | if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes) |
1da177e4 LT |
1363 | full_duplex = 1; |
1364 | speed = SPEED_1000; | |
1365 | } | |
1366 | ||
c6c75988 JP |
1367 | netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n", |
1368 | speed, (full_duplex ? "full" : "half")); | |
1da177e4 | 1369 | |
fe09bb61 BH |
1370 | |
1371 | /* We take the tx queue lock to avoid collisions between | |
1372 | * this code, the tx path and the NAPI-driven error path | |
1373 | */ | |
1374 | __netif_tx_lock(txq, smp_processor_id()); | |
1da177e4 LT |
1375 | |
1376 | val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU); | |
1377 | if (full_duplex) { | |
1378 | val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL); | |
1379 | } else { | |
1380 | /* MAC_TXCFG_NBO must be zero. */ | |
6aa20a22 | 1381 | } |
1da177e4 LT |
1382 | writel(val, gp->regs + MAC_TXCFG); |
1383 | ||
1384 | val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED); | |
1385 | if (!full_duplex && | |
1386 | (gp->phy_type == phy_mii_mdio0 || | |
1387 | gp->phy_type == phy_mii_mdio1)) { | |
1388 | val |= MAC_XIFCFG_DISE; | |
1389 | } else if (full_duplex) { | |
1390 | val |= MAC_XIFCFG_FLED; | |
1391 | } | |
1392 | ||
1393 | if (speed == SPEED_1000) | |
1394 | val |= (MAC_XIFCFG_GMII); | |
1395 | ||
1396 | writel(val, gp->regs + MAC_XIFCFG); | |
1397 | ||
1398 | /* If gigabit and half-duplex, enable carrier extension | |
1399 | * mode. Else, disable it. | |
1400 | */ | |
1401 | if (speed == SPEED_1000 && !full_duplex) { | |
1402 | val = readl(gp->regs + MAC_TXCFG); | |
1403 | writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); | |
1404 | ||
1405 | val = readl(gp->regs + MAC_RXCFG); | |
1406 | writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); | |
1407 | } else { | |
1408 | val = readl(gp->regs + MAC_TXCFG); | |
1409 | writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); | |
1410 | ||
1411 | val = readl(gp->regs + MAC_RXCFG); | |
1412 | writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); | |
1413 | } | |
1414 | ||
1415 | if (gp->phy_type == phy_serialink || | |
1416 | gp->phy_type == phy_serdes) { | |
1417 | u32 pcs_lpa = readl(gp->regs + PCS_MIILP); | |
1418 | ||
1419 | if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP)) | |
1420 | pause = 1; | |
1421 | } | |
1422 | ||
1da177e4 LT |
1423 | if (!full_duplex) |
1424 | writel(512, gp->regs + MAC_STIME); | |
1425 | else | |
1426 | writel(64, gp->regs + MAC_STIME); | |
1427 | val = readl(gp->regs + MAC_MCCFG); | |
1428 | if (pause) | |
1429 | val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE); | |
1430 | else | |
1431 | val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE); | |
1432 | writel(val, gp->regs + MAC_MCCFG); | |
1433 | ||
1434 | gem_start_dma(gp); | |
1435 | ||
fe09bb61 BH |
1436 | __netif_tx_unlock(txq); |
1437 | ||
1438 | if (netif_msg_link(gp)) { | |
1439 | if (pause) { | |
1440 | netdev_info(gp->dev, | |
1441 | "Pause is enabled (rxfifo: %d off: %d on: %d)\n", | |
1442 | gp->rx_fifo_sz, | |
1443 | gp->rx_pause_off, | |
1444 | gp->rx_pause_on); | |
1445 | } else { | |
1446 | netdev_info(gp->dev, "Pause is disabled\n"); | |
1447 | } | |
1448 | } | |
1449 | ||
1da177e4 LT |
1450 | return 0; |
1451 | } | |
1452 | ||
1da177e4 LT |
1453 | static int gem_mdio_link_not_up(struct gem *gp) |
1454 | { | |
1455 | switch (gp->lstate) { | |
1456 | case link_force_ret: | |
c6c75988 JP |
1457 | netif_info(gp, link, gp->dev, |
1458 | "Autoneg failed again, keeping forced mode\n"); | |
1da177e4 LT |
1459 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, |
1460 | gp->last_forced_speed, DUPLEX_HALF); | |
1461 | gp->timer_ticks = 5; | |
1462 | gp->lstate = link_force_ok; | |
1463 | return 0; | |
1464 | case link_aneg: | |
1465 | /* We try forced modes after a failed aneg only on PHYs that don't | |
1466 | * have "magic_aneg" bit set, which means they internally do the | |
1467 | * while forced-mode thingy. On these, we just restart aneg | |
1468 | */ | |
1469 | if (gp->phy_mii.def->magic_aneg) | |
1470 | return 1; | |
c6c75988 | 1471 | netif_info(gp, link, gp->dev, "switching to forced 100bt\n"); |
1da177e4 LT |
1472 | /* Try forced modes. */ |
1473 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100, | |
1474 | DUPLEX_HALF); | |
1475 | gp->timer_ticks = 5; | |
1476 | gp->lstate = link_force_try; | |
1477 | return 0; | |
1478 | case link_force_try: | |
1479 | /* Downgrade from 100 to 10 Mbps if necessary. | |
1480 | * If already at 10Mbps, warn user about the | |
1481 | * situation every 10 ticks. | |
1482 | */ | |
1483 | if (gp->phy_mii.speed == SPEED_100) { | |
1484 | gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10, | |
1485 | DUPLEX_HALF); | |
1486 | gp->timer_ticks = 5; | |
c6c75988 JP |
1487 | netif_info(gp, link, gp->dev, |
1488 | "switching to forced 10bt\n"); | |
1da177e4 LT |
1489 | return 0; |
1490 | } else | |
1491 | return 1; | |
1492 | default: | |
1493 | return 0; | |
1494 | } | |
1495 | } | |
1496 | ||
1497 | static void gem_link_timer(unsigned long data) | |
1498 | { | |
1499 | struct gem *gp = (struct gem *) data; | |
fe09bb61 | 1500 | struct net_device *dev = gp->dev; |
1da177e4 | 1501 | int restart_aneg = 0; |
6aa20a22 | 1502 | |
fe09bb61 | 1503 | /* There's no point doing anything if we're going to be reset */ |
1da177e4 | 1504 | if (gp->reset_task_pending) |
fe09bb61 | 1505 | return; |
6aa20a22 | 1506 | |
1da177e4 LT |
1507 | if (gp->phy_type == phy_serialink || |
1508 | gp->phy_type == phy_serdes) { | |
1509 | u32 val = readl(gp->regs + PCS_MIISTAT); | |
1510 | ||
1511 | if (!(val & PCS_MIISTAT_LS)) | |
1512 | val = readl(gp->regs + PCS_MIISTAT); | |
1513 | ||
1514 | if ((val & PCS_MIISTAT_LS) != 0) { | |
8c83f80b DM |
1515 | if (gp->lstate == link_up) |
1516 | goto restart; | |
1517 | ||
1da177e4 | 1518 | gp->lstate = link_up; |
fe09bb61 | 1519 | netif_carrier_on(dev); |
1da177e4 LT |
1520 | (void)gem_set_link_modes(gp); |
1521 | } | |
1522 | goto restart; | |
1523 | } | |
1524 | if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) { | |
1525 | /* Ok, here we got a link. If we had it due to a forced | |
1526 | * fallback, and we were configured for autoneg, we do | |
1527 | * retry a short autoneg pass. If you know your hub is | |
1528 | * broken, use ethtool ;) | |
1529 | */ | |
1530 | if (gp->lstate == link_force_try && gp->want_autoneg) { | |
1531 | gp->lstate = link_force_ret; | |
1532 | gp->last_forced_speed = gp->phy_mii.speed; | |
1533 | gp->timer_ticks = 5; | |
1534 | if (netif_msg_link(gp)) | |
fe09bb61 | 1535 | netdev_info(dev, |
c6c75988 | 1536 | "Got link after fallback, retrying autoneg once...\n"); |
1da177e4 LT |
1537 | gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising); |
1538 | } else if (gp->lstate != link_up) { | |
1539 | gp->lstate = link_up; | |
fe09bb61 | 1540 | netif_carrier_on(dev); |
1da177e4 LT |
1541 | if (gem_set_link_modes(gp)) |
1542 | restart_aneg = 1; | |
1543 | } | |
1544 | } else { | |
1545 | /* If the link was previously up, we restart the | |
1546 | * whole process | |
1547 | */ | |
1548 | if (gp->lstate == link_up) { | |
1549 | gp->lstate = link_down; | |
fe09bb61 BH |
1550 | netif_info(gp, link, dev, "Link down\n"); |
1551 | netif_carrier_off(dev); | |
1552 | gem_schedule_reset(gp); | |
1553 | /* The reset task will restart the timer */ | |
1554 | return; | |
1da177e4 LT |
1555 | } else if (++gp->timer_ticks > 10) { |
1556 | if (found_mii_phy(gp)) | |
1557 | restart_aneg = gem_mdio_link_not_up(gp); | |
1558 | else | |
1559 | restart_aneg = 1; | |
1560 | } | |
1561 | } | |
1562 | if (restart_aneg) { | |
1563 | gem_begin_auto_negotiation(gp, NULL); | |
fe09bb61 | 1564 | return; |
1da177e4 LT |
1565 | } |
1566 | restart: | |
1567 | mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); | |
1da177e4 LT |
1568 | } |
1569 | ||
1da177e4 LT |
1570 | static void gem_clean_rings(struct gem *gp) |
1571 | { | |
1572 | struct gem_init_block *gb = gp->init_block; | |
1573 | struct sk_buff *skb; | |
1574 | int i; | |
1575 | dma_addr_t dma_addr; | |
1576 | ||
1577 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1578 | struct gem_rxd *rxd; | |
1579 | ||
1580 | rxd = &gb->rxd[i]; | |
1581 | if (gp->rx_skbs[i] != NULL) { | |
1582 | skb = gp->rx_skbs[i]; | |
1583 | dma_addr = le64_to_cpu(rxd->buffer); | |
1584 | pci_unmap_page(gp->pdev, dma_addr, | |
1585 | RX_BUF_ALLOC_SIZE(gp), | |
1586 | PCI_DMA_FROMDEVICE); | |
1587 | dev_kfree_skb_any(skb); | |
1588 | gp->rx_skbs[i] = NULL; | |
1589 | } | |
1590 | rxd->status_word = 0; | |
1591 | wmb(); | |
1592 | rxd->buffer = 0; | |
1593 | } | |
1594 | ||
1595 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1596 | if (gp->tx_skbs[i] != NULL) { | |
1597 | struct gem_txd *txd; | |
1598 | int frag; | |
1599 | ||
1600 | skb = gp->tx_skbs[i]; | |
1601 | gp->tx_skbs[i] = NULL; | |
1602 | ||
1603 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { | |
1604 | int ent = i & (TX_RING_SIZE - 1); | |
1605 | ||
1606 | txd = &gb->txd[ent]; | |
1607 | dma_addr = le64_to_cpu(txd->buffer); | |
1608 | pci_unmap_page(gp->pdev, dma_addr, | |
1609 | le64_to_cpu(txd->control_word) & | |
1610 | TXDCTRL_BUFSZ, PCI_DMA_TODEVICE); | |
1611 | ||
1612 | if (frag != skb_shinfo(skb)->nr_frags) | |
1613 | i++; | |
1614 | } | |
1615 | dev_kfree_skb_any(skb); | |
1616 | } | |
1617 | } | |
1618 | } | |
1619 | ||
1da177e4 LT |
1620 | static void gem_init_rings(struct gem *gp) |
1621 | { | |
1622 | struct gem_init_block *gb = gp->init_block; | |
1623 | struct net_device *dev = gp->dev; | |
1624 | int i; | |
1625 | dma_addr_t dma_addr; | |
1626 | ||
1627 | gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0; | |
1628 | ||
1629 | gem_clean_rings(gp); | |
1630 | ||
1631 | gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN, | |
1632 | (unsigned)VLAN_ETH_FRAME_LEN); | |
1633 | ||
1634 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1635 | struct sk_buff *skb; | |
1636 | struct gem_rxd *rxd = &gb->rxd[i]; | |
1637 | ||
fe09bb61 | 1638 | skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL); |
1da177e4 LT |
1639 | if (!skb) { |
1640 | rxd->buffer = 0; | |
1641 | rxd->status_word = 0; | |
1642 | continue; | |
1643 | } | |
1644 | ||
1645 | gp->rx_skbs[i] = skb; | |
1da177e4 LT |
1646 | skb_put(skb, (gp->rx_buf_sz + RX_OFFSET)); |
1647 | dma_addr = pci_map_page(gp->pdev, | |
1648 | virt_to_page(skb->data), | |
1649 | offset_in_page(skb->data), | |
1650 | RX_BUF_ALLOC_SIZE(gp), | |
1651 | PCI_DMA_FROMDEVICE); | |
1652 | rxd->buffer = cpu_to_le64(dma_addr); | |
1653 | wmb(); | |
1654 | rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp)); | |
1655 | skb_reserve(skb, RX_OFFSET); | |
1656 | } | |
1657 | ||
1658 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1659 | struct gem_txd *txd = &gb->txd[i]; | |
1660 | ||
1661 | txd->control_word = 0; | |
1662 | wmb(); | |
1663 | txd->buffer = 0; | |
1664 | } | |
1665 | wmb(); | |
1666 | } | |
1667 | ||
1668 | /* Init PHY interface and start link poll state machine */ | |
1669 | static void gem_init_phy(struct gem *gp) | |
1670 | { | |
7fb76aa0 | 1671 | u32 mifcfg; |
1da177e4 LT |
1672 | |
1673 | /* Revert MIF CFG setting done on stop_phy */ | |
7fb76aa0 DM |
1674 | mifcfg = readl(gp->regs + MIF_CFG); |
1675 | mifcfg &= ~MIF_CFG_BBMODE; | |
1676 | writel(mifcfg, gp->regs + MIF_CFG); | |
6aa20a22 | 1677 | |
1da177e4 LT |
1678 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) { |
1679 | int i; | |
1680 | ||
7fb76aa0 DM |
1681 | /* Those delay sucks, the HW seem to love them though, I'll |
1682 | * serisouly consider breaking some locks here to be able | |
1683 | * to schedule instead | |
1684 | */ | |
1685 | for (i = 0; i < 3; i++) { | |
1da177e4 | 1686 | #ifdef CONFIG_PPC_PMAC |
7fb76aa0 DM |
1687 | pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0); |
1688 | msleep(20); | |
1da177e4 | 1689 | #endif |
7fb76aa0 DM |
1690 | /* Some PHYs used by apple have problem getting back to us, |
1691 | * we do an additional reset here | |
1692 | */ | |
1693 | phy_write(gp, MII_BMCR, BMCR_RESET); | |
1694 | msleep(20); | |
1695 | if (phy_read(gp, MII_BMCR) != 0xffff) | |
1da177e4 | 1696 | break; |
7fb76aa0 | 1697 | if (i == 2) |
c6c75988 | 1698 | netdev_warn(gp->dev, "GMAC PHY not responding !\n"); |
1da177e4 LT |
1699 | } |
1700 | } | |
1701 | ||
1702 | if (gp->pdev->vendor == PCI_VENDOR_ID_SUN && | |
1703 | gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
1704 | u32 val; | |
1705 | ||
1706 | /* Init datapath mode register. */ | |
1707 | if (gp->phy_type == phy_mii_mdio0 || | |
1708 | gp->phy_type == phy_mii_mdio1) { | |
1709 | val = PCS_DMODE_MGM; | |
1710 | } else if (gp->phy_type == phy_serialink) { | |
1711 | val = PCS_DMODE_SM | PCS_DMODE_GMOE; | |
1712 | } else { | |
1713 | val = PCS_DMODE_ESM; | |
1714 | } | |
1715 | ||
1716 | writel(val, gp->regs + PCS_DMODE); | |
1717 | } | |
1718 | ||
1719 | if (gp->phy_type == phy_mii_mdio0 || | |
1720 | gp->phy_type == phy_mii_mdio1) { | |
fe09bb61 | 1721 | /* Reset and detect MII PHY */ |
19e2f6fe | 1722 | sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr); |
1da177e4 LT |
1723 | |
1724 | /* Init PHY */ | |
1725 | if (gp->phy_mii.def && gp->phy_mii.def->ops->init) | |
1726 | gp->phy_mii.def->ops->init(&gp->phy_mii); | |
1727 | } else { | |
8c83f80b DM |
1728 | gem_pcs_reset(gp); |
1729 | gem_pcs_reinit_adv(gp); | |
1da177e4 LT |
1730 | } |
1731 | ||
1732 | /* Default aneg parameters */ | |
1733 | gp->timer_ticks = 0; | |
1734 | gp->lstate = link_down; | |
1735 | netif_carrier_off(gp->dev); | |
1736 | ||
fe09bb61 BH |
1737 | /* Print things out */ |
1738 | if (gp->phy_type == phy_mii_mdio0 || | |
1739 | gp->phy_type == phy_mii_mdio1) | |
1740 | netdev_info(gp->dev, "Found %s PHY\n", | |
1741 | gp->phy_mii.def ? gp->phy_mii.def->name : "no"); | |
1742 | ||
1da177e4 | 1743 | gem_begin_auto_negotiation(gp, NULL); |
1da177e4 LT |
1744 | } |
1745 | ||
1da177e4 LT |
1746 | static void gem_init_dma(struct gem *gp) |
1747 | { | |
1748 | u64 desc_dma = (u64) gp->gblock_dvma; | |
1749 | u32 val; | |
1750 | ||
1751 | val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE); | |
1752 | writel(val, gp->regs + TXDMA_CFG); | |
1753 | ||
1754 | writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); | |
1755 | writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); | |
1756 | desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd)); | |
1757 | ||
1758 | writel(0, gp->regs + TXDMA_KICK); | |
1759 | ||
1760 | val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) | | |
1761 | ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128); | |
1762 | writel(val, gp->regs + RXDMA_CFG); | |
1763 | ||
1764 | writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); | |
1765 | writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); | |
1766 | ||
1767 | writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); | |
1768 | ||
1769 | val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF); | |
1770 | val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON); | |
1771 | writel(val, gp->regs + RXDMA_PTHRESH); | |
1772 | ||
1773 | if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN) | |
1774 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
1775 | ((8 << 12) & RXDMA_BLANK_ITIME)), | |
1776 | gp->regs + RXDMA_BLANK); | |
1777 | else | |
1778 | writel(((5 & RXDMA_BLANK_IPKTS) | | |
1779 | ((4 << 12) & RXDMA_BLANK_ITIME)), | |
1780 | gp->regs + RXDMA_BLANK); | |
1781 | } | |
1782 | ||
1da177e4 LT |
1783 | static u32 gem_setup_multicast(struct gem *gp) |
1784 | { | |
1785 | u32 rxcfg = 0; | |
1786 | int i; | |
6aa20a22 | 1787 | |
1da177e4 | 1788 | if ((gp->dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1789 | (netdev_mc_count(gp->dev) > 256)) { |
1da177e4 LT |
1790 | for (i=0; i<16; i++) |
1791 | writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); | |
1792 | rxcfg |= MAC_RXCFG_HFE; | |
1793 | } else if (gp->dev->flags & IFF_PROMISC) { | |
1794 | rxcfg |= MAC_RXCFG_PROM; | |
1795 | } else { | |
1796 | u16 hash_table[16]; | |
1797 | u32 crc; | |
22bedad3 | 1798 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1799 | int i; |
1800 | ||
5508590c | 1801 | memset(hash_table, 0, sizeof(hash_table)); |
22bedad3 | 1802 | netdev_for_each_mc_addr(ha, gp->dev) { |
498d8e23 | 1803 | crc = ether_crc_le(6, ha->addr); |
1da177e4 LT |
1804 | crc >>= 24; |
1805 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
1806 | } | |
1807 | for (i=0; i<16; i++) | |
1808 | writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); | |
1809 | rxcfg |= MAC_RXCFG_HFE; | |
1810 | } | |
1811 | ||
1812 | return rxcfg; | |
1813 | } | |
1814 | ||
1da177e4 LT |
1815 | static void gem_init_mac(struct gem *gp) |
1816 | { | |
1817 | unsigned char *e = &gp->dev->dev_addr[0]; | |
1818 | ||
1819 | writel(0x1bf0, gp->regs + MAC_SNDPAUSE); | |
1820 | ||
1821 | writel(0x00, gp->regs + MAC_IPG0); | |
1822 | writel(0x08, gp->regs + MAC_IPG1); | |
1823 | writel(0x04, gp->regs + MAC_IPG2); | |
1824 | writel(0x40, gp->regs + MAC_STIME); | |
1825 | writel(0x40, gp->regs + MAC_MINFSZ); | |
1826 | ||
1827 | /* Ethernet payload + header + FCS + optional VLAN tag. */ | |
1828 | writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); | |
1829 | ||
1830 | writel(0x07, gp->regs + MAC_PASIZE); | |
1831 | writel(0x04, gp->regs + MAC_JAMSIZE); | |
1832 | writel(0x10, gp->regs + MAC_ATTLIM); | |
1833 | writel(0x8808, gp->regs + MAC_MCTYPE); | |
1834 | ||
1835 | writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); | |
1836 | ||
1837 | writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); | |
1838 | writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); | |
1839 | writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); | |
1840 | ||
1841 | writel(0, gp->regs + MAC_ADDR3); | |
1842 | writel(0, gp->regs + MAC_ADDR4); | |
1843 | writel(0, gp->regs + MAC_ADDR5); | |
1844 | ||
1845 | writel(0x0001, gp->regs + MAC_ADDR6); | |
1846 | writel(0xc200, gp->regs + MAC_ADDR7); | |
1847 | writel(0x0180, gp->regs + MAC_ADDR8); | |
1848 | ||
1849 | writel(0, gp->regs + MAC_AFILT0); | |
1850 | writel(0, gp->regs + MAC_AFILT1); | |
1851 | writel(0, gp->regs + MAC_AFILT2); | |
1852 | writel(0, gp->regs + MAC_AF21MSK); | |
1853 | writel(0, gp->regs + MAC_AF0MSK); | |
1854 | ||
1855 | gp->mac_rx_cfg = gem_setup_multicast(gp); | |
1856 | #ifdef STRIP_FCS | |
1857 | gp->mac_rx_cfg |= MAC_RXCFG_SFCS; | |
1858 | #endif | |
1859 | writel(0, gp->regs + MAC_NCOLL); | |
1860 | writel(0, gp->regs + MAC_FASUCC); | |
1861 | writel(0, gp->regs + MAC_ECOLL); | |
1862 | writel(0, gp->regs + MAC_LCOLL); | |
1863 | writel(0, gp->regs + MAC_DTIMER); | |
1864 | writel(0, gp->regs + MAC_PATMPS); | |
1865 | writel(0, gp->regs + MAC_RFCTR); | |
1866 | writel(0, gp->regs + MAC_LERR); | |
1867 | writel(0, gp->regs + MAC_AERR); | |
1868 | writel(0, gp->regs + MAC_FCSERR); | |
1869 | writel(0, gp->regs + MAC_RXCVERR); | |
1870 | ||
1871 | /* Clear RX/TX/MAC/XIF config, we will set these up and enable | |
1872 | * them once a link is established. | |
1873 | */ | |
1874 | writel(0, gp->regs + MAC_TXCFG); | |
1875 | writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); | |
1876 | writel(0, gp->regs + MAC_MCCFG); | |
1877 | writel(0, gp->regs + MAC_XIFCFG); | |
1878 | ||
1879 | /* Setup MAC interrupts. We want to get all of the interesting | |
1880 | * counter expiration events, but we do not want to hear about | |
1881 | * normal rx/tx as the DMA engine tells us that. | |
1882 | */ | |
1883 | writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); | |
1884 | writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); | |
1885 | ||
1886 | /* Don't enable even the PAUSE interrupts for now, we | |
1887 | * make no use of those events other than to record them. | |
1888 | */ | |
1889 | writel(0xffffffff, gp->regs + MAC_MCMASK); | |
1890 | ||
1891 | /* Don't enable GEM's WOL in normal operations | |
1892 | */ | |
1893 | if (gp->has_wol) | |
1894 | writel(0, gp->regs + WOL_WAKECSR); | |
1895 | } | |
1896 | ||
1da177e4 LT |
1897 | static void gem_init_pause_thresholds(struct gem *gp) |
1898 | { | |
1899 | u32 cfg; | |
1900 | ||
1901 | /* Calculate pause thresholds. Setting the OFF threshold to the | |
1902 | * full RX fifo size effectively disables PAUSE generation which | |
1903 | * is what we do for 10/100 only GEMs which have FIFOs too small | |
1904 | * to make real gains from PAUSE. | |
1905 | */ | |
1906 | if (gp->rx_fifo_sz <= (2 * 1024)) { | |
1907 | gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz; | |
1908 | } else { | |
1909 | int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63; | |
1910 | int off = (gp->rx_fifo_sz - (max_frame * 2)); | |
1911 | int on = off - max_frame; | |
1912 | ||
1913 | gp->rx_pause_off = off; | |
1914 | gp->rx_pause_on = on; | |
1915 | } | |
1916 | ||
1917 | ||
1918 | /* Configure the chip "burst" DMA mode & enable some | |
1919 | * HW bug fixes on Apple version | |
1920 | */ | |
1921 | cfg = 0; | |
1922 | if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) | |
1923 | cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX; | |
1924 | #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) | |
1925 | cfg |= GREG_CFG_IBURST; | |
1926 | #endif | |
1927 | cfg |= ((31 << 1) & GREG_CFG_TXDMALIM); | |
1928 | cfg |= ((31 << 6) & GREG_CFG_RXDMALIM); | |
1929 | writel(cfg, gp->regs + GREG_CFG); | |
1930 | ||
1931 | /* If Infinite Burst didn't stick, then use different | |
1932 | * thresholds (and Apple bug fixes don't exist) | |
1933 | */ | |
1934 | if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) { | |
1935 | cfg = ((2 << 1) & GREG_CFG_TXDMALIM); | |
1936 | cfg |= ((8 << 6) & GREG_CFG_RXDMALIM); | |
1937 | writel(cfg, gp->regs + GREG_CFG); | |
6aa20a22 | 1938 | } |
1da177e4 LT |
1939 | } |
1940 | ||
1941 | static int gem_check_invariants(struct gem *gp) | |
1942 | { | |
1943 | struct pci_dev *pdev = gp->pdev; | |
1944 | u32 mif_cfg; | |
1945 | ||
1946 | /* On Apple's sungem, we can't rely on registers as the chip | |
1947 | * was been powered down by the firmware. The PHY is looked | |
1948 | * up later on. | |
1949 | */ | |
1950 | if (pdev->vendor == PCI_VENDOR_ID_APPLE) { | |
1951 | gp->phy_type = phy_mii_mdio0; | |
1952 | gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; | |
1953 | gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; | |
1954 | gp->swrst_base = 0; | |
1955 | ||
1956 | mif_cfg = readl(gp->regs + MIF_CFG); | |
1957 | mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1); | |
1958 | mif_cfg |= MIF_CFG_MDI0; | |
1959 | writel(mif_cfg, gp->regs + MIF_CFG); | |
1960 | writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); | |
1961 | writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); | |
1962 | ||
1963 | /* We hard-code the PHY address so we can properly bring it out of | |
1964 | * reset later on, we can't really probe it at this point, though | |
1965 | * that isn't an issue. | |
1966 | */ | |
1967 | if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC) | |
1968 | gp->mii_phy_addr = 1; | |
1969 | else | |
1970 | gp->mii_phy_addr = 0; | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | mif_cfg = readl(gp->regs + MIF_CFG); | |
1976 | ||
1977 | if (pdev->vendor == PCI_VENDOR_ID_SUN && | |
1978 | pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) { | |
1979 | /* One of the MII PHYs _must_ be present | |
1980 | * as this chip has no gigabit PHY. | |
1981 | */ | |
1982 | if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) { | |
c6c75988 | 1983 | pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n", |
1da177e4 LT |
1984 | mif_cfg); |
1985 | return -1; | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | /* Determine initial PHY interface type guess. MDIO1 is the | |
1990 | * external PHY and thus takes precedence over MDIO0. | |
1991 | */ | |
6aa20a22 | 1992 | |
1da177e4 LT |
1993 | if (mif_cfg & MIF_CFG_MDI1) { |
1994 | gp->phy_type = phy_mii_mdio1; | |
1995 | mif_cfg |= MIF_CFG_PSELECT; | |
1996 | writel(mif_cfg, gp->regs + MIF_CFG); | |
1997 | } else if (mif_cfg & MIF_CFG_MDI0) { | |
1998 | gp->phy_type = phy_mii_mdio0; | |
1999 | mif_cfg &= ~MIF_CFG_PSELECT; | |
2000 | writel(mif_cfg, gp->regs + MIF_CFG); | |
2001 | } else { | |
e54d5512 DM |
2002 | #ifdef CONFIG_SPARC |
2003 | const char *p; | |
2004 | ||
2005 | p = of_get_property(gp->of_node, "shared-pins", NULL); | |
2006 | if (p && !strcmp(p, "serdes")) | |
2007 | gp->phy_type = phy_serdes; | |
2008 | else | |
2009 | #endif | |
2010 | gp->phy_type = phy_serialink; | |
1da177e4 LT |
2011 | } |
2012 | if (gp->phy_type == phy_mii_mdio1 || | |
2013 | gp->phy_type == phy_mii_mdio0) { | |
2014 | int i; | |
2015 | ||
2016 | for (i = 0; i < 32; i++) { | |
2017 | gp->mii_phy_addr = i; | |
2018 | if (phy_read(gp, MII_BMCR) != 0xffff) | |
2019 | break; | |
2020 | } | |
2021 | if (i == 32) { | |
2022 | if (pdev->device != PCI_DEVICE_ID_SUN_GEM) { | |
c6c75988 | 2023 | pr_err("RIO MII phy will not respond\n"); |
1da177e4 LT |
2024 | return -1; |
2025 | } | |
2026 | gp->phy_type = phy_serdes; | |
2027 | } | |
2028 | } | |
2029 | ||
2030 | /* Fetch the FIFO configurations now too. */ | |
2031 | gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64; | |
2032 | gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64; | |
2033 | ||
2034 | if (pdev->vendor == PCI_VENDOR_ID_SUN) { | |
2035 | if (pdev->device == PCI_DEVICE_ID_SUN_GEM) { | |
2036 | if (gp->tx_fifo_sz != (9 * 1024) || | |
2037 | gp->rx_fifo_sz != (20 * 1024)) { | |
c6c75988 | 2038 | pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n", |
1da177e4 LT |
2039 | gp->tx_fifo_sz, gp->rx_fifo_sz); |
2040 | return -1; | |
2041 | } | |
2042 | gp->swrst_base = 0; | |
2043 | } else { | |
2044 | if (gp->tx_fifo_sz != (2 * 1024) || | |
2045 | gp->rx_fifo_sz != (2 * 1024)) { | |
c6c75988 | 2046 | pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n", |
1da177e4 LT |
2047 | gp->tx_fifo_sz, gp->rx_fifo_sz); |
2048 | return -1; | |
2049 | } | |
2050 | gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT; | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
1da177e4 LT |
2057 | static void gem_reinit_chip(struct gem *gp) |
2058 | { | |
2059 | /* Reset the chip */ | |
2060 | gem_reset(gp); | |
2061 | ||
2062 | /* Make sure ints are disabled */ | |
2063 | gem_disable_ints(gp); | |
2064 | ||
2065 | /* Allocate & setup ring buffers */ | |
2066 | gem_init_rings(gp); | |
2067 | ||
2068 | /* Configure pause thresholds */ | |
2069 | gem_init_pause_thresholds(gp); | |
2070 | ||
2071 | /* Init DMA & MAC engines */ | |
2072 | gem_init_dma(gp); | |
2073 | gem_init_mac(gp); | |
2074 | } | |
2075 | ||
2076 | ||
1da177e4 LT |
2077 | static void gem_stop_phy(struct gem *gp, int wol) |
2078 | { | |
7fb76aa0 | 2079 | u32 mifcfg; |
1da177e4 LT |
2080 | |
2081 | /* Let the chip settle down a bit, it seems that helps | |
2082 | * for sleep mode on some models | |
2083 | */ | |
2084 | msleep(10); | |
2085 | ||
2086 | /* Make sure we aren't polling PHY status change. We | |
2087 | * don't currently use that feature though | |
2088 | */ | |
7fb76aa0 DM |
2089 | mifcfg = readl(gp->regs + MIF_CFG); |
2090 | mifcfg &= ~MIF_CFG_POLL; | |
2091 | writel(mifcfg, gp->regs + MIF_CFG); | |
1da177e4 LT |
2092 | |
2093 | if (wol && gp->has_wol) { | |
2094 | unsigned char *e = &gp->dev->dev_addr[0]; | |
2095 | u32 csr; | |
2096 | ||
2097 | /* Setup wake-on-lan for MAGIC packet */ | |
2098 | writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB, | |
6aa20a22 | 2099 | gp->regs + MAC_RXCFG); |
1da177e4 LT |
2100 | writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); |
2101 | writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); | |
2102 | writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); | |
2103 | ||
2104 | writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); | |
2105 | csr = WOL_WAKECSR_ENABLE; | |
2106 | if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0) | |
2107 | csr |= WOL_WAKECSR_MII; | |
2108 | writel(csr, gp->regs + WOL_WAKECSR); | |
2109 | } else { | |
2110 | writel(0, gp->regs + MAC_RXCFG); | |
2111 | (void)readl(gp->regs + MAC_RXCFG); | |
2112 | /* Machine sleep will die in strange ways if we | |
2113 | * dont wait a bit here, looks like the chip takes | |
2114 | * some time to really shut down | |
2115 | */ | |
2116 | msleep(10); | |
2117 | } | |
2118 | ||
2119 | writel(0, gp->regs + MAC_TXCFG); | |
2120 | writel(0, gp->regs + MAC_XIFCFG); | |
2121 | writel(0, gp->regs + TXDMA_CFG); | |
2122 | writel(0, gp->regs + RXDMA_CFG); | |
2123 | ||
2124 | if (!wol) { | |
1da177e4 LT |
2125 | gem_reset(gp); |
2126 | writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); | |
2127 | writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); | |
1da177e4 LT |
2128 | |
2129 | if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend) | |
2130 | gp->phy_mii.def->ops->suspend(&gp->phy_mii); | |
2131 | ||
2132 | /* According to Apple, we must set the MDIO pins to this begnign | |
2133 | * state or we may 1) eat more current, 2) damage some PHYs | |
2134 | */ | |
7fb76aa0 | 2135 | writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); |
1da177e4 LT |
2136 | writel(0, gp->regs + MIF_BBCLK); |
2137 | writel(0, gp->regs + MIF_BBDATA); | |
2138 | writel(0, gp->regs + MIF_BBOENAB); | |
2139 | writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); | |
2140 | (void) readl(gp->regs + MAC_XIFCFG); | |
2141 | } | |
2142 | } | |
2143 | ||
1da177e4 LT |
2144 | static int gem_do_start(struct net_device *dev) |
2145 | { | |
8f15ea42 | 2146 | struct gem *gp = netdev_priv(dev); |
fe09bb61 | 2147 | int rc; |
1da177e4 LT |
2148 | |
2149 | /* Enable the cell */ | |
2150 | gem_get_cell(gp); | |
2151 | ||
fe09bb61 BH |
2152 | /* Make sure PCI access and bus master are enabled */ |
2153 | rc = pci_enable_device(gp->pdev); | |
2154 | if (rc) { | |
2155 | netdev_err(dev, "Failed to enable chip on PCI bus !\n"); | |
71822faa | 2156 | |
fe09bb61 BH |
2157 | /* Put cell and forget it for now, it will be considered as |
2158 | * still asleep, a new sleep cycle may bring it back | |
2159 | */ | |
2160 | gem_put_cell(gp); | |
2161 | return -ENXIO; | |
1da177e4 | 2162 | } |
fe09bb61 | 2163 | pci_set_master(gp->pdev); |
1da177e4 | 2164 | |
fe09bb61 BH |
2165 | /* Init & setup chip hardware */ |
2166 | gem_reinit_chip(gp); | |
1da177e4 | 2167 | |
fe09bb61 BH |
2168 | /* An interrupt might come in handy */ |
2169 | rc = request_irq(gp->pdev->irq, gem_interrupt, | |
2170 | IRQF_SHARED, dev->name, (void *)dev); | |
2171 | if (rc) { | |
c6c75988 | 2172 | netdev_err(dev, "failed to request irq !\n"); |
1da177e4 | 2173 | |
1da177e4 LT |
2174 | gem_reset(gp); |
2175 | gem_clean_rings(gp); | |
2176 | gem_put_cell(gp); | |
fe09bb61 BH |
2177 | return rc; |
2178 | } | |
6aa20a22 | 2179 | |
fe09bb61 BH |
2180 | /* Mark us as attached again if we come from resume(), this has |
2181 | * no effect if we weren't detatched and needs to be done now. | |
2182 | */ | |
2183 | netif_device_attach(dev); | |
1da177e4 | 2184 | |
fe09bb61 BH |
2185 | /* Restart NAPI & queues */ |
2186 | gem_netif_start(gp); | |
2187 | ||
2188 | /* Detect & init PHY, start autoneg etc... this will | |
2189 | * eventually result in starting DMA operations when | |
2190 | * the link is up | |
2191 | */ | |
2192 | gem_init_phy(gp); | |
1da177e4 LT |
2193 | |
2194 | return 0; | |
2195 | } | |
2196 | ||
2197 | static void gem_do_stop(struct net_device *dev, int wol) | |
2198 | { | |
8f15ea42 | 2199 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 2200 | |
fe09bb61 BH |
2201 | /* Stop NAPI and stop tx queue */ |
2202 | gem_netif_stop(gp); | |
1da177e4 | 2203 | |
fe09bb61 BH |
2204 | /* Make sure ints are disabled. We don't care about |
2205 | * synchronizing as NAPI is disabled, thus a stray | |
2206 | * interrupt will do nothing bad (our irq handler | |
2207 | * just schedules NAPI) | |
2208 | */ | |
1da177e4 LT |
2209 | gem_disable_ints(gp); |
2210 | ||
fe09bb61 BH |
2211 | /* Stop the link timer */ |
2212 | del_timer_sync(&gp->link_timer); | |
2213 | ||
2214 | /* We cannot cancel the reset task while holding the | |
2215 | * rtnl lock, we'd get an A->B / B->A deadlock stituation | |
2216 | * if we did. This is not an issue however as the reset | |
2217 | * task is synchronized vs. us (rtnl_lock) and will do | |
2218 | * nothing if the device is down or suspended. We do | |
2219 | * still clear reset_task_pending to avoid a spurrious | |
2220 | * reset later on in case we do resume before it gets | |
2221 | * scheduled. | |
2222 | */ | |
2223 | gp->reset_task_pending = 0; | |
1da177e4 LT |
2224 | |
2225 | /* If we are going to sleep with WOL */ | |
2226 | gem_stop_dma(gp); | |
2227 | msleep(10); | |
2228 | if (!wol) | |
2229 | gem_reset(gp); | |
2230 | msleep(10); | |
2231 | ||
2232 | /* Get rid of rings */ | |
2233 | gem_clean_rings(gp); | |
2234 | ||
2235 | /* No irq needed anymore */ | |
2236 | free_irq(gp->pdev->irq, (void *) dev); | |
2237 | ||
fe09bb61 BH |
2238 | /* Shut the PHY down eventually and setup WOL */ |
2239 | gem_stop_phy(gp, wol); | |
2240 | ||
2241 | /* Make sure bus master is disabled */ | |
2242 | pci_disable_device(gp->pdev); | |
2243 | ||
1da177e4 | 2244 | /* Cell not needed neither if no WOL */ |
fe09bb61 | 2245 | if (!wol) |
1da177e4 | 2246 | gem_put_cell(gp); |
1da177e4 LT |
2247 | } |
2248 | ||
c4028958 | 2249 | static void gem_reset_task(struct work_struct *work) |
1da177e4 | 2250 | { |
c4028958 | 2251 | struct gem *gp = container_of(work, struct gem, reset_task); |
1da177e4 | 2252 | |
fe09bb61 BH |
2253 | /* Lock out the network stack (essentially shield ourselves |
2254 | * against a racing open, close, control call, or suspend | |
2255 | */ | |
2256 | rtnl_lock(); | |
1da177e4 | 2257 | |
fe09bb61 BH |
2258 | /* Skip the reset task if suspended or closed, or if it's |
2259 | * been cancelled by gem_do_stop (see comment there) | |
2260 | */ | |
2261 | if (!netif_device_present(gp->dev) || | |
2262 | !netif_running(gp->dev) || | |
2263 | !gp->reset_task_pending) { | |
2264 | rtnl_unlock(); | |
2265 | return; | |
2266 | } | |
1da177e4 | 2267 | |
fe09bb61 BH |
2268 | /* Stop the link timer */ |
2269 | del_timer_sync(&gp->link_timer); | |
1da177e4 | 2270 | |
fe09bb61 BH |
2271 | /* Stop NAPI and tx */ |
2272 | gem_netif_stop(gp); | |
1da177e4 | 2273 | |
fe09bb61 BH |
2274 | /* Reset the chip & rings */ |
2275 | gem_reinit_chip(gp); | |
2276 | if (gp->lstate == link_up) | |
2277 | gem_set_link_modes(gp); | |
dde655c9 | 2278 | |
fe09bb61 BH |
2279 | /* Restart NAPI and Tx */ |
2280 | gem_netif_start(gp); | |
1da177e4 | 2281 | |
fe09bb61 BH |
2282 | /* We are back ! */ |
2283 | gp->reset_task_pending = 0; | |
1da177e4 | 2284 | |
fe09bb61 BH |
2285 | /* If the link is not up, restart autoneg, else restart the |
2286 | * polling timer | |
2287 | */ | |
2288 | if (gp->lstate != link_up) | |
2289 | gem_begin_auto_negotiation(gp, NULL); | |
2290 | else | |
2291 | mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10)); | |
1da177e4 | 2292 | |
fe09bb61 | 2293 | rtnl_unlock(); |
1da177e4 LT |
2294 | } |
2295 | ||
1da177e4 LT |
2296 | static int gem_open(struct net_device *dev) |
2297 | { | |
fe09bb61 BH |
2298 | /* We allow open while suspended, we just do nothing, |
2299 | * the chip will be initialized in resume() | |
2300 | */ | |
2301 | if (netif_device_present(dev)) | |
2302 | return gem_do_start(dev); | |
2303 | return 0; | |
1da177e4 LT |
2304 | } |
2305 | ||
2306 | static int gem_close(struct net_device *dev) | |
2307 | { | |
fe09bb61 | 2308 | if (netif_device_present(dev)) |
1da177e4 LT |
2309 | gem_do_stop(dev, 0); |
2310 | ||
1da177e4 LT |
2311 | return 0; |
2312 | } | |
2313 | ||
2314 | #ifdef CONFIG_PM | |
2315 | static int gem_suspend(struct pci_dev *pdev, pm_message_t state) | |
2316 | { | |
2317 | struct net_device *dev = pci_get_drvdata(pdev); | |
8f15ea42 | 2318 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 2319 | |
fe09bb61 BH |
2320 | /* Lock the network stack first to avoid racing with open/close, |
2321 | * reset task and setting calls | |
2322 | */ | |
2323 | rtnl_lock(); | |
62768e28 | 2324 | |
fe09bb61 BH |
2325 | /* Not running, mark ourselves non-present, no need for |
2326 | * a lock here | |
2327 | */ | |
2328 | if (!netif_running(dev)) { | |
1da177e4 | 2329 | netif_device_detach(dev); |
fe09bb61 BH |
2330 | rtnl_unlock(); |
2331 | return 0; | |
2332 | } | |
2333 | netdev_info(dev, "suspending, WakeOnLan %s\n", | |
2334 | (gp->wake_on_lan && netif_running(dev)) ? | |
2335 | "enabled" : "disabled"); | |
1da177e4 | 2336 | |
fe09bb61 BH |
2337 | /* Tell the network stack we're gone. gem_do_stop() below will |
2338 | * synchronize with TX, stop NAPI etc... | |
1da177e4 | 2339 | */ |
fe09bb61 | 2340 | netif_device_detach(dev); |
1da177e4 | 2341 | |
fe09bb61 BH |
2342 | /* Switch off chip, remember WOL setting */ |
2343 | gp->asleep_wol = gp->wake_on_lan; | |
2344 | gem_do_stop(dev, gp->asleep_wol); | |
1da177e4 | 2345 | |
fe09bb61 BH |
2346 | /* Unlock the network stack */ |
2347 | rtnl_unlock(); | |
1da177e4 LT |
2348 | |
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | static int gem_resume(struct pci_dev *pdev) | |
2353 | { | |
2354 | struct net_device *dev = pci_get_drvdata(pdev); | |
8f15ea42 | 2355 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 2356 | |
fe09bb61 BH |
2357 | /* See locking comment in gem_suspend */ |
2358 | rtnl_lock(); | |
1da177e4 | 2359 | |
fe09bb61 BH |
2360 | /* Not running, mark ourselves present, no need for |
2361 | * a lock here | |
1da177e4 | 2362 | */ |
fe09bb61 BH |
2363 | if (!netif_running(dev)) { |
2364 | netif_device_attach(dev); | |
2365 | rtnl_unlock(); | |
1da177e4 LT |
2366 | return 0; |
2367 | } | |
1da177e4 | 2368 | |
fe09bb61 BH |
2369 | /* Restart chip. If that fails there isn't much we can do, we |
2370 | * leave things stopped. | |
1da177e4 | 2371 | */ |
fe09bb61 | 2372 | gem_do_start(dev); |
1da177e4 LT |
2373 | |
2374 | /* If we had WOL enabled, the cell clock was never turned off during | |
2375 | * sleep, so we end up beeing unbalanced. Fix that here | |
2376 | */ | |
2377 | if (gp->asleep_wol) | |
2378 | gem_put_cell(gp); | |
2379 | ||
fe09bb61 BH |
2380 | /* Unlock the network stack */ |
2381 | rtnl_unlock(); | |
1da177e4 LT |
2382 | |
2383 | return 0; | |
2384 | } | |
2385 | #endif /* CONFIG_PM */ | |
2386 | ||
2387 | static struct net_device_stats *gem_get_stats(struct net_device *dev) | |
2388 | { | |
8f15ea42 | 2389 | struct gem *gp = netdev_priv(dev); |
1da177e4 | 2390 | |
1da177e4 | 2391 | /* I have seen this being called while the PM was in progress, |
fe09bb61 BH |
2392 | * so we shield against this. Let's also not poke at registers |
2393 | * while the reset task is going on. | |
2394 | * | |
2395 | * TODO: Move stats collection elsewhere (link timer ?) and | |
2396 | * make this a nop to avoid all those synchro issues | |
1da177e4 | 2397 | */ |
fe09bb61 BH |
2398 | if (!netif_device_present(dev) || !netif_running(dev)) |
2399 | goto bail; | |
1da177e4 | 2400 | |
fe09bb61 BH |
2401 | /* Better safe than sorry... */ |
2402 | if (WARN_ON(!gp->cell_enabled)) | |
2403 | goto bail; | |
1da177e4 | 2404 | |
fe09bb61 BH |
2405 | dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR); |
2406 | writel(0, gp->regs + MAC_FCSERR); | |
1da177e4 | 2407 | |
fe09bb61 BH |
2408 | dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR); |
2409 | writel(0, gp->regs + MAC_AERR); | |
1da177e4 | 2410 | |
fe09bb61 BH |
2411 | dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR); |
2412 | writel(0, gp->regs + MAC_LERR); | |
1da177e4 | 2413 | |
fe09bb61 BH |
2414 | dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL); |
2415 | dev->stats.collisions += | |
2416 | (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL)); | |
2417 | writel(0, gp->regs + MAC_ECOLL); | |
2418 | writel(0, gp->regs + MAC_LCOLL); | |
2419 | bail: | |
aae7c473 | 2420 | return &dev->stats; |
1da177e4 LT |
2421 | } |
2422 | ||
09c72ec8 RV |
2423 | static int gem_set_mac_address(struct net_device *dev, void *addr) |
2424 | { | |
2425 | struct sockaddr *macaddr = (struct sockaddr *) addr; | |
8f15ea42 | 2426 | struct gem *gp = netdev_priv(dev); |
09c72ec8 RV |
2427 | unsigned char *e = &dev->dev_addr[0]; |
2428 | ||
2429 | if (!is_valid_ether_addr(macaddr->sa_data)) | |
2430 | return -EADDRNOTAVAIL; | |
2431 | ||
fe09bb61 BH |
2432 | memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len); |
2433 | ||
2434 | /* We'll just catch it later when the device is up'd or resumed */ | |
2435 | if (!netif_running(dev) || !netif_device_present(dev)) | |
09c72ec8 | 2436 | return 0; |
09c72ec8 | 2437 | |
fe09bb61 BH |
2438 | /* Better safe than sorry... */ |
2439 | if (WARN_ON(!gp->cell_enabled)) | |
2440 | return 0; | |
2441 | ||
2442 | writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); | |
2443 | writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); | |
2444 | writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); | |
09c72ec8 RV |
2445 | |
2446 | return 0; | |
2447 | } | |
2448 | ||
1da177e4 LT |
2449 | static void gem_set_multicast(struct net_device *dev) |
2450 | { | |
8f15ea42 | 2451 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2452 | u32 rxcfg, rxcfg_new; |
2453 | int limit = 10000; | |
6aa20a22 | 2454 | |
fe09bb61 BH |
2455 | if (!netif_running(dev) || !netif_device_present(dev)) |
2456 | return; | |
1da177e4 | 2457 | |
fe09bb61 BH |
2458 | /* Better safe than sorry... */ |
2459 | if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled)) | |
2460 | return; | |
1da177e4 LT |
2461 | |
2462 | rxcfg = readl(gp->regs + MAC_RXCFG); | |
2463 | rxcfg_new = gem_setup_multicast(gp); | |
2464 | #ifdef STRIP_FCS | |
2465 | rxcfg_new |= MAC_RXCFG_SFCS; | |
2466 | #endif | |
2467 | gp->mac_rx_cfg = rxcfg_new; | |
6aa20a22 | 2468 | |
1da177e4 LT |
2469 | writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); |
2470 | while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) { | |
2471 | if (!limit--) | |
2472 | break; | |
2473 | udelay(10); | |
2474 | } | |
2475 | ||
2476 | rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE); | |
2477 | rxcfg |= rxcfg_new; | |
2478 | ||
2479 | writel(rxcfg, gp->regs + MAC_RXCFG); | |
1da177e4 LT |
2480 | } |
2481 | ||
2482 | /* Jumbo-grams don't seem to work :-( */ | |
2483 | #define GEM_MIN_MTU 68 | |
2484 | #if 1 | |
2485 | #define GEM_MAX_MTU 1500 | |
2486 | #else | |
2487 | #define GEM_MAX_MTU 9000 | |
2488 | #endif | |
2489 | ||
2490 | static int gem_change_mtu(struct net_device *dev, int new_mtu) | |
2491 | { | |
8f15ea42 | 2492 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2493 | |
2494 | if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU) | |
2495 | return -EINVAL; | |
2496 | ||
fe09bb61 BH |
2497 | dev->mtu = new_mtu; |
2498 | ||
2499 | /* We'll just catch it later when the device is up'd or resumed */ | |
2500 | if (!netif_running(dev) || !netif_device_present(dev)) | |
1da177e4 | 2501 | return 0; |
1da177e4 | 2502 | |
fe09bb61 BH |
2503 | /* Better safe than sorry... */ |
2504 | if (WARN_ON(!gp->cell_enabled)) | |
2505 | return 0; | |
2506 | ||
2507 | gem_netif_stop(gp); | |
2508 | gem_reinit_chip(gp); | |
2509 | if (gp->lstate == link_up) | |
2510 | gem_set_link_modes(gp); | |
2511 | gem_netif_start(gp); | |
1da177e4 LT |
2512 | |
2513 | return 0; | |
2514 | } | |
2515 | ||
2516 | static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
2517 | { | |
8f15ea42 | 2518 | struct gem *gp = netdev_priv(dev); |
6aa20a22 | 2519 | |
23020ab3 RJ |
2520 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
2521 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
2522 | strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info)); | |
1da177e4 | 2523 | } |
6aa20a22 | 2524 | |
1da177e4 LT |
2525 | static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
2526 | { | |
8f15ea42 | 2527 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2528 | |
2529 | if (gp->phy_type == phy_mii_mdio0 || | |
2530 | gp->phy_type == phy_mii_mdio1) { | |
2531 | if (gp->phy_mii.def) | |
2532 | cmd->supported = gp->phy_mii.def->features; | |
2533 | else | |
2534 | cmd->supported = (SUPPORTED_10baseT_Half | | |
2535 | SUPPORTED_10baseT_Full); | |
2536 | ||
2537 | /* XXX hardcoded stuff for now */ | |
2538 | cmd->port = PORT_MII; | |
2539 | cmd->transceiver = XCVR_EXTERNAL; | |
2540 | cmd->phy_address = 0; /* XXX fixed PHYAD */ | |
2541 | ||
2542 | /* Return current PHY settings */ | |
1da177e4 | 2543 | cmd->autoneg = gp->want_autoneg; |
70739497 | 2544 | ethtool_cmd_speed_set(cmd, gp->phy_mii.speed); |
6aa20a22 | 2545 | cmd->duplex = gp->phy_mii.duplex; |
1da177e4 LT |
2546 | cmd->advertising = gp->phy_mii.advertising; |
2547 | ||
2548 | /* If we started with a forced mode, we don't have a default | |
2549 | * advertise set, we need to return something sensible so | |
2550 | * userland can re-enable autoneg properly. | |
2551 | */ | |
2552 | if (cmd->advertising == 0) | |
2553 | cmd->advertising = cmd->supported; | |
1da177e4 LT |
2554 | } else { // XXX PCS ? |
2555 | cmd->supported = | |
2556 | (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
2557 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
2558 | SUPPORTED_Autoneg); | |
2559 | cmd->advertising = cmd->supported; | |
70739497 | 2560 | ethtool_cmd_speed_set(cmd, 0); |
1da177e4 LT |
2561 | cmd->duplex = cmd->port = cmd->phy_address = |
2562 | cmd->transceiver = cmd->autoneg = 0; | |
fbf0229e HL |
2563 | |
2564 | /* serdes means usually a Fibre connector, with most fixed */ | |
2565 | if (gp->phy_type == phy_serdes) { | |
2566 | cmd->port = PORT_FIBRE; | |
2567 | cmd->supported = (SUPPORTED_1000baseT_Half | | |
2568 | SUPPORTED_1000baseT_Full | | |
2569 | SUPPORTED_FIBRE | SUPPORTED_Autoneg | | |
2570 | SUPPORTED_Pause | SUPPORTED_Asym_Pause); | |
2571 | cmd->advertising = cmd->supported; | |
2572 | cmd->transceiver = XCVR_INTERNAL; | |
2573 | if (gp->lstate == link_up) | |
70739497 | 2574 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
fbf0229e HL |
2575 | cmd->duplex = DUPLEX_FULL; |
2576 | cmd->autoneg = 1; | |
2577 | } | |
1da177e4 LT |
2578 | } |
2579 | cmd->maxtxpkt = cmd->maxrxpkt = 0; | |
2580 | ||
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2585 | { | |
8f15ea42 | 2586 | struct gem *gp = netdev_priv(dev); |
25db0338 | 2587 | u32 speed = ethtool_cmd_speed(cmd); |
1da177e4 LT |
2588 | |
2589 | /* Verify the settings we care about. */ | |
2590 | if (cmd->autoneg != AUTONEG_ENABLE && | |
2591 | cmd->autoneg != AUTONEG_DISABLE) | |
2592 | return -EINVAL; | |
2593 | ||
2594 | if (cmd->autoneg == AUTONEG_ENABLE && | |
2595 | cmd->advertising == 0) | |
2596 | return -EINVAL; | |
2597 | ||
2598 | if (cmd->autoneg == AUTONEG_DISABLE && | |
25db0338 DD |
2599 | ((speed != SPEED_1000 && |
2600 | speed != SPEED_100 && | |
2601 | speed != SPEED_10) || | |
1da177e4 LT |
2602 | (cmd->duplex != DUPLEX_HALF && |
2603 | cmd->duplex != DUPLEX_FULL))) | |
2604 | return -EINVAL; | |
6aa20a22 | 2605 | |
1da177e4 | 2606 | /* Apply settings and restart link process. */ |
fe09bb61 BH |
2607 | if (netif_device_present(gp->dev)) { |
2608 | del_timer_sync(&gp->link_timer); | |
2609 | gem_begin_auto_negotiation(gp, cmd); | |
2610 | } | |
1da177e4 LT |
2611 | |
2612 | return 0; | |
2613 | } | |
2614 | ||
2615 | static int gem_nway_reset(struct net_device *dev) | |
2616 | { | |
8f15ea42 | 2617 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2618 | |
2619 | if (!gp->want_autoneg) | |
2620 | return -EINVAL; | |
2621 | ||
fe09bb61 BH |
2622 | /* Restart link process */ |
2623 | if (netif_device_present(gp->dev)) { | |
2624 | del_timer_sync(&gp->link_timer); | |
2625 | gem_begin_auto_negotiation(gp, NULL); | |
2626 | } | |
1da177e4 LT |
2627 | |
2628 | return 0; | |
2629 | } | |
2630 | ||
2631 | static u32 gem_get_msglevel(struct net_device *dev) | |
2632 | { | |
8f15ea42 | 2633 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2634 | return gp->msg_enable; |
2635 | } | |
6aa20a22 | 2636 | |
1da177e4 LT |
2637 | static void gem_set_msglevel(struct net_device *dev, u32 value) |
2638 | { | |
8f15ea42 | 2639 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2640 | gp->msg_enable = value; |
2641 | } | |
2642 | ||
2643 | ||
2644 | /* Add more when I understand how to program the chip */ | |
2645 | /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */ | |
2646 | ||
2647 | #define WOL_SUPPORTED_MASK (WAKE_MAGIC) | |
2648 | ||
2649 | static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2650 | { | |
8f15ea42 | 2651 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2652 | |
2653 | /* Add more when I understand how to program the chip */ | |
2654 | if (gp->has_wol) { | |
2655 | wol->supported = WOL_SUPPORTED_MASK; | |
2656 | wol->wolopts = gp->wake_on_lan; | |
2657 | } else { | |
2658 | wol->supported = 0; | |
2659 | wol->wolopts = 0; | |
2660 | } | |
2661 | } | |
2662 | ||
2663 | static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2664 | { | |
8f15ea42 | 2665 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2666 | |
2667 | if (!gp->has_wol) | |
2668 | return -EOPNOTSUPP; | |
2669 | gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK; | |
2670 | return 0; | |
2671 | } | |
2672 | ||
7282d491 | 2673 | static const struct ethtool_ops gem_ethtool_ops = { |
1da177e4 LT |
2674 | .get_drvinfo = gem_get_drvinfo, |
2675 | .get_link = ethtool_op_get_link, | |
2676 | .get_settings = gem_get_settings, | |
2677 | .set_settings = gem_set_settings, | |
2678 | .nway_reset = gem_nway_reset, | |
2679 | .get_msglevel = gem_get_msglevel, | |
2680 | .set_msglevel = gem_set_msglevel, | |
2681 | .get_wol = gem_get_wol, | |
2682 | .set_wol = gem_set_wol, | |
2683 | }; | |
2684 | ||
2685 | static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2686 | { | |
8f15ea42 | 2687 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2688 | struct mii_ioctl_data *data = if_mii(ifr); |
2689 | int rc = -EOPNOTSUPP; | |
1da177e4 | 2690 | |
fe09bb61 BH |
2691 | /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that |
2692 | * netif_device_present() is true and holds rtnl_lock for us | |
2693 | * so we have nothing to worry about | |
1da177e4 | 2694 | */ |
1da177e4 LT |
2695 | |
2696 | switch (cmd) { | |
2697 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
2698 | data->phy_id = gp->mii_phy_addr; | |
2699 | /* Fallthrough... */ | |
2700 | ||
2701 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
fe09bb61 BH |
2702 | data->val_out = __phy_read(gp, data->phy_id & 0x1f, |
2703 | data->reg_num & 0x1f); | |
2704 | rc = 0; | |
1da177e4 LT |
2705 | break; |
2706 | ||
2707 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
fe09bb61 BH |
2708 | __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, |
2709 | data->val_in); | |
2710 | rc = 0; | |
1da177e4 | 2711 | break; |
6403eab1 | 2712 | } |
1da177e4 LT |
2713 | return rc; |
2714 | } | |
2715 | ||
dadb830d | 2716 | #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC)) |
1da177e4 | 2717 | /* Fetch MAC address from vital product data of PCI ROM. */ |
4120b028 | 2718 | static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr) |
1da177e4 LT |
2719 | { |
2720 | int this_offset; | |
2721 | ||
2722 | for (this_offset = 0x20; this_offset < len; this_offset++) { | |
2723 | void __iomem *p = rom_base + this_offset; | |
2724 | int i; | |
2725 | ||
2726 | if (readb(p + 0) != 0x90 || | |
2727 | readb(p + 1) != 0x00 || | |
2728 | readb(p + 2) != 0x09 || | |
2729 | readb(p + 3) != 0x4e || | |
2730 | readb(p + 4) != 0x41 || | |
2731 | readb(p + 5) != 0x06) | |
2732 | continue; | |
2733 | ||
2734 | this_offset += 6; | |
2735 | p += 6; | |
2736 | ||
2737 | for (i = 0; i < 6; i++) | |
2738 | dev_addr[i] = readb(p + i); | |
4120b028 | 2739 | return 1; |
1da177e4 | 2740 | } |
4120b028 | 2741 | return 0; |
1da177e4 LT |
2742 | } |
2743 | ||
2744 | static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr) | |
2745 | { | |
4120b028 LT |
2746 | size_t size; |
2747 | void __iomem *p = pci_map_rom(pdev, &size); | |
1da177e4 | 2748 | |
4120b028 LT |
2749 | if (p) { |
2750 | int found; | |
1da177e4 | 2751 | |
4120b028 LT |
2752 | found = readb(p) == 0x55 && |
2753 | readb(p + 1) == 0xaa && | |
2754 | find_eth_addr_in_vpd(p, (64 * 1024), dev_addr); | |
2755 | pci_unmap_rom(pdev, p); | |
2756 | if (found) | |
2757 | return; | |
2758 | } | |
1da177e4 | 2759 | |
1da177e4 LT |
2760 | /* Sun MAC prefix then 3 random bytes. */ |
2761 | dev_addr[0] = 0x08; | |
2762 | dev_addr[1] = 0x00; | |
2763 | dev_addr[2] = 0x20; | |
2764 | get_random_bytes(dev_addr + 3, 3); | |
1da177e4 LT |
2765 | } |
2766 | #endif /* not Sparc and not PPC */ | |
2767 | ||
2768 | static int __devinit gem_get_device_address(struct gem *gp) | |
2769 | { | |
dadb830d | 2770 | #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC) |
1da177e4 | 2771 | struct net_device *dev = gp->dev; |
1a2509c9 | 2772 | const unsigned char *addr; |
1da177e4 | 2773 | |
40cd3a45 | 2774 | addr = of_get_property(gp->of_node, "local-mac-address", NULL); |
1da177e4 | 2775 | if (addr == NULL) { |
457e1a8a DM |
2776 | #ifdef CONFIG_SPARC |
2777 | addr = idprom->id_ethaddr; | |
2778 | #else | |
1da177e4 | 2779 | printk("\n"); |
c6c75988 | 2780 | pr_err("%s: can't get mac-address\n", dev->name); |
1da177e4 | 2781 | return -1; |
457e1a8a | 2782 | #endif |
1da177e4 LT |
2783 | } |
2784 | memcpy(dev->dev_addr, addr, 6); | |
2785 | #else | |
2786 | get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr); | |
2787 | #endif | |
2788 | return 0; | |
2789 | } | |
2790 | ||
14904398 | 2791 | static void gem_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
2792 | { |
2793 | struct net_device *dev = pci_get_drvdata(pdev); | |
2794 | ||
2795 | if (dev) { | |
8f15ea42 | 2796 | struct gem *gp = netdev_priv(dev); |
1da177e4 LT |
2797 | |
2798 | unregister_netdev(dev); | |
2799 | ||
fe09bb61 | 2800 | /* Ensure reset task is truely gone */ |
fe8998c5 | 2801 | cancel_work_sync(&gp->reset_task); |
1da177e4 | 2802 | |
1da177e4 LT |
2803 | /* Free resources */ |
2804 | pci_free_consistent(pdev, | |
2805 | sizeof(struct gem_init_block), | |
2806 | gp->init_block, | |
2807 | gp->gblock_dvma); | |
2808 | iounmap(gp->regs); | |
2809 | pci_release_regions(pdev); | |
2810 | free_netdev(dev); | |
2811 | ||
2812 | pci_set_drvdata(pdev, NULL); | |
2813 | } | |
2814 | } | |
2815 | ||
d9a811d5 SH |
2816 | static const struct net_device_ops gem_netdev_ops = { |
2817 | .ndo_open = gem_open, | |
2818 | .ndo_stop = gem_close, | |
2819 | .ndo_start_xmit = gem_start_xmit, | |
2820 | .ndo_get_stats = gem_get_stats, | |
afc4b13d | 2821 | .ndo_set_rx_mode = gem_set_multicast, |
d9a811d5 SH |
2822 | .ndo_do_ioctl = gem_ioctl, |
2823 | .ndo_tx_timeout = gem_tx_timeout, | |
2824 | .ndo_change_mtu = gem_change_mtu, | |
d9a811d5 | 2825 | .ndo_validate_addr = eth_validate_addr, |
5ed0102f SH |
2826 | .ndo_set_mac_address = gem_set_mac_address, |
2827 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2828 | .ndo_poll_controller = gem_poll_controller, | |
2829 | #endif | |
d9a811d5 SH |
2830 | }; |
2831 | ||
1da177e4 LT |
2832 | static int __devinit gem_init_one(struct pci_dev *pdev, |
2833 | const struct pci_device_id *ent) | |
2834 | { | |
1da177e4 LT |
2835 | unsigned long gemreg_base, gemreg_len; |
2836 | struct net_device *dev; | |
2837 | struct gem *gp; | |
0795af57 | 2838 | int err, pci_using_dac; |
1da177e4 | 2839 | |
c6c75988 | 2840 | printk_once(KERN_INFO "%s", version); |
1da177e4 LT |
2841 | |
2842 | /* Apple gmac note: during probe, the chip is powered up by | |
2843 | * the arch code to allow the code below to work (and to let | |
2844 | * the chip be probed on the config space. It won't stay powered | |
2845 | * up until the interface is brought up however, so we can't rely | |
2846 | * on register configuration done at this point. | |
2847 | */ | |
2848 | err = pci_enable_device(pdev); | |
2849 | if (err) { | |
c6c75988 | 2850 | pr_err("Cannot enable MMIO operation, aborting\n"); |
1da177e4 LT |
2851 | return err; |
2852 | } | |
2853 | pci_set_master(pdev); | |
2854 | ||
2855 | /* Configure DMA attributes. */ | |
2856 | ||
2857 | /* All of the GEM documentation states that 64-bit DMA addressing | |
2858 | * is fully supported and should work just fine. However the | |
2859 | * front end for RIO based GEMs is different and only supports | |
2860 | * 32-bit addressing. | |
2861 | * | |
2862 | * For now we assume the various PPC GEMs are 32-bit only as well. | |
2863 | */ | |
2864 | if (pdev->vendor == PCI_VENDOR_ID_SUN && | |
2865 | pdev->device == PCI_DEVICE_ID_SUN_GEM && | |
6a35528a | 2866 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
1da177e4 LT |
2867 | pci_using_dac = 1; |
2868 | } else { | |
284901a9 | 2869 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2870 | if (err) { |
c6c75988 | 2871 | pr_err("No usable DMA configuration, aborting\n"); |
1da177e4 LT |
2872 | goto err_disable_device; |
2873 | } | |
2874 | pci_using_dac = 0; | |
2875 | } | |
6aa20a22 | 2876 | |
1da177e4 LT |
2877 | gemreg_base = pci_resource_start(pdev, 0); |
2878 | gemreg_len = pci_resource_len(pdev, 0); | |
2879 | ||
2880 | if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) { | |
c6c75988 | 2881 | pr_err("Cannot find proper PCI device base address, aborting\n"); |
1da177e4 LT |
2882 | err = -ENODEV; |
2883 | goto err_disable_device; | |
2884 | } | |
2885 | ||
2886 | dev = alloc_etherdev(sizeof(*gp)); | |
2887 | if (!dev) { | |
1da177e4 LT |
2888 | err = -ENOMEM; |
2889 | goto err_disable_device; | |
2890 | } | |
1da177e4 LT |
2891 | SET_NETDEV_DEV(dev, &pdev->dev); |
2892 | ||
8f15ea42 | 2893 | gp = netdev_priv(dev); |
1da177e4 LT |
2894 | |
2895 | err = pci_request_regions(pdev, DRV_NAME); | |
2896 | if (err) { | |
c6c75988 | 2897 | pr_err("Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
2898 | goto err_out_free_netdev; |
2899 | } | |
2900 | ||
2901 | gp->pdev = pdev; | |
2902 | dev->base_addr = (long) pdev; | |
2903 | gp->dev = dev; | |
2904 | ||
2905 | gp->msg_enable = DEFAULT_MSG; | |
2906 | ||
1da177e4 LT |
2907 | init_timer(&gp->link_timer); |
2908 | gp->link_timer.function = gem_link_timer; | |
2909 | gp->link_timer.data = (unsigned long) gp; | |
2910 | ||
c4028958 | 2911 | INIT_WORK(&gp->reset_task, gem_reset_task); |
6aa20a22 | 2912 | |
1da177e4 LT |
2913 | gp->lstate = link_down; |
2914 | gp->timer_ticks = 0; | |
2915 | netif_carrier_off(dev); | |
2916 | ||
2917 | gp->regs = ioremap(gemreg_base, gemreg_len); | |
79ea13ce | 2918 | if (!gp->regs) { |
c6c75988 | 2919 | pr_err("Cannot map device registers, aborting\n"); |
1da177e4 LT |
2920 | err = -EIO; |
2921 | goto err_out_free_res; | |
2922 | } | |
2923 | ||
2924 | /* On Apple, we want a reference to the Open Firmware device-tree | |
2925 | * node. We use it for clock control. | |
2926 | */ | |
457e1a8a | 2927 | #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC) |
1da177e4 LT |
2928 | gp->of_node = pci_device_to_OF_node(pdev); |
2929 | #endif | |
2930 | ||
2931 | /* Only Apple version supports WOL afaik */ | |
2932 | if (pdev->vendor == PCI_VENDOR_ID_APPLE) | |
2933 | gp->has_wol = 1; | |
2934 | ||
2935 | /* Make sure cell is enabled */ | |
2936 | gem_get_cell(gp); | |
2937 | ||
2938 | /* Make sure everything is stopped and in init state */ | |
2939 | gem_reset(gp); | |
2940 | ||
2941 | /* Fill up the mii_phy structure (even if we won't use it) */ | |
2942 | gp->phy_mii.dev = dev; | |
2943 | gp->phy_mii.mdio_read = _phy_read; | |
2944 | gp->phy_mii.mdio_write = _phy_write; | |
3c326fe9 BH |
2945 | #ifdef CONFIG_PPC_PMAC |
2946 | gp->phy_mii.platform_data = gp->of_node; | |
2947 | #endif | |
1da177e4 LT |
2948 | /* By default, we start with autoneg */ |
2949 | gp->want_autoneg = 1; | |
2950 | ||
2951 | /* Check fifo sizes, PHY type, etc... */ | |
2952 | if (gem_check_invariants(gp)) { | |
2953 | err = -ENODEV; | |
2954 | goto err_out_iounmap; | |
2955 | } | |
2956 | ||
2957 | /* It is guaranteed that the returned buffer will be at least | |
2958 | * PAGE_SIZE aligned. | |
2959 | */ | |
2960 | gp->init_block = (struct gem_init_block *) | |
2961 | pci_alloc_consistent(pdev, sizeof(struct gem_init_block), | |
2962 | &gp->gblock_dvma); | |
2963 | if (!gp->init_block) { | |
c6c75988 | 2964 | pr_err("Cannot allocate init block, aborting\n"); |
1da177e4 LT |
2965 | err = -ENOMEM; |
2966 | goto err_out_iounmap; | |
2967 | } | |
2968 | ||
2969 | if (gem_get_device_address(gp)) | |
2970 | goto err_out_free_consistent; | |
2971 | ||
d9a811d5 | 2972 | dev->netdev_ops = &gem_netdev_ops; |
bea3348e | 2973 | netif_napi_add(dev, &gp->napi, gem_poll, 64); |
1da177e4 | 2974 | dev->ethtool_ops = &gem_ethtool_ops; |
1da177e4 | 2975 | dev->watchdog_timeo = 5 * HZ; |
1da177e4 LT |
2976 | dev->irq = pdev->irq; |
2977 | dev->dma = 0; | |
1da177e4 LT |
2978 | |
2979 | /* Set that now, in case PM kicks in now */ | |
2980 | pci_set_drvdata(pdev, dev); | |
2981 | ||
fe09bb61 BH |
2982 | /* We can do scatter/gather and HW checksum */ |
2983 | dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM; | |
2984 | dev->features |= dev->hw_features | NETIF_F_RXCSUM; | |
2985 | if (pci_using_dac) | |
2986 | dev->features |= NETIF_F_HIGHDMA; | |
1da177e4 LT |
2987 | |
2988 | /* Register with kernel */ | |
2989 | if (register_netdev(dev)) { | |
c6c75988 | 2990 | pr_err("Cannot register net device, aborting\n"); |
1da177e4 LT |
2991 | err = -ENOMEM; |
2992 | goto err_out_free_consistent; | |
2993 | } | |
2994 | ||
fe09bb61 BH |
2995 | /* Undo the get_cell with appropriate locking (we could use |
2996 | * ndo_init/uninit but that would be even more clumsy imho) | |
2997 | */ | |
2998 | rtnl_lock(); | |
2999 | gem_put_cell(gp); | |
3000 | rtnl_unlock(); | |
3001 | ||
c6c75988 JP |
3002 | netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n", |
3003 | dev->dev_addr); | |
1da177e4 LT |
3004 | return 0; |
3005 | ||
3006 | err_out_free_consistent: | |
3007 | gem_remove_one(pdev); | |
3008 | err_out_iounmap: | |
3009 | gem_put_cell(gp); | |
3010 | iounmap(gp->regs); | |
3011 | ||
3012 | err_out_free_res: | |
3013 | pci_release_regions(pdev); | |
3014 | ||
3015 | err_out_free_netdev: | |
3016 | free_netdev(dev); | |
3017 | err_disable_device: | |
3018 | pci_disable_device(pdev); | |
3019 | return err; | |
3020 | ||
3021 | } | |
3022 | ||
3023 | ||
3024 | static struct pci_driver gem_driver = { | |
3025 | .name = GEM_MODULE_NAME, | |
3026 | .id_table = gem_pci_tbl, | |
3027 | .probe = gem_init_one, | |
14904398 | 3028 | .remove = gem_remove_one, |
1da177e4 LT |
3029 | #ifdef CONFIG_PM |
3030 | .suspend = gem_suspend, | |
3031 | .resume = gem_resume, | |
3032 | #endif /* CONFIG_PM */ | |
3033 | }; | |
3034 | ||
3035 | static int __init gem_init(void) | |
3036 | { | |
29917620 | 3037 | return pci_register_driver(&gem_driver); |
1da177e4 LT |
3038 | } |
3039 | ||
3040 | static void __exit gem_cleanup(void) | |
3041 | { | |
3042 | pci_unregister_driver(&gem_driver); | |
3043 | } | |
3044 | ||
3045 | module_init(gem_init); | |
3046 | module_exit(gem_cleanup); |