]>
Commit | Line | Data |
---|---|---|
1a348ccc AG |
1 | /* |
2 | * Tehuti Networks(R) Network Driver | |
3 | * ethtool interface implementation | |
4 | * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * RX HW/SW interaction overview | |
14 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
b595076a | 15 | * There are 2 types of RX communication channels between driver and NIC. |
1a348ccc AG |
16 | * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming |
17 | * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds | |
18 | * info about buffer's location, size and ID. An ID field is used to identify a | |
19 | * buffer when it's returned with data via RXD Fifo (see below) | |
20 | * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is | |
21 | * filled by HW and is readen by SW. Each descriptor holds status and ID. | |
22 | * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data, | |
23 | * via dma moves it into host memory, builds new RXD descriptor with same ID, | |
24 | * pushes it into RXD Fifo and raises interrupt to indicate new RX data. | |
25 | * | |
26 | * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos. | |
27 | * One holds 1.5K packets and another - 26K packets. Depending on incoming | |
28 | * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is | |
29 | * filled with data, HW builds new RXD descriptor for it and push it into single | |
30 | * RXD Fifo. | |
31 | * | |
32 | * RX SW Data Structures | |
33 | * ~~~~~~~~~~~~~~~~~~~~~ | |
34 | * skb db - used to keep track of all skbs owned by SW and their dma addresses. | |
35 | * For RX case, ownership lasts from allocating new empty skb for RXF until | |
36 | * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own | |
37 | * skb db. Implemented as array with bitmask. | |
38 | * fifo - keeps info about fifo's size and location, relevant HW registers, | |
39 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. | |
40 | * Implemented as simple struct. | |
41 | * | |
42 | * RX SW Execution Flow | |
43 | * ~~~~~~~~~~~~~~~~~~~~ | |
44 | * Upon initialization (ifconfig up) driver creates RX fifos and initializes | |
45 | * relevant registers. At the end of init phase, driver enables interrupts. | |
46 | * NIC sees that there is no RXF buffers and raises | |
47 | * RD_INTR interrupt, isr fills skbs and Rx begins. | |
48 | * Driver has two receive operation modes: | |
49 | * NAPI - interrupt-driven mixed with polling | |
50 | * interrupt-driven only | |
51 | * | |
52 | * Interrupt-driven only flow is following. When buffer is ready, HW raises | |
53 | * interrupt and isr is called. isr collects all available packets | |
54 | * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit. | |
55 | ||
56 | * Rx buffer allocation note | |
57 | * ~~~~~~~~~~~~~~~~~~~~~~~~~ | |
58 | * Driver cares to feed such amount of RxF descriptors that respective amount of | |
59 | * RxD descriptors can not fill entire RxD fifo. The main reason is lack of | |
60 | * overflow check in Bordeaux for RxD fifo free/used size. | |
61 | * FIXME: this is NOT fully implemented, more work should be done | |
62 | * | |
63 | */ | |
64 | ||
865a21a5 JP |
65 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
66 | ||
1a348ccc | 67 | #include "tehuti.h" |
1a348ccc | 68 | |
9baa3c34 | 69 | static const struct pci_device_id bdx_pci_tbl[] = { |
a355d865 | 70 | { PCI_VDEVICE(TEHUTI, 0x3009), }, |
71 | { PCI_VDEVICE(TEHUTI, 0x3010), }, | |
72 | { PCI_VDEVICE(TEHUTI, 0x3014), }, | |
73 | { 0 } | |
1a348ccc AG |
74 | }; |
75 | ||
76 | MODULE_DEVICE_TABLE(pci, bdx_pci_tbl); | |
77 | ||
78 | /* Definitions needed by ISR or NAPI functions */ | |
79 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f); | |
80 | static void bdx_tx_cleanup(struct bdx_priv *priv); | |
81 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget); | |
82 | ||
83 | /* Definitions needed by FW loading */ | |
84 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size); | |
85 | ||
86 | /* Definitions needed by hw_start */ | |
87 | static int bdx_tx_init(struct bdx_priv *priv); | |
88 | static int bdx_rx_init(struct bdx_priv *priv); | |
89 | ||
90 | /* Definitions needed by bdx_close */ | |
91 | static void bdx_rx_free(struct bdx_priv *priv); | |
92 | static void bdx_tx_free(struct bdx_priv *priv); | |
93 | ||
94 | /* Definitions needed by bdx_probe */ | |
c061b18d | 95 | static void bdx_set_ethtool_ops(struct net_device *netdev); |
1a348ccc AG |
96 | |
97 | /************************************************************************* | |
98 | * Print Info * | |
99 | *************************************************************************/ | |
100 | ||
101 | static void print_hw_id(struct pci_dev *pdev) | |
102 | { | |
103 | struct pci_nic *nic = pci_get_drvdata(pdev); | |
104 | u16 pci_link_status = 0; | |
105 | u16 pci_ctrl = 0; | |
106 | ||
107 | pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status); | |
108 | pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl); | |
109 | ||
865a21a5 JP |
110 | pr_info("%s%s\n", BDX_NIC_NAME, |
111 | nic->port_num == 1 ? "" : ", 2-Port"); | |
112 | pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n", | |
113 | readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF, | |
114 | readl(nic->regs + FPGA_SEED), | |
115 | GET_LINK_STATUS_LANES(pci_link_status), | |
116 | GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl)); | |
1a348ccc AG |
117 | } |
118 | ||
119 | static void print_fw_id(struct pci_nic *nic) | |
120 | { | |
865a21a5 | 121 | pr_info("fw 0x%x\n", readl(nic->regs + FW_VER)); |
1a348ccc AG |
122 | } |
123 | ||
124 | static void print_eth_id(struct net_device *ndev) | |
125 | { | |
865a21a5 JP |
126 | netdev_info(ndev, "%s, Port %c\n", |
127 | BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B'); | |
1a348ccc AG |
128 | |
129 | } | |
130 | ||
131 | /************************************************************************* | |
132 | * Code * | |
133 | *************************************************************************/ | |
134 | ||
135 | #define bdx_enable_interrupts(priv) \ | |
136 | do { WRITE_REG(priv, regIMR, IR_RUN); } while (0) | |
137 | #define bdx_disable_interrupts(priv) \ | |
138 | do { WRITE_REG(priv, regIMR, 0); } while (0) | |
139 | ||
49ce9c2c BH |
140 | /** |
141 | * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication. | |
142 | * @priv: NIC private structure | |
143 | * @f: fifo to initialize | |
144 | * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB | |
145 | * @reg_XXX: offsets of registers relative to base address | |
146 | * | |
1a348ccc AG |
147 | * 1K extra space is allocated at the end of the fifo to simplify |
148 | * processing of descriptors that wraps around fifo's end | |
1a348ccc AG |
149 | * |
150 | * Returns 0 on success, negative value on failure | |
151 | * | |
152 | */ | |
153 | static int | |
154 | bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type, | |
155 | u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR) | |
156 | { | |
157 | u16 memsz = FIFO_SIZE * (1 << fsz_type); | |
158 | ||
159 | memset(f, 0, sizeof(struct fifo)); | |
160 | /* pci_alloc_consistent gives us 4k-aligned memory */ | |
161 | f->va = pci_alloc_consistent(priv->pdev, | |
162 | memsz + FIFO_EXTRA_SPACE, &f->da); | |
163 | if (!f->va) { | |
865a21a5 | 164 | pr_err("pci_alloc_consistent failed\n"); |
1a348ccc AG |
165 | RET(-ENOMEM); |
166 | } | |
167 | f->reg_CFG0 = reg_CFG0; | |
168 | f->reg_CFG1 = reg_CFG1; | |
169 | f->reg_RPTR = reg_RPTR; | |
170 | f->reg_WPTR = reg_WPTR; | |
171 | f->rptr = 0; | |
172 | f->wptr = 0; | |
173 | f->memsz = memsz; | |
174 | f->size_mask = memsz - 1; | |
175 | WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type)); | |
176 | WRITE_REG(priv, reg_CFG1, H32_64(f->da)); | |
177 | ||
178 | RET(0); | |
179 | } | |
180 | ||
49ce9c2c BH |
181 | /** |
182 | * bdx_fifo_free - free all resources used by fifo | |
183 | * @priv: NIC private structure | |
184 | * @f: fifo to release | |
1a348ccc AG |
185 | */ |
186 | static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f) | |
187 | { | |
188 | ENTER; | |
189 | if (f->va) { | |
190 | pci_free_consistent(priv->pdev, | |
191 | f->memsz + FIFO_EXTRA_SPACE, f->va, f->da); | |
192 | f->va = NULL; | |
193 | } | |
194 | RET(); | |
195 | } | |
196 | ||
49ce9c2c | 197 | /** |
1a348ccc | 198 | * bdx_link_changed - notifies OS about hw link state. |
49ce9c2c | 199 | * @priv: hw adapter structure |
1a348ccc AG |
200 | */ |
201 | static void bdx_link_changed(struct bdx_priv *priv) | |
202 | { | |
203 | u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT; | |
204 | ||
205 | if (!link) { | |
206 | if (netif_carrier_ok(priv->ndev)) { | |
207 | netif_stop_queue(priv->ndev); | |
208 | netif_carrier_off(priv->ndev); | |
865a21a5 | 209 | netdev_err(priv->ndev, "Link Down\n"); |
1a348ccc AG |
210 | } |
211 | } else { | |
212 | if (!netif_carrier_ok(priv->ndev)) { | |
213 | netif_wake_queue(priv->ndev); | |
214 | netif_carrier_on(priv->ndev); | |
865a21a5 | 215 | netdev_err(priv->ndev, "Link Up\n"); |
1a348ccc AG |
216 | } |
217 | } | |
218 | } | |
219 | ||
220 | static void bdx_isr_extra(struct bdx_priv *priv, u32 isr) | |
221 | { | |
222 | if (isr & IR_RX_FREE_0) { | |
223 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
224 | DBG("RX_FREE_0\n"); | |
225 | } | |
226 | ||
227 | if (isr & IR_LNKCHG0) | |
228 | bdx_link_changed(priv); | |
229 | ||
230 | if (isr & IR_PCIE_LINK) | |
865a21a5 | 231 | netdev_err(priv->ndev, "PCI-E Link Fault\n"); |
1a348ccc AG |
232 | |
233 | if (isr & IR_PCIE_TOUT) | |
865a21a5 | 234 | netdev_err(priv->ndev, "PCI-E Time Out\n"); |
1a348ccc AG |
235 | |
236 | } | |
237 | ||
49ce9c2c BH |
238 | /** |
239 | * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC | |
240 | * @irq: interrupt number | |
241 | * @dev: network device | |
1a348ccc AG |
242 | * |
243 | * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise | |
244 | * | |
245 | * It reads ISR register to know interrupt reasons, and proceed them one by one. | |
246 | * Reasons of interest are: | |
247 | * RX_DESC - new packet has arrived and RXD fifo holds its descriptor | |
248 | * RX_FREE - number of free Rx buffers in RXF fifo gets low | |
249 | * TX_FREE - packet was transmited and RXF fifo holds its descriptor | |
250 | */ | |
251 | ||
252 | static irqreturn_t bdx_isr_napi(int irq, void *dev) | |
253 | { | |
254 | struct net_device *ndev = dev; | |
8f15ea42 | 255 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
256 | u32 isr; |
257 | ||
258 | ENTER; | |
259 | isr = (READ_REG(priv, regISR) & IR_RUN); | |
260 | if (unlikely(!isr)) { | |
261 | bdx_enable_interrupts(priv); | |
262 | return IRQ_NONE; /* Not our interrupt */ | |
263 | } | |
264 | ||
265 | if (isr & IR_EXTRA) | |
266 | bdx_isr_extra(priv, isr); | |
267 | ||
268 | if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) { | |
288379f0 BH |
269 | if (likely(napi_schedule_prep(&priv->napi))) { |
270 | __napi_schedule(&priv->napi); | |
1a348ccc AG |
271 | RET(IRQ_HANDLED); |
272 | } else { | |
273 | /* NOTE: we get here if intr has slipped into window | |
274 | * between these lines in bdx_poll: | |
275 | * bdx_enable_interrupts(priv); | |
276 | * return 0; | |
277 | * currently intrs are disabled (since we read ISR), | |
278 | * and we have failed to register next poll. | |
279 | * so we read the regs to trigger chip | |
280 | * and allow further interupts. */ | |
281 | READ_REG(priv, regTXF_WPTR_0); | |
282 | READ_REG(priv, regRXD_WPTR_0); | |
283 | } | |
284 | } | |
285 | ||
286 | bdx_enable_interrupts(priv); | |
287 | RET(IRQ_HANDLED); | |
288 | } | |
289 | ||
290 | static int bdx_poll(struct napi_struct *napi, int budget) | |
291 | { | |
292 | struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi); | |
1a348ccc AG |
293 | int work_done; |
294 | ||
295 | ENTER; | |
296 | bdx_tx_cleanup(priv); | |
297 | work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget); | |
298 | if ((work_done < budget) || | |
299 | (priv->napi_stop++ >= 30)) { | |
300 | DBG("rx poll is done. backing to isr-driven\n"); | |
301 | ||
302 | /* from time to time we exit to let NAPI layer release | |
303 | * device lock and allow waiting tasks (eg rmmod) to advance) */ | |
304 | priv->napi_stop = 0; | |
305 | ||
6ad20165 | 306 | napi_complete_done(napi, work_done); |
1a348ccc AG |
307 | bdx_enable_interrupts(priv); |
308 | } | |
309 | return work_done; | |
310 | } | |
311 | ||
49ce9c2c BH |
312 | /** |
313 | * bdx_fw_load - loads firmware to NIC | |
314 | * @priv: NIC private structure | |
315 | * | |
1a348ccc AG |
316 | * Firmware is loaded via TXD fifo, so it must be initialized first. |
317 | * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC | |
318 | * can have few of them). So all drivers use semaphore register to choose one | |
319 | * that will actually load FW to NIC. | |
320 | */ | |
321 | ||
322 | static int bdx_fw_load(struct bdx_priv *priv) | |
323 | { | |
06e1f9ff | 324 | const struct firmware *fw = NULL; |
1a348ccc | 325 | int master, i; |
06e1f9ff | 326 | int rc; |
1a348ccc AG |
327 | |
328 | ENTER; | |
329 | master = READ_REG(priv, regINIT_SEMAPHORE); | |
330 | if (!READ_REG(priv, regINIT_STATUS) && master) { | |
46814e08 | 331 | rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev); |
06e1f9ff BH |
332 | if (rc) |
333 | goto out; | |
334 | bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size); | |
1a348ccc AG |
335 | mdelay(100); |
336 | } | |
337 | for (i = 0; i < 200; i++) { | |
06e1f9ff BH |
338 | if (READ_REG(priv, regINIT_STATUS)) { |
339 | rc = 0; | |
340 | goto out; | |
341 | } | |
1a348ccc AG |
342 | mdelay(2); |
343 | } | |
06e1f9ff BH |
344 | rc = -EIO; |
345 | out: | |
1a348ccc AG |
346 | if (master) |
347 | WRITE_REG(priv, regINIT_SEMAPHORE, 1); | |
53c0ad52 JJ |
348 | |
349 | release_firmware(fw); | |
1a348ccc | 350 | |
06e1f9ff | 351 | if (rc) { |
865a21a5 | 352 | netdev_err(priv->ndev, "firmware loading failed\n"); |
06e1f9ff BH |
353 | if (rc == -EIO) |
354 | DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n", | |
355 | READ_REG(priv, regVPC), | |
356 | READ_REG(priv, regVIC), | |
357 | READ_REG(priv, regINIT_STATUS), i); | |
358 | RET(rc); | |
1a348ccc AG |
359 | } else { |
360 | DBG("%s: firmware loading success\n", priv->ndev->name); | |
361 | RET(0); | |
362 | } | |
363 | } | |
364 | ||
365 | static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv) | |
366 | { | |
367 | u32 val; | |
368 | ||
369 | ENTER; | |
370 | DBG("mac0=%x mac1=%x mac2=%x\n", | |
371 | READ_REG(priv, regUNC_MAC0_A), | |
372 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); | |
373 | ||
374 | val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); | |
375 | WRITE_REG(priv, regUNC_MAC2_A, val); | |
376 | val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); | |
377 | WRITE_REG(priv, regUNC_MAC1_A, val); | |
378 | val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); | |
379 | WRITE_REG(priv, regUNC_MAC0_A, val); | |
380 | ||
381 | DBG("mac0=%x mac1=%x mac2=%x\n", | |
382 | READ_REG(priv, regUNC_MAC0_A), | |
383 | READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A)); | |
384 | RET(); | |
385 | } | |
386 | ||
49ce9c2c BH |
387 | /** |
388 | * bdx_hw_start - inits registers and starts HW's Rx and Tx engines | |
389 | * @priv: NIC private structure | |
1a348ccc AG |
390 | */ |
391 | static int bdx_hw_start(struct bdx_priv *priv) | |
392 | { | |
393 | int rc = -EIO; | |
394 | struct net_device *ndev = priv->ndev; | |
395 | ||
396 | ENTER; | |
397 | bdx_link_changed(priv); | |
398 | ||
399 | /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */ | |
400 | WRITE_REG(priv, regFRM_LENGTH, 0X3FE0); | |
401 | WRITE_REG(priv, regPAUSE_QUANT, 0x96); | |
402 | WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010); | |
403 | WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010); | |
404 | WRITE_REG(priv, regRX_FULLNESS, 0); | |
405 | WRITE_REG(priv, regTX_FULLNESS, 0); | |
406 | WRITE_REG(priv, regCTRLST, | |
407 | regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA); | |
408 | ||
409 | WRITE_REG(priv, regVGLB, 0); | |
410 | WRITE_REG(priv, regMAX_FRAME_A, | |
411 | priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL); | |
412 | ||
413 | DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */ | |
414 | WRITE_REG(priv, regRDINTCM0, priv->rdintcm); | |
415 | WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */ | |
416 | ||
417 | DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */ | |
418 | WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */ | |
419 | ||
420 | /* Enable timer interrupt once in 2 secs. */ | |
421 | /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */ | |
422 | bdx_restore_mac(priv->ndev, priv); | |
423 | ||
424 | WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN | | |
425 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB); | |
426 | ||
249658d5 | 427 | #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED) |
cb001a1f JP |
428 | |
429 | rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE, | |
430 | ndev->name, ndev); | |
431 | if (rc) | |
1a348ccc AG |
432 | goto err_irq; |
433 | bdx_enable_interrupts(priv); | |
434 | ||
435 | RET(0); | |
436 | ||
437 | err_irq: | |
438 | RET(rc); | |
439 | } | |
440 | ||
441 | static void bdx_hw_stop(struct bdx_priv *priv) | |
442 | { | |
443 | ENTER; | |
444 | bdx_disable_interrupts(priv); | |
445 | free_irq(priv->pdev->irq, priv->ndev); | |
446 | ||
447 | netif_carrier_off(priv->ndev); | |
448 | netif_stop_queue(priv->ndev); | |
449 | ||
450 | RET(); | |
451 | } | |
452 | ||
453 | static int bdx_hw_reset_direct(void __iomem *regs) | |
454 | { | |
455 | u32 val, i; | |
456 | ENTER; | |
457 | ||
458 | /* reset sequences: read, write 1, read, write 0 */ | |
459 | val = readl(regs + regCLKPLL); | |
460 | writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL); | |
461 | udelay(50); | |
462 | val = readl(regs + regCLKPLL); | |
463 | writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL); | |
464 | ||
465 | /* check that the PLLs are locked and reset ended */ | |
466 | for (i = 0; i < 70; i++, mdelay(10)) | |
467 | if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { | |
468 | /* do any PCI-E read transaction */ | |
469 | readl(regs + regRXD_CFG0_0); | |
470 | return 0; | |
471 | } | |
865a21a5 | 472 | pr_err("HW reset failed\n"); |
1a348ccc AG |
473 | return 1; /* failure */ |
474 | } | |
475 | ||
476 | static int bdx_hw_reset(struct bdx_priv *priv) | |
477 | { | |
478 | u32 val, i; | |
479 | ENTER; | |
480 | ||
481 | if (priv->port == 0) { | |
482 | /* reset sequences: read, write 1, read, write 0 */ | |
483 | val = READ_REG(priv, regCLKPLL); | |
484 | WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8); | |
485 | udelay(50); | |
486 | val = READ_REG(priv, regCLKPLL); | |
487 | WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST); | |
488 | } | |
489 | /* check that the PLLs are locked and reset ended */ | |
490 | for (i = 0; i < 70; i++, mdelay(10)) | |
491 | if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) { | |
492 | /* do any PCI-E read transaction */ | |
493 | READ_REG(priv, regRXD_CFG0_0); | |
494 | return 0; | |
495 | } | |
865a21a5 | 496 | pr_err("HW reset failed\n"); |
1a348ccc AG |
497 | return 1; /* failure */ |
498 | } | |
499 | ||
500 | static int bdx_sw_reset(struct bdx_priv *priv) | |
501 | { | |
502 | int i; | |
503 | ||
504 | ENTER; | |
505 | /* 1. load MAC (obsolete) */ | |
506 | /* 2. disable Rx (and Tx) */ | |
507 | WRITE_REG(priv, regGMAC_RXF_A, 0); | |
508 | mdelay(100); | |
509 | /* 3. disable port */ | |
510 | WRITE_REG(priv, regDIS_PORT, 1); | |
511 | /* 4. disable queue */ | |
512 | WRITE_REG(priv, regDIS_QU, 1); | |
513 | /* 5. wait until hw is disabled */ | |
514 | for (i = 0; i < 50; i++) { | |
515 | if (READ_REG(priv, regRST_PORT) & 1) | |
516 | break; | |
517 | mdelay(10); | |
518 | } | |
519 | if (i == 50) | |
865a21a5 | 520 | netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n"); |
1a348ccc AG |
521 | |
522 | /* 6. disable intrs */ | |
523 | WRITE_REG(priv, regRDINTCM0, 0); | |
524 | WRITE_REG(priv, regTDINTCM0, 0); | |
525 | WRITE_REG(priv, regIMR, 0); | |
526 | READ_REG(priv, regISR); | |
527 | ||
528 | /* 7. reset queue */ | |
529 | WRITE_REG(priv, regRST_QU, 1); | |
530 | /* 8. reset port */ | |
531 | WRITE_REG(priv, regRST_PORT, 1); | |
532 | /* 9. zero all read and write pointers */ | |
533 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
534 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); | |
535 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
536 | WRITE_REG(priv, i, 0); | |
537 | /* 10. unseet port disable */ | |
538 | WRITE_REG(priv, regDIS_PORT, 0); | |
539 | /* 11. unset queue disable */ | |
540 | WRITE_REG(priv, regDIS_QU, 0); | |
541 | /* 12. unset queue reset */ | |
542 | WRITE_REG(priv, regRST_QU, 0); | |
543 | /* 13. unset port reset */ | |
544 | WRITE_REG(priv, regRST_PORT, 0); | |
545 | /* 14. enable Rx */ | |
546 | /* skiped. will be done later */ | |
547 | /* 15. save MAC (obsolete) */ | |
548 | for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10) | |
549 | DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR); | |
550 | ||
551 | RET(0); | |
552 | } | |
553 | ||
554 | /* bdx_reset - performs right type of reset depending on hw type */ | |
555 | static int bdx_reset(struct bdx_priv *priv) | |
556 | { | |
557 | ENTER; | |
558 | RET((priv->pdev->device == 0x3009) | |
559 | ? bdx_hw_reset(priv) | |
560 | : bdx_sw_reset(priv)); | |
561 | } | |
562 | ||
563 | /** | |
564 | * bdx_close - Disables a network interface | |
565 | * @netdev: network interface device structure | |
566 | * | |
567 | * Returns 0, this is not allowed to fail | |
568 | * | |
569 | * The close entry point is called when an interface is de-activated | |
570 | * by the OS. The hardware is still under the drivers control, but | |
571 | * needs to be disabled. A global MAC reset is issued to stop the | |
572 | * hardware, and all transmit and receive resources are freed. | |
573 | **/ | |
574 | static int bdx_close(struct net_device *ndev) | |
575 | { | |
576 | struct bdx_priv *priv = NULL; | |
577 | ||
578 | ENTER; | |
8f15ea42 | 579 | priv = netdev_priv(ndev); |
1a348ccc AG |
580 | |
581 | napi_disable(&priv->napi); | |
582 | ||
583 | bdx_reset(priv); | |
584 | bdx_hw_stop(priv); | |
585 | bdx_rx_free(priv); | |
586 | bdx_tx_free(priv); | |
587 | RET(0); | |
588 | } | |
589 | ||
590 | /** | |
591 | * bdx_open - Called when a network interface is made active | |
592 | * @netdev: network interface device structure | |
593 | * | |
594 | * Returns 0 on success, negative value on failure | |
595 | * | |
596 | * The open entry point is called when a network interface is made | |
597 | * active by the system (IFF_UP). At this point all resources needed | |
598 | * for transmit and receive operations are allocated, the interrupt | |
599 | * handler is registered with the OS, the watchdog timer is started, | |
600 | * and the stack is notified that the interface is ready. | |
601 | **/ | |
602 | static int bdx_open(struct net_device *ndev) | |
603 | { | |
604 | struct bdx_priv *priv; | |
605 | int rc; | |
606 | ||
607 | ENTER; | |
8f15ea42 | 608 | priv = netdev_priv(ndev); |
1a348ccc AG |
609 | bdx_reset(priv); |
610 | if (netif_running(ndev)) | |
611 | netif_stop_queue(priv->ndev); | |
612 | ||
cb001a1f JP |
613 | if ((rc = bdx_tx_init(priv)) || |
614 | (rc = bdx_rx_init(priv)) || | |
615 | (rc = bdx_fw_load(priv))) | |
1a348ccc AG |
616 | goto err; |
617 | ||
618 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
619 | ||
cb001a1f JP |
620 | rc = bdx_hw_start(priv); |
621 | if (rc) | |
1a348ccc AG |
622 | goto err; |
623 | ||
624 | napi_enable(&priv->napi); | |
625 | ||
626 | print_fw_id(priv->nic); | |
627 | ||
628 | RET(0); | |
629 | ||
630 | err: | |
631 | bdx_close(ndev); | |
632 | RET(rc); | |
633 | } | |
634 | ||
6131a260 FR |
635 | static int bdx_range_check(struct bdx_priv *priv, u32 offset) |
636 | { | |
637 | return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ? | |
638 | -EINVAL : 0; | |
639 | } | |
640 | ||
1a348ccc AG |
641 | static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd) |
642 | { | |
8f15ea42 | 643 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
644 | u32 data[3]; |
645 | int error; | |
646 | ||
647 | ENTER; | |
648 | ||
649 | DBG("jiffies=%ld cmd=%d\n", jiffies, cmd); | |
650 | if (cmd != SIOCDEVPRIVATE) { | |
651 | error = copy_from_user(data, ifr->ifr_data, sizeof(data)); | |
652 | if (error) { | |
25985edc | 653 | pr_err("can't copy from user\n"); |
d2338070 | 654 | RET(-EFAULT); |
1a348ccc AG |
655 | } |
656 | DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]); | |
657 | } | |
658 | ||
62035542 | 659 | if (!capable(CAP_SYS_RAWIO)) |
f946dffe JG |
660 | return -EPERM; |
661 | ||
1a348ccc AG |
662 | switch (data[0]) { |
663 | ||
664 | case BDX_OP_READ: | |
6131a260 FR |
665 | error = bdx_range_check(priv, data[1]); |
666 | if (error < 0) | |
667 | return error; | |
1a348ccc AG |
668 | data[2] = READ_REG(priv, data[1]); |
669 | DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2], | |
670 | data[2]); | |
671 | error = copy_to_user(ifr->ifr_data, data, sizeof(data)); | |
672 | if (error) | |
d2338070 | 673 | RET(-EFAULT); |
1a348ccc AG |
674 | break; |
675 | ||
676 | case BDX_OP_WRITE: | |
6131a260 FR |
677 | error = bdx_range_check(priv, data[1]); |
678 | if (error < 0) | |
679 | return error; | |
1a348ccc AG |
680 | WRITE_REG(priv, data[1], data[2]); |
681 | DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]); | |
682 | break; | |
683 | ||
684 | default: | |
685 | RET(-EOPNOTSUPP); | |
686 | } | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) | |
691 | { | |
692 | ENTER; | |
693 | if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15)) | |
694 | RET(bdx_ioctl_priv(ndev, ifr, cmd)); | |
695 | else | |
696 | RET(-EOPNOTSUPP); | |
697 | } | |
698 | ||
49ce9c2c | 699 | /** |
1a348ccc | 700 | * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid |
49ce9c2c BH |
701 | * @ndev: network device |
702 | * @vid: VLAN vid | |
703 | * @op: add or kill operation | |
704 | * | |
705 | * Passes VLAN filter table to hardware | |
1a348ccc AG |
706 | */ |
707 | static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable) | |
708 | { | |
8f15ea42 | 709 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
710 | u32 reg, bit, val; |
711 | ||
712 | ENTER; | |
713 | DBG2("vid=%d value=%d\n", (int)vid, enable); | |
714 | if (unlikely(vid >= 4096)) { | |
865a21a5 | 715 | pr_err("invalid VID: %u (> 4096)\n", vid); |
1a348ccc AG |
716 | RET(); |
717 | } | |
718 | reg = regVLAN_0 + (vid / 32) * 4; | |
719 | bit = 1 << vid % 32; | |
720 | val = READ_REG(priv, reg); | |
721 | DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); | |
722 | if (enable) | |
723 | val |= bit; | |
724 | else | |
725 | val &= ~bit; | |
726 | DBG2("new val %x\n", val); | |
727 | WRITE_REG(priv, reg, val); | |
728 | RET(); | |
729 | } | |
730 | ||
49ce9c2c | 731 | /** |
1a348ccc | 732 | * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table |
49ce9c2c BH |
733 | * @ndev: network device |
734 | * @vid: VLAN vid to add | |
1a348ccc | 735 | */ |
80d5c368 | 736 | static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) |
1a348ccc AG |
737 | { |
738 | __bdx_vlan_rx_vid(ndev, vid, 1); | |
8e586137 | 739 | return 0; |
1a348ccc AG |
740 | } |
741 | ||
49ce9c2c | 742 | /** |
1a348ccc | 743 | * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table |
49ce9c2c BH |
744 | * @ndev: network device |
745 | * @vid: VLAN vid to kill | |
1a348ccc | 746 | */ |
80d5c368 | 747 | static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) |
1a348ccc AG |
748 | { |
749 | __bdx_vlan_rx_vid(ndev, vid, 0); | |
8e586137 | 750 | return 0; |
1a348ccc AG |
751 | } |
752 | ||
1a348ccc AG |
753 | /** |
754 | * bdx_change_mtu - Change the Maximum Transfer Unit | |
755 | * @netdev: network interface device structure | |
756 | * @new_mtu: new value for maximum frame size | |
757 | * | |
758 | * Returns 0 on success, negative on failure | |
759 | */ | |
760 | static int bdx_change_mtu(struct net_device *ndev, int new_mtu) | |
761 | { | |
1a348ccc AG |
762 | ENTER; |
763 | ||
1a348ccc AG |
764 | ndev->mtu = new_mtu; |
765 | if (netif_running(ndev)) { | |
766 | bdx_close(ndev); | |
767 | bdx_open(ndev); | |
768 | } | |
769 | RET(0); | |
770 | } | |
771 | ||
772 | static void bdx_setmulti(struct net_device *ndev) | |
773 | { | |
8f15ea42 | 774 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
775 | |
776 | u32 rxf_val = | |
777 | GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN; | |
778 | int i; | |
779 | ||
780 | ENTER; | |
781 | /* IMF - imperfect (hash) rx multicat filter */ | |
782 | /* PMF - perfect rx multicat filter */ | |
783 | ||
784 | /* FIXME: RXE(OFF) */ | |
785 | if (ndev->flags & IFF_PROMISC) { | |
786 | rxf_val |= GMAC_RX_FILTER_PRM; | |
787 | } else if (ndev->flags & IFF_ALLMULTI) { | |
788 | /* set IMF to accept all multicast frmaes */ | |
789 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) | |
790 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0); | |
4cd24eaf | 791 | } else if (!netdev_mc_empty(ndev)) { |
1a348ccc | 792 | u8 hash; |
22bedad3 | 793 | struct netdev_hw_addr *ha; |
1a348ccc AG |
794 | u32 reg, val; |
795 | ||
796 | /* set IMF to deny all multicast frames */ | |
797 | for (i = 0; i < MAC_MCST_HASH_NUM; i++) | |
798 | WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0); | |
799 | /* set PMF to deny all multicast frames */ | |
800 | for (i = 0; i < MAC_MCST_NUM; i++) { | |
801 | WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0); | |
802 | WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0); | |
803 | } | |
804 | ||
805 | /* use PMF to accept first MAC_MCST_NUM (15) addresses */ | |
b595076a | 806 | /* TBD: sort addresses and write them in ascending order |
1a348ccc AG |
807 | * into RX_MAC_MCST regs. we skip this phase now and accept ALL |
808 | * multicast frames throu IMF */ | |
1a348ccc | 809 | /* accept the rest of addresses throu IMF */ |
22bedad3 | 810 | netdev_for_each_mc_addr(ha, ndev) { |
1a348ccc AG |
811 | hash = 0; |
812 | for (i = 0; i < ETH_ALEN; i++) | |
22bedad3 | 813 | hash ^= ha->addr[i]; |
1a348ccc AG |
814 | reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); |
815 | val = READ_REG(priv, reg); | |
816 | val |= (1 << (hash % 32)); | |
817 | WRITE_REG(priv, reg, val); | |
818 | } | |
819 | ||
820 | } else { | |
4cd24eaf | 821 | DBG("only own mac %d\n", netdev_mc_count(ndev)); |
1a348ccc AG |
822 | rxf_val |= GMAC_RX_FILTER_AB; |
823 | } | |
824 | WRITE_REG(priv, regGMAC_RXF_A, rxf_val); | |
825 | /* enable RX */ | |
826 | /* FIXME: RXE(ON) */ | |
827 | RET(); | |
828 | } | |
829 | ||
830 | static int bdx_set_mac(struct net_device *ndev, void *p) | |
831 | { | |
8f15ea42 | 832 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
833 | struct sockaddr *addr = p; |
834 | ||
835 | ENTER; | |
836 | /* | |
837 | if (netif_running(dev)) | |
838 | return -EBUSY | |
839 | */ | |
840 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
841 | bdx_restore_mac(ndev, priv); | |
842 | RET(0); | |
843 | } | |
844 | ||
845 | static int bdx_read_mac(struct bdx_priv *priv) | |
846 | { | |
847 | u16 macAddress[3], i; | |
848 | ENTER; | |
849 | ||
850 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); | |
851 | macAddress[2] = READ_REG(priv, regUNC_MAC0_A); | |
852 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); | |
853 | macAddress[1] = READ_REG(priv, regUNC_MAC1_A); | |
854 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); | |
855 | macAddress[0] = READ_REG(priv, regUNC_MAC2_A); | |
856 | for (i = 0; i < 3; i++) { | |
857 | priv->ndev->dev_addr[i * 2 + 1] = macAddress[i]; | |
858 | priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8; | |
859 | } | |
860 | RET(0); | |
861 | } | |
862 | ||
863 | static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) | |
864 | { | |
865 | u64 val; | |
866 | ||
867 | val = READ_REG(priv, reg); | |
868 | val |= ((u64) READ_REG(priv, reg + 8)) << 32; | |
869 | return val; | |
870 | } | |
871 | ||
872 | /*Do the statistics-update work*/ | |
873 | static void bdx_update_stats(struct bdx_priv *priv) | |
874 | { | |
875 | struct bdx_stats *stats = &priv->hw_stats; | |
876 | u64 *stats_vector = (u64 *) stats; | |
877 | int i; | |
878 | int addr; | |
879 | ||
880 | /*Fill HW structure */ | |
881 | addr = 0x7200; | |
882 | /*First 12 statistics - 0x7200 - 0x72B0 */ | |
883 | for (i = 0; i < 12; i++) { | |
884 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
885 | addr += 0x10; | |
886 | } | |
887 | BDX_ASSERT(addr != 0x72C0); | |
888 | /* 0x72C0-0x72E0 RSRV */ | |
889 | addr = 0x72F0; | |
890 | for (; i < 16; i++) { | |
891 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
892 | addr += 0x10; | |
893 | } | |
894 | BDX_ASSERT(addr != 0x7330); | |
895 | /* 0x7330-0x7360 RSRV */ | |
896 | addr = 0x7370; | |
897 | for (; i < 19; i++) { | |
898 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
899 | addr += 0x10; | |
900 | } | |
901 | BDX_ASSERT(addr != 0x73A0); | |
902 | /* 0x73A0-0x73B0 RSRV */ | |
903 | addr = 0x73C0; | |
904 | for (; i < 23; i++) { | |
905 | stats_vector[i] = bdx_read_l2stat(priv, addr); | |
906 | addr += 0x10; | |
907 | } | |
908 | BDX_ASSERT(addr != 0x7400); | |
909 | BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i); | |
910 | } | |
911 | ||
1a348ccc AG |
912 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, |
913 | u16 rxd_vlan); | |
914 | static void print_rxfd(struct rxf_desc *rxfd); | |
915 | ||
916 | /************************************************************************* | |
917 | * Rx DB * | |
918 | *************************************************************************/ | |
919 | ||
920 | static void bdx_rxdb_destroy(struct rxdb *db) | |
921 | { | |
c0feed87 | 922 | vfree(db); |
1a348ccc AG |
923 | } |
924 | ||
925 | static struct rxdb *bdx_rxdb_create(int nelem) | |
926 | { | |
927 | struct rxdb *db; | |
928 | int i; | |
929 | ||
930 | db = vmalloc(sizeof(struct rxdb) | |
931 | + (nelem * sizeof(int)) | |
932 | + (nelem * sizeof(struct rx_map))); | |
933 | if (likely(db != NULL)) { | |
934 | db->stack = (int *)(db + 1); | |
935 | db->elems = (void *)(db->stack + nelem); | |
936 | db->nelem = nelem; | |
937 | db->top = nelem; | |
938 | for (i = 0; i < nelem; i++) | |
939 | db->stack[i] = nelem - i - 1; /* to make first allocs | |
940 | close to db struct*/ | |
941 | } | |
942 | ||
943 | return db; | |
944 | } | |
945 | ||
946 | static inline int bdx_rxdb_alloc_elem(struct rxdb *db) | |
947 | { | |
948 | BDX_ASSERT(db->top <= 0); | |
949 | return db->stack[--(db->top)]; | |
950 | } | |
951 | ||
952 | static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n) | |
953 | { | |
954 | BDX_ASSERT((n < 0) || (n >= db->nelem)); | |
955 | return db->elems + n; | |
956 | } | |
957 | ||
958 | static inline int bdx_rxdb_available(struct rxdb *db) | |
959 | { | |
960 | return db->top; | |
961 | } | |
962 | ||
963 | static inline void bdx_rxdb_free_elem(struct rxdb *db, int n) | |
964 | { | |
965 | BDX_ASSERT((n >= db->nelem) || (n < 0)); | |
966 | db->stack[(db->top)++] = n; | |
967 | } | |
968 | ||
969 | /************************************************************************* | |
970 | * Rx Init * | |
971 | *************************************************************************/ | |
972 | ||
49ce9c2c BH |
973 | /** |
974 | * bdx_rx_init - initialize RX all related HW and SW resources | |
975 | * @priv: NIC private structure | |
1a348ccc AG |
976 | * |
977 | * Returns 0 on success, negative value on failure | |
978 | * | |
979 | * It creates rxf and rxd fifos, update relevant HW registers, preallocate | |
980 | * skb for rx. It assumes that Rx is desabled in HW | |
981 | * funcs are grouped for better cache usage | |
982 | * | |
025dfdaf | 983 | * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be |
1a348ccc | 984 | * filled and packets will be dropped by nic without getting into host or |
25985edc | 985 | * cousing interrupt. Anyway, in that condition, host has no chance to process |
1a348ccc AG |
986 | * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles |
987 | */ | |
988 | ||
989 | /* TBD: ensure proper packet size */ | |
990 | ||
991 | static int bdx_rx_init(struct bdx_priv *priv) | |
992 | { | |
993 | ENTER; | |
ddfce6bb | 994 | |
1a348ccc AG |
995 | if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size, |
996 | regRXD_CFG0_0, regRXD_CFG1_0, | |
997 | regRXD_RPTR_0, regRXD_WPTR_0)) | |
998 | goto err_mem; | |
999 | if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size, | |
1000 | regRXF_CFG0_0, regRXF_CFG1_0, | |
1001 | regRXF_RPTR_0, regRXF_WPTR_0)) | |
1002 | goto err_mem; | |
cb001a1f JP |
1003 | priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz / |
1004 | sizeof(struct rxf_desc)); | |
1005 | if (!priv->rxdb) | |
1a348ccc AG |
1006 | goto err_mem; |
1007 | ||
1008 | priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN; | |
1009 | return 0; | |
1010 | ||
1011 | err_mem: | |
865a21a5 | 1012 | netdev_err(priv->ndev, "Rx init failed\n"); |
1a348ccc AG |
1013 | return -ENOMEM; |
1014 | } | |
1015 | ||
49ce9c2c BH |
1016 | /** |
1017 | * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo | |
1018 | * @priv: NIC private structure | |
1019 | * @f: RXF fifo | |
1a348ccc AG |
1020 | */ |
1021 | static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f) | |
1022 | { | |
1023 | struct rx_map *dm; | |
1024 | struct rxdb *db = priv->rxdb; | |
1025 | u16 i; | |
1026 | ||
1027 | ENTER; | |
1028 | DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db), | |
1029 | db->nelem - bdx_rxdb_available(db)); | |
1030 | while (bdx_rxdb_available(db) > 0) { | |
1031 | i = bdx_rxdb_alloc_elem(db); | |
1032 | dm = bdx_rxdb_addr_elem(db, i); | |
1033 | dm->dma = 0; | |
1034 | } | |
1035 | for (i = 0; i < db->nelem; i++) { | |
1036 | dm = bdx_rxdb_addr_elem(db, i); | |
1037 | if (dm->dma) { | |
1038 | pci_unmap_single(priv->pdev, | |
1039 | dm->dma, f->m.pktsz, | |
1040 | PCI_DMA_FROMDEVICE); | |
1041 | dev_kfree_skb(dm->skb); | |
1042 | } | |
1043 | } | |
1044 | } | |
1045 | ||
49ce9c2c BH |
1046 | /** |
1047 | * bdx_rx_free - release all Rx resources | |
1048 | * @priv: NIC private structure | |
1049 | * | |
1a348ccc AG |
1050 | * It assumes that Rx is desabled in HW |
1051 | */ | |
1052 | static void bdx_rx_free(struct bdx_priv *priv) | |
1053 | { | |
1054 | ENTER; | |
1055 | if (priv->rxdb) { | |
1056 | bdx_rx_free_skbs(priv, &priv->rxf_fifo0); | |
1057 | bdx_rxdb_destroy(priv->rxdb); | |
1058 | priv->rxdb = NULL; | |
1059 | } | |
1060 | bdx_fifo_free(priv, &priv->rxf_fifo0.m); | |
1061 | bdx_fifo_free(priv, &priv->rxd_fifo0.m); | |
1062 | ||
1063 | RET(); | |
1064 | } | |
1065 | ||
1066 | /************************************************************************* | |
1067 | * Rx Engine * | |
1068 | *************************************************************************/ | |
1069 | ||
49ce9c2c BH |
1070 | /** |
1071 | * bdx_rx_alloc_skbs - fill rxf fifo with new skbs | |
1072 | * @priv: nic's private structure | |
1073 | * @f: RXF fifo that needs skbs | |
1074 | * | |
1a348ccc AG |
1075 | * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo. |
1076 | * skb's virtual and physical addresses are stored in skb db. | |
1077 | * To calculate free space, func uses cached values of RPTR and WPTR | |
1078 | * When needed, it also updates RPTR and WPTR. | |
1079 | */ | |
1080 | ||
1081 | /* TBD: do not update WPTR if no desc were written */ | |
1082 | ||
1083 | static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f) | |
1084 | { | |
1085 | struct sk_buff *skb; | |
1086 | struct rxf_desc *rxfd; | |
1087 | struct rx_map *dm; | |
1088 | int dno, delta, idx; | |
1089 | struct rxdb *db = priv->rxdb; | |
1090 | ||
1091 | ENTER; | |
1092 | dno = bdx_rxdb_available(db) - 1; | |
1093 | while (dno > 0) { | |
dae2e9f4 | 1094 | skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN); |
720a43ef | 1095 | if (!skb) |
1a348ccc | 1096 | break; |
720a43ef | 1097 | |
1a348ccc AG |
1098 | skb_reserve(skb, NET_IP_ALIGN); |
1099 | ||
1100 | idx = bdx_rxdb_alloc_elem(db); | |
1101 | dm = bdx_rxdb_addr_elem(db, idx); | |
1102 | dm->dma = pci_map_single(priv->pdev, | |
1103 | skb->data, f->m.pktsz, | |
1104 | PCI_DMA_FROMDEVICE); | |
1105 | dm->skb = skb; | |
1106 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); | |
1107 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ | |
1108 | rxfd->va_lo = idx; | |
1109 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); | |
1110 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); | |
1111 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); | |
1112 | print_rxfd(rxfd); | |
1113 | ||
1114 | f->m.wptr += sizeof(struct rxf_desc); | |
1115 | delta = f->m.wptr - f->m.memsz; | |
1116 | if (unlikely(delta >= 0)) { | |
1117 | f->m.wptr = delta; | |
1118 | if (delta > 0) { | |
1119 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); | |
1120 | DBG("wrapped descriptor\n"); | |
1121 | } | |
1122 | } | |
1123 | dno--; | |
1124 | } | |
1125 | /*TBD: to do - delayed rxf wptr like in txd */ | |
1126 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1127 | RET(); | |
1128 | } | |
1129 | ||
1130 | static inline void | |
1131 | NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan, | |
1132 | struct sk_buff *skb) | |
1133 | { | |
1134 | ENTER; | |
312cd513 JP |
1135 | DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1)); |
1136 | if (GET_RXD_VTAG(rxd_val1)) { | |
1137 | DBG("%s: vlan rcv vlan '%x' vtag '%x'\n", | |
1a348ccc AG |
1138 | priv->ndev->name, |
1139 | GET_RXD_VLAN_ID(rxd_vlan), | |
312cd513 | 1140 | GET_RXD_VTAG(rxd_val1)); |
86a9bad3 | 1141 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan)); |
1a348ccc | 1142 | } |
312cd513 | 1143 | netif_receive_skb(skb); |
1a348ccc AG |
1144 | } |
1145 | ||
1146 | static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd) | |
1147 | { | |
1148 | struct rxf_desc *rxfd; | |
1149 | struct rx_map *dm; | |
1150 | struct rxf_fifo *f; | |
1151 | struct rxdb *db; | |
1152 | struct sk_buff *skb; | |
1153 | int delta; | |
1154 | ||
1155 | ENTER; | |
1156 | DBG("priv=%p rxdd=%p\n", priv, rxdd); | |
1157 | f = &priv->rxf_fifo0; | |
1158 | db = priv->rxdb; | |
1159 | DBG("db=%p f=%p\n", db, f); | |
1160 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); | |
1161 | DBG("dm=%p\n", dm); | |
1162 | skb = dm->skb; | |
1163 | rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); | |
1164 | rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */ | |
1165 | rxfd->va_lo = rxdd->va_lo; | |
1166 | rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma)); | |
1167 | rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma)); | |
1168 | rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz); | |
1169 | print_rxfd(rxfd); | |
1170 | ||
1171 | f->m.wptr += sizeof(struct rxf_desc); | |
1172 | delta = f->m.wptr - f->m.memsz; | |
1173 | if (unlikely(delta >= 0)) { | |
1174 | f->m.wptr = delta; | |
1175 | if (delta > 0) { | |
1176 | memcpy(f->m.va, f->m.va + f->m.memsz, delta); | |
1177 | DBG("wrapped descriptor\n"); | |
1178 | } | |
1179 | } | |
1180 | RET(); | |
1181 | } | |
1182 | ||
49ce9c2c BH |
1183 | /** |
1184 | * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS | |
25985edc | 1185 | * NOTE: a special treatment is given to non-continuous descriptors |
1a348ccc AG |
1186 | * that start near the end, wraps around and continue at the beginning. a second |
1187 | * part is copied right after the first, and then descriptor is interpreted as | |
1188 | * normal. fifo has an extra space to allow such operations | |
49ce9c2c BH |
1189 | * @priv: nic's private structure |
1190 | * @f: RXF fifo that needs skbs | |
1191 | * @budget: maximum number of packets to receive | |
1a348ccc AG |
1192 | */ |
1193 | ||
1194 | /* TBD: replace memcpy func call by explicite inline asm */ | |
1195 | ||
1196 | static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget) | |
1197 | { | |
0add79e3 | 1198 | struct net_device *ndev = priv->ndev; |
1a348ccc AG |
1199 | struct sk_buff *skb, *skb2; |
1200 | struct rxd_desc *rxdd; | |
1201 | struct rx_map *dm; | |
1202 | struct rxf_fifo *rxf_fifo; | |
1203 | int tmp_len, size; | |
1204 | int done = 0; | |
1205 | int max_done = BDX_MAX_RX_DONE; | |
1206 | struct rxdb *db = NULL; | |
1207 | /* Unmarshalled descriptor - copy of descriptor in host order */ | |
1208 | u32 rxd_val1; | |
1209 | u16 len; | |
1210 | u16 rxd_vlan; | |
1211 | ||
1212 | ENTER; | |
1213 | max_done = budget; | |
1214 | ||
1a348ccc AG |
1215 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; |
1216 | ||
1217 | size = f->m.wptr - f->m.rptr; | |
1218 | if (size < 0) | |
1219 | size = f->m.memsz + size; /* size is negative :-) */ | |
1220 | ||
1221 | while (size > 0) { | |
1222 | ||
1223 | rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); | |
1224 | rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1); | |
1225 | ||
1226 | len = CPU_CHIP_SWAP16(rxdd->len); | |
1227 | ||
1228 | rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan); | |
1229 | ||
1230 | print_rxdd(rxdd, rxd_val1, len, rxd_vlan); | |
1231 | ||
1232 | tmp_len = GET_RXD_BC(rxd_val1) << 3; | |
1233 | BDX_ASSERT(tmp_len <= 0); | |
1234 | size -= tmp_len; | |
1235 | if (size < 0) /* test for partially arrived descriptor */ | |
1236 | break; | |
1237 | ||
1238 | f->m.rptr += tmp_len; | |
1239 | ||
1240 | tmp_len = f->m.rptr - f->m.memsz; | |
1241 | if (unlikely(tmp_len >= 0)) { | |
1242 | f->m.rptr = tmp_len; | |
1243 | if (tmp_len > 0) { | |
1244 | DBG("wrapped desc rptr=%d tmp_len=%d\n", | |
1245 | f->m.rptr, tmp_len); | |
1246 | memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | if (unlikely(GET_RXD_ERR(rxd_val1))) { | |
1251 | DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1)); | |
0add79e3 | 1252 | ndev->stats.rx_errors++; |
1a348ccc AG |
1253 | bdx_recycle_skb(priv, rxdd); |
1254 | continue; | |
1255 | } | |
1256 | ||
1257 | rxf_fifo = &priv->rxf_fifo0; | |
1258 | db = priv->rxdb; | |
1259 | dm = bdx_rxdb_addr_elem(db, rxdd->va_lo); | |
1260 | skb = dm->skb; | |
1261 | ||
1262 | if (len < BDX_COPYBREAK && | |
dae2e9f4 | 1263 | (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) { |
1a348ccc AG |
1264 | skb_reserve(skb2, NET_IP_ALIGN); |
1265 | /*skb_put(skb2, len); */ | |
1266 | pci_dma_sync_single_for_cpu(priv->pdev, | |
1267 | dm->dma, rxf_fifo->m.pktsz, | |
1268 | PCI_DMA_FROMDEVICE); | |
1269 | memcpy(skb2->data, skb->data, len); | |
1270 | bdx_recycle_skb(priv, rxdd); | |
1271 | skb = skb2; | |
1272 | } else { | |
1273 | pci_unmap_single(priv->pdev, | |
1274 | dm->dma, rxf_fifo->m.pktsz, | |
1275 | PCI_DMA_FROMDEVICE); | |
1276 | bdx_rxdb_free_elem(db, rxdd->va_lo); | |
1277 | } | |
1278 | ||
0add79e3 | 1279 | ndev->stats.rx_bytes += len; |
1a348ccc AG |
1280 | |
1281 | skb_put(skb, len); | |
0add79e3 | 1282 | skb->protocol = eth_type_trans(skb, ndev); |
1a348ccc AG |
1283 | |
1284 | /* Non-IP packets aren't checksum-offloaded */ | |
1285 | if (GET_RXD_PKT_ID(rxd_val1) == 0) | |
bc8acf2c ED |
1286 | skb_checksum_none_assert(skb); |
1287 | else | |
1288 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1a348ccc AG |
1289 | |
1290 | NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb); | |
1291 | ||
1292 | if (++done >= max_done) | |
1293 | break; | |
1294 | } | |
1295 | ||
0add79e3 | 1296 | ndev->stats.rx_packets += done; |
1a348ccc AG |
1297 | |
1298 | /* FIXME: do smth to minimize pci accesses */ | |
1299 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); | |
1300 | ||
1301 | bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0); | |
1302 | ||
1303 | RET(done); | |
1304 | } | |
1305 | ||
1306 | /************************************************************************* | |
1307 | * Debug / Temprorary Code * | |
1308 | *************************************************************************/ | |
1309 | static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len, | |
1310 | u16 rxd_vlan) | |
1311 | { | |
865a21a5 | 1312 | DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n", |
1a348ccc AG |
1313 | GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1), |
1314 | GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1), | |
1315 | GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1), | |
1316 | GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan), | |
1317 | GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo, | |
1318 | rxdd->va_hi); | |
1319 | } | |
1320 | ||
1321 | static void print_rxfd(struct rxf_desc *rxfd) | |
1322 | { | |
fd9071ec | 1323 | DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n" |
1a348ccc AG |
1324 | "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n", |
1325 | rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len); | |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * TX HW/SW interaction overview | |
1330 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
b595076a | 1331 | * There are 2 types of TX communication channels between driver and NIC. |
1a348ccc AG |
1332 | * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets |
1333 | * 2) TX Data Fifo - TXD - holds descriptors of full buffers. | |
1334 | * | |
1335 | * Currently NIC supports TSO, checksuming and gather DMA | |
1336 | * UFO and IP fragmentation is on the way | |
1337 | * | |
1338 | * RX SW Data Structures | |
1339 | * ~~~~~~~~~~~~~~~~~~~~~ | |
1340 | * txdb - used to keep track of all skbs owned by SW and their dma addresses. | |
1341 | * For TX case, ownership lasts from geting packet via hard_xmit and until HW | |
1342 | * acknowledges sent by TXF descriptors. | |
1343 | * Implemented as cyclic buffer. | |
1344 | * fifo - keeps info about fifo's size and location, relevant HW registers, | |
1345 | * usage and skb db. Each RXD and RXF Fifo has its own fifo structure. | |
1346 | * Implemented as simple struct. | |
1347 | * | |
1348 | * TX SW Execution Flow | |
1349 | * ~~~~~~~~~~~~~~~~~~~~ | |
1350 | * OS calls driver's hard_xmit method with packet to sent. | |
1351 | * Driver creates DMA mappings, builds TXD descriptors and kicks HW | |
1352 | * by updating TXD WPTR. | |
1353 | * When packet is sent, HW write us TXF descriptor and SW frees original skb. | |
1354 | * To prevent TXD fifo overflow without reading HW registers every time, | |
1355 | * SW deploys "tx level" technique. | |
1356 | * Upon strart up, tx level is initialized to TXD fifo length. | |
1357 | * For every sent packet, SW gets its TXD descriptor sizei | |
1358 | * (from precalculated array) and substructs it from tx level. | |
1359 | * The size is also stored in txdb. When TXF ack arrives, SW fetch size of | |
1360 | * original TXD descriptor from txdb and adds it to tx level. | |
1361 | * When Tx level drops under some predefined treshhold, the driver | |
1362 | * stops the TX queue. When TX level rises above that level, | |
1363 | * the tx queue is enabled again. | |
1364 | * | |
1365 | * This technique avoids eccessive reading of RPTR and WPTR registers. | |
1366 | * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput. | |
1367 | */ | |
1368 | ||
1369 | /************************************************************************* | |
1370 | * Tx DB * | |
1371 | *************************************************************************/ | |
1372 | static inline int bdx_tx_db_size(struct txdb *db) | |
1373 | { | |
1374 | int taken = db->wptr - db->rptr; | |
1375 | if (taken < 0) | |
1376 | taken = db->size + 1 + taken; /* (size + 1) equals memsz */ | |
1377 | ||
1378 | return db->size - taken; | |
1379 | } | |
1380 | ||
49ce9c2c BH |
1381 | /** |
1382 | * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap | |
1383 | * @db: tx data base | |
1384 | * @pptr: read or write pointer | |
1a348ccc AG |
1385 | */ |
1386 | static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr) | |
1387 | { | |
1388 | BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */ | |
1389 | ||
1390 | BDX_ASSERT(*pptr != db->rptr && /* expect either read */ | |
1391 | *pptr != db->wptr); /* or write pointer */ | |
1392 | ||
1393 | BDX_ASSERT(*pptr < db->start || /* pointer has to be */ | |
1394 | *pptr >= db->end); /* in range */ | |
1395 | ||
1396 | ++*pptr; | |
1397 | if (unlikely(*pptr == db->end)) | |
1398 | *pptr = db->start; | |
1399 | } | |
1400 | ||
49ce9c2c BH |
1401 | /** |
1402 | * bdx_tx_db_inc_rptr - increment read pointer | |
1403 | * @db: tx data base | |
1a348ccc AG |
1404 | */ |
1405 | static inline void bdx_tx_db_inc_rptr(struct txdb *db) | |
1406 | { | |
1407 | BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ | |
1408 | __bdx_tx_db_ptr_next(db, &db->rptr); | |
1409 | } | |
1410 | ||
49ce9c2c BH |
1411 | /** |
1412 | * bdx_tx_db_inc_wptr - increment write pointer | |
1413 | * @db: tx data base | |
1a348ccc AG |
1414 | */ |
1415 | static inline void bdx_tx_db_inc_wptr(struct txdb *db) | |
1416 | { | |
1417 | __bdx_tx_db_ptr_next(db, &db->wptr); | |
1418 | BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as | |
1419 | a result of write */ | |
1420 | } | |
1421 | ||
49ce9c2c BH |
1422 | /** |
1423 | * bdx_tx_db_init - creates and initializes tx db | |
1424 | * @d: tx data base | |
1425 | * @sz_type: size of tx fifo | |
1426 | * | |
1a348ccc AG |
1427 | * Returns 0 on success, error code otherwise |
1428 | */ | |
1429 | static int bdx_tx_db_init(struct txdb *d, int sz_type) | |
1430 | { | |
1431 | int memsz = FIFO_SIZE * (1 << (sz_type + 1)); | |
1432 | ||
1433 | d->start = vmalloc(memsz); | |
1434 | if (!d->start) | |
1435 | return -ENOMEM; | |
1436 | ||
1437 | /* | |
1438 | * In order to differentiate between db is empty and db is full | |
1439 | * states at least one element should always be empty in order to | |
1440 | * avoid rptr == wptr which means db is empty | |
1441 | */ | |
1442 | d->size = memsz / sizeof(struct tx_map) - 1; | |
1443 | d->end = d->start + d->size + 1; /* just after last element */ | |
1444 | ||
1445 | /* all dbs are created equally empty */ | |
1446 | d->rptr = d->start; | |
1447 | d->wptr = d->start; | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
49ce9c2c BH |
1452 | /** |
1453 | * bdx_tx_db_close - closes tx db and frees all memory | |
1454 | * @d: tx data base | |
1a348ccc AG |
1455 | */ |
1456 | static void bdx_tx_db_close(struct txdb *d) | |
1457 | { | |
1458 | BDX_ASSERT(d == NULL); | |
1459 | ||
c0feed87 F |
1460 | vfree(d->start); |
1461 | d->start = NULL; | |
1a348ccc AG |
1462 | } |
1463 | ||
1464 | /************************************************************************* | |
1465 | * Tx Engine * | |
1466 | *************************************************************************/ | |
1467 | ||
1468 | /* sizes of tx desc (including padding if needed) as function | |
1469 | * of skb's frag number */ | |
1470 | static struct { | |
1471 | u16 bytes; | |
1472 | u16 qwords; /* qword = 64 bit */ | |
1473 | } txd_sizes[MAX_SKB_FRAGS + 1]; | |
1474 | ||
49ce9c2c BH |
1475 | /** |
1476 | * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks | |
1477 | * @priv: NIC private structure | |
1478 | * @skb: socket buffer to map | |
1479 | * @txdd: TX descriptor to use | |
1a348ccc AG |
1480 | * |
1481 | * It makes dma mappings for skb's data blocks and writes them to PBL of | |
1482 | * new tx descriptor. It also stores them in the tx db, so they could be | |
1483 | * unmaped after data was sent. It is reponsibility of a caller to make | |
1484 | * sure that there is enough space in the tx db. Last element holds pointer | |
1485 | * to skb itself and marked with zero length | |
1486 | */ | |
1487 | static inline void | |
1488 | bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb, | |
1489 | struct txd_desc *txdd) | |
1490 | { | |
1491 | struct txdb *db = &priv->txdb; | |
1492 | struct pbl *pbl = &txdd->pbl[0]; | |
1493 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1494 | int i; | |
1495 | ||
e743d313 | 1496 | db->wptr->len = skb_headlen(skb); |
1a348ccc AG |
1497 | db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, |
1498 | db->wptr->len, PCI_DMA_TODEVICE); | |
1499 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); | |
1500 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); | |
1501 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); | |
1502 | DBG("=== pbl len: 0x%x ================\n", pbl->len); | |
1503 | DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo); | |
1504 | DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi); | |
1505 | bdx_tx_db_inc_wptr(db); | |
1506 | ||
1507 | for (i = 0; i < nr_frags; i++) { | |
9e903e08 | 1508 | const struct skb_frag_struct *frag; |
1a348ccc AG |
1509 | |
1510 | frag = &skb_shinfo(skb)->frags[i]; | |
9e903e08 | 1511 | db->wptr->len = skb_frag_size(frag); |
e4811086 | 1512 | db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag, |
9e903e08 | 1513 | 0, skb_frag_size(frag), |
5d6bcdfe | 1514 | DMA_TO_DEVICE); |
1a348ccc AG |
1515 | |
1516 | pbl++; | |
1517 | pbl->len = CPU_CHIP_SWAP32(db->wptr->len); | |
1518 | pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); | |
1519 | pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); | |
1520 | bdx_tx_db_inc_wptr(db); | |
1521 | } | |
1522 | ||
1523 | /* add skb clean up info. */ | |
1524 | db->wptr->len = -txd_sizes[nr_frags].bytes; | |
1525 | db->wptr->addr.skb = skb; | |
1526 | bdx_tx_db_inc_wptr(db); | |
1527 | } | |
1528 | ||
1529 | /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags | |
1530 | * number of frags is used as index to fetch correct descriptors size, | |
1531 | * instead of calculating it each time */ | |
1532 | static void __init init_txd_sizes(void) | |
1533 | { | |
1534 | int i, lwords; | |
1535 | ||
1536 | /* 7 - is number of lwords in txd with one phys buffer | |
1537 | * 3 - is number of lwords used for every additional phys buffer */ | |
1538 | for (i = 0; i < MAX_SKB_FRAGS + 1; i++) { | |
1539 | lwords = 7 + (i * 3); | |
1540 | if (lwords & 1) | |
1541 | lwords++; /* pad it with 1 lword */ | |
1542 | txd_sizes[i].qwords = lwords >> 1; | |
1543 | txd_sizes[i].bytes = lwords << 2; | |
1544 | } | |
1545 | } | |
1546 | ||
1547 | /* bdx_tx_init - initialize all Tx related stuff. | |
1548 | * Namely, TXD and TXF fifos, database etc */ | |
1549 | static int bdx_tx_init(struct bdx_priv *priv) | |
1550 | { | |
1551 | if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size, | |
1552 | regTXD_CFG0_0, | |
1553 | regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0)) | |
1554 | goto err_mem; | |
1555 | if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size, | |
1556 | regTXF_CFG0_0, | |
1557 | regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0)) | |
1558 | goto err_mem; | |
1559 | ||
1560 | /* The TX db has to keep mappings for all packets sent (on TxD) | |
1561 | * and not yet reclaimed (on TxF) */ | |
1562 | if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size))) | |
1563 | goto err_mem; | |
1564 | ||
1565 | priv->tx_level = BDX_MAX_TX_LEVEL; | |
1566 | #ifdef BDX_DELAY_WPTR | |
1567 | priv->tx_update_mark = priv->tx_level - 1024; | |
1568 | #endif | |
1569 | return 0; | |
1570 | ||
1571 | err_mem: | |
865a21a5 | 1572 | netdev_err(priv->ndev, "Tx init failed\n"); |
1a348ccc AG |
1573 | return -ENOMEM; |
1574 | } | |
1575 | ||
49ce9c2c | 1576 | /** |
25985edc | 1577 | * bdx_tx_space - calculates available space in TX fifo |
49ce9c2c BH |
1578 | * @priv: NIC private structure |
1579 | * | |
25985edc | 1580 | * Returns available space in TX fifo in bytes |
1a348ccc AG |
1581 | */ |
1582 | static inline int bdx_tx_space(struct bdx_priv *priv) | |
1583 | { | |
1584 | struct txd_fifo *f = &priv->txd_fifo0; | |
1585 | int fsize; | |
1586 | ||
1587 | f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR; | |
1588 | fsize = f->m.rptr - f->m.wptr; | |
1589 | if (fsize <= 0) | |
1590 | fsize = f->m.memsz + fsize; | |
249658d5 | 1591 | return fsize; |
1a348ccc AG |
1592 | } |
1593 | ||
49ce9c2c BH |
1594 | /** |
1595 | * bdx_tx_transmit - send packet to NIC | |
1596 | * @skb: packet to send | |
1597 | * @ndev: network device assigned to NIC | |
1a348ccc AG |
1598 | * Return codes: |
1599 | * o NETDEV_TX_OK everything ok. | |
1600 | * o NETDEV_TX_BUSY Cannot transmit packet, try later | |
1601 | * Usually a bug, means queue start/stop flow control is broken in | |
1602 | * the driver. Note: the driver must NOT put the skb in its DMA ring. | |
1a348ccc | 1603 | */ |
61357325 SH |
1604 | static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb, |
1605 | struct net_device *ndev) | |
1a348ccc | 1606 | { |
8f15ea42 | 1607 | struct bdx_priv *priv = netdev_priv(ndev); |
1a348ccc AG |
1608 | struct txd_fifo *f = &priv->txd_fifo0; |
1609 | int txd_checksum = 7; /* full checksum */ | |
1610 | int txd_lgsnd = 0; | |
1611 | int txd_vlan_id = 0; | |
1612 | int txd_vtag = 0; | |
1613 | int txd_mss = 0; | |
1614 | ||
1615 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1616 | struct txd_desc *txdd; | |
1617 | int len; | |
1618 | unsigned long flags; | |
1619 | ||
1620 | ENTER; | |
1621 | local_irq_save(flags); | |
a6086a89 | 1622 | spin_lock(&priv->tx_lock); |
1a348ccc AG |
1623 | |
1624 | /* build tx descriptor */ | |
1625 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ | |
1626 | txdd = (struct txd_desc *)(f->m.va + f->m.wptr); | |
1627 | if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) | |
1628 | txd_checksum = 0; | |
1629 | ||
1630 | if (skb_shinfo(skb)->gso_size) { | |
1631 | txd_mss = skb_shinfo(skb)->gso_size; | |
1632 | txd_lgsnd = 1; | |
1633 | DBG("skb %p skb len %d gso size = %d\n", skb, skb->len, | |
1634 | txd_mss); | |
1635 | } | |
1636 | ||
df8a39de | 1637 | if (skb_vlan_tag_present(skb)) { |
1a348ccc | 1638 | /*Cut VLAN ID to 12 bits */ |
df8a39de | 1639 | txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12); |
1a348ccc AG |
1640 | txd_vtag = 1; |
1641 | } | |
1642 | ||
1643 | txdd->length = CPU_CHIP_SWAP16(skb->len); | |
1644 | txdd->mss = CPU_CHIP_SWAP16(txd_mss); | |
1645 | txdd->txd_val1 = | |
1646 | CPU_CHIP_SWAP32(TXD_W1_VAL | |
1647 | (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag, | |
1648 | txd_lgsnd, txd_vlan_id)); | |
1649 | DBG("=== TxD desc =====================\n"); | |
1650 | DBG("=== w1: 0x%x ================\n", txdd->txd_val1); | |
1651 | DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length); | |
1652 | ||
1653 | bdx_tx_map_skb(priv, skb, txdd); | |
1654 | ||
1655 | /* increment TXD write pointer. In case of | |
1656 | fifo wrapping copy reminder of the descriptor | |
1657 | to the beginning */ | |
1658 | f->m.wptr += txd_sizes[nr_frags].bytes; | |
1659 | len = f->m.wptr - f->m.memsz; | |
1660 | if (unlikely(len >= 0)) { | |
1661 | f->m.wptr = len; | |
1662 | if (len > 0) { | |
1663 | BDX_ASSERT(len > f->m.memsz); | |
1664 | memcpy(f->m.va, f->m.va + f->m.memsz, len); | |
1665 | } | |
1666 | } | |
1667 | BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ | |
1668 | ||
1669 | priv->tx_level -= txd_sizes[nr_frags].bytes; | |
1670 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); | |
1671 | #ifdef BDX_DELAY_WPTR | |
1672 | if (priv->tx_level > priv->tx_update_mark) { | |
1673 | /* Force memory writes to complete before letting h/w | |
1674 | know there are new descriptors to fetch. | |
1675 | (might be needed on platforms like IA64) | |
1676 | wmb(); */ | |
1677 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1678 | } else { | |
1679 | if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) { | |
1680 | priv->tx_noupd = 0; | |
1681 | WRITE_REG(priv, f->m.reg_WPTR, | |
1682 | f->m.wptr & TXF_WPTR_WR_PTR); | |
1683 | } | |
1684 | } | |
1685 | #else | |
1686 | /* Force memory writes to complete before letting h/w | |
1687 | know there are new descriptors to fetch. | |
1688 | (might be needed on platforms like IA64) | |
1689 | wmb(); */ | |
1690 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1691 | ||
1692 | #endif | |
28679751 | 1693 | #ifdef BDX_LLTX |
860e9538 | 1694 | netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */ |
28679751 | 1695 | #endif |
0add79e3 TK |
1696 | ndev->stats.tx_packets++; |
1697 | ndev->stats.tx_bytes += skb->len; | |
1a348ccc AG |
1698 | |
1699 | if (priv->tx_level < BDX_MIN_TX_LEVEL) { | |
1700 | DBG("%s: %s: TX Q STOP level %d\n", | |
1701 | BDX_DRV_NAME, ndev->name, priv->tx_level); | |
1702 | netif_stop_queue(ndev); | |
1703 | } | |
1704 | ||
1705 | spin_unlock_irqrestore(&priv->tx_lock, flags); | |
1706 | return NETDEV_TX_OK; | |
1707 | } | |
1708 | ||
49ce9c2c BH |
1709 | /** |
1710 | * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ. | |
1711 | * @priv: bdx adapter | |
1712 | * | |
1a348ccc AG |
1713 | * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS |
1714 | * that those packets were sent | |
1715 | */ | |
1716 | static void bdx_tx_cleanup(struct bdx_priv *priv) | |
1717 | { | |
1718 | struct txf_fifo *f = &priv->txf_fifo0; | |
1719 | struct txdb *db = &priv->txdb; | |
1720 | int tx_level = 0; | |
1721 | ||
1722 | ENTER; | |
1723 | f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; | |
1724 | BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */ | |
1725 | ||
1726 | while (f->m.wptr != f->m.rptr) { | |
1727 | f->m.rptr += BDX_TXF_DESC_SZ; | |
1728 | f->m.rptr &= f->m.size_mask; | |
1729 | ||
1730 | /* unmap all the fragments */ | |
1731 | /* first has to come tx_maps containing dma */ | |
1732 | BDX_ASSERT(db->rptr->len == 0); | |
1733 | do { | |
1734 | BDX_ASSERT(db->rptr->addr.dma == 0); | |
1735 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, | |
1736 | db->rptr->len, PCI_DMA_TODEVICE); | |
1737 | bdx_tx_db_inc_rptr(db); | |
1738 | } while (db->rptr->len > 0); | |
1739 | tx_level -= db->rptr->len; /* '-' koz len is negative */ | |
1740 | ||
1741 | /* now should come skb pointer - free it */ | |
1a348ccc AG |
1742 | dev_kfree_skb_irq(db->rptr->addr.skb); |
1743 | bdx_tx_db_inc_rptr(db); | |
1744 | } | |
1745 | ||
1746 | /* let h/w know which TXF descriptors were cleaned */ | |
1747 | BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); | |
1748 | WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); | |
1749 | ||
1750 | /* We reclaimed resources, so in case the Q is stopped by xmit callback, | |
88bfe6ea | 1751 | * we resume the transmission and use tx_lock to synchronize with xmit.*/ |
1a348ccc AG |
1752 | spin_lock(&priv->tx_lock); |
1753 | priv->tx_level += tx_level; | |
1754 | BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL); | |
1755 | #ifdef BDX_DELAY_WPTR | |
1756 | if (priv->tx_noupd) { | |
1757 | priv->tx_noupd = 0; | |
1758 | WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR, | |
1759 | priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); | |
1760 | } | |
1761 | #endif | |
1762 | ||
8e95a202 JP |
1763 | if (unlikely(netif_queue_stopped(priv->ndev) && |
1764 | netif_carrier_ok(priv->ndev) && | |
1765 | (priv->tx_level >= BDX_MIN_TX_LEVEL))) { | |
1a348ccc AG |
1766 | DBG("%s: %s: TX Q WAKE level %d\n", |
1767 | BDX_DRV_NAME, priv->ndev->name, priv->tx_level); | |
1768 | netif_wake_queue(priv->ndev); | |
1769 | } | |
1770 | spin_unlock(&priv->tx_lock); | |
1771 | } | |
1772 | ||
49ce9c2c BH |
1773 | /** |
1774 | * bdx_tx_free_skbs - frees all skbs from TXD fifo. | |
1a348ccc AG |
1775 | * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod |
1776 | */ | |
1777 | static void bdx_tx_free_skbs(struct bdx_priv *priv) | |
1778 | { | |
1779 | struct txdb *db = &priv->txdb; | |
1780 | ||
1781 | ENTER; | |
1782 | while (db->rptr != db->wptr) { | |
1783 | if (likely(db->rptr->len)) | |
1784 | pci_unmap_page(priv->pdev, db->rptr->addr.dma, | |
1785 | db->rptr->len, PCI_DMA_TODEVICE); | |
1786 | else | |
1787 | dev_kfree_skb(db->rptr->addr.skb); | |
1788 | bdx_tx_db_inc_rptr(db); | |
1789 | } | |
1790 | RET(); | |
1791 | } | |
1792 | ||
1793 | /* bdx_tx_free - frees all Tx resources */ | |
1794 | static void bdx_tx_free(struct bdx_priv *priv) | |
1795 | { | |
1796 | ENTER; | |
1797 | bdx_tx_free_skbs(priv); | |
1798 | bdx_fifo_free(priv, &priv->txd_fifo0.m); | |
1799 | bdx_fifo_free(priv, &priv->txf_fifo0.m); | |
1800 | bdx_tx_db_close(&priv->txdb); | |
1801 | } | |
1802 | ||
49ce9c2c BH |
1803 | /** |
1804 | * bdx_tx_push_desc - push descriptor to TxD fifo | |
1805 | * @priv: NIC private structure | |
1806 | * @data: desc's data | |
1807 | * @size: desc's size | |
1a348ccc AG |
1808 | * |
1809 | * Pushes desc to TxD fifo and overlaps it if needed. | |
1810 | * NOTE: this func does not check for available space. this is responsibility | |
025dfdaf | 1811 | * of the caller. Neither does it check that data size is smaller than |
1a348ccc AG |
1812 | * fifo size. |
1813 | */ | |
1814 | static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size) | |
1815 | { | |
1816 | struct txd_fifo *f = &priv->txd_fifo0; | |
1817 | int i = f->m.memsz - f->m.wptr; | |
1818 | ||
1819 | if (size == 0) | |
1820 | return; | |
1821 | ||
1822 | if (i > size) { | |
1823 | memcpy(f->m.va + f->m.wptr, data, size); | |
1824 | f->m.wptr += size; | |
1825 | } else { | |
1826 | memcpy(f->m.va + f->m.wptr, data, i); | |
1827 | f->m.wptr = size - i; | |
1828 | memcpy(f->m.va, data + i, f->m.wptr); | |
1829 | } | |
1830 | WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); | |
1831 | } | |
1832 | ||
49ce9c2c BH |
1833 | /** |
1834 | * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way | |
1835 | * @priv: NIC private structure | |
1836 | * @data: desc's data | |
1837 | * @size: desc's size | |
1a348ccc | 1838 | * |
3ad2f3fb | 1839 | * NOTE: this func does check for available space and, if necessary, waits for |
1a348ccc AG |
1840 | * NIC to read existing data before writing new one. |
1841 | */ | |
1842 | static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size) | |
1843 | { | |
1844 | int timer = 0; | |
1845 | ENTER; | |
1846 | ||
1847 | while (size > 0) { | |
1848 | /* we substruct 8 because when fifo is full rptr == wptr | |
1849 | which also means that fifo is empty, we can understand | |
1850 | the difference, but could hw do the same ??? :) */ | |
1851 | int avail = bdx_tx_space(priv) - 8; | |
1852 | if (avail <= 0) { | |
1853 | if (timer++ > 300) { /* prevent endless loop */ | |
1854 | DBG("timeout while writing desc to TxD fifo\n"); | |
1855 | break; | |
1856 | } | |
1857 | udelay(50); /* give hw a chance to clean fifo */ | |
1858 | continue; | |
1859 | } | |
df7641af | 1860 | avail = min(avail, size); |
1a348ccc AG |
1861 | DBG("about to push %d bytes starting %p size %d\n", avail, |
1862 | data, size); | |
1863 | bdx_tx_push_desc(priv, data, avail); | |
1864 | size -= avail; | |
1865 | data += avail; | |
1866 | } | |
1867 | RET(); | |
1868 | } | |
1869 | ||
2f30b1f6 | 1870 | static const struct net_device_ops bdx_netdev_ops = { |
312cd513 | 1871 | .ndo_open = bdx_open, |
2f30b1f6 SH |
1872 | .ndo_stop = bdx_close, |
1873 | .ndo_start_xmit = bdx_tx_transmit, | |
1874 | .ndo_validate_addr = eth_validate_addr, | |
1875 | .ndo_do_ioctl = bdx_ioctl, | |
afc4b13d | 1876 | .ndo_set_rx_mode = bdx_setmulti, |
2f30b1f6 SH |
1877 | .ndo_change_mtu = bdx_change_mtu, |
1878 | .ndo_set_mac_address = bdx_set_mac, | |
2f30b1f6 SH |
1879 | .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid, |
1880 | .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid, | |
1881 | }; | |
1882 | ||
1a348ccc AG |
1883 | /** |
1884 | * bdx_probe - Device Initialization Routine | |
1885 | * @pdev: PCI device information struct | |
1886 | * @ent: entry in bdx_pci_tbl | |
1887 | * | |
1888 | * Returns 0 on success, negative on failure | |
1889 | * | |
1890 | * bdx_probe initializes an adapter identified by a pci_dev structure. | |
1891 | * The OS initialization, configuring of the adapter private structure, | |
1892 | * and a hardware reset occur. | |
1893 | * | |
1894 | * functions and their order used as explained in | |
1895 | * /usr/src/linux/Documentation/DMA-{API,mapping}.txt | |
1896 | * | |
1897 | */ | |
1898 | ||
1899 | /* TBD: netif_msg should be checked and implemented. I disable it for now */ | |
17abe3e4 | 1900 | static int |
1a348ccc AG |
1901 | bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1902 | { | |
1903 | struct net_device *ndev; | |
1904 | struct bdx_priv *priv; | |
1905 | int err, pci_using_dac, port; | |
1906 | unsigned long pciaddr; | |
1907 | u32 regionSize; | |
1908 | struct pci_nic *nic; | |
1909 | ||
1910 | ENTER; | |
1911 | ||
1912 | nic = vmalloc(sizeof(*nic)); | |
1913 | if (!nic) | |
1914 | RET(-ENOMEM); | |
1915 | ||
1916 | /************** pci *****************/ | |
cb001a1f JP |
1917 | err = pci_enable_device(pdev); |
1918 | if (err) /* it triggers interrupt, dunno why. */ | |
1919 | goto err_pci; /* it's not a problem though */ | |
1a348ccc | 1920 | |
6a35528a YH |
1921 | if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) && |
1922 | !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) { | |
1a348ccc AG |
1923 | pci_using_dac = 1; |
1924 | } else { | |
284901a9 YH |
1925 | if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) || |
1926 | (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) { | |
865a21a5 | 1927 | pr_err("No usable DMA configuration, aborting\n"); |
1a348ccc AG |
1928 | goto err_dma; |
1929 | } | |
1930 | pci_using_dac = 0; | |
1931 | } | |
1932 | ||
cb001a1f JP |
1933 | err = pci_request_regions(pdev, BDX_DRV_NAME); |
1934 | if (err) | |
1a348ccc AG |
1935 | goto err_dma; |
1936 | ||
1937 | pci_set_master(pdev); | |
1938 | ||
1939 | pciaddr = pci_resource_start(pdev, 0); | |
1940 | if (!pciaddr) { | |
1941 | err = -EIO; | |
865a21a5 | 1942 | pr_err("no MMIO resource\n"); |
1a348ccc AG |
1943 | goto err_out_res; |
1944 | } | |
cb001a1f JP |
1945 | regionSize = pci_resource_len(pdev, 0); |
1946 | if (regionSize < BDX_REGS_SIZE) { | |
1a348ccc | 1947 | err = -EIO; |
865a21a5 | 1948 | pr_err("MMIO resource (%x) too small\n", regionSize); |
1a348ccc AG |
1949 | goto err_out_res; |
1950 | } | |
1951 | ||
1952 | nic->regs = ioremap(pciaddr, regionSize); | |
1953 | if (!nic->regs) { | |
1954 | err = -EIO; | |
865a21a5 | 1955 | pr_err("ioremap failed\n"); |
1a348ccc AG |
1956 | goto err_out_res; |
1957 | } | |
1958 | ||
1959 | if (pdev->irq < 2) { | |
1960 | err = -EIO; | |
865a21a5 | 1961 | pr_err("invalid irq (%d)\n", pdev->irq); |
1a348ccc AG |
1962 | goto err_out_iomap; |
1963 | } | |
1964 | pci_set_drvdata(pdev, nic); | |
1965 | ||
1966 | if (pdev->device == 0x3014) | |
1967 | nic->port_num = 2; | |
1968 | else | |
1969 | nic->port_num = 1; | |
1970 | ||
1971 | print_hw_id(pdev); | |
1972 | ||
1973 | bdx_hw_reset_direct(nic->regs); | |
1974 | ||
1975 | nic->irq_type = IRQ_INTX; | |
1976 | #ifdef BDX_MSI | |
1977 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) { | |
cb001a1f JP |
1978 | err = pci_enable_msi(pdev); |
1979 | if (err) | |
d524d84b | 1980 | pr_err("Can't enable msi. error is %d\n", err); |
1a348ccc AG |
1981 | else |
1982 | nic->irq_type = IRQ_MSI; | |
1983 | } else | |
1984 | DBG("HW does not support MSI\n"); | |
1985 | #endif | |
1986 | ||
1987 | /************** netdev **************/ | |
1988 | for (port = 0; port < nic->port_num; port++) { | |
cb001a1f JP |
1989 | ndev = alloc_etherdev(sizeof(struct bdx_priv)); |
1990 | if (!ndev) { | |
1a348ccc | 1991 | err = -ENOMEM; |
1a348ccc AG |
1992 | goto err_out_iomap; |
1993 | } | |
1994 | ||
2f30b1f6 | 1995 | ndev->netdev_ops = &bdx_netdev_ops; |
1a348ccc | 1996 | ndev->tx_queue_len = BDX_NDEV_TXQ_LEN; |
1a348ccc | 1997 | |
c061b18d | 1998 | bdx_set_ethtool_ops(ndev); /* ethtool interface */ |
1a348ccc AG |
1999 | |
2000 | /* these fields are used for info purposes only | |
2001 | * so we can have them same for all ports of the board */ | |
2002 | ndev->if_port = port; | |
1a348ccc | 2003 | ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO |
f646968f PM |
2004 | | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
2005 | NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM | |
1a348ccc | 2006 | ; |
eea3250b | 2007 | ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
f646968f | 2008 | NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX; |
1a348ccc AG |
2009 | |
2010 | if (pci_using_dac) | |
2011 | ndev->features |= NETIF_F_HIGHDMA; | |
2012 | ||
2013 | /************** priv ****************/ | |
8f15ea42 | 2014 | priv = nic->priv[port] = netdev_priv(ndev); |
1a348ccc | 2015 | |
1a348ccc AG |
2016 | priv->pBdxRegs = nic->regs + port * 0x8000; |
2017 | priv->port = port; | |
2018 | priv->pdev = pdev; | |
2019 | priv->ndev = ndev; | |
2020 | priv->nic = nic; | |
2021 | priv->msg_enable = BDX_DEF_MSG_ENABLE; | |
2022 | ||
2023 | netif_napi_add(ndev, &priv->napi, bdx_poll, 64); | |
2024 | ||
2025 | if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) { | |
2026 | DBG("HW statistics not supported\n"); | |
2027 | priv->stats_flag = 0; | |
2028 | } else { | |
2029 | priv->stats_flag = 1; | |
2030 | } | |
2031 | ||
2032 | /* Initialize fifo sizes. */ | |
2033 | priv->txd_size = 2; | |
2034 | priv->txf_size = 2; | |
2035 | priv->rxd_size = 2; | |
2036 | priv->rxf_size = 3; | |
2037 | ||
2038 | /* Initialize the initial coalescing registers. */ | |
2039 | priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12); | |
2040 | priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12); | |
2041 | ||
2042 | /* ndev->xmit_lock spinlock is not used. | |
2043 | * Private priv->tx_lock is used for synchronization | |
2044 | * between transmit and TX irq cleanup. In addition | |
2045 | * set multicast list callback has to use priv->tx_lock. | |
2046 | */ | |
2047 | #ifdef BDX_LLTX | |
2048 | ndev->features |= NETIF_F_LLTX; | |
2049 | #endif | |
44770e11 JW |
2050 | /* MTU range: 60 - 16384 */ |
2051 | ndev->min_mtu = ETH_ZLEN; | |
2052 | ndev->max_mtu = BDX_MAX_MTU; | |
2053 | ||
1a348ccc AG |
2054 | spin_lock_init(&priv->tx_lock); |
2055 | ||
2056 | /*bdx_hw_reset(priv); */ | |
2057 | if (bdx_read_mac(priv)) { | |
865a21a5 | 2058 | pr_err("load MAC address failed\n"); |
1a348ccc AG |
2059 | goto err_out_iomap; |
2060 | } | |
2061 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
cb001a1f JP |
2062 | err = register_netdev(ndev); |
2063 | if (err) { | |
865a21a5 | 2064 | pr_err("register_netdev failed\n"); |
1a348ccc AG |
2065 | goto err_out_free; |
2066 | } | |
2067 | netif_carrier_off(ndev); | |
2068 | netif_stop_queue(ndev); | |
2069 | ||
2070 | print_eth_id(ndev); | |
2071 | } | |
2072 | RET(0); | |
2073 | ||
2074 | err_out_free: | |
2075 | free_netdev(ndev); | |
2076 | err_out_iomap: | |
2077 | iounmap(nic->regs); | |
2078 | err_out_res: | |
2079 | pci_release_regions(pdev); | |
2080 | err_dma: | |
2081 | pci_disable_device(pdev); | |
bc2618f7 | 2082 | err_pci: |
1a348ccc AG |
2083 | vfree(nic); |
2084 | ||
2085 | RET(err); | |
2086 | } | |
2087 | ||
2088 | /****************** Ethtool interface *********************/ | |
1a348ccc AG |
2089 | /* get strings for statistics counters */ |
2090 | static const char | |
2091 | bdx_stat_names[][ETH_GSTRING_LEN] = { | |
2092 | "InUCast", /* 0x7200 */ | |
2093 | "InMCast", /* 0x7210 */ | |
2094 | "InBCast", /* 0x7220 */ | |
2095 | "InPkts", /* 0x7230 */ | |
2096 | "InErrors", /* 0x7240 */ | |
2097 | "InDropped", /* 0x7250 */ | |
2098 | "FrameTooLong", /* 0x7260 */ | |
2099 | "FrameSequenceErrors", /* 0x7270 */ | |
2100 | "InVLAN", /* 0x7280 */ | |
2101 | "InDroppedDFE", /* 0x7290 */ | |
2102 | "InDroppedIntFull", /* 0x72A0 */ | |
2103 | "InFrameAlignErrors", /* 0x72B0 */ | |
2104 | ||
2105 | /* 0x72C0-0x72E0 RSRV */ | |
2106 | ||
2107 | "OutUCast", /* 0x72F0 */ | |
2108 | "OutMCast", /* 0x7300 */ | |
2109 | "OutBCast", /* 0x7310 */ | |
2110 | "OutPkts", /* 0x7320 */ | |
2111 | ||
2112 | /* 0x7330-0x7360 RSRV */ | |
2113 | ||
2114 | "OutVLAN", /* 0x7370 */ | |
2115 | "InUCastOctects", /* 0x7380 */ | |
2116 | "OutUCastOctects", /* 0x7390 */ | |
2117 | ||
2118 | /* 0x73A0-0x73B0 RSRV */ | |
2119 | ||
2120 | "InBCastOctects", /* 0x73C0 */ | |
2121 | "OutBCastOctects", /* 0x73D0 */ | |
2122 | "InOctects", /* 0x73E0 */ | |
2123 | "OutOctects", /* 0x73F0 */ | |
2124 | }; | |
2125 | ||
2126 | /* | |
86573f61 | 2127 | * bdx_get_link_ksettings - get device-specific settings |
1a348ccc AG |
2128 | * @netdev |
2129 | * @ecmd | |
2130 | */ | |
86573f61 PR |
2131 | static int bdx_get_link_ksettings(struct net_device *netdev, |
2132 | struct ethtool_link_ksettings *ecmd) | |
2133 | { | |
2134 | ethtool_link_ksettings_zero_link_mode(ecmd, supported); | |
2135 | ethtool_link_ksettings_add_link_mode(ecmd, supported, | |
2136 | 10000baseT_Full); | |
2137 | ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE); | |
2138 | ethtool_link_ksettings_zero_link_mode(ecmd, advertising); | |
2139 | ethtool_link_ksettings_add_link_mode(ecmd, advertising, | |
2140 | 10000baseT_Full); | |
2141 | ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE); | |
2142 | ||
2143 | ecmd->base.speed = SPEED_10000; | |
2144 | ecmd->base.duplex = DUPLEX_FULL; | |
2145 | ecmd->base.port = PORT_FIBRE; | |
2146 | ecmd->base.autoneg = AUTONEG_DISABLE; | |
1a348ccc AG |
2147 | |
2148 | return 0; | |
2149 | } | |
2150 | ||
2151 | /* | |
2152 | * bdx_get_drvinfo - report driver information | |
2153 | * @netdev | |
2154 | * @drvinfo | |
2155 | */ | |
2156 | static void | |
2157 | bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | |
2158 | { | |
8f15ea42 | 2159 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc | 2160 | |
7826d43f JP |
2161 | strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver)); |
2162 | strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version)); | |
2163 | strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | |
2164 | strlcpy(drvinfo->bus_info, pci_name(priv->pdev), | |
1a348ccc | 2165 | sizeof(drvinfo->bus_info)); |
1a348ccc AG |
2166 | } |
2167 | ||
1a348ccc AG |
2168 | /* |
2169 | * bdx_get_coalesce - get interrupt coalescing parameters | |
2170 | * @netdev | |
2171 | * @ecoal | |
2172 | */ | |
2173 | static int | |
2174 | bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) | |
2175 | { | |
2176 | u32 rdintcm; | |
2177 | u32 tdintcm; | |
8f15ea42 | 2178 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc AG |
2179 | |
2180 | rdintcm = priv->rdintcm; | |
2181 | tdintcm = priv->tdintcm; | |
2182 | ||
2183 | /* PCK_TH measures in multiples of FIFO bytes | |
2184 | We translate to packets */ | |
2185 | ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT; | |
2186 | ecoal->rx_max_coalesced_frames = | |
2187 | ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc)); | |
2188 | ||
2189 | ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT; | |
2190 | ecoal->tx_max_coalesced_frames = | |
2191 | ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ); | |
2192 | ||
2193 | /* adaptive parameters ignored */ | |
2194 | return 0; | |
2195 | } | |
2196 | ||
2197 | /* | |
2198 | * bdx_set_coalesce - set interrupt coalescing parameters | |
2199 | * @netdev | |
2200 | * @ecoal | |
2201 | */ | |
2202 | static int | |
2203 | bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal) | |
2204 | { | |
2205 | u32 rdintcm; | |
2206 | u32 tdintcm; | |
8f15ea42 | 2207 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc AG |
2208 | int rx_coal; |
2209 | int tx_coal; | |
2210 | int rx_max_coal; | |
2211 | int tx_max_coal; | |
2212 | ||
2213 | /* Check for valid input */ | |
2214 | rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT; | |
2215 | tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT; | |
2216 | rx_max_coal = ecoal->rx_max_coalesced_frames; | |
2217 | tx_max_coal = ecoal->tx_max_coalesced_frames; | |
2218 | ||
2219 | /* Translate from packets to multiples of FIFO bytes */ | |
2220 | rx_max_coal = | |
2221 | (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1) | |
2222 | / PCK_TH_MULT); | |
2223 | tx_max_coal = | |
2224 | (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1) | |
2225 | / PCK_TH_MULT); | |
2226 | ||
8e95a202 JP |
2227 | if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) || |
2228 | (rx_max_coal > 0xF) || (tx_max_coal > 0xF)) | |
1a348ccc AG |
2229 | return -EINVAL; |
2230 | ||
2231 | rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm), | |
2232 | GET_RXF_TH(priv->rdintcm), rx_max_coal); | |
2233 | tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0, | |
2234 | tx_max_coal); | |
2235 | ||
2236 | priv->rdintcm = rdintcm; | |
2237 | priv->tdintcm = tdintcm; | |
2238 | ||
2239 | WRITE_REG(priv, regRDINTCM0, rdintcm); | |
2240 | WRITE_REG(priv, regTDINTCM0, tdintcm); | |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | /* Convert RX fifo size to number of pending packets */ | |
2246 | static inline int bdx_rx_fifo_size_to_packets(int rx_size) | |
2247 | { | |
249658d5 | 2248 | return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc); |
1a348ccc AG |
2249 | } |
2250 | ||
2251 | /* Convert TX fifo size to number of pending packets */ | |
2252 | static inline int bdx_tx_fifo_size_to_packets(int tx_size) | |
2253 | { | |
249658d5 | 2254 | return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ; |
1a348ccc AG |
2255 | } |
2256 | ||
2257 | /* | |
2258 | * bdx_get_ringparam - report ring sizes | |
2259 | * @netdev | |
2260 | * @ring | |
2261 | */ | |
2262 | static void | |
2263 | bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | |
2264 | { | |
8f15ea42 | 2265 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc AG |
2266 | |
2267 | /*max_pending - the maximum-sized FIFO we allow */ | |
2268 | ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3); | |
2269 | ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3); | |
2270 | ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size); | |
2271 | ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size); | |
2272 | } | |
2273 | ||
2274 | /* | |
2275 | * bdx_set_ringparam - set ring sizes | |
2276 | * @netdev | |
2277 | * @ring | |
2278 | */ | |
2279 | static int | |
2280 | bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | |
2281 | { | |
8f15ea42 | 2282 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc AG |
2283 | int rx_size = 0; |
2284 | int tx_size = 0; | |
2285 | ||
2286 | for (; rx_size < 4; rx_size++) { | |
2287 | if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending) | |
2288 | break; | |
2289 | } | |
2290 | if (rx_size == 4) | |
2291 | rx_size = 3; | |
2292 | ||
2293 | for (; tx_size < 4; tx_size++) { | |
2294 | if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending) | |
2295 | break; | |
2296 | } | |
2297 | if (tx_size == 4) | |
2298 | tx_size = 3; | |
2299 | ||
2300 | /*Is there anything to do? */ | |
8e95a202 JP |
2301 | if ((rx_size == priv->rxf_size) && |
2302 | (tx_size == priv->txd_size)) | |
1a348ccc AG |
2303 | return 0; |
2304 | ||
2305 | priv->rxf_size = rx_size; | |
2306 | if (rx_size > 1) | |
2307 | priv->rxd_size = rx_size - 1; | |
2308 | else | |
2309 | priv->rxd_size = rx_size; | |
2310 | ||
2311 | priv->txf_size = priv->txd_size = tx_size; | |
2312 | ||
2313 | if (netif_running(netdev)) { | |
2314 | bdx_close(netdev); | |
2315 | bdx_open(netdev); | |
2316 | } | |
2317 | return 0; | |
2318 | } | |
2319 | ||
2320 | /* | |
2321 | * bdx_get_strings - return a set of strings that describe the requested objects | |
2322 | * @netdev | |
2323 | * @data | |
2324 | */ | |
2325 | static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data) | |
2326 | { | |
2327 | switch (stringset) { | |
1a348ccc AG |
2328 | case ETH_SS_STATS: |
2329 | memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names)); | |
2330 | break; | |
2331 | } | |
2332 | } | |
2333 | ||
2334 | /* | |
1ddee09f | 2335 | * bdx_get_sset_count - return number of statistics or tests |
1a348ccc AG |
2336 | * @netdev |
2337 | */ | |
1ddee09f | 2338 | static int bdx_get_sset_count(struct net_device *netdev, int stringset) |
1a348ccc | 2339 | { |
8f15ea42 | 2340 | struct bdx_priv *priv = netdev_priv(netdev); |
1ddee09f BH |
2341 | |
2342 | switch (stringset) { | |
2343 | case ETH_SS_STATS: | |
2344 | BDX_ASSERT(ARRAY_SIZE(bdx_stat_names) | |
2345 | != sizeof(struct bdx_stats) / sizeof(u64)); | |
249658d5 | 2346 | return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0; |
1ddee09f | 2347 | } |
249658d5 JP |
2348 | |
2349 | return -EINVAL; | |
1a348ccc AG |
2350 | } |
2351 | ||
2352 | /* | |
2353 | * bdx_get_ethtool_stats - return device's hardware L2 statistics | |
2354 | * @netdev | |
2355 | * @stats | |
2356 | * @data | |
2357 | */ | |
2358 | static void bdx_get_ethtool_stats(struct net_device *netdev, | |
2359 | struct ethtool_stats *stats, u64 *data) | |
2360 | { | |
8f15ea42 | 2361 | struct bdx_priv *priv = netdev_priv(netdev); |
1a348ccc AG |
2362 | |
2363 | if (priv->stats_flag) { | |
2364 | ||
2365 | /* Update stats from HW */ | |
2366 | bdx_update_stats(priv); | |
2367 | ||
2368 | /* Copy data to user buffer */ | |
2369 | memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats)); | |
2370 | } | |
2371 | } | |
2372 | ||
2373 | /* | |
c061b18d | 2374 | * bdx_set_ethtool_ops - ethtool interface implementation |
1a348ccc AG |
2375 | * @netdev |
2376 | */ | |
c061b18d | 2377 | static void bdx_set_ethtool_ops(struct net_device *netdev) |
1a348ccc | 2378 | { |
0fc0b732 | 2379 | static const struct ethtool_ops bdx_ethtool_ops = { |
1a348ccc AG |
2380 | .get_drvinfo = bdx_get_drvinfo, |
2381 | .get_link = ethtool_op_get_link, | |
2382 | .get_coalesce = bdx_get_coalesce, | |
2383 | .set_coalesce = bdx_set_coalesce, | |
2384 | .get_ringparam = bdx_get_ringparam, | |
2385 | .set_ringparam = bdx_set_ringparam, | |
1a348ccc | 2386 | .get_strings = bdx_get_strings, |
1ddee09f | 2387 | .get_sset_count = bdx_get_sset_count, |
1a348ccc | 2388 | .get_ethtool_stats = bdx_get_ethtool_stats, |
86573f61 | 2389 | .get_link_ksettings = bdx_get_link_ksettings, |
1a348ccc AG |
2390 | }; |
2391 | ||
7ad24ea4 | 2392 | netdev->ethtool_ops = &bdx_ethtool_ops; |
1a348ccc AG |
2393 | } |
2394 | ||
2395 | /** | |
2396 | * bdx_remove - Device Removal Routine | |
2397 | * @pdev: PCI device information struct | |
2398 | * | |
2399 | * bdx_remove is called by the PCI subsystem to alert the driver | |
2400 | * that it should release a PCI device. The could be caused by a | |
2401 | * Hot-Plug event, or because the driver is going to be removed from | |
2402 | * memory. | |
2403 | **/ | |
17abe3e4 | 2404 | static void bdx_remove(struct pci_dev *pdev) |
1a348ccc AG |
2405 | { |
2406 | struct pci_nic *nic = pci_get_drvdata(pdev); | |
2407 | struct net_device *ndev; | |
2408 | int port; | |
2409 | ||
2410 | for (port = 0; port < nic->port_num; port++) { | |
2411 | ndev = nic->priv[port]->ndev; | |
2412 | unregister_netdev(ndev); | |
2413 | free_netdev(ndev); | |
2414 | } | |
2415 | ||
2416 | /*bdx_hw_reset_direct(nic->regs); */ | |
2417 | #ifdef BDX_MSI | |
2418 | if (nic->irq_type == IRQ_MSI) | |
2419 | pci_disable_msi(pdev); | |
2420 | #endif | |
2421 | ||
2422 | iounmap(nic->regs); | |
2423 | pci_release_regions(pdev); | |
2424 | pci_disable_device(pdev); | |
1a348ccc AG |
2425 | vfree(nic); |
2426 | ||
2427 | RET(); | |
2428 | } | |
2429 | ||
2430 | static struct pci_driver bdx_pci_driver = { | |
2431 | .name = BDX_DRV_NAME, | |
2432 | .id_table = bdx_pci_tbl, | |
2433 | .probe = bdx_probe, | |
17abe3e4 | 2434 | .remove = bdx_remove, |
1a348ccc AG |
2435 | }; |
2436 | ||
2437 | /* | |
2438 | * print_driver_id - print parameters of the driver build | |
2439 | */ | |
2440 | static void __init print_driver_id(void) | |
2441 | { | |
865a21a5 JP |
2442 | pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION); |
2443 | pr_info("Options: hw_csum %s\n", BDX_MSI_STRING); | |
1a348ccc AG |
2444 | } |
2445 | ||
2446 | static int __init bdx_module_init(void) | |
2447 | { | |
2448 | ENTER; | |
1a348ccc AG |
2449 | init_txd_sizes(); |
2450 | print_driver_id(); | |
2451 | RET(pci_register_driver(&bdx_pci_driver)); | |
2452 | } | |
2453 | ||
2454 | module_init(bdx_module_init); | |
2455 | ||
2456 | static void __exit bdx_module_exit(void) | |
2457 | { | |
2458 | ENTER; | |
2459 | pci_unregister_driver(&bdx_pci_driver); | |
2460 | RET(); | |
2461 | } | |
2462 | ||
2463 | module_exit(bdx_module_exit); | |
2464 | ||
2465 | MODULE_LICENSE("GPL"); | |
2466 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2467 | MODULE_DESCRIPTION(BDX_DRV_DESC); | |
46814e08 | 2468 | MODULE_FIRMWARE("tehuti/bdx.bin"); |