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net: tehuti: fix error return code in bdx_probe()
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / tehuti / tehuti.c
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2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
1a348ccc
AG		 2/*
3 * Tehuti Networks(R) Network Driver
4 * ethtool interface implementation
5 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
1a348ccc
AG		 6 */
7
8/*
9 * RX HW/SW interaction overview
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
b595076a 11 * There are 2 types of RX communication channels between driver and NIC.
1a348ccc
AG		 12 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
13 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
14 * info about buffer's location, size and ID. An ID field is used to identify a
15 * buffer when it's returned with data via RXD Fifo (see below)
16 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
17 * filled by HW and is readen by SW. Each descriptor holds status and ID.
18 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
19 * via dma moves it into host memory, builds new RXD descriptor with same ID,
20 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
21 *
22 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
23 * One holds 1.5K packets and another - 26K packets. Depending on incoming
24 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
25 * filled with data, HW builds new RXD descriptor for it and push it into single
26 * RXD Fifo.
27 *
28 * RX SW Data Structures
29 * ~~~~~~~~~~~~~~~~~~~~~
30 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
31 * For RX case, ownership lasts from allocating new empty skb for RXF until
32 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
33 * skb db. Implemented as array with bitmask.
34 * fifo - keeps info about fifo's size and location, relevant HW registers,
35 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
36 * Implemented as simple struct.
37 *
38 * RX SW Execution Flow
39 * ~~~~~~~~~~~~~~~~~~~~
40 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
41 * relevant registers. At the end of init phase, driver enables interrupts.
42 * NIC sees that there is no RXF buffers and raises
43 * RD_INTR interrupt, isr fills skbs and Rx begins.
44 * Driver has two receive operation modes:
45 * NAPI - interrupt-driven mixed with polling
46 * interrupt-driven only
47 *
48 * Interrupt-driven only flow is following. When buffer is ready, HW raises
49 * interrupt and isr is called. isr collects all available packets
50 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
51
52 * Rx buffer allocation note
53 * ~~~~~~~~~~~~~~~~~~~~~~~~~
54 * Driver cares to feed such amount of RxF descriptors that respective amount of
55 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
56 * overflow check in Bordeaux for RxD fifo free/used size.
57 * FIXME: this is NOT fully implemented, more work should be done
58 *
59 */
60
865a21a5
JP		 61#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
62
1a348ccc 63#include "tehuti.h"
1a348ccc 64
9baa3c34 65static const struct pci_device_id bdx_pci_tbl[] = {
a355d865 66 { PCI_VDEVICE(TEHUTI, 0x3009), },
67 { PCI_VDEVICE(TEHUTI, 0x3010), },
68 { PCI_VDEVICE(TEHUTI, 0x3014), },
69 { 0 }
1a348ccc
AG		 70};
71
72MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
73
74/* Definitions needed by ISR or NAPI functions */
75static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
76static void bdx_tx_cleanup(struct bdx_priv *priv);
77static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
78
79/* Definitions needed by FW loading */
80static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
81
82/* Definitions needed by hw_start */
83static int bdx_tx_init(struct bdx_priv *priv);
84static int bdx_rx_init(struct bdx_priv *priv);
85
86/* Definitions needed by bdx_close */
87static void bdx_rx_free(struct bdx_priv *priv);
88static void bdx_tx_free(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_probe */
c061b18d 91static void bdx_set_ethtool_ops(struct net_device *netdev);
1a348ccc
AG		 92
93/*************************************************************************
94 * Print Info *
95 *************************************************************************/
96
97static void print_hw_id(struct pci_dev *pdev)
98{
99 struct pci_nic *nic = pci_get_drvdata(pdev);
100 u16 pci_link_status = 0;
101 u16 pci_ctrl = 0;
102
103 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
104 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
105
865a21a5
JP		 106 pr_info("%s%s\n", BDX_NIC_NAME,
107 nic->port_num == 1 ? "" : ", 2-Port");
108 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
109 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
110 readl(nic->regs + FPGA_SEED),
111 GET_LINK_STATUS_LANES(pci_link_status),
112 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
1a348ccc
AG		 113}
114
115static void print_fw_id(struct pci_nic *nic)
116{
865a21a5 117 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
1a348ccc
AG		 118}
119
120static void print_eth_id(struct net_device *ndev)
121{
865a21a5
JP		 122 netdev_info(ndev, "%s, Port %c\n",
123 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
1a348ccc
AG		 124
125}
126
127/*************************************************************************
128 * Code *
129 *************************************************************************/
130
131#define bdx_enable_interrupts(priv) \
132 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
133#define bdx_disable_interrupts(priv) \
134 do { WRITE_REG(priv, regIMR, 0); } while (0)
135
49ce9c2c
BH		 136/**
137 * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
138 * @priv: NIC private structure
139 * @f: fifo to initialize
140 * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
141 * @reg_XXX: offsets of registers relative to base address
142 *
1a348ccc
AG		 143 * 1K extra space is allocated at the end of the fifo to simplify
144 * processing of descriptors that wraps around fifo's end
1a348ccc
AG		 145 *
146 * Returns 0 on success, negative value on failure
147 *
148 */
149static int
150bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
151 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
152{
153 u16 memsz = FIFO_SIZE * (1 << fsz_type);
154
155 memset(f, 0, sizeof(struct fifo));
156 /* pci_alloc_consistent gives us 4k-aligned memory */
157 f->va = pci_alloc_consistent(priv->pdev,
158 memsz + FIFO_EXTRA_SPACE, &f->da);
159 if (!f->va) {
865a21a5 160 pr_err("pci_alloc_consistent failed\n");
1a348ccc
AG		 161 RET(-ENOMEM);
162 }
163 f->reg_CFG0 = reg_CFG0;
164 f->reg_CFG1 = reg_CFG1;
165 f->reg_RPTR = reg_RPTR;
166 f->reg_WPTR = reg_WPTR;
167 f->rptr = 0;
168 f->wptr = 0;
169 f->memsz = memsz;
170 f->size_mask = memsz - 1;
171 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
172 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
173
174 RET(0);
175}
176
49ce9c2c
BH		 177/**
178 * bdx_fifo_free - free all resources used by fifo
179 * @priv: NIC private structure
180 * @f: fifo to release
1a348ccc
AG		 181 */
182static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
183{
184 ENTER;
185 if (f->va) {
186 pci_free_consistent(priv->pdev,
187 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
188 f->va = NULL;
189 }
190 RET();
191}
192
49ce9c2c 193/**
1a348ccc 194 * bdx_link_changed - notifies OS about hw link state.
49ce9c2c 195 * @priv: hw adapter structure
1a348ccc
AG		 196 */
197static void bdx_link_changed(struct bdx_priv *priv)
198{
199 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
200
201 if (!link) {
202 if (netif_carrier_ok(priv->ndev)) {
203 netif_stop_queue(priv->ndev);
204 netif_carrier_off(priv->ndev);
865a21a5 205 netdev_err(priv->ndev, "Link Down\n");
1a348ccc
AG		 206 }
207 } else {
208 if (!netif_carrier_ok(priv->ndev)) {
209 netif_wake_queue(priv->ndev);
210 netif_carrier_on(priv->ndev);
865a21a5 211 netdev_err(priv->ndev, "Link Up\n");
1a348ccc
AG		 212 }
213 }
214}
215
216static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
217{
218 if (isr & IR_RX_FREE_0) {
219 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
220 DBG("RX_FREE_0\n");
221 }
222
223 if (isr & IR_LNKCHG0)
224 bdx_link_changed(priv);
225
226 if (isr & IR_PCIE_LINK)
865a21a5 227 netdev_err(priv->ndev, "PCI-E Link Fault\n");
1a348ccc
AG		 228
229 if (isr & IR_PCIE_TOUT)
865a21a5 230 netdev_err(priv->ndev, "PCI-E Time Out\n");
1a348ccc
AG		 231
232}
233
49ce9c2c
BH		 234/**
235 * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
236 * @irq: interrupt number
237 * @dev: network device
1a348ccc
AG		 238 *
239 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
240 *
241 * It reads ISR register to know interrupt reasons, and proceed them one by one.
242 * Reasons of interest are:
243 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
244 * RX_FREE - number of free Rx buffers in RXF fifo gets low
245 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
246 */
247
248static irqreturn_t bdx_isr_napi(int irq, void *dev)
249{
250 struct net_device *ndev = dev;
8f15ea42 251 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 252 u32 isr;
253
254 ENTER;
255 isr = (READ_REG(priv, regISR) & IR_RUN);
256 if (unlikely(!isr)) {
257 bdx_enable_interrupts(priv);
258 return IRQ_NONE; /* Not our interrupt */
259 }
260
261 if (isr & IR_EXTRA)
262 bdx_isr_extra(priv, isr);
263
264 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
288379f0
BH		 265 if (likely(napi_schedule_prep(&priv->napi))) {
266 __napi_schedule(&priv->napi);
1a348ccc
AG		 267 RET(IRQ_HANDLED);
268 } else {
269 /* NOTE: we get here if intr has slipped into window
270 * between these lines in bdx_poll:
271 * bdx_enable_interrupts(priv);
272 * return 0;
273 * currently intrs are disabled (since we read ISR),
274 * and we have failed to register next poll.
275 * so we read the regs to trigger chip
276 * and allow further interupts. */
277 READ_REG(priv, regTXF_WPTR_0);
278 READ_REG(priv, regRXD_WPTR_0);
279 }
280 }
281
282 bdx_enable_interrupts(priv);
283 RET(IRQ_HANDLED);
284}
285
286static int bdx_poll(struct napi_struct *napi, int budget)
287{
288 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
1a348ccc
AG		 289 int work_done;
290
291 ENTER;
292 bdx_tx_cleanup(priv);
293 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
294 if ((work_done < budget) ||
295 (priv->napi_stop++ >= 30)) {
296 DBG("rx poll is done. backing to isr-driven\n");
297
298 /* from time to time we exit to let NAPI layer release
299 * device lock and allow waiting tasks (eg rmmod) to advance) */
300 priv->napi_stop = 0;
301
6ad20165 302 napi_complete_done(napi, work_done);
1a348ccc
AG		 303 bdx_enable_interrupts(priv);
304 }
305 return work_done;
306}
307
49ce9c2c
BH		 308/**
309 * bdx_fw_load - loads firmware to NIC
310 * @priv: NIC private structure
311 *
1a348ccc
AG		 312 * Firmware is loaded via TXD fifo, so it must be initialized first.
313 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
314 * can have few of them). So all drivers use semaphore register to choose one
315 * that will actually load FW to NIC.
316 */
317
318static int bdx_fw_load(struct bdx_priv *priv)
319{
06e1f9ff 320 const struct firmware *fw = NULL;
1a348ccc 321 int master, i;
06e1f9ff 322 int rc;
1a348ccc
AG		 323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
46814e08 327 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
06e1f9ff
BH		 328 if (rc)
329 goto out;
330 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
1a348ccc
AG		 331 mdelay(100);
332 }
333 for (i = 0; i < 200; i++) {
06e1f9ff
BH		 334 if (READ_REG(priv, regINIT_STATUS)) {
335 rc = 0;
336 goto out;
337 }
1a348ccc
AG		 338 mdelay(2);
339 }
06e1f9ff
BH		 340 rc = -EIO;
341out:
1a348ccc
AG		 342 if (master)
343 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
53c0ad52
JJ		 344
345 release_firmware(fw);
1a348ccc 346
06e1f9ff 347 if (rc) {
865a21a5 348 netdev_err(priv->ndev, "firmware loading failed\n");
06e1f9ff
BH		 349 if (rc == -EIO)
350 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
351 READ_REG(priv, regVPC),
352 READ_REG(priv, regVIC),
353 READ_REG(priv, regINIT_STATUS), i);
354 RET(rc);
1a348ccc
AG		 355 } else {
356 DBG("%s: firmware loading success\n", priv->ndev->name);
357 RET(0);
358 }
359}
360
361static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
362{
363 u32 val;
364
365 ENTER;
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369
370 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
371 WRITE_REG(priv, regUNC_MAC2_A, val);
372 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
373 WRITE_REG(priv, regUNC_MAC1_A, val);
374 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
375 WRITE_REG(priv, regUNC_MAC0_A, val);
376
377 DBG("mac0=%x mac1=%x mac2=%x\n",
378 READ_REG(priv, regUNC_MAC0_A),
379 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
380 RET();
381}
382
49ce9c2c
BH		 383/**
384 * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
385 * @priv: NIC private structure
1a348ccc
AG		 386 */
387static int bdx_hw_start(struct bdx_priv *priv)
388{
389 int rc = -EIO;
390 struct net_device *ndev = priv->ndev;
391
392 ENTER;
393 bdx_link_changed(priv);
394
395 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
396 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
397 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
398 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
399 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
400 WRITE_REG(priv, regRX_FULLNESS, 0);
401 WRITE_REG(priv, regTX_FULLNESS, 0);
402 WRITE_REG(priv, regCTRLST,
403 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
404
405 WRITE_REG(priv, regVGLB, 0);
406 WRITE_REG(priv, regMAX_FRAME_A,
407 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
408
409 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
410 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
411 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
412
413 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
414 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
415
416 /* Enable timer interrupt once in 2 secs. */
417 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
418 bdx_restore_mac(priv->ndev, priv);
419
420 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
421 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
422
249658d5 423#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
cb001a1f
JP		 424
425 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
426 ndev->name, ndev);
427 if (rc)
1a348ccc
AG		 428 goto err_irq;
429 bdx_enable_interrupts(priv);
430
431 RET(0);
432
433err_irq:
434 RET(rc);
435}
436
437static void bdx_hw_stop(struct bdx_priv *priv)
438{
439 ENTER;
440 bdx_disable_interrupts(priv);
441 free_irq(priv->pdev->irq, priv->ndev);
442
443 netif_carrier_off(priv->ndev);
444 netif_stop_queue(priv->ndev);
445
446 RET();
447}
448
449static int bdx_hw_reset_direct(void __iomem *regs)
450{
451 u32 val, i;
452 ENTER;
453
454 /* reset sequences: read, write 1, read, write 0 */
455 val = readl(regs + regCLKPLL);
456 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
457 udelay(50);
458 val = readl(regs + regCLKPLL);
459 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
460
461 /* check that the PLLs are locked and reset ended */
462 for (i = 0; i < 70; i++, mdelay(10))
463 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
464 /* do any PCI-E read transaction */
465 readl(regs + regRXD_CFG0_0);
466 return 0;
467 }
865a21a5 468 pr_err("HW reset failed\n");
1a348ccc
AG		 469 return 1; /* failure */
470}
471
472static int bdx_hw_reset(struct bdx_priv *priv)
473{
474 u32 val, i;
475 ENTER;
476
477 if (priv->port == 0) {
478 /* reset sequences: read, write 1, read, write 0 */
479 val = READ_REG(priv, regCLKPLL);
480 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
481 udelay(50);
482 val = READ_REG(priv, regCLKPLL);
483 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
484 }
485 /* check that the PLLs are locked and reset ended */
486 for (i = 0; i < 70; i++, mdelay(10))
487 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
488 /* do any PCI-E read transaction */
489 READ_REG(priv, regRXD_CFG0_0);
490 return 0;
491 }
865a21a5 492 pr_err("HW reset failed\n");
1a348ccc
AG		 493 return 1; /* failure */
494}
495
496static int bdx_sw_reset(struct bdx_priv *priv)
497{
498 int i;
499
500 ENTER;
501 /* 1. load MAC (obsolete) */
502 /* 2. disable Rx (and Tx) */
503 WRITE_REG(priv, regGMAC_RXF_A, 0);
504 mdelay(100);
505 /* 3. disable port */
506 WRITE_REG(priv, regDIS_PORT, 1);
507 /* 4. disable queue */
508 WRITE_REG(priv, regDIS_QU, 1);
509 /* 5. wait until hw is disabled */
510 for (i = 0; i < 50; i++) {
511 if (READ_REG(priv, regRST_PORT) & 1)
512 break;
513 mdelay(10);
514 }
515 if (i == 50)
865a21a5 516 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
1a348ccc
AG		 517
518 /* 6. disable intrs */
519 WRITE_REG(priv, regRDINTCM0, 0);
520 WRITE_REG(priv, regTDINTCM0, 0);
521 WRITE_REG(priv, regIMR, 0);
522 READ_REG(priv, regISR);
523
524 /* 7. reset queue */
525 WRITE_REG(priv, regRST_QU, 1);
526 /* 8. reset port */
527 WRITE_REG(priv, regRST_PORT, 1);
528 /* 9. zero all read and write pointers */
529 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
530 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
531 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
532 WRITE_REG(priv, i, 0);
533 /* 10. unseet port disable */
534 WRITE_REG(priv, regDIS_PORT, 0);
535 /* 11. unset queue disable */
536 WRITE_REG(priv, regDIS_QU, 0);
537 /* 12. unset queue reset */
538 WRITE_REG(priv, regRST_QU, 0);
539 /* 13. unset port reset */
540 WRITE_REG(priv, regRST_PORT, 0);
541 /* 14. enable Rx */
542 /* skiped. will be done later */
543 /* 15. save MAC (obsolete) */
544 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
545 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
546
547 RET(0);
548}
549
550/* bdx_reset - performs right type of reset depending on hw type */
551static int bdx_reset(struct bdx_priv *priv)
552{
553 ENTER;
554 RET((priv->pdev->device == 0x3009)
555 ? bdx_hw_reset(priv)
556 : bdx_sw_reset(priv));
557}
558
559/**
560 * bdx_close - Disables a network interface
561 * @netdev: network interface device structure
562 *
563 * Returns 0, this is not allowed to fail
564 *
565 * The close entry point is called when an interface is de-activated
566 * by the OS. The hardware is still under the drivers control, but
567 * needs to be disabled. A global MAC reset is issued to stop the
568 * hardware, and all transmit and receive resources are freed.
569 **/
570static int bdx_close(struct net_device *ndev)
571{
572 struct bdx_priv *priv = NULL;
573
574 ENTER;
8f15ea42 575 priv = netdev_priv(ndev);
1a348ccc
AG		 576
577 napi_disable(&priv->napi);
578
579 bdx_reset(priv);
580 bdx_hw_stop(priv);
581 bdx_rx_free(priv);
582 bdx_tx_free(priv);
583 RET(0);
584}
585
586/**
587 * bdx_open - Called when a network interface is made active
588 * @netdev: network interface device structure
589 *
590 * Returns 0 on success, negative value on failure
591 *
592 * The open entry point is called when a network interface is made
593 * active by the system (IFF_UP). At this point all resources needed
594 * for transmit and receive operations are allocated, the interrupt
595 * handler is registered with the OS, the watchdog timer is started,
596 * and the stack is notified that the interface is ready.
597 **/
598static int bdx_open(struct net_device *ndev)
599{
600 struct bdx_priv *priv;
601 int rc;
602
603 ENTER;
8f15ea42 604 priv = netdev_priv(ndev);
1a348ccc
AG		 605 bdx_reset(priv);
606 if (netif_running(ndev))
607 netif_stop_queue(priv->ndev);
608
cb001a1f
JP		 609 if ((rc = bdx_tx_init(priv)) ||
610 (rc = bdx_rx_init(priv)) ||
611 (rc = bdx_fw_load(priv)))
1a348ccc
AG		 612 goto err;
613
614 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
615
cb001a1f
JP		 616 rc = bdx_hw_start(priv);
617 if (rc)
1a348ccc
AG		 618 goto err;
619
620 napi_enable(&priv->napi);
621
622 print_fw_id(priv->nic);
623
624 RET(0);
625
626err:
627 bdx_close(ndev);
628 RET(rc);
629}
630
6131a260
FR		 631static int bdx_range_check(struct bdx_priv *priv, u32 offset)
632{
633 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
634 -EINVAL : 0;
635}
636
1a348ccc
AG		 637static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
638{
8f15ea42 639 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 640 u32 data[3];
641 int error;
642
643 ENTER;
644
645 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
646 if (cmd != SIOCDEVPRIVATE) {
647 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
648 if (error) {
25985edc 649 pr_err("can't copy from user\n");
d2338070 650 RET(-EFAULT);
1a348ccc
AG		 651 }
652 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
1e6c22ae
CIK		 653 } else {
654 return -EOPNOTSUPP;
1a348ccc
AG		 655 }
656
62035542 657 if (!capable(CAP_SYS_RAWIO))
f946dffe
JG		 658 return -EPERM;
659
1a348ccc
AG		 660 switch (data[0]) {
661
662 case BDX_OP_READ:
6131a260
FR		 663 error = bdx_range_check(priv, data[1]);
664 if (error < 0)
665 return error;
1a348ccc
AG		 666 data[2] = READ_REG(priv, data[1]);
667 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
668 data[2]);
669 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
670 if (error)
d2338070 671 RET(-EFAULT);
1a348ccc
AG		 672 break;
673
674 case BDX_OP_WRITE:
6131a260
FR		 675 error = bdx_range_check(priv, data[1]);
676 if (error < 0)
677 return error;
1a348ccc
AG		 678 WRITE_REG(priv, data[1], data[2]);
679 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
680 break;
681
682 default:
683 RET(-EOPNOTSUPP);
684 }
685 return 0;
686}
687
688static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
689{
690 ENTER;
691 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
692 RET(bdx_ioctl_priv(ndev, ifr, cmd));
693 else
694 RET(-EOPNOTSUPP);
695}
696
49ce9c2c 697/**
1a348ccc 698 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
49ce9c2c
BH		 699 * @ndev: network device
700 * @vid: VLAN vid
701 * @op: add or kill operation
702 *
703 * Passes VLAN filter table to hardware
1a348ccc
AG		 704 */
705static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
706{
8f15ea42 707 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 708 u32 reg, bit, val;
709
710 ENTER;
711 DBG2("vid=%d value=%d\n", (int)vid, enable);
712 if (unlikely(vid >= 4096)) {
865a21a5 713 pr_err("invalid VID: %u (> 4096)\n", vid);
1a348ccc
AG		 714 RET();
715 }
716 reg = regVLAN_0 + (vid / 32) * 4;
717 bit = 1 << vid % 32;
718 val = READ_REG(priv, reg);
719 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
720 if (enable)
721 val |= bit;
722 else
723 val &= ~bit;
724 DBG2("new val %x\n", val);
725 WRITE_REG(priv, reg, val);
726 RET();
727}
728
49ce9c2c 729/**
1a348ccc 730 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
49ce9c2c
BH		 731 * @ndev: network device
732 * @vid: VLAN vid to add
1a348ccc 733 */
80d5c368 734static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
1a348ccc
AG		 735{
736 __bdx_vlan_rx_vid(ndev, vid, 1);
8e586137 737 return 0;
1a348ccc
AG		 738}
739
49ce9c2c 740/**
1a348ccc 741 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
49ce9c2c
BH		 742 * @ndev: network device
743 * @vid: VLAN vid to kill
1a348ccc 744 */
80d5c368 745static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
1a348ccc
AG		 746{
747 __bdx_vlan_rx_vid(ndev, vid, 0);
8e586137 748 return 0;
1a348ccc
AG		 749}
750
1a348ccc
AG		 751/**
752 * bdx_change_mtu - Change the Maximum Transfer Unit
753 * @netdev: network interface device structure
754 * @new_mtu: new value for maximum frame size
755 *
756 * Returns 0 on success, negative on failure
757 */
758static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
759{
1a348ccc
AG		 760 ENTER;
761
1a348ccc
AG		 762 ndev->mtu = new_mtu;
763 if (netif_running(ndev)) {
764 bdx_close(ndev);
765 bdx_open(ndev);
766 }
767 RET(0);
768}
769
770static void bdx_setmulti(struct net_device *ndev)
771{
8f15ea42 772 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 773
774 u32 rxf_val =
775 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
776 int i;
777
778 ENTER;
779 /* IMF - imperfect (hash) rx multicat filter */
780 /* PMF - perfect rx multicat filter */
781
782 /* FIXME: RXE(OFF) */
783 if (ndev->flags & IFF_PROMISC) {
784 rxf_val |= GMAC_RX_FILTER_PRM;
785 } else if (ndev->flags & IFF_ALLMULTI) {
786 /* set IMF to accept all multicast frmaes */
787 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
788 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
4cd24eaf 789 } else if (!netdev_mc_empty(ndev)) {
1a348ccc 790 u8 hash;
22bedad3 791 struct netdev_hw_addr *ha;
1a348ccc
AG		 792 u32 reg, val;
793
794 /* set IMF to deny all multicast frames */
795 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
796 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
797 /* set PMF to deny all multicast frames */
798 for (i = 0; i < MAC_MCST_NUM; i++) {
799 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
800 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
801 }
802
803 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
b595076a 804 /* TBD: sort addresses and write them in ascending order
1a348ccc
AG		 805 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
806 * multicast frames throu IMF */
1a348ccc 807 /* accept the rest of addresses throu IMF */
22bedad3 808 netdev_for_each_mc_addr(ha, ndev) {
1a348ccc
AG		 809 hash = 0;
810 for (i = 0; i < ETH_ALEN; i++)
22bedad3 811 hash ^= ha->addr[i];
1a348ccc
AG		 812 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
813 val = READ_REG(priv, reg);
814 val |= (1 << (hash % 32));
815 WRITE_REG(priv, reg, val);
816 }
817
818 } else {
4cd24eaf 819 DBG("only own mac %d\n", netdev_mc_count(ndev));
1a348ccc
AG		 820 rxf_val |= GMAC_RX_FILTER_AB;
821 }
822 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
823 /* enable RX */
824 /* FIXME: RXE(ON) */
825 RET();
826}
827
828static int bdx_set_mac(struct net_device *ndev, void *p)
829{
8f15ea42 830 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 831 struct sockaddr *addr = p;
832
833 ENTER;
834 /*
835 if (netif_running(dev))
836 return -EBUSY
837 */
838 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
839 bdx_restore_mac(ndev, priv);
840 RET(0);
841}
842
843static int bdx_read_mac(struct bdx_priv *priv)
844{
845 u16 macAddress[3], i;
846 ENTER;
847
848 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
849 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
850 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
851 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
852 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
853 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
854 for (i = 0; i < 3; i++) {
855 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
856 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
857 }
858 RET(0);
859}
860
861static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
862{
863 u64 val;
864
865 val = READ_REG(priv, reg);
866 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
867 return val;
868}
869
870/*Do the statistics-update work*/
871static void bdx_update_stats(struct bdx_priv *priv)
872{
873 struct bdx_stats *stats = &priv->hw_stats;
874 u64 *stats_vector = (u64 *) stats;
875 int i;
876 int addr;
877
878 /*Fill HW structure */
879 addr = 0x7200;
880 /*First 12 statistics - 0x7200 - 0x72B0 */
881 for (i = 0; i < 12; i++) {
882 stats_vector[i] = bdx_read_l2stat(priv, addr);
883 addr += 0x10;
884 }
885 BDX_ASSERT(addr != 0x72C0);
886 /* 0x72C0-0x72E0 RSRV */
887 addr = 0x72F0;
888 for (; i < 16; i++) {
889 stats_vector[i] = bdx_read_l2stat(priv, addr);
890 addr += 0x10;
891 }
892 BDX_ASSERT(addr != 0x7330);
893 /* 0x7330-0x7360 RSRV */
894 addr = 0x7370;
895 for (; i < 19; i++) {
896 stats_vector[i] = bdx_read_l2stat(priv, addr);
897 addr += 0x10;
898 }
899 BDX_ASSERT(addr != 0x73A0);
900 /* 0x73A0-0x73B0 RSRV */
901 addr = 0x73C0;
902 for (; i < 23; i++) {
903 stats_vector[i] = bdx_read_l2stat(priv, addr);
904 addr += 0x10;
905 }
906 BDX_ASSERT(addr != 0x7400);
907 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
908}
909
1a348ccc
AG		 910static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
911 u16 rxd_vlan);
912static void print_rxfd(struct rxf_desc *rxfd);
913
914/*************************************************************************
915 * Rx DB *
916 *************************************************************************/
917
918static void bdx_rxdb_destroy(struct rxdb *db)
919{
c0feed87 920 vfree(db);
1a348ccc
AG		 921}
922
923static struct rxdb *bdx_rxdb_create(int nelem)
924{
925 struct rxdb *db;
926 int i;
927
928 db = vmalloc(sizeof(struct rxdb)
929 + (nelem * sizeof(int))
930 + (nelem * sizeof(struct rx_map)));
931 if (likely(db != NULL)) {
932 db->stack = (int *)(db + 1);
933 db->elems = (void *)(db->stack + nelem);
934 db->nelem = nelem;
935 db->top = nelem;
936 for (i = 0; i < nelem; i++)
937 db->stack[i] = nelem - i - 1; /* to make first allocs
938 close to db struct*/
939 }
940
941 return db;
942}
943
944static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
945{
946 BDX_ASSERT(db->top <= 0);
947 return db->stack[--(db->top)];
948}
949
950static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
951{
952 BDX_ASSERT((n < 0) || (n >= db->nelem));
953 return db->elems + n;
954}
955
956static inline int bdx_rxdb_available(struct rxdb *db)
957{
958 return db->top;
959}
960
961static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
962{
963 BDX_ASSERT((n >= db->nelem) || (n < 0));
964 db->stack[(db->top)++] = n;
965}
966
967/*************************************************************************
968 * Rx Init *
969 *************************************************************************/
970
49ce9c2c
BH		 971/**
972 * bdx_rx_init - initialize RX all related HW and SW resources
973 * @priv: NIC private structure
1a348ccc
AG		 974 *
975 * Returns 0 on success, negative value on failure
976 *
977 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
978 * skb for rx. It assumes that Rx is desabled in HW
979 * funcs are grouped for better cache usage
980 *
025dfdaf 981 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
1a348ccc 982 * filled and packets will be dropped by nic without getting into host or
25985edc 983 * cousing interrupt. Anyway, in that condition, host has no chance to process
1a348ccc
AG		 984 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
985 */
986
987/* TBD: ensure proper packet size */
988
989static int bdx_rx_init(struct bdx_priv *priv)
990{
991 ENTER;
ddfce6bb 992
1a348ccc
AG		 993 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
994 regRXD_CFG0_0, regRXD_CFG1_0,
995 regRXD_RPTR_0, regRXD_WPTR_0))
996 goto err_mem;
997 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
998 regRXF_CFG0_0, regRXF_CFG1_0,
999 regRXF_RPTR_0, regRXF_WPTR_0))
1000 goto err_mem;
cb001a1f
JP		 1001 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1002 sizeof(struct rxf_desc));
1003 if (!priv->rxdb)
1a348ccc
AG		 1004 goto err_mem;
1005
1006 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1007 return 0;
1008
1009err_mem:
865a21a5 1010 netdev_err(priv->ndev, "Rx init failed\n");
1a348ccc
AG		 1011 return -ENOMEM;
1012}
1013
49ce9c2c
BH		 1014/**
1015 * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1016 * @priv: NIC private structure
1017 * @f: RXF fifo
1a348ccc
AG		 1018 */
1019static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1020{
1021 struct rx_map *dm;
1022 struct rxdb *db = priv->rxdb;
1023 u16 i;
1024
1025 ENTER;
1026 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1027 db->nelem - bdx_rxdb_available(db));
1028 while (bdx_rxdb_available(db) > 0) {
1029 i = bdx_rxdb_alloc_elem(db);
1030 dm = bdx_rxdb_addr_elem(db, i);
1031 dm->dma = 0;
1032 }
1033 for (i = 0; i < db->nelem; i++) {
1034 dm = bdx_rxdb_addr_elem(db, i);
1035 if (dm->dma) {
1036 pci_unmap_single(priv->pdev,
1037 dm->dma, f->m.pktsz,
1038 PCI_DMA_FROMDEVICE);
1039 dev_kfree_skb(dm->skb);
1040 }
1041 }
1042}
1043
49ce9c2c
BH		 1044/**
1045 * bdx_rx_free - release all Rx resources
1046 * @priv: NIC private structure
1047 *
1a348ccc
AG		 1048 * It assumes that Rx is desabled in HW
1049 */
1050static void bdx_rx_free(struct bdx_priv *priv)
1051{
1052 ENTER;
1053 if (priv->rxdb) {
1054 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1055 bdx_rxdb_destroy(priv->rxdb);
1056 priv->rxdb = NULL;
1057 }
1058 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1059 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1060
1061 RET();
1062}
1063
1064/*************************************************************************
1065 * Rx Engine *
1066 *************************************************************************/
1067
49ce9c2c
BH		 1068/**
1069 * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1070 * @priv: nic's private structure
1071 * @f: RXF fifo that needs skbs
1072 *
1a348ccc
AG		 1073 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1074 * skb's virtual and physical addresses are stored in skb db.
1075 * To calculate free space, func uses cached values of RPTR and WPTR
1076 * When needed, it also updates RPTR and WPTR.
1077 */
1078
1079/* TBD: do not update WPTR if no desc were written */
1080
1081static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1082{
1083 struct sk_buff *skb;
1084 struct rxf_desc *rxfd;
1085 struct rx_map *dm;
1086 int dno, delta, idx;
1087 struct rxdb *db = priv->rxdb;
1088
1089 ENTER;
1090 dno = bdx_rxdb_available(db) - 1;
1091 while (dno > 0) {
dae2e9f4 1092 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
720a43ef 1093 if (!skb)
1a348ccc 1094 break;
720a43ef 1095
1a348ccc
AG		 1096 skb_reserve(skb, NET_IP_ALIGN);
1097
1098 idx = bdx_rxdb_alloc_elem(db);
1099 dm = bdx_rxdb_addr_elem(db, idx);
1100 dm->dma = pci_map_single(priv->pdev,
1101 skb->data, f->m.pktsz,
1102 PCI_DMA_FROMDEVICE);
1103 dm->skb = skb;
1104 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1105 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1106 rxfd->va_lo = idx;
1107 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1108 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1109 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1110 print_rxfd(rxfd);
1111
1112 f->m.wptr += sizeof(struct rxf_desc);
1113 delta = f->m.wptr - f->m.memsz;
1114 if (unlikely(delta >= 0)) {
1115 f->m.wptr = delta;
1116 if (delta > 0) {
1117 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1118 DBG("wrapped descriptor\n");
1119 }
1120 }
1121 dno--;
1122 }
1123 /*TBD: to do - delayed rxf wptr like in txd */
1124 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1125 RET();
1126}
1127
1128static inline void
1129NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1130 struct sk_buff *skb)
1131{
1132 ENTER;
312cd513
JP		 1133 DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1134 if (GET_RXD_VTAG(rxd_val1)) {
1135 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1a348ccc
AG		 1136 priv->ndev->name,
1137 GET_RXD_VLAN_ID(rxd_vlan),
312cd513 1138 GET_RXD_VTAG(rxd_val1));
86a9bad3 1139 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1a348ccc 1140 }
312cd513 1141 netif_receive_skb(skb);
1a348ccc
AG		 1142}
1143
1144static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1145{
1146 struct rxf_desc *rxfd;
1147 struct rx_map *dm;
1148 struct rxf_fifo *f;
1149 struct rxdb *db;
1a348ccc
AG		 1150 int delta;
1151
1152 ENTER;
1153 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1154 f = &priv->rxf_fifo0;
1155 db = priv->rxdb;
1156 DBG("db=%p f=%p\n", db, f);
1157 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1158 DBG("dm=%p\n", dm);
1a348ccc
AG		 1159 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1160 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1161 rxfd->va_lo = rxdd->va_lo;
1162 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1163 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1164 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1165 print_rxfd(rxfd);
1166
1167 f->m.wptr += sizeof(struct rxf_desc);
1168 delta = f->m.wptr - f->m.memsz;
1169 if (unlikely(delta >= 0)) {
1170 f->m.wptr = delta;
1171 if (delta > 0) {
1172 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1173 DBG("wrapped descriptor\n");
1174 }
1175 }
1176 RET();
1177}
1178
49ce9c2c
BH		 1179/**
1180 * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
25985edc 1181 * NOTE: a special treatment is given to non-continuous descriptors
1a348ccc
AG		 1182 * that start near the end, wraps around and continue at the beginning. a second
1183 * part is copied right after the first, and then descriptor is interpreted as
1184 * normal. fifo has an extra space to allow such operations
49ce9c2c
BH		 1185 * @priv: nic's private structure
1186 * @f: RXF fifo that needs skbs
1187 * @budget: maximum number of packets to receive
1a348ccc
AG		 1188 */
1189
1190/* TBD: replace memcpy func call by explicite inline asm */
1191
1192static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1193{
0add79e3 1194 struct net_device *ndev = priv->ndev;
1a348ccc
AG		 1195 struct sk_buff *skb, *skb2;
1196 struct rxd_desc *rxdd;
1197 struct rx_map *dm;
1198 struct rxf_fifo *rxf_fifo;
1199 int tmp_len, size;
1200 int done = 0;
1201 int max_done = BDX_MAX_RX_DONE;
1202 struct rxdb *db = NULL;
1203 /* Unmarshalled descriptor - copy of descriptor in host order */
1204 u32 rxd_val1;
1205 u16 len;
1206 u16 rxd_vlan;
1207
1208 ENTER;
1209 max_done = budget;
1210
1a348ccc
AG		 1211 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1212
1213 size = f->m.wptr - f->m.rptr;
1214 if (size < 0)
1215 size = f->m.memsz + size; /* size is negative :-) */
1216
1217 while (size > 0) {
1218
1219 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1220 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1221
1222 len = CPU_CHIP_SWAP16(rxdd->len);
1223
1224 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1225
1226 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1227
1228 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1229 BDX_ASSERT(tmp_len <= 0);
1230 size -= tmp_len;
1231 if (size < 0) /* test for partially arrived descriptor */
1232 break;
1233
1234 f->m.rptr += tmp_len;
1235
1236 tmp_len = f->m.rptr - f->m.memsz;
1237 if (unlikely(tmp_len >= 0)) {
1238 f->m.rptr = tmp_len;
1239 if (tmp_len > 0) {
1240 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1241 f->m.rptr, tmp_len);
1242 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1243 }
1244 }
1245
1246 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1247 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
0add79e3 1248 ndev->stats.rx_errors++;
1a348ccc
AG		 1249 bdx_recycle_skb(priv, rxdd);
1250 continue;
1251 }
1252
1253 rxf_fifo = &priv->rxf_fifo0;
1254 db = priv->rxdb;
1255 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1256 skb = dm->skb;
1257
1258 if (len < BDX_COPYBREAK &&
dae2e9f4 1259 (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1a348ccc
AG		 1260 skb_reserve(skb2, NET_IP_ALIGN);
1261 /*skb_put(skb2, len); */
1262 pci_dma_sync_single_for_cpu(priv->pdev,
1263 dm->dma, rxf_fifo->m.pktsz,
1264 PCI_DMA_FROMDEVICE);
1265 memcpy(skb2->data, skb->data, len);
1266 bdx_recycle_skb(priv, rxdd);
1267 skb = skb2;
1268 } else {
1269 pci_unmap_single(priv->pdev,
1270 dm->dma, rxf_fifo->m.pktsz,
1271 PCI_DMA_FROMDEVICE);
1272 bdx_rxdb_free_elem(db, rxdd->va_lo);
1273 }
1274
0add79e3 1275 ndev->stats.rx_bytes += len;
1a348ccc
AG		 1276
1277 skb_put(skb, len);
0add79e3 1278 skb->protocol = eth_type_trans(skb, ndev);
1a348ccc
AG		 1279
1280 /* Non-IP packets aren't checksum-offloaded */
1281 if (GET_RXD_PKT_ID(rxd_val1) == 0)
bc8acf2c
ED		 1282 skb_checksum_none_assert(skb);
1283 else
1284 skb->ip_summed = CHECKSUM_UNNECESSARY;
1a348ccc
AG		 1285
1286 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1287
1288 if (++done >= max_done)
1289 break;
1290 }
1291
0add79e3 1292 ndev->stats.rx_packets += done;
1a348ccc
AG		 1293
1294 /* FIXME: do smth to minimize pci accesses */
1295 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1296
1297 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1298
1299 RET(done);
1300}
1301
1302/*************************************************************************
1303 * Debug / Temprorary Code *
1304 *************************************************************************/
1305static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1306 u16 rxd_vlan)
1307{
865a21a5 1308 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1a348ccc
AG		 1309 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1310 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1311 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1312 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1313 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1314 rxdd->va_hi);
1315}
1316
1317static void print_rxfd(struct rxf_desc *rxfd)
1318{
fd9071ec 1319 DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1a348ccc
AG		 1320 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1321 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1322}
1323
1324/*
1325 * TX HW/SW interaction overview
1326 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
b595076a 1327 * There are 2 types of TX communication channels between driver and NIC.
1a348ccc
AG		 1328 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1329 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1330 *
1331 * Currently NIC supports TSO, checksuming and gather DMA
1332 * UFO and IP fragmentation is on the way
1333 *
1334 * RX SW Data Structures
1335 * ~~~~~~~~~~~~~~~~~~~~~
1336 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1337 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1338 * acknowledges sent by TXF descriptors.
1339 * Implemented as cyclic buffer.
1340 * fifo - keeps info about fifo's size and location, relevant HW registers,
1341 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1342 * Implemented as simple struct.
1343 *
1344 * TX SW Execution Flow
1345 * ~~~~~~~~~~~~~~~~~~~~
1346 * OS calls driver's hard_xmit method with packet to sent.
1347 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1348 * by updating TXD WPTR.
1349 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1350 * To prevent TXD fifo overflow without reading HW registers every time,
1351 * SW deploys "tx level" technique.
1352 * Upon strart up, tx level is initialized to TXD fifo length.
1353 * For every sent packet, SW gets its TXD descriptor sizei
1354 * (from precalculated array) and substructs it from tx level.
1355 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1356 * original TXD descriptor from txdb and adds it to tx level.
1357 * When Tx level drops under some predefined treshhold, the driver
1358 * stops the TX queue. When TX level rises above that level,
1359 * the tx queue is enabled again.
1360 *
1361 * This technique avoids eccessive reading of RPTR and WPTR registers.
1362 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1363 */
1364
1365/*************************************************************************
1366 * Tx DB *
1367 *************************************************************************/
1368static inline int bdx_tx_db_size(struct txdb *db)
1369{
1370 int taken = db->wptr - db->rptr;
1371 if (taken < 0)
1372 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1373
1374 return db->size - taken;
1375}
1376
49ce9c2c
BH		 1377/**
1378 * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
1379 * @db: tx data base
1380 * @pptr: read or write pointer
1a348ccc
AG		 1381 */
1382static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1383{
1384 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1385
1386 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1387 *pptr != db->wptr); /* or write pointer */
1388
1389 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1390 *pptr >= db->end); /* in range */
1391
1392 ++*pptr;
1393 if (unlikely(*pptr == db->end))
1394 *pptr = db->start;
1395}
1396
49ce9c2c
BH		 1397/**
1398 * bdx_tx_db_inc_rptr - increment read pointer
1399 * @db: tx data base
1a348ccc
AG		 1400 */
1401static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1402{
1403 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1404 __bdx_tx_db_ptr_next(db, &db->rptr);
1405}
1406
49ce9c2c
BH		 1407/**
1408 * bdx_tx_db_inc_wptr - increment write pointer
1409 * @db: tx data base
1a348ccc
AG		 1410 */
1411static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1412{
1413 __bdx_tx_db_ptr_next(db, &db->wptr);
1414 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1415 a result of write */
1416}
1417
49ce9c2c
BH		 1418/**
1419 * bdx_tx_db_init - creates and initializes tx db
1420 * @d: tx data base
1421 * @sz_type: size of tx fifo
1422 *
1a348ccc
AG		 1423 * Returns 0 on success, error code otherwise
1424 */
1425static int bdx_tx_db_init(struct txdb *d, int sz_type)
1426{
1427 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1428
1429 d->start = vmalloc(memsz);
1430 if (!d->start)
1431 return -ENOMEM;
1432
1433 /*
1434 * In order to differentiate between db is empty and db is full
1435 * states at least one element should always be empty in order to
1436 * avoid rptr == wptr which means db is empty
1437 */
1438 d->size = memsz / sizeof(struct tx_map) - 1;
1439 d->end = d->start + d->size + 1; /* just after last element */
1440
1441 /* all dbs are created equally empty */
1442 d->rptr = d->start;
1443 d->wptr = d->start;
1444
1445 return 0;
1446}
1447
49ce9c2c
BH		 1448/**
1449 * bdx_tx_db_close - closes tx db and frees all memory
1450 * @d: tx data base
1a348ccc
AG		 1451 */
1452static void bdx_tx_db_close(struct txdb *d)
1453{
1454 BDX_ASSERT(d == NULL);
1455
c0feed87
F		 1456 vfree(d->start);
1457 d->start = NULL;
1a348ccc
AG		 1458}
1459
1460/*************************************************************************
1461 * Tx Engine *
1462 *************************************************************************/
1463
1464/* sizes of tx desc (including padding if needed) as function
1465 * of skb's frag number */
1466static struct {
1467 u16 bytes;
1468 u16 qwords; /* qword = 64 bit */
1469} txd_sizes[MAX_SKB_FRAGS + 1];
1470
49ce9c2c
BH		 1471/**
1472 * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
1473 * @priv: NIC private structure
1474 * @skb: socket buffer to map
1475 * @txdd: TX descriptor to use
1a348ccc
AG		 1476 *
1477 * It makes dma mappings for skb's data blocks and writes them to PBL of
1478 * new tx descriptor. It also stores them in the tx db, so they could be
1479 * unmaped after data was sent. It is reponsibility of a caller to make
1480 * sure that there is enough space in the tx db. Last element holds pointer
1481 * to skb itself and marked with zero length
1482 */
1483static inline void
1484bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1485 struct txd_desc *txdd)
1486{
1487 struct txdb *db = &priv->txdb;
1488 struct pbl *pbl = &txdd->pbl[0];
1489 int nr_frags = skb_shinfo(skb)->nr_frags;
1490 int i;
1491
e743d313 1492 db->wptr->len = skb_headlen(skb);
1a348ccc
AG		 1493 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1494 db->wptr->len, PCI_DMA_TODEVICE);
1495 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1496 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1497 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1498 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1499 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1500 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1501 bdx_tx_db_inc_wptr(db);
1502
1503 for (i = 0; i < nr_frags; i++) {
d7840976 1504 const skb_frag_t *frag;
1a348ccc
AG		 1505
1506 frag = &skb_shinfo(skb)->frags[i];
9e903e08 1507 db->wptr->len = skb_frag_size(frag);
e4811086 1508 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
9e903e08 1509 0, skb_frag_size(frag),
5d6bcdfe 1510 DMA_TO_DEVICE);
1a348ccc
AG		 1511
1512 pbl++;
1513 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1514 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1515 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1516 bdx_tx_db_inc_wptr(db);
1517 }
1518
1519 /* add skb clean up info. */
1520 db->wptr->len = -txd_sizes[nr_frags].bytes;
1521 db->wptr->addr.skb = skb;
1522 bdx_tx_db_inc_wptr(db);
1523}
1524
1525/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1526 * number of frags is used as index to fetch correct descriptors size,
1527 * instead of calculating it each time */
1528static void __init init_txd_sizes(void)
1529{
1530 int i, lwords;
1531
1532 /* 7 - is number of lwords in txd with one phys buffer
1533 * 3 - is number of lwords used for every additional phys buffer */
1534 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1535 lwords = 7 + (i * 3);
1536 if (lwords & 1)
1537 lwords++; /* pad it with 1 lword */
1538 txd_sizes[i].qwords = lwords >> 1;
1539 txd_sizes[i].bytes = lwords << 2;
1540 }
1541}
1542
1543/* bdx_tx_init - initialize all Tx related stuff.
1544 * Namely, TXD and TXF fifos, database etc */
1545static int bdx_tx_init(struct bdx_priv *priv)
1546{
1547 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1548 regTXD_CFG0_0,
1549 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1550 goto err_mem;
1551 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1552 regTXF_CFG0_0,
1553 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1554 goto err_mem;
1555
1556 /* The TX db has to keep mappings for all packets sent (on TxD)
1557 * and not yet reclaimed (on TxF) */
1558 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1559 goto err_mem;
1560
1561 priv->tx_level = BDX_MAX_TX_LEVEL;
1562#ifdef BDX_DELAY_WPTR
1563 priv->tx_update_mark = priv->tx_level - 1024;
1564#endif
1565 return 0;
1566
1567err_mem:
865a21a5 1568 netdev_err(priv->ndev, "Tx init failed\n");
1a348ccc
AG		 1569 return -ENOMEM;
1570}
1571
49ce9c2c 1572/**
25985edc 1573 * bdx_tx_space - calculates available space in TX fifo
49ce9c2c
BH		 1574 * @priv: NIC private structure
1575 *
25985edc 1576 * Returns available space in TX fifo in bytes
1a348ccc
AG		 1577 */
1578static inline int bdx_tx_space(struct bdx_priv *priv)
1579{
1580 struct txd_fifo *f = &priv->txd_fifo0;
1581 int fsize;
1582
1583 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1584 fsize = f->m.rptr - f->m.wptr;
1585 if (fsize <= 0)
1586 fsize = f->m.memsz + fsize;
249658d5 1587 return fsize;
1a348ccc
AG		 1588}
1589
49ce9c2c
BH		 1590/**
1591 * bdx_tx_transmit - send packet to NIC
1592 * @skb: packet to send
1593 * @ndev: network device assigned to NIC
1a348ccc
AG		 1594 * Return codes:
1595 * o NETDEV_TX_OK everything ok.
1596 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1597 * Usually a bug, means queue start/stop flow control is broken in
1598 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1a348ccc 1599 */
61357325
SH		 1600static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1601 struct net_device *ndev)
1a348ccc 1602{
8f15ea42 1603 struct bdx_priv *priv = netdev_priv(ndev);
1a348ccc
AG		 1604 struct txd_fifo *f = &priv->txd_fifo0;
1605 int txd_checksum = 7; /* full checksum */
1606 int txd_lgsnd = 0;
1607 int txd_vlan_id = 0;
1608 int txd_vtag = 0;
1609 int txd_mss = 0;
1610
1611 int nr_frags = skb_shinfo(skb)->nr_frags;
1612 struct txd_desc *txdd;
1613 int len;
1614 unsigned long flags;
1615
1616 ENTER;
1617 local_irq_save(flags);
a6086a89 1618 spin_lock(&priv->tx_lock);
1a348ccc
AG		 1619
1620 /* build tx descriptor */
1621 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1622 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1623 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1624 txd_checksum = 0;
1625
1626 if (skb_shinfo(skb)->gso_size) {
1627 txd_mss = skb_shinfo(skb)->gso_size;
1628 txd_lgsnd = 1;
1629 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1630 txd_mss);
1631 }
1632
df8a39de 1633 if (skb_vlan_tag_present(skb)) {
1a348ccc 1634 /*Cut VLAN ID to 12 bits */
df8a39de 1635 txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1a348ccc
AG		 1636 txd_vtag = 1;
1637 }
1638
1639 txdd->length = CPU_CHIP_SWAP16(skb->len);
1640 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1641 txdd->txd_val1 =
1642 CPU_CHIP_SWAP32(TXD_W1_VAL
1643 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1644 txd_lgsnd, txd_vlan_id));
1645 DBG("=== TxD desc =====================\n");
1646 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1647 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1648
1649 bdx_tx_map_skb(priv, skb, txdd);
1650
1651 /* increment TXD write pointer. In case of
1652 fifo wrapping copy reminder of the descriptor
1653 to the beginning */
1654 f->m.wptr += txd_sizes[nr_frags].bytes;
1655 len = f->m.wptr - f->m.memsz;
1656 if (unlikely(len >= 0)) {
1657 f->m.wptr = len;
1658 if (len > 0) {
1659 BDX_ASSERT(len > f->m.memsz);
1660 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1661 }
1662 }
1663 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1664
1665 priv->tx_level -= txd_sizes[nr_frags].bytes;
1666 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1667#ifdef BDX_DELAY_WPTR
1668 if (priv->tx_level > priv->tx_update_mark) {
1669 /* Force memory writes to complete before letting h/w
1670 know there are new descriptors to fetch.
1671 (might be needed on platforms like IA64)
1672 wmb(); */
1673 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1674 } else {
1675 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1676 priv->tx_noupd = 0;
1677 WRITE_REG(priv, f->m.reg_WPTR,
1678 f->m.wptr & TXF_WPTR_WR_PTR);
1679 }
1680 }
1681#else
1682 /* Force memory writes to complete before letting h/w
1683 know there are new descriptors to fetch.
1684 (might be needed on platforms like IA64)
1685 wmb(); */
1686 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1687
1688#endif
28679751 1689#ifdef BDX_LLTX
860e9538 1690 netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */
28679751 1691#endif
0add79e3
TK		 1692 ndev->stats.tx_packets++;
1693 ndev->stats.tx_bytes += skb->len;
1a348ccc
AG		 1694
1695 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1696 DBG("%s: %s: TX Q STOP level %d\n",
1697 BDX_DRV_NAME, ndev->name, priv->tx_level);
1698 netif_stop_queue(ndev);
1699 }
1700
1701 spin_unlock_irqrestore(&priv->tx_lock, flags);
1702 return NETDEV_TX_OK;
1703}
1704
49ce9c2c
BH		 1705/**
1706 * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1707 * @priv: bdx adapter
1708 *
1a348ccc
AG		 1709 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1710 * that those packets were sent
1711 */
1712static void bdx_tx_cleanup(struct bdx_priv *priv)
1713{
1714 struct txf_fifo *f = &priv->txf_fifo0;
1715 struct txdb *db = &priv->txdb;
1716 int tx_level = 0;
1717
1718 ENTER;
1719 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1720 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1721
1722 while (f->m.wptr != f->m.rptr) {
1723 f->m.rptr += BDX_TXF_DESC_SZ;
1724 f->m.rptr &= f->m.size_mask;
1725
1726 /* unmap all the fragments */
1727 /* first has to come tx_maps containing dma */
1728 BDX_ASSERT(db->rptr->len == 0);
1729 do {
1730 BDX_ASSERT(db->rptr->addr.dma == 0);
1731 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1732 db->rptr->len, PCI_DMA_TODEVICE);
1733 bdx_tx_db_inc_rptr(db);
1734 } while (db->rptr->len > 0);
1735 tx_level -= db->rptr->len; /* '-' koz len is negative */
1736
1737 /* now should come skb pointer - free it */
f4ad1a61 1738 dev_consume_skb_irq(db->rptr->addr.skb);
1a348ccc
AG		 1739 bdx_tx_db_inc_rptr(db);
1740 }
1741
1742 /* let h/w know which TXF descriptors were cleaned */
1743 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1744 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1745
1746 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
88bfe6ea 1747 * we resume the transmission and use tx_lock to synchronize with xmit.*/
1a348ccc
AG		 1748 spin_lock(&priv->tx_lock);
1749 priv->tx_level += tx_level;
1750 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1751#ifdef BDX_DELAY_WPTR
1752 if (priv->tx_noupd) {
1753 priv->tx_noupd = 0;
1754 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1755 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1756 }
1757#endif
1758
8e95a202
JP		 1759 if (unlikely(netif_queue_stopped(priv->ndev) &&
1760 netif_carrier_ok(priv->ndev) &&
1761 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1a348ccc
AG		 1762 DBG("%s: %s: TX Q WAKE level %d\n",
1763 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1764 netif_wake_queue(priv->ndev);
1765 }
1766 spin_unlock(&priv->tx_lock);
1767}
1768
49ce9c2c
BH		 1769/**
1770 * bdx_tx_free_skbs - frees all skbs from TXD fifo.
1a348ccc
AG		 1771 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1772 */
1773static void bdx_tx_free_skbs(struct bdx_priv *priv)
1774{
1775 struct txdb *db = &priv->txdb;
1776
1777 ENTER;
1778 while (db->rptr != db->wptr) {
1779 if (likely(db->rptr->len))
1780 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1781 db->rptr->len, PCI_DMA_TODEVICE);
1782 else
1783 dev_kfree_skb(db->rptr->addr.skb);
1784 bdx_tx_db_inc_rptr(db);
1785 }
1786 RET();
1787}
1788
1789/* bdx_tx_free - frees all Tx resources */
1790static void bdx_tx_free(struct bdx_priv *priv)
1791{
1792 ENTER;
1793 bdx_tx_free_skbs(priv);
1794 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1795 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1796 bdx_tx_db_close(&priv->txdb);
1797}
1798
49ce9c2c
BH		 1799/**
1800 * bdx_tx_push_desc - push descriptor to TxD fifo
1801 * @priv: NIC private structure
1802 * @data: desc's data
1803 * @size: desc's size
1a348ccc
AG		 1804 *
1805 * Pushes desc to TxD fifo and overlaps it if needed.
1806 * NOTE: this func does not check for available space. this is responsibility
025dfdaf 1807 * of the caller. Neither does it check that data size is smaller than
1a348ccc
AG		 1808 * fifo size.
1809 */
1810static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1811{
1812 struct txd_fifo *f = &priv->txd_fifo0;
1813 int i = f->m.memsz - f->m.wptr;
1814
1815 if (size == 0)
1816 return;
1817
1818 if (i > size) {
1819 memcpy(f->m.va + f->m.wptr, data, size);
1820 f->m.wptr += size;
1821 } else {
1822 memcpy(f->m.va + f->m.wptr, data, i);
1823 f->m.wptr = size - i;
1824 memcpy(f->m.va, data + i, f->m.wptr);
1825 }
1826 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1827}
1828
49ce9c2c
BH		 1829/**
1830 * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1831 * @priv: NIC private structure
1832 * @data: desc's data
1833 * @size: desc's size
1a348ccc 1834 *
3ad2f3fb 1835 * NOTE: this func does check for available space and, if necessary, waits for
1a348ccc
AG		 1836 * NIC to read existing data before writing new one.
1837 */
1838static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1839{
1840 int timer = 0;
1841 ENTER;
1842
1843 while (size > 0) {
1844 /* we substruct 8 because when fifo is full rptr == wptr
1845 which also means that fifo is empty, we can understand
1846 the difference, but could hw do the same ??? :) */
1847 int avail = bdx_tx_space(priv) - 8;
1848 if (avail <= 0) {
1849 if (timer++ > 300) { /* prevent endless loop */
1850 DBG("timeout while writing desc to TxD fifo\n");
1851 break;
1852 }
1853 udelay(50); /* give hw a chance to clean fifo */
1854 continue;
1855 }
df7641af 1856 avail = min(avail, size);
1a348ccc
AG		 1857 DBG("about to push %d bytes starting %p size %d\n", avail,
1858 data, size);
1859 bdx_tx_push_desc(priv, data, avail);
1860 size -= avail;
1861 data += avail;
1862 }
1863 RET();
1864}
1865
2f30b1f6 1866static const struct net_device_ops bdx_netdev_ops = {
312cd513 1867 .ndo_open = bdx_open,
2f30b1f6
SH		 1868 .ndo_stop = bdx_close,
1869 .ndo_start_xmit = bdx_tx_transmit,
1870 .ndo_validate_addr = eth_validate_addr,
1871 .ndo_do_ioctl = bdx_ioctl,
afc4b13d 1872 .ndo_set_rx_mode = bdx_setmulti,
2f30b1f6
SH		 1873 .ndo_change_mtu = bdx_change_mtu,
1874 .ndo_set_mac_address = bdx_set_mac,
2f30b1f6
SH		 1875 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1876 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1877};
1878
1a348ccc
AG		 1879/**
1880 * bdx_probe - Device Initialization Routine
1881 * @pdev: PCI device information struct
1882 * @ent: entry in bdx_pci_tbl
1883 *
1884 * Returns 0 on success, negative on failure
1885 *
1886 * bdx_probe initializes an adapter identified by a pci_dev structure.
1887 * The OS initialization, configuring of the adapter private structure,
1888 * and a hardware reset occur.
1889 *
1890 * functions and their order used as explained in
1891 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1892 *
1893 */
1894
1895/* TBD: netif_msg should be checked and implemented. I disable it for now */
17abe3e4 1896static int
1a348ccc
AG		 1897bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1898{
1899 struct net_device *ndev;
1900 struct bdx_priv *priv;
1901 int err, pci_using_dac, port;
1902 unsigned long pciaddr;
1903 u32 regionSize;
1904 struct pci_nic *nic;
1905
1906 ENTER;
1907
1908 nic = vmalloc(sizeof(*nic));
1909 if (!nic)
1910 RET(-ENOMEM);
1911
1912 /************** pci *****************/
cb001a1f
JP		 1913 err = pci_enable_device(pdev);
1914 if (err) /* it triggers interrupt, dunno why. */
1915 goto err_pci; /* it's not a problem though */
1a348ccc 1916
6a35528a
YH		 1917 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1918 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1a348ccc
AG		 1919 pci_using_dac = 1;
1920 } else {
284901a9
YH		 1921 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1922 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
865a21a5 1923 pr_err("No usable DMA configuration, aborting\n");
1a348ccc
AG		 1924 goto err_dma;
1925 }
1926 pci_using_dac = 0;
1927 }
1928
cb001a1f
JP		 1929 err = pci_request_regions(pdev, BDX_DRV_NAME);
1930 if (err)
1a348ccc
AG		 1931 goto err_dma;
1932
1933 pci_set_master(pdev);
1934
1935 pciaddr = pci_resource_start(pdev, 0);
1936 if (!pciaddr) {
1937 err = -EIO;
865a21a5 1938 pr_err("no MMIO resource\n");
1a348ccc
AG		 1939 goto err_out_res;
1940 }
cb001a1f
JP		 1941 regionSize = pci_resource_len(pdev, 0);
1942 if (regionSize < BDX_REGS_SIZE) {
1a348ccc 1943 err = -EIO;
865a21a5 1944 pr_err("MMIO resource (%x) too small\n", regionSize);
1a348ccc
AG		 1945 goto err_out_res;
1946 }
1947
1948 nic->regs = ioremap(pciaddr, regionSize);
1949 if (!nic->regs) {
1950 err = -EIO;
865a21a5 1951 pr_err("ioremap failed\n");
1a348ccc
AG		 1952 goto err_out_res;
1953 }
1954
1955 if (pdev->irq < 2) {
1956 err = -EIO;
865a21a5 1957 pr_err("invalid irq (%d)\n", pdev->irq);
1a348ccc
AG		 1958 goto err_out_iomap;
1959 }
1960 pci_set_drvdata(pdev, nic);
1961
1962 if (pdev->device == 0x3014)
1963 nic->port_num = 2;
1964 else
1965 nic->port_num = 1;
1966
1967 print_hw_id(pdev);
1968
1969 bdx_hw_reset_direct(nic->regs);
1970
1971 nic->irq_type = IRQ_INTX;
1972#ifdef BDX_MSI
1973 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
cb001a1f
JP		 1974 err = pci_enable_msi(pdev);
1975 if (err)
d524d84b 1976 pr_err("Can't enable msi. error is %d\n", err);
1a348ccc
AG		 1977 else
1978 nic->irq_type = IRQ_MSI;
1979 } else
1980 DBG("HW does not support MSI\n");
1981#endif
1982
1983 /************** netdev **************/
1984 for (port = 0; port < nic->port_num; port++) {
cb001a1f
JP		 1985 ndev = alloc_etherdev(sizeof(struct bdx_priv));
1986 if (!ndev) {
1a348ccc 1987 err = -ENOMEM;
1a348ccc
AG		 1988 goto err_out_iomap;
1989 }
1990
2f30b1f6 1991 ndev->netdev_ops = &bdx_netdev_ops;
1a348ccc 1992 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1a348ccc 1993
c061b18d 1994 bdx_set_ethtool_ops(ndev); /* ethtool interface */
1a348ccc
AG		 1995
1996 /* these fields are used for info purposes only
1997 * so we can have them same for all ports of the board */
1998 ndev->if_port = port;
1a348ccc 1999 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
f646968f
PM		 2000 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2001 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
1a348ccc 2002 ;
eea3250b 2003 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
f646968f 2004 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
1a348ccc
AG		 2005
2006 if (pci_using_dac)
2007 ndev->features |= NETIF_F_HIGHDMA;
2008
2009 /************** priv ****************/
8f15ea42 2010 priv = nic->priv[port] = netdev_priv(ndev);
1a348ccc 2011
1a348ccc
AG		 2012 priv->pBdxRegs = nic->regs + port * 0x8000;
2013 priv->port = port;
2014 priv->pdev = pdev;
2015 priv->ndev = ndev;
2016 priv->nic = nic;
2017 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2018
2019 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2020
2021 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2022 DBG("HW statistics not supported\n");
2023 priv->stats_flag = 0;
2024 } else {
2025 priv->stats_flag = 1;
2026 }
2027
2028 /* Initialize fifo sizes. */
2029 priv->txd_size = 2;
2030 priv->txf_size = 2;
2031 priv->rxd_size = 2;
2032 priv->rxf_size = 3;
2033
2034 /* Initialize the initial coalescing registers. */
2035 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2036 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2037
2038 /* ndev->xmit_lock spinlock is not used.
2039 * Private priv->tx_lock is used for synchronization
2040 * between transmit and TX irq cleanup. In addition
2041 * set multicast list callback has to use priv->tx_lock.
2042 */
2043#ifdef BDX_LLTX
2044 ndev->features |= NETIF_F_LLTX;
2045#endif
44770e11
JW		 2046 /* MTU range: 60 - 16384 */
2047 ndev->min_mtu = ETH_ZLEN;
2048 ndev->max_mtu = BDX_MAX_MTU;
2049
1a348ccc
AG		 2050 spin_lock_init(&priv->tx_lock);
2051
2052 /*bdx_hw_reset(priv); */
2053 if (bdx_read_mac(priv)) {
865a21a5 2054 pr_err("load MAC address failed\n");
4f21a2ab 2055 err = -EFAULT;
1a348ccc
AG		 2056 goto err_out_iomap;
2057 }
2058 SET_NETDEV_DEV(ndev, &pdev->dev);
cb001a1f
JP		 2059 err = register_netdev(ndev);
2060 if (err) {
865a21a5 2061 pr_err("register_netdev failed\n");
1a348ccc
AG		 2062 goto err_out_free;
2063 }
2064 netif_carrier_off(ndev);
2065 netif_stop_queue(ndev);
2066
2067 print_eth_id(ndev);
2068 }
2069 RET(0);
2070
2071err_out_free:
2072 free_netdev(ndev);
2073err_out_iomap:
2074 iounmap(nic->regs);
2075err_out_res:
2076 pci_release_regions(pdev);
2077err_dma:
2078 pci_disable_device(pdev);
bc2618f7 2079err_pci:
1a348ccc
AG		 2080 vfree(nic);
2081
2082 RET(err);
2083}
2084
2085/****************** Ethtool interface *********************/
1a348ccc
AG		 2086/* get strings for statistics counters */
2087static const char
2088 bdx_stat_names[][ETH_GSTRING_LEN] = {
2089 "InUCast", /* 0x7200 */
2090 "InMCast", /* 0x7210 */
2091 "InBCast", /* 0x7220 */
2092 "InPkts", /* 0x7230 */
2093 "InErrors", /* 0x7240 */
2094 "InDropped", /* 0x7250 */
2095 "FrameTooLong", /* 0x7260 */
2096 "FrameSequenceErrors", /* 0x7270 */
2097 "InVLAN", /* 0x7280 */
2098 "InDroppedDFE", /* 0x7290 */
2099 "InDroppedIntFull", /* 0x72A0 */
2100 "InFrameAlignErrors", /* 0x72B0 */
2101
2102 /* 0x72C0-0x72E0 RSRV */
2103
2104 "OutUCast", /* 0x72F0 */
2105 "OutMCast", /* 0x7300 */
2106 "OutBCast", /* 0x7310 */
2107 "OutPkts", /* 0x7320 */
2108
2109 /* 0x7330-0x7360 RSRV */
2110
2111 "OutVLAN", /* 0x7370 */
2112 "InUCastOctects", /* 0x7380 */
2113 "OutUCastOctects", /* 0x7390 */
2114
2115 /* 0x73A0-0x73B0 RSRV */
2116
2117 "InBCastOctects", /* 0x73C0 */
2118 "OutBCastOctects", /* 0x73D0 */
2119 "InOctects", /* 0x73E0 */
2120 "OutOctects", /* 0x73F0 */
2121};
2122
2123/*
86573f61 2124 * bdx_get_link_ksettings - get device-specific settings
1a348ccc
AG		 2125 * @netdev
2126 * @ecmd
2127 */
86573f61
PR		 2128static int bdx_get_link_ksettings(struct net_device *netdev,
2129 struct ethtool_link_ksettings *ecmd)
2130{
2131 ethtool_link_ksettings_zero_link_mode(ecmd, supported);
2132 ethtool_link_ksettings_add_link_mode(ecmd, supported,
2133 10000baseT_Full);
2134 ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE);
2135 ethtool_link_ksettings_zero_link_mode(ecmd, advertising);
2136 ethtool_link_ksettings_add_link_mode(ecmd, advertising,
2137 10000baseT_Full);
2138 ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE);
2139
2140 ecmd->base.speed = SPEED_10000;
2141 ecmd->base.duplex = DUPLEX_FULL;
2142 ecmd->base.port = PORT_FIBRE;
2143 ecmd->base.autoneg = AUTONEG_DISABLE;
1a348ccc
AG		 2144
2145 return 0;
2146}
2147
2148/*
2149 * bdx_get_drvinfo - report driver information
2150 * @netdev
2151 * @drvinfo
2152 */
2153static void
2154bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2155{
8f15ea42 2156 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc 2157
7826d43f
JP		 2158 strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2159 strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2160 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2161 strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
1a348ccc 2162 sizeof(drvinfo->bus_info));
1a348ccc
AG		 2163}
2164
1a348ccc
AG		 2165/*
2166 * bdx_get_coalesce - get interrupt coalescing parameters
2167 * @netdev
2168 * @ecoal
2169 */
2170static int
2171bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2172{
2173 u32 rdintcm;
2174 u32 tdintcm;
8f15ea42 2175 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2176
2177 rdintcm = priv->rdintcm;
2178 tdintcm = priv->tdintcm;
2179
2180 /* PCK_TH measures in multiples of FIFO bytes
2181 We translate to packets */
2182 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2183 ecoal->rx_max_coalesced_frames =
2184 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2185
2186 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2187 ecoal->tx_max_coalesced_frames =
2188 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2189
2190 /* adaptive parameters ignored */
2191 return 0;
2192}
2193
2194/*
2195 * bdx_set_coalesce - set interrupt coalescing parameters
2196 * @netdev
2197 * @ecoal
2198 */
2199static int
2200bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2201{
2202 u32 rdintcm;
2203 u32 tdintcm;
8f15ea42 2204 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2205 int rx_coal;
2206 int tx_coal;
2207 int rx_max_coal;
2208 int tx_max_coal;
2209
2210 /* Check for valid input */
2211 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2212 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2213 rx_max_coal = ecoal->rx_max_coalesced_frames;
2214 tx_max_coal = ecoal->tx_max_coalesced_frames;
2215
2216 /* Translate from packets to multiples of FIFO bytes */
2217 rx_max_coal =
2218 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2219 / PCK_TH_MULT);
2220 tx_max_coal =
2221 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2222 / PCK_TH_MULT);
2223
8e95a202
JP		 2224 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2225 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
1a348ccc
AG		 2226 return -EINVAL;
2227
2228 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2229 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2230 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2231 tx_max_coal);
2232
2233 priv->rdintcm = rdintcm;
2234 priv->tdintcm = tdintcm;
2235
2236 WRITE_REG(priv, regRDINTCM0, rdintcm);
2237 WRITE_REG(priv, regTDINTCM0, tdintcm);
2238
2239 return 0;
2240}
2241
2242/* Convert RX fifo size to number of pending packets */
2243static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2244{
249658d5 2245 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
1a348ccc
AG		 2246}
2247
2248/* Convert TX fifo size to number of pending packets */
2249static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2250{
249658d5 2251 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
1a348ccc
AG		 2252}
2253
2254/*
2255 * bdx_get_ringparam - report ring sizes
2256 * @netdev
2257 * @ring
2258 */
2259static void
2260bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2261{
8f15ea42 2262 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2263
2264 /*max_pending - the maximum-sized FIFO we allow */
2265 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2266 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2267 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2268 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2269}
2270
2271/*
2272 * bdx_set_ringparam - set ring sizes
2273 * @netdev
2274 * @ring
2275 */
2276static int
2277bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2278{
8f15ea42 2279 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2280 int rx_size = 0;
2281 int tx_size = 0;
2282
2283 for (; rx_size < 4; rx_size++) {
2284 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2285 break;
2286 }
2287 if (rx_size == 4)
2288 rx_size = 3;
2289
2290 for (; tx_size < 4; tx_size++) {
2291 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2292 break;
2293 }
2294 if (tx_size == 4)
2295 tx_size = 3;
2296
2297 /*Is there anything to do? */
8e95a202
JP		 2298 if ((rx_size == priv->rxf_size) &&
2299 (tx_size == priv->txd_size))
1a348ccc
AG		 2300 return 0;
2301
2302 priv->rxf_size = rx_size;
2303 if (rx_size > 1)
2304 priv->rxd_size = rx_size - 1;
2305 else
2306 priv->rxd_size = rx_size;
2307
2308 priv->txf_size = priv->txd_size = tx_size;
2309
2310 if (netif_running(netdev)) {
2311 bdx_close(netdev);
2312 bdx_open(netdev);
2313 }
2314 return 0;
2315}
2316
2317/*
2318 * bdx_get_strings - return a set of strings that describe the requested objects
2319 * @netdev
2320 * @data
2321 */
2322static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2323{
2324 switch (stringset) {
1a348ccc
AG		 2325 case ETH_SS_STATS:
2326 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2327 break;
2328 }
2329}
2330
2331/*
1ddee09f 2332 * bdx_get_sset_count - return number of statistics or tests
1a348ccc
AG		 2333 * @netdev
2334 */
1ddee09f 2335static int bdx_get_sset_count(struct net_device *netdev, int stringset)
1a348ccc 2336{
8f15ea42 2337 struct bdx_priv *priv = netdev_priv(netdev);
1ddee09f
BH		 2338
2339 switch (stringset) {
2340 case ETH_SS_STATS:
2341 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2342 != sizeof(struct bdx_stats) / sizeof(u64));
249658d5 2343 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
1ddee09f 2344 }
249658d5
JP		 2345
2346 return -EINVAL;
1a348ccc
AG		 2347}
2348
2349/*
2350 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2351 * @netdev
2352 * @stats
2353 * @data
2354 */
2355static void bdx_get_ethtool_stats(struct net_device *netdev,
2356 struct ethtool_stats *stats, u64 *data)
2357{
8f15ea42 2358 struct bdx_priv *priv = netdev_priv(netdev);
1a348ccc
AG		 2359
2360 if (priv->stats_flag) {
2361
2362 /* Update stats from HW */
2363 bdx_update_stats(priv);
2364
2365 /* Copy data to user buffer */
2366 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2367 }
2368}
2369
2370/*
c061b18d 2371 * bdx_set_ethtool_ops - ethtool interface implementation
1a348ccc
AG		 2372 * @netdev
2373 */
c061b18d 2374static void bdx_set_ethtool_ops(struct net_device *netdev)
1a348ccc 2375{
0fc0b732 2376 static const struct ethtool_ops bdx_ethtool_ops = {
1a348ccc
AG		 2377 .get_drvinfo = bdx_get_drvinfo,
2378 .get_link = ethtool_op_get_link,
2379 .get_coalesce = bdx_get_coalesce,
2380 .set_coalesce = bdx_set_coalesce,
2381 .get_ringparam = bdx_get_ringparam,
2382 .set_ringparam = bdx_set_ringparam,
1a348ccc 2383 .get_strings = bdx_get_strings,
1ddee09f 2384 .get_sset_count = bdx_get_sset_count,
1a348ccc 2385 .get_ethtool_stats = bdx_get_ethtool_stats,
86573f61 2386 .get_link_ksettings = bdx_get_link_ksettings,
1a348ccc
AG		 2387 };
2388
7ad24ea4 2389 netdev->ethtool_ops = &bdx_ethtool_ops;
1a348ccc
AG		 2390}
2391
2392/**
2393 * bdx_remove - Device Removal Routine
2394 * @pdev: PCI device information struct
2395 *
2396 * bdx_remove is called by the PCI subsystem to alert the driver
2397 * that it should release a PCI device. The could be caused by a
2398 * Hot-Plug event, or because the driver is going to be removed from
2399 * memory.
2400 **/
17abe3e4 2401static void bdx_remove(struct pci_dev *pdev)
1a348ccc
AG		 2402{
2403 struct pci_nic *nic = pci_get_drvdata(pdev);
2404 struct net_device *ndev;
2405 int port;
2406
2407 for (port = 0; port < nic->port_num; port++) {
2408 ndev = nic->priv[port]->ndev;
2409 unregister_netdev(ndev);
2410 free_netdev(ndev);
2411 }
2412
2413 /*bdx_hw_reset_direct(nic->regs); */
2414#ifdef BDX_MSI
2415 if (nic->irq_type == IRQ_MSI)
2416 pci_disable_msi(pdev);
2417#endif
2418
2419 iounmap(nic->regs);
2420 pci_release_regions(pdev);
2421 pci_disable_device(pdev);
1a348ccc
AG		 2422 vfree(nic);
2423
2424 RET();
2425}
2426
2427static struct pci_driver bdx_pci_driver = {
2428 .name = BDX_DRV_NAME,
2429 .id_table = bdx_pci_tbl,
2430 .probe = bdx_probe,
17abe3e4 2431 .remove = bdx_remove,
1a348ccc
AG		 2432};
2433
2434/*
2435 * print_driver_id - print parameters of the driver build
2436 */
2437static void __init print_driver_id(void)
2438{
865a21a5
JP		 2439 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2440 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
1a348ccc
AG		 2441}
2442
2443static int __init bdx_module_init(void)
2444{
2445 ENTER;
1a348ccc
AG		 2446 init_txd_sizes();
2447 print_driver_id();
2448 RET(pci_register_driver(&bdx_pci_driver));
2449}
2450
2451module_init(bdx_module_init);
2452
2453static void __exit bdx_module_exit(void)
2454{
2455 ENTER;
2456 pci_unregister_driver(&bdx_pci_driver);
2457 RET();
2458}
2459
2460module_exit(bdx_module_exit);
2461
2462MODULE_LICENSE("GPL");
2463MODULE_AUTHOR(DRIVER_AUTHOR);
2464MODULE_DESCRIPTION(BDX_DRV_DESC);
46814e08 2465MODULE_FIRMWARE("tehuti/bdx.bin");
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