[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / ti / cpsw-phy-sel.c

// SPDX-License-Identifier: GPL-2.0
/* Texas Instruments Ethernet Switch Driver
 *
 * Copyright (C) 2013 Texas Instruments
 *
 * Module Author: Mugunthan V N <mugunthanvnm@ti.com>
 *
 */

#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include "cpsw.h"

/* AM33xx SoC specific definitions for the CONTROL port */
#define AM33XX_GMII_SEL_MODE_MII	0
#define AM33XX_GMII_SEL_MODE_RMII	1
#define AM33XX_GMII_SEL_MODE_RGMII	2

#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN	BIT(7)
#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN	BIT(6)
#define AM33XX_GMII_SEL_RGMII2_IDMODE	BIT(5)
#define AM33XX_GMII_SEL_RGMII1_IDMODE	BIT(4)

#define GMII_SEL_MODE_MASK		0x3

struct cpsw_phy_sel_priv {
	struct device	*dev;
	u32 __iomem	*gmii_sel;
	bool		rmii_clock_external;
	void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
			     phy_interface_t phy_mode, int slave);
};


static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
				 phy_interface_t phy_mode, int slave)
{
	u32 reg;
	u32 mask;
	u32 mode = 0;
	bool rgmii_id = false;

	reg = readl(priv->gmii_sel);

	switch (phy_mode) {
	case PHY_INTERFACE_MODE_RMII:
		mode = AM33XX_GMII_SEL_MODE_RMII;
		break;

	case PHY_INTERFACE_MODE_RGMII:
		mode = AM33XX_GMII_SEL_MODE_RGMII;
		break;

	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		mode = AM33XX_GMII_SEL_MODE_RGMII;
		rgmii_id = true;
		break;

	default:
		dev_warn(priv->dev,
			 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
			phy_modes(phy_mode));
		fallthrough;
	case PHY_INTERFACE_MODE_MII:
		mode = AM33XX_GMII_SEL_MODE_MII;
		break;
	}

	mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
	mask |= BIT(slave + 4);
	mode <<= slave * 2;

	if (priv->rmii_clock_external) {
		if (slave == 0)
			mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
		else
			mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
	}

	if (rgmii_id) {
		if (slave == 0)
			mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
		else
			mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
	}

	reg &= ~mask;
	reg |= mode;

	writel(reg, priv->gmii_sel);
}

static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
				 phy_interface_t phy_mode, int slave)
{
	u32 reg;
	u32 mask;
	u32 mode = 0;

	reg = readl(priv->gmii_sel);

	switch (phy_mode) {
	case PHY_INTERFACE_MODE_RMII:
		mode = AM33XX_GMII_SEL_MODE_RMII;
		break;

	case PHY_INTERFACE_MODE_RGMII:
	case PHY_INTERFACE_MODE_RGMII_ID:
	case PHY_INTERFACE_MODE_RGMII_RXID:
	case PHY_INTERFACE_MODE_RGMII_TXID:
		mode = AM33XX_GMII_SEL_MODE_RGMII;
		break;

	default:
		dev_warn(priv->dev,
			 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
			phy_modes(phy_mode));
		fallthrough;
	case PHY_INTERFACE_MODE_MII:
		mode = AM33XX_GMII_SEL_MODE_MII;
		break;
	}

	switch (slave) {
	case 0:
		mask = GMII_SEL_MODE_MASK;
		break;
	case 1:
		mask = GMII_SEL_MODE_MASK << 4;
		mode <<= 4;
		break;
	default:
		dev_err(priv->dev, "invalid slave number...\n");
		return;
	}

	if (priv->rmii_clock_external)
		dev_err(priv->dev, "RMII External clock is not supported\n");

	reg &= ~mask;
	reg |= mode;

	writel(reg, priv->gmii_sel);
}

static struct platform_driver cpsw_phy_sel_driver;
static int match(struct device *dev, const void *data)
{
	const struct device_node *node = (const struct device_node *)data;
	return dev->of_node == node &&
		dev->driver == &cpsw_phy_sel_driver.driver;
}

void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
{
	struct device_node *node;
	struct cpsw_phy_sel_priv *priv;

	node = of_parse_phandle(dev->of_node, "cpsw-phy-sel", 0);
	if (!node) {
		node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
		if (!node) {
			dev_err(dev, "Phy mode driver DT not found\n");
			return;
		}
	}

	dev = bus_find_device(&platform_bus_type, NULL, node, match);
	if (!dev) {
		dev_err(dev, "unable to find platform device for %pOF\n", node);
		goto out;
	}

	priv = dev_get_drvdata(dev);

	priv->cpsw_phy_sel(priv, phy_mode, slave);

	put_device(dev);
out:
	of_node_put(node);
}
EXPORT_SYMBOL_GPL(cpsw_phy_sel);

static const struct of_device_id cpsw_phy_sel_id_table[] = {
	{
		.compatible	= "ti,am3352-cpsw-phy-sel",
		.data		= &cpsw_gmii_sel_am3352,
	},
	{
		.compatible	= "ti,dra7xx-cpsw-phy-sel",
		.data		= &cpsw_gmii_sel_dra7xx,
	},
	{
		.compatible	= "ti,am43xx-cpsw-phy-sel",
		.data		= &cpsw_gmii_sel_am3352,
	},
	{}
};

static int cpsw_phy_sel_probe(struct platform_device *pdev)
{
	struct resource	*res;
	const struct of_device_id *of_id;
	struct cpsw_phy_sel_priv *priv;

	of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
	if (!of_id)
		return -EINVAL;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
		return -ENOMEM;
	}

	priv->dev = &pdev->dev;
	priv->cpsw_phy_sel = of_id->data;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
	priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->gmii_sel))
		return PTR_ERR(priv->gmii_sel);

	if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
		priv->rmii_clock_external = true;

	dev_set_drvdata(&pdev->dev, priv);

	return 0;
}

static struct platform_driver cpsw_phy_sel_driver = {
	.probe		= cpsw_phy_sel_probe,
	.driver		= {
		.name	= "cpsw-phy-sel",
		.of_match_table = cpsw_phy_sel_id_table,
	},
};
builtin_platform_driver(cpsw_phy_sel_driver);
Commit	Line	Data
68cf027f	1	// SPDX-License-Identifier: GPL-2.0
5892cd13 M	2	/* Texas Instruments Ethernet Switch Driver
	3	*
	4	* Copyright (C) 2013 Texas Instruments
	5	*
b3c8ec35 PG	6	* Module Author: Mugunthan V N <mugunthanvnm@ti.com>
b3c8ec35 PG	7	*
5892cd13 M	8	*/
	9
	10	#include <linux/platform_device.h>
b3c8ec35	11	#include <linux/init.h>
5892cd13 M	12	#include <linux/netdevice.h>
	13	#include <linux/phy.h>
	14	#include <linux/of.h>
	15	#include <linux/of_device.h>
	16
	17	#include "cpsw.h"
	18
	19	/* AM33xx SoC specific definitions for the CONTROL port */
	20	#define AM33XX_GMII_SEL_MODE_MII 0
	21	#define AM33XX_GMII_SEL_MODE_RMII 1
	22	#define AM33XX_GMII_SEL_MODE_RGMII 2
	23
	24	#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
	25	#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
0fb26c30 M	26	#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
0fb26c30 M	27	#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
5892cd13	28
d415fa1b M	29	#define GMII_SEL_MODE_MASK 0x3
d415fa1b M	30
5892cd13 M	31	struct cpsw_phy_sel_priv {
	32	struct device *dev;
	33	u32 __iomem *gmii_sel;
	34	bool rmii_clock_external;
	35	void (cpsw_phy_sel)(struct cpsw_phy_sel_priv priv,
	36	phy_interface_t phy_mode, int slave);
	37	};
	38
	39
	40	static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
	41	phy_interface_t phy_mode, int slave)
	42	{
	43	u32 reg;
	44	u32 mask;
	45	u32 mode = 0;
0fb26c30	46	bool rgmii_id = false;
5892cd13 M	47
	48	reg = readl(priv->gmii_sel);
	49
	50	switch (phy_mode) {
	51	case PHY_INTERFACE_MODE_RMII:
	52	mode = AM33XX_GMII_SEL_MODE_RMII;
	53	break;
	54
	55	case PHY_INTERFACE_MODE_RGMII:
0fb26c30 M	56	mode = AM33XX_GMII_SEL_MODE_RGMII;
	57	break;
	58
5892cd13 M	59	case PHY_INTERFACE_MODE_RGMII_ID:
	60	case PHY_INTERFACE_MODE_RGMII_RXID:
	61	case PHY_INTERFACE_MODE_RGMII_TXID:
	62	mode = AM33XX_GMII_SEL_MODE_RGMII;
0fb26c30	63	rgmii_id = true;
5892cd13 M	64	break;
5892cd13 M	65
5892cd13	66	default:
d148bbd3 DR	67	dev_warn(priv->dev,
	68	"Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
	69	phy_modes(phy_mode));
df561f66	70	fallthrough;
d148bbd3	71	case PHY_INTERFACE_MODE_MII:
5892cd13 M	72	mode = AM33XX_GMII_SEL_MODE_MII;
5892cd13 M	73	break;
5c423d71	74	}
5892cd13	75
d415fa1b	76	mask = GMII_SEL_MODE_MASK << (slave * 2) \| BIT(slave + 6);
74685b08	77	mask \|= BIT(slave + 4);
5892cd13 M	78	mode <<= slave * 2;
	79
	80	if (priv->rmii_clock_external) {
	81	if (slave == 0)
	82	mode \|= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
	83	else
	84	mode \|= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
	85	}
	86
0fb26c30 M	87	if (rgmii_id) {
	88	if (slave == 0)
	89	mode \|= AM33XX_GMII_SEL_RGMII1_IDMODE;
	90	else
	91	mode \|= AM33XX_GMII_SEL_RGMII2_IDMODE;
	92	}
	93
5892cd13 M	94	reg &= ~mask;
	95	reg \|= mode;
	96
	97	writel(reg, priv->gmii_sel);
	98	}
	99
d415fa1b M	100	static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
	101	phy_interface_t phy_mode, int slave)
	102	{
	103	u32 reg;
	104	u32 mask;
	105	u32 mode = 0;
	106
	107	reg = readl(priv->gmii_sel);
	108
	109	switch (phy_mode) {
	110	case PHY_INTERFACE_MODE_RMII:
	111	mode = AM33XX_GMII_SEL_MODE_RMII;
	112	break;
	113
	114	case PHY_INTERFACE_MODE_RGMII:
	115	case PHY_INTERFACE_MODE_RGMII_ID:
	116	case PHY_INTERFACE_MODE_RGMII_RXID:
	117	case PHY_INTERFACE_MODE_RGMII_TXID:
	118	mode = AM33XX_GMII_SEL_MODE_RGMII;
	119	break;
	120
d415fa1b	121	default:
d148bbd3 DR	122	dev_warn(priv->dev,
	123	"Unsupported PHY mode: \"%s\". Defaulting to MII.\n",
	124	phy_modes(phy_mode));
df561f66	125	fallthrough;
d148bbd3	126	case PHY_INTERFACE_MODE_MII:
d415fa1b M	127	mode = AM33XX_GMII_SEL_MODE_MII;
d415fa1b M	128	break;
5c423d71	129	}
d415fa1b M	130
	131	switch (slave) {
	132	case 0:
	133	mask = GMII_SEL_MODE_MASK;
	134	break;
	135	case 1:
	136	mask = GMII_SEL_MODE_MASK << 4;
	137	mode <<= 4;
	138	break;
	139	default:
	140	dev_err(priv->dev, "invalid slave number...\n");
	141	return;
	142	}
	143
	144	if (priv->rmii_clock_external)
	145	dev_err(priv->dev, "RMII External clock is not supported\n");
	146
	147	reg &= ~mask;
	148	reg \|= mode;
	149
	150	writel(reg, priv->gmii_sel);
	151	}
	152
5892cd13	153	static struct platform_driver cpsw_phy_sel_driver;
418e3ea1	154	static int match(struct device dev, const void data)
5892cd13	155	{
418e3ea1	156	const struct device_node node = (const struct device_node )data;
5892cd13 M	157	return dev->of_node == node &&
	158	dev->driver == &cpsw_phy_sel_driver.driver;
	159	}
	160
	161	void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
	162	{
	163	struct device_node *node;
	164	struct cpsw_phy_sel_priv *priv;
	165
18eb8aea	166	node = of_parse_phandle(dev->of_node, "cpsw-phy-sel", 0);
5892cd13	167	if (!node) {
18eb8aea TL	168	node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
	169	if (!node) {
	170	dev_err(dev, "Phy mode driver DT not found\n");
	171	return;
	172	}
5892cd13 M	173	}
	174
	175	dev = bus_find_device(&platform_bus_type, NULL, node, match);
c6213eb1 GS	176	if (!dev) {
	177	dev_err(dev, "unable to find platform device for %pOF\n", node);
	178	goto out;
	179	}
	180
5892cd13 M	181	priv = dev_get_drvdata(dev);
	182
	183	priv->cpsw_phy_sel(priv, phy_mode, slave);
c7262aaa JH	184
c7262aaa JH	185	put_device(dev);
c6213eb1 GS	186	out:
c6213eb1 GS	187	of_node_put(node);
5892cd13 M	188	}
	189	EXPORT_SYMBOL_GPL(cpsw_phy_sel);
	190
	191	static const struct of_device_id cpsw_phy_sel_id_table[] = {
	192	{
	193	.compatible = "ti,am3352-cpsw-phy-sel",
	194	.data = &cpsw_gmii_sel_am3352,
	195	},
d415fa1b M	196	{
	197	.compatible = "ti,dra7xx-cpsw-phy-sel",
	198	.data = &cpsw_gmii_sel_dra7xx,
	199	},
b80b9309 M	200	{
	201	.compatible = "ti,am43xx-cpsw-phy-sel",
	202	.data = &cpsw_gmii_sel_am3352,
	203	},
5892cd13 M	204	{}
5892cd13 M	205	};
5892cd13 M	206
	207	static int cpsw_phy_sel_probe(struct platform_device *pdev)
	208	{
	209	struct resource *res;
	210	const struct of_device_id *of_id;
	211	struct cpsw_phy_sel_priv *priv;
	212
	213	of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
	214	if (!of_id)
	215	return -EINVAL;
	216
	217	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	218	if (!priv) {
	219	dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
	220	return -ENOMEM;
	221	}
	222
84ef36bd	223	priv->dev = &pdev->dev;
5892cd13 M	224	priv->cpsw_phy_sel = of_id->data;
	225
	226	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
	227	priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
	228	if (IS_ERR(priv->gmii_sel))
	229	return PTR_ERR(priv->gmii_sel);
	230
	231	if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
	232	priv->rmii_clock_external = true;
	233
	234	dev_set_drvdata(&pdev->dev, priv);
	235
	236	return 0;
	237	}
	238
	239	static struct platform_driver cpsw_phy_sel_driver = {
	240	.probe = cpsw_phy_sel_probe,
	241	.driver = {
	242	.name = "cpsw-phy-sel",
2afc6dff	243	.of_match_table = cpsw_phy_sel_id_table,
5892cd13 M	244	},
5892cd13 M	245	};
b3c8ec35	246	builtin_platform_driver(cpsw_phy_sel_driver);