]>
Commit | Line | Data |
---|---|---|
df828598 M |
1 | /* |
2 | * Texas Instruments Ethernet Switch Driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/timer.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/irqreturn.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/netdevice.h> | |
2e5b38ab | 27 | #include <linux/net_tstamp.h> |
df828598 M |
28 | #include <linux/phy.h> |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/delay.h> | |
f150bd7f | 31 | #include <linux/pm_runtime.h> |
2eb32b0a M |
32 | #include <linux/of.h> |
33 | #include <linux/of_net.h> | |
34 | #include <linux/of_device.h> | |
df828598 M |
35 | |
36 | #include <linux/platform_data/cpsw.h> | |
37 | ||
38 | #include "cpsw_ale.h" | |
2e5b38ab | 39 | #include "cpts.h" |
df828598 M |
40 | #include "davinci_cpdma.h" |
41 | ||
42 | #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ | |
43 | NETIF_MSG_DRV | NETIF_MSG_LINK | \ | |
44 | NETIF_MSG_IFUP | NETIF_MSG_INTR | \ | |
45 | NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ | |
46 | NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ | |
47 | NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ | |
48 | NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ | |
49 | NETIF_MSG_RX_STATUS) | |
50 | ||
51 | #define cpsw_info(priv, type, format, ...) \ | |
52 | do { \ | |
53 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
54 | dev_info(priv->dev, format, ## __VA_ARGS__); \ | |
55 | } while (0) | |
56 | ||
57 | #define cpsw_err(priv, type, format, ...) \ | |
58 | do { \ | |
59 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
60 | dev_err(priv->dev, format, ## __VA_ARGS__); \ | |
61 | } while (0) | |
62 | ||
63 | #define cpsw_dbg(priv, type, format, ...) \ | |
64 | do { \ | |
65 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
66 | dev_dbg(priv->dev, format, ## __VA_ARGS__); \ | |
67 | } while (0) | |
68 | ||
69 | #define cpsw_notice(priv, type, format, ...) \ | |
70 | do { \ | |
71 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
72 | dev_notice(priv->dev, format, ## __VA_ARGS__); \ | |
73 | } while (0) | |
74 | ||
5c50a856 M |
75 | #define ALE_ALL_PORTS 0x7 |
76 | ||
df828598 M |
77 | #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) |
78 | #define CPSW_MINOR_VERSION(reg) (reg & 0xff) | |
79 | #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) | |
80 | ||
e90cfac6 RC |
81 | #define CPSW_VERSION_1 0x19010a |
82 | #define CPSW_VERSION_2 0x19010c | |
549985ee RC |
83 | |
84 | #define HOST_PORT_NUM 0 | |
85 | #define SLIVER_SIZE 0x40 | |
86 | ||
87 | #define CPSW1_HOST_PORT_OFFSET 0x028 | |
88 | #define CPSW1_SLAVE_OFFSET 0x050 | |
89 | #define CPSW1_SLAVE_SIZE 0x040 | |
90 | #define CPSW1_CPDMA_OFFSET 0x100 | |
91 | #define CPSW1_STATERAM_OFFSET 0x200 | |
92 | #define CPSW1_CPTS_OFFSET 0x500 | |
93 | #define CPSW1_ALE_OFFSET 0x600 | |
94 | #define CPSW1_SLIVER_OFFSET 0x700 | |
95 | ||
96 | #define CPSW2_HOST_PORT_OFFSET 0x108 | |
97 | #define CPSW2_SLAVE_OFFSET 0x200 | |
98 | #define CPSW2_SLAVE_SIZE 0x100 | |
99 | #define CPSW2_CPDMA_OFFSET 0x800 | |
100 | #define CPSW2_STATERAM_OFFSET 0xa00 | |
101 | #define CPSW2_CPTS_OFFSET 0xc00 | |
102 | #define CPSW2_ALE_OFFSET 0xd00 | |
103 | #define CPSW2_SLIVER_OFFSET 0xd80 | |
104 | #define CPSW2_BD_OFFSET 0x2000 | |
105 | ||
df828598 M |
106 | #define CPDMA_RXTHRESH 0x0c0 |
107 | #define CPDMA_RXFREE 0x0e0 | |
108 | #define CPDMA_TXHDP 0x00 | |
109 | #define CPDMA_RXHDP 0x20 | |
110 | #define CPDMA_TXCP 0x40 | |
111 | #define CPDMA_RXCP 0x60 | |
112 | ||
df828598 M |
113 | #define CPSW_POLL_WEIGHT 64 |
114 | #define CPSW_MIN_PACKET_SIZE 60 | |
115 | #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) | |
116 | ||
117 | #define RX_PRIORITY_MAPPING 0x76543210 | |
118 | #define TX_PRIORITY_MAPPING 0x33221100 | |
119 | #define CPDMA_TX_PRIORITY_MAP 0x76543210 | |
120 | ||
121 | #define cpsw_enable_irq(priv) \ | |
122 | do { \ | |
123 | u32 i; \ | |
124 | for (i = 0; i < priv->num_irqs; i++) \ | |
125 | enable_irq(priv->irqs_table[i]); \ | |
126 | } while (0); | |
127 | #define cpsw_disable_irq(priv) \ | |
128 | do { \ | |
129 | u32 i; \ | |
130 | for (i = 0; i < priv->num_irqs; i++) \ | |
131 | disable_irq_nosync(priv->irqs_table[i]); \ | |
132 | } while (0); | |
133 | ||
134 | static int debug_level; | |
135 | module_param(debug_level, int, 0); | |
136 | MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); | |
137 | ||
138 | static int ale_ageout = 10; | |
139 | module_param(ale_ageout, int, 0); | |
140 | MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); | |
141 | ||
142 | static int rx_packet_max = CPSW_MAX_PACKET_SIZE; | |
143 | module_param(rx_packet_max, int, 0); | |
144 | MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); | |
145 | ||
996a5c27 | 146 | struct cpsw_wr_regs { |
df828598 M |
147 | u32 id_ver; |
148 | u32 soft_reset; | |
149 | u32 control; | |
150 | u32 int_control; | |
151 | u32 rx_thresh_en; | |
152 | u32 rx_en; | |
153 | u32 tx_en; | |
154 | u32 misc_en; | |
155 | }; | |
156 | ||
996a5c27 | 157 | struct cpsw_ss_regs { |
df828598 M |
158 | u32 id_ver; |
159 | u32 control; | |
160 | u32 soft_reset; | |
161 | u32 stat_port_en; | |
162 | u32 ptype; | |
bd357af2 RC |
163 | u32 soft_idle; |
164 | u32 thru_rate; | |
165 | u32 gap_thresh; | |
166 | u32 tx_start_wds; | |
167 | u32 flow_control; | |
168 | u32 vlan_ltype; | |
169 | u32 ts_ltype; | |
170 | u32 dlr_ltype; | |
df828598 M |
171 | }; |
172 | ||
9750a3ad RC |
173 | /* CPSW_PORT_V1 */ |
174 | #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ | |
175 | #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ | |
176 | #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ | |
177 | #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ | |
178 | #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ | |
179 | #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ | |
180 | #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ | |
181 | #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ | |
182 | ||
183 | /* CPSW_PORT_V2 */ | |
184 | #define CPSW2_CONTROL 0x00 /* Control Register */ | |
185 | #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ | |
186 | #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ | |
187 | #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ | |
188 | #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ | |
189 | #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ | |
190 | #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ | |
191 | ||
192 | /* CPSW_PORT_V1 and V2 */ | |
193 | #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ | |
194 | #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ | |
195 | #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ | |
196 | ||
197 | /* CPSW_PORT_V2 only */ | |
198 | #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ | |
199 | #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ | |
200 | #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ | |
201 | #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ | |
202 | #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ | |
203 | #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ | |
204 | #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ | |
205 | #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ | |
206 | ||
207 | /* Bit definitions for the CPSW2_CONTROL register */ | |
208 | #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ | |
209 | #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ | |
210 | #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ | |
211 | #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ | |
212 | #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ | |
213 | #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ | |
214 | #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ | |
215 | #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ | |
216 | #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ | |
217 | #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ | |
218 | #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ | |
219 | #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ | |
220 | #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ | |
221 | #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ | |
222 | #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ | |
223 | #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ | |
224 | ||
225 | #define CTRL_TS_BITS \ | |
226 | (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ | |
227 | TS_ANNEX_D_EN | TS_LTYPE1_EN) | |
228 | ||
229 | #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) | |
230 | #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) | |
231 | #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) | |
232 | ||
233 | /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ | |
234 | #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ | |
235 | #define TS_SEQ_ID_OFFSET_MASK (0x3f) | |
236 | #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ | |
237 | #define TS_MSG_TYPE_EN_MASK (0xffff) | |
238 | ||
239 | /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ | |
240 | #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) | |
df828598 | 241 | |
2e5b38ab RC |
242 | /* Bit definitions for the CPSW1_TS_CTL register */ |
243 | #define CPSW_V1_TS_RX_EN BIT(0) | |
244 | #define CPSW_V1_TS_TX_EN BIT(4) | |
245 | #define CPSW_V1_MSG_TYPE_OFS 16 | |
246 | ||
247 | /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ | |
248 | #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 | |
249 | ||
df828598 M |
250 | struct cpsw_host_regs { |
251 | u32 max_blks; | |
252 | u32 blk_cnt; | |
253 | u32 flow_thresh; | |
254 | u32 port_vlan; | |
255 | u32 tx_pri_map; | |
256 | u32 cpdma_tx_pri_map; | |
257 | u32 cpdma_rx_chan_map; | |
258 | }; | |
259 | ||
260 | struct cpsw_sliver_regs { | |
261 | u32 id_ver; | |
262 | u32 mac_control; | |
263 | u32 mac_status; | |
264 | u32 soft_reset; | |
265 | u32 rx_maxlen; | |
266 | u32 __reserved_0; | |
267 | u32 rx_pause; | |
268 | u32 tx_pause; | |
269 | u32 __reserved_1; | |
270 | u32 rx_pri_map; | |
271 | }; | |
272 | ||
273 | struct cpsw_slave { | |
9750a3ad | 274 | void __iomem *regs; |
df828598 M |
275 | struct cpsw_sliver_regs __iomem *sliver; |
276 | int slave_num; | |
277 | u32 mac_control; | |
278 | struct cpsw_slave_data *data; | |
279 | struct phy_device *phy; | |
280 | }; | |
281 | ||
9750a3ad RC |
282 | static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) |
283 | { | |
284 | return __raw_readl(slave->regs + offset); | |
285 | } | |
286 | ||
287 | static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) | |
288 | { | |
289 | __raw_writel(val, slave->regs + offset); | |
290 | } | |
291 | ||
df828598 M |
292 | struct cpsw_priv { |
293 | spinlock_t lock; | |
294 | struct platform_device *pdev; | |
295 | struct net_device *ndev; | |
296 | struct resource *cpsw_res; | |
a65dd5b2 | 297 | struct resource *cpsw_wr_res; |
df828598 M |
298 | struct napi_struct napi; |
299 | struct device *dev; | |
300 | struct cpsw_platform_data data; | |
996a5c27 RC |
301 | struct cpsw_ss_regs __iomem *regs; |
302 | struct cpsw_wr_regs __iomem *wr_regs; | |
df828598 M |
303 | struct cpsw_host_regs __iomem *host_port_regs; |
304 | u32 msg_enable; | |
e90cfac6 | 305 | u32 version; |
df828598 M |
306 | struct net_device_stats stats; |
307 | int rx_packet_max; | |
308 | int host_port; | |
309 | struct clk *clk; | |
310 | u8 mac_addr[ETH_ALEN]; | |
311 | struct cpsw_slave *slaves; | |
312 | struct cpdma_ctlr *dma; | |
313 | struct cpdma_chan *txch, *rxch; | |
314 | struct cpsw_ale *ale; | |
315 | /* snapshot of IRQ numbers */ | |
316 | u32 irqs_table[4]; | |
317 | u32 num_irqs; | |
2e5b38ab | 318 | struct cpts cpts; |
df828598 M |
319 | }; |
320 | ||
321 | #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) | |
322 | #define for_each_slave(priv, func, arg...) \ | |
323 | do { \ | |
324 | int idx; \ | |
325 | for (idx = 0; idx < (priv)->data.slaves; idx++) \ | |
326 | (func)((priv)->slaves + idx, ##arg); \ | |
327 | } while (0) | |
328 | ||
5c50a856 M |
329 | static void cpsw_ndo_set_rx_mode(struct net_device *ndev) |
330 | { | |
331 | struct cpsw_priv *priv = netdev_priv(ndev); | |
332 | ||
333 | if (ndev->flags & IFF_PROMISC) { | |
334 | /* Enable promiscuous mode */ | |
335 | dev_err(priv->dev, "Ignoring Promiscuous mode\n"); | |
336 | return; | |
337 | } | |
338 | ||
339 | /* Clear all mcast from ALE */ | |
340 | cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); | |
341 | ||
342 | if (!netdev_mc_empty(ndev)) { | |
343 | struct netdev_hw_addr *ha; | |
344 | ||
345 | /* program multicast address list into ALE register */ | |
346 | netdev_for_each_mc_addr(ha, ndev) { | |
347 | cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr, | |
348 | ALE_ALL_PORTS << priv->host_port, 0, 0); | |
349 | } | |
350 | } | |
351 | } | |
352 | ||
df828598 M |
353 | static void cpsw_intr_enable(struct cpsw_priv *priv) |
354 | { | |
996a5c27 RC |
355 | __raw_writel(0xFF, &priv->wr_regs->tx_en); |
356 | __raw_writel(0xFF, &priv->wr_regs->rx_en); | |
df828598 M |
357 | |
358 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
359 | return; | |
360 | } | |
361 | ||
362 | static void cpsw_intr_disable(struct cpsw_priv *priv) | |
363 | { | |
996a5c27 RC |
364 | __raw_writel(0, &priv->wr_regs->tx_en); |
365 | __raw_writel(0, &priv->wr_regs->rx_en); | |
df828598 M |
366 | |
367 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
368 | return; | |
369 | } | |
370 | ||
371 | void cpsw_tx_handler(void *token, int len, int status) | |
372 | { | |
373 | struct sk_buff *skb = token; | |
374 | struct net_device *ndev = skb->dev; | |
375 | struct cpsw_priv *priv = netdev_priv(ndev); | |
376 | ||
377 | if (unlikely(netif_queue_stopped(ndev))) | |
378 | netif_start_queue(ndev); | |
2e5b38ab | 379 | cpts_tx_timestamp(&priv->cpts, skb); |
df828598 M |
380 | priv->stats.tx_packets++; |
381 | priv->stats.tx_bytes += len; | |
382 | dev_kfree_skb_any(skb); | |
383 | } | |
384 | ||
385 | void cpsw_rx_handler(void *token, int len, int status) | |
386 | { | |
387 | struct sk_buff *skb = token; | |
388 | struct net_device *ndev = skb->dev; | |
389 | struct cpsw_priv *priv = netdev_priv(ndev); | |
390 | int ret = 0; | |
391 | ||
392 | /* free and bail if we are shutting down */ | |
393 | if (unlikely(!netif_running(ndev)) || | |
394 | unlikely(!netif_carrier_ok(ndev))) { | |
395 | dev_kfree_skb_any(skb); | |
396 | return; | |
397 | } | |
398 | if (likely(status >= 0)) { | |
399 | skb_put(skb, len); | |
2e5b38ab | 400 | cpts_rx_timestamp(&priv->cpts, skb); |
df828598 M |
401 | skb->protocol = eth_type_trans(skb, ndev); |
402 | netif_receive_skb(skb); | |
403 | priv->stats.rx_bytes += len; | |
404 | priv->stats.rx_packets++; | |
405 | skb = NULL; | |
406 | } | |
407 | ||
408 | if (unlikely(!netif_running(ndev))) { | |
409 | if (skb) | |
410 | dev_kfree_skb_any(skb); | |
411 | return; | |
412 | } | |
413 | ||
414 | if (likely(!skb)) { | |
415 | skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); | |
416 | if (WARN_ON(!skb)) | |
417 | return; | |
418 | ||
419 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, | |
420 | skb_tailroom(skb), GFP_KERNEL); | |
421 | } | |
422 | WARN_ON(ret < 0); | |
423 | } | |
424 | ||
425 | static irqreturn_t cpsw_interrupt(int irq, void *dev_id) | |
426 | { | |
427 | struct cpsw_priv *priv = dev_id; | |
428 | ||
429 | if (likely(netif_running(priv->ndev))) { | |
430 | cpsw_intr_disable(priv); | |
431 | cpsw_disable_irq(priv); | |
432 | napi_schedule(&priv->napi); | |
433 | } | |
434 | return IRQ_HANDLED; | |
435 | } | |
436 | ||
437 | static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) | |
438 | { | |
439 | if (priv->host_port == 0) | |
440 | return slave_num + 1; | |
441 | else | |
442 | return slave_num; | |
443 | } | |
444 | ||
445 | static int cpsw_poll(struct napi_struct *napi, int budget) | |
446 | { | |
447 | struct cpsw_priv *priv = napi_to_priv(napi); | |
448 | int num_tx, num_rx; | |
449 | ||
450 | num_tx = cpdma_chan_process(priv->txch, 128); | |
451 | num_rx = cpdma_chan_process(priv->rxch, budget); | |
452 | ||
453 | if (num_rx || num_tx) | |
454 | cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", | |
455 | num_rx, num_tx); | |
456 | ||
457 | if (num_rx < budget) { | |
458 | napi_complete(napi); | |
459 | cpsw_intr_enable(priv); | |
460 | cpdma_ctlr_eoi(priv->dma); | |
461 | cpsw_enable_irq(priv); | |
462 | } | |
463 | ||
464 | return num_rx; | |
465 | } | |
466 | ||
467 | static inline void soft_reset(const char *module, void __iomem *reg) | |
468 | { | |
469 | unsigned long timeout = jiffies + HZ; | |
470 | ||
471 | __raw_writel(1, reg); | |
472 | do { | |
473 | cpu_relax(); | |
474 | } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); | |
475 | ||
476 | WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); | |
477 | } | |
478 | ||
479 | #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ | |
480 | ((mac)[2] << 16) | ((mac)[3] << 24)) | |
481 | #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) | |
482 | ||
483 | static void cpsw_set_slave_mac(struct cpsw_slave *slave, | |
484 | struct cpsw_priv *priv) | |
485 | { | |
9750a3ad RC |
486 | slave_write(slave, mac_hi(priv->mac_addr), SA_HI); |
487 | slave_write(slave, mac_lo(priv->mac_addr), SA_LO); | |
df828598 M |
488 | } |
489 | ||
490 | static void _cpsw_adjust_link(struct cpsw_slave *slave, | |
491 | struct cpsw_priv *priv, bool *link) | |
492 | { | |
493 | struct phy_device *phy = slave->phy; | |
494 | u32 mac_control = 0; | |
495 | u32 slave_port; | |
496 | ||
497 | if (!phy) | |
498 | return; | |
499 | ||
500 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
501 | ||
502 | if (phy->link) { | |
503 | mac_control = priv->data.mac_control; | |
504 | ||
505 | /* enable forwarding */ | |
506 | cpsw_ale_control_set(priv->ale, slave_port, | |
507 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
508 | ||
509 | if (phy->speed == 1000) | |
510 | mac_control |= BIT(7); /* GIGABITEN */ | |
511 | if (phy->duplex) | |
512 | mac_control |= BIT(0); /* FULLDUPLEXEN */ | |
342b7b74 DM |
513 | |
514 | /* set speed_in input in case RMII mode is used in 100Mbps */ | |
515 | if (phy->speed == 100) | |
516 | mac_control |= BIT(15); | |
517 | ||
df828598 M |
518 | *link = true; |
519 | } else { | |
520 | mac_control = 0; | |
521 | /* disable forwarding */ | |
522 | cpsw_ale_control_set(priv->ale, slave_port, | |
523 | ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); | |
524 | } | |
525 | ||
526 | if (mac_control != slave->mac_control) { | |
527 | phy_print_status(phy); | |
528 | __raw_writel(mac_control, &slave->sliver->mac_control); | |
529 | } | |
530 | ||
531 | slave->mac_control = mac_control; | |
532 | } | |
533 | ||
534 | static void cpsw_adjust_link(struct net_device *ndev) | |
535 | { | |
536 | struct cpsw_priv *priv = netdev_priv(ndev); | |
537 | bool link = false; | |
538 | ||
539 | for_each_slave(priv, _cpsw_adjust_link, priv, &link); | |
540 | ||
541 | if (link) { | |
542 | netif_carrier_on(ndev); | |
543 | if (netif_running(ndev)) | |
544 | netif_wake_queue(ndev); | |
545 | } else { | |
546 | netif_carrier_off(ndev); | |
547 | netif_stop_queue(ndev); | |
548 | } | |
549 | } | |
550 | ||
551 | static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) | |
552 | { | |
553 | static char *leader = "........................................"; | |
554 | ||
555 | if (!val) | |
556 | return 0; | |
557 | else | |
558 | return snprintf(buf, maxlen, "%s %s %10d\n", name, | |
559 | leader + strlen(name), val); | |
560 | } | |
561 | ||
562 | static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) | |
563 | { | |
564 | char name[32]; | |
565 | u32 slave_port; | |
566 | ||
567 | sprintf(name, "slave-%d", slave->slave_num); | |
568 | ||
569 | soft_reset(name, &slave->sliver->soft_reset); | |
570 | ||
571 | /* setup priority mapping */ | |
572 | __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); | |
9750a3ad RC |
573 | |
574 | switch (priv->version) { | |
575 | case CPSW_VERSION_1: | |
576 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); | |
577 | break; | |
578 | case CPSW_VERSION_2: | |
579 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); | |
580 | break; | |
581 | } | |
df828598 M |
582 | |
583 | /* setup max packet size, and mac address */ | |
584 | __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); | |
585 | cpsw_set_slave_mac(slave, priv); | |
586 | ||
587 | slave->mac_control = 0; /* no link yet */ | |
588 | ||
589 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
590 | ||
591 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
592 | 1 << slave_port, 0, ALE_MCAST_FWD_2); | |
593 | ||
594 | slave->phy = phy_connect(priv->ndev, slave->data->phy_id, | |
595 | &cpsw_adjust_link, 0, slave->data->phy_if); | |
596 | if (IS_ERR(slave->phy)) { | |
597 | dev_err(priv->dev, "phy %s not found on slave %d\n", | |
598 | slave->data->phy_id, slave->slave_num); | |
599 | slave->phy = NULL; | |
600 | } else { | |
601 | dev_info(priv->dev, "phy found : id is : 0x%x\n", | |
602 | slave->phy->phy_id); | |
603 | phy_start(slave->phy); | |
604 | } | |
605 | } | |
606 | ||
607 | static void cpsw_init_host_port(struct cpsw_priv *priv) | |
608 | { | |
609 | /* soft reset the controller and initialize ale */ | |
610 | soft_reset("cpsw", &priv->regs->soft_reset); | |
611 | cpsw_ale_start(priv->ale); | |
612 | ||
613 | /* switch to vlan unaware mode */ | |
614 | cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0); | |
615 | ||
616 | /* setup host port priority mapping */ | |
617 | __raw_writel(CPDMA_TX_PRIORITY_MAP, | |
618 | &priv->host_port_regs->cpdma_tx_pri_map); | |
619 | __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); | |
620 | ||
621 | cpsw_ale_control_set(priv->ale, priv->host_port, | |
622 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
623 | ||
624 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0); | |
625 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
626 | 1 << priv->host_port, 0, ALE_MCAST_FWD_2); | |
627 | } | |
628 | ||
629 | static int cpsw_ndo_open(struct net_device *ndev) | |
630 | { | |
631 | struct cpsw_priv *priv = netdev_priv(ndev); | |
632 | int i, ret; | |
633 | u32 reg; | |
634 | ||
635 | cpsw_intr_disable(priv); | |
636 | netif_carrier_off(ndev); | |
637 | ||
f150bd7f | 638 | pm_runtime_get_sync(&priv->pdev->dev); |
df828598 | 639 | |
549985ee | 640 | reg = priv->version; |
df828598 M |
641 | |
642 | dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", | |
643 | CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), | |
644 | CPSW_RTL_VERSION(reg)); | |
645 | ||
646 | /* initialize host and slave ports */ | |
647 | cpsw_init_host_port(priv); | |
648 | for_each_slave(priv, cpsw_slave_open, priv); | |
649 | ||
650 | /* setup tx dma to fixed prio and zero offset */ | |
651 | cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); | |
652 | cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); | |
653 | ||
654 | /* disable priority elevation and enable statistics on all ports */ | |
655 | __raw_writel(0, &priv->regs->ptype); | |
656 | ||
657 | /* enable statistics collection only on the host port */ | |
658 | __raw_writel(0x7, &priv->regs->stat_port_en); | |
659 | ||
660 | if (WARN_ON(!priv->data.rx_descs)) | |
661 | priv->data.rx_descs = 128; | |
662 | ||
663 | for (i = 0; i < priv->data.rx_descs; i++) { | |
664 | struct sk_buff *skb; | |
665 | ||
666 | ret = -ENOMEM; | |
667 | skb = netdev_alloc_skb_ip_align(priv->ndev, | |
668 | priv->rx_packet_max); | |
669 | if (!skb) | |
670 | break; | |
671 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, | |
672 | skb_tailroom(skb), GFP_KERNEL); | |
673 | if (WARN_ON(ret < 0)) | |
674 | break; | |
675 | } | |
676 | /* continue even if we didn't manage to submit all receive descs */ | |
677 | cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); | |
678 | ||
679 | cpdma_ctlr_start(priv->dma); | |
680 | cpsw_intr_enable(priv); | |
681 | napi_enable(&priv->napi); | |
682 | cpdma_ctlr_eoi(priv->dma); | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) | |
688 | { | |
689 | if (!slave->phy) | |
690 | return; | |
691 | phy_stop(slave->phy); | |
692 | phy_disconnect(slave->phy); | |
693 | slave->phy = NULL; | |
694 | } | |
695 | ||
696 | static int cpsw_ndo_stop(struct net_device *ndev) | |
697 | { | |
698 | struct cpsw_priv *priv = netdev_priv(ndev); | |
699 | ||
700 | cpsw_info(priv, ifdown, "shutting down cpsw device\n"); | |
df828598 M |
701 | netif_stop_queue(priv->ndev); |
702 | napi_disable(&priv->napi); | |
703 | netif_carrier_off(priv->ndev); | |
71380f9b M |
704 | cpsw_intr_disable(priv); |
705 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
706 | cpdma_ctlr_stop(priv->dma); | |
df828598 M |
707 | cpsw_ale_stop(priv->ale); |
708 | for_each_slave(priv, cpsw_slave_stop, priv); | |
f150bd7f | 709 | pm_runtime_put_sync(&priv->pdev->dev); |
df828598 M |
710 | return 0; |
711 | } | |
712 | ||
713 | static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, | |
714 | struct net_device *ndev) | |
715 | { | |
716 | struct cpsw_priv *priv = netdev_priv(ndev); | |
717 | int ret; | |
718 | ||
719 | ndev->trans_start = jiffies; | |
720 | ||
721 | if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { | |
722 | cpsw_err(priv, tx_err, "packet pad failed\n"); | |
723 | priv->stats.tx_dropped++; | |
724 | return NETDEV_TX_OK; | |
725 | } | |
726 | ||
2e5b38ab RC |
727 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && priv->cpts.tx_enable) |
728 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
729 | ||
730 | skb_tx_timestamp(skb); | |
731 | ||
df828598 M |
732 | ret = cpdma_chan_submit(priv->txch, skb, skb->data, |
733 | skb->len, GFP_KERNEL); | |
734 | if (unlikely(ret != 0)) { | |
735 | cpsw_err(priv, tx_err, "desc submit failed\n"); | |
736 | goto fail; | |
737 | } | |
738 | ||
739 | return NETDEV_TX_OK; | |
740 | fail: | |
741 | priv->stats.tx_dropped++; | |
742 | netif_stop_queue(ndev); | |
743 | return NETDEV_TX_BUSY; | |
744 | } | |
745 | ||
746 | static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) | |
747 | { | |
748 | /* | |
749 | * The switch cannot operate in promiscuous mode without substantial | |
750 | * headache. For promiscuous mode to work, we would need to put the | |
751 | * ALE in bypass mode and route all traffic to the host port. | |
752 | * Subsequently, the host will need to operate as a "bridge", learn, | |
753 | * and flood as needed. For now, we simply complain here and | |
754 | * do nothing about it :-) | |
755 | */ | |
756 | if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) | |
757 | dev_err(&ndev->dev, "promiscuity ignored!\n"); | |
758 | ||
759 | /* | |
760 | * The switch cannot filter multicast traffic unless it is configured | |
761 | * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a | |
762 | * whole bunch of additional logic that this driver does not implement | |
763 | * at present. | |
764 | */ | |
765 | if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) | |
766 | dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); | |
767 | } | |
768 | ||
2e5b38ab RC |
769 | #ifdef CONFIG_TI_CPTS |
770 | ||
771 | static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) | |
772 | { | |
773 | struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; | |
774 | u32 ts_en, seq_id; | |
775 | ||
776 | if (!priv->cpts.tx_enable && !priv->cpts.rx_enable) { | |
777 | slave_write(slave, 0, CPSW1_TS_CTL); | |
778 | return; | |
779 | } | |
780 | ||
781 | seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; | |
782 | ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; | |
783 | ||
784 | if (priv->cpts.tx_enable) | |
785 | ts_en |= CPSW_V1_TS_TX_EN; | |
786 | ||
787 | if (priv->cpts.rx_enable) | |
788 | ts_en |= CPSW_V1_TS_RX_EN; | |
789 | ||
790 | slave_write(slave, ts_en, CPSW1_TS_CTL); | |
791 | slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); | |
792 | } | |
793 | ||
794 | static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) | |
795 | { | |
796 | struct cpsw_slave *slave = &priv->slaves[priv->data.cpts_active_slave]; | |
797 | u32 ctrl, mtype; | |
798 | ||
799 | ctrl = slave_read(slave, CPSW2_CONTROL); | |
800 | ctrl &= ~CTRL_ALL_TS_MASK; | |
801 | ||
802 | if (priv->cpts.tx_enable) | |
803 | ctrl |= CTRL_TX_TS_BITS; | |
804 | ||
805 | if (priv->cpts.rx_enable) | |
806 | ctrl |= CTRL_RX_TS_BITS; | |
807 | ||
808 | mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; | |
809 | ||
810 | slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); | |
811 | slave_write(slave, ctrl, CPSW2_CONTROL); | |
812 | __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); | |
813 | } | |
814 | ||
3177bf6f | 815 | static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) |
2e5b38ab | 816 | { |
3177bf6f | 817 | struct cpsw_priv *priv = netdev_priv(dev); |
2e5b38ab RC |
818 | struct cpts *cpts = &priv->cpts; |
819 | struct hwtstamp_config cfg; | |
820 | ||
821 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
822 | return -EFAULT; | |
823 | ||
824 | /* reserved for future extensions */ | |
825 | if (cfg.flags) | |
826 | return -EINVAL; | |
827 | ||
828 | switch (cfg.tx_type) { | |
829 | case HWTSTAMP_TX_OFF: | |
830 | cpts->tx_enable = 0; | |
831 | break; | |
832 | case HWTSTAMP_TX_ON: | |
833 | cpts->tx_enable = 1; | |
834 | break; | |
835 | default: | |
836 | return -ERANGE; | |
837 | } | |
838 | ||
839 | switch (cfg.rx_filter) { | |
840 | case HWTSTAMP_FILTER_NONE: | |
841 | cpts->rx_enable = 0; | |
842 | break; | |
843 | case HWTSTAMP_FILTER_ALL: | |
844 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
845 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
846 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
847 | return -ERANGE; | |
848 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
849 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
850 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
851 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
852 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
853 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
854 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
855 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
856 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
857 | cpts->rx_enable = 1; | |
858 | cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
859 | break; | |
860 | default: | |
861 | return -ERANGE; | |
862 | } | |
863 | ||
864 | switch (priv->version) { | |
865 | case CPSW_VERSION_1: | |
866 | cpsw_hwtstamp_v1(priv); | |
867 | break; | |
868 | case CPSW_VERSION_2: | |
869 | cpsw_hwtstamp_v2(priv); | |
870 | break; | |
871 | default: | |
872 | return -ENOTSUPP; | |
873 | } | |
874 | ||
875 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
876 | } | |
877 | ||
878 | #endif /*CONFIG_TI_CPTS*/ | |
879 | ||
880 | static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
881 | { | |
2e5b38ab RC |
882 | if (!netif_running(dev)) |
883 | return -EINVAL; | |
884 | ||
885 | #ifdef CONFIG_TI_CPTS | |
886 | if (cmd == SIOCSHWTSTAMP) | |
3177bf6f | 887 | return cpsw_hwtstamp_ioctl(dev, req); |
2e5b38ab RC |
888 | #endif |
889 | return -ENOTSUPP; | |
890 | } | |
891 | ||
df828598 M |
892 | static void cpsw_ndo_tx_timeout(struct net_device *ndev) |
893 | { | |
894 | struct cpsw_priv *priv = netdev_priv(ndev); | |
895 | ||
896 | cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); | |
897 | priv->stats.tx_errors++; | |
898 | cpsw_intr_disable(priv); | |
899 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
900 | cpdma_chan_stop(priv->txch); | |
901 | cpdma_chan_start(priv->txch); | |
902 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
903 | cpsw_intr_enable(priv); | |
904 | cpdma_ctlr_eoi(priv->dma); | |
905 | } | |
906 | ||
907 | static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) | |
908 | { | |
909 | struct cpsw_priv *priv = netdev_priv(ndev); | |
910 | return &priv->stats; | |
911 | } | |
912 | ||
913 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
914 | static void cpsw_ndo_poll_controller(struct net_device *ndev) | |
915 | { | |
916 | struct cpsw_priv *priv = netdev_priv(ndev); | |
917 | ||
918 | cpsw_intr_disable(priv); | |
919 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
920 | cpsw_interrupt(ndev->irq, priv); | |
921 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
922 | cpsw_intr_enable(priv); | |
923 | cpdma_ctlr_eoi(priv->dma); | |
924 | } | |
925 | #endif | |
926 | ||
927 | static const struct net_device_ops cpsw_netdev_ops = { | |
928 | .ndo_open = cpsw_ndo_open, | |
929 | .ndo_stop = cpsw_ndo_stop, | |
930 | .ndo_start_xmit = cpsw_ndo_start_xmit, | |
931 | .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, | |
2e5b38ab | 932 | .ndo_do_ioctl = cpsw_ndo_ioctl, |
df828598 | 933 | .ndo_validate_addr = eth_validate_addr, |
5c473ed2 | 934 | .ndo_change_mtu = eth_change_mtu, |
df828598 M |
935 | .ndo_tx_timeout = cpsw_ndo_tx_timeout, |
936 | .ndo_get_stats = cpsw_ndo_get_stats, | |
5c50a856 | 937 | .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, |
df828598 M |
938 | #ifdef CONFIG_NET_POLL_CONTROLLER |
939 | .ndo_poll_controller = cpsw_ndo_poll_controller, | |
940 | #endif | |
941 | }; | |
942 | ||
943 | static void cpsw_get_drvinfo(struct net_device *ndev, | |
944 | struct ethtool_drvinfo *info) | |
945 | { | |
946 | struct cpsw_priv *priv = netdev_priv(ndev); | |
947 | strcpy(info->driver, "TI CPSW Driver v1.0"); | |
948 | strcpy(info->version, "1.0"); | |
949 | strcpy(info->bus_info, priv->pdev->name); | |
950 | } | |
951 | ||
952 | static u32 cpsw_get_msglevel(struct net_device *ndev) | |
953 | { | |
954 | struct cpsw_priv *priv = netdev_priv(ndev); | |
955 | return priv->msg_enable; | |
956 | } | |
957 | ||
958 | static void cpsw_set_msglevel(struct net_device *ndev, u32 value) | |
959 | { | |
960 | struct cpsw_priv *priv = netdev_priv(ndev); | |
961 | priv->msg_enable = value; | |
962 | } | |
963 | ||
2e5b38ab RC |
964 | static int cpsw_get_ts_info(struct net_device *ndev, |
965 | struct ethtool_ts_info *info) | |
966 | { | |
967 | #ifdef CONFIG_TI_CPTS | |
968 | struct cpsw_priv *priv = netdev_priv(ndev); | |
969 | ||
970 | info->so_timestamping = | |
971 | SOF_TIMESTAMPING_TX_HARDWARE | | |
972 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
973 | SOF_TIMESTAMPING_RX_HARDWARE | | |
974 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
975 | SOF_TIMESTAMPING_SOFTWARE | | |
976 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
977 | info->phc_index = priv->cpts.phc_index; | |
978 | info->tx_types = | |
979 | (1 << HWTSTAMP_TX_OFF) | | |
980 | (1 << HWTSTAMP_TX_ON); | |
981 | info->rx_filters = | |
982 | (1 << HWTSTAMP_FILTER_NONE) | | |
983 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); | |
984 | #else | |
985 | info->so_timestamping = | |
986 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
987 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
988 | SOF_TIMESTAMPING_SOFTWARE; | |
989 | info->phc_index = -1; | |
990 | info->tx_types = 0; | |
991 | info->rx_filters = 0; | |
992 | #endif | |
993 | return 0; | |
994 | } | |
995 | ||
df828598 M |
996 | static const struct ethtool_ops cpsw_ethtool_ops = { |
997 | .get_drvinfo = cpsw_get_drvinfo, | |
998 | .get_msglevel = cpsw_get_msglevel, | |
999 | .set_msglevel = cpsw_set_msglevel, | |
1000 | .get_link = ethtool_op_get_link, | |
2e5b38ab | 1001 | .get_ts_info = cpsw_get_ts_info, |
df828598 M |
1002 | }; |
1003 | ||
549985ee RC |
1004 | static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, |
1005 | u32 slave_reg_ofs, u32 sliver_reg_ofs) | |
df828598 M |
1006 | { |
1007 | void __iomem *regs = priv->regs; | |
1008 | int slave_num = slave->slave_num; | |
1009 | struct cpsw_slave_data *data = priv->data.slave_data + slave_num; | |
1010 | ||
1011 | slave->data = data; | |
549985ee RC |
1012 | slave->regs = regs + slave_reg_ofs; |
1013 | slave->sliver = regs + sliver_reg_ofs; | |
df828598 M |
1014 | } |
1015 | ||
2eb32b0a M |
1016 | static int cpsw_probe_dt(struct cpsw_platform_data *data, |
1017 | struct platform_device *pdev) | |
1018 | { | |
1019 | struct device_node *node = pdev->dev.of_node; | |
1020 | struct device_node *slave_node; | |
1021 | int i = 0, ret; | |
1022 | u32 prop; | |
1023 | ||
1024 | if (!node) | |
1025 | return -EINVAL; | |
1026 | ||
1027 | if (of_property_read_u32(node, "slaves", &prop)) { | |
1028 | pr_err("Missing slaves property in the DT.\n"); | |
1029 | return -EINVAL; | |
1030 | } | |
1031 | data->slaves = prop; | |
1032 | ||
78ca0b28 RC |
1033 | if (of_property_read_u32(node, "cpts_active_slave", &prop)) { |
1034 | pr_err("Missing cpts_active_slave property in the DT.\n"); | |
1035 | ret = -EINVAL; | |
1036 | goto error_ret; | |
1037 | } | |
1038 | data->cpts_active_slave = prop; | |
1039 | ||
00ab94ee RC |
1040 | if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { |
1041 | pr_err("Missing cpts_clock_mult property in the DT.\n"); | |
1042 | ret = -EINVAL; | |
1043 | goto error_ret; | |
1044 | } | |
1045 | data->cpts_clock_mult = prop; | |
1046 | ||
1047 | if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { | |
1048 | pr_err("Missing cpts_clock_shift property in the DT.\n"); | |
1049 | ret = -EINVAL; | |
1050 | goto error_ret; | |
1051 | } | |
1052 | data->cpts_clock_shift = prop; | |
1053 | ||
2eb32b0a M |
1054 | data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) * |
1055 | data->slaves, GFP_KERNEL); | |
1056 | if (!data->slave_data) { | |
1057 | pr_err("Could not allocate slave memory.\n"); | |
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
2eb32b0a M |
1061 | if (of_property_read_u32(node, "cpdma_channels", &prop)) { |
1062 | pr_err("Missing cpdma_channels property in the DT.\n"); | |
1063 | ret = -EINVAL; | |
1064 | goto error_ret; | |
1065 | } | |
1066 | data->channels = prop; | |
1067 | ||
2eb32b0a M |
1068 | if (of_property_read_u32(node, "ale_entries", &prop)) { |
1069 | pr_err("Missing ale_entries property in the DT.\n"); | |
1070 | ret = -EINVAL; | |
1071 | goto error_ret; | |
1072 | } | |
1073 | data->ale_entries = prop; | |
1074 | ||
2eb32b0a M |
1075 | if (of_property_read_u32(node, "bd_ram_size", &prop)) { |
1076 | pr_err("Missing bd_ram_size property in the DT.\n"); | |
1077 | ret = -EINVAL; | |
1078 | goto error_ret; | |
1079 | } | |
1080 | data->bd_ram_size = prop; | |
1081 | ||
1082 | if (of_property_read_u32(node, "rx_descs", &prop)) { | |
1083 | pr_err("Missing rx_descs property in the DT.\n"); | |
1084 | ret = -EINVAL; | |
1085 | goto error_ret; | |
1086 | } | |
1087 | data->rx_descs = prop; | |
1088 | ||
1089 | if (of_property_read_u32(node, "mac_control", &prop)) { | |
1090 | pr_err("Missing mac_control property in the DT.\n"); | |
1091 | ret = -EINVAL; | |
1092 | goto error_ret; | |
1093 | } | |
1094 | data->mac_control = prop; | |
1095 | ||
549985ee RC |
1096 | /* |
1097 | * Populate all the child nodes here... | |
1098 | */ | |
1099 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); | |
1100 | /* We do not want to force this, as in some cases may not have child */ | |
1101 | if (ret) | |
1102 | pr_warn("Doesn't have any child node\n"); | |
1103 | ||
1fb19aa7 | 1104 | for_each_node_by_name(slave_node, "slave") { |
2eb32b0a | 1105 | struct cpsw_slave_data *slave_data = data->slave_data + i; |
2eb32b0a | 1106 | const void *mac_addr = NULL; |
549985ee RC |
1107 | u32 phyid; |
1108 | int lenp; | |
1109 | const __be32 *parp; | |
1110 | struct device_node *mdio_node; | |
1111 | struct platform_device *mdio; | |
1112 | ||
1113 | parp = of_get_property(slave_node, "phy_id", &lenp); | |
1114 | if ((parp == NULL) && (lenp != (sizeof(void *) * 2))) { | |
2eb32b0a M |
1115 | pr_err("Missing slave[%d] phy_id property\n", i); |
1116 | ret = -EINVAL; | |
1117 | goto error_ret; | |
1118 | } | |
549985ee RC |
1119 | mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); |
1120 | phyid = be32_to_cpup(parp+1); | |
1121 | mdio = of_find_device_by_node(mdio_node); | |
1122 | snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), | |
1123 | PHY_ID_FMT, mdio->name, phyid); | |
2eb32b0a M |
1124 | |
1125 | mac_addr = of_get_mac_address(slave_node); | |
1126 | if (mac_addr) | |
1127 | memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); | |
1128 | ||
1129 | i++; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | ||
1134 | error_ret: | |
1135 | kfree(data->slave_data); | |
1136 | return ret; | |
1137 | } | |
1138 | ||
663e12e6 | 1139 | static int cpsw_probe(struct platform_device *pdev) |
df828598 M |
1140 | { |
1141 | struct cpsw_platform_data *data = pdev->dev.platform_data; | |
1142 | struct net_device *ndev; | |
1143 | struct cpsw_priv *priv; | |
1144 | struct cpdma_params dma_params; | |
1145 | struct cpsw_ale_params ale_params; | |
549985ee | 1146 | void __iomem *ss_regs, *wr_regs; |
df828598 | 1147 | struct resource *res; |
549985ee | 1148 | u32 slave_offset, sliver_offset, slave_size; |
df828598 M |
1149 | int ret = 0, i, k = 0; |
1150 | ||
df828598 M |
1151 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); |
1152 | if (!ndev) { | |
1153 | pr_err("error allocating net_device\n"); | |
1154 | return -ENOMEM; | |
1155 | } | |
1156 | ||
1157 | platform_set_drvdata(pdev, ndev); | |
1158 | priv = netdev_priv(ndev); | |
1159 | spin_lock_init(&priv->lock); | |
df828598 M |
1160 | priv->pdev = pdev; |
1161 | priv->ndev = ndev; | |
1162 | priv->dev = &ndev->dev; | |
1163 | priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1164 | priv->rx_packet_max = max(rx_packet_max, 128); | |
1165 | ||
1fb19aa7 VH |
1166 | /* |
1167 | * This may be required here for child devices. | |
1168 | */ | |
1169 | pm_runtime_enable(&pdev->dev); | |
1170 | ||
2eb32b0a M |
1171 | if (cpsw_probe_dt(&priv->data, pdev)) { |
1172 | pr_err("cpsw: platform data missing\n"); | |
1173 | ret = -ENODEV; | |
1174 | goto clean_ndev_ret; | |
1175 | } | |
1176 | data = &priv->data; | |
1177 | ||
df828598 M |
1178 | if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { |
1179 | memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); | |
1180 | pr_info("Detected MACID = %pM", priv->mac_addr); | |
1181 | } else { | |
7efd26d0 | 1182 | eth_random_addr(priv->mac_addr); |
df828598 M |
1183 | pr_info("Random MACID = %pM", priv->mac_addr); |
1184 | } | |
1185 | ||
1186 | memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); | |
1187 | ||
1188 | priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves, | |
1189 | GFP_KERNEL); | |
1190 | if (!priv->slaves) { | |
1191 | ret = -EBUSY; | |
1192 | goto clean_ndev_ret; | |
1193 | } | |
1194 | for (i = 0; i < data->slaves; i++) | |
1195 | priv->slaves[i].slave_num = i; | |
1196 | ||
f150bd7f | 1197 | priv->clk = clk_get(&pdev->dev, "fck"); |
df828598 | 1198 | if (IS_ERR(priv->clk)) { |
f150bd7f M |
1199 | dev_err(&pdev->dev, "fck is not found\n"); |
1200 | ret = -ENODEV; | |
1201 | goto clean_slave_ret; | |
df828598 M |
1202 | } |
1203 | ||
1204 | priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1205 | if (!priv->cpsw_res) { | |
1206 | dev_err(priv->dev, "error getting i/o resource\n"); | |
1207 | ret = -ENOENT; | |
1208 | goto clean_clk_ret; | |
1209 | } | |
df828598 M |
1210 | if (!request_mem_region(priv->cpsw_res->start, |
1211 | resource_size(priv->cpsw_res), ndev->name)) { | |
1212 | dev_err(priv->dev, "failed request i/o region\n"); | |
1213 | ret = -ENXIO; | |
1214 | goto clean_clk_ret; | |
1215 | } | |
549985ee RC |
1216 | ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res)); |
1217 | if (!ss_regs) { | |
df828598 M |
1218 | dev_err(priv->dev, "unable to map i/o region\n"); |
1219 | goto clean_cpsw_iores_ret; | |
1220 | } | |
549985ee RC |
1221 | priv->regs = ss_regs; |
1222 | priv->version = __raw_readl(&priv->regs->id_ver); | |
1223 | priv->host_port = HOST_PORT_NUM; | |
df828598 | 1224 | |
a65dd5b2 RC |
1225 | priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1226 | if (!priv->cpsw_wr_res) { | |
df828598 M |
1227 | dev_err(priv->dev, "error getting i/o resource\n"); |
1228 | ret = -ENOENT; | |
5250c969 | 1229 | goto clean_iomap_ret; |
df828598 | 1230 | } |
a65dd5b2 RC |
1231 | if (!request_mem_region(priv->cpsw_wr_res->start, |
1232 | resource_size(priv->cpsw_wr_res), ndev->name)) { | |
df828598 M |
1233 | dev_err(priv->dev, "failed request i/o region\n"); |
1234 | ret = -ENXIO; | |
5250c969 | 1235 | goto clean_iomap_ret; |
df828598 | 1236 | } |
549985ee | 1237 | wr_regs = ioremap(priv->cpsw_wr_res->start, |
a65dd5b2 | 1238 | resource_size(priv->cpsw_wr_res)); |
549985ee | 1239 | if (!wr_regs) { |
df828598 | 1240 | dev_err(priv->dev, "unable to map i/o region\n"); |
a65dd5b2 | 1241 | goto clean_cpsw_wr_iores_ret; |
df828598 | 1242 | } |
549985ee | 1243 | priv->wr_regs = wr_regs; |
df828598 M |
1244 | |
1245 | memset(&dma_params, 0, sizeof(dma_params)); | |
549985ee RC |
1246 | memset(&ale_params, 0, sizeof(ale_params)); |
1247 | ||
1248 | switch (priv->version) { | |
1249 | case CPSW_VERSION_1: | |
1250 | priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; | |
1251 | priv->cpts.reg = ss_regs + CPSW1_CPTS_OFFSET; | |
1252 | dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; | |
1253 | dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; | |
1254 | ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; | |
1255 | slave_offset = CPSW1_SLAVE_OFFSET; | |
1256 | slave_size = CPSW1_SLAVE_SIZE; | |
1257 | sliver_offset = CPSW1_SLIVER_OFFSET; | |
1258 | dma_params.desc_mem_phys = 0; | |
1259 | break; | |
1260 | case CPSW_VERSION_2: | |
1261 | priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; | |
1262 | priv->cpts.reg = ss_regs + CPSW2_CPTS_OFFSET; | |
1263 | dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; | |
1264 | dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; | |
1265 | ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; | |
1266 | slave_offset = CPSW2_SLAVE_OFFSET; | |
1267 | slave_size = CPSW2_SLAVE_SIZE; | |
1268 | sliver_offset = CPSW2_SLIVER_OFFSET; | |
1269 | dma_params.desc_mem_phys = | |
1270 | (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET; | |
1271 | break; | |
1272 | default: | |
1273 | dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); | |
1274 | ret = -ENODEV; | |
1275 | goto clean_cpsw_wr_iores_ret; | |
1276 | } | |
1277 | for (i = 0; i < priv->data.slaves; i++) { | |
1278 | struct cpsw_slave *slave = &priv->slaves[i]; | |
1279 | cpsw_slave_init(slave, priv, slave_offset, sliver_offset); | |
1280 | slave_offset += slave_size; | |
1281 | sliver_offset += SLIVER_SIZE; | |
1282 | } | |
1283 | ||
df828598 | 1284 | dma_params.dev = &pdev->dev; |
549985ee RC |
1285 | dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; |
1286 | dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; | |
1287 | dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; | |
1288 | dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; | |
1289 | dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; | |
df828598 M |
1290 | |
1291 | dma_params.num_chan = data->channels; | |
1292 | dma_params.has_soft_reset = true; | |
1293 | dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; | |
1294 | dma_params.desc_mem_size = data->bd_ram_size; | |
1295 | dma_params.desc_align = 16; | |
1296 | dma_params.has_ext_regs = true; | |
549985ee | 1297 | dma_params.desc_hw_addr = dma_params.desc_mem_phys; |
df828598 M |
1298 | |
1299 | priv->dma = cpdma_ctlr_create(&dma_params); | |
1300 | if (!priv->dma) { | |
1301 | dev_err(priv->dev, "error initializing dma\n"); | |
1302 | ret = -ENOMEM; | |
5250c969 | 1303 | goto clean_wr_iomap_ret; |
df828598 M |
1304 | } |
1305 | ||
1306 | priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), | |
1307 | cpsw_tx_handler); | |
1308 | priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), | |
1309 | cpsw_rx_handler); | |
1310 | ||
1311 | if (WARN_ON(!priv->txch || !priv->rxch)) { | |
1312 | dev_err(priv->dev, "error initializing dma channels\n"); | |
1313 | ret = -ENOMEM; | |
1314 | goto clean_dma_ret; | |
1315 | } | |
1316 | ||
df828598 | 1317 | ale_params.dev = &ndev->dev; |
df828598 M |
1318 | ale_params.ale_ageout = ale_ageout; |
1319 | ale_params.ale_entries = data->ale_entries; | |
1320 | ale_params.ale_ports = data->slaves; | |
1321 | ||
1322 | priv->ale = cpsw_ale_create(&ale_params); | |
1323 | if (!priv->ale) { | |
1324 | dev_err(priv->dev, "error initializing ale engine\n"); | |
1325 | ret = -ENODEV; | |
1326 | goto clean_dma_ret; | |
1327 | } | |
1328 | ||
1329 | ndev->irq = platform_get_irq(pdev, 0); | |
1330 | if (ndev->irq < 0) { | |
1331 | dev_err(priv->dev, "error getting irq resource\n"); | |
1332 | ret = -ENOENT; | |
1333 | goto clean_ale_ret; | |
1334 | } | |
1335 | ||
1336 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { | |
1337 | for (i = res->start; i <= res->end; i++) { | |
1338 | if (request_irq(i, cpsw_interrupt, IRQF_DISABLED, | |
1339 | dev_name(&pdev->dev), priv)) { | |
1340 | dev_err(priv->dev, "error attaching irq\n"); | |
1341 | goto clean_ale_ret; | |
1342 | } | |
1343 | priv->irqs_table[k] = i; | |
1344 | priv->num_irqs = k; | |
1345 | } | |
1346 | k++; | |
1347 | } | |
1348 | ||
1349 | ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */ | |
1350 | ||
1351 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1352 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1353 | netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1354 | ||
1355 | /* register the network device */ | |
1356 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1357 | ret = register_netdev(ndev); | |
1358 | if (ret) { | |
1359 | dev_err(priv->dev, "error registering net device\n"); | |
1360 | ret = -ENODEV; | |
1361 | goto clean_irq_ret; | |
1362 | } | |
1363 | ||
2e5b38ab RC |
1364 | if (cpts_register(&pdev->dev, &priv->cpts, |
1365 | data->cpts_clock_mult, data->cpts_clock_shift)) | |
1366 | dev_err(priv->dev, "error registering cpts device\n"); | |
1367 | ||
df828598 M |
1368 | cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", |
1369 | priv->cpsw_res->start, ndev->irq); | |
1370 | ||
1371 | return 0; | |
1372 | ||
1373 | clean_irq_ret: | |
1374 | free_irq(ndev->irq, priv); | |
1375 | clean_ale_ret: | |
1376 | cpsw_ale_destroy(priv->ale); | |
1377 | clean_dma_ret: | |
1378 | cpdma_chan_destroy(priv->txch); | |
1379 | cpdma_chan_destroy(priv->rxch); | |
1380 | cpdma_ctlr_destroy(priv->dma); | |
5250c969 RC |
1381 | clean_wr_iomap_ret: |
1382 | iounmap(priv->wr_regs); | |
a65dd5b2 RC |
1383 | clean_cpsw_wr_iores_ret: |
1384 | release_mem_region(priv->cpsw_wr_res->start, | |
1385 | resource_size(priv->cpsw_wr_res)); | |
5250c969 RC |
1386 | clean_iomap_ret: |
1387 | iounmap(priv->regs); | |
df828598 M |
1388 | clean_cpsw_iores_ret: |
1389 | release_mem_region(priv->cpsw_res->start, | |
1390 | resource_size(priv->cpsw_res)); | |
1391 | clean_clk_ret: | |
1392 | clk_put(priv->clk); | |
f150bd7f M |
1393 | clean_slave_ret: |
1394 | pm_runtime_disable(&pdev->dev); | |
df828598 M |
1395 | kfree(priv->slaves); |
1396 | clean_ndev_ret: | |
1397 | free_netdev(ndev); | |
1398 | return ret; | |
1399 | } | |
1400 | ||
663e12e6 | 1401 | static int cpsw_remove(struct platform_device *pdev) |
df828598 M |
1402 | { |
1403 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1404 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1405 | ||
1406 | pr_info("removing device"); | |
1407 | platform_set_drvdata(pdev, NULL); | |
1408 | ||
2e5b38ab | 1409 | cpts_unregister(&priv->cpts); |
df828598 M |
1410 | free_irq(ndev->irq, priv); |
1411 | cpsw_ale_destroy(priv->ale); | |
1412 | cpdma_chan_destroy(priv->txch); | |
1413 | cpdma_chan_destroy(priv->rxch); | |
1414 | cpdma_ctlr_destroy(priv->dma); | |
1415 | iounmap(priv->regs); | |
1416 | release_mem_region(priv->cpsw_res->start, | |
1417 | resource_size(priv->cpsw_res)); | |
5250c969 | 1418 | iounmap(priv->wr_regs); |
a65dd5b2 RC |
1419 | release_mem_region(priv->cpsw_wr_res->start, |
1420 | resource_size(priv->cpsw_wr_res)); | |
f150bd7f | 1421 | pm_runtime_disable(&pdev->dev); |
df828598 M |
1422 | clk_put(priv->clk); |
1423 | kfree(priv->slaves); | |
1424 | free_netdev(ndev); | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | static int cpsw_suspend(struct device *dev) | |
1430 | { | |
1431 | struct platform_device *pdev = to_platform_device(dev); | |
1432 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1433 | ||
1434 | if (netif_running(ndev)) | |
1435 | cpsw_ndo_stop(ndev); | |
f150bd7f M |
1436 | pm_runtime_put_sync(&pdev->dev); |
1437 | ||
df828598 M |
1438 | return 0; |
1439 | } | |
1440 | ||
1441 | static int cpsw_resume(struct device *dev) | |
1442 | { | |
1443 | struct platform_device *pdev = to_platform_device(dev); | |
1444 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1445 | ||
f150bd7f | 1446 | pm_runtime_get_sync(&pdev->dev); |
df828598 M |
1447 | if (netif_running(ndev)) |
1448 | cpsw_ndo_open(ndev); | |
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | static const struct dev_pm_ops cpsw_pm_ops = { | |
1453 | .suspend = cpsw_suspend, | |
1454 | .resume = cpsw_resume, | |
1455 | }; | |
1456 | ||
2eb32b0a M |
1457 | static const struct of_device_id cpsw_of_mtable[] = { |
1458 | { .compatible = "ti,cpsw", }, | |
1459 | { /* sentinel */ }, | |
1460 | }; | |
1461 | ||
df828598 M |
1462 | static struct platform_driver cpsw_driver = { |
1463 | .driver = { | |
1464 | .name = "cpsw", | |
1465 | .owner = THIS_MODULE, | |
1466 | .pm = &cpsw_pm_ops, | |
2eb32b0a | 1467 | .of_match_table = of_match_ptr(cpsw_of_mtable), |
df828598 M |
1468 | }, |
1469 | .probe = cpsw_probe, | |
663e12e6 | 1470 | .remove = cpsw_remove, |
df828598 M |
1471 | }; |
1472 | ||
1473 | static int __init cpsw_init(void) | |
1474 | { | |
1475 | return platform_driver_register(&cpsw_driver); | |
1476 | } | |
1477 | late_initcall(cpsw_init); | |
1478 | ||
1479 | static void __exit cpsw_exit(void) | |
1480 | { | |
1481 | platform_driver_unregister(&cpsw_driver); | |
1482 | } | |
1483 | module_exit(cpsw_exit); | |
1484 | ||
1485 | MODULE_LICENSE("GPL"); | |
1486 | MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); | |
1487 | MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); | |
1488 | MODULE_DESCRIPTION("TI CPSW Ethernet driver"); |