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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
e05107e6 127#define CPDMA_TX_PRIORITY_MAP 0x01234567
df828598 128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
606f3993
IK		 143#define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
e38b5a3d 146#define IRQ_NUM 2
e05107e6 147#define CPSW_MAX_QUEUES 8
90225bf0 148#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
d3bb9c58 149
df828598
M		 150static int debug_level;
151module_param(debug_level, int, 0);
152MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
153
154static int ale_ageout = 10;
155module_param(ale_ageout, int, 0);
156MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
157
158static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
159module_param(rx_packet_max, int, 0);
160MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
161
90225bf0
GS		 162static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
163module_param(descs_pool_size, int, 0444);
164MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
165
996a5c27 166struct cpsw_wr_regs {
df828598
M		 167 u32 id_ver;
168 u32 soft_reset;
169 u32 control;
170 u32 int_control;
171 u32 rx_thresh_en;
172 u32 rx_en;
173 u32 tx_en;
174 u32 misc_en;
ff5b8ef2
M		 175 u32 mem_allign1[8];
176 u32 rx_thresh_stat;
177 u32 rx_stat;
178 u32 tx_stat;
179 u32 misc_stat;
180 u32 mem_allign2[8];
181 u32 rx_imax;
182 u32 tx_imax;
183
df828598
M		 184};
185
996a5c27 186struct cpsw_ss_regs {
df828598
M		 187 u32 id_ver;
188 u32 control;
189 u32 soft_reset;
190 u32 stat_port_en;
191 u32 ptype;
bd357af2
RC		 192 u32 soft_idle;
193 u32 thru_rate;
194 u32 gap_thresh;
195 u32 tx_start_wds;
196 u32 flow_control;
197 u32 vlan_ltype;
198 u32 ts_ltype;
199 u32 dlr_ltype;
df828598
M		 200};
201
9750a3ad
RC		 202/* CPSW_PORT_V1 */
203#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
204#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
205#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
206#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
207#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
208#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
209#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
210#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
211
212/* CPSW_PORT_V2 */
213#define CPSW2_CONTROL 0x00 /* Control Register */
214#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
215#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
216#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
217#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
218#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
219#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
220
221/* CPSW_PORT_V1 and V2 */
222#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
223#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
224#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
225
226/* CPSW_PORT_V2 only */
227#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
228#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
229#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
230#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
231#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
235
236/* Bit definitions for the CPSW2_CONTROL register */
237#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
238#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
239#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
240#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
241#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
242#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
243#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
244#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
245#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
246#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 247#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
248#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 249#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
250#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
251#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
252#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
253#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
254
09c55372
GC		 255#define CTRL_V2_TS_BITS \
256 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
257 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 258
09c55372
GC		 259#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
260#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
261#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
262
263
264#define CTRL_V3_TS_BITS \
265 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
266 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
267 TS_LTYPE1_EN)
268
269#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
270#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
271#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 272
273/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
274#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
275#define TS_SEQ_ID_OFFSET_MASK (0x3f)
276#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
277#define TS_MSG_TYPE_EN_MASK (0xffff)
278
279/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
280#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 281
2e5b38ab
RC		 282/* Bit definitions for the CPSW1_TS_CTL register */
283#define CPSW_V1_TS_RX_EN BIT(0)
284#define CPSW_V1_TS_TX_EN BIT(4)
285#define CPSW_V1_MSG_TYPE_OFS 16
286
287/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
288#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
289
48f5bccc
GS		 290#define CPSW_MAX_BLKS_TX 15
291#define CPSW_MAX_BLKS_TX_SHIFT 4
292#define CPSW_MAX_BLKS_RX 5
293
df828598
M		 294struct cpsw_host_regs {
295 u32 max_blks;
296 u32 blk_cnt;
d9ba8f9e 297 u32 tx_in_ctl;
df828598
M		 298 u32 port_vlan;
299 u32 tx_pri_map;
300 u32 cpdma_tx_pri_map;
301 u32 cpdma_rx_chan_map;
302};
303
304struct cpsw_sliver_regs {
305 u32 id_ver;
306 u32 mac_control;
307 u32 mac_status;
308 u32 soft_reset;
309 u32 rx_maxlen;
310 u32 __reserved_0;
311 u32 rx_pause;
312 u32 tx_pause;
313 u32 __reserved_1;
314 u32 rx_pri_map;
315};
316
d9718546
M		 317struct cpsw_hw_stats {
318 u32 rxgoodframes;
319 u32 rxbroadcastframes;
320 u32 rxmulticastframes;
321 u32 rxpauseframes;
322 u32 rxcrcerrors;
323 u32 rxaligncodeerrors;
324 u32 rxoversizedframes;
325 u32 rxjabberframes;
326 u32 rxundersizedframes;
327 u32 rxfragments;
328 u32 __pad_0[2];
329 u32 rxoctets;
330 u32 txgoodframes;
331 u32 txbroadcastframes;
332 u32 txmulticastframes;
333 u32 txpauseframes;
334 u32 txdeferredframes;
335 u32 txcollisionframes;
336 u32 txsinglecollframes;
337 u32 txmultcollframes;
338 u32 txexcessivecollisions;
339 u32 txlatecollisions;
340 u32 txunderrun;
341 u32 txcarriersenseerrors;
342 u32 txoctets;
343 u32 octetframes64;
344 u32 octetframes65t127;
345 u32 octetframes128t255;
346 u32 octetframes256t511;
347 u32 octetframes512t1023;
348 u32 octetframes1024tup;
349 u32 netoctets;
350 u32 rxsofoverruns;
351 u32 rxmofoverruns;
352 u32 rxdmaoverruns;
353};
354
df828598 355struct cpsw_slave {
9750a3ad 356 void __iomem *regs;
df828598
M		 357 struct cpsw_sliver_regs __iomem *sliver;
358 int slave_num;
359 u32 mac_control;
360 struct cpsw_slave_data *data;
361 struct phy_device *phy;
d9ba8f9e
M		 362 struct net_device *ndev;
363 u32 port_vlan;
df828598
M		 364};
365
9750a3ad
RC		 366static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
367{
368 return __raw_readl(slave->regs + offset);
369}
370
371static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
372{
373 __raw_writel(val, slave->regs + offset);
374}
375
8feb0a19
IK		 376struct cpsw_vector {
377 struct cpdma_chan *ch;
378 int budget;
379};
380
649a1688 381struct cpsw_common {
56e31bd8 382 struct device *dev;
606f3993 383 struct cpsw_platform_data data;
dbc4ec52
IK		 384 struct napi_struct napi_rx;
385 struct napi_struct napi_tx;
5d8d0d4d
IK		 386 struct cpsw_ss_regs __iomem *regs;
387 struct cpsw_wr_regs __iomem *wr_regs;
388 u8 __iomem *hw_stats;
389 struct cpsw_host_regs __iomem *host_port_regs;
2a05a622
IK		 390 u32 version;
391 u32 coal_intvl;
392 u32 bus_freq_mhz;
393 int rx_packet_max;
606f3993 394 struct cpsw_slave *slaves;
2c836bd9 395 struct cpdma_ctlr *dma;
8feb0a19
IK		 396 struct cpsw_vector txv[CPSW_MAX_QUEUES];
397 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
2a05a622 398 struct cpsw_ale *ale;
e38b5a3d
IK		 399 bool quirk_irq;
400 bool rx_irq_disabled;
401 bool tx_irq_disabled;
402 u32 irqs_table[IRQ_NUM];
2a05a622 403 struct cpts *cpts;
e05107e6 404 int rx_ch_num, tx_ch_num;
0be01b8e 405 int speed;
d5bc1613 406 int usage_count;
649a1688
IK		 407};
408
409struct cpsw_priv {
df828598 410 struct net_device *ndev;
df828598 411 struct device *dev;
df828598 412 u32 msg_enable;
df828598 413 u8 mac_addr[ETH_ALEN];
1923d6e4
M		 414 bool rx_pause;
415 bool tx_pause;
d9ba8f9e 416 u32 emac_port;
649a1688 417 struct cpsw_common *cpsw;
df828598
M		 418};
419
d9718546
M		 420struct cpsw_stats {
421 char stat_string[ETH_GSTRING_LEN];
422 int type;
423 int sizeof_stat;
424 int stat_offset;
425};
426
427enum {
428 CPSW_STATS,
429 CPDMA_RX_STATS,
430 CPDMA_TX_STATS,
431};
432
433#define CPSW_STAT(m) CPSW_STATS, \
434 sizeof(((struct cpsw_hw_stats *)0)->m), \
435 offsetof(struct cpsw_hw_stats, m)
436#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
437 sizeof(((struct cpdma_chan_stats *)0)->m), \
438 offsetof(struct cpdma_chan_stats, m)
439#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
440 sizeof(((struct cpdma_chan_stats *)0)->m), \
441 offsetof(struct cpdma_chan_stats, m)
442
443static const struct cpsw_stats cpsw_gstrings_stats[] = {
444 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
445 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
446 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
447 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
448 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
449 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
450 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
451 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
452 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
453 { "Rx Fragments", CPSW_STAT(rxfragments) },
454 { "Rx Octets", CPSW_STAT(rxoctets) },
455 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
456 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
457 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
458 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
459 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
460 { "Collisions", CPSW_STAT(txcollisionframes) },
461 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
462 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
463 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
464 { "Late Collisions", CPSW_STAT(txlatecollisions) },
465 { "Tx Underrun", CPSW_STAT(txunderrun) },
466 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
467 { "Tx Octets", CPSW_STAT(txoctets) },
468 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
469 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
470 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
471 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
472 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
473 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
474 { "Net Octets", CPSW_STAT(netoctets) },
475 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
476 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
477 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
d9718546
M		 478};
479
e05107e6
IK		 480static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
481 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
482 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
483 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
484 { "misqueued", CPDMA_RX_STAT(misqueued) },
485 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
486 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
487 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
488 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
489 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
490 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
491 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
492 { "requeue", CPDMA_RX_STAT(requeue) },
493 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
494};
495
496#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
497#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
d9718546 498
649a1688 499#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
dbc4ec52 500#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
d9ba8f9e
M		 501#define for_each_slave(priv, func, arg...) \
502 do { \
6e6ceaed 503 struct cpsw_slave *slave; \
606f3993 504 struct cpsw_common *cpsw = (priv)->cpsw; \
6e6ceaed 505 int n; \
606f3993
IK		 506 if (cpsw->data.dual_emac) \
507 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
d9ba8f9e 508 else \
606f3993
IK		 509 for (n = cpsw->data.slaves, \
510 slave = cpsw->slaves; \
6e6ceaed
SS		 511 n; n--) \
512 (func)(slave++, ##arg); \
d9ba8f9e 513 } while (0)
d9ba8f9e 514
2a05a622 515#define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
d9ba8f9e 516 do { \
606f3993 517 if (!cpsw->data.dual_emac) \
d9ba8f9e
M		 518 break; \
519 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
606f3993 520 ndev = cpsw->slaves[0].ndev; \
d9ba8f9e
M		 521 skb->dev = ndev; \
522 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
606f3993 523 ndev = cpsw->slaves[1].ndev; \
d9ba8f9e
M		 524 skb->dev = ndev; \
525 } \
df828598 526 } while (0)
606f3993 527#define cpsw_add_mcast(cpsw, priv, addr) \
d9ba8f9e 528 do { \
606f3993
IK		 529 if (cpsw->data.dual_emac) { \
530 struct cpsw_slave *slave = cpsw->slaves + \
d9ba8f9e 531 priv->emac_port; \
6f1f5836 532 int slave_port = cpsw_get_slave_port( \
d9ba8f9e 533 slave->slave_num); \
2a05a622 534 cpsw_ale_add_mcast(cpsw->ale, addr, \
71a2cbb7 535 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 536 ALE_VLAN, slave->port_vlan, 0); \
537 } else { \
2a05a622 538 cpsw_ale_add_mcast(cpsw->ale, addr, \
61f1cef9 539 ALE_ALL_PORTS, \
d9ba8f9e
M		 540 0, 0, 0); \
541 } \
542 } while (0)
543
6f1f5836 544static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 545{
71a2cbb7 546 return slave_num + 1;
d9ba8f9e 547}
df828598 548
0cd8f9cc
M		 549static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
550{
2a05a622
IK		 551 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
552 struct cpsw_ale *ale = cpsw->ale;
0cd8f9cc
M		 553 int i;
554
606f3993 555 if (cpsw->data.dual_emac) {
0cd8f9cc
M		 556 bool flag = false;
557
558 /* Enabling promiscuous mode for one interface will be
559 * common for both the interface as the interface shares
560 * the same hardware resource.
561 */
606f3993
IK		 562 for (i = 0; i < cpsw->data.slaves; i++)
563 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
0cd8f9cc
M		 564 flag = true;
565
566 if (!enable && flag) {
567 enable = true;
568 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
569 }
570
571 if (enable) {
572 /* Enable Bypass */
573 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
574
575 dev_dbg(&ndev->dev, "promiscuity enabled\n");
576 } else {
577 /* Disable Bypass */
578 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
579 dev_dbg(&ndev->dev, "promiscuity disabled\n");
580 }
581 } else {
582 if (enable) {
583 unsigned long timeout = jiffies + HZ;
584
6f979eb3 585 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 586 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 587 cpsw_ale_control_set(ale, i,
588 ALE_PORT_NOLEARN, 1);
589 cpsw_ale_control_set(ale, i,
590 ALE_PORT_NO_SA_UPDATE, 1);
591 }
592
593 /* Clear All Untouched entries */
594 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
595 do {
596 cpu_relax();
597 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
598 break;
599 } while (time_after(timeout, jiffies));
600 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
601
602 /* Clear all mcast from ALE */
61f1cef9 603 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 604
605 /* Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
607 dev_dbg(&ndev->dev, "promiscuity enabled\n");
608 } else {
6f979eb3 609 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 610 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
611
6f979eb3 612 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 613 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 614 cpsw_ale_control_set(ale, i,
615 ALE_PORT_NOLEARN, 0);
616 cpsw_ale_control_set(ale, i,
617 ALE_PORT_NO_SA_UPDATE, 0);
618 }
619 dev_dbg(&ndev->dev, "promiscuity disabled\n");
620 }
621 }
622}
623
5c50a856
M		 624static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
625{
626 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993 627 struct cpsw_common *cpsw = priv->cpsw;
25906052
M		 628 int vid;
629
606f3993
IK		 630 if (cpsw->data.dual_emac)
631 vid = cpsw->slaves[priv->emac_port].port_vlan;
25906052 632 else
606f3993 633 vid = cpsw->data.default_vlan;
5c50a856
M		 634
635 if (ndev->flags & IFF_PROMISC) {
636 /* Enable promiscuous mode */
0cd8f9cc 637 cpsw_set_promiscious(ndev, true);
2a05a622 638 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
5c50a856 639 return;
0cd8f9cc
M		 640 } else {
641 /* Disable promiscuous mode */
642 cpsw_set_promiscious(ndev, false);
5c50a856
M		 643 }
644
1e5c4bc4 645 /* Restore allmulti on vlans if necessary */
2a05a622 646 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
1e5c4bc4 647
5c50a856 648 /* Clear all mcast from ALE */
2a05a622 649 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 650
651 if (!netdev_mc_empty(ndev)) {
652 struct netdev_hw_addr *ha;
653
654 /* program multicast address list into ALE register */
655 netdev_for_each_mc_addr(ha, ndev) {
606f3993 656 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
5c50a856
M		 657 }
658 }
659}
660
2c836bd9 661static void cpsw_intr_enable(struct cpsw_common *cpsw)
df828598 662{
5d8d0d4d
IK		 663 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
664 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
df828598 665
2c836bd9 666 cpdma_ctlr_int_ctrl(cpsw->dma, true);
df828598
M		 667 return;
668}
669
2c836bd9 670static void cpsw_intr_disable(struct cpsw_common *cpsw)
df828598 671{
5d8d0d4d
IK		 672 __raw_writel(0, &cpsw->wr_regs->tx_en);
673 __raw_writel(0, &cpsw->wr_regs->rx_en);
df828598 674
2c836bd9 675 cpdma_ctlr_int_ctrl(cpsw->dma, false);
df828598
M		 676 return;
677}
678
1a3b5056 679static void cpsw_tx_handler(void *token, int len, int status)
df828598 680{
e05107e6 681 struct netdev_queue *txq;
df828598
M		 682 struct sk_buff *skb = token;
683 struct net_device *ndev = skb->dev;
2a05a622 684 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 685
fae50823
M		 686 /* Check whether the queue is stopped due to stalled tx dma, if the
687 * queue is stopped then start the queue as we have free desc for tx
688 */
e05107e6
IK		 689 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
690 if (unlikely(netif_tx_queue_stopped(txq)))
691 netif_tx_wake_queue(txq);
692
2a05a622 693 cpts_tx_timestamp(cpsw->cpts, skb);
8dc43ddc
TK		 694 ndev->stats.tx_packets++;
695 ndev->stats.tx_bytes += len;
df828598
M		 696 dev_kfree_skb_any(skb);
697}
698
1a3b5056 699static void cpsw_rx_handler(void *token, int len, int status)
df828598 700{
e05107e6 701 struct cpdma_chan *ch;
df828598 702 struct sk_buff *skb = token;
b4727e69 703 struct sk_buff *new_skb;
df828598 704 struct net_device *ndev = skb->dev;
df828598 705 int ret = 0;
2a05a622 706 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 707
2a05a622 708 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
d9ba8f9e 709
16e5c57d 710 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
fe734d0a 711 /* In dual emac mode check for all interfaces */
d5bc1613 712 if (cpsw->data.dual_emac && cpsw->usage_count &&
fe734d0a 713 (status >= 0)) {
a0e2c822
M		 714 /* The packet received is for the interface which
715 * is already down and the other interface is up
dbedd44e 716 * and running, instead of freeing which results
a0e2c822
M		 717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
719 */
720 new_skb = skb;
721 goto requeue;
722 }
723
b4727e69 724 /* the interface is going down, skbs are purged */
df828598
M		 725 dev_kfree_skb_any(skb);
726 return;
727 }
b4727e69 728
2a05a622 729 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
b4727e69 730 if (new_skb) {
e05107e6 731 skb_copy_queue_mapping(new_skb, skb);
df828598 732 skb_put(skb, len);
2a05a622 733 cpts_rx_timestamp(cpsw->cpts, skb);
df828598
M		 734 skb->protocol = eth_type_trans(skb, ndev);
735 netif_receive_skb(skb);
8dc43ddc
TK		 736 ndev->stats.rx_bytes += len;
737 ndev->stats.rx_packets++;
254a49d5 738 kmemleak_not_leak(new_skb);
b4727e69 739 } else {
8dc43ddc 740 ndev->stats.rx_dropped++;
b4727e69 741 new_skb = skb;
df828598
M		 742 }
743
a0e2c822 744requeue:
ce52c744
IK		 745 if (netif_dormant(ndev)) {
746 dev_kfree_skb_any(new_skb);
747 return;
748 }
749
8feb0a19 750 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
e05107e6 751 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
2c836bd9 752 skb_tailroom(new_skb), 0);
b4727e69
SS		 753 if (WARN_ON(ret < 0))
754 dev_kfree_skb_any(new_skb);
df828598
M		 755}
756
32b78d85 757static void cpsw_split_res(struct net_device *ndev)
48e0a83e
IK		 758{
759 struct cpsw_priv *priv = netdev_priv(ndev);
32b78d85 760 u32 consumed_rate = 0, bigest_rate = 0;
48e0a83e
IK		 761 struct cpsw_common *cpsw = priv->cpsw;
762 struct cpsw_vector *txv = cpsw->txv;
32b78d85 763 int i, ch_weight, rlim_ch_num = 0;
48e0a83e 764 int budget, bigest_rate_ch = 0;
48e0a83e
IK		 765 u32 ch_rate, max_rate;
766 int ch_budget = 0;
767
48e0a83e
IK		 768 for (i = 0; i < cpsw->tx_ch_num; i++) {
769 ch_rate = cpdma_chan_get_rate(txv[i].ch);
770 if (!ch_rate)
771 continue;
772
773 rlim_ch_num++;
774 consumed_rate += ch_rate;
775 }
776
777 if (cpsw->tx_ch_num == rlim_ch_num) {
778 max_rate = consumed_rate;
32b78d85
IK		 779 } else if (!rlim_ch_num) {
780 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
781 bigest_rate = 0;
782 max_rate = consumed_rate;
48e0a83e 783 } else {
0be01b8e
IK		 784 max_rate = cpsw->speed * 1000;
785
786 /* if max_rate is less then expected due to reduced link speed,
787 * split proportionally according next potential max speed
788 */
789 if (max_rate < consumed_rate)
790 max_rate *= 10;
791
792 if (max_rate < consumed_rate)
793 max_rate *= 10;
32b78d85 794
48e0a83e
IK		 795 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
796 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
797 (cpsw->tx_ch_num - rlim_ch_num);
798 bigest_rate = (max_rate - consumed_rate) /
799 (cpsw->tx_ch_num - rlim_ch_num);
800 }
801
32b78d85 802 /* split tx weight/budget */
48e0a83e
IK		 803 budget = CPSW_POLL_WEIGHT;
804 for (i = 0; i < cpsw->tx_ch_num; i++) {
805 ch_rate = cpdma_chan_get_rate(txv[i].ch);
806 if (ch_rate) {
807 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
808 if (!txv[i].budget)
32b78d85 809 txv[i].budget++;
48e0a83e
IK		 810 if (ch_rate > bigest_rate) {
811 bigest_rate_ch = i;
812 bigest_rate = ch_rate;
813 }
32b78d85
IK		 814
815 ch_weight = (ch_rate * 100) / max_rate;
816 if (!ch_weight)
817 ch_weight++;
818 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
48e0a83e
IK		 819 } else {
820 txv[i].budget = ch_budget;
821 if (!bigest_rate_ch)
822 bigest_rate_ch = i;
32b78d85 823 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
48e0a83e
IK		 824 }
825
826 budget -= txv[i].budget;
827 }
828
829 if (budget)
830 txv[bigest_rate_ch].budget += budget;
831
832 /* split rx budget */
833 budget = CPSW_POLL_WEIGHT;
834 ch_budget = budget / cpsw->rx_ch_num;
835 for (i = 0; i < cpsw->rx_ch_num; i++) {
836 cpsw->rxv[i].budget = ch_budget;
837 budget -= ch_budget;
838 }
839
840 if (budget)
841 cpsw->rxv[0].budget += budget;
842}
843
c03abd84 844static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598 845{
dbc4ec52 846 struct cpsw_common *cpsw = dev_id;
7ce67a38 847
5d8d0d4d 848 writel(0, &cpsw->wr_regs->tx_en);
2c836bd9 849 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
c03abd84 850
e38b5a3d
IK		 851 if (cpsw->quirk_irq) {
852 disable_irq_nosync(cpsw->irqs_table[1]);
853 cpsw->tx_irq_disabled = true;
7da11600
M		 854 }
855
dbc4ec52 856 napi_schedule(&cpsw->napi_tx);
c03abd84
FB		 857 return IRQ_HANDLED;
858}
859
860static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
861{
dbc4ec52 862 struct cpsw_common *cpsw = dev_id;
c03abd84 863
2c836bd9 864 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
5d8d0d4d 865 writel(0, &cpsw->wr_regs->rx_en);
fd51cf19 866
e38b5a3d
IK		 867 if (cpsw->quirk_irq) {
868 disable_irq_nosync(cpsw->irqs_table[0]);
869 cpsw->rx_irq_disabled = true;
7da11600
M		 870 }
871
dbc4ec52 872 napi_schedule(&cpsw->napi_rx);
d354eb85 873 return IRQ_HANDLED;
df828598
M		 874}
875
32a7432c
M		 876static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
877{
e05107e6 878 u32 ch_map;
8feb0a19 879 int num_tx, cur_budget, ch;
dbc4ec52 880 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
8feb0a19 881 struct cpsw_vector *txv;
32a7432c 882
e05107e6
IK		 883 /* process every unprocessed channel */
884 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
342934a5 885 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
e05107e6
IK		 886 if (!(ch_map & 0x01))
887 continue;
888
8feb0a19
IK		 889 txv = &cpsw->txv[ch];
890 if (unlikely(txv->budget > budget - num_tx))
891 cur_budget = budget - num_tx;
892 else
893 cur_budget = txv->budget;
894
895 num_tx += cpdma_chan_process(txv->ch, cur_budget);
342934a5
IK		 896 if (num_tx >= budget)
897 break;
e05107e6
IK		 898 }
899
32a7432c
M		 900 if (num_tx < budget) {
901 napi_complete(napi_tx);
5d8d0d4d 902 writel(0xff, &cpsw->wr_regs->tx_en);
e38b5a3d
IK		 903 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
904 cpsw->tx_irq_disabled = false;
905 enable_irq(cpsw->irqs_table[1]);
7da11600 906 }
32a7432c
M		 907 }
908
32a7432c
M		 909 return num_tx;
910}
911
912static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 913{
e05107e6 914 u32 ch_map;
8feb0a19 915 int num_rx, cur_budget, ch;
dbc4ec52 916 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
8feb0a19 917 struct cpsw_vector *rxv;
df828598 918
e05107e6
IK		 919 /* process every unprocessed channel */
920 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
342934a5 921 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
e05107e6
IK		 922 if (!(ch_map & 0x01))
923 continue;
924
8feb0a19
IK		 925 rxv = &cpsw->rxv[ch];
926 if (unlikely(rxv->budget > budget - num_rx))
927 cur_budget = budget - num_rx;
928 else
929 cur_budget = rxv->budget;
930
931 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
342934a5
IK		 932 if (num_rx >= budget)
933 break;
e05107e6
IK		 934 }
935
df828598 936 if (num_rx < budget) {
6ad20165 937 napi_complete_done(napi_rx, num_rx);
5d8d0d4d 938 writel(0xff, &cpsw->wr_regs->rx_en);
e38b5a3d
IK		 939 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
940 cpsw->rx_irq_disabled = false;
941 enable_irq(cpsw->irqs_table[0]);
7da11600 942 }
df828598
M		 943 }
944
945 return num_rx;
946}
947
948static inline void soft_reset(const char *module, void __iomem *reg)
949{
950 unsigned long timeout = jiffies + HZ;
951
952 __raw_writel(1, reg);
953 do {
954 cpu_relax();
955 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
956
957 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
958}
959
960#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
961 ((mac)[2] << 16) | ((mac)[3] << 24))
962#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
963
964static void cpsw_set_slave_mac(struct cpsw_slave *slave,
965 struct cpsw_priv *priv)
966{
9750a3ad
RC		 967 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
968 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 969}
970
971static void _cpsw_adjust_link(struct cpsw_slave *slave,
972 struct cpsw_priv *priv, bool *link)
973{
974 struct phy_device *phy = slave->phy;
975 u32 mac_control = 0;
976 u32 slave_port;
606f3993 977 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 978
979 if (!phy)
980 return;
981
6f1f5836 982 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 983
984 if (phy->link) {
606f3993 985 mac_control = cpsw->data.mac_control;
df828598
M		 986
987 /* enable forwarding */
2a05a622 988 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 989 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
990
991 if (phy->speed == 1000)
992 mac_control |= BIT(7); /* GIGABITEN */
993 if (phy->duplex)
994 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 995
996 /* set speed_in input in case RMII mode is used in 100Mbps */
997 if (phy->speed == 100)
998 mac_control |= BIT(15);
a81d8762
M		 999 else if (phy->speed == 10)
1000 mac_control |= BIT(18); /* In Band mode */
342b7b74 1001
1923d6e4
M		 1002 if (priv->rx_pause)
1003 mac_control |= BIT(3);
1004
1005 if (priv->tx_pause)
1006 mac_control |= BIT(4);
1007
df828598
M		 1008 *link = true;
1009 } else {
1010 mac_control = 0;
1011 /* disable forwarding */
2a05a622 1012 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 1013 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1014 }
1015
1016 if (mac_control != slave->mac_control) {
1017 phy_print_status(phy);
1018 __raw_writel(mac_control, &slave->sliver->mac_control);
1019 }
1020
1021 slave->mac_control = mac_control;
1022}
1023
0be01b8e
IK		 1024static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1025{
1026 int i, speed;
1027
1028 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1029 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1030 speed += cpsw->slaves[i].phy->speed;
1031
1032 return speed;
1033}
1034
1035static int cpsw_need_resplit(struct cpsw_common *cpsw)
1036{
1037 int i, rlim_ch_num;
1038 int speed, ch_rate;
1039
1040 /* re-split resources only in case speed was changed */
1041 speed = cpsw_get_common_speed(cpsw);
1042 if (speed == cpsw->speed || !speed)
1043 return 0;
1044
1045 cpsw->speed = speed;
1046
1047 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1048 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1049 if (!ch_rate)
1050 break;
1051
1052 rlim_ch_num++;
1053 }
1054
1055 /* cases not dependent on speed */
1056 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1057 return 0;
1058
1059 return 1;
1060}
1061
df828598
M		 1062static void cpsw_adjust_link(struct net_device *ndev)
1063{
1064 struct cpsw_priv *priv = netdev_priv(ndev);
0be01b8e 1065 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1066 bool link = false;
1067
1068 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1069
1070 if (link) {
0be01b8e
IK		 1071 if (cpsw_need_resplit(cpsw))
1072 cpsw_split_res(ndev);
1073
df828598
M		 1074 netif_carrier_on(ndev);
1075 if (netif_running(ndev))
e05107e6 1076 netif_tx_wake_all_queues(ndev);
df828598
M		 1077 } else {
1078 netif_carrier_off(ndev);
e05107e6 1079 netif_tx_stop_all_queues(ndev);
df828598
M		 1080 }
1081}
1082
ff5b8ef2
M		 1083static int cpsw_get_coalesce(struct net_device *ndev,
1084 struct ethtool_coalesce *coal)
1085{
2a05a622 1086 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
ff5b8ef2 1087
2a05a622 1088 coal->rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 1089 return 0;
1090}
1091
1092static int cpsw_set_coalesce(struct net_device *ndev,
1093 struct ethtool_coalesce *coal)
1094{
1095 struct cpsw_priv *priv = netdev_priv(ndev);
1096 u32 int_ctrl;
1097 u32 num_interrupts = 0;
1098 u32 prescale = 0;
1099 u32 addnl_dvdr = 1;
1100 u32 coal_intvl = 0;
5d8d0d4d 1101 struct cpsw_common *cpsw = priv->cpsw;
ff5b8ef2 1102
ff5b8ef2
M		 1103 coal_intvl = coal->rx_coalesce_usecs;
1104
5d8d0d4d 1105 int_ctrl = readl(&cpsw->wr_regs->int_control);
2a05a622 1106 prescale = cpsw->bus_freq_mhz * 4;
ff5b8ef2 1107
a84bc2a9
M		 1108 if (!coal->rx_coalesce_usecs) {
1109 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1110 goto update_return;
1111 }
1112
ff5b8ef2
M		 1113 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1114 coal_intvl = CPSW_CMINTMIN_INTVL;
1115
1116 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1117 /* Interrupt pacer works with 4us Pulse, we can
1118 * throttle further by dilating the 4us pulse.
1119 */
1120 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1121
1122 if (addnl_dvdr > 1) {
1123 prescale *= addnl_dvdr;
1124 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1125 coal_intvl = (CPSW_CMINTMAX_INTVL
1126 * addnl_dvdr);
1127 } else {
1128 addnl_dvdr = 1;
1129 coal_intvl = CPSW_CMINTMAX_INTVL;
1130 }
1131 }
1132
1133 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
5d8d0d4d
IK		 1134 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1135 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
ff5b8ef2
M		 1136
1137 int_ctrl |= CPSW_INTPACEEN;
1138 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1139 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 1140
1141update_return:
5d8d0d4d 1142 writel(int_ctrl, &cpsw->wr_regs->int_control);
ff5b8ef2
M		 1143
1144 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
2a05a622 1145 cpsw->coal_intvl = coal_intvl;
ff5b8ef2
M		 1146
1147 return 0;
1148}
1149
d9718546
M		 1150static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1151{
e05107e6
IK		 1152 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1153
d9718546
M		 1154 switch (sset) {
1155 case ETH_SS_STATS:
e05107e6
IK		 1156 return (CPSW_STATS_COMMON_LEN +
1157 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1158 CPSW_STATS_CH_LEN);
d9718546
M		 1159 default:
1160 return -EOPNOTSUPP;
1161 }
1162}
1163
e05107e6
IK		 1164static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1165{
1166 int ch_stats_len;
1167 int line;
1168 int i;
1169
1170 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1171 for (i = 0; i < ch_stats_len; i++) {
1172 line = i % CPSW_STATS_CH_LEN;
1173 snprintf(*p, ETH_GSTRING_LEN,
1174 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1175 i / CPSW_STATS_CH_LEN,
1176 cpsw_gstrings_ch_stats[line].stat_string);
1177 *p += ETH_GSTRING_LEN;
1178 }
1179}
1180
d9718546
M		 1181static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1182{
e05107e6 1183 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
d9718546
M		 1184 u8 *p = data;
1185 int i;
1186
1187 switch (stringset) {
1188 case ETH_SS_STATS:
e05107e6 1189 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
d9718546
M		 1190 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1191 ETH_GSTRING_LEN);
1192 p += ETH_GSTRING_LEN;
1193 }
e05107e6
IK		 1194
1195 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1196 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
d9718546
M		 1197 break;
1198 }
1199}
1200
1201static void cpsw_get_ethtool_stats(struct net_device *ndev,
1202 struct ethtool_stats *stats, u64 *data)
1203{
d9718546 1204 u8 *p;
2c836bd9 1205 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
e05107e6
IK		 1206 struct cpdma_chan_stats ch_stats;
1207 int i, l, ch;
d9718546
M		 1208
1209 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
e05107e6
IK		 1210 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1211 data[l] = readl(cpsw->hw_stats +
1212 cpsw_gstrings_stats[l].stat_offset);
1213
1214 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
8feb0a19 1215 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
e05107e6
IK		 1216 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1217 p = (u8 *)&ch_stats +
1218 cpsw_gstrings_ch_stats[i].stat_offset;
1219 data[l] = *(u32 *)p;
1220 }
1221 }
d9718546 1222
e05107e6 1223 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
8feb0a19 1224 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
e05107e6
IK		 1225 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1226 p = (u8 *)&ch_stats +
1227 cpsw_gstrings_ch_stats[i].stat_offset;
1228 data[l] = *(u32 *)p;
d9718546
M		 1229 }
1230 }
1231}
1232
27e9e103 1233static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
e05107e6
IK		 1234 struct sk_buff *skb,
1235 struct cpdma_chan *txch)
d9ba8f9e 1236{
2c836bd9
IK		 1237 struct cpsw_common *cpsw = priv->cpsw;
1238
98fdd857 1239 skb_tx_timestamp(skb);
e05107e6 1240 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
606f3993 1241 priv->emac_port + cpsw->data.dual_emac);
d9ba8f9e
M		 1242}
1243
1244static inline void cpsw_add_dual_emac_def_ale_entries(
1245 struct cpsw_priv *priv, struct cpsw_slave *slave,
1246 u32 slave_port)
1247{
2a05a622 1248 struct cpsw_common *cpsw = priv->cpsw;
71a2cbb7 1249 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e 1250
2a05a622 1251 if (cpsw->version == CPSW_VERSION_1)
d9ba8f9e
M		 1252 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1253 else
1254 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
2a05a622 1255 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
d9ba8f9e 1256 port_mask, port_mask, 0);
2a05a622 1257 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1258 port_mask, ALE_VLAN, slave->port_vlan, 0);
2a05a622
IK		 1259 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1260 HOST_PORT_NUM, ALE_VLAN |
1261 ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1262}
1263
1e7a2e21 1264static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1265{
1266 char name[32];
df828598 1267
1e7a2e21 1268 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1269 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1270}
1271
1272static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1273{
1274 u32 slave_port;
30c57f07 1275 struct phy_device *phy;
649a1688 1276 struct cpsw_common *cpsw = priv->cpsw;
1e7a2e21
DM		 1277
1278 soft_reset_slave(slave);
df828598
M		 1279
1280 /* setup priority mapping */
1281 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad 1282
2a05a622 1283 switch (cpsw->version) {
9750a3ad
RC		 1284 case CPSW_VERSION_1:
1285 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
48f5bccc
GS		 1286 /* Increase RX FIFO size to 5 for supporting fullduplex
1287 * flow control mode
1288 */
1289 slave_write(slave,
1290 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1291 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
9750a3ad
RC		 1292 break;
1293 case CPSW_VERSION_2:
c193f365 1294 case CPSW_VERSION_3:
926489be 1295 case CPSW_VERSION_4:
9750a3ad 1296 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
48f5bccc
GS		 1297 /* Increase RX FIFO size to 5 for supporting fullduplex
1298 * flow control mode
1299 */
1300 slave_write(slave,
1301 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1302 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
9750a3ad
RC		 1303 break;
1304 }
df828598
M		 1305
1306 /* setup max packet size, and mac address */
2a05a622 1307 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
df828598
M		 1308 cpsw_set_slave_mac(slave, priv);
1309
1310 slave->mac_control = 0; /* no link yet */
1311
6f1f5836 1312 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1313
606f3993 1314 if (cpsw->data.dual_emac)
d9ba8f9e
M		 1315 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1316 else
2a05a622 1317 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1318 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1319
d733f754 1320 if (slave->data->phy_node) {
30c57f07 1321 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1322 &cpsw_adjust_link, 0, slave->data->phy_if);
30c57f07 1323 if (!phy) {
d733f754
DR		 1324 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1325 slave->data->phy_node->full_name,
1326 slave->slave_num);
1327 return;
1328 }
1329 } else {
30c57f07 1330 phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1331 &cpsw_adjust_link, slave->data->phy_if);
30c57f07 1332 if (IS_ERR(phy)) {
d733f754
DR		 1333 dev_err(priv->dev,
1334 "phy \"%s\" not found on slave %d, err %ld\n",
1335 slave->data->phy_id, slave->slave_num,
30c57f07 1336 PTR_ERR(phy));
d733f754
DR		 1337 return;
1338 }
1339 }
2220943a 1340
30c57f07
SN		 1341 slave->phy = phy;
1342
d733f754 1343 phy_attached_info(slave->phy);
388367a5 1344
d733f754
DR		 1345 phy_start(slave->phy);
1346
1347 /* Configure GMII_SEL register */
56e31bd8 1348 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1349}
1350
3b72c2fe
M		 1351static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1352{
606f3993
IK		 1353 struct cpsw_common *cpsw = priv->cpsw;
1354 const int vlan = cpsw->data.default_vlan;
3b72c2fe
M		 1355 u32 reg;
1356 int i;
1e5c4bc4 1357 int unreg_mcast_mask;
3b72c2fe 1358
2a05a622 1359 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
3b72c2fe
M		 1360 CPSW2_PORT_VLAN;
1361
5d8d0d4d 1362 writel(vlan, &cpsw->host_port_regs->port_vlan);
3b72c2fe 1363
606f3993
IK		 1364 for (i = 0; i < cpsw->data.slaves; i++)
1365 slave_write(cpsw->slaves + i, vlan, reg);
3b72c2fe 1366
1e5c4bc4
LS		 1367 if (priv->ndev->flags & IFF_ALLMULTI)
1368 unreg_mcast_mask = ALE_ALL_PORTS;
1369 else
1370 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1371
2a05a622 1372 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
61f1cef9
GS		 1373 ALE_ALL_PORTS, ALE_ALL_PORTS,
1374 unreg_mcast_mask);
3b72c2fe
M		 1375}
1376
df828598
M		 1377static void cpsw_init_host_port(struct cpsw_priv *priv)
1378{
d9ba8f9e 1379 u32 fifo_mode;
5d8d0d4d
IK		 1380 u32 control_reg;
1381 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe 1382
df828598 1383 /* soft reset the controller and initialize ale */
5d8d0d4d 1384 soft_reset("cpsw", &cpsw->regs->soft_reset);
2a05a622 1385 cpsw_ale_start(cpsw->ale);
df828598
M		 1386
1387 /* switch to vlan unaware mode */
2a05a622 1388 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe 1389 CPSW_ALE_VLAN_AWARE);
5d8d0d4d 1390 control_reg = readl(&cpsw->regs->control);
3b72c2fe 1391 control_reg |= CPSW_VLAN_AWARE;
5d8d0d4d 1392 writel(control_reg, &cpsw->regs->control);
606f3993 1393 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
d9ba8f9e 1394 CPSW_FIFO_NORMAL_MODE;
5d8d0d4d 1395 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
df828598
M		 1396
1397 /* setup host port priority mapping */
1398 __raw_writel(CPDMA_TX_PRIORITY_MAP,
5d8d0d4d
IK		 1399 &cpsw->host_port_regs->cpdma_tx_pri_map);
1400 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
df828598 1401
2a05a622 1402 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
df828598
M		 1403 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1404
606f3993 1405 if (!cpsw->data.dual_emac) {
2a05a622 1406 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e 1407 0, 0);
2a05a622 1408 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
71a2cbb7 1409 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1410 }
df828598
M		 1411}
1412
3802dce1
IK		 1413static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1414{
1415 struct cpsw_common *cpsw = priv->cpsw;
1416 struct sk_buff *skb;
1417 int ch_buf_num;
e05107e6
IK		 1418 int ch, i, ret;
1419
1420 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
8feb0a19 1421 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
e05107e6
IK		 1422 for (i = 0; i < ch_buf_num; i++) {
1423 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1424 cpsw->rx_packet_max,
1425 GFP_KERNEL);
1426 if (!skb) {
1427 cpsw_err(priv, ifup, "cannot allocate skb\n");
1428 return -ENOMEM;
1429 }
3802dce1 1430
e05107e6 1431 skb_set_queue_mapping(skb, ch);
8feb0a19
IK		 1432 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1433 skb->data, skb_tailroom(skb),
1434 0);
e05107e6
IK		 1435 if (ret < 0) {
1436 cpsw_err(priv, ifup,
1437 "cannot submit skb to channel %d rx, error %d\n",
1438 ch, ret);
1439 kfree_skb(skb);
1440 return ret;
1441 }
1442 kmemleak_not_leak(skb);
3802dce1 1443 }
3802dce1 1444
e05107e6
IK		 1445 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1446 ch, ch_buf_num);
1447 }
3802dce1 1448
e05107e6 1449 return 0;
3802dce1
IK		 1450}
1451
2a05a622 1452static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
aacebbf8 1453{
3995d265
SP		 1454 u32 slave_port;
1455
6f1f5836 1456 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1457
aacebbf8
SS		 1458 if (!slave->phy)
1459 return;
1460 phy_stop(slave->phy);
1461 phy_disconnect(slave->phy);
1462 slave->phy = NULL;
2a05a622 1463 cpsw_ale_control_set(cpsw->ale, slave_port,
3995d265 1464 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1465 soft_reset_slave(slave);
aacebbf8
SS		 1466}
1467
df828598
M		 1468static int cpsw_ndo_open(struct net_device *ndev)
1469{
1470 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1471 struct cpsw_common *cpsw = priv->cpsw;
3802dce1 1472 int ret;
df828598
M		 1473 u32 reg;
1474
56e31bd8 1475 ret = pm_runtime_get_sync(cpsw->dev);
108a6537 1476 if (ret < 0) {
56e31bd8 1477 pm_runtime_put_noidle(cpsw->dev);
108a6537
GS		 1478 return ret;
1479 }
3fa88c51 1480
df828598
M		 1481 netif_carrier_off(ndev);
1482
e05107e6
IK		 1483 /* Notify the stack of the actual queue counts. */
1484 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1485 if (ret) {
1486 dev_err(priv->dev, "cannot set real number of tx queues\n");
1487 goto err_cleanup;
1488 }
1489
1490 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1491 if (ret) {
1492 dev_err(priv->dev, "cannot set real number of rx queues\n");
1493 goto err_cleanup;
1494 }
1495
2a05a622 1496 reg = cpsw->version;
df828598
M		 1497
1498 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1499 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1500 CPSW_RTL_VERSION(reg));
1501
d5bc1613
IK		 1502 /* Initialize host and slave ports */
1503 if (!cpsw->usage_count)
d9ba8f9e 1504 cpsw_init_host_port(priv);
df828598
M		 1505 for_each_slave(priv, cpsw_slave_open, priv);
1506
3b72c2fe 1507 /* Add default VLAN */
606f3993 1508 if (!cpsw->data.dual_emac)
e6afea0b
M		 1509 cpsw_add_default_vlan(priv);
1510 else
2a05a622 1511 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
61f1cef9 1512 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1513
d5bc1613
IK		 1514 /* initialize shared resources for every ndev */
1515 if (!cpsw->usage_count) {
d9ba8f9e 1516 /* disable priority elevation */
5d8d0d4d 1517 __raw_writel(0, &cpsw->regs->ptype);
df828598 1518
d9ba8f9e 1519 /* enable statistics collection only on all ports */
5d8d0d4d 1520 __raw_writel(0x7, &cpsw->regs->stat_port_en);
df828598 1521
1923d6e4 1522 /* Enable internal fifo flow control */
5d8d0d4d 1523 writel(0x7, &cpsw->regs->flow_control);
1923d6e4 1524
dbc4ec52
IK		 1525 napi_enable(&cpsw->napi_rx);
1526 napi_enable(&cpsw->napi_tx);
d354eb85 1527
e38b5a3d
IK		 1528 if (cpsw->tx_irq_disabled) {
1529 cpsw->tx_irq_disabled = false;
1530 enable_irq(cpsw->irqs_table[1]);
7da11600
M		 1531 }
1532
e38b5a3d
IK		 1533 if (cpsw->rx_irq_disabled) {
1534 cpsw->rx_irq_disabled = false;
1535 enable_irq(cpsw->irqs_table[0]);
7da11600
M		 1536 }
1537
3802dce1
IK		 1538 ret = cpsw_fill_rx_channels(priv);
1539 if (ret < 0)
1540 goto err_cleanup;
f280e89a 1541
8a2c9a5a 1542 if (cpts_register(cpsw->cpts))
f280e89a
M		 1543 dev_err(priv->dev, "error registering cpts device\n");
1544
df828598 1545 }
df828598 1546
ff5b8ef2 1547 /* Enable Interrupt pacing if configured */
2a05a622 1548 if (cpsw->coal_intvl != 0) {
ff5b8ef2
M		 1549 struct ethtool_coalesce coal;
1550
2a05a622 1551 coal.rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 1552 cpsw_set_coalesce(ndev, &coal);
1553 }
1554
2c836bd9
IK		 1555 cpdma_ctlr_start(cpsw->dma);
1556 cpsw_intr_enable(cpsw);
d5bc1613 1557 cpsw->usage_count++;
f63a975e 1558
df828598 1559 return 0;
df828598 1560
aacebbf8 1561err_cleanup:
2c836bd9 1562 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1563 for_each_slave(priv, cpsw_slave_stop, cpsw);
56e31bd8 1564 pm_runtime_put_sync(cpsw->dev);
aacebbf8
SS		 1565 netif_carrier_off(priv->ndev);
1566 return ret;
df828598
M		 1567}
1568
1569static int cpsw_ndo_stop(struct net_device *ndev)
1570{
1571 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1572 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1573
1574 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
e05107e6 1575 netif_tx_stop_all_queues(priv->ndev);
df828598 1576 netif_carrier_off(priv->ndev);
d9ba8f9e 1577
d5bc1613 1578 if (cpsw->usage_count <= 1) {
dbc4ec52
IK		 1579 napi_disable(&cpsw->napi_rx);
1580 napi_disable(&cpsw->napi_tx);
2a05a622 1581 cpts_unregister(cpsw->cpts);
2c836bd9
IK		 1582 cpsw_intr_disable(cpsw);
1583 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1584 cpsw_ale_stop(cpsw->ale);
d9ba8f9e 1585 }
2a05a622 1586 for_each_slave(priv, cpsw_slave_stop, cpsw);
0be01b8e
IK		 1587
1588 if (cpsw_need_resplit(cpsw))
1589 cpsw_split_res(ndev);
1590
d5bc1613 1591 cpsw->usage_count--;
56e31bd8 1592 pm_runtime_put_sync(cpsw->dev);
df828598
M		 1593 return 0;
1594}
1595
1596static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1597 struct net_device *ndev)
1598{
1599 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1600 struct cpsw_common *cpsw = priv->cpsw;
f44f8417 1601 struct cpts *cpts = cpsw->cpts;
e05107e6
IK		 1602 struct netdev_queue *txq;
1603 struct cpdma_chan *txch;
1604 int ret, q_idx;
df828598 1605
df828598
M		 1606 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1607 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1608 ndev->stats.tx_dropped++;
1bf96050 1609 return NET_XMIT_DROP;
df828598
M		 1610 }
1611
9232b16d 1612 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
f44f8417 1613 cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
2e5b38ab
RC		 1614 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1615
e05107e6
IK		 1616 q_idx = skb_get_queue_mapping(skb);
1617 if (q_idx >= cpsw->tx_ch_num)
1618 q_idx = q_idx % cpsw->tx_ch_num;
1619
8feb0a19 1620 txch = cpsw->txv[q_idx].ch;
e05107e6 1621 ret = cpsw_tx_packet_submit(priv, skb, txch);
df828598
M		 1622 if (unlikely(ret != 0)) {
1623 cpsw_err(priv, tx_err, "desc submit failed\n");
1624 goto fail;
1625 }
1626
fae50823
M		 1627 /* If there is no more tx desc left free then we need to
1628 * tell the kernel to stop sending us tx frames.
1629 */
e05107e6
IK		 1630 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1631 txq = netdev_get_tx_queue(ndev, q_idx);
1632 netif_tx_stop_queue(txq);
1633 }
fae50823 1634
df828598
M		 1635 return NETDEV_TX_OK;
1636fail:
8dc43ddc 1637 ndev->stats.tx_dropped++;
e05107e6
IK		 1638 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1639 netif_tx_stop_queue(txq);
df828598
M		 1640 return NETDEV_TX_BUSY;
1641}
1642
c8395d4e 1643#if IS_ENABLED(CONFIG_TI_CPTS)
2e5b38ab 1644
2a05a622 1645static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2e5b38ab 1646{
606f3993 1647 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2e5b38ab
RC		 1648 u32 ts_en, seq_id;
1649
b63ba58e
GS		 1650 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1651 !cpts_is_rx_enabled(cpsw->cpts)) {
2e5b38ab
RC		 1652 slave_write(slave, 0, CPSW1_TS_CTL);
1653 return;
1654 }
1655
1656 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1657 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1658
b63ba58e 1659 if (cpts_is_tx_enabled(cpsw->cpts))
2e5b38ab
RC		 1660 ts_en |= CPSW_V1_TS_TX_EN;
1661
b63ba58e 1662 if (cpts_is_rx_enabled(cpsw->cpts))
2e5b38ab
RC		 1663 ts_en |= CPSW_V1_TS_RX_EN;
1664
1665 slave_write(slave, ts_en, CPSW1_TS_CTL);
1666 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1667}
1668
1669static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1670{
d9ba8f9e 1671 struct cpsw_slave *slave;
5d8d0d4d 1672 struct cpsw_common *cpsw = priv->cpsw;
2e5b38ab
RC		 1673 u32 ctrl, mtype;
1674
cb7d78d0 1675 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
d9ba8f9e 1676
2e5b38ab 1677 ctrl = slave_read(slave, CPSW2_CONTROL);
2a05a622 1678 switch (cpsw->version) {
09c55372
GC		 1679 case CPSW_VERSION_2:
1680 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1681
b63ba58e 1682 if (cpts_is_tx_enabled(cpsw->cpts))
09c55372 1683 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1684
b63ba58e 1685 if (cpts_is_rx_enabled(cpsw->cpts))
09c55372 1686 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1687 break;
09c55372
GC		 1688 case CPSW_VERSION_3:
1689 default:
1690 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1691
b63ba58e 1692 if (cpts_is_tx_enabled(cpsw->cpts))
09c55372
GC		 1693 ctrl |= CTRL_V3_TX_TS_BITS;
1694
b63ba58e 1695 if (cpts_is_rx_enabled(cpsw->cpts))
09c55372 1696 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1697 break;
09c55372 1698 }
2e5b38ab
RC		 1699
1700 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1701
1702 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1703 slave_write(slave, ctrl, CPSW2_CONTROL);
5d8d0d4d 1704 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
2e5b38ab
RC		 1705}
1706
a5b4145b 1707static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1708{
3177bf6f 1709 struct cpsw_priv *priv = netdev_priv(dev);
2e5b38ab 1710 struct hwtstamp_config cfg;
2a05a622
IK		 1711 struct cpsw_common *cpsw = priv->cpsw;
1712 struct cpts *cpts = cpsw->cpts;
2e5b38ab 1713
2a05a622
IK		 1714 if (cpsw->version != CPSW_VERSION_1 &&
1715 cpsw->version != CPSW_VERSION_2 &&
1716 cpsw->version != CPSW_VERSION_3)
2ee91e54
BH		 1717 return -EOPNOTSUPP;
1718
2e5b38ab
RC		 1719 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1720 return -EFAULT;
1721
1722 /* reserved for future extensions */
1723 if (cfg.flags)
1724 return -EINVAL;
1725
2ee91e54 1726 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1727 return -ERANGE;
2e5b38ab
RC		 1728
1729 switch (cfg.rx_filter) {
1730 case HWTSTAMP_FILTER_NONE:
b63ba58e 1731 cpts_rx_enable(cpts, 0);
2e5b38ab
RC		 1732 break;
1733 case HWTSTAMP_FILTER_ALL:
e9523a5a
GS		 1734 case HWTSTAMP_FILTER_NTP_ALL:
1735 return -ERANGE;
2e5b38ab
RC		 1736 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1737 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1738 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
e9523a5a
GS		 1739 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1740 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1741 break;
2e5b38ab
RC		 1742 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1743 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1744 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1745 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1746 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1747 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1748 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1749 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e9523a5a 1751 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2e5b38ab
RC		 1752 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1753 break;
1754 default:
1755 return -ERANGE;
1756 }
1757
b63ba58e 1758 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2ee91e54 1759
2a05a622 1760 switch (cpsw->version) {
2e5b38ab 1761 case CPSW_VERSION_1:
2a05a622 1762 cpsw_hwtstamp_v1(cpsw);
2e5b38ab
RC		 1763 break;
1764 case CPSW_VERSION_2:
f7d403cb 1765 case CPSW_VERSION_3:
2e5b38ab
RC		 1766 cpsw_hwtstamp_v2(priv);
1767 break;
1768 default:
2ee91e54 1769 WARN_ON(1);
2e5b38ab
RC		 1770 }
1771
1772 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1773}
1774
a5b4145b
BH		 1775static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1776{
2a05a622
IK		 1777 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1778 struct cpts *cpts = cpsw->cpts;
a5b4145b
BH		 1779 struct hwtstamp_config cfg;
1780
2a05a622
IK		 1781 if (cpsw->version != CPSW_VERSION_1 &&
1782 cpsw->version != CPSW_VERSION_2 &&
1783 cpsw->version != CPSW_VERSION_3)
a5b4145b
BH		 1784 return -EOPNOTSUPP;
1785
1786 cfg.flags = 0;
b63ba58e
GS		 1787 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1788 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1789 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
e9523a5a 1790 cpts->rx_enable : HWTSTAMP_FILTER_NONE);
a5b4145b
BH		 1791
1792 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1793}
c8395d4e
GS		 1794#else
1795static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1796{
1797 return -EOPNOTSUPP;
1798}
a5b4145b 1799
c8395d4e
GS		 1800static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1801{
1802 return -EOPNOTSUPP;
1803}
2e5b38ab
RC		 1804#endif /*CONFIG_TI_CPTS*/
1805
1806static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1807{
11f2c988 1808 struct cpsw_priv *priv = netdev_priv(dev);
606f3993
IK		 1809 struct cpsw_common *cpsw = priv->cpsw;
1810 int slave_no = cpsw_slave_index(cpsw, priv);
11f2c988 1811
2e5b38ab
RC		 1812 if (!netif_running(dev))
1813 return -EINVAL;
1814
11f2c988 1815 switch (cmd) {
11f2c988 1816 case SIOCSHWTSTAMP:
a5b4145b
BH		 1817 return cpsw_hwtstamp_set(dev, req);
1818 case SIOCGHWTSTAMP:
1819 return cpsw_hwtstamp_get(dev, req);
11f2c988
M		 1820 }
1821
606f3993 1822 if (!cpsw->slaves[slave_no].phy)
c1b59947 1823 return -EOPNOTSUPP;
606f3993 1824 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1825}
1826
df828598
M		 1827static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1828{
1829 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1830 struct cpsw_common *cpsw = priv->cpsw;
e05107e6 1831 int ch;
df828598
M		 1832
1833 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1834 ndev->stats.tx_errors++;
2c836bd9 1835 cpsw_intr_disable(cpsw);
e05107e6 1836 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
8feb0a19
IK		 1837 cpdma_chan_stop(cpsw->txv[ch].ch);
1838 cpdma_chan_start(cpsw->txv[ch].ch);
e05107e6
IK		 1839 }
1840
2c836bd9 1841 cpsw_intr_enable(cpsw);
75514b66
GS		 1842 netif_trans_update(ndev);
1843 netif_tx_wake_all_queues(ndev);
df828598
M		 1844}
1845
dcfd8d58
M		 1846static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1847{
1848 struct cpsw_priv *priv = netdev_priv(ndev);
1849 struct sockaddr *addr = (struct sockaddr *)p;
649a1688 1850 struct cpsw_common *cpsw = priv->cpsw;
dcfd8d58
M		 1851 int flags = 0;
1852 u16 vid = 0;
a6c5d14f 1853 int ret;
dcfd8d58
M		 1854
1855 if (!is_valid_ether_addr(addr->sa_data))
1856 return -EADDRNOTAVAIL;
1857
56e31bd8 1858 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1859 if (ret < 0) {
56e31bd8 1860 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1861 return ret;
1862 }
1863
606f3993
IK		 1864 if (cpsw->data.dual_emac) {
1865 vid = cpsw->slaves[priv->emac_port].port_vlan;
dcfd8d58
M		 1866 flags = ALE_VLAN;
1867 }
1868
2a05a622 1869 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1870 flags, vid);
2a05a622 1871 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1872 flags, vid);
1873
1874 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1875 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1876 for_each_slave(priv, cpsw_set_slave_mac, priv);
1877
56e31bd8 1878 pm_runtime_put(cpsw->dev);
a6c5d14f 1879
dcfd8d58
M		 1880 return 0;
1881}
1882
df828598
M		 1883#ifdef CONFIG_NET_POLL_CONTROLLER
1884static void cpsw_ndo_poll_controller(struct net_device *ndev)
1885{
dbc4ec52 1886 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 1887
dbc4ec52
IK		 1888 cpsw_intr_disable(cpsw);
1889 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1890 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1891 cpsw_intr_enable(cpsw);
df828598
M		 1892}
1893#endif
1894
3b72c2fe
M		 1895static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1896 unsigned short vid)
1897{
1898 int ret;
9f6bd8fa
M		 1899 int unreg_mcast_mask = 0;
1900 u32 port_mask;
606f3993 1901 struct cpsw_common *cpsw = priv->cpsw;
1e5c4bc4 1902
606f3993 1903 if (cpsw->data.dual_emac) {
9f6bd8fa 1904 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1905
9f6bd8fa
M		 1906 if (priv->ndev->flags & IFF_ALLMULTI)
1907 unreg_mcast_mask = port_mask;
1908 } else {
1909 port_mask = ALE_ALL_PORTS;
1910
1911 if (priv->ndev->flags & IFF_ALLMULTI)
1912 unreg_mcast_mask = ALE_ALL_PORTS;
1913 else
1914 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1915 }
3b72c2fe 1916
2a05a622 1917 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
61f1cef9 1918 unreg_mcast_mask);
3b72c2fe
M		 1919 if (ret != 0)
1920 return ret;
1921
2a05a622 1922 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1923 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1924 if (ret != 0)
1925 goto clean_vid;
1926
2a05a622 1927 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
9f6bd8fa 1928 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1929 if (ret != 0)
1930 goto clean_vlan_ucast;
1931 return 0;
1932
1933clean_vlan_ucast:
2a05a622 1934 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1935 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe 1936clean_vid:
2a05a622 1937 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 1938 return ret;
1939}
1940
1941static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1942 __be16 proto, u16 vid)
3b72c2fe
M		 1943{
1944 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1945 struct cpsw_common *cpsw = priv->cpsw;
a6c5d14f 1946 int ret;
3b72c2fe 1947
606f3993 1948 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 1949 return 0;
1950
56e31bd8 1951 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1952 if (ret < 0) {
56e31bd8 1953 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1954 return ret;
1955 }
1956
606f3993 1957 if (cpsw->data.dual_emac) {
02a54164
M		 1958 /* In dual EMAC, reserved VLAN id should not be used for
1959 * creating VLAN interfaces as this can break the dual
1960 * EMAC port separation
1961 */
1962 int i;
1963
606f3993
IK		 1964 for (i = 0; i < cpsw->data.slaves; i++) {
1965 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 1966 return -EINVAL;
1967 }
1968 }
1969
3b72c2fe 1970 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1971 ret = cpsw_add_vlan_ale_entry(priv, vid);
1972
56e31bd8 1973 pm_runtime_put(cpsw->dev);
a6c5d14f 1974 return ret;
3b72c2fe
M		 1975}
1976
1977static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1978 __be16 proto, u16 vid)
3b72c2fe
M		 1979{
1980 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1981 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 1982 int ret;
1983
606f3993 1984 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 1985 return 0;
1986
56e31bd8 1987 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1988 if (ret < 0) {
56e31bd8 1989 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1990 return ret;
1991 }
1992
606f3993 1993 if (cpsw->data.dual_emac) {
02a54164
M		 1994 int i;
1995
606f3993
IK		 1996 for (i = 0; i < cpsw->data.slaves; i++) {
1997 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 1998 return -EINVAL;
1999 }
2000 }
2001
3b72c2fe 2002 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2a05a622 2003 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 2004 if (ret != 0)
2005 return ret;
2006
2a05a622 2007 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
61f1cef9 2008 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 2009 if (ret != 0)
2010 return ret;
2011
2a05a622 2012 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
a6c5d14f 2013 0, ALE_VLAN, vid);
56e31bd8 2014 pm_runtime_put(cpsw->dev);
a6c5d14f 2015 return ret;
3b72c2fe
M		 2016}
2017
83fcad0c
IK		 2018static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2019{
2020 struct cpsw_priv *priv = netdev_priv(ndev);
83fcad0c 2021 struct cpsw_common *cpsw = priv->cpsw;
52986a2f 2022 struct cpsw_slave *slave;
32b78d85 2023 u32 min_rate;
83fcad0c 2024 u32 ch_rate;
52986a2f 2025 int i, ret;
83fcad0c
IK		 2026
2027 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2028 if (ch_rate == rate)
2029 return 0;
2030
32b78d85
IK		 2031 ch_rate = rate * 1000;
2032 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2033 if ((ch_rate < min_rate && ch_rate)) {
2034 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2035 min_rate);
83fcad0c
IK		 2036 return -EINVAL;
2037 }
2038
0be01b8e 2039 if (rate > cpsw->speed) {
32b78d85 2040 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
83fcad0c
IK		 2041 return -EINVAL;
2042 }
2043
2044 ret = pm_runtime_get_sync(cpsw->dev);
2045 if (ret < 0) {
2046 pm_runtime_put_noidle(cpsw->dev);
2047 return ret;
2048 }
2049
32b78d85
IK		 2050 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2051 pm_runtime_put(cpsw->dev);
83fcad0c 2052
32b78d85
IK		 2053 if (ret)
2054 return ret;
83fcad0c 2055
52986a2f
IK		 2056 /* update rates for slaves tx queues */
2057 for (i = 0; i < cpsw->data.slaves; i++) {
2058 slave = &cpsw->slaves[i];
2059 if (!slave->ndev)
2060 continue;
2061
2062 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2063 }
2064
32b78d85 2065 cpsw_split_res(ndev);
83fcad0c
IK		 2066 return ret;
2067}
2068
df828598
M		 2069static const struct net_device_ops cpsw_netdev_ops = {
2070 .ndo_open = cpsw_ndo_open,
2071 .ndo_stop = cpsw_ndo_stop,
2072 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 2073 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 2074 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598
M		 2075 .ndo_validate_addr = eth_validate_addr,
2076 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 2077 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
83fcad0c 2078 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
df828598
M		 2079#ifdef CONFIG_NET_POLL_CONTROLLER
2080 .ndo_poll_controller = cpsw_ndo_poll_controller,
2081#endif
3b72c2fe
M		 2082 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2083 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 2084};
2085
52c4f0ec
M		 2086static int cpsw_get_regs_len(struct net_device *ndev)
2087{
606f3993 2088 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec 2089
606f3993 2090 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
52c4f0ec
M		 2091}
2092
2093static void cpsw_get_regs(struct net_device *ndev,
2094 struct ethtool_regs *regs, void *p)
2095{
52c4f0ec 2096 u32 *reg = p;
2a05a622 2097 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec
M		 2098
2099 /* update CPSW IP version */
2a05a622 2100 regs->version = cpsw->version;
52c4f0ec 2101
2a05a622 2102 cpsw_ale_dump(cpsw->ale, reg);
52c4f0ec
M		 2103}
2104
df828598
M		 2105static void cpsw_get_drvinfo(struct net_device *ndev,
2106 struct ethtool_drvinfo *info)
2107{
649a1688 2108 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
56e31bd8 2109 struct platform_device *pdev = to_platform_device(cpsw->dev);
7826d43f 2110
52c4f0ec 2111 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f 2112 strlcpy(info->version, "1.0", sizeof(info->version));
56e31bd8 2113 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
df828598
M		 2114}
2115
2116static u32 cpsw_get_msglevel(struct net_device *ndev)
2117{
2118 struct cpsw_priv *priv = netdev_priv(ndev);
2119 return priv->msg_enable;
2120}
2121
2122static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2123{
2124 struct cpsw_priv *priv = netdev_priv(ndev);
2125 priv->msg_enable = value;
2126}
2127
c8395d4e 2128#if IS_ENABLED(CONFIG_TI_CPTS)
2e5b38ab
RC		 2129static int cpsw_get_ts_info(struct net_device *ndev,
2130 struct ethtool_ts_info *info)
2131{
2a05a622 2132 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2e5b38ab
RC		 2133
2134 info->so_timestamping =
2135 SOF_TIMESTAMPING_TX_HARDWARE |
2136 SOF_TIMESTAMPING_TX_SOFTWARE |
2137 SOF_TIMESTAMPING_RX_HARDWARE |
2138 SOF_TIMESTAMPING_RX_SOFTWARE |
2139 SOF_TIMESTAMPING_SOFTWARE |
2140 SOF_TIMESTAMPING_RAW_HARDWARE;
2a05a622 2141 info->phc_index = cpsw->cpts->phc_index;
2e5b38ab
RC		 2142 info->tx_types =
2143 (1 << HWTSTAMP_TX_OFF) |
2144 (1 << HWTSTAMP_TX_ON);
2145 info->rx_filters =
2146 (1 << HWTSTAMP_FILTER_NONE) |
e9523a5a 2147 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2e5b38ab 2148 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
c8395d4e
GS		 2149 return 0;
2150}
2e5b38ab 2151#else
c8395d4e
GS		 2152static int cpsw_get_ts_info(struct net_device *ndev,
2153 struct ethtool_ts_info *info)
2154{
2e5b38ab
RC		 2155 info->so_timestamping =
2156 SOF_TIMESTAMPING_TX_SOFTWARE |
2157 SOF_TIMESTAMPING_RX_SOFTWARE |
2158 SOF_TIMESTAMPING_SOFTWARE;
2159 info->phc_index = -1;
2160 info->tx_types = 0;
2161 info->rx_filters = 0;
2e5b38ab
RC		 2162 return 0;
2163}
c8395d4e 2164#endif
2e5b38ab 2165
2479876d
PR		 2166static int cpsw_get_link_ksettings(struct net_device *ndev,
2167 struct ethtool_link_ksettings *ecmd)
d3bb9c58
M		 2168{
2169 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2170 struct cpsw_common *cpsw = priv->cpsw;
2171 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 2172
5514174f 2173 if (!cpsw->slaves[slave_no].phy)
d3bb9c58 2174 return -EOPNOTSUPP;
5514174f 2175
2176 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2177 return 0;
d3bb9c58
M		 2178}
2179
2479876d
PR		 2180static int cpsw_set_link_ksettings(struct net_device *ndev,
2181 const struct ethtool_link_ksettings *ecmd)
d3bb9c58
M		 2182{
2183 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2184 struct cpsw_common *cpsw = priv->cpsw;
2185 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 2186
606f3993 2187 if (cpsw->slaves[slave_no].phy)
2479876d
PR		 2188 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2189 ecmd);
d3bb9c58
M		 2190 else
2191 return -EOPNOTSUPP;
2192}
2193
d8a64420
MU		 2194static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2195{
2196 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2197 struct cpsw_common *cpsw = priv->cpsw;
2198 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420
MU		 2199
2200 wol->supported = 0;
2201 wol->wolopts = 0;
2202
606f3993
IK		 2203 if (cpsw->slaves[slave_no].phy)
2204 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2205}
2206
2207static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2208{
2209 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2210 struct cpsw_common *cpsw = priv->cpsw;
2211 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420 2212
606f3993
IK		 2213 if (cpsw->slaves[slave_no].phy)
2214 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2215 else
2216 return -EOPNOTSUPP;
2217}
2218
1923d6e4
M		 2219static void cpsw_get_pauseparam(struct net_device *ndev,
2220 struct ethtool_pauseparam *pause)
2221{
2222 struct cpsw_priv *priv = netdev_priv(ndev);
2223
2224 pause->autoneg = AUTONEG_DISABLE;
2225 pause->rx_pause = priv->rx_pause ? true : false;
2226 pause->tx_pause = priv->tx_pause ? true : false;
2227}
2228
2229static int cpsw_set_pauseparam(struct net_device *ndev,
2230 struct ethtool_pauseparam *pause)
2231{
2232 struct cpsw_priv *priv = netdev_priv(ndev);
2233 bool link;
2234
2235 priv->rx_pause = pause->rx_pause ? true : false;
2236 priv->tx_pause = pause->tx_pause ? true : false;
2237
2238 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 2239 return 0;
2240}
2241
7898b1da
GS		 2242static int cpsw_ethtool_op_begin(struct net_device *ndev)
2243{
2244 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 2245 struct cpsw_common *cpsw = priv->cpsw;
7898b1da
GS		 2246 int ret;
2247
56e31bd8 2248 ret = pm_runtime_get_sync(cpsw->dev);
7898b1da
GS		 2249 if (ret < 0) {
2250 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
56e31bd8 2251 pm_runtime_put_noidle(cpsw->dev);
7898b1da
GS		 2252 }
2253
2254 return ret;
2255}
2256
2257static void cpsw_ethtool_op_complete(struct net_device *ndev)
2258{
2259 struct cpsw_priv *priv = netdev_priv(ndev);
2260 int ret;
2261
56e31bd8 2262 ret = pm_runtime_put(priv->cpsw->dev);
7898b1da
GS		 2263 if (ret < 0)
2264 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2265}
2266
ce52c744
IK		 2267static void cpsw_get_channels(struct net_device *ndev,
2268 struct ethtool_channels *ch)
2269{
2270 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2271
2272 ch->max_combined = 0;
2273 ch->max_rx = CPSW_MAX_QUEUES;
2274 ch->max_tx = CPSW_MAX_QUEUES;
2275 ch->max_other = 0;
2276 ch->other_count = 0;
2277 ch->rx_count = cpsw->rx_ch_num;
2278 ch->tx_count = cpsw->tx_ch_num;
2279 ch->combined_count = 0;
2280}
2281
2282static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2283 struct ethtool_channels *ch)
2284{
2285 if (ch->combined_count)
2286 return -EINVAL;
2287
2288 /* verify we have at least one channel in each direction */
2289 if (!ch->rx_count || !ch->tx_count)
2290 return -EINVAL;
2291
2292 if (ch->rx_count > cpsw->data.channels ||
2293 ch->tx_count > cpsw->data.channels)
2294 return -EINVAL;
2295
2296 return 0;
2297}
2298
2299static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2300{
2301 int (*poll)(struct napi_struct *, int);
2302 struct cpsw_common *cpsw = priv->cpsw;
2303 void (*handler)(void *, int, int);
83fcad0c 2304 struct netdev_queue *queue;
8feb0a19 2305 struct cpsw_vector *vec;
ce52c744
IK		 2306 int ret, *ch;
2307
2308 if (rx) {
2309 ch = &cpsw->rx_ch_num;
8feb0a19 2310 vec = cpsw->rxv;
ce52c744
IK		 2311 handler = cpsw_rx_handler;
2312 poll = cpsw_rx_poll;
2313 } else {
2314 ch = &cpsw->tx_ch_num;
8feb0a19 2315 vec = cpsw->txv;
ce52c744
IK		 2316 handler = cpsw_tx_handler;
2317 poll = cpsw_tx_poll;
2318 }
2319
2320 while (*ch < ch_num) {
8feb0a19 2321 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
83fcad0c
IK		 2322 queue = netdev_get_tx_queue(priv->ndev, *ch);
2323 queue->tx_maxrate = 0;
ce52c744 2324
8feb0a19
IK		 2325 if (IS_ERR(vec[*ch].ch))
2326 return PTR_ERR(vec[*ch].ch);
ce52c744 2327
8feb0a19 2328 if (!vec[*ch].ch)
ce52c744
IK		 2329 return -EINVAL;
2330
2331 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2332 (rx ? "rx" : "tx"));
2333 (*ch)++;
2334 }
2335
2336 while (*ch > ch_num) {
2337 (*ch)--;
2338
8feb0a19 2339 ret = cpdma_chan_destroy(vec[*ch].ch);
ce52c744
IK		 2340 if (ret)
2341 return ret;
2342
2343 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2344 (rx ? "rx" : "tx"));
2345 }
2346
2347 return 0;
2348}
2349
2350static int cpsw_update_channels(struct cpsw_priv *priv,
2351 struct ethtool_channels *ch)
2352{
2353 int ret;
2354
2355 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2356 if (ret)
2357 return ret;
2358
2359 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2360 if (ret)
2361 return ret;
2362
2363 return 0;
2364}
2365
022d7ad7 2366static void cpsw_suspend_data_pass(struct net_device *ndev)
ce52c744 2367{
022d7ad7 2368 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
ce52c744 2369 struct cpsw_slave *slave;
022d7ad7 2370 int i;
ce52c744
IK		 2371
2372 /* Disable NAPI scheduling */
2373 cpsw_intr_disable(cpsw);
2374
2375 /* Stop all transmit queues for every network device.
2376 * Disable re-using rx descriptors with dormant_on.
2377 */
2378 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2379 if (!(slave->ndev && netif_running(slave->ndev)))
2380 continue;
2381
2382 netif_tx_stop_all_queues(slave->ndev);
2383 netif_dormant_on(slave->ndev);
2384 }
2385
2386 /* Handle rest of tx packets and stop cpdma channels */
2387 cpdma_ctlr_stop(cpsw->dma);
022d7ad7
IK		 2388}
2389
2390static int cpsw_resume_data_pass(struct net_device *ndev)
2391{
2392 struct cpsw_priv *priv = netdev_priv(ndev);
2393 struct cpsw_common *cpsw = priv->cpsw;
2394 struct cpsw_slave *slave;
2395 int i, ret;
2396
2397 /* Allow rx packets handling */
2398 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2399 if (slave->ndev && netif_running(slave->ndev))
2400 netif_dormant_off(slave->ndev);
2401
2402 /* After this receive is started */
d5bc1613 2403 if (cpsw->usage_count) {
022d7ad7
IK		 2404 ret = cpsw_fill_rx_channels(priv);
2405 if (ret)
2406 return ret;
2407
2408 cpdma_ctlr_start(cpsw->dma);
2409 cpsw_intr_enable(cpsw);
2410 }
2411
2412 /* Resume transmit for every affected interface */
2413 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2414 if (slave->ndev && netif_running(slave->ndev))
2415 netif_tx_start_all_queues(slave->ndev);
2416
2417 return 0;
2418}
2419
2420static int cpsw_set_channels(struct net_device *ndev,
2421 struct ethtool_channels *chs)
2422{
2423 struct cpsw_priv *priv = netdev_priv(ndev);
2424 struct cpsw_common *cpsw = priv->cpsw;
2425 struct cpsw_slave *slave;
2426 int i, ret;
2427
2428 ret = cpsw_check_ch_settings(cpsw, chs);
2429 if (ret < 0)
2430 return ret;
2431
2432 cpsw_suspend_data_pass(ndev);
ce52c744
IK		 2433 ret = cpsw_update_channels(priv, chs);
2434 if (ret)
2435 goto err;
2436
2437 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2438 if (!(slave->ndev && netif_running(slave->ndev)))
2439 continue;
2440
2441 /* Inform stack about new count of queues */
2442 ret = netif_set_real_num_tx_queues(slave->ndev,
2443 cpsw->tx_ch_num);
2444 if (ret) {
2445 dev_err(priv->dev, "cannot set real number of tx queues\n");
2446 goto err;
2447 }
2448
2449 ret = netif_set_real_num_rx_queues(slave->ndev,
2450 cpsw->rx_ch_num);
2451 if (ret) {
2452 dev_err(priv->dev, "cannot set real number of rx queues\n");
2453 goto err;
2454 }
ce52c744
IK		 2455 }
2456
d5bc1613 2457 if (cpsw->usage_count)
32b78d85 2458 cpsw_split_res(ndev);
8feb0a19 2459
022d7ad7
IK		 2460 ret = cpsw_resume_data_pass(ndev);
2461 if (!ret)
2462 return 0;
ce52c744
IK		 2463err:
2464 dev_err(priv->dev, "cannot update channels number, closing device\n");
2465 dev_close(ndev);
2466 return ret;
2467}
2468
a0909949
YY		 2469static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2470{
2471 struct cpsw_priv *priv = netdev_priv(ndev);
2472 struct cpsw_common *cpsw = priv->cpsw;
2473 int slave_no = cpsw_slave_index(cpsw, priv);
2474
2475 if (cpsw->slaves[slave_no].phy)
2476 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2477 else
2478 return -EOPNOTSUPP;
2479}
2480
2481static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2482{
2483 struct cpsw_priv *priv = netdev_priv(ndev);
2484 struct cpsw_common *cpsw = priv->cpsw;
2485 int slave_no = cpsw_slave_index(cpsw, priv);
2486
2487 if (cpsw->slaves[slave_no].phy)
2488 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2489 else
2490 return -EOPNOTSUPP;
2491}
2492
6bb10c2b
YY		 2493static int cpsw_nway_reset(struct net_device *ndev)
2494{
2495 struct cpsw_priv *priv = netdev_priv(ndev);
2496 struct cpsw_common *cpsw = priv->cpsw;
2497 int slave_no = cpsw_slave_index(cpsw, priv);
2498
2499 if (cpsw->slaves[slave_no].phy)
2500 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2501 else
2502 return -EOPNOTSUPP;
2503}
2504
be034fc1
GS		 2505static void cpsw_get_ringparam(struct net_device *ndev,
2506 struct ethtool_ringparam *ering)
2507{
2508 struct cpsw_priv *priv = netdev_priv(ndev);
2509 struct cpsw_common *cpsw = priv->cpsw;
2510
2511 /* not supported */
2512 ering->tx_max_pending = 0;
2513 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
f89d21b9 2514 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
be034fc1
GS		 2515 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2516}
2517
2518static int cpsw_set_ringparam(struct net_device *ndev,
2519 struct ethtool_ringparam *ering)
2520{
2521 struct cpsw_priv *priv = netdev_priv(ndev);
2522 struct cpsw_common *cpsw = priv->cpsw;
022d7ad7 2523 int ret;
be034fc1
GS		 2524
2525 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2526
2527 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
f89d21b9
IK		 2528 ering->rx_pending < CPSW_MAX_QUEUES ||
2529 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
be034fc1
GS		 2530 return -EINVAL;
2531
2532 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2533 return 0;
2534
022d7ad7 2535 cpsw_suspend_data_pass(ndev);
be034fc1
GS		 2536
2537 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2538
d5bc1613 2539 if (cpsw->usage_count)
be034fc1
GS		 2540 cpdma_chan_split_pool(cpsw->dma);
2541
022d7ad7
IK		 2542 ret = cpsw_resume_data_pass(ndev);
2543 if (!ret)
2544 return 0;
be034fc1 2545
022d7ad7 2546 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
be034fc1
GS		 2547 dev_close(ndev);
2548 return ret;
2549}
2550
df828598
M		 2551static const struct ethtool_ops cpsw_ethtool_ops = {
2552 .get_drvinfo = cpsw_get_drvinfo,
2553 .get_msglevel = cpsw_get_msglevel,
2554 .set_msglevel = cpsw_set_msglevel,
2555 .get_link = ethtool_op_get_link,
2e5b38ab 2556 .get_ts_info = cpsw_get_ts_info,
ff5b8ef2
M		 2557 .get_coalesce = cpsw_get_coalesce,
2558 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 2559 .get_sset_count = cpsw_get_sset_count,
2560 .get_strings = cpsw_get_strings,
2561 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 2562 .get_pauseparam = cpsw_get_pauseparam,
2563 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 2564 .get_wol = cpsw_get_wol,
2565 .set_wol = cpsw_set_wol,
52c4f0ec
M		 2566 .get_regs_len = cpsw_get_regs_len,
2567 .get_regs = cpsw_get_regs,
7898b1da
GS		 2568 .begin = cpsw_ethtool_op_begin,
2569 .complete = cpsw_ethtool_op_complete,
ce52c744
IK		 2570 .get_channels = cpsw_get_channels,
2571 .set_channels = cpsw_set_channels,
2479876d
PR		 2572 .get_link_ksettings = cpsw_get_link_ksettings,
2573 .set_link_ksettings = cpsw_set_link_ksettings,
a0909949
YY		 2574 .get_eee = cpsw_get_eee,
2575 .set_eee = cpsw_set_eee,
6bb10c2b 2576 .nway_reset = cpsw_nway_reset,
be034fc1
GS		 2577 .get_ringparam = cpsw_get_ringparam,
2578 .set_ringparam = cpsw_set_ringparam,
df828598
M		 2579};
2580
606f3993 2581static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
549985ee 2582 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598 2583{
5d8d0d4d 2584 void __iomem *regs = cpsw->regs;
df828598 2585 int slave_num = slave->slave_num;
606f3993 2586 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
df828598
M		 2587
2588 slave->data = data;
549985ee
RC		 2589 slave->regs = regs + slave_reg_ofs;
2590 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 2591 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 2592}
2593
552165bc 2594static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 2595 struct platform_device *pdev)
2596{
2597 struct device_node *node = pdev->dev.of_node;
2598 struct device_node *slave_node;
2599 int i = 0, ret;
2600 u32 prop;
2601
2602 if (!node)
2603 return -EINVAL;
2604
2605 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 2606 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 2607 return -EINVAL;
2608 }
2609 data->slaves = prop;
2610
e86ac13b 2611 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 2612 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 2613 return -EINVAL;
78ca0b28 2614 }
e86ac13b 2615 data->active_slave = prop;
78ca0b28 2616
aa1a15e2
DM		 2617 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2618 * sizeof(struct cpsw_slave_data),
2619 GFP_KERNEL);
b2adaca9 2620 if (!data->slave_data)
aa1a15e2 2621 return -ENOMEM;
2eb32b0a 2622
2eb32b0a 2623 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2624 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2625 return -EINVAL;
2eb32b0a
M		 2626 }
2627 data->channels = prop;
2628
2eb32b0a 2629 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2630 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2631 return -EINVAL;
2eb32b0a
M		 2632 }
2633 data->ale_entries = prop;
2634
2eb32b0a 2635 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2636 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2637 return -EINVAL;
2eb32b0a
M		 2638 }
2639 data->bd_ram_size = prop;
2640
2eb32b0a 2641 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2642 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2643 return -EINVAL;
2eb32b0a
M		 2644 }
2645 data->mac_control = prop;
2646
281abd96
MP		 2647 if (of_property_read_bool(node, "dual_emac"))
2648 data->dual_emac = 1;
d9ba8f9e 2649
549985ee
RC		 2650 /*
2651 * Populate all the child nodes here...
2652 */
2653 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2654 /* We do not want to force this, as in some cases may not have child */
2655 if (ret)
88c99ff6 2656 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2657
8658aaf2 2658 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2659 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2660 const void *mac_addr = NULL;
549985ee
RC		 2661 int lenp;
2662 const __be32 *parp;
549985ee 2663
f468b10e
MP		 2664 /* This is no slave child node, continue */
2665 if (strcmp(slave_node->name, "slave"))
2666 continue;
2667
552165bc
DR		 2668 slave_data->phy_node = of_parse_phandle(slave_node,
2669 "phy-handle", 0);
f1eea5c1 2670 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2671 if (slave_data->phy_node) {
2672 dev_dbg(&pdev->dev,
2673 "slave[%d] using phy-handle=\"%s\"\n",
2674 i, slave_data->phy_node->full_name);
2675 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2676 /* In the case of a fixed PHY, the DT node associated
2677 * to the PHY is the Ethernet MAC DT node.
2678 */
1f71e8c9 2679 ret = of_phy_register_fixed_link(slave_node);
23a09873
JH		 2680 if (ret) {
2681 if (ret != -EPROBE_DEFER)
2682 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
1f71e8c9 2683 return ret;
23a09873 2684 }
06cd6d6e 2685 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2686 } else if (parp) {
2687 u32 phyid;
2688 struct device_node *mdio_node;
2689 struct platform_device *mdio;
2690
2691 if (lenp != (sizeof(__be32) * 2)) {
2692 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2693 goto no_phy_slave;
2694 }
2695 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2696 phyid = be32_to_cpup(parp+1);
2697 mdio = of_find_device_by_node(mdio_node);
2698 of_node_put(mdio_node);
2699 if (!mdio) {
2700 dev_err(&pdev->dev, "Missing mdio platform device\n");
2701 return -EINVAL;
2702 }
2703 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2704 PHY_ID_FMT, mdio->name, phyid);
86e1d5ad 2705 put_device(&mdio->dev);
f1eea5c1 2706 } else {
ae092b5b
DR		 2707 dev_err(&pdev->dev,
2708 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2709 i);
47276fcc 2710 goto no_phy_slave;
2eb32b0a 2711 }
47276fcc
M		 2712 slave_data->phy_if = of_get_phy_mode(slave_node);
2713 if (slave_data->phy_if < 0) {
2714 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2715 i);
2716 return slave_data->phy_if;
2717 }
2718
2719no_phy_slave:
2eb32b0a 2720 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2721 if (mac_addr) {
2eb32b0a 2722 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2723 } else {
b6745f6e
M		 2724 ret = ti_cm_get_macid(&pdev->dev, i,
2725 slave_data->mac_addr);
2726 if (ret)
2727 return ret;
0ba517b1 2728 }
d9ba8f9e 2729 if (data->dual_emac) {
91c4166c 2730 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2731 &prop)) {
88c99ff6 2732 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2733 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2734 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2735 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2736 } else {
2737 slave_data->dual_emac_res_vlan = prop;
2738 }
2739 }
2740
2eb32b0a 2741 i++;
3a27bfac
M		 2742 if (i == data->slaves)
2743 break;
2eb32b0a
M		 2744 }
2745
2746 return 0;
2eb32b0a
M		 2747}
2748
a4e32b0d
JH		 2749static void cpsw_remove_dt(struct platform_device *pdev)
2750{
8cbcc466
JH		 2751 struct net_device *ndev = platform_get_drvdata(pdev);
2752 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2753 struct cpsw_platform_data *data = &cpsw->data;
2754 struct device_node *node = pdev->dev.of_node;
2755 struct device_node *slave_node;
2756 int i = 0;
2757
2758 for_each_available_child_of_node(node, slave_node) {
2759 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2760
2761 if (strcmp(slave_node->name, "slave"))
2762 continue;
2763
3f65047c
JH		 2764 if (of_phy_is_fixed_link(slave_node))
2765 of_phy_deregister_fixed_link(slave_node);
8cbcc466
JH		 2766
2767 of_node_put(slave_data->phy_node);
2768
2769 i++;
2770 if (i == data->slaves)
2771 break;
2772 }
2773
a4e32b0d
JH		 2774 of_platform_depopulate(&pdev->dev);
2775}
2776
56e31bd8 2777static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
d9ba8f9e 2778{
606f3993
IK		 2779 struct cpsw_common *cpsw = priv->cpsw;
2780 struct cpsw_platform_data *data = &cpsw->data;
d9ba8f9e
M		 2781 struct net_device *ndev;
2782 struct cpsw_priv *priv_sl2;
e38b5a3d 2783 int ret = 0;
d9ba8f9e 2784
e05107e6 2785 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
d9ba8f9e 2786 if (!ndev) {
56e31bd8 2787 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2788 return -ENOMEM;
2789 }
2790
2791 priv_sl2 = netdev_priv(ndev);
606f3993 2792 priv_sl2->cpsw = cpsw;
d9ba8f9e
M		 2793 priv_sl2->ndev = ndev;
2794 priv_sl2->dev = &ndev->dev;
2795 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
d9ba8f9e
M		 2796
2797 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2798 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2799 ETH_ALEN);
56e31bd8
IK		 2800 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2801 priv_sl2->mac_addr);
d9ba8f9e
M		 2802 } else {
2803 random_ether_addr(priv_sl2->mac_addr);
56e31bd8
IK		 2804 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2805 priv_sl2->mac_addr);
d9ba8f9e
M		 2806 }
2807 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2808
d9ba8f9e 2809 priv_sl2->emac_port = 1;
606f3993 2810 cpsw->slaves[1].ndev = ndev;
f646968f 2811 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2812
2813 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2814 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2815
2816 /* register the network device */
56e31bd8 2817 SET_NETDEV_DEV(ndev, cpsw->dev);
d9ba8f9e
M		 2818 ret = register_netdev(ndev);
2819 if (ret) {
56e31bd8 2820 dev_err(cpsw->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2821 free_netdev(ndev);
2822 ret = -ENODEV;
2823 }
2824
2825 return ret;
2826}
2827
7da11600
M		 2828#define CPSW_QUIRK_IRQ BIT(0)
2829
2830static struct platform_device_id cpsw_devtype[] = {
2831 {
2832 /* keep it for existing comaptibles */
2833 .name = "cpsw",
2834 .driver_data = CPSW_QUIRK_IRQ,
2835 }, {
2836 .name = "am335x-cpsw",
2837 .driver_data = CPSW_QUIRK_IRQ,
2838 }, {
2839 .name = "am4372-cpsw",
2840 .driver_data = 0,
2841 }, {
2842 .name = "dra7-cpsw",
2843 .driver_data = 0,
2844 }, {
2845 /* sentinel */
2846 }
2847};
2848MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2849
2850enum ti_cpsw_type {
2851 CPSW = 0,
2852 AM335X_CPSW,
2853 AM4372_CPSW,
2854 DRA7_CPSW,
2855};
2856
2857static const struct of_device_id cpsw_of_mtable[] = {
2858 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2859 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2860 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2861 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2862 { /* sentinel */ },
2863};
2864MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2865
663e12e6 2866static int cpsw_probe(struct platform_device *pdev)
df828598 2867{
ef4183a1 2868 struct clk *clk;
d1bd9acf 2869 struct cpsw_platform_data *data;
df828598
M		 2870 struct net_device *ndev;
2871 struct cpsw_priv *priv;
2872 struct cpdma_params dma_params;
2873 struct cpsw_ale_params ale_params;
aa1a15e2 2874 void __iomem *ss_regs;
8a2c9a5a 2875 void __iomem *cpts_regs;
aa1a15e2 2876 struct resource *res, *ss_res;
7da11600 2877 const struct of_device_id *of_id;
1d147ccb 2878 struct gpio_descs *mode;
549985ee 2879 u32 slave_offset, sliver_offset, slave_size;
649a1688 2880 struct cpsw_common *cpsw;
5087b915
FB		 2881 int ret = 0, i;
2882 int irq;
df828598 2883
649a1688 2884 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
3420ea88
JH		 2885 if (!cpsw)
2886 return -ENOMEM;
2887
56e31bd8 2888 cpsw->dev = &pdev->dev;
649a1688 2889
e05107e6 2890 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
df828598 2891 if (!ndev) {
88c99ff6 2892 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2893 return -ENOMEM;
2894 }
2895
2896 platform_set_drvdata(pdev, ndev);
2897 priv = netdev_priv(ndev);
649a1688 2898 priv->cpsw = cpsw;
df828598
M		 2899 priv->ndev = ndev;
2900 priv->dev = &ndev->dev;
2901 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2a05a622 2902 cpsw->rx_packet_max = max(rx_packet_max, 128);
df828598 2903
1d147ccb
M		 2904 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2905 if (IS_ERR(mode)) {
2906 ret = PTR_ERR(mode);
2907 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2908 goto clean_ndev_ret;
2909 }
2910
1fb19aa7
VH		 2911 /*
2912 * This may be required here for child devices.
2913 */
2914 pm_runtime_enable(&pdev->dev);
2915
739683b4
M		 2916 /* Select default pin state */
2917 pinctrl_pm_select_default_state(&pdev->dev);
2918
a4e32b0d
JH		 2919 /* Need to enable clocks with runtime PM api to access module
2920 * registers
2921 */
2922 ret = pm_runtime_get_sync(&pdev->dev);
2923 if (ret < 0) {
2924 pm_runtime_put_noidle(&pdev->dev);
aa1a15e2 2925 goto clean_runtime_disable_ret;
2eb32b0a 2926 }
a4e32b0d 2927
23a09873
JH		 2928 ret = cpsw_probe_dt(&cpsw->data, pdev);
2929 if (ret)
a4e32b0d 2930 goto clean_dt_ret;
23a09873 2931
606f3993 2932 data = &cpsw->data;
e05107e6
IK		 2933 cpsw->rx_ch_num = 1;
2934 cpsw->tx_ch_num = 1;
2eb32b0a 2935
df828598
M		 2936 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2937 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2938 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2939 } else {
7efd26d0 2940 eth_random_addr(priv->mac_addr);
88c99ff6 2941 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2942 }
2943
2944 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2945
606f3993 2946 cpsw->slaves = devm_kzalloc(&pdev->dev,
aa1a15e2
DM		 2947 sizeof(struct cpsw_slave) * data->slaves,
2948 GFP_KERNEL);
606f3993 2949 if (!cpsw->slaves) {
aa1a15e2 2950 ret = -ENOMEM;
a4e32b0d 2951 goto clean_dt_ret;
df828598
M		 2952 }
2953 for (i = 0; i < data->slaves; i++)
606f3993 2954 cpsw->slaves[i].slave_num = i;
df828598 2955
606f3993 2956 cpsw->slaves[0].ndev = ndev;
d9ba8f9e
M		 2957 priv->emac_port = 0;
2958
ef4183a1
IK		 2959 clk = devm_clk_get(&pdev->dev, "fck");
2960 if (IS_ERR(clk)) {
aa1a15e2 2961 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2962 ret = -ENODEV;
a4e32b0d 2963 goto clean_dt_ret;
df828598 2964 }
2a05a622 2965 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2966
aa1a15e2
DM		 2967 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2968 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2969 if (IS_ERR(ss_regs)) {
2970 ret = PTR_ERR(ss_regs);
a4e32b0d 2971 goto clean_dt_ret;
df828598 2972 }
5d8d0d4d 2973 cpsw->regs = ss_regs;
df828598 2974
2a05a622 2975 cpsw->version = readl(&cpsw->regs->id_ver);
f280e89a 2976
aa1a15e2 2977 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5d8d0d4d
IK		 2978 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2979 if (IS_ERR(cpsw->wr_regs)) {
2980 ret = PTR_ERR(cpsw->wr_regs);
a4e32b0d 2981 goto clean_dt_ret;
df828598 2982 }
df828598
M		 2983
2984 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2985 memset(&ale_params, 0, sizeof(ale_params));
2986
2a05a622 2987 switch (cpsw->version) {
549985ee 2988 case CPSW_VERSION_1:
5d8d0d4d 2989 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
8a2c9a5a 2990 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
5d8d0d4d 2991 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2992 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2993 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2994 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2995 slave_offset = CPSW1_SLAVE_OFFSET;
2996 slave_size = CPSW1_SLAVE_SIZE;
2997 sliver_offset = CPSW1_SLIVER_OFFSET;
2998 dma_params.desc_mem_phys = 0;
2999 break;
3000 case CPSW_VERSION_2:
c193f365 3001 case CPSW_VERSION_3:
926489be 3002 case CPSW_VERSION_4:
5d8d0d4d 3003 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
8a2c9a5a 3004 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
5d8d0d4d 3005 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 3006 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3007 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3008 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3009 slave_offset = CPSW2_SLAVE_OFFSET;
3010 slave_size = CPSW2_SLAVE_SIZE;
3011 sliver_offset = CPSW2_SLIVER_OFFSET;
3012 dma_params.desc_mem_phys =
aa1a15e2 3013 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 3014 break;
3015 default:
2a05a622 3016 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
549985ee 3017 ret = -ENODEV;
a4e32b0d 3018 goto clean_dt_ret;
549985ee 3019 }
606f3993
IK		 3020 for (i = 0; i < cpsw->data.slaves; i++) {
3021 struct cpsw_slave *slave = &cpsw->slaves[i];
3022
3023 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
549985ee
RC		 3024 slave_offset += slave_size;
3025 sliver_offset += SLIVER_SIZE;
3026 }
3027
df828598 3028 dma_params.dev = &pdev->dev;
549985ee
RC		 3029 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3030 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3031 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3032 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3033 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 3034
3035 dma_params.num_chan = data->channels;
3036 dma_params.has_soft_reset = true;
3037 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3038 dma_params.desc_mem_size = data->bd_ram_size;
3039 dma_params.desc_align = 16;
3040 dma_params.has_ext_regs = true;
549985ee 3041 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
83fcad0c 3042 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
90225bf0 3043 dma_params.descs_pool_size = descs_pool_size;
df828598 3044
2c836bd9
IK		 3045 cpsw->dma = cpdma_ctlr_create(&dma_params);
3046 if (!cpsw->dma) {
df828598
M		 3047 dev_err(priv->dev, "error initializing dma\n");
3048 ret = -ENOMEM;
a4e32b0d 3049 goto clean_dt_ret;
df828598
M		 3050 }
3051
8feb0a19
IK		 3052 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3053 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3054 if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
df828598
M		 3055 dev_err(priv->dev, "error initializing dma channels\n");
3056 ret = -ENOMEM;
3057 goto clean_dma_ret;
3058 }
3059
9fe9aa0b 3060 ale_params.dev = &pdev->dev;
df828598
M		 3061 ale_params.ale_ageout = ale_ageout;
3062 ale_params.ale_entries = data->ale_entries;
3063 ale_params.ale_ports = data->slaves;
3064
2a05a622
IK		 3065 cpsw->ale = cpsw_ale_create(&ale_params);
3066 if (!cpsw->ale) {
df828598
M		 3067 dev_err(priv->dev, "error initializing ale engine\n");
3068 ret = -ENODEV;
3069 goto clean_dma_ret;
3070 }
3071
4a88fb95 3072 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
8a2c9a5a
GS		 3073 if (IS_ERR(cpsw->cpts)) {
3074 ret = PTR_ERR(cpsw->cpts);
3075 goto clean_ale_ret;
3076 }
3077
c03abd84 3078 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 3079 if (ndev->irq < 0) {
3080 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 3081 ret = ndev->irq;
df828598
M		 3082 goto clean_ale_ret;
3083 }
3084
7da11600
M		 3085 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3086 if (of_id) {
3087 pdev->id_entry = of_id->data;
3088 if (pdev->id_entry->driver_data)
e38b5a3d 3089 cpsw->quirk_irq = true;
7da11600
M		 3090 }
3091
070f9c65
K		 3092 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3093
3094 ndev->netdev_ops = &cpsw_netdev_ops;
3095 ndev->ethtool_ops = &cpsw_ethtool_ops;
3096 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3097 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3098 cpsw_split_res(ndev);
3099
3100 /* register the network device */
3101 SET_NETDEV_DEV(ndev, &pdev->dev);
3102 ret = register_netdev(ndev);
3103 if (ret) {
3104 dev_err(priv->dev, "error registering net device\n");
3105 ret = -ENODEV;
3106 goto clean_ale_ret;
3107 }
3108
3109 if (cpsw->data.dual_emac) {
3110 ret = cpsw_probe_dual_emac(priv);
3111 if (ret) {
3112 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3113 goto clean_unregister_netdev_ret;
3114 }
3115 }
3116
c03abd84
FB		 3117 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3118 * MISC IRQs which are always kept disabled with this driver so
3119 * we will not request them.
3120 *
3121 * If anyone wants to implement support for those, make sure to
3122 * first request and append them to irqs_table array.
3123 */
c2b32e58 3124
c03abd84 3125 /* RX IRQ */
5087b915 3126 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 3127 if (irq < 0) {
3128 ret = irq;
5087b915 3129 goto clean_ale_ret;
c1e3334f 3130 }
5087b915 3131
e38b5a3d 3132 cpsw->irqs_table[0] = irq;
c03abd84 3133 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
dbc4ec52 3134 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 3135 if (ret < 0) {
3136 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3137 goto clean_ale_ret;
3138 }
3139
c03abd84 3140 /* TX IRQ */
5087b915 3141 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 3142 if (irq < 0) {
3143 ret = irq;
5087b915 3144 goto clean_ale_ret;
c1e3334f 3145 }
5087b915 3146
e38b5a3d 3147 cpsw->irqs_table[1] = irq;
c03abd84 3148 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
dbc4ec52 3149 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 3150 if (ret < 0) {
3151 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3152 goto clean_ale_ret;
df828598 3153 }
c2b32e58 3154
90225bf0
GS		 3155 cpsw_notice(priv, probe,
3156 "initialized device (regs %pa, irq %d, pool size %d)\n",
3157 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
d9ba8f9e 3158
c46ab7e0
JH		 3159 pm_runtime_put(&pdev->dev);
3160
df828598
M		 3161 return 0;
3162
a7fe9d46
JH		 3163clean_unregister_netdev_ret:
3164 unregister_netdev(ndev);
df828598 3165clean_ale_ret:
2a05a622 3166 cpsw_ale_destroy(cpsw->ale);
df828598 3167clean_dma_ret:
2c836bd9 3168 cpdma_ctlr_destroy(cpsw->dma);
a4e32b0d
JH		 3169clean_dt_ret:
3170 cpsw_remove_dt(pdev);
c46ab7e0 3171 pm_runtime_put_sync(&pdev->dev);
aa1a15e2 3172clean_runtime_disable_ret:
f150bd7f 3173 pm_runtime_disable(&pdev->dev);
df828598 3174clean_ndev_ret:
d1bd9acf 3175 free_netdev(priv->ndev);
df828598
M		 3176 return ret;
3177}
3178
663e12e6 3179static int cpsw_remove(struct platform_device *pdev)
df828598
M		 3180{
3181 struct net_device *ndev = platform_get_drvdata(pdev);
2a05a622 3182 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
8a0b6dc9
GS		 3183 int ret;
3184
3185 ret = pm_runtime_get_sync(&pdev->dev);
3186 if (ret < 0) {
3187 pm_runtime_put_noidle(&pdev->dev);
3188 return ret;
3189 }
df828598 3190
606f3993
IK		 3191 if (cpsw->data.dual_emac)
3192 unregister_netdev(cpsw->slaves[1].ndev);
d1bd9acf 3193 unregister_netdev(ndev);
df828598 3194
8a2c9a5a 3195 cpts_release(cpsw->cpts);
2a05a622 3196 cpsw_ale_destroy(cpsw->ale);
2c836bd9 3197 cpdma_ctlr_destroy(cpsw->dma);
a4e32b0d 3198 cpsw_remove_dt(pdev);
8a0b6dc9
GS		 3199 pm_runtime_put_sync(&pdev->dev);
3200 pm_runtime_disable(&pdev->dev);
606f3993
IK		 3201 if (cpsw->data.dual_emac)
3202 free_netdev(cpsw->slaves[1].ndev);
df828598 3203 free_netdev(ndev);
df828598
M		 3204 return 0;
3205}
3206
8963a504 3207#ifdef CONFIG_PM_SLEEP
df828598
M		 3208static int cpsw_suspend(struct device *dev)
3209{
3210 struct platform_device *pdev = to_platform_device(dev);
3211 struct net_device *ndev = platform_get_drvdata(pdev);
606f3993 3212 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 3213
606f3993 3214 if (cpsw->data.dual_emac) {
618073e3 3215 int i;
1e7a2e21 3216
606f3993
IK		 3217 for (i = 0; i < cpsw->data.slaves; i++) {
3218 if (netif_running(cpsw->slaves[i].ndev))
3219 cpsw_ndo_stop(cpsw->slaves[i].ndev);
618073e3
M		 3220 }
3221 } else {
3222 if (netif_running(ndev))
3223 cpsw_ndo_stop(ndev);
618073e3 3224 }
1e7a2e21 3225
739683b4 3226 /* Select sleep pin state */
56e31bd8 3227 pinctrl_pm_select_sleep_state(dev);
739683b4 3228
df828598
M		 3229 return 0;
3230}
3231
3232static int cpsw_resume(struct device *dev)
3233{
3234 struct platform_device *pdev = to_platform_device(dev);
3235 struct net_device *ndev = platform_get_drvdata(pdev);
a60ced99 3236 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 3237
739683b4 3238 /* Select default pin state */
56e31bd8 3239 pinctrl_pm_select_default_state(dev);
739683b4 3240
4ccfd638
GS		 3241 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3242 rtnl_lock();
606f3993 3243 if (cpsw->data.dual_emac) {
618073e3
M		 3244 int i;
3245
606f3993
IK		 3246 for (i = 0; i < cpsw->data.slaves; i++) {
3247 if (netif_running(cpsw->slaves[i].ndev))
3248 cpsw_ndo_open(cpsw->slaves[i].ndev);
618073e3
M		 3249 }
3250 } else {
3251 if (netif_running(ndev))
3252 cpsw_ndo_open(ndev);
3253 }
4ccfd638
GS		 3254 rtnl_unlock();
3255
df828598
M		 3256 return 0;
3257}
8963a504 3258#endif
df828598 3259
8963a504 3260static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 3261
3262static struct platform_driver cpsw_driver = {
3263 .driver = {
3264 .name = "cpsw",
df828598 3265 .pm = &cpsw_pm_ops,
1e5c76d4 3266 .of_match_table = cpsw_of_mtable,
df828598
M		 3267 },
3268 .probe = cpsw_probe,
663e12e6 3269 .remove = cpsw_remove,
df828598
M		 3270};
3271
6fb3b6b5 3272module_platform_driver(cpsw_driver);
df828598
M		 3273
3274MODULE_LICENSE("GPL");
3275MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3276MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3277MODULE_DESCRIPTION("TI CPSW Ethernet driver");
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