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net: ethernet: ti: cpdma: correct error handling for chan create
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
c6395f12 91#define CPSW_ALE_PORTS_NUM 3
549985ee
RC		 92#define SLIVER_SIZE 0x40
93
94#define CPSW1_HOST_PORT_OFFSET 0x028
95#define CPSW1_SLAVE_OFFSET 0x050
96#define CPSW1_SLAVE_SIZE 0x040
97#define CPSW1_CPDMA_OFFSET 0x100
98#define CPSW1_STATERAM_OFFSET 0x200
d9718546 99#define CPSW1_HW_STATS 0x400
549985ee
RC		 100#define CPSW1_CPTS_OFFSET 0x500
101#define CPSW1_ALE_OFFSET 0x600
102#define CPSW1_SLIVER_OFFSET 0x700
103
104#define CPSW2_HOST_PORT_OFFSET 0x108
105#define CPSW2_SLAVE_OFFSET 0x200
106#define CPSW2_SLAVE_SIZE 0x100
107#define CPSW2_CPDMA_OFFSET 0x800
d9718546 108#define CPSW2_HW_STATS 0x900
549985ee
RC		 109#define CPSW2_STATERAM_OFFSET 0xa00
110#define CPSW2_CPTS_OFFSET 0xc00
111#define CPSW2_ALE_OFFSET 0xd00
112#define CPSW2_SLIVER_OFFSET 0xd80
113#define CPSW2_BD_OFFSET 0x2000
114
df828598
M		 115#define CPDMA_RXTHRESH 0x0c0
116#define CPDMA_RXFREE 0x0e0
117#define CPDMA_TXHDP 0x00
118#define CPDMA_RXHDP 0x20
119#define CPDMA_TXCP 0x40
120#define CPDMA_RXCP 0x60
121
df828598 122#define CPSW_POLL_WEIGHT 64
9421c901
GS		 123#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
124#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
df828598
M		 125
126#define RX_PRIORITY_MAPPING 0x76543210
127#define TX_PRIORITY_MAPPING 0x33221100
e05107e6 128#define CPDMA_TX_PRIORITY_MAP 0x01234567
df828598 129
3b72c2fe
M		 130#define CPSW_VLAN_AWARE BIT(1)
131#define CPSW_ALE_VLAN_AWARE 1
132
35717d8d
JO		 133#define CPSW_FIFO_NORMAL_MODE (0 << 16)
134#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
135#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 136
ff5b8ef2
M		 137#define CPSW_INTPACEEN (0x3f << 16)
138#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
139#define CPSW_CMINTMAX_CNT 63
140#define CPSW_CMINTMIN_CNT 2
141#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
142#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143
606f3993
IK		 144#define cpsw_slave_index(cpsw, priv) \
145 ((cpsw->data.dual_emac) ? priv->emac_port : \
146 cpsw->data.active_slave)
e38b5a3d 147#define IRQ_NUM 2
e05107e6 148#define CPSW_MAX_QUEUES 8
90225bf0 149#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
d3bb9c58 150
df828598
M		 151static int debug_level;
152module_param(debug_level, int, 0);
153MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
154
155static int ale_ageout = 10;
156module_param(ale_ageout, int, 0);
157MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
158
159static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
160module_param(rx_packet_max, int, 0);
161MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
162
90225bf0
GS		 163static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
164module_param(descs_pool_size, int, 0444);
165MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
166
996a5c27 167struct cpsw_wr_regs {
df828598
M		 168 u32 id_ver;
169 u32 soft_reset;
170 u32 control;
171 u32 int_control;
172 u32 rx_thresh_en;
173 u32 rx_en;
174 u32 tx_en;
175 u32 misc_en;
ff5b8ef2
M		 176 u32 mem_allign1[8];
177 u32 rx_thresh_stat;
178 u32 rx_stat;
179 u32 tx_stat;
180 u32 misc_stat;
181 u32 mem_allign2[8];
182 u32 rx_imax;
183 u32 tx_imax;
184
df828598
M		 185};
186
996a5c27 187struct cpsw_ss_regs {
df828598
M		 188 u32 id_ver;
189 u32 control;
190 u32 soft_reset;
191 u32 stat_port_en;
192 u32 ptype;
bd357af2
RC		 193 u32 soft_idle;
194 u32 thru_rate;
195 u32 gap_thresh;
196 u32 tx_start_wds;
197 u32 flow_control;
198 u32 vlan_ltype;
199 u32 ts_ltype;
200 u32 dlr_ltype;
df828598
M		 201};
202
9750a3ad
RC		 203/* CPSW_PORT_V1 */
204#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
205#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
206#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
207#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
208#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
209#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
210#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
211#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
212
213/* CPSW_PORT_V2 */
214#define CPSW2_CONTROL 0x00 /* Control Register */
215#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
216#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
217#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
218#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
219#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
220#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
221
222/* CPSW_PORT_V1 and V2 */
223#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
224#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
225#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
226
227/* CPSW_PORT_V2 only */
228#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
229#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
230#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
231#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
236
237/* Bit definitions for the CPSW2_CONTROL register */
238#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
239#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
240#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
241#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
242#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
243#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
244#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
245#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
246#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
247#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 248#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
249#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 250#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
251#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
252#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
253#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
254#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
255
09c55372
GC		 256#define CTRL_V2_TS_BITS \
257 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
258 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 259
09c55372
GC		 260#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
261#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
262#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
263
264
265#define CTRL_V3_TS_BITS \
266 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
267 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
268 TS_LTYPE1_EN)
269
270#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
271#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
272#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 273
274/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
275#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
276#define TS_SEQ_ID_OFFSET_MASK (0x3f)
277#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
278#define TS_MSG_TYPE_EN_MASK (0xffff)
279
280/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
281#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 282
2e5b38ab
RC		 283/* Bit definitions for the CPSW1_TS_CTL register */
284#define CPSW_V1_TS_RX_EN BIT(0)
285#define CPSW_V1_TS_TX_EN BIT(4)
286#define CPSW_V1_MSG_TYPE_OFS 16
287
288/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
289#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
290
48f5bccc
GS		 291#define CPSW_MAX_BLKS_TX 15
292#define CPSW_MAX_BLKS_TX_SHIFT 4
293#define CPSW_MAX_BLKS_RX 5
294
df828598
M		 295struct cpsw_host_regs {
296 u32 max_blks;
297 u32 blk_cnt;
d9ba8f9e 298 u32 tx_in_ctl;
df828598
M		 299 u32 port_vlan;
300 u32 tx_pri_map;
301 u32 cpdma_tx_pri_map;
302 u32 cpdma_rx_chan_map;
303};
304
305struct cpsw_sliver_regs {
306 u32 id_ver;
307 u32 mac_control;
308 u32 mac_status;
309 u32 soft_reset;
310 u32 rx_maxlen;
311 u32 __reserved_0;
312 u32 rx_pause;
313 u32 tx_pause;
314 u32 __reserved_1;
315 u32 rx_pri_map;
316};
317
d9718546
M		 318struct cpsw_hw_stats {
319 u32 rxgoodframes;
320 u32 rxbroadcastframes;
321 u32 rxmulticastframes;
322 u32 rxpauseframes;
323 u32 rxcrcerrors;
324 u32 rxaligncodeerrors;
325 u32 rxoversizedframes;
326 u32 rxjabberframes;
327 u32 rxundersizedframes;
328 u32 rxfragments;
329 u32 __pad_0[2];
330 u32 rxoctets;
331 u32 txgoodframes;
332 u32 txbroadcastframes;
333 u32 txmulticastframes;
334 u32 txpauseframes;
335 u32 txdeferredframes;
336 u32 txcollisionframes;
337 u32 txsinglecollframes;
338 u32 txmultcollframes;
339 u32 txexcessivecollisions;
340 u32 txlatecollisions;
341 u32 txunderrun;
342 u32 txcarriersenseerrors;
343 u32 txoctets;
344 u32 octetframes64;
345 u32 octetframes65t127;
346 u32 octetframes128t255;
347 u32 octetframes256t511;
348 u32 octetframes512t1023;
349 u32 octetframes1024tup;
350 u32 netoctets;
351 u32 rxsofoverruns;
352 u32 rxmofoverruns;
353 u32 rxdmaoverruns;
354};
355
2c8a14d6
GS		 356struct cpsw_slave_data {
357 struct device_node *phy_node;
358 char phy_id[MII_BUS_ID_SIZE];
359 int phy_if;
360 u8 mac_addr[ETH_ALEN];
361 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
362};
363
364struct cpsw_platform_data {
365 struct cpsw_slave_data *slave_data;
366 u32 ss_reg_ofs; /* Subsystem control register offset */
367 u32 channels; /* number of cpdma channels (symmetric) */
368 u32 slaves; /* number of slave cpgmac ports */
369 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
370 u32 ale_entries; /* ale table size */
371 u32 bd_ram_size; /*buffer descriptor ram size */
372 u32 mac_control; /* Mac control register */
373 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
374 bool dual_emac; /* Enable Dual EMAC mode */
375};
376
df828598 377struct cpsw_slave {
9750a3ad 378 void __iomem *regs;
df828598
M		 379 struct cpsw_sliver_regs __iomem *sliver;
380 int slave_num;
381 u32 mac_control;
382 struct cpsw_slave_data *data;
383 struct phy_device *phy;
d9ba8f9e
M		 384 struct net_device *ndev;
385 u32 port_vlan;
df828598
M		 386};
387
9750a3ad
RC		 388static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
389{
dda5f5fe 390 return readl_relaxed(slave->regs + offset);
9750a3ad
RC		 391}
392
393static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
394{
dda5f5fe 395 writel_relaxed(val, slave->regs + offset);
9750a3ad
RC		 396}
397
8feb0a19
IK		 398struct cpsw_vector {
399 struct cpdma_chan *ch;
400 int budget;
401};
402
649a1688 403struct cpsw_common {
56e31bd8 404 struct device *dev;
606f3993 405 struct cpsw_platform_data data;
dbc4ec52
IK		 406 struct napi_struct napi_rx;
407 struct napi_struct napi_tx;
5d8d0d4d
IK		 408 struct cpsw_ss_regs __iomem *regs;
409 struct cpsw_wr_regs __iomem *wr_regs;
410 u8 __iomem *hw_stats;
411 struct cpsw_host_regs __iomem *host_port_regs;
2a05a622
IK		 412 u32 version;
413 u32 coal_intvl;
414 u32 bus_freq_mhz;
415 int rx_packet_max;
606f3993 416 struct cpsw_slave *slaves;
2c836bd9 417 struct cpdma_ctlr *dma;
8feb0a19
IK		 418 struct cpsw_vector txv[CPSW_MAX_QUEUES];
419 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
2a05a622 420 struct cpsw_ale *ale;
e38b5a3d
IK		 421 bool quirk_irq;
422 bool rx_irq_disabled;
423 bool tx_irq_disabled;
424 u32 irqs_table[IRQ_NUM];
2a05a622 425 struct cpts *cpts;
e05107e6 426 int rx_ch_num, tx_ch_num;
0be01b8e 427 int speed;
d5bc1613 428 int usage_count;
649a1688
IK		 429};
430
431struct cpsw_priv {
df828598 432 struct net_device *ndev;
df828598 433 struct device *dev;
df828598 434 u32 msg_enable;
df828598 435 u8 mac_addr[ETH_ALEN];
1923d6e4
M		 436 bool rx_pause;
437 bool tx_pause;
d9ba8f9e 438 u32 emac_port;
649a1688 439 struct cpsw_common *cpsw;
df828598
M		 440};
441
d9718546
M		 442struct cpsw_stats {
443 char stat_string[ETH_GSTRING_LEN];
444 int type;
445 int sizeof_stat;
446 int stat_offset;
447};
448
449enum {
450 CPSW_STATS,
451 CPDMA_RX_STATS,
452 CPDMA_TX_STATS,
453};
454
455#define CPSW_STAT(m) CPSW_STATS, \
456 sizeof(((struct cpsw_hw_stats *)0)->m), \
457 offsetof(struct cpsw_hw_stats, m)
458#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
459 sizeof(((struct cpdma_chan_stats *)0)->m), \
460 offsetof(struct cpdma_chan_stats, m)
461#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
462 sizeof(((struct cpdma_chan_stats *)0)->m), \
463 offsetof(struct cpdma_chan_stats, m)
464
465static const struct cpsw_stats cpsw_gstrings_stats[] = {
466 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
467 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
468 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
469 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
470 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
471 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
472 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
473 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
474 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
475 { "Rx Fragments", CPSW_STAT(rxfragments) },
476 { "Rx Octets", CPSW_STAT(rxoctets) },
477 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
478 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
479 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
480 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
481 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
482 { "Collisions", CPSW_STAT(txcollisionframes) },
483 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
484 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
485 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
486 { "Late Collisions", CPSW_STAT(txlatecollisions) },
487 { "Tx Underrun", CPSW_STAT(txunderrun) },
488 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
489 { "Tx Octets", CPSW_STAT(txoctets) },
490 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
491 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
492 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
493 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
494 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
495 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
496 { "Net Octets", CPSW_STAT(netoctets) },
497 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
498 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
499 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
d9718546
M		 500};
501
e05107e6
IK		 502static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
503 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
504 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
505 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
506 { "misqueued", CPDMA_RX_STAT(misqueued) },
507 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
508 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
509 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
510 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
511 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
512 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
513 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
514 { "requeue", CPDMA_RX_STAT(requeue) },
515 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
516};
517
518#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
519#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
d9718546 520
649a1688 521#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
dbc4ec52 522#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
d9ba8f9e
M		 523#define for_each_slave(priv, func, arg...) \
524 do { \
6e6ceaed 525 struct cpsw_slave *slave; \
606f3993 526 struct cpsw_common *cpsw = (priv)->cpsw; \
6e6ceaed 527 int n; \
606f3993
IK		 528 if (cpsw->data.dual_emac) \
529 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
d9ba8f9e 530 else \
606f3993
IK		 531 for (n = cpsw->data.slaves, \
532 slave = cpsw->slaves; \
6e6ceaed
SS		 533 n; n--) \
534 (func)(slave++, ##arg); \
d9ba8f9e 535 } while (0)
d9ba8f9e 536
2a05a622 537#define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
d9ba8f9e 538 do { \
606f3993 539 if (!cpsw->data.dual_emac) \
d9ba8f9e
M		 540 break; \
541 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
606f3993 542 ndev = cpsw->slaves[0].ndev; \
d9ba8f9e
M		 543 skb->dev = ndev; \
544 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
606f3993 545 ndev = cpsw->slaves[1].ndev; \
d9ba8f9e
M		 546 skb->dev = ndev; \
547 } \
df828598 548 } while (0)
606f3993 549#define cpsw_add_mcast(cpsw, priv, addr) \
d9ba8f9e 550 do { \
606f3993
IK		 551 if (cpsw->data.dual_emac) { \
552 struct cpsw_slave *slave = cpsw->slaves + \
d9ba8f9e 553 priv->emac_port; \
6f1f5836 554 int slave_port = cpsw_get_slave_port( \
d9ba8f9e 555 slave->slave_num); \
2a05a622 556 cpsw_ale_add_mcast(cpsw->ale, addr, \
71a2cbb7 557 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 558 ALE_VLAN, slave->port_vlan, 0); \
559 } else { \
2a05a622 560 cpsw_ale_add_mcast(cpsw->ale, addr, \
61f1cef9 561 ALE_ALL_PORTS, \
d9ba8f9e
M		 562 0, 0, 0); \
563 } \
564 } while (0)
565
6f1f5836 566static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 567{
71a2cbb7 568 return slave_num + 1;
d9ba8f9e 569}
df828598 570
0cd8f9cc
M		 571static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
572{
2a05a622
IK		 573 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
574 struct cpsw_ale *ale = cpsw->ale;
0cd8f9cc
M		 575 int i;
576
606f3993 577 if (cpsw->data.dual_emac) {
0cd8f9cc
M		 578 bool flag = false;
579
580 /* Enabling promiscuous mode for one interface will be
581 * common for both the interface as the interface shares
582 * the same hardware resource.
583 */
606f3993
IK		 584 for (i = 0; i < cpsw->data.slaves; i++)
585 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
0cd8f9cc
M		 586 flag = true;
587
588 if (!enable && flag) {
589 enable = true;
590 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
591 }
592
593 if (enable) {
594 /* Enable Bypass */
595 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
596
597 dev_dbg(&ndev->dev, "promiscuity enabled\n");
598 } else {
599 /* Disable Bypass */
600 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
601 dev_dbg(&ndev->dev, "promiscuity disabled\n");
602 }
603 } else {
604 if (enable) {
605 unsigned long timeout = jiffies + HZ;
606
6f979eb3 607 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 608 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 609 cpsw_ale_control_set(ale, i,
610 ALE_PORT_NOLEARN, 1);
611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NO_SA_UPDATE, 1);
613 }
614
615 /* Clear All Untouched entries */
616 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
617 do {
618 cpu_relax();
619 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
620 break;
621 } while (time_after(timeout, jiffies));
622 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
623
624 /* Clear all mcast from ALE */
61f1cef9 625 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 626
627 /* Flood All Unicast Packets to Host port */
628 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
629 dev_dbg(&ndev->dev, "promiscuity enabled\n");
630 } else {
6f979eb3 631 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 632 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
633
6f979eb3 634 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
606f3993 635 for (i = 0; i <= cpsw->data.slaves; i++) {
0cd8f9cc
M		 636 cpsw_ale_control_set(ale, i,
637 ALE_PORT_NOLEARN, 0);
638 cpsw_ale_control_set(ale, i,
639 ALE_PORT_NO_SA_UPDATE, 0);
640 }
641 dev_dbg(&ndev->dev, "promiscuity disabled\n");
642 }
643 }
644}
645
5c50a856
M		 646static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
647{
648 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993 649 struct cpsw_common *cpsw = priv->cpsw;
25906052
M		 650 int vid;
651
606f3993
IK		 652 if (cpsw->data.dual_emac)
653 vid = cpsw->slaves[priv->emac_port].port_vlan;
25906052 654 else
606f3993 655 vid = cpsw->data.default_vlan;
5c50a856
M		 656
657 if (ndev->flags & IFF_PROMISC) {
658 /* Enable promiscuous mode */
0cd8f9cc 659 cpsw_set_promiscious(ndev, true);
2a05a622 660 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
5c50a856 661 return;
0cd8f9cc
M		 662 } else {
663 /* Disable promiscuous mode */
664 cpsw_set_promiscious(ndev, false);
5c50a856
M		 665 }
666
1e5c4bc4 667 /* Restore allmulti on vlans if necessary */
2a05a622 668 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
1e5c4bc4 669
5c50a856 670 /* Clear all mcast from ALE */
2a05a622 671 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 672
673 if (!netdev_mc_empty(ndev)) {
674 struct netdev_hw_addr *ha;
675
676 /* program multicast address list into ALE register */
677 netdev_for_each_mc_addr(ha, ndev) {
606f3993 678 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
5c50a856
M		 679 }
680 }
681}
682
2c836bd9 683static void cpsw_intr_enable(struct cpsw_common *cpsw)
df828598 684{
dda5f5fe
GS		 685 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
686 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
df828598 687
2c836bd9 688 cpdma_ctlr_int_ctrl(cpsw->dma, true);
df828598
M		 689 return;
690}
691
2c836bd9 692static void cpsw_intr_disable(struct cpsw_common *cpsw)
df828598 693{
dda5f5fe
GS		 694 writel_relaxed(0, &cpsw->wr_regs->tx_en);
695 writel_relaxed(0, &cpsw->wr_regs->rx_en);
df828598 696
2c836bd9 697 cpdma_ctlr_int_ctrl(cpsw->dma, false);
df828598
M		 698 return;
699}
700
1a3b5056 701static void cpsw_tx_handler(void *token, int len, int status)
df828598 702{
e05107e6 703 struct netdev_queue *txq;
df828598
M		 704 struct sk_buff *skb = token;
705 struct net_device *ndev = skb->dev;
2a05a622 706 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 707
fae50823
M		 708 /* Check whether the queue is stopped due to stalled tx dma, if the
709 * queue is stopped then start the queue as we have free desc for tx
710 */
e05107e6
IK		 711 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
712 if (unlikely(netif_tx_queue_stopped(txq)))
713 netif_tx_wake_queue(txq);
714
2a05a622 715 cpts_tx_timestamp(cpsw->cpts, skb);
8dc43ddc
TK		 716 ndev->stats.tx_packets++;
717 ndev->stats.tx_bytes += len;
df828598
M		 718 dev_kfree_skb_any(skb);
719}
720
1a3b5056 721static void cpsw_rx_handler(void *token, int len, int status)
df828598 722{
e05107e6 723 struct cpdma_chan *ch;
df828598 724 struct sk_buff *skb = token;
b4727e69 725 struct sk_buff *new_skb;
df828598 726 struct net_device *ndev = skb->dev;
df828598 727 int ret = 0;
2a05a622 728 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 729
2a05a622 730 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
d9ba8f9e 731
16e5c57d 732 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
fe734d0a 733 /* In dual emac mode check for all interfaces */
d5bc1613 734 if (cpsw->data.dual_emac && cpsw->usage_count &&
fe734d0a 735 (status >= 0)) {
a0e2c822
M		 736 /* The packet received is for the interface which
737 * is already down and the other interface is up
dbedd44e 738 * and running, instead of freeing which results
a0e2c822
M		 739 * in reducing of the number of rx descriptor in
740 * DMA engine, requeue skb back to cpdma.
741 */
742 new_skb = skb;
743 goto requeue;
744 }
745
b4727e69 746 /* the interface is going down, skbs are purged */
df828598
M		 747 dev_kfree_skb_any(skb);
748 return;
749 }
b4727e69 750
2a05a622 751 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
b4727e69 752 if (new_skb) {
e05107e6 753 skb_copy_queue_mapping(new_skb, skb);
df828598 754 skb_put(skb, len);
2a05a622 755 cpts_rx_timestamp(cpsw->cpts, skb);
df828598
M		 756 skb->protocol = eth_type_trans(skb, ndev);
757 netif_receive_skb(skb);
8dc43ddc
TK		 758 ndev->stats.rx_bytes += len;
759 ndev->stats.rx_packets++;
254a49d5 760 kmemleak_not_leak(new_skb);
b4727e69 761 } else {
8dc43ddc 762 ndev->stats.rx_dropped++;
b4727e69 763 new_skb = skb;
df828598
M		 764 }
765
a0e2c822 766requeue:
ce52c744
IK		 767 if (netif_dormant(ndev)) {
768 dev_kfree_skb_any(new_skb);
769 return;
770 }
771
8feb0a19 772 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
e05107e6 773 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
2c836bd9 774 skb_tailroom(new_skb), 0);
b4727e69
SS		 775 if (WARN_ON(ret < 0))
776 dev_kfree_skb_any(new_skb);
df828598
M		 777}
778
32b78d85 779static void cpsw_split_res(struct net_device *ndev)
48e0a83e
IK		 780{
781 struct cpsw_priv *priv = netdev_priv(ndev);
32b78d85 782 u32 consumed_rate = 0, bigest_rate = 0;
48e0a83e
IK		 783 struct cpsw_common *cpsw = priv->cpsw;
784 struct cpsw_vector *txv = cpsw->txv;
32b78d85 785 int i, ch_weight, rlim_ch_num = 0;
48e0a83e 786 int budget, bigest_rate_ch = 0;
48e0a83e
IK		 787 u32 ch_rate, max_rate;
788 int ch_budget = 0;
789
48e0a83e
IK		 790 for (i = 0; i < cpsw->tx_ch_num; i++) {
791 ch_rate = cpdma_chan_get_rate(txv[i].ch);
792 if (!ch_rate)
793 continue;
794
795 rlim_ch_num++;
796 consumed_rate += ch_rate;
797 }
798
799 if (cpsw->tx_ch_num == rlim_ch_num) {
800 max_rate = consumed_rate;
32b78d85
IK		 801 } else if (!rlim_ch_num) {
802 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
803 bigest_rate = 0;
804 max_rate = consumed_rate;
48e0a83e 805 } else {
0be01b8e
IK		 806 max_rate = cpsw->speed * 1000;
807
808 /* if max_rate is less then expected due to reduced link speed,
809 * split proportionally according next potential max speed
810 */
811 if (max_rate < consumed_rate)
812 max_rate *= 10;
813
814 if (max_rate < consumed_rate)
815 max_rate *= 10;
32b78d85 816
48e0a83e
IK		 817 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
818 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
819 (cpsw->tx_ch_num - rlim_ch_num);
820 bigest_rate = (max_rate - consumed_rate) /
821 (cpsw->tx_ch_num - rlim_ch_num);
822 }
823
32b78d85 824 /* split tx weight/budget */
48e0a83e
IK		 825 budget = CPSW_POLL_WEIGHT;
826 for (i = 0; i < cpsw->tx_ch_num; i++) {
827 ch_rate = cpdma_chan_get_rate(txv[i].ch);
828 if (ch_rate) {
829 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
830 if (!txv[i].budget)
32b78d85 831 txv[i].budget++;
48e0a83e
IK		 832 if (ch_rate > bigest_rate) {
833 bigest_rate_ch = i;
834 bigest_rate = ch_rate;
835 }
32b78d85
IK		 836
837 ch_weight = (ch_rate * 100) / max_rate;
838 if (!ch_weight)
839 ch_weight++;
840 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
48e0a83e
IK		 841 } else {
842 txv[i].budget = ch_budget;
843 if (!bigest_rate_ch)
844 bigest_rate_ch = i;
32b78d85 845 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
48e0a83e
IK		 846 }
847
848 budget -= txv[i].budget;
849 }
850
851 if (budget)
852 txv[bigest_rate_ch].budget += budget;
853
854 /* split rx budget */
855 budget = CPSW_POLL_WEIGHT;
856 ch_budget = budget / cpsw->rx_ch_num;
857 for (i = 0; i < cpsw->rx_ch_num; i++) {
858 cpsw->rxv[i].budget = ch_budget;
859 budget -= ch_budget;
860 }
861
862 if (budget)
863 cpsw->rxv[0].budget += budget;
864}
865
c03abd84 866static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598 867{
dbc4ec52 868 struct cpsw_common *cpsw = dev_id;
7ce67a38 869
5d8d0d4d 870 writel(0, &cpsw->wr_regs->tx_en);
2c836bd9 871 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
c03abd84 872
e38b5a3d
IK		 873 if (cpsw->quirk_irq) {
874 disable_irq_nosync(cpsw->irqs_table[1]);
875 cpsw->tx_irq_disabled = true;
7da11600
M		 876 }
877
dbc4ec52 878 napi_schedule(&cpsw->napi_tx);
c03abd84
FB		 879 return IRQ_HANDLED;
880}
881
882static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
883{
dbc4ec52 884 struct cpsw_common *cpsw = dev_id;
c03abd84 885
2c836bd9 886 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
5d8d0d4d 887 writel(0, &cpsw->wr_regs->rx_en);
fd51cf19 888
e38b5a3d
IK		 889 if (cpsw->quirk_irq) {
890 disable_irq_nosync(cpsw->irqs_table[0]);
891 cpsw->rx_irq_disabled = true;
7da11600
M		 892 }
893
dbc4ec52 894 napi_schedule(&cpsw->napi_rx);
d354eb85 895 return IRQ_HANDLED;
df828598
M		 896}
897
32a7432c
M		 898static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
899{
e05107e6 900 u32 ch_map;
8feb0a19 901 int num_tx, cur_budget, ch;
dbc4ec52 902 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
8feb0a19 903 struct cpsw_vector *txv;
32a7432c 904
e05107e6
IK		 905 /* process every unprocessed channel */
906 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
342934a5 907 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
e05107e6
IK		 908 if (!(ch_map & 0x01))
909 continue;
910
8feb0a19
IK		 911 txv = &cpsw->txv[ch];
912 if (unlikely(txv->budget > budget - num_tx))
913 cur_budget = budget - num_tx;
914 else
915 cur_budget = txv->budget;
916
917 num_tx += cpdma_chan_process(txv->ch, cur_budget);
342934a5
IK		 918 if (num_tx >= budget)
919 break;
e05107e6
IK		 920 }
921
32a7432c
M		 922 if (num_tx < budget) {
923 napi_complete(napi_tx);
5d8d0d4d 924 writel(0xff, &cpsw->wr_regs->tx_en);
e38b5a3d
IK		 925 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
926 cpsw->tx_irq_disabled = false;
927 enable_irq(cpsw->irqs_table[1]);
7da11600 928 }
32a7432c
M		 929 }
930
32a7432c
M		 931 return num_tx;
932}
933
934static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 935{
e05107e6 936 u32 ch_map;
8feb0a19 937 int num_rx, cur_budget, ch;
dbc4ec52 938 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
8feb0a19 939 struct cpsw_vector *rxv;
df828598 940
e05107e6
IK		 941 /* process every unprocessed channel */
942 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
342934a5 943 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
e05107e6
IK		 944 if (!(ch_map & 0x01))
945 continue;
946
8feb0a19
IK		 947 rxv = &cpsw->rxv[ch];
948 if (unlikely(rxv->budget > budget - num_rx))
949 cur_budget = budget - num_rx;
950 else
951 cur_budget = rxv->budget;
952
953 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
342934a5
IK		 954 if (num_rx >= budget)
955 break;
e05107e6
IK		 956 }
957
df828598 958 if (num_rx < budget) {
6ad20165 959 napi_complete_done(napi_rx, num_rx);
5d8d0d4d 960 writel(0xff, &cpsw->wr_regs->rx_en);
e38b5a3d
IK		 961 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
962 cpsw->rx_irq_disabled = false;
963 enable_irq(cpsw->irqs_table[0]);
7da11600 964 }
df828598
M		 965 }
966
967 return num_rx;
968}
969
970static inline void soft_reset(const char *module, void __iomem *reg)
971{
972 unsigned long timeout = jiffies + HZ;
973
dda5f5fe 974 writel_relaxed(1, reg);
df828598
M		 975 do {
976 cpu_relax();
dda5f5fe 977 } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
df828598 978
dda5f5fe 979 WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
df828598
M		 980}
981
df828598
M		 982static void cpsw_set_slave_mac(struct cpsw_slave *slave,
983 struct cpsw_priv *priv)
984{
9750a3ad
RC		 985 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
986 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 987}
988
989static void _cpsw_adjust_link(struct cpsw_slave *slave,
990 struct cpsw_priv *priv, bool *link)
991{
992 struct phy_device *phy = slave->phy;
993 u32 mac_control = 0;
994 u32 slave_port;
606f3993 995 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 996
997 if (!phy)
998 return;
999
6f1f5836 1000 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 1001
1002 if (phy->link) {
606f3993 1003 mac_control = cpsw->data.mac_control;
df828598
M		 1004
1005 /* enable forwarding */
2a05a622 1006 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 1007 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1008
1009 if (phy->speed == 1000)
1010 mac_control |= BIT(7); /* GIGABITEN */
1011 if (phy->duplex)
1012 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 1013
1014 /* set speed_in input in case RMII mode is used in 100Mbps */
1015 if (phy->speed == 100)
1016 mac_control |= BIT(15);
a81d8762
M		 1017 else if (phy->speed == 10)
1018 mac_control |= BIT(18); /* In Band mode */
342b7b74 1019
1923d6e4
M		 1020 if (priv->rx_pause)
1021 mac_control |= BIT(3);
1022
1023 if (priv->tx_pause)
1024 mac_control |= BIT(4);
1025
df828598
M		 1026 *link = true;
1027 } else {
1028 mac_control = 0;
1029 /* disable forwarding */
2a05a622 1030 cpsw_ale_control_set(cpsw->ale, slave_port,
df828598
M		 1031 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1032 }
1033
1034 if (mac_control != slave->mac_control) {
1035 phy_print_status(phy);
dda5f5fe 1036 writel_relaxed(mac_control, &slave->sliver->mac_control);
df828598
M		 1037 }
1038
1039 slave->mac_control = mac_control;
1040}
1041
0be01b8e
IK		 1042static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1043{
1044 int i, speed;
1045
1046 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1047 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1048 speed += cpsw->slaves[i].phy->speed;
1049
1050 return speed;
1051}
1052
1053static int cpsw_need_resplit(struct cpsw_common *cpsw)
1054{
1055 int i, rlim_ch_num;
1056 int speed, ch_rate;
1057
1058 /* re-split resources only in case speed was changed */
1059 speed = cpsw_get_common_speed(cpsw);
1060 if (speed == cpsw->speed || !speed)
1061 return 0;
1062
1063 cpsw->speed = speed;
1064
1065 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1066 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1067 if (!ch_rate)
1068 break;
1069
1070 rlim_ch_num++;
1071 }
1072
1073 /* cases not dependent on speed */
1074 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1075 return 0;
1076
1077 return 1;
1078}
1079
df828598
M		 1080static void cpsw_adjust_link(struct net_device *ndev)
1081{
1082 struct cpsw_priv *priv = netdev_priv(ndev);
0be01b8e 1083 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1084 bool link = false;
1085
1086 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1087
1088 if (link) {
0be01b8e
IK		 1089 if (cpsw_need_resplit(cpsw))
1090 cpsw_split_res(ndev);
1091
df828598
M		 1092 netif_carrier_on(ndev);
1093 if (netif_running(ndev))
e05107e6 1094 netif_tx_wake_all_queues(ndev);
df828598
M		 1095 } else {
1096 netif_carrier_off(ndev);
e05107e6 1097 netif_tx_stop_all_queues(ndev);
df828598
M		 1098 }
1099}
1100
ff5b8ef2
M		 1101static int cpsw_get_coalesce(struct net_device *ndev,
1102 struct ethtool_coalesce *coal)
1103{
2a05a622 1104 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
ff5b8ef2 1105
2a05a622 1106 coal->rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 1107 return 0;
1108}
1109
1110static int cpsw_set_coalesce(struct net_device *ndev,
1111 struct ethtool_coalesce *coal)
1112{
1113 struct cpsw_priv *priv = netdev_priv(ndev);
1114 u32 int_ctrl;
1115 u32 num_interrupts = 0;
1116 u32 prescale = 0;
1117 u32 addnl_dvdr = 1;
1118 u32 coal_intvl = 0;
5d8d0d4d 1119 struct cpsw_common *cpsw = priv->cpsw;
ff5b8ef2 1120
ff5b8ef2
M		 1121 coal_intvl = coal->rx_coalesce_usecs;
1122
5d8d0d4d 1123 int_ctrl = readl(&cpsw->wr_regs->int_control);
2a05a622 1124 prescale = cpsw->bus_freq_mhz * 4;
ff5b8ef2 1125
a84bc2a9
M		 1126 if (!coal->rx_coalesce_usecs) {
1127 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1128 goto update_return;
1129 }
1130
ff5b8ef2
M		 1131 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1132 coal_intvl = CPSW_CMINTMIN_INTVL;
1133
1134 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1135 /* Interrupt pacer works with 4us Pulse, we can
1136 * throttle further by dilating the 4us pulse.
1137 */
1138 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1139
1140 if (addnl_dvdr > 1) {
1141 prescale *= addnl_dvdr;
1142 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1143 coal_intvl = (CPSW_CMINTMAX_INTVL
1144 * addnl_dvdr);
1145 } else {
1146 addnl_dvdr = 1;
1147 coal_intvl = CPSW_CMINTMAX_INTVL;
1148 }
1149 }
1150
1151 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
5d8d0d4d
IK		 1152 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1153 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
ff5b8ef2
M		 1154
1155 int_ctrl |= CPSW_INTPACEEN;
1156 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1157 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 1158
1159update_return:
5d8d0d4d 1160 writel(int_ctrl, &cpsw->wr_regs->int_control);
ff5b8ef2
M		 1161
1162 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
2a05a622 1163 cpsw->coal_intvl = coal_intvl;
ff5b8ef2
M		 1164
1165 return 0;
1166}
1167
d9718546
M		 1168static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1169{
e05107e6
IK		 1170 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1171
d9718546
M		 1172 switch (sset) {
1173 case ETH_SS_STATS:
e05107e6
IK		 1174 return (CPSW_STATS_COMMON_LEN +
1175 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1176 CPSW_STATS_CH_LEN);
d9718546
M		 1177 default:
1178 return -EOPNOTSUPP;
1179 }
1180}
1181
e05107e6
IK		 1182static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1183{
1184 int ch_stats_len;
1185 int line;
1186 int i;
1187
1188 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1189 for (i = 0; i < ch_stats_len; i++) {
1190 line = i % CPSW_STATS_CH_LEN;
1191 snprintf(*p, ETH_GSTRING_LEN,
1192 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1193 i / CPSW_STATS_CH_LEN,
1194 cpsw_gstrings_ch_stats[line].stat_string);
1195 *p += ETH_GSTRING_LEN;
1196 }
1197}
1198
d9718546
M		 1199static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1200{
e05107e6 1201 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
d9718546
M		 1202 u8 *p = data;
1203 int i;
1204
1205 switch (stringset) {
1206 case ETH_SS_STATS:
e05107e6 1207 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
d9718546
M		 1208 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1209 ETH_GSTRING_LEN);
1210 p += ETH_GSTRING_LEN;
1211 }
e05107e6
IK		 1212
1213 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1214 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
d9718546
M		 1215 break;
1216 }
1217}
1218
1219static void cpsw_get_ethtool_stats(struct net_device *ndev,
1220 struct ethtool_stats *stats, u64 *data)
1221{
d9718546 1222 u8 *p;
2c836bd9 1223 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
e05107e6
IK		 1224 struct cpdma_chan_stats ch_stats;
1225 int i, l, ch;
d9718546
M		 1226
1227 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
e05107e6
IK		 1228 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1229 data[l] = readl(cpsw->hw_stats +
1230 cpsw_gstrings_stats[l].stat_offset);
1231
1232 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
8feb0a19 1233 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
e05107e6
IK		 1234 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1235 p = (u8 *)&ch_stats +
1236 cpsw_gstrings_ch_stats[i].stat_offset;
1237 data[l] = *(u32 *)p;
1238 }
1239 }
d9718546 1240
e05107e6 1241 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
8feb0a19 1242 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
e05107e6
IK		 1243 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1244 p = (u8 *)&ch_stats +
1245 cpsw_gstrings_ch_stats[i].stat_offset;
1246 data[l] = *(u32 *)p;
d9718546
M		 1247 }
1248 }
1249}
1250
27e9e103 1251static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
e05107e6
IK		 1252 struct sk_buff *skb,
1253 struct cpdma_chan *txch)
d9ba8f9e 1254{
2c836bd9
IK		 1255 struct cpsw_common *cpsw = priv->cpsw;
1256
98fdd857 1257 skb_tx_timestamp(skb);
e05107e6 1258 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
606f3993 1259 priv->emac_port + cpsw->data.dual_emac);
d9ba8f9e
M		 1260}
1261
1262static inline void cpsw_add_dual_emac_def_ale_entries(
1263 struct cpsw_priv *priv, struct cpsw_slave *slave,
1264 u32 slave_port)
1265{
2a05a622 1266 struct cpsw_common *cpsw = priv->cpsw;
71a2cbb7 1267 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e 1268
2a05a622 1269 if (cpsw->version == CPSW_VERSION_1)
d9ba8f9e
M		 1270 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1271 else
1272 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
2a05a622 1273 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
d9ba8f9e 1274 port_mask, port_mask, 0);
2a05a622 1275 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1276 port_mask, ALE_VLAN, slave->port_vlan, 0);
2a05a622
IK		 1277 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1278 HOST_PORT_NUM, ALE_VLAN |
1279 ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1280}
1281
1e7a2e21 1282static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1283{
1284 char name[32];
df828598 1285
1e7a2e21 1286 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1287 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1288}
1289
1290static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1291{
1292 u32 slave_port;
30c57f07 1293 struct phy_device *phy;
649a1688 1294 struct cpsw_common *cpsw = priv->cpsw;
1e7a2e21
DM		 1295
1296 soft_reset_slave(slave);
df828598
M		 1297
1298 /* setup priority mapping */
dda5f5fe 1299 writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad 1300
2a05a622 1301 switch (cpsw->version) {
9750a3ad
RC		 1302 case CPSW_VERSION_1:
1303 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
48f5bccc
GS		 1304 /* Increase RX FIFO size to 5 for supporting fullduplex
1305 * flow control mode
1306 */
1307 slave_write(slave,
1308 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1309 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
9750a3ad
RC		 1310 break;
1311 case CPSW_VERSION_2:
c193f365 1312 case CPSW_VERSION_3:
926489be 1313 case CPSW_VERSION_4:
9750a3ad 1314 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
48f5bccc
GS		 1315 /* Increase RX FIFO size to 5 for supporting fullduplex
1316 * flow control mode
1317 */
1318 slave_write(slave,
1319 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1320 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
9750a3ad
RC		 1321 break;
1322 }
df828598
M		 1323
1324 /* setup max packet size, and mac address */
dda5f5fe 1325 writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
df828598
M		 1326 cpsw_set_slave_mac(slave, priv);
1327
1328 slave->mac_control = 0; /* no link yet */
1329
6f1f5836 1330 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1331
606f3993 1332 if (cpsw->data.dual_emac)
d9ba8f9e
M		 1333 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1334 else
2a05a622 1335 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
d9ba8f9e 1336 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1337
d733f754 1338 if (slave->data->phy_node) {
30c57f07 1339 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1340 &cpsw_adjust_link, 0, slave->data->phy_if);
30c57f07 1341 if (!phy) {
f7ce9103
RH		 1342 dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1343 slave->data->phy_node,
d733f754
DR		 1344 slave->slave_num);
1345 return;
1346 }
1347 } else {
30c57f07 1348 phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1349 &cpsw_adjust_link, slave->data->phy_if);
30c57f07 1350 if (IS_ERR(phy)) {
d733f754
DR		 1351 dev_err(priv->dev,
1352 "phy \"%s\" not found on slave %d, err %ld\n",
1353 slave->data->phy_id, slave->slave_num,
30c57f07 1354 PTR_ERR(phy));
d733f754
DR		 1355 return;
1356 }
1357 }
2220943a 1358
30c57f07
SN		 1359 slave->phy = phy;
1360
d733f754 1361 phy_attached_info(slave->phy);
388367a5 1362
d733f754
DR		 1363 phy_start(slave->phy);
1364
1365 /* Configure GMII_SEL register */
56e31bd8 1366 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1367}
1368
3b72c2fe
M		 1369static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1370{
606f3993
IK		 1371 struct cpsw_common *cpsw = priv->cpsw;
1372 const int vlan = cpsw->data.default_vlan;
3b72c2fe
M		 1373 u32 reg;
1374 int i;
1e5c4bc4 1375 int unreg_mcast_mask;
3b72c2fe 1376
2a05a622 1377 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
3b72c2fe
M		 1378 CPSW2_PORT_VLAN;
1379
5d8d0d4d 1380 writel(vlan, &cpsw->host_port_regs->port_vlan);
3b72c2fe 1381
606f3993
IK		 1382 for (i = 0; i < cpsw->data.slaves; i++)
1383 slave_write(cpsw->slaves + i, vlan, reg);
3b72c2fe 1384
1e5c4bc4
LS		 1385 if (priv->ndev->flags & IFF_ALLMULTI)
1386 unreg_mcast_mask = ALE_ALL_PORTS;
1387 else
1388 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1389
2a05a622 1390 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
61f1cef9
GS		 1391 ALE_ALL_PORTS, ALE_ALL_PORTS,
1392 unreg_mcast_mask);
3b72c2fe
M		 1393}
1394
df828598
M		 1395static void cpsw_init_host_port(struct cpsw_priv *priv)
1396{
d9ba8f9e 1397 u32 fifo_mode;
5d8d0d4d
IK		 1398 u32 control_reg;
1399 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe 1400
df828598 1401 /* soft reset the controller and initialize ale */
5d8d0d4d 1402 soft_reset("cpsw", &cpsw->regs->soft_reset);
2a05a622 1403 cpsw_ale_start(cpsw->ale);
df828598
M		 1404
1405 /* switch to vlan unaware mode */
2a05a622 1406 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe 1407 CPSW_ALE_VLAN_AWARE);
5d8d0d4d 1408 control_reg = readl(&cpsw->regs->control);
3b72c2fe 1409 control_reg |= CPSW_VLAN_AWARE;
5d8d0d4d 1410 writel(control_reg, &cpsw->regs->control);
606f3993 1411 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
d9ba8f9e 1412 CPSW_FIFO_NORMAL_MODE;
5d8d0d4d 1413 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
df828598
M		 1414
1415 /* setup host port priority mapping */
dda5f5fe
GS		 1416 writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1417 &cpsw->host_port_regs->cpdma_tx_pri_map);
1418 writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
df828598 1419
2a05a622 1420 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
df828598
M		 1421 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1422
606f3993 1423 if (!cpsw->data.dual_emac) {
2a05a622 1424 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e 1425 0, 0);
2a05a622 1426 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
71a2cbb7 1427 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1428 }
df828598
M		 1429}
1430
3802dce1
IK		 1431static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1432{
1433 struct cpsw_common *cpsw = priv->cpsw;
1434 struct sk_buff *skb;
1435 int ch_buf_num;
e05107e6
IK		 1436 int ch, i, ret;
1437
1438 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
8feb0a19 1439 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
e05107e6
IK		 1440 for (i = 0; i < ch_buf_num; i++) {
1441 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1442 cpsw->rx_packet_max,
1443 GFP_KERNEL);
1444 if (!skb) {
1445 cpsw_err(priv, ifup, "cannot allocate skb\n");
1446 return -ENOMEM;
1447 }
3802dce1 1448
e05107e6 1449 skb_set_queue_mapping(skb, ch);
8feb0a19
IK		 1450 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1451 skb->data, skb_tailroom(skb),
1452 0);
e05107e6
IK		 1453 if (ret < 0) {
1454 cpsw_err(priv, ifup,
1455 "cannot submit skb to channel %d rx, error %d\n",
1456 ch, ret);
1457 kfree_skb(skb);
1458 return ret;
1459 }
1460 kmemleak_not_leak(skb);
3802dce1 1461 }
3802dce1 1462
e05107e6
IK		 1463 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1464 ch, ch_buf_num);
1465 }
3802dce1 1466
e05107e6 1467 return 0;
3802dce1
IK		 1468}
1469
2a05a622 1470static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
aacebbf8 1471{
3995d265
SP		 1472 u32 slave_port;
1473
6f1f5836 1474 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1475
aacebbf8
SS		 1476 if (!slave->phy)
1477 return;
1478 phy_stop(slave->phy);
1479 phy_disconnect(slave->phy);
1480 slave->phy = NULL;
2a05a622 1481 cpsw_ale_control_set(cpsw->ale, slave_port,
3995d265 1482 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1483 soft_reset_slave(slave);
aacebbf8
SS		 1484}
1485
df828598
M		 1486static int cpsw_ndo_open(struct net_device *ndev)
1487{
1488 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1489 struct cpsw_common *cpsw = priv->cpsw;
3802dce1 1490 int ret;
df828598
M		 1491 u32 reg;
1492
56e31bd8 1493 ret = pm_runtime_get_sync(cpsw->dev);
108a6537 1494 if (ret < 0) {
56e31bd8 1495 pm_runtime_put_noidle(cpsw->dev);
108a6537
GS		 1496 return ret;
1497 }
3fa88c51 1498
df828598
M		 1499 netif_carrier_off(ndev);
1500
e05107e6
IK		 1501 /* Notify the stack of the actual queue counts. */
1502 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1503 if (ret) {
1504 dev_err(priv->dev, "cannot set real number of tx queues\n");
1505 goto err_cleanup;
1506 }
1507
1508 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1509 if (ret) {
1510 dev_err(priv->dev, "cannot set real number of rx queues\n");
1511 goto err_cleanup;
1512 }
1513
2a05a622 1514 reg = cpsw->version;
df828598
M		 1515
1516 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1517 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1518 CPSW_RTL_VERSION(reg));
1519
d5bc1613
IK		 1520 /* Initialize host and slave ports */
1521 if (!cpsw->usage_count)
d9ba8f9e 1522 cpsw_init_host_port(priv);
df828598
M		 1523 for_each_slave(priv, cpsw_slave_open, priv);
1524
3b72c2fe 1525 /* Add default VLAN */
606f3993 1526 if (!cpsw->data.dual_emac)
e6afea0b
M		 1527 cpsw_add_default_vlan(priv);
1528 else
2a05a622 1529 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
61f1cef9 1530 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1531
d5bc1613
IK		 1532 /* initialize shared resources for every ndev */
1533 if (!cpsw->usage_count) {
d9ba8f9e 1534 /* disable priority elevation */
dda5f5fe 1535 writel_relaxed(0, &cpsw->regs->ptype);
df828598 1536
d9ba8f9e 1537 /* enable statistics collection only on all ports */
dda5f5fe 1538 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
df828598 1539
1923d6e4 1540 /* Enable internal fifo flow control */
5d8d0d4d 1541 writel(0x7, &cpsw->regs->flow_control);
1923d6e4 1542
dbc4ec52
IK		 1543 napi_enable(&cpsw->napi_rx);
1544 napi_enable(&cpsw->napi_tx);
d354eb85 1545
e38b5a3d
IK		 1546 if (cpsw->tx_irq_disabled) {
1547 cpsw->tx_irq_disabled = false;
1548 enable_irq(cpsw->irqs_table[1]);
7da11600
M		 1549 }
1550
e38b5a3d
IK		 1551 if (cpsw->rx_irq_disabled) {
1552 cpsw->rx_irq_disabled = false;
1553 enable_irq(cpsw->irqs_table[0]);
7da11600
M		 1554 }
1555
3802dce1
IK		 1556 ret = cpsw_fill_rx_channels(priv);
1557 if (ret < 0)
1558 goto err_cleanup;
f280e89a 1559
8a2c9a5a 1560 if (cpts_register(cpsw->cpts))
f280e89a
M		 1561 dev_err(priv->dev, "error registering cpts device\n");
1562
df828598 1563 }
df828598 1564
ff5b8ef2 1565 /* Enable Interrupt pacing if configured */
2a05a622 1566 if (cpsw->coal_intvl != 0) {
ff5b8ef2
M		 1567 struct ethtool_coalesce coal;
1568
2a05a622 1569 coal.rx_coalesce_usecs = cpsw->coal_intvl;
ff5b8ef2
M		 1570 cpsw_set_coalesce(ndev, &coal);
1571 }
1572
2c836bd9
IK		 1573 cpdma_ctlr_start(cpsw->dma);
1574 cpsw_intr_enable(cpsw);
d5bc1613 1575 cpsw->usage_count++;
f63a975e 1576
df828598 1577 return 0;
df828598 1578
aacebbf8 1579err_cleanup:
2c836bd9 1580 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1581 for_each_slave(priv, cpsw_slave_stop, cpsw);
56e31bd8 1582 pm_runtime_put_sync(cpsw->dev);
aacebbf8
SS		 1583 netif_carrier_off(priv->ndev);
1584 return ret;
df828598
M		 1585}
1586
1587static int cpsw_ndo_stop(struct net_device *ndev)
1588{
1589 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1590 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1591
1592 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
e05107e6 1593 netif_tx_stop_all_queues(priv->ndev);
df828598 1594 netif_carrier_off(priv->ndev);
d9ba8f9e 1595
d5bc1613 1596 if (cpsw->usage_count <= 1) {
dbc4ec52
IK		 1597 napi_disable(&cpsw->napi_rx);
1598 napi_disable(&cpsw->napi_tx);
2a05a622 1599 cpts_unregister(cpsw->cpts);
2c836bd9
IK		 1600 cpsw_intr_disable(cpsw);
1601 cpdma_ctlr_stop(cpsw->dma);
2a05a622 1602 cpsw_ale_stop(cpsw->ale);
d9ba8f9e 1603 }
2a05a622 1604 for_each_slave(priv, cpsw_slave_stop, cpsw);
0be01b8e
IK		 1605
1606 if (cpsw_need_resplit(cpsw))
1607 cpsw_split_res(ndev);
1608
d5bc1613 1609 cpsw->usage_count--;
56e31bd8 1610 pm_runtime_put_sync(cpsw->dev);
df828598
M		 1611 return 0;
1612}
1613
1614static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1615 struct net_device *ndev)
1616{
1617 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1618 struct cpsw_common *cpsw = priv->cpsw;
f44f8417 1619 struct cpts *cpts = cpsw->cpts;
e05107e6
IK		 1620 struct netdev_queue *txq;
1621 struct cpdma_chan *txch;
1622 int ret, q_idx;
df828598 1623
df828598
M		 1624 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1625 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1626 ndev->stats.tx_dropped++;
1bf96050 1627 return NET_XMIT_DROP;
df828598
M		 1628 }
1629
9232b16d 1630 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
f44f8417 1631 cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
2e5b38ab
RC		 1632 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1633
e05107e6
IK		 1634 q_idx = skb_get_queue_mapping(skb);
1635 if (q_idx >= cpsw->tx_ch_num)
1636 q_idx = q_idx % cpsw->tx_ch_num;
1637
8feb0a19 1638 txch = cpsw->txv[q_idx].ch;
e05107e6 1639 ret = cpsw_tx_packet_submit(priv, skb, txch);
df828598
M		 1640 if (unlikely(ret != 0)) {
1641 cpsw_err(priv, tx_err, "desc submit failed\n");
1642 goto fail;
1643 }
1644
fae50823
M		 1645 /* If there is no more tx desc left free then we need to
1646 * tell the kernel to stop sending us tx frames.
1647 */
e05107e6
IK		 1648 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1649 txq = netdev_get_tx_queue(ndev, q_idx);
1650 netif_tx_stop_queue(txq);
1651 }
fae50823 1652
df828598
M		 1653 return NETDEV_TX_OK;
1654fail:
8dc43ddc 1655 ndev->stats.tx_dropped++;
e05107e6
IK		 1656 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1657 netif_tx_stop_queue(txq);
df828598
M		 1658 return NETDEV_TX_BUSY;
1659}
1660
c8395d4e 1661#if IS_ENABLED(CONFIG_TI_CPTS)
2e5b38ab 1662
2a05a622 1663static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
2e5b38ab 1664{
606f3993 1665 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
2e5b38ab
RC		 1666 u32 ts_en, seq_id;
1667
b63ba58e
GS		 1668 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1669 !cpts_is_rx_enabled(cpsw->cpts)) {
2e5b38ab
RC		 1670 slave_write(slave, 0, CPSW1_TS_CTL);
1671 return;
1672 }
1673
1674 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1675 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1676
b63ba58e 1677 if (cpts_is_tx_enabled(cpsw->cpts))
2e5b38ab
RC		 1678 ts_en |= CPSW_V1_TS_TX_EN;
1679
b63ba58e 1680 if (cpts_is_rx_enabled(cpsw->cpts))
2e5b38ab
RC		 1681 ts_en |= CPSW_V1_TS_RX_EN;
1682
1683 slave_write(slave, ts_en, CPSW1_TS_CTL);
1684 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1685}
1686
1687static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1688{
d9ba8f9e 1689 struct cpsw_slave *slave;
5d8d0d4d 1690 struct cpsw_common *cpsw = priv->cpsw;
2e5b38ab
RC		 1691 u32 ctrl, mtype;
1692
cb7d78d0 1693 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
d9ba8f9e 1694
2e5b38ab 1695 ctrl = slave_read(slave, CPSW2_CONTROL);
2a05a622 1696 switch (cpsw->version) {
09c55372
GC		 1697 case CPSW_VERSION_2:
1698 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1699
b63ba58e 1700 if (cpts_is_tx_enabled(cpsw->cpts))
09c55372 1701 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1702
b63ba58e 1703 if (cpts_is_rx_enabled(cpsw->cpts))
09c55372 1704 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1705 break;
09c55372
GC		 1706 case CPSW_VERSION_3:
1707 default:
1708 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1709
b63ba58e 1710 if (cpts_is_tx_enabled(cpsw->cpts))
09c55372
GC		 1711 ctrl |= CTRL_V3_TX_TS_BITS;
1712
b63ba58e 1713 if (cpts_is_rx_enabled(cpsw->cpts))
09c55372 1714 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1715 break;
09c55372 1716 }
2e5b38ab
RC		 1717
1718 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1719
1720 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1721 slave_write(slave, ctrl, CPSW2_CONTROL);
dda5f5fe 1722 writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
2e5b38ab
RC		 1723}
1724
a5b4145b 1725static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1726{
3177bf6f 1727 struct cpsw_priv *priv = netdev_priv(dev);
2e5b38ab 1728 struct hwtstamp_config cfg;
2a05a622
IK		 1729 struct cpsw_common *cpsw = priv->cpsw;
1730 struct cpts *cpts = cpsw->cpts;
2e5b38ab 1731
2a05a622
IK		 1732 if (cpsw->version != CPSW_VERSION_1 &&
1733 cpsw->version != CPSW_VERSION_2 &&
1734 cpsw->version != CPSW_VERSION_3)
2ee91e54
BH		 1735 return -EOPNOTSUPP;
1736
2e5b38ab
RC		 1737 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1738 return -EFAULT;
1739
1740 /* reserved for future extensions */
1741 if (cfg.flags)
1742 return -EINVAL;
1743
2ee91e54 1744 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1745 return -ERANGE;
2e5b38ab
RC		 1746
1747 switch (cfg.rx_filter) {
1748 case HWTSTAMP_FILTER_NONE:
b63ba58e 1749 cpts_rx_enable(cpts, 0);
2e5b38ab
RC		 1750 break;
1751 case HWTSTAMP_FILTER_ALL:
e9523a5a
GS		 1752 case HWTSTAMP_FILTER_NTP_ALL:
1753 return -ERANGE;
2e5b38ab
RC		 1754 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1755 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1756 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
e9523a5a
GS		 1757 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1758 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1759 break;
2e5b38ab
RC		 1760 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1761 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1762 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1763 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1764 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1765 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1766 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1767 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1768 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e9523a5a 1769 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
2e5b38ab
RC		 1770 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1771 break;
1772 default:
1773 return -ERANGE;
1774 }
1775
b63ba58e 1776 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
2ee91e54 1777
2a05a622 1778 switch (cpsw->version) {
2e5b38ab 1779 case CPSW_VERSION_1:
2a05a622 1780 cpsw_hwtstamp_v1(cpsw);
2e5b38ab
RC		 1781 break;
1782 case CPSW_VERSION_2:
f7d403cb 1783 case CPSW_VERSION_3:
2e5b38ab
RC		 1784 cpsw_hwtstamp_v2(priv);
1785 break;
1786 default:
2ee91e54 1787 WARN_ON(1);
2e5b38ab
RC		 1788 }
1789
1790 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1791}
1792
a5b4145b
BH		 1793static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1794{
2a05a622
IK		 1795 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1796 struct cpts *cpts = cpsw->cpts;
a5b4145b
BH		 1797 struct hwtstamp_config cfg;
1798
2a05a622
IK		 1799 if (cpsw->version != CPSW_VERSION_1 &&
1800 cpsw->version != CPSW_VERSION_2 &&
1801 cpsw->version != CPSW_VERSION_3)
a5b4145b
BH		 1802 return -EOPNOTSUPP;
1803
1804 cfg.flags = 0;
b63ba58e
GS		 1805 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1806 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1807 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
e9523a5a 1808 cpts->rx_enable : HWTSTAMP_FILTER_NONE);
a5b4145b
BH		 1809
1810 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1811}
c8395d4e
GS		 1812#else
1813static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1814{
1815 return -EOPNOTSUPP;
1816}
a5b4145b 1817
c8395d4e
GS		 1818static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1819{
1820 return -EOPNOTSUPP;
1821}
2e5b38ab
RC		 1822#endif /*CONFIG_TI_CPTS*/
1823
1824static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1825{
11f2c988 1826 struct cpsw_priv *priv = netdev_priv(dev);
606f3993
IK		 1827 struct cpsw_common *cpsw = priv->cpsw;
1828 int slave_no = cpsw_slave_index(cpsw, priv);
11f2c988 1829
2e5b38ab
RC		 1830 if (!netif_running(dev))
1831 return -EINVAL;
1832
11f2c988 1833 switch (cmd) {
11f2c988 1834 case SIOCSHWTSTAMP:
a5b4145b
BH		 1835 return cpsw_hwtstamp_set(dev, req);
1836 case SIOCGHWTSTAMP:
1837 return cpsw_hwtstamp_get(dev, req);
11f2c988
M		 1838 }
1839
606f3993 1840 if (!cpsw->slaves[slave_no].phy)
c1b59947 1841 return -EOPNOTSUPP;
606f3993 1842 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1843}
1844
df828598
M		 1845static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1846{
1847 struct cpsw_priv *priv = netdev_priv(ndev);
2c836bd9 1848 struct cpsw_common *cpsw = priv->cpsw;
e05107e6 1849 int ch;
df828598
M		 1850
1851 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1852 ndev->stats.tx_errors++;
2c836bd9 1853 cpsw_intr_disable(cpsw);
e05107e6 1854 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
8feb0a19
IK		 1855 cpdma_chan_stop(cpsw->txv[ch].ch);
1856 cpdma_chan_start(cpsw->txv[ch].ch);
e05107e6
IK		 1857 }
1858
2c836bd9 1859 cpsw_intr_enable(cpsw);
75514b66
GS		 1860 netif_trans_update(ndev);
1861 netif_tx_wake_all_queues(ndev);
df828598
M		 1862}
1863
dcfd8d58
M		 1864static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1865{
1866 struct cpsw_priv *priv = netdev_priv(ndev);
1867 struct sockaddr *addr = (struct sockaddr *)p;
649a1688 1868 struct cpsw_common *cpsw = priv->cpsw;
dcfd8d58
M		 1869 int flags = 0;
1870 u16 vid = 0;
a6c5d14f 1871 int ret;
dcfd8d58
M		 1872
1873 if (!is_valid_ether_addr(addr->sa_data))
1874 return -EADDRNOTAVAIL;
1875
56e31bd8 1876 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1877 if (ret < 0) {
56e31bd8 1878 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1879 return ret;
1880 }
1881
606f3993
IK		 1882 if (cpsw->data.dual_emac) {
1883 vid = cpsw->slaves[priv->emac_port].port_vlan;
dcfd8d58
M		 1884 flags = ALE_VLAN;
1885 }
1886
2a05a622 1887 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1888 flags, vid);
2a05a622 1889 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1890 flags, vid);
1891
1892 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1893 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1894 for_each_slave(priv, cpsw_set_slave_mac, priv);
1895
56e31bd8 1896 pm_runtime_put(cpsw->dev);
a6c5d14f 1897
dcfd8d58
M		 1898 return 0;
1899}
1900
df828598
M		 1901#ifdef CONFIG_NET_POLL_CONTROLLER
1902static void cpsw_ndo_poll_controller(struct net_device *ndev)
1903{
dbc4ec52 1904 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 1905
dbc4ec52
IK		 1906 cpsw_intr_disable(cpsw);
1907 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1908 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1909 cpsw_intr_enable(cpsw);
df828598
M		 1910}
1911#endif
1912
3b72c2fe
M		 1913static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1914 unsigned short vid)
1915{
1916 int ret;
9f6bd8fa
M		 1917 int unreg_mcast_mask = 0;
1918 u32 port_mask;
606f3993 1919 struct cpsw_common *cpsw = priv->cpsw;
1e5c4bc4 1920
606f3993 1921 if (cpsw->data.dual_emac) {
9f6bd8fa 1922 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1923
9f6bd8fa
M		 1924 if (priv->ndev->flags & IFF_ALLMULTI)
1925 unreg_mcast_mask = port_mask;
1926 } else {
1927 port_mask = ALE_ALL_PORTS;
1928
1929 if (priv->ndev->flags & IFF_ALLMULTI)
1930 unreg_mcast_mask = ALE_ALL_PORTS;
1931 else
1932 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1933 }
3b72c2fe 1934
2a05a622 1935 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
61f1cef9 1936 unreg_mcast_mask);
3b72c2fe
M		 1937 if (ret != 0)
1938 return ret;
1939
2a05a622 1940 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1941 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1942 if (ret != 0)
1943 goto clean_vid;
1944
2a05a622 1945 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
9f6bd8fa 1946 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1947 if (ret != 0)
1948 goto clean_vlan_ucast;
1949 return 0;
1950
1951clean_vlan_ucast:
2a05a622 1952 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
71a2cbb7 1953 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe 1954clean_vid:
2a05a622 1955 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 1956 return ret;
1957}
1958
1959static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1960 __be16 proto, u16 vid)
3b72c2fe
M		 1961{
1962 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1963 struct cpsw_common *cpsw = priv->cpsw;
a6c5d14f 1964 int ret;
3b72c2fe 1965
606f3993 1966 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 1967 return 0;
1968
56e31bd8 1969 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 1970 if (ret < 0) {
56e31bd8 1971 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 1972 return ret;
1973 }
1974
606f3993 1975 if (cpsw->data.dual_emac) {
02a54164
M		 1976 /* In dual EMAC, reserved VLAN id should not be used for
1977 * creating VLAN interfaces as this can break the dual
1978 * EMAC port separation
1979 */
1980 int i;
1981
606f3993
IK		 1982 for (i = 0; i < cpsw->data.slaves; i++) {
1983 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 1984 return -EINVAL;
1985 }
1986 }
1987
3b72c2fe 1988 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1989 ret = cpsw_add_vlan_ale_entry(priv, vid);
1990
56e31bd8 1991 pm_runtime_put(cpsw->dev);
a6c5d14f 1992 return ret;
3b72c2fe
M		 1993}
1994
1995static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1996 __be16 proto, u16 vid)
3b72c2fe
M		 1997{
1998 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1999 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 2000 int ret;
2001
606f3993 2002 if (vid == cpsw->data.default_vlan)
3b72c2fe
M		 2003 return 0;
2004
56e31bd8 2005 ret = pm_runtime_get_sync(cpsw->dev);
a6c5d14f 2006 if (ret < 0) {
56e31bd8 2007 pm_runtime_put_noidle(cpsw->dev);
a6c5d14f
GS		 2008 return ret;
2009 }
2010
606f3993 2011 if (cpsw->data.dual_emac) {
02a54164
M		 2012 int i;
2013
606f3993
IK		 2014 for (i = 0; i < cpsw->data.slaves; i++) {
2015 if (vid == cpsw->slaves[i].port_vlan)
02a54164
M		 2016 return -EINVAL;
2017 }
2018 }
2019
3b72c2fe 2020 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2a05a622 2021 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
3b72c2fe
M		 2022 if (ret != 0)
2023 return ret;
2024
2a05a622 2025 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
61f1cef9 2026 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 2027 if (ret != 0)
2028 return ret;
2029
2a05a622 2030 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
a6c5d14f 2031 0, ALE_VLAN, vid);
56e31bd8 2032 pm_runtime_put(cpsw->dev);
a6c5d14f 2033 return ret;
3b72c2fe
M		 2034}
2035
83fcad0c
IK		 2036static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2037{
2038 struct cpsw_priv *priv = netdev_priv(ndev);
83fcad0c 2039 struct cpsw_common *cpsw = priv->cpsw;
52986a2f 2040 struct cpsw_slave *slave;
32b78d85 2041 u32 min_rate;
83fcad0c 2042 u32 ch_rate;
52986a2f 2043 int i, ret;
83fcad0c
IK		 2044
2045 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2046 if (ch_rate == rate)
2047 return 0;
2048
32b78d85
IK		 2049 ch_rate = rate * 1000;
2050 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2051 if ((ch_rate < min_rate && ch_rate)) {
2052 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2053 min_rate);
83fcad0c
IK		 2054 return -EINVAL;
2055 }
2056
0be01b8e 2057 if (rate > cpsw->speed) {
32b78d85 2058 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
83fcad0c
IK		 2059 return -EINVAL;
2060 }
2061
2062 ret = pm_runtime_get_sync(cpsw->dev);
2063 if (ret < 0) {
2064 pm_runtime_put_noidle(cpsw->dev);
2065 return ret;
2066 }
2067
32b78d85
IK		 2068 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2069 pm_runtime_put(cpsw->dev);
83fcad0c 2070
32b78d85
IK		 2071 if (ret)
2072 return ret;
83fcad0c 2073
52986a2f
IK		 2074 /* update rates for slaves tx queues */
2075 for (i = 0; i < cpsw->data.slaves; i++) {
2076 slave = &cpsw->slaves[i];
2077 if (!slave->ndev)
2078 continue;
2079
2080 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2081 }
2082
32b78d85 2083 cpsw_split_res(ndev);
83fcad0c
IK		 2084 return ret;
2085}
2086
df828598
M		 2087static const struct net_device_ops cpsw_netdev_ops = {
2088 .ndo_open = cpsw_ndo_open,
2089 .ndo_stop = cpsw_ndo_stop,
2090 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 2091 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 2092 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598
M		 2093 .ndo_validate_addr = eth_validate_addr,
2094 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 2095 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
83fcad0c 2096 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
df828598
M		 2097#ifdef CONFIG_NET_POLL_CONTROLLER
2098 .ndo_poll_controller = cpsw_ndo_poll_controller,
2099#endif
3b72c2fe
M		 2100 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 2102};
2103
52c4f0ec
M		 2104static int cpsw_get_regs_len(struct net_device *ndev)
2105{
606f3993 2106 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec 2107
606f3993 2108 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
52c4f0ec
M		 2109}
2110
2111static void cpsw_get_regs(struct net_device *ndev,
2112 struct ethtool_regs *regs, void *p)
2113{
52c4f0ec 2114 u32 *reg = p;
2a05a622 2115 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
52c4f0ec
M		 2116
2117 /* update CPSW IP version */
2a05a622 2118 regs->version = cpsw->version;
52c4f0ec 2119
2a05a622 2120 cpsw_ale_dump(cpsw->ale, reg);
52c4f0ec
M		 2121}
2122
df828598
M		 2123static void cpsw_get_drvinfo(struct net_device *ndev,
2124 struct ethtool_drvinfo *info)
2125{
649a1688 2126 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
56e31bd8 2127 struct platform_device *pdev = to_platform_device(cpsw->dev);
7826d43f 2128
52c4f0ec 2129 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f 2130 strlcpy(info->version, "1.0", sizeof(info->version));
56e31bd8 2131 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
df828598
M		 2132}
2133
2134static u32 cpsw_get_msglevel(struct net_device *ndev)
2135{
2136 struct cpsw_priv *priv = netdev_priv(ndev);
2137 return priv->msg_enable;
2138}
2139
2140static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2141{
2142 struct cpsw_priv *priv = netdev_priv(ndev);
2143 priv->msg_enable = value;
2144}
2145
c8395d4e 2146#if IS_ENABLED(CONFIG_TI_CPTS)
2e5b38ab
RC		 2147static int cpsw_get_ts_info(struct net_device *ndev,
2148 struct ethtool_ts_info *info)
2149{
2a05a622 2150 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2e5b38ab
RC		 2151
2152 info->so_timestamping =
2153 SOF_TIMESTAMPING_TX_HARDWARE |
2154 SOF_TIMESTAMPING_TX_SOFTWARE |
2155 SOF_TIMESTAMPING_RX_HARDWARE |
2156 SOF_TIMESTAMPING_RX_SOFTWARE |
2157 SOF_TIMESTAMPING_SOFTWARE |
2158 SOF_TIMESTAMPING_RAW_HARDWARE;
2a05a622 2159 info->phc_index = cpsw->cpts->phc_index;
2e5b38ab
RC		 2160 info->tx_types =
2161 (1 << HWTSTAMP_TX_OFF) |
2162 (1 << HWTSTAMP_TX_ON);
2163 info->rx_filters =
2164 (1 << HWTSTAMP_FILTER_NONE) |
e9523a5a 2165 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2e5b38ab 2166 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
c8395d4e
GS		 2167 return 0;
2168}
2e5b38ab 2169#else
c8395d4e
GS		 2170static int cpsw_get_ts_info(struct net_device *ndev,
2171 struct ethtool_ts_info *info)
2172{
2e5b38ab
RC		 2173 info->so_timestamping =
2174 SOF_TIMESTAMPING_TX_SOFTWARE |
2175 SOF_TIMESTAMPING_RX_SOFTWARE |
2176 SOF_TIMESTAMPING_SOFTWARE;
2177 info->phc_index = -1;
2178 info->tx_types = 0;
2179 info->rx_filters = 0;
2e5b38ab
RC		 2180 return 0;
2181}
c8395d4e 2182#endif
2e5b38ab 2183
2479876d
PR		 2184static int cpsw_get_link_ksettings(struct net_device *ndev,
2185 struct ethtool_link_ksettings *ecmd)
d3bb9c58
M		 2186{
2187 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2188 struct cpsw_common *cpsw = priv->cpsw;
2189 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 2190
5514174f 2191 if (!cpsw->slaves[slave_no].phy)
d3bb9c58 2192 return -EOPNOTSUPP;
5514174f 2193
2194 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2195 return 0;
d3bb9c58
M		 2196}
2197
2479876d
PR		 2198static int cpsw_set_link_ksettings(struct net_device *ndev,
2199 const struct ethtool_link_ksettings *ecmd)
d3bb9c58
M		 2200{
2201 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2202 struct cpsw_common *cpsw = priv->cpsw;
2203 int slave_no = cpsw_slave_index(cpsw, priv);
d3bb9c58 2204
606f3993 2205 if (cpsw->slaves[slave_no].phy)
2479876d
PR		 2206 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2207 ecmd);
d3bb9c58
M		 2208 else
2209 return -EOPNOTSUPP;
2210}
2211
d8a64420
MU		 2212static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2213{
2214 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2215 struct cpsw_common *cpsw = priv->cpsw;
2216 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420
MU		 2217
2218 wol->supported = 0;
2219 wol->wolopts = 0;
2220
606f3993
IK		 2221 if (cpsw->slaves[slave_no].phy)
2222 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2223}
2224
2225static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2226{
2227 struct cpsw_priv *priv = netdev_priv(ndev);
606f3993
IK		 2228 struct cpsw_common *cpsw = priv->cpsw;
2229 int slave_no = cpsw_slave_index(cpsw, priv);
d8a64420 2230
606f3993
IK		 2231 if (cpsw->slaves[slave_no].phy)
2232 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
d8a64420
MU		 2233 else
2234 return -EOPNOTSUPP;
2235}
2236
1923d6e4
M		 2237static void cpsw_get_pauseparam(struct net_device *ndev,
2238 struct ethtool_pauseparam *pause)
2239{
2240 struct cpsw_priv *priv = netdev_priv(ndev);
2241
2242 pause->autoneg = AUTONEG_DISABLE;
2243 pause->rx_pause = priv->rx_pause ? true : false;
2244 pause->tx_pause = priv->tx_pause ? true : false;
2245}
2246
2247static int cpsw_set_pauseparam(struct net_device *ndev,
2248 struct ethtool_pauseparam *pause)
2249{
2250 struct cpsw_priv *priv = netdev_priv(ndev);
2251 bool link;
2252
2253 priv->rx_pause = pause->rx_pause ? true : false;
2254 priv->tx_pause = pause->tx_pause ? true : false;
2255
2256 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 2257 return 0;
2258}
2259
7898b1da
GS		 2260static int cpsw_ethtool_op_begin(struct net_device *ndev)
2261{
2262 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 2263 struct cpsw_common *cpsw = priv->cpsw;
7898b1da
GS		 2264 int ret;
2265
56e31bd8 2266 ret = pm_runtime_get_sync(cpsw->dev);
7898b1da
GS		 2267 if (ret < 0) {
2268 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
56e31bd8 2269 pm_runtime_put_noidle(cpsw->dev);
7898b1da
GS		 2270 }
2271
2272 return ret;
2273}
2274
2275static void cpsw_ethtool_op_complete(struct net_device *ndev)
2276{
2277 struct cpsw_priv *priv = netdev_priv(ndev);
2278 int ret;
2279
56e31bd8 2280 ret = pm_runtime_put(priv->cpsw->dev);
7898b1da
GS		 2281 if (ret < 0)
2282 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2283}
2284
ce52c744
IK		 2285static void cpsw_get_channels(struct net_device *ndev,
2286 struct ethtool_channels *ch)
2287{
2288 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2289
2290 ch->max_combined = 0;
2291 ch->max_rx = CPSW_MAX_QUEUES;
2292 ch->max_tx = CPSW_MAX_QUEUES;
2293 ch->max_other = 0;
2294 ch->other_count = 0;
2295 ch->rx_count = cpsw->rx_ch_num;
2296 ch->tx_count = cpsw->tx_ch_num;
2297 ch->combined_count = 0;
2298}
2299
2300static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2301 struct ethtool_channels *ch)
2302{
2303 if (ch->combined_count)
2304 return -EINVAL;
2305
2306 /* verify we have at least one channel in each direction */
2307 if (!ch->rx_count || !ch->tx_count)
2308 return -EINVAL;
2309
2310 if (ch->rx_count > cpsw->data.channels ||
2311 ch->tx_count > cpsw->data.channels)
2312 return -EINVAL;
2313
2314 return 0;
2315}
2316
2317static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2318{
ce52c744
IK		 2319 struct cpsw_common *cpsw = priv->cpsw;
2320 void (*handler)(void *, int, int);
83fcad0c 2321 struct netdev_queue *queue;
8feb0a19 2322 struct cpsw_vector *vec;
ce52c744
IK		 2323 int ret, *ch;
2324
2325 if (rx) {
2326 ch = &cpsw->rx_ch_num;
8feb0a19 2327 vec = cpsw->rxv;
ce52c744 2328 handler = cpsw_rx_handler;
ce52c744
IK		 2329 } else {
2330 ch = &cpsw->tx_ch_num;
8feb0a19 2331 vec = cpsw->txv;
ce52c744 2332 handler = cpsw_tx_handler;
ce52c744
IK		 2333 }
2334
2335 while (*ch < ch_num) {
8feb0a19 2336 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
83fcad0c
IK		 2337 queue = netdev_get_tx_queue(priv->ndev, *ch);
2338 queue->tx_maxrate = 0;
ce52c744 2339
8feb0a19
IK		 2340 if (IS_ERR(vec[*ch].ch))
2341 return PTR_ERR(vec[*ch].ch);
ce52c744 2342
8feb0a19 2343 if (!vec[*ch].ch)
ce52c744
IK		 2344 return -EINVAL;
2345
2346 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2347 (rx ? "rx" : "tx"));
2348 (*ch)++;
2349 }
2350
2351 while (*ch > ch_num) {
2352 (*ch)--;
2353
8feb0a19 2354 ret = cpdma_chan_destroy(vec[*ch].ch);
ce52c744
IK		 2355 if (ret)
2356 return ret;
2357
2358 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2359 (rx ? "rx" : "tx"));
2360 }
2361
2362 return 0;
2363}
2364
2365static int cpsw_update_channels(struct cpsw_priv *priv,
2366 struct ethtool_channels *ch)
2367{
2368 int ret;
2369
2370 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2371 if (ret)
2372 return ret;
2373
2374 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2375 if (ret)
2376 return ret;
2377
2378 return 0;
2379}
2380
022d7ad7 2381static void cpsw_suspend_data_pass(struct net_device *ndev)
ce52c744 2382{
022d7ad7 2383 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
ce52c744 2384 struct cpsw_slave *slave;
022d7ad7 2385 int i;
ce52c744
IK		 2386
2387 /* Disable NAPI scheduling */
2388 cpsw_intr_disable(cpsw);
2389
2390 /* Stop all transmit queues for every network device.
2391 * Disable re-using rx descriptors with dormant_on.
2392 */
2393 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2394 if (!(slave->ndev && netif_running(slave->ndev)))
2395 continue;
2396
2397 netif_tx_stop_all_queues(slave->ndev);
2398 netif_dormant_on(slave->ndev);
2399 }
2400
2401 /* Handle rest of tx packets and stop cpdma channels */
2402 cpdma_ctlr_stop(cpsw->dma);
022d7ad7
IK		 2403}
2404
2405static int cpsw_resume_data_pass(struct net_device *ndev)
2406{
2407 struct cpsw_priv *priv = netdev_priv(ndev);
2408 struct cpsw_common *cpsw = priv->cpsw;
2409 struct cpsw_slave *slave;
2410 int i, ret;
2411
2412 /* Allow rx packets handling */
2413 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2414 if (slave->ndev && netif_running(slave->ndev))
2415 netif_dormant_off(slave->ndev);
2416
2417 /* After this receive is started */
d5bc1613 2418 if (cpsw->usage_count) {
022d7ad7
IK		 2419 ret = cpsw_fill_rx_channels(priv);
2420 if (ret)
2421 return ret;
2422
2423 cpdma_ctlr_start(cpsw->dma);
2424 cpsw_intr_enable(cpsw);
2425 }
2426
2427 /* Resume transmit for every affected interface */
2428 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2429 if (slave->ndev && netif_running(slave->ndev))
2430 netif_tx_start_all_queues(slave->ndev);
2431
2432 return 0;
2433}
2434
2435static int cpsw_set_channels(struct net_device *ndev,
2436 struct ethtool_channels *chs)
2437{
2438 struct cpsw_priv *priv = netdev_priv(ndev);
2439 struct cpsw_common *cpsw = priv->cpsw;
2440 struct cpsw_slave *slave;
2441 int i, ret;
2442
2443 ret = cpsw_check_ch_settings(cpsw, chs);
2444 if (ret < 0)
2445 return ret;
2446
2447 cpsw_suspend_data_pass(ndev);
ce52c744
IK		 2448 ret = cpsw_update_channels(priv, chs);
2449 if (ret)
2450 goto err;
2451
2452 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2453 if (!(slave->ndev && netif_running(slave->ndev)))
2454 continue;
2455
2456 /* Inform stack about new count of queues */
2457 ret = netif_set_real_num_tx_queues(slave->ndev,
2458 cpsw->tx_ch_num);
2459 if (ret) {
2460 dev_err(priv->dev, "cannot set real number of tx queues\n");
2461 goto err;
2462 }
2463
2464 ret = netif_set_real_num_rx_queues(slave->ndev,
2465 cpsw->rx_ch_num);
2466 if (ret) {
2467 dev_err(priv->dev, "cannot set real number of rx queues\n");
2468 goto err;
2469 }
ce52c744
IK		 2470 }
2471
d5bc1613 2472 if (cpsw->usage_count)
32b78d85 2473 cpsw_split_res(ndev);
8feb0a19 2474
022d7ad7
IK		 2475 ret = cpsw_resume_data_pass(ndev);
2476 if (!ret)
2477 return 0;
ce52c744
IK		 2478err:
2479 dev_err(priv->dev, "cannot update channels number, closing device\n");
2480 dev_close(ndev);
2481 return ret;
2482}
2483
a0909949
YY		 2484static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2485{
2486 struct cpsw_priv *priv = netdev_priv(ndev);
2487 struct cpsw_common *cpsw = priv->cpsw;
2488 int slave_no = cpsw_slave_index(cpsw, priv);
2489
2490 if (cpsw->slaves[slave_no].phy)
2491 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2492 else
2493 return -EOPNOTSUPP;
2494}
2495
2496static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2497{
2498 struct cpsw_priv *priv = netdev_priv(ndev);
2499 struct cpsw_common *cpsw = priv->cpsw;
2500 int slave_no = cpsw_slave_index(cpsw, priv);
2501
2502 if (cpsw->slaves[slave_no].phy)
2503 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2504 else
2505 return -EOPNOTSUPP;
2506}
2507
6bb10c2b
YY		 2508static int cpsw_nway_reset(struct net_device *ndev)
2509{
2510 struct cpsw_priv *priv = netdev_priv(ndev);
2511 struct cpsw_common *cpsw = priv->cpsw;
2512 int slave_no = cpsw_slave_index(cpsw, priv);
2513
2514 if (cpsw->slaves[slave_no].phy)
2515 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2516 else
2517 return -EOPNOTSUPP;
2518}
2519
be034fc1
GS		 2520static void cpsw_get_ringparam(struct net_device *ndev,
2521 struct ethtool_ringparam *ering)
2522{
2523 struct cpsw_priv *priv = netdev_priv(ndev);
2524 struct cpsw_common *cpsw = priv->cpsw;
2525
2526 /* not supported */
2527 ering->tx_max_pending = 0;
2528 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
f89d21b9 2529 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
be034fc1
GS		 2530 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2531}
2532
2533static int cpsw_set_ringparam(struct net_device *ndev,
2534 struct ethtool_ringparam *ering)
2535{
2536 struct cpsw_priv *priv = netdev_priv(ndev);
2537 struct cpsw_common *cpsw = priv->cpsw;
022d7ad7 2538 int ret;
be034fc1
GS		 2539
2540 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2541
2542 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
f89d21b9
IK		 2543 ering->rx_pending < CPSW_MAX_QUEUES ||
2544 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
be034fc1
GS		 2545 return -EINVAL;
2546
2547 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2548 return 0;
2549
022d7ad7 2550 cpsw_suspend_data_pass(ndev);
be034fc1
GS		 2551
2552 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2553
d5bc1613 2554 if (cpsw->usage_count)
be034fc1
GS		 2555 cpdma_chan_split_pool(cpsw->dma);
2556
022d7ad7
IK		 2557 ret = cpsw_resume_data_pass(ndev);
2558 if (!ret)
2559 return 0;
be034fc1 2560
022d7ad7 2561 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
be034fc1
GS		 2562 dev_close(ndev);
2563 return ret;
2564}
2565
df828598
M		 2566static const struct ethtool_ops cpsw_ethtool_ops = {
2567 .get_drvinfo = cpsw_get_drvinfo,
2568 .get_msglevel = cpsw_get_msglevel,
2569 .set_msglevel = cpsw_set_msglevel,
2570 .get_link = ethtool_op_get_link,
2e5b38ab 2571 .get_ts_info = cpsw_get_ts_info,
ff5b8ef2
M		 2572 .get_coalesce = cpsw_get_coalesce,
2573 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 2574 .get_sset_count = cpsw_get_sset_count,
2575 .get_strings = cpsw_get_strings,
2576 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 2577 .get_pauseparam = cpsw_get_pauseparam,
2578 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 2579 .get_wol = cpsw_get_wol,
2580 .set_wol = cpsw_set_wol,
52c4f0ec
M		 2581 .get_regs_len = cpsw_get_regs_len,
2582 .get_regs = cpsw_get_regs,
7898b1da
GS		 2583 .begin = cpsw_ethtool_op_begin,
2584 .complete = cpsw_ethtool_op_complete,
ce52c744
IK		 2585 .get_channels = cpsw_get_channels,
2586 .set_channels = cpsw_set_channels,
2479876d
PR		 2587 .get_link_ksettings = cpsw_get_link_ksettings,
2588 .set_link_ksettings = cpsw_set_link_ksettings,
a0909949
YY		 2589 .get_eee = cpsw_get_eee,
2590 .set_eee = cpsw_set_eee,
6bb10c2b 2591 .nway_reset = cpsw_nway_reset,
be034fc1
GS		 2592 .get_ringparam = cpsw_get_ringparam,
2593 .set_ringparam = cpsw_set_ringparam,
df828598
M		 2594};
2595
606f3993 2596static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
549985ee 2597 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598 2598{
5d8d0d4d 2599 void __iomem *regs = cpsw->regs;
df828598 2600 int slave_num = slave->slave_num;
606f3993 2601 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
df828598
M		 2602
2603 slave->data = data;
549985ee
RC		 2604 slave->regs = regs + slave_reg_ofs;
2605 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 2606 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 2607}
2608
552165bc 2609static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 2610 struct platform_device *pdev)
2611{
2612 struct device_node *node = pdev->dev.of_node;
2613 struct device_node *slave_node;
2614 int i = 0, ret;
2615 u32 prop;
2616
2617 if (!node)
2618 return -EINVAL;
2619
2620 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 2621 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 2622 return -EINVAL;
2623 }
2624 data->slaves = prop;
2625
e86ac13b 2626 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 2627 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 2628 return -EINVAL;
78ca0b28 2629 }
e86ac13b 2630 data->active_slave = prop;
78ca0b28 2631
aa1a15e2
DM		 2632 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2633 * sizeof(struct cpsw_slave_data),
2634 GFP_KERNEL);
b2adaca9 2635 if (!data->slave_data)
aa1a15e2 2636 return -ENOMEM;
2eb32b0a 2637
2eb32b0a 2638 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2639 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2640 return -EINVAL;
2eb32b0a
M		 2641 }
2642 data->channels = prop;
2643
2eb32b0a 2644 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2645 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2646 return -EINVAL;
2eb32b0a
M		 2647 }
2648 data->ale_entries = prop;
2649
2eb32b0a 2650 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2651 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2652 return -EINVAL;
2eb32b0a
M		 2653 }
2654 data->bd_ram_size = prop;
2655
2eb32b0a 2656 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2657 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2658 return -EINVAL;
2eb32b0a
M		 2659 }
2660 data->mac_control = prop;
2661
281abd96
MP		 2662 if (of_property_read_bool(node, "dual_emac"))
2663 data->dual_emac = 1;
d9ba8f9e 2664
549985ee
RC		 2665 /*
2666 * Populate all the child nodes here...
2667 */
2668 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2669 /* We do not want to force this, as in some cases may not have child */
2670 if (ret)
88c99ff6 2671 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2672
8658aaf2 2673 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2674 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2675 const void *mac_addr = NULL;
549985ee
RC		 2676 int lenp;
2677 const __be32 *parp;
549985ee 2678
f468b10e
MP		 2679 /* This is no slave child node, continue */
2680 if (strcmp(slave_node->name, "slave"))
2681 continue;
2682
552165bc
DR		 2683 slave_data->phy_node = of_parse_phandle(slave_node,
2684 "phy-handle", 0);
f1eea5c1 2685 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2686 if (slave_data->phy_node) {
2687 dev_dbg(&pdev->dev,
f7ce9103
RH		 2688 "slave[%d] using phy-handle=\"%pOF\"\n",
2689 i, slave_data->phy_node);
ae092b5b 2690 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2691 /* In the case of a fixed PHY, the DT node associated
2692 * to the PHY is the Ethernet MAC DT node.
2693 */
1f71e8c9 2694 ret = of_phy_register_fixed_link(slave_node);
23a09873
JH		 2695 if (ret) {
2696 if (ret != -EPROBE_DEFER)
2697 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
1f71e8c9 2698 return ret;
23a09873 2699 }
06cd6d6e 2700 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2701 } else if (parp) {
2702 u32 phyid;
2703 struct device_node *mdio_node;
2704 struct platform_device *mdio;
2705
2706 if (lenp != (sizeof(__be32) * 2)) {
2707 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2708 goto no_phy_slave;
2709 }
2710 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2711 phyid = be32_to_cpup(parp+1);
2712 mdio = of_find_device_by_node(mdio_node);
2713 of_node_put(mdio_node);
2714 if (!mdio) {
2715 dev_err(&pdev->dev, "Missing mdio platform device\n");
2716 return -EINVAL;
2717 }
2718 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2719 PHY_ID_FMT, mdio->name, phyid);
86e1d5ad 2720 put_device(&mdio->dev);
f1eea5c1 2721 } else {
ae092b5b
DR		 2722 dev_err(&pdev->dev,
2723 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2724 i);
47276fcc 2725 goto no_phy_slave;
2eb32b0a 2726 }
47276fcc
M		 2727 slave_data->phy_if = of_get_phy_mode(slave_node);
2728 if (slave_data->phy_if < 0) {
2729 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2730 i);
2731 return slave_data->phy_if;
2732 }
2733
2734no_phy_slave:
2eb32b0a 2735 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2736 if (mac_addr) {
2eb32b0a 2737 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2738 } else {
b6745f6e
M		 2739 ret = ti_cm_get_macid(&pdev->dev, i,
2740 slave_data->mac_addr);
2741 if (ret)
2742 return ret;
0ba517b1 2743 }
d9ba8f9e 2744 if (data->dual_emac) {
91c4166c 2745 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2746 &prop)) {
88c99ff6 2747 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2748 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2749 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2750 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2751 } else {
2752 slave_data->dual_emac_res_vlan = prop;
2753 }
2754 }
2755
2eb32b0a 2756 i++;
3a27bfac
M		 2757 if (i == data->slaves)
2758 break;
2eb32b0a
M		 2759 }
2760
2761 return 0;
2eb32b0a
M		 2762}
2763
a4e32b0d
JH		 2764static void cpsw_remove_dt(struct platform_device *pdev)
2765{
8cbcc466
JH		 2766 struct net_device *ndev = platform_get_drvdata(pdev);
2767 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2768 struct cpsw_platform_data *data = &cpsw->data;
2769 struct device_node *node = pdev->dev.of_node;
2770 struct device_node *slave_node;
2771 int i = 0;
2772
2773 for_each_available_child_of_node(node, slave_node) {
2774 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2775
2776 if (strcmp(slave_node->name, "slave"))
2777 continue;
2778
3f65047c
JH		 2779 if (of_phy_is_fixed_link(slave_node))
2780 of_phy_deregister_fixed_link(slave_node);
8cbcc466
JH		 2781
2782 of_node_put(slave_data->phy_node);
2783
2784 i++;
2785 if (i == data->slaves)
2786 break;
2787 }
2788
a4e32b0d
JH		 2789 of_platform_depopulate(&pdev->dev);
2790}
2791
56e31bd8 2792static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
d9ba8f9e 2793{
606f3993
IK		 2794 struct cpsw_common *cpsw = priv->cpsw;
2795 struct cpsw_platform_data *data = &cpsw->data;
d9ba8f9e
M		 2796 struct net_device *ndev;
2797 struct cpsw_priv *priv_sl2;
e38b5a3d 2798 int ret = 0;
d9ba8f9e 2799
e05107e6 2800 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
d9ba8f9e 2801 if (!ndev) {
56e31bd8 2802 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2803 return -ENOMEM;
2804 }
2805
2806 priv_sl2 = netdev_priv(ndev);
606f3993 2807 priv_sl2->cpsw = cpsw;
d9ba8f9e
M		 2808 priv_sl2->ndev = ndev;
2809 priv_sl2->dev = &ndev->dev;
2810 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
d9ba8f9e
M		 2811
2812 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2813 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2814 ETH_ALEN);
56e31bd8
IK		 2815 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2816 priv_sl2->mac_addr);
d9ba8f9e
M		 2817 } else {
2818 random_ether_addr(priv_sl2->mac_addr);
56e31bd8
IK		 2819 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2820 priv_sl2->mac_addr);
d9ba8f9e
M		 2821 }
2822 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2823
d9ba8f9e 2824 priv_sl2->emac_port = 1;
606f3993 2825 cpsw->slaves[1].ndev = ndev;
f646968f 2826 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2827
2828 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2829 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2830
2831 /* register the network device */
56e31bd8 2832 SET_NETDEV_DEV(ndev, cpsw->dev);
d9ba8f9e
M		 2833 ret = register_netdev(ndev);
2834 if (ret) {
56e31bd8 2835 dev_err(cpsw->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2836 free_netdev(ndev);
2837 ret = -ENODEV;
2838 }
2839
2840 return ret;
2841}
2842
7da11600
M		 2843#define CPSW_QUIRK_IRQ BIT(0)
2844
f5b58948 2845static const struct platform_device_id cpsw_devtype[] = {
7da11600
M		 2846 {
2847 /* keep it for existing comaptibles */
2848 .name = "cpsw",
2849 .driver_data = CPSW_QUIRK_IRQ,
2850 }, {
2851 .name = "am335x-cpsw",
2852 .driver_data = CPSW_QUIRK_IRQ,
2853 }, {
2854 .name = "am4372-cpsw",
2855 .driver_data = 0,
2856 }, {
2857 .name = "dra7-cpsw",
2858 .driver_data = 0,
2859 }, {
2860 /* sentinel */
2861 }
2862};
2863MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2864
2865enum ti_cpsw_type {
2866 CPSW = 0,
2867 AM335X_CPSW,
2868 AM4372_CPSW,
2869 DRA7_CPSW,
2870};
2871
2872static const struct of_device_id cpsw_of_mtable[] = {
2873 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2874 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2875 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2876 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2877 { /* sentinel */ },
2878};
2879MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2880
663e12e6 2881static int cpsw_probe(struct platform_device *pdev)
df828598 2882{
ef4183a1 2883 struct clk *clk;
d1bd9acf 2884 struct cpsw_platform_data *data;
df828598
M		 2885 struct net_device *ndev;
2886 struct cpsw_priv *priv;
2887 struct cpdma_params dma_params;
2888 struct cpsw_ale_params ale_params;
aa1a15e2 2889 void __iomem *ss_regs;
8a2c9a5a 2890 void __iomem *cpts_regs;
aa1a15e2 2891 struct resource *res, *ss_res;
7da11600 2892 const struct of_device_id *of_id;
1d147ccb 2893 struct gpio_descs *mode;
549985ee 2894 u32 slave_offset, sliver_offset, slave_size;
649a1688 2895 struct cpsw_common *cpsw;
5087b915
FB		 2896 int ret = 0, i;
2897 int irq;
df828598 2898
649a1688 2899 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
3420ea88
JH		 2900 if (!cpsw)
2901 return -ENOMEM;
2902
56e31bd8 2903 cpsw->dev = &pdev->dev;
649a1688 2904
e05107e6 2905 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
df828598 2906 if (!ndev) {
88c99ff6 2907 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2908 return -ENOMEM;
2909 }
2910
2911 platform_set_drvdata(pdev, ndev);
2912 priv = netdev_priv(ndev);
649a1688 2913 priv->cpsw = cpsw;
df828598
M		 2914 priv->ndev = ndev;
2915 priv->dev = &ndev->dev;
2916 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2a05a622 2917 cpsw->rx_packet_max = max(rx_packet_max, 128);
df828598 2918
1d147ccb
M		 2919 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2920 if (IS_ERR(mode)) {
2921 ret = PTR_ERR(mode);
2922 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2923 goto clean_ndev_ret;
2924 }
2925
1fb19aa7
VH		 2926 /*
2927 * This may be required here for child devices.
2928 */
2929 pm_runtime_enable(&pdev->dev);
2930
739683b4
M		 2931 /* Select default pin state */
2932 pinctrl_pm_select_default_state(&pdev->dev);
2933
a4e32b0d
JH		 2934 /* Need to enable clocks with runtime PM api to access module
2935 * registers
2936 */
2937 ret = pm_runtime_get_sync(&pdev->dev);
2938 if (ret < 0) {
2939 pm_runtime_put_noidle(&pdev->dev);
aa1a15e2 2940 goto clean_runtime_disable_ret;
2eb32b0a 2941 }
a4e32b0d 2942
23a09873
JH		 2943 ret = cpsw_probe_dt(&cpsw->data, pdev);
2944 if (ret)
a4e32b0d 2945 goto clean_dt_ret;
23a09873 2946
606f3993 2947 data = &cpsw->data;
e05107e6
IK		 2948 cpsw->rx_ch_num = 1;
2949 cpsw->tx_ch_num = 1;
2eb32b0a 2950
df828598
M		 2951 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2952 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2953 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2954 } else {
7efd26d0 2955 eth_random_addr(priv->mac_addr);
88c99ff6 2956 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2957 }
2958
2959 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2960
606f3993 2961 cpsw->slaves = devm_kzalloc(&pdev->dev,
aa1a15e2
DM		 2962 sizeof(struct cpsw_slave) * data->slaves,
2963 GFP_KERNEL);
606f3993 2964 if (!cpsw->slaves) {
aa1a15e2 2965 ret = -ENOMEM;
a4e32b0d 2966 goto clean_dt_ret;
df828598
M		 2967 }
2968 for (i = 0; i < data->slaves; i++)
606f3993 2969 cpsw->slaves[i].slave_num = i;
df828598 2970
606f3993 2971 cpsw->slaves[0].ndev = ndev;
d9ba8f9e
M		 2972 priv->emac_port = 0;
2973
ef4183a1
IK		 2974 clk = devm_clk_get(&pdev->dev, "fck");
2975 if (IS_ERR(clk)) {
aa1a15e2 2976 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2977 ret = -ENODEV;
a4e32b0d 2978 goto clean_dt_ret;
df828598 2979 }
2a05a622 2980 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2981
aa1a15e2
DM		 2982 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2983 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2984 if (IS_ERR(ss_regs)) {
2985 ret = PTR_ERR(ss_regs);
a4e32b0d 2986 goto clean_dt_ret;
df828598 2987 }
5d8d0d4d 2988 cpsw->regs = ss_regs;
df828598 2989
2a05a622 2990 cpsw->version = readl(&cpsw->regs->id_ver);
f280e89a 2991
aa1a15e2 2992 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5d8d0d4d
IK		 2993 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2994 if (IS_ERR(cpsw->wr_regs)) {
2995 ret = PTR_ERR(cpsw->wr_regs);
a4e32b0d 2996 goto clean_dt_ret;
df828598 2997 }
df828598
M		 2998
2999 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 3000 memset(&ale_params, 0, sizeof(ale_params));
3001
2a05a622 3002 switch (cpsw->version) {
549985ee 3003 case CPSW_VERSION_1:
5d8d0d4d 3004 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
8a2c9a5a 3005 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
5d8d0d4d 3006 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 3007 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3008 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3009 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3010 slave_offset = CPSW1_SLAVE_OFFSET;
3011 slave_size = CPSW1_SLAVE_SIZE;
3012 sliver_offset = CPSW1_SLIVER_OFFSET;
3013 dma_params.desc_mem_phys = 0;
3014 break;
3015 case CPSW_VERSION_2:
c193f365 3016 case CPSW_VERSION_3:
926489be 3017 case CPSW_VERSION_4:
5d8d0d4d 3018 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
8a2c9a5a 3019 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
5d8d0d4d 3020 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 3021 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3022 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3023 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3024 slave_offset = CPSW2_SLAVE_OFFSET;
3025 slave_size = CPSW2_SLAVE_SIZE;
3026 sliver_offset = CPSW2_SLIVER_OFFSET;
3027 dma_params.desc_mem_phys =
aa1a15e2 3028 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 3029 break;
3030 default:
2a05a622 3031 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
549985ee 3032 ret = -ENODEV;
a4e32b0d 3033 goto clean_dt_ret;
549985ee 3034 }
606f3993
IK		 3035 for (i = 0; i < cpsw->data.slaves; i++) {
3036 struct cpsw_slave *slave = &cpsw->slaves[i];
3037
3038 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
549985ee
RC		 3039 slave_offset += slave_size;
3040 sliver_offset += SLIVER_SIZE;
3041 }
3042
df828598 3043 dma_params.dev = &pdev->dev;
549985ee
RC		 3044 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3045 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3046 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3047 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3048 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 3049
3050 dma_params.num_chan = data->channels;
3051 dma_params.has_soft_reset = true;
3052 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3053 dma_params.desc_mem_size = data->bd_ram_size;
3054 dma_params.desc_align = 16;
3055 dma_params.has_ext_regs = true;
549985ee 3056 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
83fcad0c 3057 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
90225bf0 3058 dma_params.descs_pool_size = descs_pool_size;
df828598 3059
2c836bd9
IK		 3060 cpsw->dma = cpdma_ctlr_create(&dma_params);
3061 if (!cpsw->dma) {
df828598
M		 3062 dev_err(priv->dev, "error initializing dma\n");
3063 ret = -ENOMEM;
a4e32b0d 3064 goto clean_dt_ret;
df828598
M		 3065 }
3066
8feb0a19 3067 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
8a83c5d7
IK		 3068 if (IS_ERR(cpsw->txv[0].ch)) {
3069 dev_err(priv->dev, "error initializing tx dma channel\n");
3070 ret = PTR_ERR(cpsw->txv[0].ch);
3071 goto clean_dma_ret;
3072 }
3073
8feb0a19 3074 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
8a83c5d7
IK		 3075 if (IS_ERR(cpsw->rxv[0].ch)) {
3076 dev_err(priv->dev, "error initializing rx dma channel\n");
3077 ret = PTR_ERR(cpsw->rxv[0].ch);
df828598
M		 3078 goto clean_dma_ret;
3079 }
3080
9fe9aa0b 3081 ale_params.dev = &pdev->dev;
df828598
M		 3082 ale_params.ale_ageout = ale_ageout;
3083 ale_params.ale_entries = data->ale_entries;
c6395f12 3084 ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
df828598 3085
2a05a622
IK		 3086 cpsw->ale = cpsw_ale_create(&ale_params);
3087 if (!cpsw->ale) {
df828598
M		 3088 dev_err(priv->dev, "error initializing ale engine\n");
3089 ret = -ENODEV;
3090 goto clean_dma_ret;
3091 }
3092
4a88fb95 3093 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
8a2c9a5a
GS		 3094 if (IS_ERR(cpsw->cpts)) {
3095 ret = PTR_ERR(cpsw->cpts);
1971ab58 3096 goto clean_dma_ret;
8a2c9a5a
GS		 3097 }
3098
c03abd84 3099 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 3100 if (ndev->irq < 0) {
3101 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 3102 ret = ndev->irq;
1971ab58 3103 goto clean_dma_ret;
df828598
M		 3104 }
3105
7da11600
M		 3106 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3107 if (of_id) {
3108 pdev->id_entry = of_id->data;
3109 if (pdev->id_entry->driver_data)
e38b5a3d 3110 cpsw->quirk_irq = true;
7da11600
M		 3111 }
3112
070f9c65
K		 3113 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3114
3115 ndev->netdev_ops = &cpsw_netdev_ops;
3116 ndev->ethtool_ops = &cpsw_ethtool_ops;
3117 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3118 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3119 cpsw_split_res(ndev);
3120
3121 /* register the network device */
3122 SET_NETDEV_DEV(ndev, &pdev->dev);
3123 ret = register_netdev(ndev);
3124 if (ret) {
3125 dev_err(priv->dev, "error registering net device\n");
3126 ret = -ENODEV;
1971ab58 3127 goto clean_dma_ret;
070f9c65
K		 3128 }
3129
3130 if (cpsw->data.dual_emac) {
3131 ret = cpsw_probe_dual_emac(priv);
3132 if (ret) {
3133 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3134 goto clean_unregister_netdev_ret;
3135 }
3136 }
3137
c03abd84
FB		 3138 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3139 * MISC IRQs which are always kept disabled with this driver so
3140 * we will not request them.
3141 *
3142 * If anyone wants to implement support for those, make sure to
3143 * first request and append them to irqs_table array.
3144 */
c2b32e58 3145
c03abd84 3146 /* RX IRQ */
5087b915 3147 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 3148 if (irq < 0) {
3149 ret = irq;
1971ab58 3150 goto clean_dma_ret;
c1e3334f 3151 }
5087b915 3152
e38b5a3d 3153 cpsw->irqs_table[0] = irq;
c03abd84 3154 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
dbc4ec52 3155 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 3156 if (ret < 0) {
3157 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
1971ab58 3158 goto clean_dma_ret;
5087b915
FB		 3159 }
3160
c03abd84 3161 /* TX IRQ */
5087b915 3162 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 3163 if (irq < 0) {
3164 ret = irq;
1971ab58 3165 goto clean_dma_ret;
c1e3334f 3166 }
5087b915 3167
e38b5a3d 3168 cpsw->irqs_table[1] = irq;
c03abd84 3169 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
dbc4ec52 3170 0, dev_name(&pdev->dev), cpsw);
5087b915
FB		 3171 if (ret < 0) {
3172 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
1971ab58 3173 goto clean_dma_ret;
df828598 3174 }
c2b32e58 3175
90225bf0
GS		 3176 cpsw_notice(priv, probe,
3177 "initialized device (regs %pa, irq %d, pool size %d)\n",
3178 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
d9ba8f9e 3179
c46ab7e0
JH		 3180 pm_runtime_put(&pdev->dev);
3181
df828598
M		 3182 return 0;
3183
a7fe9d46
JH		 3184clean_unregister_netdev_ret:
3185 unregister_netdev(ndev);
df828598 3186clean_dma_ret:
2c836bd9 3187 cpdma_ctlr_destroy(cpsw->dma);
a4e32b0d
JH		 3188clean_dt_ret:
3189 cpsw_remove_dt(pdev);
c46ab7e0 3190 pm_runtime_put_sync(&pdev->dev);
aa1a15e2 3191clean_runtime_disable_ret:
f150bd7f 3192 pm_runtime_disable(&pdev->dev);
df828598 3193clean_ndev_ret:
d1bd9acf 3194 free_netdev(priv->ndev);
df828598
M		 3195 return ret;
3196}
3197
663e12e6 3198static int cpsw_remove(struct platform_device *pdev)
df828598
M		 3199{
3200 struct net_device *ndev = platform_get_drvdata(pdev);
2a05a622 3201 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
8a0b6dc9
GS		 3202 int ret;
3203
3204 ret = pm_runtime_get_sync(&pdev->dev);
3205 if (ret < 0) {
3206 pm_runtime_put_noidle(&pdev->dev);
3207 return ret;
3208 }
df828598 3209
606f3993
IK		 3210 if (cpsw->data.dual_emac)
3211 unregister_netdev(cpsw->slaves[1].ndev);
d1bd9acf 3212 unregister_netdev(ndev);
df828598 3213
8a2c9a5a 3214 cpts_release(cpsw->cpts);
2c836bd9 3215 cpdma_ctlr_destroy(cpsw->dma);
a4e32b0d 3216 cpsw_remove_dt(pdev);
8a0b6dc9
GS		 3217 pm_runtime_put_sync(&pdev->dev);
3218 pm_runtime_disable(&pdev->dev);
606f3993
IK		 3219 if (cpsw->data.dual_emac)
3220 free_netdev(cpsw->slaves[1].ndev);
df828598 3221 free_netdev(ndev);
df828598
M		 3222 return 0;
3223}
3224
8963a504 3225#ifdef CONFIG_PM_SLEEP
df828598
M		 3226static int cpsw_suspend(struct device *dev)
3227{
3228 struct platform_device *pdev = to_platform_device(dev);
3229 struct net_device *ndev = platform_get_drvdata(pdev);
606f3993 3230 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 3231
606f3993 3232 if (cpsw->data.dual_emac) {
618073e3 3233 int i;
1e7a2e21 3234
606f3993
IK		 3235 for (i = 0; i < cpsw->data.slaves; i++) {
3236 if (netif_running(cpsw->slaves[i].ndev))
3237 cpsw_ndo_stop(cpsw->slaves[i].ndev);
618073e3
M		 3238 }
3239 } else {
3240 if (netif_running(ndev))
3241 cpsw_ndo_stop(ndev);
618073e3 3242 }
1e7a2e21 3243
739683b4 3244 /* Select sleep pin state */
56e31bd8 3245 pinctrl_pm_select_sleep_state(dev);
739683b4 3246
df828598
M		 3247 return 0;
3248}
3249
3250static int cpsw_resume(struct device *dev)
3251{
3252 struct platform_device *pdev = to_platform_device(dev);
3253 struct net_device *ndev = platform_get_drvdata(pdev);
a60ced99 3254 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
df828598 3255
739683b4 3256 /* Select default pin state */
56e31bd8 3257 pinctrl_pm_select_default_state(dev);
739683b4 3258
4ccfd638
GS		 3259 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3260 rtnl_lock();
606f3993 3261 if (cpsw->data.dual_emac) {
618073e3
M		 3262 int i;
3263
606f3993
IK		 3264 for (i = 0; i < cpsw->data.slaves; i++) {
3265 if (netif_running(cpsw->slaves[i].ndev))
3266 cpsw_ndo_open(cpsw->slaves[i].ndev);
618073e3
M		 3267 }
3268 } else {
3269 if (netif_running(ndev))
3270 cpsw_ndo_open(ndev);
3271 }
4ccfd638
GS		 3272 rtnl_unlock();
3273
df828598
M		 3274 return 0;
3275}
8963a504 3276#endif
df828598 3277
8963a504 3278static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 3279
3280static struct platform_driver cpsw_driver = {
3281 .driver = {
3282 .name = "cpsw",
df828598 3283 .pm = &cpsw_pm_ops,
1e5c76d4 3284 .of_match_table = cpsw_of_mtable,
df828598
M		 3285 },
3286 .probe = cpsw_probe,
663e12e6 3287 .remove = cpsw_remove,
df828598
M		 3288};
3289
6fb3b6b5 3290module_platform_driver(cpsw_driver);
df828598
M		 3291
3292MODULE_LICENSE("GPL");
3293MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3294MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3295MODULE_DESCRIPTION("TI CPSW Ethernet driver");
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