[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / ti / cpts.h

/*
 * TI Common Platform Time Sync
 *
 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#ifndef _TI_CPTS_H_
#define _TI_CPTS_H_

#if IS_ENABLED(CONFIG_TI_CPTS)

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/skbuff.h>
#include <linux/timecounter.h>

struct cpsw_cpts {
	u32 idver;                /* Identification and version */
	u32 control;              /* Time sync control */
	u32 res1;
	u32 ts_push;              /* Time stamp event push */
	u32 ts_load_val;          /* Time stamp load value */
	u32 ts_load_en;           /* Time stamp load enable */
	u32 res2[2];
	u32 intstat_raw;          /* Time sync interrupt status raw */
	u32 intstat_masked;       /* Time sync interrupt status masked */
	u32 int_enable;           /* Time sync interrupt enable */
	u32 res3;
	u32 event_pop;            /* Event interrupt pop */
	u32 event_low;            /* 32 Bit Event Time Stamp */
	u32 event_high;           /* Event Type Fields */
};

/* Bit definitions for the IDVER register */
#define TX_IDENT_SHIFT       (16)    /* TX Identification Value */
#define TX_IDENT_MASK        (0xffff)
#define RTL_VER_SHIFT        (11)    /* RTL Version Value */
#define RTL_VER_MASK         (0x1f)
#define MAJOR_VER_SHIFT      (8)     /* Major Version Value */
#define MAJOR_VER_MASK       (0x7)
#define MINOR_VER_SHIFT      (0)     /* Minor Version Value */
#define MINOR_VER_MASK       (0xff)

/* Bit definitions for the CONTROL register */
#define HW4_TS_PUSH_EN       (1<<11) /* Hardware push 4 enable */
#define HW3_TS_PUSH_EN       (1<<10) /* Hardware push 3 enable */
#define HW2_TS_PUSH_EN       (1<<9)  /* Hardware push 2 enable */
#define HW1_TS_PUSH_EN       (1<<8)  /* Hardware push 1 enable */
#define INT_TEST             (1<<1)  /* Interrupt Test */
#define CPTS_EN              (1<<0)  /* Time Sync Enable */

/*
 * Definitions for the single bit resisters:
 * TS_PUSH TS_LOAD_EN  INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
 */
#define TS_PUSH             (1<<0)  /* Time stamp event push */
#define TS_LOAD_EN          (1<<0)  /* Time Stamp Load */
#define TS_PEND_RAW         (1<<0)  /* int read (before enable) */
#define TS_PEND             (1<<0)  /* masked interrupt read (after enable) */
#define TS_PEND_EN          (1<<0)  /* masked interrupt enable */
#define EVENT_POP           (1<<0)  /* writing discards one event */

/* Bit definitions for the EVENT_HIGH register */
#define PORT_NUMBER_SHIFT    (24)    /* Indicates Ethernet port or HW pin */
#define PORT_NUMBER_MASK     (0x1f)
#define EVENT_TYPE_SHIFT     (20)    /* Time sync event type */
#define EVENT_TYPE_MASK      (0xf)
#define MESSAGE_TYPE_SHIFT   (16)    /* PTP message type */
#define MESSAGE_TYPE_MASK    (0xf)
#define SEQUENCE_ID_SHIFT    (0)     /* PTP message sequence ID */
#define SEQUENCE_ID_MASK     (0xffff)

enum {
	CPTS_EV_PUSH, /* Time Stamp Push Event */
	CPTS_EV_ROLL, /* Time Stamp Rollover Event */
	CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
	CPTS_EV_HW,   /* Hardware Time Stamp Push Event */
	CPTS_EV_RX,   /* Ethernet Receive Event */
	CPTS_EV_TX,   /* Ethernet Transmit Event */
};

/* This covers any input clock up to about 500 MHz. */
#define CPTS_OVERFLOW_PERIOD (HZ * 8)

#define CPTS_FIFO_DEPTH 16
#define CPTS_MAX_EVENTS 32

struct cpts_event {
	struct list_head list;
	unsigned long tmo;
	u32 high;
	u32 low;
};

struct cpts {
	struct device *dev;
	struct cpsw_cpts __iomem *reg;
	int tx_enable;
	int rx_enable;
	struct ptp_clock_info info;
	struct ptp_clock *clock;
	spinlock_t lock; /* protects time registers */
	u32 cc_mult; /* for the nominal frequency */
	struct cyclecounter cc;
	struct timecounter tc;
	struct delayed_work overflow_work;
	int phc_index;
	struct clk *refclk;
	struct list_head events;
	struct list_head pool;
	struct cpts_event pool_data[CPTS_MAX_EVENTS];
};

void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
int cpts_register(struct cpts *cpts);
void cpts_unregister(struct cpts *cpts);
struct cpts *cpts_create(struct device *dev, void __iomem *regs,
			 u32 mult, u32 shift);
void cpts_release(struct cpts *cpts);

static inline void cpts_rx_enable(struct cpts *cpts, int enable)
{
	cpts->rx_enable = enable;
}

static inline bool cpts_is_rx_enabled(struct cpts *cpts)
{
	return !!cpts->rx_enable;
}

static inline void cpts_tx_enable(struct cpts *cpts, int enable)
{
	cpts->tx_enable = enable;
}

static inline bool cpts_is_tx_enabled(struct cpts *cpts)
{
	return !!cpts->tx_enable;
}

#else
struct cpts;

static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
{
}
static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
{
}

static inline
struct cpts *cpts_create(struct device *dev, void __iomem *regs,
			 u32 mult, u32 shift)
{
	return NULL;
}

static inline void cpts_release(struct cpts *cpts)
{
}

static inline int
cpts_register(struct cpts *cpts)
{
	return 0;
}

static inline void cpts_unregister(struct cpts *cpts)
{
}

static inline void cpts_rx_enable(struct cpts *cpts, int enable)
{
}

static inline bool cpts_is_rx_enabled(struct cpts *cpts)
{
	return false;
}

static inline void cpts_tx_enable(struct cpts *cpts, int enable)
{
}

static inline bool cpts_is_tx_enabled(struct cpts *cpts)
{
	return false;
}
#endif


#endif
Commit	Line	Data
87c0e764 RC	1	/*
	2	* TI Common Platform Time Sync
	3	*
	4	* Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#ifndef _TI_CPTS_H_
	21	#define _TI_CPTS_H_
	22
8a2c9a5a GS	23	#if IS_ENABLED(CONFIG_TI_CPTS)
8a2c9a5a GS	24
87c0e764 RC	25	#include <linux/clk.h>
	26	#include <linux/clkdev.h>
	27	#include <linux/clocksource.h>
	28	#include <linux/device.h>
	29	#include <linux/list.h>
	30	#include <linux/ptp_clock_kernel.h>
	31	#include <linux/skbuff.h>
74d23cc7	32	#include <linux/timecounter.h>
87c0e764 RC	33
	34	struct cpsw_cpts {
	35	u32 idver; /* Identification and version */
	36	u32 control; /* Time sync control */
	37	u32 res1;
	38	u32 ts_push; /* Time stamp event push */
	39	u32 ts_load_val; /* Time stamp load value */
	40	u32 ts_load_en; /* Time stamp load enable */
	41	u32 res2[2];
	42	u32 intstat_raw; /* Time sync interrupt status raw */
	43	u32 intstat_masked; /* Time sync interrupt status masked */
	44	u32 int_enable; /* Time sync interrupt enable */
	45	u32 res3;
	46	u32 event_pop; /* Event interrupt pop */
	47	u32 event_low; /* 32 Bit Event Time Stamp */
	48	u32 event_high; /* Event Type Fields */
	49	};
	50
	51	/* Bit definitions for the IDVER register */
	52	#define TX_IDENT_SHIFT (16) /* TX Identification Value */
	53	#define TX_IDENT_MASK (0xffff)
	54	#define RTL_VER_SHIFT (11) /* RTL Version Value */
	55	#define RTL_VER_MASK (0x1f)
	56	#define MAJOR_VER_SHIFT (8) /* Major Version Value */
	57	#define MAJOR_VER_MASK (0x7)
	58	#define MINOR_VER_SHIFT (0) /* Minor Version Value */
	59	#define MINOR_VER_MASK (0xff)
	60
	61	/* Bit definitions for the CONTROL register */
	62	#define HW4_TS_PUSH_EN (1<<11) /* Hardware push 4 enable */
	63	#define HW3_TS_PUSH_EN (1<<10) /* Hardware push 3 enable */
	64	#define HW2_TS_PUSH_EN (1<<9) /* Hardware push 2 enable */
	65	#define HW1_TS_PUSH_EN (1<<8) /* Hardware push 1 enable */
	66	#define INT_TEST (1<<1) /* Interrupt Test */
	67	#define CPTS_EN (1<<0) /* Time Sync Enable */
	68
	69	/*
	70	* Definitions for the single bit resisters:
	71	* TS_PUSH TS_LOAD_EN INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
	72	*/
	73	#define TS_PUSH (1<<0) /* Time stamp event push */
	74	#define TS_LOAD_EN (1<<0) /* Time Stamp Load */
	75	#define TS_PEND_RAW (1<<0) /* int read (before enable) */
	76	#define TS_PEND (1<<0) /* masked interrupt read (after enable) */
	77	#define TS_PEND_EN (1<<0) /* masked interrupt enable */
	78	#define EVENT_POP (1<<0) /* writing discards one event */
	79
	80	/* Bit definitions for the EVENT_HIGH register */
	81	#define PORT_NUMBER_SHIFT (24) /* Indicates Ethernet port or HW pin */
	82	#define PORT_NUMBER_MASK (0x1f)
	83	#define EVENT_TYPE_SHIFT (20) /* Time sync event type */
	84	#define EVENT_TYPE_MASK (0xf)
	85	#define MESSAGE_TYPE_SHIFT (16) /* PTP message type */
	86	#define MESSAGE_TYPE_MASK (0xf)
	87	#define SEQUENCE_ID_SHIFT (0) /* PTP message sequence ID */
	88	#define SEQUENCE_ID_MASK (0xffff)
	89
	90	enum {
	91	CPTS_EV_PUSH, /* Time Stamp Push Event */
	92	CPTS_EV_ROLL, /* Time Stamp Rollover Event */
	93	CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
	94	CPTS_EV_HW, /* Hardware Time Stamp Push Event */
	95	CPTS_EV_RX, /* Ethernet Receive Event */
	96	CPTS_EV_TX, /* Ethernet Transmit Event */
97	};
98
99	/* This covers any input clock up to about 500 MHz. */
100	#define CPTS_OVERFLOW_PERIOD (HZ * 8)
101
102	#define CPTS_FIFO_DEPTH 16
103	#define CPTS_MAX_EVENTS 32
104
105	struct cpts_event {
106	struct list_head list;
107	unsigned long tmo;
108	u32 high;
109	u32 low;
110	};
111
112	struct cpts {
8a2c9a5a	113	struct device *dev;
87c0e764 RC	114	struct cpsw_cpts __iomem *reg;
	115	int tx_enable;
	116	int rx_enable;
87c0e764 RC	117	struct ptp_clock_info info;
	118	struct ptp_clock *clock;
	119	spinlock_t lock; /* protects time registers */
	120	u32 cc_mult; /* for the nominal frequency */
	121	struct cyclecounter cc;
	122	struct timecounter tc;
	123	struct delayed_work overflow_work;
	124	int phc_index;
	125	struct clk *refclk;
87c0e764 RC	126	struct list_head events;
	127	struct list_head pool;
	128	struct cpts_event pool_data[CPTS_MAX_EVENTS];
87c0e764 RC	129	};
87c0e764 RC	130
95f7f151 JP	131	void cpts_rx_timestamp(struct cpts cpts, struct sk_buff skb);
95f7f151 JP	132	void cpts_tx_timestamp(struct cpts cpts, struct sk_buff skb);
8a2c9a5a	133	int cpts_register(struct cpts *cpts);
c8395d4e	134	void cpts_unregister(struct cpts *cpts);
8a2c9a5a GS	135	struct cpts cpts_create(struct device dev, void __iomem *regs,
	136	u32 mult, u32 shift);
	137	void cpts_release(struct cpts *cpts);
b63ba58e GS	138
	139	static inline void cpts_rx_enable(struct cpts *cpts, int enable)
	140	{
	141	cpts->rx_enable = enable;
	142	}
	143
	144	static inline bool cpts_is_rx_enabled(struct cpts *cpts)
	145	{
	146	return !!cpts->rx_enable;
	147	}
	148
	149	static inline void cpts_tx_enable(struct cpts *cpts, int enable)
	150	{
	151	cpts->tx_enable = enable;
	152	}
	153
	154	static inline bool cpts_is_tx_enabled(struct cpts *cpts)
	155	{
	156	return !!cpts->tx_enable;
	157	}
	158
87c0e764	159	#else
8a2c9a5a GS	160	struct cpts;
8a2c9a5a GS	161
87c0e764 RC	162	static inline void cpts_rx_timestamp(struct cpts cpts, struct sk_buff skb)
	163	{
	164	}
	165	static inline void cpts_tx_timestamp(struct cpts cpts, struct sk_buff skb)
	166	{
	167	}
c8395d4e	168
8a2c9a5a GS	169	static inline
	170	struct cpts cpts_create(struct device dev, void __iomem *regs,
	171	u32 mult, u32 shift)
	172	{
	173	return NULL;
	174	}
	175
	176	static inline void cpts_release(struct cpts *cpts)
	177	{
	178	}
	179
c8395d4e	180	static inline int
8a2c9a5a	181	cpts_register(struct cpts *cpts)
c8395d4e GS	182	{
	183	return 0;
	184	}
	185
	186	static inline void cpts_unregister(struct cpts *cpts)
	187	{
	188	}
b63ba58e GS	189
	190	static inline void cpts_rx_enable(struct cpts *cpts, int enable)
	191	{
	192	}
	193
	194	static inline bool cpts_is_rx_enabled(struct cpts *cpts)
	195	{
	196	return false;
	197	}
	198
	199	static inline void cpts_tx_enable(struct cpts *cpts, int enable)
	200	{
	201	}
	202
	203	static inline bool cpts_is_tx_enabled(struct cpts *cpts)
	204	{
	205	return false;
	206	}
87c0e764 RC	207	#endif
87c0e764 RC	208
87c0e764 RC	209
87c0e764 RC	210	#endif