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a6286ee6 AG |
1 | /* |
2 | * DaVinci Ethernet Medium Access Controller | |
3 | * | |
4 | * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine | |
5 | * | |
6 | * Copyright (C) 2009 Texas Instruments. | |
7 | * | |
8 | * --------------------------------------------------------------------------- | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * --------------------------------------------------------------------------- | |
24 | * History: | |
25 | * 0-5 A number of folks worked on this driver in bits and pieces but the major | |
26 | * contribution came from Suraj Iyer and Anant Gole | |
27 | * 6.0 Anant Gole - rewrote the driver as per Linux conventions | |
28 | * 6.1 Chaithrika U S - added support for Gigabit and RMII features, | |
29 | * PHY layer usage | |
30 | */ | |
31 | ||
a6286ee6 AG |
32 | #include <linux/module.h> |
33 | #include <linux/kernel.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/timer.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/mm.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/netdevice.h> | |
45 | #include <linux/etherdevice.h> | |
46 | #include <linux/skbuff.h> | |
47 | #include <linux/ethtool.h> | |
48 | #include <linux/highmem.h> | |
49 | #include <linux/proc_fs.h> | |
50 | #include <linux/ctype.h> | |
a6286ee6 AG |
51 | #include <linux/spinlock.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/clk.h> | |
54 | #include <linux/platform_device.h> | |
f276c0ce | 55 | #include <linux/regmap.h> |
a6286ee6 AG |
56 | #include <linux/semaphore.h> |
57 | #include <linux/phy.h> | |
58 | #include <linux/bitops.h> | |
59 | #include <linux/io.h> | |
60 | #include <linux/uaccess.h> | |
3ba97381 | 61 | #include <linux/pm_runtime.h> |
8ee2bf9a | 62 | #include <linux/davinci_emac.h> |
42f59967 HS |
63 | #include <linux/of.h> |
64 | #include <linux/of_address.h> | |
dd0df47d | 65 | #include <linux/of_device.h> |
1d82ffa6 | 66 | #include <linux/of_mdio.h> |
42f59967 HS |
67 | #include <linux/of_irq.h> |
68 | #include <linux/of_net.h> | |
f276c0ce | 69 | #include <linux/mfd/syscon.h> |
42f59967 | 70 | |
a6286ee6 AG |
71 | #include <asm/irq.h> |
72 | #include <asm/page.h> | |
73 | ||
9120bd6e | 74 | #include "cpsw.h" |
3ef0fdb2 CC |
75 | #include "davinci_cpdma.h" |
76 | ||
a6286ee6 AG |
77 | static int debug_level; |
78 | module_param(debug_level, int, 0); | |
79 | MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); | |
80 | ||
81 | /* Netif debug messages possible */ | |
82 | #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ | |
83 | NETIF_MSG_PROBE | \ | |
84 | NETIF_MSG_LINK | \ | |
85 | NETIF_MSG_TIMER | \ | |
86 | NETIF_MSG_IFDOWN | \ | |
87 | NETIF_MSG_IFUP | \ | |
88 | NETIF_MSG_RX_ERR | \ | |
89 | NETIF_MSG_TX_ERR | \ | |
90 | NETIF_MSG_TX_QUEUED | \ | |
91 | NETIF_MSG_INTR | \ | |
92 | NETIF_MSG_TX_DONE | \ | |
93 | NETIF_MSG_RX_STATUS | \ | |
94 | NETIF_MSG_PKTDATA | \ | |
95 | NETIF_MSG_HW | \ | |
96 | NETIF_MSG_WOL) | |
97 | ||
98 | /* version info */ | |
99 | #define EMAC_MAJOR_VERSION 6 | |
100 | #define EMAC_MINOR_VERSION 1 | |
101 | #define EMAC_MODULE_VERSION "6.1" | |
102 | MODULE_VERSION(EMAC_MODULE_VERSION); | |
103 | static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; | |
104 | ||
105 | /* Configuration items */ | |
25985edc | 106 | #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ |
a6286ee6 AG |
107 | #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ |
108 | #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ | |
109 | #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ | |
110 | #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ | |
111 | #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ | |
25985edc LDM |
112 | #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ |
113 | #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ | |
a6286ee6 AG |
114 | #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ |
115 | #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ | |
116 | #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ | |
117 | #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ | |
118 | ||
119 | #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ | |
120 | #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ | |
121 | ||
122 | #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ | |
123 | #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ | |
124 | #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) | |
125 | #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ | |
126 | #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ | |
3ef0fdb2 | 127 | #define EMAC_DEF_RX_NUM_DESC (128) |
a6286ee6 AG |
128 | #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ |
129 | #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ | |
130 | #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ | |
131 | ||
132 | /* Buffer descriptor parameters */ | |
133 | #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ | |
134 | #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ | |
135 | ||
136 | /* EMAC register related defines */ | |
137 | #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) | |
138 | #define EMAC_NUM_MULTICAST_BITS (64) | |
a6286ee6 AG |
139 | #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) |
140 | #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) | |
141 | #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) | |
142 | #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) | |
143 | #define EMAC_INT_MASK_CLEAR (0xFF) | |
144 | ||
145 | /* RX MBP register bit positions */ | |
146 | #define EMAC_RXMBP_PASSCRC_MASK BIT(30) | |
147 | #define EMAC_RXMBP_QOSEN_MASK BIT(29) | |
148 | #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) | |
149 | #define EMAC_RXMBP_CMFEN_MASK BIT(24) | |
150 | #define EMAC_RXMBP_CSFEN_MASK BIT(23) | |
151 | #define EMAC_RXMBP_CEFEN_MASK BIT(22) | |
152 | #define EMAC_RXMBP_CAFEN_MASK BIT(21) | |
153 | #define EMAC_RXMBP_PROMCH_SHIFT (16) | |
154 | #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) | |
155 | #define EMAC_RXMBP_BROADEN_MASK BIT(13) | |
156 | #define EMAC_RXMBP_BROADCH_SHIFT (8) | |
157 | #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) | |
158 | #define EMAC_RXMBP_MULTIEN_MASK BIT(5) | |
159 | #define EMAC_RXMBP_MULTICH_SHIFT (0) | |
160 | #define EMAC_RXMBP_MULTICH_MASK (0x7) | |
161 | #define EMAC_RXMBP_CHMASK (0x7) | |
162 | ||
163 | /* EMAC register definitions/bit maps used */ | |
164 | # define EMAC_MBP_RXPROMISC (0x00200000) | |
165 | # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) | |
166 | # define EMAC_MBP_RXBCAST (0x00002000) | |
167 | # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) | |
168 | # define EMAC_MBP_RXMCAST (0x00000020) | |
169 | # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) | |
170 | ||
171 | /* EMAC mac_control register */ | |
69ef9694 | 172 | #define EMAC_MACCONTROL_TXPTYPE BIT(9) |
173 | #define EMAC_MACCONTROL_TXPACEEN BIT(6) | |
174 | #define EMAC_MACCONTROL_GMIIEN BIT(5) | |
175 | #define EMAC_MACCONTROL_GIGABITEN BIT(7) | |
176 | #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) | |
a6286ee6 AG |
177 | #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) |
178 | ||
179 | /* GIGABIT MODE related bits */ | |
a6286ee6 AG |
180 | #define EMAC_DM646X_MACCONTORL_GIG BIT(7) |
181 | #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) | |
182 | ||
183 | /* EMAC mac_status register */ | |
184 | #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) | |
185 | #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) | |
186 | #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) | |
187 | #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) | |
188 | #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) | |
189 | #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) | |
190 | #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) | |
191 | #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) | |
192 | ||
193 | /* EMAC RX register masks */ | |
194 | #define EMAC_RX_MAX_LEN_MASK (0xFFFF) | |
195 | #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) | |
196 | ||
197 | /* MAC_IN_VECTOR (0x180) register bit fields */ | |
69ef9694 | 198 | #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) |
199 | #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) | |
200 | #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) | |
201 | #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) | |
a6286ee6 AG |
202 | |
203 | /** NOTE:: For DM646x the IN_VECTOR has changed */ | |
204 | #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) | |
205 | #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) | |
43c2ed8e S |
206 | #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) |
207 | #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) | |
208 | ||
a6286ee6 AG |
209 | /* CPPI bit positions */ |
210 | #define EMAC_CPPI_SOP_BIT BIT(31) | |
211 | #define EMAC_CPPI_EOP_BIT BIT(30) | |
212 | #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) | |
213 | #define EMAC_CPPI_EOQ_BIT BIT(28) | |
214 | #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) | |
215 | #define EMAC_CPPI_PASS_CRC_BIT BIT(26) | |
216 | #define EMAC_RX_BD_BUF_SIZE (0xFFFF) | |
217 | #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ | |
218 | #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) | |
219 | ||
220 | /* Max hardware defines */ | |
221 | #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ | |
222 | #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ | |
223 | ||
224 | /* EMAC Peripheral Device Register Memory Layout structure */ | |
a6286ee6 AG |
225 | #define EMAC_MACINVECTOR 0x90 |
226 | ||
227 | #define EMAC_DM646X_MACEOIVECTOR 0x94 | |
228 | ||
a6286ee6 AG |
229 | #define EMAC_MACINTSTATRAW 0xB0 |
230 | #define EMAC_MACINTSTATMASKED 0xB4 | |
231 | #define EMAC_MACINTMASKSET 0xB8 | |
232 | #define EMAC_MACINTMASKCLEAR 0xBC | |
233 | ||
234 | #define EMAC_RXMBPENABLE 0x100 | |
235 | #define EMAC_RXUNICASTSET 0x104 | |
236 | #define EMAC_RXUNICASTCLEAR 0x108 | |
237 | #define EMAC_RXMAXLEN 0x10C | |
238 | #define EMAC_RXBUFFEROFFSET 0x110 | |
239 | #define EMAC_RXFILTERLOWTHRESH 0x114 | |
240 | ||
241 | #define EMAC_MACCONTROL 0x160 | |
242 | #define EMAC_MACSTATUS 0x164 | |
243 | #define EMAC_EMCONTROL 0x168 | |
244 | #define EMAC_FIFOCONTROL 0x16C | |
245 | #define EMAC_MACCONFIG 0x170 | |
246 | #define EMAC_SOFTRESET 0x174 | |
247 | #define EMAC_MACSRCADDRLO 0x1D0 | |
248 | #define EMAC_MACSRCADDRHI 0x1D4 | |
249 | #define EMAC_MACHASH1 0x1D8 | |
250 | #define EMAC_MACHASH2 0x1DC | |
251 | #define EMAC_MACADDRLO 0x500 | |
252 | #define EMAC_MACADDRHI 0x504 | |
253 | #define EMAC_MACINDEX 0x508 | |
254 | ||
a6286ee6 AG |
255 | /* EMAC statistics registers */ |
256 | #define EMAC_RXGOODFRAMES 0x200 | |
257 | #define EMAC_RXBCASTFRAMES 0x204 | |
258 | #define EMAC_RXMCASTFRAMES 0x208 | |
259 | #define EMAC_RXPAUSEFRAMES 0x20C | |
260 | #define EMAC_RXCRCERRORS 0x210 | |
261 | #define EMAC_RXALIGNCODEERRORS 0x214 | |
262 | #define EMAC_RXOVERSIZED 0x218 | |
263 | #define EMAC_RXJABBER 0x21C | |
264 | #define EMAC_RXUNDERSIZED 0x220 | |
265 | #define EMAC_RXFRAGMENTS 0x224 | |
266 | #define EMAC_RXFILTERED 0x228 | |
267 | #define EMAC_RXQOSFILTERED 0x22C | |
268 | #define EMAC_RXOCTETS 0x230 | |
269 | #define EMAC_TXGOODFRAMES 0x234 | |
270 | #define EMAC_TXBCASTFRAMES 0x238 | |
271 | #define EMAC_TXMCASTFRAMES 0x23C | |
272 | #define EMAC_TXPAUSEFRAMES 0x240 | |
273 | #define EMAC_TXDEFERRED 0x244 | |
274 | #define EMAC_TXCOLLISION 0x248 | |
275 | #define EMAC_TXSINGLECOLL 0x24C | |
276 | #define EMAC_TXMULTICOLL 0x250 | |
277 | #define EMAC_TXEXCESSIVECOLL 0x254 | |
278 | #define EMAC_TXLATECOLL 0x258 | |
279 | #define EMAC_TXUNDERRUN 0x25C | |
280 | #define EMAC_TXCARRIERSENSE 0x260 | |
281 | #define EMAC_TXOCTETS 0x264 | |
282 | #define EMAC_NETOCTETS 0x280 | |
283 | #define EMAC_RXSOFOVERRUNS 0x284 | |
284 | #define EMAC_RXMOFOVERRUNS 0x288 | |
285 | #define EMAC_RXDMAOVERRUNS 0x28C | |
286 | ||
287 | /* EMAC DM644x control registers */ | |
288 | #define EMAC_CTRL_EWCTL (0x4) | |
289 | #define EMAC_CTRL_EWINTTCNT (0x8) | |
290 | ||
84da2658 S |
291 | /* EMAC DM644x control module masks */ |
292 | #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF | |
293 | #define EMAC_DM644X_INTMIN_INTVL 0x1 | |
294 | #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) | |
295 | ||
a6286ee6 | 296 | /* EMAC DM646X control module registers */ |
84da2658 S |
297 | #define EMAC_DM646X_CMINTCTRL 0x0C |
298 | #define EMAC_DM646X_CMRXINTEN 0x14 | |
299 | #define EMAC_DM646X_CMTXINTEN 0x18 | |
300 | #define EMAC_DM646X_CMRXINTMAX 0x70 | |
301 | #define EMAC_DM646X_CMTXINTMAX 0x74 | |
302 | ||
303 | /* EMAC DM646X control module masks */ | |
304 | #define EMAC_DM646X_INTPACEEN (0x3 << 16) | |
305 | #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) | |
306 | #define EMAC_DM646X_CMINTMAX_CNT 63 | |
307 | #define EMAC_DM646X_CMINTMIN_CNT 2 | |
308 | #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) | |
309 | #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) | |
310 | ||
a6286ee6 AG |
311 | |
312 | /* EMAC EOI codes for C0 */ | |
313 | #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) | |
314 | #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) | |
315 | ||
0fe7463a S |
316 | /* EMAC Stats Clear Mask */ |
317 | #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) | |
318 | ||
a6286ee6 AG |
319 | /* emac_priv: EMAC private data structure |
320 | * | |
321 | * EMAC adapter private data structure | |
322 | */ | |
323 | struct emac_priv { | |
324 | u32 msg_enable; | |
325 | struct net_device *ndev; | |
326 | struct platform_device *pdev; | |
327 | struct napi_struct napi; | |
328 | char mac_addr[6]; | |
a6286ee6 AG |
329 | void __iomem *remap_addr; |
330 | u32 emac_base_phys; | |
331 | void __iomem *emac_base; | |
332 | void __iomem *ctrl_base; | |
3ef0fdb2 CC |
333 | struct cpdma_ctlr *dma; |
334 | struct cpdma_chan *txchan; | |
335 | struct cpdma_chan *rxchan; | |
a6286ee6 AG |
336 | u32 link; /* 1=link on, 0=link off */ |
337 | u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ | |
338 | u32 duplex; /* Link duplex: 0=Half, 1=Full */ | |
339 | u32 rx_buf_size; | |
340 | u32 isr_count; | |
84da2658 S |
341 | u32 coal_intvl; |
342 | u32 bus_freq_mhz; | |
a6286ee6 AG |
343 | u8 rmii_en; |
344 | u8 version; | |
a6286ee6 AG |
345 | u32 mac_hash1; |
346 | u32 mac_hash2; | |
347 | u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; | |
348 | u32 rx_addr_type; | |
5d69e007 | 349 | const char *phy_id; |
42f59967 | 350 | struct device_node *phy_node; |
a6286ee6 | 351 | spinlock_t lock; |
01a9af36 S |
352 | /*platform specific members*/ |
353 | void (*int_enable) (void); | |
354 | void (*int_disable) (void); | |
a6286ee6 AG |
355 | }; |
356 | ||
a6286ee6 AG |
357 | /* EMAC TX Host Error description strings */ |
358 | static char *emac_txhost_errcodes[16] = { | |
359 | "No error", "SOP error", "Ownership bit not set in SOP buffer", | |
360 | "Zero Next Buffer Descriptor Pointer Without EOP", | |
361 | "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", | |
362 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", | |
363 | "Reserved", "Reserved", "Reserved", "Reserved" | |
364 | }; | |
365 | ||
366 | /* EMAC RX Host Error description strings */ | |
367 | static char *emac_rxhost_errcodes[16] = { | |
368 | "No error", "Reserved", "Ownership bit not set in input buffer", | |
369 | "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", | |
370 | "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", | |
371 | "Reserved", "Reserved", "Reserved", "Reserved" | |
372 | }; | |
373 | ||
374 | /* Helper macros */ | |
375 | #define emac_read(reg) ioread32(priv->emac_base + (reg)) | |
376 | #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) | |
377 | ||
378 | #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) | |
379 | #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) | |
380 | ||
a6286ee6 | 381 | /** |
49ce9c2c | 382 | * emac_get_drvinfo - Get EMAC driver information |
a6286ee6 AG |
383 | * @ndev: The DaVinci EMAC network adapter |
384 | * @info: ethtool info structure containing name and version | |
385 | * | |
386 | * Returns EMAC driver information (name and version) | |
387 | * | |
388 | */ | |
389 | static void emac_get_drvinfo(struct net_device *ndev, | |
390 | struct ethtool_drvinfo *info) | |
391 | { | |
7826d43f JP |
392 | strlcpy(info->driver, emac_version_string, sizeof(info->driver)); |
393 | strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); | |
a6286ee6 AG |
394 | } |
395 | ||
84da2658 | 396 | /** |
49ce9c2c | 397 | * emac_get_coalesce - Get interrupt coalesce settings for this device |
84da2658 S |
398 | * @ndev : The DaVinci EMAC network adapter |
399 | * @coal : ethtool coalesce settings structure | |
400 | * | |
401 | * Fetch the current interrupt coalesce settings | |
402 | * | |
403 | */ | |
404 | static int emac_get_coalesce(struct net_device *ndev, | |
405 | struct ethtool_coalesce *coal) | |
406 | { | |
407 | struct emac_priv *priv = netdev_priv(ndev); | |
408 | ||
409 | coal->rx_coalesce_usecs = priv->coal_intvl; | |
410 | return 0; | |
411 | ||
412 | } | |
413 | ||
414 | /** | |
49ce9c2c | 415 | * emac_set_coalesce - Set interrupt coalesce settings for this device |
84da2658 S |
416 | * @ndev : The DaVinci EMAC network adapter |
417 | * @coal : ethtool coalesce settings structure | |
418 | * | |
419 | * Set interrupt coalesce parameters | |
420 | * | |
421 | */ | |
422 | static int emac_set_coalesce(struct net_device *ndev, | |
423 | struct ethtool_coalesce *coal) | |
424 | { | |
425 | struct emac_priv *priv = netdev_priv(ndev); | |
426 | u32 int_ctrl, num_interrupts = 0; | |
427 | u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; | |
428 | ||
429 | if (!coal->rx_coalesce_usecs) | |
430 | return -EINVAL; | |
431 | ||
432 | coal_intvl = coal->rx_coalesce_usecs; | |
433 | ||
434 | switch (priv->version) { | |
435 | case EMAC_VERSION_2: | |
436 | int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); | |
437 | prescale = priv->bus_freq_mhz * 4; | |
438 | ||
439 | if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) | |
440 | coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; | |
441 | ||
442 | if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { | |
443 | /* | |
444 | * Interrupt pacer works with 4us Pulse, we can | |
445 | * throttle further by dilating the 4us pulse. | |
446 | */ | |
447 | addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; | |
448 | ||
449 | if (addnl_dvdr > 1) { | |
450 | prescale *= addnl_dvdr; | |
451 | if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL | |
452 | * addnl_dvdr)) | |
453 | coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL | |
454 | * addnl_dvdr); | |
455 | } else { | |
456 | addnl_dvdr = 1; | |
457 | coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; | |
458 | } | |
459 | } | |
460 | ||
461 | num_interrupts = (1000 * addnl_dvdr) / coal_intvl; | |
462 | ||
463 | int_ctrl |= EMAC_DM646X_INTPACEEN; | |
464 | int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); | |
465 | int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); | |
466 | emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); | |
467 | ||
468 | emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); | |
469 | emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); | |
470 | ||
471 | break; | |
472 | default: | |
473 | int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); | |
474 | int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); | |
475 | prescale = coal_intvl * priv->bus_freq_mhz; | |
476 | if (prescale > EMAC_DM644X_EWINTCNT_MASK) { | |
477 | prescale = EMAC_DM644X_EWINTCNT_MASK; | |
478 | coal_intvl = prescale / priv->bus_freq_mhz; | |
479 | } | |
480 | emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); | |
481 | ||
482 | break; | |
483 | } | |
484 | ||
485 | printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); | |
486 | priv->coal_intvl = coal_intvl; | |
487 | ||
488 | return 0; | |
489 | ||
490 | } | |
491 | ||
492 | ||
1aa8b471 | 493 | /* ethtool_ops: DaVinci EMAC Ethtool structure |
a6286ee6 AG |
494 | * |
495 | * Ethtool support for EMAC adapter | |
a6286ee6 AG |
496 | */ |
497 | static const struct ethtool_ops ethtool_ops = { | |
498 | .get_drvinfo = emac_get_drvinfo, | |
a6286ee6 | 499 | .get_link = ethtool_op_get_link, |
84da2658 S |
500 | .get_coalesce = emac_get_coalesce, |
501 | .set_coalesce = emac_set_coalesce, | |
1fa68bed | 502 | .get_ts_info = ethtool_op_get_ts_info, |
efb15c39 PR |
503 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
504 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
a6286ee6 AG |
505 | }; |
506 | ||
507 | /** | |
49ce9c2c | 508 | * emac_update_phystatus - Update Phy status |
a6286ee6 AG |
509 | * @priv: The DaVinci EMAC private adapter structure |
510 | * | |
511 | * Updates phy status and takes action for network queue if required | |
512 | * based upon link status | |
513 | * | |
514 | */ | |
515 | static void emac_update_phystatus(struct emac_priv *priv) | |
516 | { | |
517 | u32 mac_control; | |
518 | u32 new_duplex; | |
519 | u32 cur_duplex; | |
520 | struct net_device *ndev = priv->ndev; | |
521 | ||
522 | mac_control = emac_read(EMAC_MACCONTROL); | |
523 | cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? | |
524 | DUPLEX_FULL : DUPLEX_HALF; | |
c332177e PR |
525 | if (ndev->phydev) |
526 | new_duplex = ndev->phydev->duplex; | |
a6286ee6 AG |
527 | else |
528 | new_duplex = DUPLEX_FULL; | |
529 | ||
530 | /* We get called only if link has changed (speed/duplex/status) */ | |
531 | if ((priv->link) && (new_duplex != cur_duplex)) { | |
532 | priv->duplex = new_duplex; | |
533 | if (DUPLEX_FULL == priv->duplex) | |
534 | mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); | |
535 | else | |
536 | mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); | |
537 | } | |
538 | ||
539 | if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { | |
540 | mac_control = emac_read(EMAC_MACCONTROL); | |
69ef9694 | 541 | mac_control |= (EMAC_DM646X_MACCONTORL_GIG | |
a6286ee6 AG |
542 | EMAC_DM646X_MACCONTORL_GIGFORCE); |
543 | } else { | |
544 | /* Clear the GIG bit and GIGFORCE bit */ | |
545 | mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | | |
546 | EMAC_DM646X_MACCONTORL_GIG); | |
547 | ||
548 | if (priv->rmii_en && (priv->speed == SPEED_100)) | |
549 | mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; | |
550 | else | |
551 | mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; | |
552 | } | |
553 | ||
554 | /* Update mac_control if changed */ | |
555 | emac_write(EMAC_MACCONTROL, mac_control); | |
556 | ||
557 | if (priv->link) { | |
558 | /* link ON */ | |
559 | if (!netif_carrier_ok(ndev)) | |
560 | netif_carrier_on(ndev); | |
561 | /* reactivate the transmit queue if it is stopped */ | |
562 | if (netif_running(ndev) && netif_queue_stopped(ndev)) | |
563 | netif_wake_queue(ndev); | |
564 | } else { | |
565 | /* link OFF */ | |
566 | if (netif_carrier_ok(ndev)) | |
567 | netif_carrier_off(ndev); | |
568 | if (!netif_queue_stopped(ndev)) | |
569 | netif_stop_queue(ndev); | |
570 | } | |
571 | } | |
572 | ||
573 | /** | |
49ce9c2c | 574 | * hash_get - Calculate hash value from mac address |
a6286ee6 AG |
575 | * @addr: mac address to delete from hash table |
576 | * | |
577 | * Calculates hash value from mac address | |
578 | * | |
579 | */ | |
580 | static u32 hash_get(u8 *addr) | |
581 | { | |
582 | u32 hash; | |
583 | u8 tmpval; | |
584 | int cnt; | |
585 | hash = 0; | |
586 | ||
587 | for (cnt = 0; cnt < 2; cnt++) { | |
588 | tmpval = *addr++; | |
589 | hash ^= (tmpval >> 2) ^ (tmpval << 4); | |
590 | tmpval = *addr++; | |
591 | hash ^= (tmpval >> 4) ^ (tmpval << 2); | |
592 | tmpval = *addr++; | |
593 | hash ^= (tmpval >> 6) ^ (tmpval); | |
594 | } | |
595 | ||
596 | return hash & 0x3F; | |
597 | } | |
598 | ||
599 | /** | |
e87a8f24 | 600 | * emac_hash_add - Hash function to add mac addr from hash table |
a6286ee6 | 601 | * @priv: The DaVinci EMAC private adapter structure |
49ce9c2c | 602 | * @mac_addr: mac address to delete from hash table |
a6286ee6 AG |
603 | * |
604 | * Adds mac address to the internal hash table | |
605 | * | |
606 | */ | |
e87a8f24 | 607 | static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr) |
a6286ee6 AG |
608 | { |
609 | struct device *emac_dev = &priv->ndev->dev; | |
610 | u32 rc = 0; | |
611 | u32 hash_bit; | |
612 | u32 hash_value = hash_get(mac_addr); | |
613 | ||
614 | if (hash_value >= EMAC_NUM_MULTICAST_BITS) { | |
615 | if (netif_msg_drv(priv)) { | |
e87a8f24 | 616 | dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\ |
a6286ee6 AG |
617 | "Hash %08x, should not be greater than %08x", |
618 | hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); | |
619 | } | |
620 | return -1; | |
621 | } | |
622 | ||
623 | /* set the hash bit only if not previously set */ | |
624 | if (priv->multicast_hash_cnt[hash_value] == 0) { | |
625 | rc = 1; /* hash value changed */ | |
626 | if (hash_value < 32) { | |
627 | hash_bit = BIT(hash_value); | |
628 | priv->mac_hash1 |= hash_bit; | |
629 | } else { | |
630 | hash_bit = BIT((hash_value - 32)); | |
631 | priv->mac_hash2 |= hash_bit; | |
632 | } | |
633 | } | |
634 | ||
635 | /* incr counter for num of mcast addr's mapped to "this" hash bit */ | |
636 | ++priv->multicast_hash_cnt[hash_value]; | |
637 | ||
638 | return rc; | |
639 | } | |
640 | ||
641 | /** | |
e87a8f24 | 642 | * emac_hash_del - Hash function to delete mac addr from hash table |
a6286ee6 | 643 | * @priv: The DaVinci EMAC private adapter structure |
49ce9c2c | 644 | * @mac_addr: mac address to delete from hash table |
a6286ee6 AG |
645 | * |
646 | * Removes mac address from the internal hash table | |
647 | * | |
648 | */ | |
e87a8f24 | 649 | static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr) |
a6286ee6 AG |
650 | { |
651 | u32 hash_value; | |
652 | u32 hash_bit; | |
653 | ||
654 | hash_value = hash_get(mac_addr); | |
655 | if (priv->multicast_hash_cnt[hash_value] > 0) { | |
656 | /* dec cntr for num of mcast addr's mapped to this hash bit */ | |
657 | --priv->multicast_hash_cnt[hash_value]; | |
658 | } | |
659 | ||
660 | /* if counter still > 0, at least one multicast address refers | |
661 | * to this hash bit. so return 0 */ | |
662 | if (priv->multicast_hash_cnt[hash_value] > 0) | |
663 | return 0; | |
664 | ||
665 | if (hash_value < 32) { | |
666 | hash_bit = BIT(hash_value); | |
667 | priv->mac_hash1 &= ~hash_bit; | |
668 | } else { | |
669 | hash_bit = BIT((hash_value - 32)); | |
670 | priv->mac_hash2 &= ~hash_bit; | |
671 | } | |
672 | ||
673 | /* return 1 to indicate change in mac_hash registers reqd */ | |
674 | return 1; | |
675 | } | |
676 | ||
677 | /* EMAC multicast operation */ | |
678 | #define EMAC_MULTICAST_ADD 0 | |
679 | #define EMAC_MULTICAST_DEL 1 | |
680 | #define EMAC_ALL_MULTI_SET 2 | |
681 | #define EMAC_ALL_MULTI_CLR 3 | |
682 | ||
683 | /** | |
49ce9c2c | 684 | * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) |
a6286ee6 AG |
685 | * @priv: The DaVinci EMAC private adapter structure |
686 | * @action: multicast operation to perform | |
687 | * mac_addr: mac address to set | |
688 | * | |
689 | * Set multicast addresses in EMAC adapter - internal function | |
690 | * | |
691 | */ | |
692 | static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) | |
693 | { | |
694 | struct device *emac_dev = &priv->ndev->dev; | |
695 | int update = -1; | |
696 | ||
697 | switch (action) { | |
698 | case EMAC_MULTICAST_ADD: | |
e87a8f24 | 699 | update = emac_hash_add(priv, mac_addr); |
a6286ee6 AG |
700 | break; |
701 | case EMAC_MULTICAST_DEL: | |
e87a8f24 | 702 | update = emac_hash_del(priv, mac_addr); |
a6286ee6 AG |
703 | break; |
704 | case EMAC_ALL_MULTI_SET: | |
705 | update = 1; | |
706 | priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; | |
707 | priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; | |
708 | break; | |
709 | case EMAC_ALL_MULTI_CLR: | |
710 | update = 1; | |
711 | priv->mac_hash1 = 0; | |
712 | priv->mac_hash2 = 0; | |
713 | memset(&(priv->multicast_hash_cnt[0]), 0, | |
714 | sizeof(priv->multicast_hash_cnt[0]) * | |
715 | EMAC_NUM_MULTICAST_BITS); | |
716 | break; | |
717 | default: | |
718 | if (netif_msg_drv(priv)) | |
719 | dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ | |
720 | ": bad operation %d", action); | |
721 | break; | |
722 | } | |
723 | ||
724 | /* write to the hardware only if the register status chances */ | |
725 | if (update > 0) { | |
726 | emac_write(EMAC_MACHASH1, priv->mac_hash1); | |
727 | emac_write(EMAC_MACHASH2, priv->mac_hash2); | |
728 | } | |
729 | } | |
730 | ||
731 | /** | |
49ce9c2c | 732 | * emac_dev_mcast_set - Set multicast address in the EMAC adapter |
a6286ee6 AG |
733 | * @ndev: The DaVinci EMAC network adapter |
734 | * | |
735 | * Set multicast addresses in EMAC adapter | |
736 | * | |
737 | */ | |
738 | static void emac_dev_mcast_set(struct net_device *ndev) | |
739 | { | |
740 | u32 mbp_enable; | |
741 | struct emac_priv *priv = netdev_priv(ndev); | |
742 | ||
743 | mbp_enable = emac_read(EMAC_RXMBPENABLE); | |
744 | if (ndev->flags & IFF_PROMISC) { | |
745 | mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); | |
746 | mbp_enable |= (EMAC_MBP_RXPROMISC); | |
747 | } else { | |
748 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); | |
749 | if ((ndev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 750 | netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { |
a6286ee6 AG |
751 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
752 | emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); | |
d69e0f7e | 753 | } else if (!netdev_mc_empty(ndev)) { |
22bedad3 JP |
754 | struct netdev_hw_addr *ha; |
755 | ||
a6286ee6 AG |
756 | mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); |
757 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); | |
758 | /* program multicast address list into EMAC hardware */ | |
22bedad3 | 759 | netdev_for_each_mc_addr(ha, ndev) { |
a6286ee6 | 760 | emac_add_mcast(priv, EMAC_MULTICAST_ADD, |
22bedad3 | 761 | (u8 *) ha->addr); |
a6286ee6 AG |
762 | } |
763 | } else { | |
764 | mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); | |
765 | emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); | |
766 | } | |
767 | } | |
768 | /* Set mbp config register */ | |
769 | emac_write(EMAC_RXMBPENABLE, mbp_enable); | |
770 | } | |
771 | ||
772 | /************************************************************************* | |
773 | * EMAC Hardware manipulation | |
774 | *************************************************************************/ | |
775 | ||
776 | /** | |
49ce9c2c | 777 | * emac_int_disable - Disable EMAC module interrupt (from adapter) |
a6286ee6 AG |
778 | * @priv: The DaVinci EMAC private adapter structure |
779 | * | |
780 | * Disable EMAC interrupt on the adapter | |
781 | * | |
782 | */ | |
783 | static void emac_int_disable(struct emac_priv *priv) | |
784 | { | |
785 | if (priv->version == EMAC_VERSION_2) { | |
786 | unsigned long flags; | |
787 | ||
788 | local_irq_save(flags); | |
789 | ||
790 | /* Program C0_Int_En to zero to turn off | |
791 | * interrupts to the CPU */ | |
792 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); | |
793 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); | |
794 | /* NOTE: Rx Threshold and Misc interrupts are not disabled */ | |
01a9af36 S |
795 | if (priv->int_disable) |
796 | priv->int_disable(); | |
a6286ee6 | 797 | |
cd2d6d33 TL |
798 | /* NOTE: Rx Threshold and Misc interrupts are not enabled */ |
799 | ||
800 | /* ack rxen only then a new pulse will be generated */ | |
801 | emac_write(EMAC_DM646X_MACEOIVECTOR, | |
802 | EMAC_DM646X_MAC_EOI_C0_RXEN); | |
803 | ||
804 | /* ack txen- only then a new pulse will be generated */ | |
805 | emac_write(EMAC_DM646X_MACEOIVECTOR, | |
806 | EMAC_DM646X_MAC_EOI_C0_TXEN); | |
807 | ||
a6286ee6 AG |
808 | local_irq_restore(flags); |
809 | ||
810 | } else { | |
811 | /* Set DM644x control registers for interrupt control */ | |
812 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); | |
813 | } | |
814 | } | |
815 | ||
816 | /** | |
49ce9c2c | 817 | * emac_int_enable - Enable EMAC module interrupt (from adapter) |
a6286ee6 AG |
818 | * @priv: The DaVinci EMAC private adapter structure |
819 | * | |
820 | * Enable EMAC interrupt on the adapter | |
821 | * | |
822 | */ | |
823 | static void emac_int_enable(struct emac_priv *priv) | |
824 | { | |
825 | if (priv->version == EMAC_VERSION_2) { | |
01a9af36 S |
826 | if (priv->int_enable) |
827 | priv->int_enable(); | |
828 | ||
a6286ee6 AG |
829 | emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); |
830 | emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); | |
831 | ||
832 | /* In addition to turning on interrupt Enable, we need | |
833 | * ack by writing appropriate values to the EOI | |
834 | * register */ | |
835 | ||
836 | /* NOTE: Rx Threshold and Misc interrupts are not enabled */ | |
a6286ee6 AG |
837 | } else { |
838 | /* Set DM644x control registers for interrupt control */ | |
839 | emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); | |
840 | } | |
841 | } | |
842 | ||
843 | /** | |
49ce9c2c | 844 | * emac_irq - EMAC interrupt handler |
a6286ee6 AG |
845 | * @irq: interrupt number |
846 | * @dev_id: EMAC network adapter data structure ptr | |
847 | * | |
848 | * EMAC Interrupt handler - we only schedule NAPI and not process any packets | |
849 | * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function | |
850 | * | |
851 | * Returns interrupt handled condition | |
852 | */ | |
853 | static irqreturn_t emac_irq(int irq, void *dev_id) | |
854 | { | |
855 | struct net_device *ndev = (struct net_device *)dev_id; | |
856 | struct emac_priv *priv = netdev_priv(ndev); | |
857 | ||
858 | ++priv->isr_count; | |
859 | if (likely(netif_running(priv->ndev))) { | |
860 | emac_int_disable(priv); | |
861 | napi_schedule(&priv->napi); | |
862 | } else { | |
863 | /* we are closing down, so dont process anything */ | |
864 | } | |
865 | return IRQ_HANDLED; | |
866 | } | |
867 | ||
3ef0fdb2 CC |
868 | static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) |
869 | { | |
dae2e9f4 | 870 | struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); |
3ef0fdb2 CC |
871 | if (WARN_ON(!skb)) |
872 | return NULL; | |
3ef0fdb2 CC |
873 | skb_reserve(skb, NET_IP_ALIGN); |
874 | return skb; | |
875 | } | |
876 | ||
877 | static void emac_rx_handler(void *token, int len, int status) | |
878 | { | |
879 | struct sk_buff *skb = token; | |
880 | struct net_device *ndev = skb->dev; | |
881 | struct emac_priv *priv = netdev_priv(ndev); | |
882 | struct device *emac_dev = &ndev->dev; | |
883 | int ret; | |
884 | ||
885 | /* free and bail if we are shutting down */ | |
5d697032 | 886 | if (unlikely(!netif_running(ndev))) { |
3ef0fdb2 CC |
887 | dev_kfree_skb_any(skb); |
888 | return; | |
889 | } | |
890 | ||
25985edc | 891 | /* recycle on receive error */ |
3ef0fdb2 CC |
892 | if (status < 0) { |
893 | ndev->stats.rx_errors++; | |
894 | goto recycle; | |
895 | } | |
896 | ||
897 | /* feed received packet up the stack */ | |
898 | skb_put(skb, len); | |
899 | skb->protocol = eth_type_trans(skb, ndev); | |
900 | netif_receive_skb(skb); | |
901 | ndev->stats.rx_bytes += len; | |
902 | ndev->stats.rx_packets++; | |
903 | ||
904 | /* alloc a new packet for receive */ | |
905 | skb = emac_rx_alloc(priv); | |
906 | if (!skb) { | |
907 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
908 | dev_err(emac_dev, "failed rx buffer alloc\n"); | |
909 | return; | |
910 | } | |
911 | ||
912 | recycle: | |
913 | ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, | |
aef614e1 | 914 | skb_tailroom(skb), 0); |
5d697032 CR |
915 | |
916 | WARN_ON(ret == -ENOMEM); | |
917 | if (unlikely(ret < 0)) | |
3ef0fdb2 CC |
918 | dev_kfree_skb_any(skb); |
919 | } | |
920 | ||
921 | static void emac_tx_handler(void *token, int len, int status) | |
922 | { | |
923 | struct sk_buff *skb = token; | |
924 | struct net_device *ndev = skb->dev; | |
925 | ||
fae50823 M |
926 | /* Check whether the queue is stopped due to stalled tx dma, if the |
927 | * queue is stopped then start the queue as we have free desc for tx | |
928 | */ | |
3ef0fdb2 | 929 | if (unlikely(netif_queue_stopped(ndev))) |
7e51cde2 | 930 | netif_wake_queue(ndev); |
3ef0fdb2 CC |
931 | ndev->stats.tx_packets++; |
932 | ndev->stats.tx_bytes += len; | |
933 | dev_kfree_skb_any(skb); | |
934 | } | |
935 | ||
a6286ee6 | 936 | /** |
49ce9c2c | 937 | * emac_dev_xmit - EMAC Transmit function |
a6286ee6 AG |
938 | * @skb: SKB pointer |
939 | * @ndev: The DaVinci EMAC network adapter | |
940 | * | |
941 | * Called by the system to transmit a packet - we queue the packet in | |
942 | * EMAC hardware transmit queue | |
943 | * | |
944 | * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) | |
945 | */ | |
946 | static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) | |
947 | { | |
948 | struct device *emac_dev = &ndev->dev; | |
949 | int ret_code; | |
a6286ee6 AG |
950 | struct emac_priv *priv = netdev_priv(ndev); |
951 | ||
952 | /* If no link, return */ | |
953 | if (unlikely(!priv->link)) { | |
954 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
955 | dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); | |
3ef0fdb2 | 956 | goto fail_tx; |
a6286ee6 AG |
957 | } |
958 | ||
3ef0fdb2 CC |
959 | ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); |
960 | if (unlikely(ret_code < 0)) { | |
961 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
962 | dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); | |
963 | goto fail_tx; | |
964 | } | |
965 | ||
5bf0c191 RC |
966 | skb_tx_timestamp(skb); |
967 | ||
3ef0fdb2 | 968 | ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, |
aef614e1 | 969 | 0); |
a6286ee6 | 970 | if (unlikely(ret_code != 0)) { |
3ef0fdb2 CC |
971 | if (netif_msg_tx_err(priv) && net_ratelimit()) |
972 | dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); | |
973 | goto fail_tx; | |
a6286ee6 AG |
974 | } |
975 | ||
fae50823 M |
976 | /* If there is no more tx desc left free then we need to |
977 | * tell the kernel to stop sending us tx frames. | |
978 | */ | |
75b9b61b | 979 | if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) |
86d8c07f SH |
980 | netif_stop_queue(ndev); |
981 | ||
a6286ee6 | 982 | return NETDEV_TX_OK; |
3ef0fdb2 CC |
983 | |
984 | fail_tx: | |
985 | ndev->stats.tx_dropped++; | |
986 | netif_stop_queue(ndev); | |
987 | return NETDEV_TX_BUSY; | |
a6286ee6 AG |
988 | } |
989 | ||
990 | /** | |
49ce9c2c | 991 | * emac_dev_tx_timeout - EMAC Transmit timeout function |
a6286ee6 AG |
992 | * @ndev: The DaVinci EMAC network adapter |
993 | * | |
994 | * Called when system detects that a skb timeout period has expired | |
995 | * potentially due to a fault in the adapter in not being able to send | |
996 | * it out on the wire. We teardown the TX channel assuming a hardware | |
997 | * error and re-initialize the TX channel for hardware operation | |
998 | * | |
999 | */ | |
1000 | static void emac_dev_tx_timeout(struct net_device *ndev) | |
1001 | { | |
1002 | struct emac_priv *priv = netdev_priv(ndev); | |
1003 | struct device *emac_dev = &ndev->dev; | |
1004 | ||
1005 | if (netif_msg_tx_err(priv)) | |
1006 | dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); | |
1007 | ||
78e8c532 | 1008 | ndev->stats.tx_errors++; |
a6286ee6 | 1009 | emac_int_disable(priv); |
3ef0fdb2 CC |
1010 | cpdma_chan_stop(priv->txchan); |
1011 | cpdma_chan_start(priv->txchan); | |
a6286ee6 AG |
1012 | emac_int_enable(priv); |
1013 | } | |
1014 | ||
a6286ee6 | 1015 | /** |
49ce9c2c | 1016 | * emac_set_type0addr - Set EMAC Type0 mac address |
a6286ee6 AG |
1017 | * @priv: The DaVinci EMAC private adapter structure |
1018 | * @ch: RX channel number | |
1019 | * @mac_addr: MAC address to set in device | |
1020 | * | |
1021 | * Called internally to set Type0 mac address of the adapter (Device) | |
1022 | * | |
1023 | * Returns success (0) or appropriate error code (none as of now) | |
1024 | */ | |
1025 | static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1026 | { | |
1027 | u32 val; | |
1028 | val = ((mac_addr[5] << 8) | (mac_addr[4])); | |
1029 | emac_write(EMAC_MACSRCADDRLO, val); | |
1030 | ||
1031 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1032 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1033 | emac_write(EMAC_MACSRCADDRHI, val); | |
1034 | val = emac_read(EMAC_RXUNICASTSET); | |
1035 | val |= BIT(ch); | |
1036 | emac_write(EMAC_RXUNICASTSET, val); | |
1037 | val = emac_read(EMAC_RXUNICASTCLEAR); | |
1038 | val &= ~BIT(ch); | |
1039 | emac_write(EMAC_RXUNICASTCLEAR, val); | |
1040 | } | |
1041 | ||
1042 | /** | |
49ce9c2c | 1043 | * emac_set_type1addr - Set EMAC Type1 mac address |
a6286ee6 AG |
1044 | * @priv: The DaVinci EMAC private adapter structure |
1045 | * @ch: RX channel number | |
1046 | * @mac_addr: MAC address to set in device | |
1047 | * | |
1048 | * Called internally to set Type1 mac address of the adapter (Device) | |
1049 | * | |
1050 | * Returns success (0) or appropriate error code (none as of now) | |
1051 | */ | |
1052 | static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1053 | { | |
1054 | u32 val; | |
1055 | emac_write(EMAC_MACINDEX, ch); | |
1056 | val = ((mac_addr[5] << 8) | mac_addr[4]); | |
1057 | emac_write(EMAC_MACADDRLO, val); | |
1058 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1059 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1060 | emac_write(EMAC_MACADDRHI, val); | |
1061 | emac_set_type0addr(priv, ch, mac_addr); | |
1062 | } | |
1063 | ||
1064 | /** | |
49ce9c2c | 1065 | * emac_set_type2addr - Set EMAC Type2 mac address |
a6286ee6 AG |
1066 | * @priv: The DaVinci EMAC private adapter structure |
1067 | * @ch: RX channel number | |
1068 | * @mac_addr: MAC address to set in device | |
1069 | * @index: index into RX address entries | |
1070 | * @match: match parameter for RX address matching logic | |
1071 | * | |
1072 | * Called internally to set Type2 mac address of the adapter (Device) | |
1073 | * | |
1074 | * Returns success (0) or appropriate error code (none as of now) | |
1075 | */ | |
1076 | static void emac_set_type2addr(struct emac_priv *priv, u32 ch, | |
1077 | char *mac_addr, int index, int match) | |
1078 | { | |
1079 | u32 val; | |
1080 | emac_write(EMAC_MACINDEX, index); | |
1081 | val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ | |
1082 | (mac_addr[1] << 8) | (mac_addr[0])); | |
1083 | emac_write(EMAC_MACADDRHI, val); | |
1084 | val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ | |
1085 | (match << 19) | BIT(20)); | |
1086 | emac_write(EMAC_MACADDRLO, val); | |
1087 | emac_set_type0addr(priv, ch, mac_addr); | |
1088 | } | |
1089 | ||
1090 | /** | |
49ce9c2c | 1091 | * emac_setmac - Set mac address in the adapter (internal function) |
a6286ee6 AG |
1092 | * @priv: The DaVinci EMAC private adapter structure |
1093 | * @ch: RX channel number | |
1094 | * @mac_addr: MAC address to set in device | |
1095 | * | |
1096 | * Called internally to set the mac address of the adapter (Device) | |
1097 | * | |
1098 | * Returns success (0) or appropriate error code (none as of now) | |
1099 | */ | |
1100 | static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) | |
1101 | { | |
1102 | struct device *emac_dev = &priv->ndev->dev; | |
1103 | ||
1104 | if (priv->rx_addr_type == 0) { | |
1105 | emac_set_type0addr(priv, ch, mac_addr); | |
1106 | } else if (priv->rx_addr_type == 1) { | |
1107 | u32 cnt; | |
1108 | for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) | |
1109 | emac_set_type1addr(priv, ch, mac_addr); | |
1110 | } else if (priv->rx_addr_type == 2) { | |
1111 | emac_set_type2addr(priv, ch, mac_addr, ch, 1); | |
1112 | emac_set_type0addr(priv, ch, mac_addr); | |
1113 | } else { | |
1114 | if (netif_msg_drv(priv)) | |
1115 | dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | /** | |
49ce9c2c | 1120 | * emac_dev_setmac_addr - Set mac address in the adapter |
a6286ee6 AG |
1121 | * @ndev: The DaVinci EMAC network adapter |
1122 | * @addr: MAC address to set in device | |
1123 | * | |
1124 | * Called by the system to set the mac address of the adapter (Device) | |
1125 | * | |
1126 | * Returns success (0) or appropriate error code (none as of now) | |
1127 | */ | |
1128 | static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) | |
1129 | { | |
1130 | struct emac_priv *priv = netdev_priv(ndev); | |
a6286ee6 AG |
1131 | struct device *emac_dev = &priv->ndev->dev; |
1132 | struct sockaddr *sa = addr; | |
a6286ee6 | 1133 | |
64c8165b | 1134 | if (!is_valid_ether_addr(sa->sa_data)) |
504f9b5a | 1135 | return -EADDRNOTAVAIL; |
64c8165b | 1136 | |
a6286ee6 AG |
1137 | /* Store mac addr in priv and rx channel and set it in EMAC hw */ |
1138 | memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); | |
a6286ee6 | 1139 | memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); |
64c8165b | 1140 | |
64c8165b PB |
1141 | /* MAC address is configured only after the interface is enabled. */ |
1142 | if (netif_running(ndev)) { | |
3ef0fdb2 | 1143 | emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); |
64c8165b | 1144 | } |
a6286ee6 AG |
1145 | |
1146 | if (netif_msg_drv(priv)) | |
5c726166 C |
1147 | dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", |
1148 | priv->mac_addr); | |
a6286ee6 AG |
1149 | |
1150 | return 0; | |
1151 | } | |
1152 | ||
a6286ee6 | 1153 | /** |
49ce9c2c | 1154 | * emac_hw_enable - Enable EMAC hardware for packet transmission/reception |
a6286ee6 AG |
1155 | * @priv: The DaVinci EMAC private adapter structure |
1156 | * | |
1157 | * Enables EMAC hardware for packet processing - enables PHY, enables RX | |
1158 | * for packet reception and enables device interrupts and then NAPI | |
1159 | * | |
1160 | * Returns success (0) or appropriate error code (none right now) | |
1161 | */ | |
1162 | static int emac_hw_enable(struct emac_priv *priv) | |
1163 | { | |
3ef0fdb2 | 1164 | u32 val, mbp_enable, mac_control; |
a6286ee6 AG |
1165 | |
1166 | /* Soft reset */ | |
1167 | emac_write(EMAC_SOFTRESET, 1); | |
1168 | while (emac_read(EMAC_SOFTRESET)) | |
1169 | cpu_relax(); | |
1170 | ||
1171 | /* Disable interrupt & Set pacing for more interrupts initially */ | |
1172 | emac_int_disable(priv); | |
1173 | ||
1174 | /* Full duplex enable bit set when auto negotiation happens */ | |
1175 | mac_control = | |
1176 | (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | | |
1177 | ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | | |
1178 | ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | | |
1179 | ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); | |
1180 | emac_write(EMAC_MACCONTROL, mac_control); | |
1181 | ||
1182 | mbp_enable = | |
1183 | (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | | |
1184 | ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | | |
1185 | ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | | |
1186 | ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | | |
1187 | ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | | |
1188 | ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | | |
1189 | ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | | |
1190 | ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ | |
1191 | EMAC_RXMBP_PROMCH_SHIFT) | | |
1192 | ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | | |
1193 | ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ | |
1194 | EMAC_RXMBP_BROADCH_SHIFT) | | |
1195 | ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | | |
1196 | ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ | |
1197 | EMAC_RXMBP_MULTICH_SHIFT)); | |
1198 | emac_write(EMAC_RXMBPENABLE, mbp_enable); | |
1199 | emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & | |
1200 | EMAC_RX_MAX_LEN_MASK)); | |
1201 | emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & | |
1202 | EMAC_RX_BUFFER_OFFSET_MASK)); | |
1203 | emac_write(EMAC_RXFILTERLOWTHRESH, 0); | |
1204 | emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); | |
1205 | priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; | |
1206 | ||
a6286ee6 AG |
1207 | emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); |
1208 | ||
3ef0fdb2 | 1209 | emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); |
a6286ee6 AG |
1210 | |
1211 | /* Enable MII */ | |
1212 | val = emac_read(EMAC_MACCONTROL); | |
69ef9694 | 1213 | val |= (EMAC_MACCONTROL_GMIIEN); |
a6286ee6 AG |
1214 | emac_write(EMAC_MACCONTROL, val); |
1215 | ||
1216 | /* Enable NAPI and interrupts */ | |
1217 | napi_enable(&priv->napi); | |
1218 | emac_int_enable(priv); | |
1219 | return 0; | |
1220 | ||
1221 | } | |
1222 | ||
1223 | /** | |
49ce9c2c | 1224 | * emac_poll - EMAC NAPI Poll function |
a6286ee6 AG |
1225 | * @ndev: The DaVinci EMAC network adapter |
1226 | * @budget: Number of receive packets to process (as told by NAPI layer) | |
1227 | * | |
1228 | * NAPI Poll function implemented to process packets as per budget. We check | |
1229 | * the type of interrupt on the device and accordingly call the TX or RX | |
1230 | * packet processing functions. We follow the budget for RX processing and | |
1231 | * also put a cap on number of TX pkts processed through config param. The | |
1232 | * NAPI schedule function is called if more packets pending. | |
1233 | * | |
1234 | * Returns number of packets received (in most cases; else TX pkts - rarely) | |
1235 | */ | |
1236 | static int emac_poll(struct napi_struct *napi, int budget) | |
1237 | { | |
1238 | unsigned int mask; | |
1239 | struct emac_priv *priv = container_of(napi, struct emac_priv, napi); | |
1240 | struct net_device *ndev = priv->ndev; | |
1241 | struct device *emac_dev = &ndev->dev; | |
1242 | u32 status = 0; | |
3725b1fe | 1243 | u32 num_tx_pkts = 0, num_rx_pkts = 0; |
a6286ee6 | 1244 | |
a6286ee6 AG |
1245 | /* Check interrupt vectors and call packet processing */ |
1246 | status = emac_read(EMAC_MACINVECTOR); | |
1247 | ||
1248 | mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; | |
1249 | ||
1250 | if (priv->version == EMAC_VERSION_2) | |
1251 | mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; | |
1252 | ||
1253 | if (status & mask) { | |
3ef0fdb2 CC |
1254 | num_tx_pkts = cpdma_chan_process(priv->txchan, |
1255 | EMAC_DEF_TX_MAX_SERVICE); | |
a6286ee6 AG |
1256 | } /* TX processing */ |
1257 | ||
a6286ee6 AG |
1258 | mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; |
1259 | ||
1260 | if (priv->version == EMAC_VERSION_2) | |
1261 | mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; | |
1262 | ||
1263 | if (status & mask) { | |
3ef0fdb2 | 1264 | num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); |
a6286ee6 AG |
1265 | } /* RX processing */ |
1266 | ||
43c2ed8e S |
1267 | mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; |
1268 | if (priv->version == EMAC_VERSION_2) | |
1269 | mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; | |
1270 | ||
1271 | if (unlikely(status & mask)) { | |
a6286ee6 AG |
1272 | u32 ch, cause; |
1273 | dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); | |
1274 | netif_stop_queue(ndev); | |
1275 | napi_disable(&priv->napi); | |
1276 | ||
1277 | status = emac_read(EMAC_MACSTATUS); | |
1278 | cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> | |
1279 | EMAC_MACSTATUS_TXERRCODE_SHIFT); | |
1280 | if (cause) { | |
1281 | ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> | |
1282 | EMAC_MACSTATUS_TXERRCH_SHIFT); | |
1283 | if (net_ratelimit()) { | |
1284 | dev_err(emac_dev, "TX Host error %s on ch=%d\n", | |
1285 | &emac_txhost_errcodes[cause][0], ch); | |
1286 | } | |
1287 | } | |
1288 | cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> | |
1289 | EMAC_MACSTATUS_RXERRCODE_SHIFT); | |
1290 | if (cause) { | |
1291 | ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> | |
1292 | EMAC_MACSTATUS_RXERRCH_SHIFT); | |
1293 | if (netif_msg_hw(priv) && net_ratelimit()) | |
1294 | dev_err(emac_dev, "RX Host error %s on ch=%d\n", | |
1295 | &emac_rxhost_errcodes[cause][0], ch); | |
1296 | } | |
3725b1fe S |
1297 | } else if (num_rx_pkts < budget) { |
1298 | napi_complete(napi); | |
1299 | emac_int_enable(priv); | |
1300 | } | |
a6286ee6 | 1301 | |
3725b1fe | 1302 | return num_rx_pkts; |
a6286ee6 AG |
1303 | } |
1304 | ||
1305 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1306 | /** | |
49ce9c2c | 1307 | * emac_poll_controller - EMAC Poll controller function |
a6286ee6 AG |
1308 | * @ndev: The DaVinci EMAC network adapter |
1309 | * | |
1310 | * Polled functionality used by netconsole and others in non interrupt mode | |
1311 | * | |
1312 | */ | |
e052a589 | 1313 | static void emac_poll_controller(struct net_device *ndev) |
a6286ee6 AG |
1314 | { |
1315 | struct emac_priv *priv = netdev_priv(ndev); | |
1316 | ||
1317 | emac_int_disable(priv); | |
c8ee5538 | 1318 | emac_irq(ndev->irq, ndev); |
a6286ee6 AG |
1319 | emac_int_enable(priv); |
1320 | } | |
1321 | #endif | |
1322 | ||
a6286ee6 AG |
1323 | static void emac_adjust_link(struct net_device *ndev) |
1324 | { | |
1325 | struct emac_priv *priv = netdev_priv(ndev); | |
c332177e | 1326 | struct phy_device *phydev = ndev->phydev; |
a6286ee6 AG |
1327 | unsigned long flags; |
1328 | int new_state = 0; | |
1329 | ||
1330 | spin_lock_irqsave(&priv->lock, flags); | |
1331 | ||
1332 | if (phydev->link) { | |
1333 | /* check the mode of operation - full/half duplex */ | |
1334 | if (phydev->duplex != priv->duplex) { | |
1335 | new_state = 1; | |
1336 | priv->duplex = phydev->duplex; | |
1337 | } | |
1338 | if (phydev->speed != priv->speed) { | |
1339 | new_state = 1; | |
1340 | priv->speed = phydev->speed; | |
1341 | } | |
1342 | if (!priv->link) { | |
1343 | new_state = 1; | |
1344 | priv->link = 1; | |
1345 | } | |
1346 | ||
1347 | } else if (priv->link) { | |
1348 | new_state = 1; | |
1349 | priv->link = 0; | |
1350 | priv->speed = 0; | |
1351 | priv->duplex = ~0; | |
1352 | } | |
1353 | if (new_state) { | |
1354 | emac_update_phystatus(priv); | |
c332177e | 1355 | phy_print_status(ndev->phydev); |
a6286ee6 AG |
1356 | } |
1357 | ||
1358 | spin_unlock_irqrestore(&priv->lock, flags); | |
1359 | } | |
1360 | ||
1361 | /************************************************************************* | |
1362 | * Linux Driver Model | |
1363 | *************************************************************************/ | |
1364 | ||
1365 | /** | |
49ce9c2c | 1366 | * emac_devioctl - EMAC adapter ioctl |
a6286ee6 AG |
1367 | * @ndev: The DaVinci EMAC network adapter |
1368 | * @ifrq: request parameter | |
1369 | * @cmd: command parameter | |
1370 | * | |
1371 | * EMAC driver ioctl function | |
1372 | * | |
1373 | * Returns success(0) or appropriate error code | |
1374 | */ | |
1375 | static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) | |
1376 | { | |
a6286ee6 AG |
1377 | if (!(netif_running(ndev))) |
1378 | return -EINVAL; | |
1379 | ||
1380 | /* TODO: Add phy read and write and private statistics get feature */ | |
1381 | ||
c332177e PR |
1382 | if (ndev->phydev) |
1383 | return phy_mii_ioctl(ndev->phydev, ifrq, cmd); | |
62522ef3 NA |
1384 | else |
1385 | return -EOPNOTSUPP; | |
a6286ee6 AG |
1386 | } |
1387 | ||
5d69e007 CC |
1388 | static int match_first_device(struct device *dev, void *data) |
1389 | { | |
1ab8be4a | 1390 | return !strncmp(dev_name(dev), "davinci_mdio", 12); |
5d69e007 CC |
1391 | } |
1392 | ||
a6286ee6 | 1393 | /** |
49ce9c2c | 1394 | * emac_dev_open - EMAC device open |
a6286ee6 AG |
1395 | * @ndev: The DaVinci EMAC network adapter |
1396 | * | |
1397 | * Called when system wants to start the interface. We init TX/RX channels | |
1398 | * and enable the hardware for packet reception/transmission and start the | |
1399 | * network queue. | |
1400 | * | |
1401 | * Returns 0 for a successful open, or appropriate error code | |
1402 | */ | |
1403 | static int emac_dev_open(struct net_device *ndev) | |
1404 | { | |
1405 | struct device *emac_dev = &ndev->dev; | |
3ef0fdb2 | 1406 | u32 cnt; |
a6286ee6 | 1407 | struct resource *res; |
33b7107f | 1408 | int q, m, ret; |
cd11cf50 | 1409 | int res_num = 0, irq_num = 0; |
a6286ee6 | 1410 | int i = 0; |
a6286ee6 | 1411 | struct emac_priv *priv = netdev_priv(ndev); |
c332177e | 1412 | struct phy_device *phydev = NULL; |
6bed0118 | 1413 | struct device *phy = NULL; |
a6286ee6 | 1414 | |
b5133e7a TL |
1415 | ret = pm_runtime_get_sync(&priv->pdev->dev); |
1416 | if (ret < 0) { | |
1417 | pm_runtime_put_noidle(&priv->pdev->dev); | |
1418 | dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", | |
1419 | __func__, ret); | |
1420 | return ret; | |
1421 | } | |
3ba97381 | 1422 | |
a6286ee6 | 1423 | netif_carrier_off(ndev); |
4d27b877 | 1424 | for (cnt = 0; cnt < ETH_ALEN; cnt++) |
a6286ee6 AG |
1425 | ndev->dev_addr[cnt] = priv->mac_addr[cnt]; |
1426 | ||
1427 | /* Configuration items */ | |
1428 | priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; | |
1429 | ||
a6286ee6 AG |
1430 | priv->mac_hash1 = 0; |
1431 | priv->mac_hash2 = 0; | |
1432 | emac_write(EMAC_MACHASH1, 0); | |
1433 | emac_write(EMAC_MACHASH2, 0); | |
1434 | ||
3ef0fdb2 CC |
1435 | for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { |
1436 | struct sk_buff *skb = emac_rx_alloc(priv); | |
1437 | ||
1438 | if (!skb) | |
1439 | break; | |
1440 | ||
1441 | ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, | |
aef614e1 | 1442 | skb_tailroom(skb), 0); |
3ef0fdb2 CC |
1443 | if (WARN_ON(ret < 0)) |
1444 | break; | |
a6286ee6 AG |
1445 | } |
1446 | ||
1447 | /* Request IRQ */ | |
cd11cf50 CR |
1448 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, |
1449 | res_num))) { | |
1450 | for (irq_num = res->start; irq_num <= res->end; irq_num++) { | |
cd11cf50 CR |
1451 | if (request_irq(irq_num, emac_irq, 0, ndev->name, |
1452 | ndev)) { | |
1453 | dev_err(emac_dev, | |
1454 | "DaVinci EMAC: request_irq() failed\n"); | |
1455 | ret = -EBUSY; | |
a6286ee6 | 1456 | |
a6286ee6 | 1457 | goto rollback; |
cd11cf50 | 1458 | } |
a6286ee6 | 1459 | } |
cd11cf50 | 1460 | res_num++; |
a6286ee6 | 1461 | } |
cd11cf50 CR |
1462 | /* prepare counters for rollback in case of an error */ |
1463 | res_num--; | |
1464 | irq_num--; | |
a6286ee6 AG |
1465 | |
1466 | /* Start/Enable EMAC hardware */ | |
1467 | emac_hw_enable(priv); | |
1468 | ||
84da2658 S |
1469 | /* Enable Interrupt pacing if configured */ |
1470 | if (priv->coal_intvl != 0) { | |
1471 | struct ethtool_coalesce coal; | |
1472 | ||
1473 | coal.rx_coalesce_usecs = (priv->coal_intvl << 4); | |
1474 | emac_set_coalesce(ndev, &coal); | |
1475 | } | |
1476 | ||
3ef0fdb2 CC |
1477 | cpdma_ctlr_start(priv->dma); |
1478 | ||
1d82ffa6 | 1479 | if (priv->phy_node) { |
c332177e PR |
1480 | phydev = of_phy_connect(ndev, priv->phy_node, |
1481 | &emac_adjust_link, 0, 0); | |
1482 | if (!phydev) { | |
1d82ffa6 TL |
1483 | dev_err(emac_dev, "could not connect to phy %s\n", |
1484 | priv->phy_node->full_name); | |
1485 | ret = -ENODEV; | |
1486 | goto err; | |
1487 | } | |
1488 | } | |
1489 | ||
5d69e007 | 1490 | /* use the first phy on the bus if pdata did not give us a phy id */ |
c332177e | 1491 | if (!phydev && !priv->phy_id) { |
5d69e007 CC |
1492 | phy = bus_find_device(&mdio_bus_type, NULL, NULL, |
1493 | match_first_device); | |
6bed0118 | 1494 | if (phy) { |
5d69e007 | 1495 | priv->phy_id = dev_name(phy); |
6bed0118 JH |
1496 | if (!priv->phy_id || !*priv->phy_id) |
1497 | put_device(phy); | |
1498 | } | |
5d69e007 | 1499 | } |
a6286ee6 | 1500 | |
c332177e PR |
1501 | if (!phydev && priv->phy_id && *priv->phy_id) { |
1502 | phydev = phy_connect(ndev, priv->phy_id, | |
1503 | &emac_adjust_link, | |
1504 | PHY_INTERFACE_MODE_MII); | |
6bed0118 | 1505 | put_device(phy); /* reference taken by bus_find_device */ |
c332177e | 1506 | if (IS_ERR(phydev)) { |
5d69e007 CC |
1507 | dev_err(emac_dev, "could not connect to phy %s\n", |
1508 | priv->phy_id); | |
c332177e | 1509 | ret = PTR_ERR(phydev); |
3ba97381 | 1510 | goto err; |
a6286ee6 AG |
1511 | } |
1512 | ||
1513 | priv->link = 0; | |
1514 | priv->speed = 0; | |
1515 | priv->duplex = ~0; | |
1516 | ||
c332177e | 1517 | phy_attached_info(phydev); |
1d82ffa6 TL |
1518 | } |
1519 | ||
c332177e | 1520 | if (!phydev) { |
a6286ee6 | 1521 | /* No PHY , fix the link, speed and duplex settings */ |
5d69e007 | 1522 | dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); |
a6286ee6 AG |
1523 | priv->link = 1; |
1524 | priv->speed = SPEED_100; | |
1525 | priv->duplex = DUPLEX_FULL; | |
1526 | emac_update_phystatus(priv); | |
1527 | } | |
1528 | ||
a6286ee6 AG |
1529 | if (netif_msg_drv(priv)) |
1530 | dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); | |
1531 | ||
c332177e PR |
1532 | if (phydev) |
1533 | phy_start(phydev); | |
a6286ee6 AG |
1534 | |
1535 | return 0; | |
1536 | ||
cd11cf50 CR |
1537 | err: |
1538 | emac_int_disable(priv); | |
1539 | napi_disable(&priv->napi); | |
33b7107f | 1540 | |
cd11cf50 CR |
1541 | rollback: |
1542 | for (q = res_num; q >= 0; q--) { | |
1543 | res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q); | |
1544 | /* at the first iteration, irq_num is already set to the | |
1545 | * right value | |
1546 | */ | |
1547 | if (q != res_num) | |
1548 | irq_num = res->end; | |
1549 | ||
1550 | for (m = irq_num; m >= res->start; m--) | |
33b7107f | 1551 | free_irq(m, ndev); |
33b7107f | 1552 | } |
cd11cf50 | 1553 | cpdma_ctlr_stop(priv->dma); |
3ba97381 MG |
1554 | pm_runtime_put(&priv->pdev->dev); |
1555 | return ret; | |
a6286ee6 AG |
1556 | } |
1557 | ||
1558 | /** | |
49ce9c2c | 1559 | * emac_dev_stop - EMAC device stop |
a6286ee6 AG |
1560 | * @ndev: The DaVinci EMAC network adapter |
1561 | * | |
1562 | * Called when system wants to stop or down the interface. We stop the network | |
1563 | * queue, disable interrupts and cleanup TX/RX channels. | |
1564 | * | |
1565 | * We return the statistics in net_device_stats structure pulled from emac | |
1566 | */ | |
1567 | static int emac_dev_stop(struct net_device *ndev) | |
1568 | { | |
33b7107f CR |
1569 | struct resource *res; |
1570 | int i = 0; | |
1571 | int irq_num; | |
a6286ee6 AG |
1572 | struct emac_priv *priv = netdev_priv(ndev); |
1573 | struct device *emac_dev = &ndev->dev; | |
1574 | ||
1575 | /* inform the upper layers. */ | |
1576 | netif_stop_queue(ndev); | |
1577 | napi_disable(&priv->napi); | |
1578 | ||
1579 | netif_carrier_off(ndev); | |
1580 | emac_int_disable(priv); | |
3ef0fdb2 | 1581 | cpdma_ctlr_stop(priv->dma); |
a6286ee6 AG |
1582 | emac_write(EMAC_SOFTRESET, 1); |
1583 | ||
c332177e PR |
1584 | if (ndev->phydev) |
1585 | phy_disconnect(ndev->phydev); | |
a6286ee6 | 1586 | |
33b7107f CR |
1587 | /* Free IRQ */ |
1588 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { | |
1589 | for (irq_num = res->start; irq_num <= res->end; irq_num++) | |
1590 | free_irq(irq_num, priv->ndev); | |
1591 | i++; | |
1592 | } | |
1593 | ||
a6286ee6 AG |
1594 | if (netif_msg_drv(priv)) |
1595 | dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); | |
1596 | ||
3ba97381 | 1597 | pm_runtime_put(&priv->pdev->dev); |
a6286ee6 AG |
1598 | return 0; |
1599 | } | |
1600 | ||
1601 | /** | |
49ce9c2c | 1602 | * emac_dev_getnetstats - EMAC get statistics function |
a6286ee6 AG |
1603 | * @ndev: The DaVinci EMAC network adapter |
1604 | * | |
1605 | * Called when system wants to get statistics from the device. | |
1606 | * | |
1607 | * We return the statistics in net_device_stats structure pulled from emac | |
1608 | */ | |
1609 | static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) | |
1610 | { | |
1611 | struct emac_priv *priv = netdev_priv(ndev); | |
0fe7463a S |
1612 | u32 mac_control; |
1613 | u32 stats_clear_mask; | |
b5133e7a TL |
1614 | int err; |
1615 | ||
1616 | err = pm_runtime_get_sync(&priv->pdev->dev); | |
1617 | if (err < 0) { | |
1618 | pm_runtime_put_noidle(&priv->pdev->dev); | |
1619 | dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", | |
1620 | __func__, err); | |
1621 | return &ndev->stats; | |
1622 | } | |
a6286ee6 AG |
1623 | |
1624 | /* update emac hardware stats and reset the registers*/ | |
1625 | ||
0fe7463a S |
1626 | mac_control = emac_read(EMAC_MACCONTROL); |
1627 | ||
1628 | if (mac_control & EMAC_MACCONTROL_GMIIEN) | |
1629 | stats_clear_mask = EMAC_STATS_CLR_MASK; | |
1630 | else | |
1631 | stats_clear_mask = 0; | |
1632 | ||
78e8c532 | 1633 | ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); |
0fe7463a | 1634 | emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); |
a6286ee6 | 1635 | |
78e8c532 | 1636 | ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + |
a6286ee6 AG |
1637 | emac_read(EMAC_TXSINGLECOLL) + |
1638 | emac_read(EMAC_TXMULTICOLL)); | |
0fe7463a S |
1639 | emac_write(EMAC_TXCOLLISION, stats_clear_mask); |
1640 | emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); | |
1641 | emac_write(EMAC_TXMULTICOLL, stats_clear_mask); | |
a6286ee6 | 1642 | |
78e8c532 | 1643 | ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + |
a6286ee6 AG |
1644 | emac_read(EMAC_RXJABBER) + |
1645 | emac_read(EMAC_RXUNDERSIZED)); | |
0fe7463a S |
1646 | emac_write(EMAC_RXOVERSIZED, stats_clear_mask); |
1647 | emac_write(EMAC_RXJABBER, stats_clear_mask); | |
1648 | emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); | |
a6286ee6 | 1649 | |
78e8c532 | 1650 | ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + |
a6286ee6 | 1651 | emac_read(EMAC_RXMOFOVERRUNS)); |
0fe7463a S |
1652 | emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); |
1653 | emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); | |
a6286ee6 | 1654 | |
78e8c532 | 1655 | ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); |
0fe7463a | 1656 | emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); |
a6286ee6 | 1657 | |
78e8c532 | 1658 | ndev->stats.tx_carrier_errors += |
a6286ee6 | 1659 | emac_read(EMAC_TXCARRIERSENSE); |
0fe7463a | 1660 | emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); |
a6286ee6 | 1661 | |
60aeba23 | 1662 | ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); |
0fe7463a | 1663 | emac_write(EMAC_TXUNDERRUN, stats_clear_mask); |
a6286ee6 | 1664 | |
b5133e7a TL |
1665 | pm_runtime_put(&priv->pdev->dev); |
1666 | ||
78e8c532 | 1667 | return &ndev->stats; |
a6286ee6 AG |
1668 | } |
1669 | ||
1670 | static const struct net_device_ops emac_netdev_ops = { | |
1671 | .ndo_open = emac_dev_open, | |
1672 | .ndo_stop = emac_dev_stop, | |
1673 | .ndo_start_xmit = emac_dev_xmit, | |
afc4b13d | 1674 | .ndo_set_rx_mode = emac_dev_mcast_set, |
a6286ee6 AG |
1675 | .ndo_set_mac_address = emac_dev_setmac_addr, |
1676 | .ndo_do_ioctl = emac_devioctl, | |
1677 | .ndo_tx_timeout = emac_dev_tx_timeout, | |
1678 | .ndo_get_stats = emac_dev_getnetstats, | |
1679 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1680 | .ndo_poll_controller = emac_poll_controller, | |
1681 | #endif | |
1682 | }; | |
1683 | ||
dd0df47d TL |
1684 | static const struct of_device_id davinci_emac_of_match[]; |
1685 | ||
151328c8 LP |
1686 | static struct emac_platform_data * |
1687 | davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) | |
42f59967 HS |
1688 | { |
1689 | struct device_node *np; | |
dd0df47d TL |
1690 | const struct of_device_id *match; |
1691 | const struct emac_platform_data *auxdata; | |
42f59967 HS |
1692 | struct emac_platform_data *pdata = NULL; |
1693 | const u8 *mac_addr; | |
42f59967 | 1694 | |
151328c8 | 1695 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) |
20e6f33b | 1696 | return dev_get_platdata(&pdev->dev); |
151328c8 LP |
1697 | |
1698 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1699 | if (!pdata) | |
1700 | return NULL; | |
42f59967 HS |
1701 | |
1702 | np = pdev->dev.of_node; | |
151328c8 | 1703 | pdata->version = EMAC_VERSION_2; |
42f59967 HS |
1704 | |
1705 | if (!is_valid_ether_addr(pdata->mac_addr)) { | |
1706 | mac_addr = of_get_mac_address(np); | |
1707 | if (mac_addr) | |
9120bd6e | 1708 | ether_addr_copy(pdata->mac_addr, mac_addr); |
42f59967 HS |
1709 | } |
1710 | ||
151328c8 LP |
1711 | of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", |
1712 | &pdata->ctrl_reg_offset); | |
42f59967 | 1713 | |
151328c8 LP |
1714 | of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", |
1715 | &pdata->ctrl_mod_reg_offset); | |
42f59967 | 1716 | |
151328c8 LP |
1717 | of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", |
1718 | &pdata->ctrl_ram_offset); | |
42f59967 | 1719 | |
151328c8 LP |
1720 | of_property_read_u32(np, "ti,davinci-ctrl-ram-size", |
1721 | &pdata->ctrl_ram_size); | |
42f59967 | 1722 | |
151328c8 | 1723 | of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); |
42f59967 | 1724 | |
151328c8 | 1725 | pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); |
42f59967 HS |
1726 | |
1727 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); | |
1bb6aa56 NA |
1728 | if (!priv->phy_node) { |
1729 | if (!of_phy_is_fixed_link(np)) | |
1730 | pdata->phy_id = NULL; | |
1731 | else if (of_phy_register_fixed_link(np) >= 0) | |
1732 | priv->phy_node = of_node_get(np); | |
1733 | } | |
dd0df47d TL |
1734 | |
1735 | auxdata = pdev->dev.platform_data; | |
1736 | if (auxdata) { | |
1737 | pdata->interrupt_enable = auxdata->interrupt_enable; | |
1738 | pdata->interrupt_disable = auxdata->interrupt_disable; | |
1739 | } | |
1740 | ||
1741 | match = of_match_device(davinci_emac_of_match, &pdev->dev); | |
1742 | if (match && match->data) { | |
1743 | auxdata = match->data; | |
1744 | pdata->version = auxdata->version; | |
1745 | pdata->hw_ram_addr = auxdata->hw_ram_addr; | |
1746 | } | |
42f59967 | 1747 | |
42f59967 HS |
1748 | return pdata; |
1749 | } | |
151328c8 | 1750 | |
9120bd6e TL |
1751 | static int davinci_emac_try_get_mac(struct platform_device *pdev, |
1752 | int instance, u8 *mac_addr) | |
1753 | { | |
9120bd6e | 1754 | if (!pdev->dev.of_node) |
b6745f6e M |
1755 | return -EINVAL; |
1756 | ||
1757 | return ti_cm_get_macid(&pdev->dev, instance, mac_addr); | |
9120bd6e TL |
1758 | } |
1759 | ||
a6286ee6 | 1760 | /** |
49ce9c2c | 1761 | * davinci_emac_probe - EMAC device probe |
a6286ee6 AG |
1762 | * @pdev: The DaVinci EMAC device that we are removing |
1763 | * | |
1764 | * Called when probing for emac devicesr. We get details of instances and | |
1765 | * resource information from platform init and register a network device | |
1766 | * and allocate resources necessary for driver to perform | |
1767 | */ | |
e38921d4 | 1768 | static int davinci_emac_probe(struct platform_device *pdev) |
a6286ee6 AG |
1769 | { |
1770 | int rc = 0; | |
a1594321 | 1771 | struct resource *res, *res_ctrl; |
a6286ee6 AG |
1772 | struct net_device *ndev; |
1773 | struct emac_priv *priv; | |
6892b41d | 1774 | unsigned long hw_ram_addr; |
a6286ee6 | 1775 | struct emac_platform_data *pdata; |
3ef0fdb2 | 1776 | struct cpdma_params dma_params; |
3ba97381 MG |
1777 | struct clk *emac_clk; |
1778 | unsigned long emac_bus_frequency; | |
1779 | ||
a6286ee6 AG |
1780 | |
1781 | /* obtain emac clock from kernel */ | |
b8092861 | 1782 | emac_clk = devm_clk_get(&pdev->dev, NULL); |
a6286ee6 | 1783 | if (IS_ERR(emac_clk)) { |
240b2628 | 1784 | dev_err(&pdev->dev, "failed to get EMAC clock\n"); |
a6286ee6 AG |
1785 | return -EBUSY; |
1786 | } | |
1787 | emac_bus_frequency = clk_get_rate(emac_clk); | |
0f537273 | 1788 | devm_clk_put(&pdev->dev, emac_clk); |
3ba97381 | 1789 | |
a6286ee6 AG |
1790 | /* TODO: Probe PHY here if possible */ |
1791 | ||
1792 | ndev = alloc_etherdev(sizeof(struct emac_priv)); | |
b8092861 SN |
1793 | if (!ndev) |
1794 | return -ENOMEM; | |
a6286ee6 AG |
1795 | |
1796 | platform_set_drvdata(pdev, ndev); | |
1797 | priv = netdev_priv(ndev); | |
1798 | priv->pdev = pdev; | |
1799 | priv->ndev = ndev; | |
1800 | priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); | |
1801 | ||
a6286ee6 AG |
1802 | spin_lock_init(&priv->lock); |
1803 | ||
42f59967 | 1804 | pdata = davinci_emac_of_get_pdata(pdev, priv); |
a6286ee6 | 1805 | if (!pdata) { |
240b2628 | 1806 | dev_err(&pdev->dev, "no platform data\n"); |
b722dbf1 | 1807 | rc = -ENODEV; |
b8092861 | 1808 | goto no_pdata; |
a6286ee6 AG |
1809 | } |
1810 | ||
1811 | /* MAC addr and PHY mask , RMII enable info from platform_data */ | |
d458cdf7 | 1812 | memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN); |
5d69e007 | 1813 | priv->phy_id = pdata->phy_id; |
a6286ee6 AG |
1814 | priv->rmii_en = pdata->rmii_en; |
1815 | priv->version = pdata->version; | |
01a9af36 S |
1816 | priv->int_enable = pdata->interrupt_enable; |
1817 | priv->int_disable = pdata->interrupt_disable; | |
1818 | ||
84da2658 S |
1819 | priv->coal_intvl = 0; |
1820 | priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); | |
1821 | ||
a6286ee6 AG |
1822 | /* Get EMAC platform data */ |
1823 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a6286ee6 | 1824 | priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; |
6892b41d LP |
1825 | priv->remap_addr = devm_ioremap_resource(&pdev->dev, res); |
1826 | if (IS_ERR(priv->remap_addr)) { | |
6892b41d | 1827 | rc = PTR_ERR(priv->remap_addr); |
b8092861 | 1828 | goto no_pdata; |
a6286ee6 | 1829 | } |
a1594321 TL |
1830 | |
1831 | res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1832 | if (res_ctrl) { | |
1833 | priv->ctrl_base = | |
1834 | devm_ioremap_resource(&pdev->dev, res_ctrl); | |
1ef53ebf JL |
1835 | if (IS_ERR(priv->ctrl_base)) { |
1836 | rc = PTR_ERR(priv->ctrl_base); | |
a1594321 | 1837 | goto no_pdata; |
1ef53ebf | 1838 | } |
a1594321 TL |
1839 | } else { |
1840 | priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; | |
1841 | } | |
1842 | ||
a6286ee6 AG |
1843 | priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; |
1844 | ndev->base_addr = (unsigned long)priv->remap_addr; | |
1845 | ||
3ef0fdb2 CC |
1846 | hw_ram_addr = pdata->hw_ram_addr; |
1847 | if (!hw_ram_addr) | |
1848 | hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; | |
1849 | ||
1850 | memset(&dma_params, 0, sizeof(dma_params)); | |
68bc74fe | 1851 | dma_params.dev = &pdev->dev; |
3ef0fdb2 CC |
1852 | dma_params.dmaregs = priv->emac_base; |
1853 | dma_params.rxthresh = priv->emac_base + 0x120; | |
1854 | dma_params.rxfree = priv->emac_base + 0x140; | |
1855 | dma_params.txhdp = priv->emac_base + 0x600; | |
1856 | dma_params.rxhdp = priv->emac_base + 0x620; | |
1857 | dma_params.txcp = priv->emac_base + 0x640; | |
1858 | dma_params.rxcp = priv->emac_base + 0x660; | |
1859 | dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; | |
1860 | dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; | |
6a1fef6d | 1861 | dma_params.desc_hw_addr = hw_ram_addr; |
3ef0fdb2 CC |
1862 | dma_params.desc_mem_size = pdata->ctrl_ram_size; |
1863 | dma_params.desc_align = 16; | |
1864 | ||
6a1fef6d S |
1865 | dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : |
1866 | (u32 __force)res->start + pdata->ctrl_ram_offset; | |
1867 | ||
3ef0fdb2 CC |
1868 | priv->dma = cpdma_ctlr_create(&dma_params); |
1869 | if (!priv->dma) { | |
240b2628 | 1870 | dev_err(&pdev->dev, "error initializing DMA\n"); |
3ef0fdb2 | 1871 | rc = -ENOMEM; |
b8092861 | 1872 | goto no_pdata; |
3ef0fdb2 CC |
1873 | } |
1874 | ||
925d65e6 IK |
1875 | priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH, |
1876 | emac_tx_handler, 0); | |
1877 | priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH, | |
1878 | emac_rx_handler, 1); | |
3ef0fdb2 CC |
1879 | if (WARN_ON(!priv->txchan || !priv->rxchan)) { |
1880 | rc = -ENOMEM; | |
b8092861 | 1881 | goto no_cpdma_chan; |
3ef0fdb2 | 1882 | } |
ad021ae8 | 1883 | |
a6286ee6 AG |
1884 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1885 | if (!res) { | |
240b2628 | 1886 | dev_err(&pdev->dev, "error getting irq res\n"); |
a6286ee6 | 1887 | rc = -ENOENT; |
b8092861 | 1888 | goto no_cpdma_chan; |
a6286ee6 AG |
1889 | } |
1890 | ndev->irq = res->start; | |
1891 | ||
9120bd6e TL |
1892 | rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr); |
1893 | if (!rc) | |
1894 | ether_addr_copy(ndev->dev_addr, priv->mac_addr); | |
1895 | ||
a6286ee6 | 1896 | if (!is_valid_ether_addr(priv->mac_addr)) { |
a6286ee6 | 1897 | /* Use random MAC if none passed */ |
baf1d378 DK |
1898 | eth_hw_addr_random(ndev); |
1899 | memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); | |
240b2628 JH |
1900 | dev_warn(&pdev->dev, "using random MAC addr: %pM\n", |
1901 | priv->mac_addr); | |
a6286ee6 AG |
1902 | } |
1903 | ||
1904 | ndev->netdev_ops = &emac_netdev_ops; | |
7ad24ea4 | 1905 | ndev->ethtool_ops = ðtool_ops; |
a6286ee6 AG |
1906 | netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); |
1907 | ||
b5133e7a TL |
1908 | pm_runtime_enable(&pdev->dev); |
1909 | rc = pm_runtime_get_sync(&pdev->dev); | |
1910 | if (rc < 0) { | |
1911 | pm_runtime_put_noidle(&pdev->dev); | |
1912 | dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", | |
1913 | __func__, rc); | |
1914 | goto no_cpdma_chan; | |
1915 | } | |
1916 | ||
a6286ee6 AG |
1917 | /* register the network device */ |
1918 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1919 | rc = register_netdev(ndev); | |
1920 | if (rc) { | |
240b2628 | 1921 | dev_err(&pdev->dev, "error in register_netdev\n"); |
a6286ee6 | 1922 | rc = -ENODEV; |
b5133e7a | 1923 | pm_runtime_put(&pdev->dev); |
b8092861 | 1924 | goto no_cpdma_chan; |
a6286ee6 AG |
1925 | } |
1926 | ||
a6286ee6 | 1927 | |
a6286ee6 | 1928 | if (netif_msg_probe(priv)) { |
68bc74fe | 1929 | dev_notice(&pdev->dev, "DaVinci EMAC Probe found device " |
a6286ee6 AG |
1930 | "(regs: %p, irq: %d)\n", |
1931 | (void *)priv->emac_base_phys, ndev->irq); | |
1932 | } | |
b5133e7a | 1933 | pm_runtime_put(&pdev->dev); |
3ba97381 | 1934 | |
a6286ee6 AG |
1935 | return 0; |
1936 | ||
b8092861 | 1937 | no_cpdma_chan: |
3ef0fdb2 CC |
1938 | if (priv->txchan) |
1939 | cpdma_chan_destroy(priv->txchan); | |
1940 | if (priv->rxchan) | |
1941 | cpdma_chan_destroy(priv->rxchan); | |
1942 | cpdma_ctlr_destroy(priv->dma); | |
b8092861 | 1943 | no_pdata: |
a6286ee6 AG |
1944 | free_netdev(ndev); |
1945 | return rc; | |
1946 | } | |
1947 | ||
1948 | /** | |
49ce9c2c | 1949 | * davinci_emac_remove - EMAC device remove |
a6286ee6 AG |
1950 | * @pdev: The DaVinci EMAC device that we are removing |
1951 | * | |
1952 | * Called when removing the device driver. We disable clock usage and release | |
1953 | * the resources taken up by the driver and unregister network device | |
1954 | */ | |
e38921d4 | 1955 | static int davinci_emac_remove(struct platform_device *pdev) |
a6286ee6 | 1956 | { |
a6286ee6 AG |
1957 | struct net_device *ndev = platform_get_drvdata(pdev); |
1958 | struct emac_priv *priv = netdev_priv(ndev); | |
1959 | ||
1960 | dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); | |
1961 | ||
3ef0fdb2 CC |
1962 | if (priv->txchan) |
1963 | cpdma_chan_destroy(priv->txchan); | |
1964 | if (priv->rxchan) | |
1965 | cpdma_chan_destroy(priv->rxchan); | |
1966 | cpdma_ctlr_destroy(priv->dma); | |
1967 | ||
a6286ee6 | 1968 | unregister_netdev(ndev); |
5817f977 | 1969 | of_node_put(priv->phy_node); |
99164f9e | 1970 | pm_runtime_disable(&pdev->dev); |
2a1bc0d5 | 1971 | free_netdev(ndev); |
a6286ee6 | 1972 | |
a6286ee6 AG |
1973 | return 0; |
1974 | } | |
1975 | ||
d4fdcd92 | 1976 | static int davinci_emac_suspend(struct device *dev) |
8d044fe6 | 1977 | { |
d4fdcd92 | 1978 | struct platform_device *pdev = to_platform_device(dev); |
1979 | struct net_device *ndev = platform_get_drvdata(pdev); | |
8d044fe6 | 1980 | |
d4fdcd92 | 1981 | if (netif_running(ndev)) |
1982 | emac_dev_stop(ndev); | |
8d044fe6 | 1983 | |
8d044fe6 RL |
1984 | return 0; |
1985 | } | |
1986 | ||
d4fdcd92 | 1987 | static int davinci_emac_resume(struct device *dev) |
8d044fe6 | 1988 | { |
d4fdcd92 | 1989 | struct platform_device *pdev = to_platform_device(dev); |
1990 | struct net_device *ndev = platform_get_drvdata(pdev); | |
8d044fe6 | 1991 | |
d4fdcd92 | 1992 | if (netif_running(ndev)) |
1993 | emac_dev_open(ndev); | |
8d044fe6 RL |
1994 | |
1995 | return 0; | |
1996 | } | |
1997 | ||
d4fdcd92 | 1998 | static const struct dev_pm_ops davinci_emac_pm_ops = { |
1999 | .suspend = davinci_emac_suspend, | |
2000 | .resume = davinci_emac_resume, | |
2001 | }; | |
2002 | ||
151328c8 | 2003 | #if IS_ENABLED(CONFIG_OF) |
dd0df47d TL |
2004 | static const struct emac_platform_data am3517_emac_data = { |
2005 | .version = EMAC_VERSION_2, | |
2006 | .hw_ram_addr = 0x01e20000, | |
2007 | }; | |
2008 | ||
de390083 TL |
2009 | static const struct emac_platform_data dm816_emac_data = { |
2010 | .version = EMAC_VERSION_2, | |
2011 | }; | |
2012 | ||
42f59967 HS |
2013 | static const struct of_device_id davinci_emac_of_match[] = { |
2014 | {.compatible = "ti,davinci-dm6467-emac", }, | |
dd0df47d | 2015 | {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, |
de390083 | 2016 | {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, |
42f59967 HS |
2017 | {}, |
2018 | }; | |
2019 | MODULE_DEVICE_TABLE(of, davinci_emac_of_match); | |
151328c8 | 2020 | #endif |
42f59967 | 2021 | |
1aa8b471 | 2022 | /* davinci_emac_driver: EMAC platform driver structure */ |
a6286ee6 AG |
2023 | static struct platform_driver davinci_emac_driver = { |
2024 | .driver = { | |
2025 | .name = "davinci_emac", | |
d4fdcd92 | 2026 | .pm = &davinci_emac_pm_ops, |
42f59967 | 2027 | .of_match_table = of_match_ptr(davinci_emac_of_match), |
a6286ee6 AG |
2028 | }, |
2029 | .probe = davinci_emac_probe, | |
e38921d4 | 2030 | .remove = davinci_emac_remove, |
a6286ee6 AG |
2031 | }; |
2032 | ||
2033 | /** | |
49ce9c2c | 2034 | * davinci_emac_init - EMAC driver module init |
a6286ee6 AG |
2035 | * |
2036 | * Called when initializing the driver. We register the driver with | |
2037 | * the platform. | |
2038 | */ | |
2039 | static int __init davinci_emac_init(void) | |
2040 | { | |
2041 | return platform_driver_register(&davinci_emac_driver); | |
2042 | } | |
2db9517e | 2043 | late_initcall(davinci_emac_init); |
a6286ee6 AG |
2044 | |
2045 | /** | |
49ce9c2c | 2046 | * davinci_emac_exit - EMAC driver module exit |
a6286ee6 AG |
2047 | * |
2048 | * Called when exiting the driver completely. We unregister the driver with | |
2049 | * the platform and exit | |
2050 | */ | |
2051 | static void __exit davinci_emac_exit(void) | |
2052 | { | |
2053 | platform_driver_unregister(&davinci_emac_driver); | |
2054 | } | |
2055 | module_exit(davinci_emac_exit); | |
2056 | ||
2057 | MODULE_LICENSE("GPL"); | |
2058 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); | |
2059 | MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); | |
2060 | MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); |