[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / ti / davinci_mdio.c

/*
 * DaVinci MDIO Module driver
 *
 * Copyright (C) 2010 Texas Instruments.
 *
 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
 *
 * Copyright (C) 2009 Texas Instruments.
 *
 * ---------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ---------------------------------------------------------------------------
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/davinci_emac.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/pinctrl/consumer.h>

/*
 * This timeout definition is a worst-case ultra defensive measure against
 * unexpected controller lock ups.  Ideally, we should never ever hit this
 * scenario in practice.
 */
#define MDIO_TIMEOUT		100 /* msecs */

#define PHY_REG_MASK		0x1f
#define PHY_ID_MASK		0x1f

#define DEF_OUT_FREQ		2200000		/* 2.2 MHz */

struct davinci_mdio_regs {
	u32	version;
	u32	control;
#define CONTROL_IDLE		BIT(31)
#define CONTROL_ENABLE		BIT(30)
#define CONTROL_MAX_DIV		(0xffff)

	u32	alive;
	u32	link;
	u32	linkintraw;
	u32	linkintmasked;
	u32	__reserved_0[2];
	u32	userintraw;
	u32	userintmasked;
	u32	userintmaskset;
	u32	userintmaskclr;
	u32	__reserved_1[20];

	struct {
		u32	access;
#define USERACCESS_GO		BIT(31)
#define USERACCESS_WRITE	BIT(30)
#define USERACCESS_ACK		BIT(29)
#define USERACCESS_READ		(0)
#define USERACCESS_DATA		(0xffff)

		u32	physel;
	}	user[0];
};

static const struct mdio_platform_data default_pdata = {
	.bus_freq = DEF_OUT_FREQ,
};

struct davinci_mdio_data {
	struct mdio_platform_data pdata;
	struct davinci_mdio_regs __iomem *regs;
	spinlock_t	lock;
	struct clk	*clk;
	struct device	*dev;
	struct mii_bus	*bus;
	bool		suspended;
	unsigned long	access_time; /* jiffies */
	/* Indicates that driver shouldn't modify phy_mask in case
	 * if MDIO bus is registered from DT.
	 */
	bool		skip_scan;
};

static void __davinci_mdio_reset(struct davinci_mdio_data *data)
{
	u32 mdio_in, div, mdio_out_khz, access_time;

	mdio_in = clk_get_rate(data->clk);
	div = (mdio_in / data->pdata.bus_freq) - 1;
	if (div > CONTROL_MAX_DIV)
		div = CONTROL_MAX_DIV;

	/* set enable and clock divider */
	__raw_writel(div | CONTROL_ENABLE, &data->regs->control);

	/*
	 * One mdio transaction consists of:
	 *	32 bits of preamble
	 *	32 bits of transferred data
	 *	24 bits of bus yield (not needed unless shared?)
	 */
	mdio_out_khz = mdio_in / (1000 * (div + 1));
	access_time  = (88 * 1000) / mdio_out_khz;

	/*
	 * In the worst case, we could be kicking off a user-access immediately
	 * after the mdio bus scan state-machine triggered its own read.  If
	 * so, our request could get deferred by one access cycle.  We
	 * defensively allow for 4 access cycles.
	 */
	data->access_time = usecs_to_jiffies(access_time * 4);
	if (!data->access_time)
		data->access_time = 1;
}

static int davinci_mdio_reset(struct mii_bus *bus)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 phy_mask, ver;

	__davinci_mdio_reset(data);

	/* wait for scan logic to settle */
	msleep(PHY_MAX_ADDR * data->access_time);

	/* dump hardware version info */
	ver = __raw_readl(&data->regs->version);
	dev_info(data->dev, "davinci mdio revision %d.%d\n",
		 (ver >> 8) & 0xff, ver & 0xff);

	if (data->skip_scan)
		return 0;

	/* get phy mask from the alive register */
	phy_mask = __raw_readl(&data->regs->alive);
	if (phy_mask) {
		/* restrict mdio bus to live phys only */
		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
		phy_mask = ~phy_mask;
	} else {
		/* desperately scan all phys */
		dev_warn(data->dev, "no live phy, scanning all\n");
		phy_mask = 0;
	}
	data->bus->phy_mask = phy_mask;

	return 0;
}

/* wait until hardware is ready for another user access */
static inline int wait_for_user_access(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	u32 reg;

	while (time_after(timeout, jiffies)) {
		reg = __raw_readl(&regs->user[0].access);
		if ((reg & USERACCESS_GO) == 0)
			return 0;

		reg = __raw_readl(&regs->control);
		if ((reg & CONTROL_IDLE) == 0)
			continue;

		/*
		 * An emac soft_reset may have clobbered the mdio controller's
		 * state machine.  We need to reset and retry the current
		 * operation
		 */
		dev_warn(data->dev, "resetting idled controller\n");
		__davinci_mdio_reset(data);
		return -EAGAIN;
	}

	reg = __raw_readl(&regs->user[0].access);
	if ((reg & USERACCESS_GO) == 0)
		return 0;

	dev_err(data->dev, "timed out waiting for user access\n");
	return -ETIMEDOUT;
}

/* wait until hardware state machine is idle */
static inline int wait_for_idle(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);

	while (time_after(timeout, jiffies)) {
		if (__raw_readl(&regs->control) & CONTROL_IDLE)
			return 0;
	}
	dev_err(data->dev, "timed out waiting for idle\n");
	return -ETIMEDOUT;
}

static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	spin_lock(&data->lock);

	if (data->suspended) {
		spin_unlock(&data->lock);
		return -ENODEV;
	}

	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
	       (phy_id << 16));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		reg = __raw_readl(&data->regs->user[0].access);
		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
		break;
	}

	spin_unlock(&data->lock);

	return ret;
}

static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
			      int phy_reg, u16 phy_data)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	spin_lock(&data->lock);

	if (data->suspended) {
		spin_unlock(&data->lock);
		return -ENODEV;
	}

	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
		   (phy_id << 16) | (phy_data & USERACCESS_DATA));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		break;
	}

	spin_unlock(&data->lock);

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
			 struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	u32 prop;

	if (!node)
		return -EINVAL;

	if (of_property_read_u32(node, "bus_freq", &prop)) {
		dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
		return -EINVAL;
	}
	data->bus_freq = prop;

	return 0;
}
#endif

static int davinci_mdio_probe(struct platform_device *pdev)
{
	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device *dev = &pdev->dev;
	struct davinci_mdio_data *data;
	struct resource *res;
	struct phy_device *phy;
	int ret, addr;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->bus = devm_mdiobus_alloc(dev);
	if (!data->bus) {
		dev_err(dev, "failed to alloc mii bus\n");
		return -ENOMEM;
	}

	if (dev->of_node) {
		if (davinci_mdio_probe_dt(&data->pdata, pdev))
			data->pdata = default_pdata;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
	} else {
		data->pdata = pdata ? (*pdata) : default_pdata;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
			 pdev->name, pdev->id);
	}

	data->bus->name		= dev_name(dev);
	data->bus->read		= davinci_mdio_read,
	data->bus->write	= davinci_mdio_write,
	data->bus->reset	= davinci_mdio_reset,
	data->bus->parent	= dev;
	data->bus->priv		= data;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);
	data->clk = devm_clk_get(dev, "fck");
	if (IS_ERR(data->clk)) {
		dev_err(dev, "failed to get device clock\n");
		ret = PTR_ERR(data->clk);
		data->clk = NULL;
		goto bail_out;
	}

	dev_set_drvdata(dev, data);
	data->dev = dev;
	spin_lock_init(&data->lock);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(data->regs)) {
		ret = PTR_ERR(data->regs);
		goto bail_out;
	}

	/* register the mii bus
	 * Create PHYs from DT only in case if PHY child nodes are explicitly
	 * defined to support backward compatibility with DTs which assume that
	 * Davinci MDIO will always scan the bus for PHYs detection.
	 */
	if (dev->of_node && of_get_child_count(dev->of_node)) {
		data->skip_scan = true;
		ret = of_mdiobus_register(data->bus, dev->of_node);
	} else {
		ret = mdiobus_register(data->bus);
	}
	if (ret)
		goto bail_out;

	/* scan and dump the bus */
	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		phy = mdiobus_get_phy(data->bus, addr);
		if (phy) {
			dev_info(dev, "phy[%d]: device %s, driver %s\n",
				 phy->mdio.addr, phydev_name(phy),
				 phy->drv ? phy->drv->name : "unknown");
		}
	}

	return 0;

bail_out:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int davinci_mdio_remove(struct platform_device *pdev)
{
	struct davinci_mdio_data *data = platform_get_drvdata(pdev);

	if (data->bus)
		mdiobus_unregister(data->bus);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int davinci_mdio_suspend(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	u32 ctrl;

	spin_lock(&data->lock);

	/* shutdown the scan state machine */
	ctrl = __raw_readl(&data->regs->control);
	ctrl &= ~CONTROL_ENABLE;
	__raw_writel(ctrl, &data->regs->control);
	wait_for_idle(data);

	data->suspended = true;
	spin_unlock(&data->lock);
	pm_runtime_put_sync(data->dev);

	/* Select sleep pin state */
	pinctrl_pm_select_sleep_state(dev);

	return 0;
}

static int davinci_mdio_resume(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);

	/* Select default pin state */
	pinctrl_pm_select_default_state(dev);

	pm_runtime_get_sync(data->dev);

	spin_lock(&data->lock);
	/* restart the scan state machine */
	__davinci_mdio_reset(data);

	data->suspended = false;
	spin_unlock(&data->lock);

	return 0;
}
#endif

static const struct dev_pm_ops davinci_mdio_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
};

#if IS_ENABLED(CONFIG_OF)
static const struct of_device_id davinci_mdio_of_mtable[] = {
	{ .compatible = "ti,davinci_mdio", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
#endif

static struct platform_driver davinci_mdio_driver = {
	.driver = {
		.name	 = "davinci_mdio",
		.pm	 = &davinci_mdio_pm_ops,
		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
	},
	.probe = davinci_mdio_probe,
	.remove = davinci_mdio_remove,
};

static int __init davinci_mdio_init(void)
{
	return platform_driver_register(&davinci_mdio_driver);
}
device_initcall(davinci_mdio_init);

static void __exit davinci_mdio_exit(void)
{
	platform_driver_unregister(&davinci_mdio_driver);
}
module_exit(davinci_mdio_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DaVinci MDIO driver");
Commit	Line	Data
f20136eb CC	1	/*
	2	* DaVinci MDIO Module driver
	3	*
	4	* Copyright (C) 2010 Texas Instruments.
	5	*
	6	* Shamelessly ripped out of davinci_emac.c, original copyrights follow:
	7	*
	8	* Copyright (C) 2009 Texas Instruments.
	9	*
	10	* ---------------------------------------------------------------------------
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	* ---------------------------------------------------------------------------
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/delay.h>
	31	#include <linux/sched.h>
	32	#include <linux/slab.h>
	33	#include <linux/phy.h>
	34	#include <linux/clk.h>
	35	#include <linux/err.h>
	36	#include <linux/io.h>
8e476d9d	37	#include <linux/pm_runtime.h>
f20136eb	38	#include <linux/davinci_emac.h>
ec03e6a8 M	39	#include <linux/of.h>
ec03e6a8 M	40	#include <linux/of_device.h>
0a0ea068	41	#include <linux/of_mdio.h>
5c0e3580	42	#include <linux/pinctrl/consumer.h>
f20136eb CC	43
	44	/*
	45	* This timeout definition is a worst-case ultra defensive measure against
	46	* unexpected controller lock ups. Ideally, we should never ever hit this
	47	* scenario in practice.
	48	*/
	49	#define MDIO_TIMEOUT 100 /* msecs */
	50
	51	#define PHY_REG_MASK 0x1f
	52	#define PHY_ID_MASK 0x1f
	53
	54	#define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
	55
	56	struct davinci_mdio_regs {
	57	u32 version;
	58	u32 control;
	59	#define CONTROL_IDLE BIT(31)
	60	#define CONTROL_ENABLE BIT(30)
7c3a95a1	61	#define CONTROL_MAX_DIV (0xffff)
f20136eb CC	62
	63	u32 alive;
	64	u32 link;
	65	u32 linkintraw;
	66	u32 linkintmasked;
	67	u32 __reserved_0[2];
	68	u32 userintraw;
	69	u32 userintmasked;
	70	u32 userintmaskset;
	71	u32 userintmaskclr;
	72	u32 __reserved_1[20];
	73
	74	struct {
	75	u32 access;
	76	#define USERACCESS_GO BIT(31)
	77	#define USERACCESS_WRITE BIT(30)
	78	#define USERACCESS_ACK BIT(29)
	79	#define USERACCESS_READ (0)
	80	#define USERACCESS_DATA (0xffff)
	81
	82	u32 physel;
	83	} user[0];
	84	};
	85
9b05f462	86	static const struct mdio_platform_data default_pdata = {
f20136eb CC	87	.bus_freq = DEF_OUT_FREQ,
	88	};
	89
	90	struct davinci_mdio_data {
	91	struct mdio_platform_data pdata;
	92	struct davinci_mdio_regs __iomem *regs;
	93	spinlock_t lock;
	94	struct clk *clk;
	95	struct device *dev;
	96	struct mii_bus *bus;
	97	bool suspended;
	98	unsigned long access_time; /* jiffies */
0a0ea068 GS	99	/* Indicates that driver shouldn't modify phy_mask in case
	100	* if MDIO bus is registered from DT.
	101	*/
	102	bool skip_scan;
f20136eb CC	103	};
	104
	105	static void __davinci_mdio_reset(struct davinci_mdio_data *data)
	106	{
	107	u32 mdio_in, div, mdio_out_khz, access_time;
	108
	109	mdio_in = clk_get_rate(data->clk);
	110	div = (mdio_in / data->pdata.bus_freq) - 1;
	111	if (div > CONTROL_MAX_DIV)
	112	div = CONTROL_MAX_DIV;
	113
	114	/* set enable and clock divider */
	115	__raw_writel(div \| CONTROL_ENABLE, &data->regs->control);
	116
	117	/*
	118	* One mdio transaction consists of:
	119	* 32 bits of preamble
	120	* 32 bits of transferred data
	121	* 24 bits of bus yield (not needed unless shared?)
	122	*/
	123	mdio_out_khz = mdio_in / (1000 * (div + 1));
	124	access_time = (88 * 1000) / mdio_out_khz;
	125
	126	/*
	127	* In the worst case, we could be kicking off a user-access immediately
	128	* after the mdio bus scan state-machine triggered its own read. If
	129	* so, our request could get deferred by one access cycle. We
	130	* defensively allow for 4 access cycles.
	131	*/
	132	data->access_time = usecs_to_jiffies(access_time * 4);
	133	if (!data->access_time)
	134	data->access_time = 1;
	135	}
	136
	137	static int davinci_mdio_reset(struct mii_bus *bus)
	138	{
	139	struct davinci_mdio_data *data = bus->priv;
	140	u32 phy_mask, ver;
	141
	142	__davinci_mdio_reset(data);
	143
	144	/* wait for scan logic to settle */
	145	msleep(PHY_MAX_ADDR * data->access_time);
	146
	147	/* dump hardware version info */
	148	ver = __raw_readl(&data->regs->version);
	149	dev_info(data->dev, "davinci mdio revision %d.%d\n",
	150	(ver >> 8) & 0xff, ver & 0xff);
	151
0a0ea068 GS	152	if (data->skip_scan)
	153	return 0;
	154
f20136eb CC	155	/* get phy mask from the alive register */
	156	phy_mask = __raw_readl(&data->regs->alive);
	157	if (phy_mask) {
	158	/* restrict mdio bus to live phys only */
	159	dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
	160	phy_mask = ~phy_mask;
	161	} else {
	162	/* desperately scan all phys */
	163	dev_warn(data->dev, "no live phy, scanning all\n");
	164	phy_mask = 0;
	165	}
	166	data->bus->phy_mask = phy_mask;
	167
	168	return 0;
	169	}
	170
	171	/* wait until hardware is ready for another user access */
	172	static inline int wait_for_user_access(struct davinci_mdio_data *data)
	173	{
	174	struct davinci_mdio_regs __iomem *regs = data->regs;
	175	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	176	u32 reg;
	177
	178	while (time_after(timeout, jiffies)) {
	179	reg = __raw_readl(&regs->user[0].access);
	180	if ((reg & USERACCESS_GO) == 0)
	181	return 0;
	182
	183	reg = __raw_readl(&regs->control);
	184	if ((reg & CONTROL_IDLE) == 0)
	185	continue;
	186
	187	/*
	188	* An emac soft_reset may have clobbered the mdio controller's
	189	* state machine. We need to reset and retry the current
	190	* operation
	191	*/
	192	dev_warn(data->dev, "resetting idled controller\n");
	193	__davinci_mdio_reset(data);
	194	return -EAGAIN;
	195	}
5b76d060 CR	196
	197	reg = __raw_readl(&regs->user[0].access);
	198	if ((reg & USERACCESS_GO) == 0)
	199	return 0;
	200
f20136eb CC	201	dev_err(data->dev, "timed out waiting for user access\n");
	202	return -ETIMEDOUT;
	203	}
	204
	205	/* wait until hardware state machine is idle */
	206	static inline int wait_for_idle(struct davinci_mdio_data *data)
	207	{
	208	struct davinci_mdio_regs __iomem *regs = data->regs;
	209	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	210
	211	while (time_after(timeout, jiffies)) {
	212	if (__raw_readl(&regs->control) & CONTROL_IDLE)
	213	return 0;
	214	}
	215	dev_err(data->dev, "timed out waiting for idle\n");
	216	return -ETIMEDOUT;
	217	}
	218
	219	static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
	220	{
	221	struct davinci_mdio_data *data = bus->priv;
	222	u32 reg;
	223	int ret;
	224
	225	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
	226	return -EINVAL;
	227
	228	spin_lock(&data->lock);
	229
	230	if (data->suspended) {
	231	spin_unlock(&data->lock);
	232	return -ENODEV;
	233	}
	234
	235	reg = (USERACCESS_GO \| USERACCESS_READ \| (phy_reg << 21) \|
	236	(phy_id << 16));
	237
	238	while (1) {
	239	ret = wait_for_user_access(data);
	240	if (ret == -EAGAIN)
	241	continue;
	242	if (ret < 0)
	243	break;
	244
	245	__raw_writel(reg, &data->regs->user[0].access);
	246
	247	ret = wait_for_user_access(data);
	248	if (ret == -EAGAIN)
	249	continue;
	250	if (ret < 0)
	251	break;
	252
	253	reg = __raw_readl(&data->regs->user[0].access);
	254	ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
	255	break;
	256	}
	257
	258	spin_unlock(&data->lock);
	259
	260	return ret;
	261	}
	262
	263	static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
	264	int phy_reg, u16 phy_data)
265	{
266	struct davinci_mdio_data *data = bus->priv;
267	u32 reg;
268	int ret;
269
270	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
271	return -EINVAL;
272
273	spin_lock(&data->lock);
274
275	if (data->suspended) {
276	spin_unlock(&data->lock);
277	return -ENODEV;
278	}
279
280	reg = (USERACCESS_GO \| USERACCESS_WRITE \| (phy_reg << 21) \|
281	(phy_id << 16) \| (phy_data & USERACCESS_DATA));
282
283	while (1) {
284	ret = wait_for_user_access(data);
285	if (ret == -EAGAIN)
286	continue;
287	if (ret < 0)
288	break;
289
290	__raw_writel(reg, &data->regs->user[0].access);
291
292	ret = wait_for_user_access(data);
293	if (ret == -EAGAIN)
294	continue;
295	break;
296	}
297
298	spin_unlock(&data->lock);
299
300	return 0;
301	}
302
277e2a84	303	#if IS_ENABLED(CONFIG_OF)
ec03e6a8 M	304	static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
	305	struct platform_device *pdev)
	306	{
	307	struct device_node *node = pdev->dev.of_node;
	308	u32 prop;
	309
	310	if (!node)
	311	return -EINVAL;
	312
	313	if (of_property_read_u32(node, "bus_freq", &prop)) {
a92f40a9	314	dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
ec03e6a8 M	315	return -EINVAL;
	316	}
	317	data->bus_freq = prop;
	318
	319	return 0;
	320	}
277e2a84	321	#endif
ec03e6a8	322
e38921d4	323	static int davinci_mdio_probe(struct platform_device *pdev)
f20136eb	324	{
894cdbb0	325	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
f20136eb CC	326	struct device *dev = &pdev->dev;
	327	struct davinci_mdio_data *data;
	328	struct resource *res;
	329	struct phy_device *phy;
	330	int ret, addr;
	331
50d0636e	332	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
b2adaca9	333	if (!data)
f20136eb	334	return -ENOMEM;
f20136eb	335
50d0636e	336	data->bus = devm_mdiobus_alloc(dev);
f20136eb CC	337	if (!data->bus) {
f20136eb CC	338	dev_err(dev, "failed to alloc mii bus\n");
50d0636e	339	return -ENOMEM;
f20136eb CC	340	}
f20136eb CC	341
ec03e6a8 M	342	if (dev->of_node) {
	343	if (davinci_mdio_probe_dt(&data->pdata, pdev))
	344	data->pdata = default_pdata;
	345	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
	346	} else {
	347	data->pdata = pdata ? (*pdata) : default_pdata;
	348	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
	349	pdev->name, pdev->id);
	350	}
	351
f20136eb CC	352	data->bus->name = dev_name(dev);
	353	data->bus->read = davinci_mdio_read,
	354	data->bus->write = davinci_mdio_write,
	355	data->bus->reset = davinci_mdio_reset,
	356	data->bus->parent = dev;
	357	data->bus->priv = data;
f20136eb	358
8e476d9d M	359	pm_runtime_enable(&pdev->dev);
8e476d9d M	360	pm_runtime_get_sync(&pdev->dev);
50d0636e	361	data->clk = devm_clk_get(dev, "fck");
f20136eb	362	if (IS_ERR(data->clk)) {
f20136eb CC	363	dev_err(dev, "failed to get device clock\n");
f20136eb CC	364	ret = PTR_ERR(data->clk);
cb0a178c	365	data->clk = NULL;
f20136eb CC	366	goto bail_out;
	367	}
	368
f20136eb CC	369	dev_set_drvdata(dev, data);
	370	data->dev = dev;
	371	spin_lock_init(&data->lock);
	372
	373	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9728e1a7 GS	374	data->regs = devm_ioremap_resource(dev, res);
	375	if (IS_ERR(data->regs)) {
	376	ret = PTR_ERR(data->regs);
f20136eb CC	377	goto bail_out;
	378	}
	379
0a0ea068 GS	380	/* register the mii bus
	381	* Create PHYs from DT only in case if PHY child nodes are explicitly
	382	* defined to support backward compatibility with DTs which assume that
	383	* Davinci MDIO will always scan the bus for PHYs detection.
	384	*/
	385	if (dev->of_node && of_get_child_count(dev->of_node)) {
	386	data->skip_scan = true;
	387	ret = of_mdiobus_register(data->bus, dev->of_node);
	388	} else {
	389	ret = mdiobus_register(data->bus);
	390	}
f20136eb CC	391	if (ret)
	392	goto bail_out;
	393
	394	/* scan and dump the bus */
	395	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
7f854420	396	phy = mdiobus_get_phy(data->bus, addr);
f20136eb CC	397	if (phy) {
f20136eb CC	398	dev_info(dev, "phy[%d]: device %s, driver %s\n",
e5a03bfd	399	phy->mdio.addr, phydev_name(phy),
f20136eb CC	400	phy->drv ? phy->drv->name : "unknown");
	401	}
	402	}
	403
	404	return 0;
	405
	406	bail_out:
8e476d9d M	407	pm_runtime_put_sync(&pdev->dev);
8e476d9d M	408	pm_runtime_disable(&pdev->dev);
f20136eb	409
f20136eb CC	410	return ret;
	411	}
	412
e38921d4	413	static int davinci_mdio_remove(struct platform_device *pdev)
f20136eb	414	{
84ce22df	415	struct davinci_mdio_data *data = platform_get_drvdata(pdev);
f20136eb	416
50d0636e	417	if (data->bus)
b27393ae	418	mdiobus_unregister(data->bus);
f20136eb	419
8e476d9d M	420	pm_runtime_put_sync(&pdev->dev);
8e476d9d M	421	pm_runtime_disable(&pdev->dev);
f20136eb	422
f20136eb CC	423	return 0;
	424	}
	425
2f5c54ce	426	#ifdef CONFIG_PM_SLEEP
f20136eb CC	427	static int davinci_mdio_suspend(struct device *dev)
	428	{
	429	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	430	u32 ctrl;
	431
	432	spin_lock(&data->lock);
	433
	434	/* shutdown the scan state machine */
	435	ctrl = __raw_readl(&data->regs->control);
	436	ctrl &= ~CONTROL_ENABLE;
	437	__raw_writel(ctrl, &data->regs->control);
	438	wait_for_idle(data);
	439
f20136eb CC	440	data->suspended = true;
f20136eb CC	441	spin_unlock(&data->lock);
2786aae7	442	pm_runtime_put_sync(data->dev);
f20136eb	443
5c0e3580 M	444	/* Select sleep pin state */
	445	pinctrl_pm_select_sleep_state(dev);
	446
f20136eb CC	447	return 0;
	448	}
	449
	450	static int davinci_mdio_resume(struct device *dev)
	451	{
	452	struct davinci_mdio_data *data = dev_get_drvdata(dev);
f20136eb	453
5c0e3580 M	454	/* Select default pin state */
	455	pinctrl_pm_select_default_state(dev);
	456
d1df50f4	457	pm_runtime_get_sync(data->dev);
f20136eb	458
2786aae7	459	spin_lock(&data->lock);
f20136eb	460	/* restart the scan state machine */
cc60ab0a	461	__davinci_mdio_reset(data);
f20136eb CC	462
	463	data->suspended = false;
	464	spin_unlock(&data->lock);
	465
	466	return 0;
	467	}
2f5c54ce	468	#endif
f20136eb CC	469
f20136eb CC	470	static const struct dev_pm_ops davinci_mdio_pm_ops = {
2f5c54ce	471	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
f20136eb CC	472	};
f20136eb CC	473
277e2a84	474	#if IS_ENABLED(CONFIG_OF)
ec03e6a8 M	475	static const struct of_device_id davinci_mdio_of_mtable[] = {
	476	{ .compatible = "ti,davinci_mdio", },
	477	{ /* sentinel */ },
	478	};
4bc21d41	479	MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
277e2a84	480	#endif
ec03e6a8	481
f20136eb CC	482	static struct platform_driver davinci_mdio_driver = {
	483	.driver = {
	484	.name = "davinci_mdio",
f20136eb	485	.pm = &davinci_mdio_pm_ops,
ec03e6a8	486	.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
f20136eb CC	487	},
f20136eb CC	488	.probe = davinci_mdio_probe,
e38921d4	489	.remove = davinci_mdio_remove,
f20136eb CC	490	};
	491
	492	static int __init davinci_mdio_init(void)
	493	{
	494	return platform_driver_register(&davinci_mdio_driver);
	495	}
	496	device_initcall(davinci_mdio_init);
	497
	498	static void __exit davinci_mdio_exit(void)
	499	{
	500	platform_driver_unregister(&davinci_mdio_driver);
	501	}
	502	module_exit(davinci_mdio_exit);
	503
	504	MODULE_LICENSE("GPL");
	505	MODULE_DESCRIPTION("DaVinci MDIO driver");