[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / xilinx / ll_temac.h

/* SPDX-License-Identifier: GPL-2.0 */

#ifndef XILINX_LL_TEMAC_H
#define XILINX_LL_TEMAC_H

#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/spinlock.h>

#ifdef CONFIG_PPC_DCR
#include <asm/dcr.h>
#include <asm/dcr-regs.h>
#endif

/* packet size info */
#define XTE_HDR_SIZE			14      /* size of Ethernet header */
#define XTE_TRL_SIZE			4       /* size of Ethernet trailer (FCS) */
#define XTE_JUMBO_MTU			9000
#define XTE_MAX_JUMBO_FRAME_SIZE	(XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)

/*  Configuration options */

/*  Accept all incoming packets.
 *  This option defaults to disabled (cleared) */
#define XTE_OPTION_PROMISC                      (1 << 0)
/*  Jumbo frame support for Tx & Rx.
 *  This option defaults to disabled (cleared) */
#define XTE_OPTION_JUMBO                        (1 << 1)
/*  VLAN Rx & Tx frame support.
 *  This option defaults to disabled (cleared) */
#define XTE_OPTION_VLAN                         (1 << 2)
/*  Enable recognition of flow control frames on Rx
 *  This option defaults to enabled (set) */
#define XTE_OPTION_FLOW_CONTROL                 (1 << 4)
/*  Strip FCS and PAD from incoming frames.
 *  Note: PAD from VLAN frames is not stripped.
 *  This option defaults to disabled (set) */
#define XTE_OPTION_FCS_STRIP                    (1 << 5)
/*  Generate FCS field and add PAD automatically for outgoing frames.
 *  This option defaults to enabled (set) */
#define XTE_OPTION_FCS_INSERT                   (1 << 6)
/*  Enable Length/Type error checking for incoming frames. When this option is
set, the MAC will filter frames that have a mismatched type/length field
and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
types of frames are encountered. When this option is cleared, the MAC will
allow these types of frames to be received.
This option defaults to enabled (set) */
#define XTE_OPTION_LENTYPE_ERR                  (1 << 7)
/*  Enable the transmitter.
 *  This option defaults to enabled (set) */
#define XTE_OPTION_TXEN                         (1 << 11)
/*  Enable the receiver
*   This option defaults to enabled (set) */
#define XTE_OPTION_RXEN                         (1 << 12)

/*  Default options set when device is initialized or reset */
#define XTE_OPTION_DEFAULTS                     \
	(XTE_OPTION_TXEN |                          \
	 XTE_OPTION_FLOW_CONTROL |                  \
	 XTE_OPTION_RXEN)

/* XPS_LL_TEMAC SDMA registers definition */

#define TX_NXTDESC_PTR      0x00            /* r */
#define TX_CURBUF_ADDR      0x01            /* r */
#define TX_CURBUF_LENGTH    0x02            /* r */
#define TX_CURDESC_PTR      0x03            /* rw */
#define TX_TAILDESC_PTR     0x04            /* rw */
#define TX_CHNL_CTRL        0x05            /* rw */
/*
 0:7      24:31       IRQTimeout
 8:15     16:23       IRQCount
 16:20    11:15       Reserved
 21       10          0
 22       9           UseIntOnEnd
 23       8           LdIRQCnt
 24       7           IRQEn
 25:28    3:6         Reserved
 29       2           IrqErrEn
 30       1           IrqDlyEn
 31       0           IrqCoalEn
*/
#define CHNL_CTRL_IRQ_IOE       (1 << 9)
#define CHNL_CTRL_IRQ_EN        (1 << 7)
#define CHNL_CTRL_IRQ_ERR_EN    (1 << 2)
#define CHNL_CTRL_IRQ_DLY_EN    (1 << 1)
#define CHNL_CTRL_IRQ_COAL_EN   (1 << 0)
#define TX_IRQ_REG          0x06            /* rw */
/*
  0:7      24:31       DltTmrValue
 8:15     16:23       ClscCntrValue
 16:17    14:15       Reserved
 18:21    10:13       ClscCnt
 22:23    8:9         DlyCnt
 24:28    3::7        Reserved
 29       2           ErrIrq
 30       1           DlyIrq
 31       0           CoalIrq
 */
#define TX_CHNL_STS         0x07            /* r */
/*
   0:9      22:31   Reserved
 10       21      TailPErr
 11       20      CmpErr
 12       19      AddrErr
 13       18      NxtPErr
 14       17      CurPErr
 15       16      BsyWr
 16:23    8:15    Reserved
 24       7       Error
 25       6       IOE
 26       5       SOE
 27       4       Cmplt
 28       3       SOP
 29       2       EOP
 30       1       EngBusy
 31       0       Reserved
*/

#define RX_NXTDESC_PTR      0x08            /* r */
#define RX_CURBUF_ADDR      0x09            /* r */
#define RX_CURBUF_LENGTH    0x0a            /* r */
#define RX_CURDESC_PTR      0x0b            /* rw */
#define RX_TAILDESC_PTR     0x0c            /* rw */
#define RX_CHNL_CTRL        0x0d            /* rw */
/*
 0:7      24:31       IRQTimeout
 8:15     16:23       IRQCount
 16:20    11:15       Reserved
 21       10          0
 22       9           UseIntOnEnd
 23       8           LdIRQCnt
 24       7           IRQEn
 25:28    3:6         Reserved
 29       2           IrqErrEn
 30       1           IrqDlyEn
 31       0           IrqCoalEn
 */
#define RX_IRQ_REG          0x0e            /* rw */
#define IRQ_COAL        (1 << 0)
#define IRQ_DLY         (1 << 1)
#define IRQ_ERR         (1 << 2)
#define IRQ_DMAERR      (1 << 7)            /* this is not documented ??? */
/*
 0:7      24:31       DltTmrValue
 8:15     16:23       ClscCntrValue
 16:17    14:15       Reserved
 18:21    10:13       ClscCnt
 22:23    8:9         DlyCnt
 24:28    3::7        Reserved
*/
#define RX_CHNL_STS         0x0f        /* r */
#define CHNL_STS_ENGBUSY    (1 << 1)
#define CHNL_STS_EOP        (1 << 2)
#define CHNL_STS_SOP        (1 << 3)
#define CHNL_STS_CMPLT      (1 << 4)
#define CHNL_STS_SOE        (1 << 5)
#define CHNL_STS_IOE        (1 << 6)
#define CHNL_STS_ERR        (1 << 7)

#define CHNL_STS_BSYWR      (1 << 16)
#define CHNL_STS_CURPERR    (1 << 17)
#define CHNL_STS_NXTPERR    (1 << 18)
#define CHNL_STS_ADDRERR    (1 << 19)
#define CHNL_STS_CMPERR     (1 << 20)
#define CHNL_STS_TAILERR    (1 << 21)
/*
 0:9      22:31   Reserved
 10       21      TailPErr
 11       20      CmpErr
 12       19      AddrErr
 13       18      NxtPErr
 14       17      CurPErr
 15       16      BsyWr
 16:23    8:15    Reserved
 24       7       Error
 25       6       IOE
 26       5       SOE
 27       4       Cmplt
 28       3       SOP
 29       2       EOP
 30       1       EngBusy
 31       0       Reserved
*/

#define DMA_CONTROL_REG             0x10            /* rw */
#define DMA_CONTROL_RST                 (1 << 0)
#define DMA_TAIL_ENABLE                 (1 << 2)

/* XPS_LL_TEMAC direct registers definition */

#define XTE_RAF0_OFFSET              0x00
#define RAF0_RST                        (1 << 0)
#define RAF0_MCSTREJ                    (1 << 1)
#define RAF0_BCSTREJ                    (1 << 2)
#define XTE_TPF0_OFFSET              0x04
#define XTE_IFGP0_OFFSET             0x08
#define XTE_ISR0_OFFSET              0x0c
#define ISR0_HARDACSCMPLT               (1 << 0)
#define ISR0_AUTONEG                    (1 << 1)
#define ISR0_RXCMPLT                    (1 << 2)
#define ISR0_RXREJ                      (1 << 3)
#define ISR0_RXFIFOOVR                  (1 << 4)
#define ISR0_TXCMPLT                    (1 << 5)
#define ISR0_RXDCMLCK                   (1 << 6)

#define XTE_IPR0_OFFSET              0x10
#define XTE_IER0_OFFSET              0x14

#define XTE_MSW0_OFFSET              0x20
#define XTE_LSW0_OFFSET              0x24
#define XTE_CTL0_OFFSET              0x28
#define XTE_RDY0_OFFSET              0x2c

#define XTE_RSE_MIIM_RR_MASK      0x0002
#define XTE_RSE_MIIM_WR_MASK      0x0004
#define XTE_RSE_CFG_RR_MASK       0x0020
#define XTE_RSE_CFG_WR_MASK       0x0040
#define XTE_RDY0_HARD_ACS_RDY_MASK  (0x10000)

/* XPS_LL_TEMAC indirect registers offset definition */

#define	XTE_RXC0_OFFSET			0x00000200 /* Rx configuration word 0 */
#define	XTE_RXC1_OFFSET			0x00000240 /* Rx configuration word 1 */
#define XTE_RXC1_RXRST_MASK		(1 << 31)  /* Receiver reset */
#define XTE_RXC1_RXJMBO_MASK		(1 << 30)  /* Jumbo frame enable */
#define XTE_RXC1_RXFCS_MASK		(1 << 29)  /* FCS not stripped */
#define XTE_RXC1_RXEN_MASK		(1 << 28)  /* Receiver enable */
#define XTE_RXC1_RXVLAN_MASK		(1 << 27)  /* VLAN enable */
#define XTE_RXC1_RXHD_MASK		(1 << 26)  /* Half duplex */
#define XTE_RXC1_RXLT_MASK		(1 << 25)  /* Length/type check disable */

#define XTE_TXC_OFFSET			0x00000280 /*  Tx configuration */
#define XTE_TXC_TXRST_MASK		(1 << 31)  /* Transmitter reset */
#define XTE_TXC_TXJMBO_MASK		(1 << 30)  /* Jumbo frame enable */
#define XTE_TXC_TXFCS_MASK		(1 << 29)  /* Generate FCS */
#define XTE_TXC_TXEN_MASK		(1 << 28)  /* Transmitter enable */
#define XTE_TXC_TXVLAN_MASK		(1 << 27)  /* VLAN enable */
#define XTE_TXC_TXHD_MASK		(1 << 26)  /* Half duplex */

#define XTE_FCC_OFFSET			0x000002C0 /* Flow control config */
#define XTE_FCC_RXFLO_MASK		(1 << 29)  /* Rx flow control enable */
#define XTE_FCC_TXFLO_MASK		(1 << 30)  /* Tx flow control enable */

#define XTE_EMCFG_OFFSET		0x00000300 /* EMAC configuration */
#define XTE_EMCFG_LINKSPD_MASK		0xC0000000 /* Link speed */
#define XTE_EMCFG_HOSTEN_MASK		(1 << 26)  /* Host interface enable */
#define XTE_EMCFG_LINKSPD_10		0x00000000 /* 10 Mbit LINKSPD_MASK */
#define XTE_EMCFG_LINKSPD_100		(1 << 30)  /* 100 Mbit LINKSPD_MASK */
#define XTE_EMCFG_LINKSPD_1000		(1 << 31)  /* 1000 Mbit LINKSPD_MASK */

#define XTE_GMIC_OFFSET			0x00000320 /* RGMII/SGMII config */
#define XTE_MC_OFFSET			0x00000340 /* MDIO configuration */
#define XTE_UAW0_OFFSET			0x00000380 /* Unicast address word 0 */
#define XTE_UAW1_OFFSET			0x00000384 /* Unicast address word 1 */

#define XTE_MAW0_OFFSET			0x00000388 /* Multicast addr word 0 */
#define XTE_MAW1_OFFSET			0x0000038C /* Multicast addr word 1 */
#define XTE_AFM_OFFSET			0x00000390 /* Promiscuous mode */
#define XTE_AFM_EPPRM_MASK		(1 << 31)  /* Promiscuous mode enable */

/* Interrupt Request status */
#define XTE_TIS_OFFSET			0x000003A0
#define TIS_FRIS			(1 << 0)
#define TIS_MRIS			(1 << 1)
#define TIS_MWIS			(1 << 2)
#define TIS_ARIS			(1 << 3)
#define TIS_AWIS			(1 << 4)
#define TIS_CRIS			(1 << 5)
#define TIS_CWIS			(1 << 6)

#define XTE_TIE_OFFSET			0x000003A4 /* Interrupt enable */

/**  MII Mamagement Control register (MGTCR) */
#define XTE_MGTDR_OFFSET		0x000003B0 /* MII data */
#define XTE_MIIMAI_OFFSET		0x000003B4 /* MII control */

#define CNTLREG_WRITE_ENABLE_MASK   0x8000
#define CNTLREG_EMAC1SEL_MASK       0x0400
#define CNTLREG_ADDRESSCODE_MASK    0x03ff

/* CDMAC descriptor status bit definitions */

#define STS_CTRL_APP0_ERR         (1 << 31)
#define STS_CTRL_APP0_IRQONEND    (1 << 30)
/* undoccumented */
#define STS_CTRL_APP0_STOPONEND   (1 << 29)
#define STS_CTRL_APP0_CMPLT       (1 << 28)
#define STS_CTRL_APP0_SOP         (1 << 27)
#define STS_CTRL_APP0_EOP         (1 << 26)
#define STS_CTRL_APP0_ENGBUSY     (1 << 25)
/* undocumented */
#define STS_CTRL_APP0_ENGRST      (1 << 24)

#define TX_CONTROL_CALC_CSUM_MASK   1

#define MULTICAST_CAM_TABLE_NUM 4

/* TEMAC Synthesis features */
#define TEMAC_FEATURE_RX_CSUM  (1 << 0)
#define TEMAC_FEATURE_TX_CSUM  (1 << 1)

/* TX/RX CURDESC_PTR points to first descriptor */
/* TX/RX TAILDESC_PTR points to last descriptor in linked list */

/**
 * struct cdmac_bd - LocalLink buffer descriptor format
 *
 * app0 bits:
 *	0    Error
 *	1    IrqOnEnd    generate an interrupt at completion of DMA  op
 *	2    reserved
 *	3    completed   Current descriptor completed
 *	4    SOP         TX - marks first desc/ RX marks first desct
 *	5    EOP         TX marks last desc/RX marks last desc
 *	6    EngBusy     DMA is processing
 *	7    reserved
 *	8:31 application specific
 */
struct cdmac_bd {
	u32 next;	/* Physical address of next buffer descriptor */
	u32 phys;
	u32 len;
	u32 app0;
	u32 app1;	/* TX start << 16 | insert */
	u32 app2;	/* TX csum */
	u32 app3;
	u32 app4;	/* skb for TX length for RX */
};

struct temac_local {
	struct net_device *ndev;
	struct device *dev;

	/* Connection to PHY device */
	struct device_node *phy_node;

	/* MDIO bus data */
	struct mii_bus *mii_bus;	/* MII bus reference */

	/* IO registers, dma functions and IRQs */
	void __iomem *regs;
	void __iomem *sdma_regs;
#ifdef CONFIG_PPC_DCR
	dcr_host_t sdma_dcrs;
#endif
	u32 (*dma_in)(struct temac_local *, int);
	void (*dma_out)(struct temac_local *, int, u32);

	int tx_irq;
	int rx_irq;
	int emac_num;

	struct sk_buff **rx_skb;
	spinlock_t rx_lock;
	struct mutex indirect_mutex;
	u32 options;			/* Current options word */
	int last_link;
	unsigned int temac_features;

	/* Buffer descriptors */
	struct cdmac_bd *tx_bd_v;
	dma_addr_t tx_bd_p;
	struct cdmac_bd *rx_bd_v;
	dma_addr_t rx_bd_p;
	int tx_bd_ci;
	int tx_bd_next;
	int tx_bd_tail;
	int rx_bd_ci;
};

/* xilinx_temac.c */
u32 temac_ior(struct temac_local *lp, int offset);
void temac_iow(struct temac_local *lp, int offset, u32 value);
int temac_indirect_busywait(struct temac_local *lp);
u32 temac_indirect_in32(struct temac_local *lp, int reg);
void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);


/* xilinx_temac_mdio.c */
int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
void temac_mdio_teardown(struct temac_local *lp);

#endif /* XILINX_LL_TEMAC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
92744989 GL	2
	3	#ifndef XILINX_LL_TEMAC_H
	4	#define XILINX_LL_TEMAC_H
	5
	6	#include <linux/netdevice.h>
	7	#include <linux/of.h>
	8	#include <linux/spinlock.h>
e44171f1 JL	9
e44171f1 JL	10	#ifdef CONFIG_PPC_DCR
92744989 GL	11	#include <asm/dcr.h>
92744989 GL	12	#include <asm/dcr-regs.h>
e44171f1	13	#endif
92744989 GL	14
	15	/* packet size info */
	16	#define XTE_HDR_SIZE 14 /* size of Ethernet header */
	17	#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
	18	#define XTE_JUMBO_MTU 9000
	19	#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
	20
	21	/* Configuration options */
	22
	23	/* Accept all incoming packets.
	24	* This option defaults to disabled (cleared) */
	25	#define XTE_OPTION_PROMISC (1 << 0)
	26	/* Jumbo frame support for Tx & Rx.
	27	* This option defaults to disabled (cleared) */
	28	#define XTE_OPTION_JUMBO (1 << 1)
	29	/* VLAN Rx & Tx frame support.
	30	* This option defaults to disabled (cleared) */
	31	#define XTE_OPTION_VLAN (1 << 2)
	32	/* Enable recognition of flow control frames on Rx
	33	* This option defaults to enabled (set) */
	34	#define XTE_OPTION_FLOW_CONTROL (1 << 4)
	35	/* Strip FCS and PAD from incoming frames.
	36	* Note: PAD from VLAN frames is not stripped.
	37	* This option defaults to disabled (set) */
	38	#define XTE_OPTION_FCS_STRIP (1 << 5)
	39	/* Generate FCS field and add PAD automatically for outgoing frames.
	40	* This option defaults to enabled (set) */
	41	#define XTE_OPTION_FCS_INSERT (1 << 6)
	42	/* Enable Length/Type error checking for incoming frames. When this option is
	43	set, the MAC will filter frames that have a mismatched type/length field
	44	and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
	45	types of frames are encountered. When this option is cleared, the MAC will
	46	allow these types of frames to be received.
	47	This option defaults to enabled (set) */
	48	#define XTE_OPTION_LENTYPE_ERR (1 << 7)
	49	/* Enable the transmitter.
	50	* This option defaults to enabled (set) */
	51	#define XTE_OPTION_TXEN (1 << 11)
	52	/* Enable the receiver
	53	* This option defaults to enabled (set) */
	54	#define XTE_OPTION_RXEN (1 << 12)
	55
	56	/* Default options set when device is initialized or reset */
	57	#define XTE_OPTION_DEFAULTS \
	58	(XTE_OPTION_TXEN \| \
	59	XTE_OPTION_FLOW_CONTROL \| \
	60	XTE_OPTION_RXEN)
	61
	62	/* XPS_LL_TEMAC SDMA registers definition */
	63
	64	#define TX_NXTDESC_PTR 0x00 /* r */
	65	#define TX_CURBUF_ADDR 0x01 /* r */
	66	#define TX_CURBUF_LENGTH 0x02 /* r */
	67	#define TX_CURDESC_PTR 0x03 /* rw */
	68	#define TX_TAILDESC_PTR 0x04 /* rw */
	69	#define TX_CHNL_CTRL 0x05 /* rw */
	70	/*
	71	0:7 24:31 IRQTimeout
	72	8:15 16:23 IRQCount
	73	16:20 11:15 Reserved
	74	21 10 0
	75	22 9 UseIntOnEnd
	76	23 8 LdIRQCnt
	77	24 7 IRQEn
78	25:28 3:6 Reserved
79	29 2 IrqErrEn
80	30 1 IrqDlyEn
81	31 0 IrqCoalEn
82	*/
83	#define CHNL_CTRL_IRQ_IOE (1 << 9)
84	#define CHNL_CTRL_IRQ_EN (1 << 7)
85	#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
86	#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)
87	#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
88	#define TX_IRQ_REG 0x06 /* rw */
89	/*
90	0:7 24:31 DltTmrValue
91	8:15 16:23 ClscCntrValue
92	16:17 14:15 Reserved
93	18:21 10:13 ClscCnt
94	22:23 8:9 DlyCnt
95	24:28 3::7 Reserved
96	29 2 ErrIrq
97	30 1 DlyIrq
98	31 0 CoalIrq
99	*/
100	#define TX_CHNL_STS 0x07 /* r */
101	/*
102	0:9 22:31 Reserved
103	10 21 TailPErr
104	11 20 CmpErr
105	12 19 AddrErr
106	13 18 NxtPErr
107	14 17 CurPErr
108	15 16 BsyWr
109	16:23 8:15 Reserved
110	24 7 Error
111	25 6 IOE
112	26 5 SOE
113	27 4 Cmplt
114	28 3 SOP
115	29 2 EOP
116	30 1 EngBusy
117	31 0 Reserved
118	*/
119
120	#define RX_NXTDESC_PTR 0x08 /* r */
121	#define RX_CURBUF_ADDR 0x09 /* r */
122	#define RX_CURBUF_LENGTH 0x0a /* r */
123	#define RX_CURDESC_PTR 0x0b /* rw */
124	#define RX_TAILDESC_PTR 0x0c /* rw */
125	#define RX_CHNL_CTRL 0x0d /* rw */
126	/*
127	0:7 24:31 IRQTimeout
128	8:15 16:23 IRQCount
129	16:20 11:15 Reserved
130	21 10 0
131	22 9 UseIntOnEnd
132	23 8 LdIRQCnt
133	24 7 IRQEn
134	25:28 3:6 Reserved
135	29 2 IrqErrEn
136	30 1 IrqDlyEn
137	31 0 IrqCoalEn
138	*/
139	#define RX_IRQ_REG 0x0e /* rw */
140	#define IRQ_COAL (1 << 0)
141	#define IRQ_DLY (1 << 1)
142	#define IRQ_ERR (1 << 2)
143	#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
144	/*
145	0:7 24:31 DltTmrValue
146	8:15 16:23 ClscCntrValue
147	16:17 14:15 Reserved
148	18:21 10:13 ClscCnt
149	22:23 8:9 DlyCnt
150	24:28 3::7 Reserved
151	*/
152	#define RX_CHNL_STS 0x0f /* r */
153	#define CHNL_STS_ENGBUSY (1 << 1)
154	#define CHNL_STS_EOP (1 << 2)
155	#define CHNL_STS_SOP (1 << 3)
156	#define CHNL_STS_CMPLT (1 << 4)
157	#define CHNL_STS_SOE (1 << 5)
158	#define CHNL_STS_IOE (1 << 6)
159	#define CHNL_STS_ERR (1 << 7)
160
161	#define CHNL_STS_BSYWR (1 << 16)
162	#define CHNL_STS_CURPERR (1 << 17)
163	#define CHNL_STS_NXTPERR (1 << 18)
164	#define CHNL_STS_ADDRERR (1 << 19)
165	#define CHNL_STS_CMPERR (1 << 20)
166	#define CHNL_STS_TAILERR (1 << 21)
167	/*
168	0:9 22:31 Reserved
169	10 21 TailPErr
170	11 20 CmpErr
171	12 19 AddrErr
172	13 18 NxtPErr
173	14 17 CurPErr
174	15 16 BsyWr
175	16:23 8:15 Reserved
176	24 7 Error
177	25 6 IOE
178	26 5 SOE
179	27 4 Cmplt
180	28 3 SOP
181	29 2 EOP
182	30 1 EngBusy
183	31 0 Reserved
184	*/
185
186	#define DMA_CONTROL_REG 0x10 /* rw */
187	#define DMA_CONTROL_RST (1 << 0)
188	#define DMA_TAIL_ENABLE (1 << 2)
189
190	/* XPS_LL_TEMAC direct registers definition */
191
192	#define XTE_RAF0_OFFSET 0x00
193	#define RAF0_RST (1 << 0)
194	#define RAF0_MCSTREJ (1 << 1)
195	#define RAF0_BCSTREJ (1 << 2)
196	#define XTE_TPF0_OFFSET 0x04
197	#define XTE_IFGP0_OFFSET 0x08
198	#define XTE_ISR0_OFFSET 0x0c
199	#define ISR0_HARDACSCMPLT (1 << 0)
200	#define ISR0_AUTONEG (1 << 1)
201	#define ISR0_RXCMPLT (1 << 2)
202	#define ISR0_RXREJ (1 << 3)
203	#define ISR0_RXFIFOOVR (1 << 4)
204	#define ISR0_TXCMPLT (1 << 5)
205	#define ISR0_RXDCMLCK (1 << 6)
206
207	#define XTE_IPR0_OFFSET 0x10
208	#define XTE_IER0_OFFSET 0x14
209
210	#define XTE_MSW0_OFFSET 0x20
211	#define XTE_LSW0_OFFSET 0x24
212	#define XTE_CTL0_OFFSET 0x28
213	#define XTE_RDY0_OFFSET 0x2c
214
215	#define XTE_RSE_MIIM_RR_MASK 0x0002
216	#define XTE_RSE_MIIM_WR_MASK 0x0004
217	#define XTE_RSE_CFG_RR_MASK 0x0020
218	#define XTE_RSE_CFG_WR_MASK 0x0040
219	#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)
220
221	/* XPS_LL_TEMAC indirect registers offset definition */
222
223	#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */
224	#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */
225	#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */
226	#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */
227	#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */
228	#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */
229	#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */
230	#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */
231	#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */
232
233	#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */
234	#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */
235	#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */
236	#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */
237	#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */
238	#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */
239	#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */
240
241	#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */
242	#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */
243	#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */
244
245	#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */
246	#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */
247	#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */
248	#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */
249	#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */
250	#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */
251
252	#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */
253	#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */
254	#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */
255	#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */
256
257	#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */
258	#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */
259	#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */
260	#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */
261
262	/* Interrupt Request status */
263	#define XTE_TIS_OFFSET 0x000003A0
264	#define TIS_FRIS (1 << 0)
265	#define TIS_MRIS (1 << 1)
266	#define TIS_MWIS (1 << 2)
267	#define TIS_ARIS (1 << 3)
268	#define TIS_AWIS (1 << 4)
269	#define TIS_CRIS (1 << 5)
270	#define TIS_CWIS (1 << 6)
271
272	#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */
273
274	/** MII Mamagement Control register (MGTCR) */
275	#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */
276	#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */
277
278	#define CNTLREG_WRITE_ENABLE_MASK 0x8000
279	#define CNTLREG_EMAC1SEL_MASK 0x0400
280	#define CNTLREG_ADDRESSCODE_MASK 0x03ff
281
282	/* CDMAC descriptor status bit definitions */
283
284	#define STS_CTRL_APP0_ERR (1 << 31)
285	#define STS_CTRL_APP0_IRQONEND (1 << 30)
286	/* undoccumented */
287	#define STS_CTRL_APP0_STOPONEND (1 << 29)
288	#define STS_CTRL_APP0_CMPLT (1 << 28)
289	#define STS_CTRL_APP0_SOP (1 << 27)
290	#define STS_CTRL_APP0_EOP (1 << 26)
291	#define STS_CTRL_APP0_ENGBUSY (1 << 25)
292	/* undocumented */
293	#define STS_CTRL_APP0_ENGRST (1 << 24)
294
295	#define TX_CONTROL_CALC_CSUM_MASK 1
296
92744989 GL	297	#define MULTICAST_CAM_TABLE_NUM 4
92744989 GL	298
23ecc4bd BH	299	/* TEMAC Synthesis features */
	300	#define TEMAC_FEATURE_RX_CSUM (1 << 0)
	301	#define TEMAC_FEATURE_TX_CSUM (1 << 1)
	302
92744989 GL	303	/* TX/RX CURDESC_PTR points to first descriptor */
	304	/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
	305
	306	/**
	307	* struct cdmac_bd - LocalLink buffer descriptor format
	308	*
	309	* app0 bits:
	310	* 0 Error
	311	* 1 IrqOnEnd generate an interrupt at completion of DMA op
	312	* 2 reserved
	313	* 3 completed Current descriptor completed
	314	* 4 SOP TX - marks first desc/ RX marks first desct
	315	* 5 EOP TX marks last desc/RX marks last desc
	316	* 6 EngBusy DMA is processing
	317	* 7 reserved
	318	* 8:31 application specific
	319	*/
	320	struct cdmac_bd {
	321	u32 next; /* Physical address of next buffer descriptor */
	322	u32 phys;
	323	u32 len;
	324	u32 app0;
	325	u32 app1; /* TX start << 16 \| insert */
	326	u32 app2; /* TX csum */
	327	u32 app3;
	328	u32 app4; /* skb for TX length for RX */
	329	};
	330
	331	struct temac_local {
	332	struct net_device *ndev;
	333	struct device *dev;
	334
	335	/* Connection to PHY device */
92744989 GL	336	struct device_node *phy_node;
	337
	338	/* MDIO bus data */
	339	struct mii_bus mii_bus; / MII bus reference */
92744989	340
e44171f1	341	/* IO registers, dma functions and IRQs */
92744989	342	void __iomem *regs;
e44171f1 JL	343	void __iomem *sdma_regs;
e44171f1 JL	344	#ifdef CONFIG_PPC_DCR
92744989	345	dcr_host_t sdma_dcrs;
e44171f1 JL	346	#endif
	347	u32 (dma_in)(struct temac_local , int);
	348	void (dma_out)(struct temac_local , int, u32);
	349
92744989 GL	350	int tx_irq;
	351	int rx_irq;
	352	int emac_num;
	353
	354	struct sk_buff **rx_skb;
	355	spinlock_t rx_lock;
	356	struct mutex indirect_mutex;
	357	u32 options; /* Current options word */
	358	int last_link;
23ecc4bd	359	unsigned int temac_features;
92744989 GL	360
	361	/* Buffer descriptors */
	362	struct cdmac_bd *tx_bd_v;
	363	dma_addr_t tx_bd_p;
	364	struct cdmac_bd *rx_bd_v;
	365	dma_addr_t rx_bd_p;
	366	int tx_bd_ci;
	367	int tx_bd_next;
	368	int tx_bd_tail;
	369	int rx_bd_ci;
	370	};
	371
	372	/* xilinx_temac.c */
	373	u32 temac_ior(struct temac_local *lp, int offset);
	374	void temac_iow(struct temac_local *lp, int offset, u32 value);
	375	int temac_indirect_busywait(struct temac_local *lp);
	376	u32 temac_indirect_in32(struct temac_local *lp, int reg);
	377	void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
	378
	379
	380	/* xilinx_temac_mdio.c */
	381	int temac_mdio_setup(struct temac_local lp, struct device_node np);
	382	void temac_mdio_teardown(struct temac_local *lp);
	383
	384	#endif /* XILINX_LL_TEMAC_H */