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09c434b8 1// SPDX-License-Identifier: GPL-2.0-only
92744989
GL		 2/*
3 * Driver for Xilinx TEMAC Ethernet device
4 *
5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 *
9 * This is a driver for the Xilinx ll_temac ipcore which is often used
10 * in the Virtex and Spartan series of chips.
11 *
12 * Notes:
13 * - The ll_temac hardware uses indirect access for many of the TEMAC
14 * registers, include the MDIO bus. However, indirect access to MDIO
15 * registers take considerably more clock cycles than to TEMAC registers.
16 * MDIO accesses are long, so threads doing them should probably sleep
17 * rather than busywait. However, since only one indirect access can be
18 * in progress at any given time, that means that *all* indirect accesses
19 * could end up sleeping (to wait for an MDIO access to complete).
20 * Fortunately none of the indirect accesses are on the 'hot' path for tx
21 * or rx, so this should be okay.
22 *
23 * TODO:
92744989
GL		 24 * - Factor out locallink DMA code into separate driver
25 * - Fix multicast assignment.
26 * - Fix support for hardware checksumming.
27 * - Testing. Lots and lots of testing.
28 *
29 */
30
31#include <linux/delay.h>
32#include <linux/etherdevice.h>
92744989
GL		 33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
8425c41d 37#include <linux/if_ether.h>
92744989
GL		 38#include <linux/of.h>
39#include <linux/of_device.h>
5c9f303e 40#include <linux/of_irq.h>
92744989 41#include <linux/of_mdio.h>
06205472 42#include <linux/of_net.h>
92744989 43#include <linux/of_platform.h>
9f1a1fca 44#include <linux/of_address.h>
92744989
GL		 45#include <linux/skbuff.h>
46#include <linux/spinlock.h>
47#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
48#include <linux/udp.h> /* needed for sizeof(udphdr) */
49#include <linux/phy.h>
50#include <linux/in.h>
51#include <linux/io.h>
52#include <linux/ip.h>
5a0e3ad6 53#include <linux/slab.h>
ffbc03bc 54#include <linux/interrupt.h>
84cac398 55#include <linux/dma-mapping.h>
8425c41d 56#include <linux/platform_data/xilinx-ll-temac.h>
92744989
GL		 57
58#include "ll_temac.h"
59
60#define TX_BD_NUM 64
61#define RX_BD_NUM 128
62
63/* ---------------------------------------------------------------------
64 * Low level register access functions
65 */
66
6e05b833 67static u32 _temac_ior_be(struct temac_local *lp, int offset)
92744989 68{
a3246dc4 69 return ioread32be(lp->regs + offset);
92744989
GL		 70}
71
6e05b833 72static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
92744989 73{
a3246dc4
EH		 74 return iowrite32be(value, lp->regs + offset);
75}
76
6e05b833 77static u32 _temac_ior_le(struct temac_local *lp, int offset)
a3246dc4
EH		 78{
79 return ioread32(lp->regs + offset);
80}
81
6e05b833 82static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
a3246dc4
EH		 83{
84 return iowrite32(value, lp->regs + offset);
92744989
GL		 85}
86
87int temac_indirect_busywait(struct temac_local *lp)
88{
9f8b93cb 89 unsigned long end = jiffies + 2;
92744989
GL		 90
91 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
3aeea53f 92 if (time_before_eq(end, jiffies)) {
92744989
GL		 93 WARN_ON(1);
94 return -ETIMEDOUT;
95 }
901d14ab 96 usleep_range(500, 1000);
92744989
GL		 97 }
98 return 0;
99}
100
101/**
102 * temac_indirect_in32
103 *
104 * lp->indirect_mutex must be held when calling this function
105 */
106u32 temac_indirect_in32(struct temac_local *lp, int reg)
107{
108 u32 val;
109
110 if (temac_indirect_busywait(lp))
111 return -ETIMEDOUT;
112 temac_iow(lp, XTE_CTL0_OFFSET, reg);
113 if (temac_indirect_busywait(lp))
114 return -ETIMEDOUT;
115 val = temac_ior(lp, XTE_LSW0_OFFSET);
116
117 return val;
118}
119
120/**
121 * temac_indirect_out32
122 *
123 * lp->indirect_mutex must be held when calling this function
124 */
125void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
126{
127 if (temac_indirect_busywait(lp))
128 return;
129 temac_iow(lp, XTE_LSW0_OFFSET, value);
130 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
f79d7e6f 131 temac_indirect_busywait(lp);
92744989
GL		 132}
133
e44171f1 134/**
a3246dc4
EH		 135 * temac_dma_in32_* - Memory mapped DMA read, these function expects a
136 * register input that is based on DCR word addresses which are then
137 * converted to memory mapped byte addresses. To be assigned to
138 * lp->dma_in32.
e44171f1 139 */
a3246dc4 140static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
92744989 141{
a3246dc4
EH		 142 return ioread32be(lp->sdma_regs + (reg << 2));
143}
144
145static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
146{
147 return ioread32(lp->sdma_regs + (reg << 2));
92744989
GL		 148}
149
e44171f1 150/**
a3246dc4
EH		 151 * temac_dma_out32_* - Memory mapped DMA read, these function expects
152 * a register input that is based on DCR word addresses which are then
153 * converted to memory mapped byte addresses. To be assigned to
154 * lp->dma_out32.
e44171f1 155 */
a3246dc4
EH		 156static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
157{
158 iowrite32be(value, lp->sdma_regs + (reg << 2));
159}
160
161static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
e44171f1 162{
a3246dc4 163 iowrite32(value, lp->sdma_regs + (reg << 2));
e44171f1
JL		 164}
165
166/* DMA register access functions can be DCR based or memory mapped.
167 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
168 * memory mapped.
169 */
170#ifdef CONFIG_PPC_DCR
171
172/**
173 * temac_dma_dcr_in32 - DCR based DMA read
174 */
175static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
176{
177 return dcr_read(lp->sdma_dcrs, reg);
178}
179
180/**
181 * temac_dma_dcr_out32 - DCR based DMA write
182 */
183static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 184{
185 dcr_write(lp->sdma_dcrs, reg, value);
186}
187
e44171f1
JL		 188/**
189 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
190 * I/O functions
191 */
2dc11581 192static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 193 struct device_node *np)
194{
195 unsigned int dcrs;
196
197 /* setup the dcr address mapping if it's in the device tree */
198
199 dcrs = dcr_resource_start(np, 0);
200 if (dcrs != 0) {
201 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
202 lp->dma_in = temac_dma_dcr_in;
203 lp->dma_out = temac_dma_dcr_out;
204 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
205 return 0;
206 }
207 /* no DCR in the device tree, indicate a failure */
208 return -1;
209}
210
211#else
212
213/*
214 * temac_dcr_setup - This is a stub for when DCR is not supported,
8425c41d 215 * such as with MicroBlaze and x86
e44171f1 216 */
2dc11581 217static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 218 struct device_node *np)
219{
220 return -1;
221}
222
223#endif
224
301e9d96 225/**
49ce9c2c 226 * temac_dma_bd_release - Release buffer descriptor rings
301e9d96
DK		 227 */
228static void temac_dma_bd_release(struct net_device *ndev)
229{
230 struct temac_local *lp = netdev_priv(ndev);
231 int i;
232
50ec1538
RR		 233 /* Reset Local Link (DMA) */
234 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
235
301e9d96
DK		 236 for (i = 0; i < RX_BD_NUM; i++) {
237 if (!lp->rx_skb[i])
238 break;
239 else {
240 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
241 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
242 dev_kfree_skb(lp->rx_skb[i]);
243 }
244 }
245 if (lp->rx_bd_v)
246 dma_free_coherent(ndev->dev.parent,
247 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
248 lp->rx_bd_v, lp->rx_bd_p);
249 if (lp->tx_bd_v)
250 dma_free_coherent(ndev->dev.parent,
251 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
252 lp->tx_bd_v, lp->tx_bd_p);
301e9d96
DK		 253}
254
92744989
GL		 255/**
256 * temac_dma_bd_init - Setup buffer descriptor rings
257 */
258static int temac_dma_bd_init(struct net_device *ndev)
259{
260 struct temac_local *lp = netdev_priv(ndev);
261 struct sk_buff *skb;
fdd7454e 262 dma_addr_t skb_dma_addr;
92744989
GL		 263 int i;
264
a63625d2
EH		 265 lp->rx_skb = devm_kcalloc(&ndev->dev, RX_BD_NUM, sizeof(*lp->rx_skb),
266 GFP_KERNEL);
b2adaca9 267 if (!lp->rx_skb)
fe62c298 268 goto out;
b2adaca9 269
92744989 270 /* allocate the tx and rx ring buffer descriptors. */
b595076a 271 /* returns a virtual address and a physical address. */
750afb08
LC		 272 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
273 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
274 &lp->tx_bd_p, GFP_KERNEL);
d0320f75 275 if (!lp->tx_bd_v)
fe62c298 276 goto out;
d0320f75 277
750afb08
LC		 278 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
279 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
280 &lp->rx_bd_p, GFP_KERNEL);
d0320f75 281 if (!lp->rx_bd_v)
fe62c298 282 goto out;
92744989 283
92744989 284 for (i = 0; i < TX_BD_NUM; i++) {
fdd7454e
EH		 285 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
286 + sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM));
92744989
GL		 287 }
288
92744989 289 for (i = 0; i < RX_BD_NUM; i++) {
fdd7454e
EH		 290 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
291 + sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM));
92744989 292
e44171f1
JL		 293 skb = netdev_alloc_skb_ip_align(ndev,
294 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 295 if (!skb)
fe62c298 296 goto out;
720a43ef 297
92744989 298 lp->rx_skb[i] = skb;
92744989 299 /* returns physical address of skb->data */
fdd7454e
EH		 300 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
301 XTE_MAX_JUMBO_FRAME_SIZE,
302 DMA_FROM_DEVICE);
303 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
304 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
305 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
92744989
GL		 306 }
307
7e97a194
EH		 308 /* Configure DMA channel (irq setup) */
309 lp->dma_out(lp, TX_CHNL_CTRL, lp->tx_chnl_ctrl |
310 0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
311 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
312 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
313 lp->dma_out(lp, RX_CHNL_CTRL, lp->rx_chnl_ctrl |
314 CHNL_CTRL_IRQ_IOE |
315 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
316 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
92744989 317
7167cf0e
RR		 318 /* Init descriptor indexes */
319 lp->tx_bd_ci = 0;
320 lp->tx_bd_next = 0;
321 lp->tx_bd_tail = 0;
322 lp->rx_bd_ci = 0;
323
73f7375d
EH		 324 /* Enable RX DMA transfers */
325 wmb();
326 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
327 lp->dma_out(lp, RX_TAILDESC_PTR,
328 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
329
330 /* Prepare for TX DMA transfer */
331 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
332
92744989 333 return 0;
fe62c298
DK		 334
335out:
301e9d96 336 temac_dma_bd_release(ndev);
fe62c298 337 return -ENOMEM;
92744989
GL		 338}
339
340/* ---------------------------------------------------------------------
341 * net_device_ops
342 */
343
04e406dc 344static void temac_do_set_mac_address(struct net_device *ndev)
92744989
GL		 345{
346 struct temac_local *lp = netdev_priv(ndev);
347
92744989 348 /* set up unicast MAC address filter set its mac address */
f14f5c11 349 mutex_lock(lp->indirect_mutex);
92744989
GL		 350 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
351 (ndev->dev_addr[0]) |
352 (ndev->dev_addr[1] << 8) |
353 (ndev->dev_addr[2] << 16) |
354 (ndev->dev_addr[3] << 24));
355 /* There are reserved bits in EUAW1
356 * so don't affect them Set MAC bits [47:32] in EUAW1 */
357 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
358 (ndev->dev_addr[4] & 0x000000ff) |
359 (ndev->dev_addr[5] << 8));
f14f5c11 360 mutex_unlock(lp->indirect_mutex);
04e406dc 361}
92744989 362
06205472 363static int temac_init_mac_address(struct net_device *ndev, const void *address)
04e406dc 364{
2d2924af 365 ether_addr_copy(ndev->dev_addr, address);
04e406dc
JP		 366 if (!is_valid_ether_addr(ndev->dev_addr))
367 eth_hw_addr_random(ndev);
368 temac_do_set_mac_address(ndev);
92744989
GL		 369 return 0;
370}
371
04e406dc 372static int temac_set_mac_address(struct net_device *ndev, void *p)
8ea7a37c
SM		 373{
374 struct sockaddr *addr = p;
375
04e406dc
JP		 376 if (!is_valid_ether_addr(addr->sa_data))
377 return -EADDRNOTAVAIL;
378 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
379 temac_do_set_mac_address(ndev);
380 return 0;
8ea7a37c
SM		 381}
382
92744989
GL		 383static void temac_set_multicast_list(struct net_device *ndev)
384{
385 struct temac_local *lp = netdev_priv(ndev);
386 u32 multi_addr_msw, multi_addr_lsw, val;
387 int i;
388
f14f5c11 389 mutex_lock(lp->indirect_mutex);
8e95a202 390 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 391 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 392 /*
393 * We must make the kernel realise we had to move
394 * into promisc mode or we start all out war on
395 * the cable. If it was a promisc request the
396 * flag is already set. If not we assert it.
397 */
398 ndev->flags |= IFF_PROMISC;
399 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
400 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 401 } else if (!netdev_mc_empty(ndev)) {
22bedad3 402 struct netdev_hw_addr *ha;
92744989 403
f9dcbcc9 404 i = 0;
22bedad3 405 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 406 if (i >= MULTICAST_CAM_TABLE_NUM)
407 break;
22bedad3
JP		 408 multi_addr_msw = ((ha->addr[3] << 24) |
409 (ha->addr[2] << 16) |
410 (ha->addr[1] << 8) |
411 (ha->addr[0]));
92744989
GL		 412 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
413 multi_addr_msw);
22bedad3
JP		 414 multi_addr_lsw = ((ha->addr[5] << 8) |
415 (ha->addr[4]) | (i << 16));
92744989
GL		 416 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
417 multi_addr_lsw);
f9dcbcc9 418 i++;
92744989
GL		 419 }
420 } else {
421 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
422 temac_indirect_out32(lp, XTE_AFM_OFFSET,
423 val & ~XTE_AFM_EPPRM_MASK);
424 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
425 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
426 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
427 }
f14f5c11 428 mutex_unlock(lp->indirect_mutex);
92744989
GL		 429}
430
84ea0ded 431static struct temac_option {
92744989
GL		 432 int flg;
433 u32 opt;
434 u32 reg;
435 u32 m_or;
436 u32 m_and;
437} temac_options[] = {
438 /* Turn on jumbo packet support for both Rx and Tx */
439 {
440 .opt = XTE_OPTION_JUMBO,
441 .reg = XTE_TXC_OFFSET,
442 .m_or = XTE_TXC_TXJMBO_MASK,
443 },
444 {
445 .opt = XTE_OPTION_JUMBO,
446 .reg = XTE_RXC1_OFFSET,
447 .m_or =XTE_RXC1_RXJMBO_MASK,
448 },
449 /* Turn on VLAN packet support for both Rx and Tx */
450 {
451 .opt = XTE_OPTION_VLAN,
452 .reg = XTE_TXC_OFFSET,
453 .m_or =XTE_TXC_TXVLAN_MASK,
454 },
455 {
456 .opt = XTE_OPTION_VLAN,
457 .reg = XTE_RXC1_OFFSET,
458 .m_or =XTE_RXC1_RXVLAN_MASK,
459 },
460 /* Turn on FCS stripping on receive packets */
461 {
462 .opt = XTE_OPTION_FCS_STRIP,
463 .reg = XTE_RXC1_OFFSET,
464 .m_or =XTE_RXC1_RXFCS_MASK,
465 },
466 /* Turn on FCS insertion on transmit packets */
467 {
468 .opt = XTE_OPTION_FCS_INSERT,
469 .reg = XTE_TXC_OFFSET,
470 .m_or =XTE_TXC_TXFCS_MASK,
471 },
472 /* Turn on length/type field checking on receive packets */
473 {
474 .opt = XTE_OPTION_LENTYPE_ERR,
475 .reg = XTE_RXC1_OFFSET,
476 .m_or =XTE_RXC1_RXLT_MASK,
477 },
478 /* Turn on flow control */
479 {
480 .opt = XTE_OPTION_FLOW_CONTROL,
481 .reg = XTE_FCC_OFFSET,
482 .m_or =XTE_FCC_RXFLO_MASK,
483 },
484 /* Turn on flow control */
485 {
486 .opt = XTE_OPTION_FLOW_CONTROL,
487 .reg = XTE_FCC_OFFSET,
488 .m_or =XTE_FCC_TXFLO_MASK,
489 },
490 /* Turn on promiscuous frame filtering (all frames are received ) */
491 {
492 .opt = XTE_OPTION_PROMISC,
493 .reg = XTE_AFM_OFFSET,
494 .m_or =XTE_AFM_EPPRM_MASK,
495 },
496 /* Enable transmitter if not already enabled */
497 {
498 .opt = XTE_OPTION_TXEN,
499 .reg = XTE_TXC_OFFSET,
500 .m_or =XTE_TXC_TXEN_MASK,
501 },
502 /* Enable receiver? */
503 {
504 .opt = XTE_OPTION_RXEN,
505 .reg = XTE_RXC1_OFFSET,
506 .m_or =XTE_RXC1_RXEN_MASK,
507 },
508 {}
509};
510
511/**
512 * temac_setoptions
513 */
514static u32 temac_setoptions(struct net_device *ndev, u32 options)
515{
516 struct temac_local *lp = netdev_priv(ndev);
517 struct temac_option *tp = &temac_options[0];
518 int reg;
519
f14f5c11 520 mutex_lock(lp->indirect_mutex);
92744989
GL		 521 while (tp->opt) {
522 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
523 if (options & tp->opt)
524 reg |= tp->m_or;
525 temac_indirect_out32(lp, tp->reg, reg);
526 tp++;
527 }
528 lp->options |= options;
f14f5c11 529 mutex_unlock(lp->indirect_mutex);
92744989 530
807540ba 531 return 0;
92744989
GL		 532}
533
421f91d2 534/* Initialize temac */
92744989
GL		 535static void temac_device_reset(struct net_device *ndev)
536{
537 struct temac_local *lp = netdev_priv(ndev);
538 u32 timeout;
539 u32 val;
540
541 /* Perform a software reset */
542
543 /* 0x300 host enable bit ? */
544 /* reset PHY through control register ?:1 */
545
546 dev_dbg(&ndev->dev, "%s()\n", __func__);
547
f14f5c11 548 mutex_lock(lp->indirect_mutex);
92744989
GL		 549 /* Reset the receiver and wait for it to finish reset */
550 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
551 timeout = 1000;
552 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
553 udelay(1);
554 if (--timeout == 0) {
555 dev_err(&ndev->dev,
556 "temac_device_reset RX reset timeout!!\n");
557 break;
558 }
559 }
560
561 /* Reset the transmitter and wait for it to finish reset */
562 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
563 timeout = 1000;
564 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
565 udelay(1);
566 if (--timeout == 0) {
567 dev_err(&ndev->dev,
568 "temac_device_reset TX reset timeout!!\n");
569 break;
570 }
571 }
572
573 /* Disable the receiver */
574 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
575 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
576
577 /* Reset Local Link (DMA) */
e44171f1 578 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 579 timeout = 1000;
e44171f1 580 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 581 udelay(1);
582 if (--timeout == 0) {
583 dev_err(&ndev->dev,
584 "temac_device_reset DMA reset timeout!!\n");
585 break;
586 }
587 }
e44171f1 588 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 589
fe62c298
DK		 590 if (temac_dma_bd_init(ndev)) {
591 dev_err(&ndev->dev,
592 "temac_device_reset descriptor allocation failed\n");
593 }
92744989
GL		 594
595 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
596 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
597 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
598 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
599
f14f5c11 600 mutex_unlock(lp->indirect_mutex);
92744989
GL		 601
602 /* Sync default options with HW
603 * but leave receiver and transmitter disabled. */
604 temac_setoptions(ndev,
605 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
606
04e406dc 607 temac_do_set_mac_address(ndev);
92744989
GL		 608
609 /* Set address filter table */
610 temac_set_multicast_list(ndev);
611 if (temac_setoptions(ndev, lp->options))
612 dev_err(&ndev->dev, "Error setting TEMAC options\n");
613
614 /* Init Driver variable */
860e9538 615 netif_trans_update(ndev); /* prevent tx timeout */
92744989
GL		 616}
617
84ea0ded 618static void temac_adjust_link(struct net_device *ndev)
92744989
GL		 619{
620 struct temac_local *lp = netdev_priv(ndev);
31abbe34 621 struct phy_device *phy = ndev->phydev;
92744989
GL		 622 u32 mii_speed;
623 int link_state;
624
625 /* hash together the state values to decide if something has changed */
626 link_state = phy->speed | (phy->duplex << 1) | phy->link;
627
f14f5c11 628 mutex_lock(lp->indirect_mutex);
92744989
GL		 629 if (lp->last_link != link_state) {
630 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
631 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
632
633 switch (phy->speed) {
634 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
635 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
636 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
637 }
638
639 /* Write new speed setting out to TEMAC */
640 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
641 lp->last_link = link_state;
642 phy_print_status(phy);
643 }
f14f5c11 644 mutex_unlock(lp->indirect_mutex);
92744989
GL		 645}
646
d84aec42
EH		 647#ifdef CONFIG_64BIT
648
6e05b833 649static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
d84aec42
EH		 650{
651 bd->app3 = (u32)(((u64)p) >> 32);
652 bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
653}
654
6e05b833 655static void *ptr_from_txbd(struct cdmac_bd *bd)
d84aec42
EH		 656{
657 return (void *)(((u64)(bd->app3) << 32) | bd->app4);
658}
659
660#else
661
6e05b833 662static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
d84aec42
EH		 663{
664 bd->app4 = (u32)p;
665}
666
6e05b833 667static void *ptr_from_txbd(struct cdmac_bd *bd)
d84aec42
EH		 668{
669 return (void *)(bd->app4);
670}
671
672#endif
673
92744989
GL		 674static void temac_start_xmit_done(struct net_device *ndev)
675{
676 struct temac_local *lp = netdev_priv(ndev);
677 struct cdmac_bd *cur_p;
678 unsigned int stat = 0;
d84aec42 679 struct sk_buff *skb;
92744989
GL		 680
681 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
fdd7454e 682 stat = be32_to_cpu(cur_p->app0);
92744989
GL		 683
684 while (stat & STS_CTRL_APP0_CMPLT) {
fdd7454e
EH		 685 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
686 be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
d84aec42
EH		 687 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
688 if (skb)
689 dev_consume_skb_irq(skb);
92744989 690 cur_p->app0 = 0;
23ecc4bd
BH		 691 cur_p->app1 = 0;
692 cur_p->app2 = 0;
693 cur_p->app3 = 0;
694 cur_p->app4 = 0;
92744989
GL		 695
696 ndev->stats.tx_packets++;
fdd7454e 697 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
92744989
GL		 698
699 lp->tx_bd_ci++;
700 if (lp->tx_bd_ci >= TX_BD_NUM)
701 lp->tx_bd_ci = 0;
702
703 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
fdd7454e 704 stat = be32_to_cpu(cur_p->app0);
92744989
GL		 705 }
706
707 netif_wake_queue(ndev);
708}
709
23ecc4bd
BH		 710static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
711{
712 struct cdmac_bd *cur_p;
713 int tail;
714
715 tail = lp->tx_bd_tail;
716 cur_p = &lp->tx_bd_v[tail];
717
718 do {
719 if (cur_p->app0)
720 return NETDEV_TX_BUSY;
721
722 tail++;
723 if (tail >= TX_BD_NUM)
724 tail = 0;
725
726 cur_p = &lp->tx_bd_v[tail];
727 num_frag--;
728 } while (num_frag >= 0);
729
730 return 0;
731}
732
81255af8
Y		 733static netdev_tx_t
734temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
92744989
GL		 735{
736 struct temac_local *lp = netdev_priv(ndev);
737 struct cdmac_bd *cur_p;
fdd7454e 738 dma_addr_t start_p, tail_p, skb_dma_addr;
92744989
GL		 739 int ii;
740 unsigned long num_frag;
741 skb_frag_t *frag;
742
743 num_frag = skb_shinfo(skb)->nr_frags;
744 frag = &skb_shinfo(skb)->frags[0];
745 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
746 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
747
2c9938e7 748 if (temac_check_tx_bd_space(lp, num_frag + 1)) {
3824246d 749 if (!netif_queue_stopped(ndev))
92744989 750 netif_stop_queue(ndev);
92744989
GL		 751 return NETDEV_TX_BUSY;
752 }
753
754 cur_p->app0 = 0;
755 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 756 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 757 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
758
fdd7454e
EH		 759 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
760 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
761 | csum_index_off);
23ecc4bd 762 cur_p->app2 = 0; /* initial checksum seed */
92744989 763 }
23ecc4bd 764
fdd7454e
EH		 765 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
766 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
767 skb_headlen(skb), DMA_TO_DEVICE);
768 cur_p->len = cpu_to_be32(skb_headlen(skb));
769 cur_p->phys = cpu_to_be32(skb_dma_addr);
d84aec42 770 ptr_to_txbd((void *)skb, cur_p);
92744989
GL		 771
772 for (ii = 0; ii < num_frag; ii++) {
773 lp->tx_bd_tail++;
774 if (lp->tx_bd_tail >= TX_BD_NUM)
775 lp->tx_bd_tail = 0;
776
777 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
fdd7454e
EH		 778 skb_dma_addr = dma_map_single(ndev->dev.parent,
779 skb_frag_address(frag),
780 skb_frag_size(frag),
781 DMA_TO_DEVICE);
782 cur_p->phys = cpu_to_be32(skb_dma_addr);
783 cur_p->len = cpu_to_be32(skb_frag_size(frag));
92744989
GL		 784 cur_p->app0 = 0;
785 frag++;
786 }
fdd7454e 787 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
92744989
GL		 788
789 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
790 lp->tx_bd_tail++;
791 if (lp->tx_bd_tail >= TX_BD_NUM)
792 lp->tx_bd_tail = 0;
793
93e0ed15
RC		 794 skb_tx_timestamp(skb);
795
92744989 796 /* Kick off the transfer */
73f7375d 797 wmb();
e44171f1 798 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 799
6ed10654 800 return NETDEV_TX_OK;
92744989
GL		 801}
802
803
804static void ll_temac_recv(struct net_device *ndev)
805{
806 struct temac_local *lp = netdev_priv(ndev);
807 struct sk_buff *skb, *new_skb;
808 unsigned int bdstat;
809 struct cdmac_bd *cur_p;
fdd7454e 810 dma_addr_t tail_p, skb_dma_addr;
92744989 811 int length;
92744989
GL		 812 unsigned long flags;
813
814 spin_lock_irqsave(&lp->rx_lock, flags);
815
816 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
817 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
818
fdd7454e 819 bdstat = be32_to_cpu(cur_p->app0);
92744989
GL		 820 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
821
822 skb = lp->rx_skb[lp->rx_bd_ci];
fdd7454e 823 length = be32_to_cpu(cur_p->app4) & 0x3FFF;
92744989 824
fdd7454e 825 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
a8c9bd3b 826 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
92744989
GL		 827
828 skb_put(skb, length);
92744989 829 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 830 skb_checksum_none_assert(skb);
92744989 831
23ecc4bd
BH		 832 /* if we're doing rx csum offload, set it up */
833 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
ceffc4ac
JP		 834 (skb->protocol == htons(ETH_P_IP)) &&
835 (skb->len > 64)) {
23ecc4bd 836
fdd7454e
EH		 837 /* Convert from device endianness (be32) to cpu
838 * endiannes, and if necessary swap the bytes
839 * (back) for proper IP checksum byte order
840 * (be16).
841 */
842 skb->csum = htons(be32_to_cpu(cur_p->app3) & 0xFFFF);
23ecc4bd
BH		 843 skb->ip_summed = CHECKSUM_COMPLETE;
844 }
845
93e0ed15
RC		 846 if (!skb_defer_rx_timestamp(skb))
847 netif_rx(skb);
92744989
GL		 848
849 ndev->stats.rx_packets++;
850 ndev->stats.rx_bytes += length;
851
e44171f1
JL		 852 new_skb = netdev_alloc_skb_ip_align(ndev,
853 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 854 if (!new_skb) {
92744989
GL		 855 spin_unlock_irqrestore(&lp->rx_lock, flags);
856 return;
857 }
858
fdd7454e
EH		 859 cur_p->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
860 skb_dma_addr = dma_map_single(ndev->dev.parent, new_skb->data,
861 XTE_MAX_JUMBO_FRAME_SIZE,
862 DMA_FROM_DEVICE);
863 cur_p->phys = cpu_to_be32(skb_dma_addr);
864 cur_p->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
92744989
GL		 865 lp->rx_skb[lp->rx_bd_ci] = new_skb;
866
867 lp->rx_bd_ci++;
868 if (lp->rx_bd_ci >= RX_BD_NUM)
869 lp->rx_bd_ci = 0;
870
871 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
fdd7454e 872 bdstat = be32_to_cpu(cur_p->app0);
92744989 873 }
e44171f1 874 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 875
876 spin_unlock_irqrestore(&lp->rx_lock, flags);
877}
878
879static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
880{
881 struct net_device *ndev = _ndev;
882 struct temac_local *lp = netdev_priv(ndev);
883 unsigned int status;
884
e44171f1
JL		 885 status = lp->dma_in(lp, TX_IRQ_REG);
886 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 887
888 if (status & (IRQ_COAL | IRQ_DLY))
889 temac_start_xmit_done(lp->ndev);
5db9c740
EH		 890 if (status & (IRQ_ERR | IRQ_DMAERR))
891 dev_err_ratelimited(&ndev->dev,
892 "TX error 0x%x TX_CHNL_STS=0x%08x\n",
893 status, lp->dma_in(lp, TX_CHNL_STS));
92744989
GL		 894
895 return IRQ_HANDLED;
896}
897
898static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
899{
900 struct net_device *ndev = _ndev;
901 struct temac_local *lp = netdev_priv(ndev);
902 unsigned int status;
903
904 /* Read and clear the status registers */
e44171f1
JL		 905 status = lp->dma_in(lp, RX_IRQ_REG);
906 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 907
908 if (status & (IRQ_COAL | IRQ_DLY))
909 ll_temac_recv(lp->ndev);
5db9c740
EH		 910 if (status & (IRQ_ERR | IRQ_DMAERR))
911 dev_err_ratelimited(&ndev->dev,
912 "RX error 0x%x RX_CHNL_STS=0x%08x\n",
913 status, lp->dma_in(lp, RX_CHNL_STS));
92744989
GL		 914
915 return IRQ_HANDLED;
916}
917
918static int temac_open(struct net_device *ndev)
919{
920 struct temac_local *lp = netdev_priv(ndev);
31abbe34 921 struct phy_device *phydev = NULL;
92744989
GL		 922 int rc;
923
924 dev_dbg(&ndev->dev, "temac_open()\n");
925
926 if (lp->phy_node) {
31abbe34
PR		 927 phydev = of_phy_connect(lp->ndev, lp->phy_node,
928 temac_adjust_link, 0, 0);
929 if (!phydev) {
92744989
GL		 930 dev_err(lp->dev, "of_phy_connect() failed\n");
931 return -ENODEV;
932 }
8425c41d
EH		 933 phy_start(phydev);
934 } else if (strlen(lp->phy_name) > 0) {
935 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
936 lp->phy_interface);
1ffc4b7c 937 if (IS_ERR(phydev)) {
8425c41d 938 dev_err(lp->dev, "phy_connect() failed\n");
1ffc4b7c 939 return PTR_ERR(phydev);
8425c41d 940 }
31abbe34 941 phy_start(phydev);
92744989
GL		 942 }
943
50ec1538
RR		 944 temac_device_reset(ndev);
945
92744989
GL		 946 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
947 if (rc)
948 goto err_tx_irq;
949 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
950 if (rc)
951 goto err_rx_irq;
952
92744989
GL		 953 return 0;
954
955 err_rx_irq:
956 free_irq(lp->tx_irq, ndev);
957 err_tx_irq:
31abbe34
PR		 958 if (phydev)
959 phy_disconnect(phydev);
92744989
GL		 960 dev_err(lp->dev, "request_irq() failed\n");
961 return rc;
962}
963
964static int temac_stop(struct net_device *ndev)
965{
966 struct temac_local *lp = netdev_priv(ndev);
31abbe34 967 struct phy_device *phydev = ndev->phydev;
92744989
GL		 968
969 dev_dbg(&ndev->dev, "temac_close()\n");
970
971 free_irq(lp->tx_irq, ndev);
972 free_irq(lp->rx_irq, ndev);
973
31abbe34
PR		 974 if (phydev)
975 phy_disconnect(phydev);
92744989 976
301e9d96
DK		 977 temac_dma_bd_release(ndev);
978
92744989
GL		 979 return 0;
980}
981
982#ifdef CONFIG_NET_POLL_CONTROLLER
983static void
984temac_poll_controller(struct net_device *ndev)
985{
986 struct temac_local *lp = netdev_priv(ndev);
987
988 disable_irq(lp->tx_irq);
989 disable_irq(lp->rx_irq);
990
8539992f
MS		 991 ll_temac_rx_irq(lp->tx_irq, ndev);
992 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 993
994 enable_irq(lp->tx_irq);
995 enable_irq(lp->rx_irq);
996}
997#endif
998
8d8bdfe8
RR		 999static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1000{
8d8bdfe8
RR		 1001 if (!netif_running(ndev))
1002 return -EINVAL;
1003
31abbe34 1004 if (!ndev->phydev)
8d8bdfe8
RR		 1005 return -EINVAL;
1006
31abbe34 1007 return phy_mii_ioctl(ndev->phydev, rq, cmd);
8d8bdfe8
RR		 1008}
1009
92744989
GL		 1010static const struct net_device_ops temac_netdev_ops = {
1011 .ndo_open = temac_open,
1012 .ndo_stop = temac_stop,
1013 .ndo_start_xmit = temac_start_xmit,
04e406dc 1014 .ndo_set_mac_address = temac_set_mac_address,
60eb5fd1 1015 .ndo_validate_addr = eth_validate_addr,
8d8bdfe8 1016 .ndo_do_ioctl = temac_ioctl,
92744989
GL		 1017#ifdef CONFIG_NET_POLL_CONTROLLER
1018 .ndo_poll_controller = temac_poll_controller,
1019#endif
1020};
1021
1022/* ---------------------------------------------------------------------
1023 * SYSFS device attributes
1024 */
1025static ssize_t temac_show_llink_regs(struct device *dev,
1026 struct device_attribute *attr, char *buf)
1027{
1028 struct net_device *ndev = dev_get_drvdata(dev);
1029 struct temac_local *lp = netdev_priv(ndev);
1030 int i, len = 0;
1031
1032 for (i = 0; i < 0x11; i++)
e44171f1 1033 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 1034 (i % 8) == 7 ? "\n" : " ");
1035 len += sprintf(buf + len, "\n");
1036
1037 return len;
1038}
1039
1040static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1041
1042static struct attribute *temac_device_attrs[] = {
1043 &dev_attr_llink_regs.attr,
1044 NULL,
1045};
1046
1047static const struct attribute_group temac_attr_group = {
1048 .attrs = temac_device_attrs,
1049};
1050
9eac2d4d 1051/* ethtool support */
9eac2d4d 1052static const struct ethtool_ops temac_ethtool_ops = {
16250527 1053 .nway_reset = phy_ethtool_nway_reset,
9eac2d4d 1054 .get_link = ethtool_op_get_link,
f85e5ea2 1055 .get_ts_info = ethtool_op_get_ts_info,
e6dab902
PR		 1056 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1057 .set_link_ksettings = phy_ethtool_set_link_ksettings,
9eac2d4d
RR		 1058};
1059
8425c41d 1060static int temac_probe(struct platform_device *pdev)
92744989 1061{
8425c41d
EH		 1062 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1063 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
92744989
GL		 1064 struct temac_local *lp;
1065 struct net_device *ndev;
8425c41d 1066 struct resource *res;
92744989 1067 const void *addr;
23ecc4bd 1068 __be32 *p;
a3246dc4 1069 bool little_endian;
06205472 1070 int rc = 0;
92744989
GL		 1071
1072 /* Init network device structure */
a63625d2 1073 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
41de8d4c 1074 if (!ndev)
92744989 1075 return -ENOMEM;
41de8d4c 1076
8425c41d
EH		 1077 platform_set_drvdata(pdev, ndev);
1078 SET_NETDEV_DEV(ndev, &pdev->dev);
92744989 1079 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
28e24c62 1080 ndev->features = NETIF_F_SG;
92744989 1081 ndev->netdev_ops = &temac_netdev_ops;
9eac2d4d 1082 ndev->ethtool_ops = &temac_ethtool_ops;
92744989
GL		 1083#if 0
1084 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1085 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1086 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1087 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
f646968f
PM		 1088 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1089 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1090 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
92744989
GL		 1091 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1092 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1093 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1094 ndev->features |= NETIF_F_LRO; /* large receive offload */
1095#endif
1096
1097 /* setup temac private info structure */
1098 lp = netdev_priv(ndev);
1099 lp->ndev = ndev;
8425c41d 1100 lp->dev = &pdev->dev;
92744989
GL		 1101 lp->options = XTE_OPTION_DEFAULTS;
1102 spin_lock_init(&lp->rx_lock);
f14f5c11
EH		 1103
1104 /* Setup mutex for synchronization of indirect register access */
1105 if (pdata) {
1106 if (!pdata->indirect_mutex) {
1107 dev_err(&pdev->dev,
1108 "indirect_mutex missing in platform_data\n");
1109 return -EINVAL;
1110 }
1111 lp->indirect_mutex = pdata->indirect_mutex;
1112 } else {
1113 lp->indirect_mutex = devm_kmalloc(&pdev->dev,
1114 sizeof(*lp->indirect_mutex),
1115 GFP_KERNEL);
1116 mutex_init(lp->indirect_mutex);
1117 }
92744989
GL		 1118
1119 /* map device registers */
8425c41d
EH		 1120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 lp->regs = devm_ioremap_nocache(&pdev->dev, res->start,
1122 resource_size(res));
1123 if (IS_ERR(lp->regs)) {
1124 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1125 return PTR_ERR(lp->regs);
92744989
GL		 1126 }
1127
a3246dc4
EH		 1128 /* Select register access functions with the specified
1129 * endianness mode. Default for OF devices is big-endian.
1130 */
1131 little_endian = false;
1132 if (temac_np) {
1133 if (of_get_property(temac_np, "little-endian", NULL))
1134 little_endian = true;
1135 } else if (pdata) {
1136 little_endian = pdata->reg_little_endian;
1137 }
1138 if (little_endian) {
1139 lp->temac_ior = _temac_ior_le;
1140 lp->temac_iow = _temac_iow_le;
1141 } else {
1142 lp->temac_ior = _temac_ior_be;
1143 lp->temac_iow = _temac_iow_be;
1144 }
1145
23ecc4bd
BH		 1146 /* Setup checksum offload, but default to off if not specified */
1147 lp->temac_features = 0;
8425c41d
EH		 1148 if (temac_np) {
1149 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1150 if (p && be32_to_cpu(*p))
1151 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1152 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1153 if (p && be32_to_cpu(*p))
1154 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1155 } else if (pdata) {
1156 if (pdata->txcsum)
1157 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1158 if (pdata->rxcsum)
1159 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1160 }
1161 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
23ecc4bd
BH		 1162 /* Can checksum TCP/UDP over IPv4. */
1163 ndev->features |= NETIF_F_IP_CSUM;
92744989 1164
8425c41d
EH		 1165 /* Setup LocalLink DMA */
1166 if (temac_np) {
1167 /* Find the DMA node, map the DMA registers, and
1168 * decode the DMA IRQs.
1169 */
1170 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1171 if (!dma_np) {
1172 dev_err(&pdev->dev, "could not find DMA node\n");
1173 return -ENODEV;
1174 }
e44171f1 1175
8425c41d
EH		 1176 /* Setup the DMA register accesses, could be DCR or
1177 * memory mapped.
1178 */
1179 if (temac_dcr_setup(lp, pdev, dma_np)) {
1180 /* no DCR in the device tree, try non-DCR */
1181 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1182 NULL);
1183 if (IS_ERR(lp->sdma_regs)) {
1184 dev_err(&pdev->dev,
1185 "unable to map DMA registers\n");
1186 of_node_put(dma_np);
1187 return PTR_ERR(lp->sdma_regs);
1188 }
a3246dc4
EH		 1189 if (of_get_property(dma_np, "little-endian", NULL)) {
1190 lp->dma_in = temac_dma_in32_le;
1191 lp->dma_out = temac_dma_out32_le;
1192 } else {
1193 lp->dma_in = temac_dma_in32_be;
1194 lp->dma_out = temac_dma_out32_be;
1195 }
8425c41d 1196 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
e44171f1 1197 }
7cc36f6f 1198
8425c41d
EH		 1199 /* Get DMA RX and TX interrupts */
1200 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1201 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1202
7e97a194
EH		 1203 /* Use defaults for IRQ delay/coalescing setup. These
1204 * are configuration values, so does not belong in
1205 * device-tree.
1206 */
1207 lp->tx_chnl_ctrl = 0x10220000;
1208 lp->rx_chnl_ctrl = 0xff070000;
1209
8425c41d
EH		 1210 /* Finished with the DMA node; drop the reference */
1211 of_node_put(dma_np);
1212 } else if (pdata) {
1213 /* 2nd memory resource specifies DMA registers */
1214 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1215 lp->sdma_regs = devm_ioremap_nocache(&pdev->dev, res->start,
1216 resource_size(res));
1217 if (IS_ERR(lp->sdma_regs)) {
1218 dev_err(&pdev->dev,
1219 "could not map DMA registers\n");
1220 return PTR_ERR(lp->sdma_regs);
1221 }
a3246dc4
EH		 1222 if (pdata->dma_little_endian) {
1223 lp->dma_in = temac_dma_in32_le;
1224 lp->dma_out = temac_dma_out32_le;
1225 } else {
1226 lp->dma_in = temac_dma_in32_be;
1227 lp->dma_out = temac_dma_out32_be;
1228 }
7cc36f6f 1229
8425c41d
EH		 1230 /* Get DMA RX and TX interrupts */
1231 lp->rx_irq = platform_get_irq(pdev, 0);
1232 lp->tx_irq = platform_get_irq(pdev, 1);
7e97a194
EH		 1233
1234 /* IRQ delay/coalescing setup */
1235 if (pdata->tx_irq_timeout || pdata->tx_irq_count)
1236 lp->tx_chnl_ctrl = (pdata->tx_irq_timeout << 24) |
1237 (pdata->tx_irq_count << 16);
1238 else
1239 lp->tx_chnl_ctrl = 0x10220000;
1240 if (pdata->rx_irq_timeout || pdata->rx_irq_count)
1241 lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) |
1242 (pdata->rx_irq_count << 16);
1243 else
1244 lp->rx_chnl_ctrl = 0xff070000;
92744989
GL		 1245 }
1246
8425c41d
EH		 1247 /* Error handle returned DMA RX and TX interrupts */
1248 if (lp->rx_irq < 0) {
1249 if (lp->rx_irq != -EPROBE_DEFER)
1250 dev_err(&pdev->dev, "could not get DMA RX irq\n");
1251 return lp->rx_irq;
1252 }
1253 if (lp->tx_irq < 0) {
1254 if (lp->tx_irq != -EPROBE_DEFER)
1255 dev_err(&pdev->dev, "could not get DMA TX irq\n");
1256 return lp->tx_irq;
1257 }
92744989 1258
8425c41d
EH		 1259 if (temac_np) {
1260 /* Retrieve the MAC address */
1261 addr = of_get_mac_address(temac_np);
a51645f7 1262 if (IS_ERR(addr)) {
8425c41d
EH		 1263 dev_err(&pdev->dev, "could not find MAC address\n");
1264 return -ENODEV;
1265 }
1266 temac_init_mac_address(ndev, addr);
1267 } else if (pdata) {
1268 temac_init_mac_address(ndev, pdata->mac_addr);
92744989 1269 }
92744989 1270
a63625d2 1271 rc = temac_mdio_setup(lp, pdev);
92744989 1272 if (rc)
8425c41d
EH		 1273 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1274
1275 if (temac_np) {
1276 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1277 if (lp->phy_node)
1278 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1279 } else if (pdata) {
1280 snprintf(lp->phy_name, sizeof(lp->phy_name),
1281 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1282 lp->phy_interface = pdata->phy_interface;
1283 }
92744989
GL		 1284
1285 /* Add the device attributes */
1286 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1287 if (rc) {
1288 dev_err(lp->dev, "Error creating sysfs files\n");
a63625d2 1289 goto err_sysfs_create;
92744989
GL		 1290 }
1291
1292 rc = register_netdev(lp->ndev);
1293 if (rc) {
1294 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1295 goto err_register_ndev;
1296 }
1297
1298 return 0;
1299
a63625d2 1300err_register_ndev:
92744989 1301 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
a63625d2 1302err_sysfs_create:
8425c41d
EH		 1303 if (lp->phy_node)
1304 of_node_put(lp->phy_node);
a63625d2 1305 temac_mdio_teardown(lp);
92744989
GL		 1306 return rc;
1307}
1308
8425c41d 1309static int temac_remove(struct platform_device *pdev)
92744989 1310{
8425c41d 1311 struct net_device *ndev = platform_get_drvdata(pdev);
92744989
GL		 1312 struct temac_local *lp = netdev_priv(ndev);
1313
92744989
GL		 1314 unregister_netdev(ndev);
1315 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
8425c41d
EH		 1316 if (lp->phy_node)
1317 of_node_put(lp->phy_node);
a63625d2 1318 temac_mdio_teardown(lp);
92744989
GL		 1319 return 0;
1320}
1321
74847f23 1322static const struct of_device_id temac_of_match[] = {
92744989 1323 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1324 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1325 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1326 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1327 {},
1328};
1329MODULE_DEVICE_TABLE(of, temac_of_match);
1330
8425c41d
EH		 1331static struct platform_driver temac_driver = {
1332 .probe = temac_probe,
1333 .remove = temac_remove,
92744989 1334 .driver = {
92744989 1335 .name = "xilinx_temac",
4018294b 1336 .of_match_table = temac_of_match,
92744989
GL		 1337 },
1338};
1339
8425c41d 1340module_platform_driver(temac_driver);
92744989
GL		 1341
1342MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1343MODULE_AUTHOR("Yoshio Kashiwagi");
1344MODULE_LICENSE("GPL");
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