]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/ethernet/xilinx/ll_temac_main.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: Add SPDX license identifier for missed files
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
CommitLineData
92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
92744989
GL		 32#include <linux/mii.h>
33#include <linux/module.h>
34#include <linux/mutex.h>
35#include <linux/netdevice.h>
8425c41d 36#include <linux/if_ether.h>
92744989
GL		 37#include <linux/of.h>
38#include <linux/of_device.h>
5c9f303e 39#include <linux/of_irq.h>
92744989 40#include <linux/of_mdio.h>
06205472 41#include <linux/of_net.h>
92744989 42#include <linux/of_platform.h>
9f1a1fca 43#include <linux/of_address.h>
92744989
GL		 44#include <linux/skbuff.h>
45#include <linux/spinlock.h>
46#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
47#include <linux/udp.h> /* needed for sizeof(udphdr) */
48#include <linux/phy.h>
49#include <linux/in.h>
50#include <linux/io.h>
51#include <linux/ip.h>
5a0e3ad6 52#include <linux/slab.h>
ffbc03bc 53#include <linux/interrupt.h>
84cac398 54#include <linux/dma-mapping.h>
8425c41d 55#include <linux/platform_data/xilinx-ll-temac.h>
92744989
GL		 56
57#include "ll_temac.h"
58
59#define TX_BD_NUM 64
60#define RX_BD_NUM 128
61
62/* ---------------------------------------------------------------------
63 * Low level register access functions
64 */
65
6e05b833 66static u32 _temac_ior_be(struct temac_local *lp, int offset)
92744989 67{
a3246dc4 68 return ioread32be(lp->regs + offset);
92744989
GL		 69}
70
6e05b833 71static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
92744989 72{
a3246dc4
EH		 73 return iowrite32be(value, lp->regs + offset);
74}
75
6e05b833 76static u32 _temac_ior_le(struct temac_local *lp, int offset)
a3246dc4
EH		 77{
78 return ioread32(lp->regs + offset);
79}
80
6e05b833 81static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
a3246dc4
EH		 82{
83 return iowrite32(value, lp->regs + offset);
92744989
GL		 84}
85
86int temac_indirect_busywait(struct temac_local *lp)
87{
9f8b93cb 88 unsigned long end = jiffies + 2;
92744989
GL		 89
90 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
3aeea53f 91 if (time_before_eq(end, jiffies)) {
92744989
GL		 92 WARN_ON(1);
93 return -ETIMEDOUT;
94 }
901d14ab 95 usleep_range(500, 1000);
92744989
GL		 96 }
97 return 0;
98}
99
100/**
101 * temac_indirect_in32
102 *
103 * lp->indirect_mutex must be held when calling this function
104 */
105u32 temac_indirect_in32(struct temac_local *lp, int reg)
106{
107 u32 val;
108
109 if (temac_indirect_busywait(lp))
110 return -ETIMEDOUT;
111 temac_iow(lp, XTE_CTL0_OFFSET, reg);
112 if (temac_indirect_busywait(lp))
113 return -ETIMEDOUT;
114 val = temac_ior(lp, XTE_LSW0_OFFSET);
115
116 return val;
117}
118
119/**
120 * temac_indirect_out32
121 *
122 * lp->indirect_mutex must be held when calling this function
123 */
124void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
125{
126 if (temac_indirect_busywait(lp))
127 return;
128 temac_iow(lp, XTE_LSW0_OFFSET, value);
129 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
f79d7e6f 130 temac_indirect_busywait(lp);
92744989
GL		 131}
132
e44171f1 133/**
a3246dc4
EH		 134 * temac_dma_in32_* - Memory mapped DMA read, these function expects a
135 * register input that is based on DCR word addresses which are then
136 * converted to memory mapped byte addresses. To be assigned to
137 * lp->dma_in32.
e44171f1 138 */
a3246dc4 139static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
92744989 140{
a3246dc4
EH		 141 return ioread32be(lp->sdma_regs + (reg << 2));
142}
143
144static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
145{
146 return ioread32(lp->sdma_regs + (reg << 2));
92744989
GL		 147}
148
e44171f1 149/**
a3246dc4
EH		 150 * temac_dma_out32_* - Memory mapped DMA read, these function expects
151 * a register input that is based on DCR word addresses which are then
152 * converted to memory mapped byte addresses. To be assigned to
153 * lp->dma_out32.
e44171f1 154 */
a3246dc4
EH		 155static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
156{
157 iowrite32be(value, lp->sdma_regs + (reg << 2));
158}
159
160static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
e44171f1 161{
a3246dc4 162 iowrite32(value, lp->sdma_regs + (reg << 2));
e44171f1
JL		 163}
164
165/* DMA register access functions can be DCR based or memory mapped.
166 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
167 * memory mapped.
168 */
169#ifdef CONFIG_PPC_DCR
170
171/**
172 * temac_dma_dcr_in32 - DCR based DMA read
173 */
174static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
175{
176 return dcr_read(lp->sdma_dcrs, reg);
177}
178
179/**
180 * temac_dma_dcr_out32 - DCR based DMA write
181 */
182static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 183{
184 dcr_write(lp->sdma_dcrs, reg, value);
185}
186
e44171f1
JL		 187/**
188 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
189 * I/O functions
190 */
2dc11581 191static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 192 struct device_node *np)
193{
194 unsigned int dcrs;
195
196 /* setup the dcr address mapping if it's in the device tree */
197
198 dcrs = dcr_resource_start(np, 0);
199 if (dcrs != 0) {
200 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
201 lp->dma_in = temac_dma_dcr_in;
202 lp->dma_out = temac_dma_dcr_out;
203 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
204 return 0;
205 }
206 /* no DCR in the device tree, indicate a failure */
207 return -1;
208}
209
210#else
211
212/*
213 * temac_dcr_setup - This is a stub for when DCR is not supported,
8425c41d 214 * such as with MicroBlaze and x86
e44171f1 215 */
2dc11581 216static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 217 struct device_node *np)
218{
219 return -1;
220}
221
222#endif
223
301e9d96 224/**
49ce9c2c 225 * temac_dma_bd_release - Release buffer descriptor rings
301e9d96
DK		 226 */
227static void temac_dma_bd_release(struct net_device *ndev)
228{
229 struct temac_local *lp = netdev_priv(ndev);
230 int i;
231
50ec1538
RR		 232 /* Reset Local Link (DMA) */
233 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
234
301e9d96
DK		 235 for (i = 0; i < RX_BD_NUM; i++) {
236 if (!lp->rx_skb[i])
237 break;
238 else {
239 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
240 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
241 dev_kfree_skb(lp->rx_skb[i]);
242 }
243 }
244 if (lp->rx_bd_v)
245 dma_free_coherent(ndev->dev.parent,
246 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
247 lp->rx_bd_v, lp->rx_bd_p);
248 if (lp->tx_bd_v)
249 dma_free_coherent(ndev->dev.parent,
250 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
251 lp->tx_bd_v, lp->tx_bd_p);
301e9d96
DK		 252}
253
92744989
GL		 254/**
255 * temac_dma_bd_init - Setup buffer descriptor rings
256 */
257static int temac_dma_bd_init(struct net_device *ndev)
258{
259 struct temac_local *lp = netdev_priv(ndev);
260 struct sk_buff *skb;
fdd7454e 261 dma_addr_t skb_dma_addr;
92744989
GL		 262 int i;
263
a63625d2
EH		 264 lp->rx_skb = devm_kcalloc(&ndev->dev, RX_BD_NUM, sizeof(*lp->rx_skb),
265 GFP_KERNEL);
b2adaca9 266 if (!lp->rx_skb)
fe62c298 267 goto out;
b2adaca9 268
92744989 269 /* allocate the tx and rx ring buffer descriptors. */
b595076a 270 /* returns a virtual address and a physical address. */
750afb08
LC		 271 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
272 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
273 &lp->tx_bd_p, GFP_KERNEL);
d0320f75 274 if (!lp->tx_bd_v)
fe62c298 275 goto out;
d0320f75 276
750afb08
LC		 277 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
278 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
279 &lp->rx_bd_p, GFP_KERNEL);
d0320f75 280 if (!lp->rx_bd_v)
fe62c298 281 goto out;
92744989 282
92744989 283 for (i = 0; i < TX_BD_NUM; i++) {
fdd7454e
EH		 284 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
285 + sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM));
92744989
GL		 286 }
287
92744989 288 for (i = 0; i < RX_BD_NUM; i++) {
fdd7454e
EH		 289 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
290 + sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM));
92744989 291
e44171f1
JL		 292 skb = netdev_alloc_skb_ip_align(ndev,
293 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 294 if (!skb)
fe62c298 295 goto out;
720a43ef 296
92744989 297 lp->rx_skb[i] = skb;
92744989 298 /* returns physical address of skb->data */
fdd7454e
EH		 299 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
300 XTE_MAX_JUMBO_FRAME_SIZE,
301 DMA_FROM_DEVICE);
302 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
303 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
304 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
92744989
GL		 305 }
306
7e97a194
EH		 307 /* Configure DMA channel (irq setup) */
308 lp->dma_out(lp, TX_CHNL_CTRL, lp->tx_chnl_ctrl |
309 0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
310 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
311 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
312 lp->dma_out(lp, RX_CHNL_CTRL, lp->rx_chnl_ctrl |
313 CHNL_CTRL_IRQ_IOE |
314 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
315 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
92744989 316
7167cf0e
RR		 317 /* Init descriptor indexes */
318 lp->tx_bd_ci = 0;
319 lp->tx_bd_next = 0;
320 lp->tx_bd_tail = 0;
321 lp->rx_bd_ci = 0;
322
73f7375d
EH		 323 /* Enable RX DMA transfers */
324 wmb();
325 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
326 lp->dma_out(lp, RX_TAILDESC_PTR,
327 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
328
329 /* Prepare for TX DMA transfer */
330 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
331
92744989 332 return 0;
fe62c298
DK		 333
334out:
301e9d96 335 temac_dma_bd_release(ndev);
fe62c298 336 return -ENOMEM;
92744989
GL		 337}
338
339/* ---------------------------------------------------------------------
340 * net_device_ops
341 */
342
04e406dc 343static void temac_do_set_mac_address(struct net_device *ndev)
92744989
GL		 344{
345 struct temac_local *lp = netdev_priv(ndev);
346
92744989 347 /* set up unicast MAC address filter set its mac address */
f14f5c11 348 mutex_lock(lp->indirect_mutex);
92744989
GL		 349 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
350 (ndev->dev_addr[0]) |
351 (ndev->dev_addr[1] << 8) |
352 (ndev->dev_addr[2] << 16) |
353 (ndev->dev_addr[3] << 24));
354 /* There are reserved bits in EUAW1
355 * so don't affect them Set MAC bits [47:32] in EUAW1 */
356 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
357 (ndev->dev_addr[4] & 0x000000ff) |
358 (ndev->dev_addr[5] << 8));
f14f5c11 359 mutex_unlock(lp->indirect_mutex);
04e406dc 360}
92744989 361
06205472 362static int temac_init_mac_address(struct net_device *ndev, const void *address)
04e406dc 363{
2d2924af 364 ether_addr_copy(ndev->dev_addr, address);
04e406dc
JP		 365 if (!is_valid_ether_addr(ndev->dev_addr))
366 eth_hw_addr_random(ndev);
367 temac_do_set_mac_address(ndev);
92744989
GL		 368 return 0;
369}
370
04e406dc 371static int temac_set_mac_address(struct net_device *ndev, void *p)
8ea7a37c
SM		 372{
373 struct sockaddr *addr = p;
374
04e406dc
JP		 375 if (!is_valid_ether_addr(addr->sa_data))
376 return -EADDRNOTAVAIL;
377 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
378 temac_do_set_mac_address(ndev);
379 return 0;
8ea7a37c
SM		 380}
381
92744989
GL		 382static void temac_set_multicast_list(struct net_device *ndev)
383{
384 struct temac_local *lp = netdev_priv(ndev);
385 u32 multi_addr_msw, multi_addr_lsw, val;
386 int i;
387
f14f5c11 388 mutex_lock(lp->indirect_mutex);
8e95a202 389 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 390 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 391 /*
392 * We must make the kernel realise we had to move
393 * into promisc mode or we start all out war on
394 * the cable. If it was a promisc request the
395 * flag is already set. If not we assert it.
396 */
397 ndev->flags |= IFF_PROMISC;
398 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
399 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 400 } else if (!netdev_mc_empty(ndev)) {
22bedad3 401 struct netdev_hw_addr *ha;
92744989 402
f9dcbcc9 403 i = 0;
22bedad3 404 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 405 if (i >= MULTICAST_CAM_TABLE_NUM)
406 break;
22bedad3
JP		 407 multi_addr_msw = ((ha->addr[3] << 24) |
408 (ha->addr[2] << 16) |
409 (ha->addr[1] << 8) |
410 (ha->addr[0]));
92744989
GL		 411 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
412 multi_addr_msw);
22bedad3
JP		 413 multi_addr_lsw = ((ha->addr[5] << 8) |
414 (ha->addr[4]) | (i << 16));
92744989
GL		 415 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
416 multi_addr_lsw);
f9dcbcc9 417 i++;
92744989
GL		 418 }
419 } else {
420 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
421 temac_indirect_out32(lp, XTE_AFM_OFFSET,
422 val & ~XTE_AFM_EPPRM_MASK);
423 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
424 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
425 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
426 }
f14f5c11 427 mutex_unlock(lp->indirect_mutex);
92744989
GL		 428}
429
84ea0ded 430static struct temac_option {
92744989
GL		 431 int flg;
432 u32 opt;
433 u32 reg;
434 u32 m_or;
435 u32 m_and;
436} temac_options[] = {
437 /* Turn on jumbo packet support for both Rx and Tx */
438 {
439 .opt = XTE_OPTION_JUMBO,
440 .reg = XTE_TXC_OFFSET,
441 .m_or = XTE_TXC_TXJMBO_MASK,
442 },
443 {
444 .opt = XTE_OPTION_JUMBO,
445 .reg = XTE_RXC1_OFFSET,
446 .m_or =XTE_RXC1_RXJMBO_MASK,
447 },
448 /* Turn on VLAN packet support for both Rx and Tx */
449 {
450 .opt = XTE_OPTION_VLAN,
451 .reg = XTE_TXC_OFFSET,
452 .m_or =XTE_TXC_TXVLAN_MASK,
453 },
454 {
455 .opt = XTE_OPTION_VLAN,
456 .reg = XTE_RXC1_OFFSET,
457 .m_or =XTE_RXC1_RXVLAN_MASK,
458 },
459 /* Turn on FCS stripping on receive packets */
460 {
461 .opt = XTE_OPTION_FCS_STRIP,
462 .reg = XTE_RXC1_OFFSET,
463 .m_or =XTE_RXC1_RXFCS_MASK,
464 },
465 /* Turn on FCS insertion on transmit packets */
466 {
467 .opt = XTE_OPTION_FCS_INSERT,
468 .reg = XTE_TXC_OFFSET,
469 .m_or =XTE_TXC_TXFCS_MASK,
470 },
471 /* Turn on length/type field checking on receive packets */
472 {
473 .opt = XTE_OPTION_LENTYPE_ERR,
474 .reg = XTE_RXC1_OFFSET,
475 .m_or =XTE_RXC1_RXLT_MASK,
476 },
477 /* Turn on flow control */
478 {
479 .opt = XTE_OPTION_FLOW_CONTROL,
480 .reg = XTE_FCC_OFFSET,
481 .m_or =XTE_FCC_RXFLO_MASK,
482 },
483 /* Turn on flow control */
484 {
485 .opt = XTE_OPTION_FLOW_CONTROL,
486 .reg = XTE_FCC_OFFSET,
487 .m_or =XTE_FCC_TXFLO_MASK,
488 },
489 /* Turn on promiscuous frame filtering (all frames are received ) */
490 {
491 .opt = XTE_OPTION_PROMISC,
492 .reg = XTE_AFM_OFFSET,
493 .m_or =XTE_AFM_EPPRM_MASK,
494 },
495 /* Enable transmitter if not already enabled */
496 {
497 .opt = XTE_OPTION_TXEN,
498 .reg = XTE_TXC_OFFSET,
499 .m_or =XTE_TXC_TXEN_MASK,
500 },
501 /* Enable receiver? */
502 {
503 .opt = XTE_OPTION_RXEN,
504 .reg = XTE_RXC1_OFFSET,
505 .m_or =XTE_RXC1_RXEN_MASK,
506 },
507 {}
508};
509
510/**
511 * temac_setoptions
512 */
513static u32 temac_setoptions(struct net_device *ndev, u32 options)
514{
515 struct temac_local *lp = netdev_priv(ndev);
516 struct temac_option *tp = &temac_options[0];
517 int reg;
518
f14f5c11 519 mutex_lock(lp->indirect_mutex);
92744989
GL		 520 while (tp->opt) {
521 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
522 if (options & tp->opt)
523 reg |= tp->m_or;
524 temac_indirect_out32(lp, tp->reg, reg);
525 tp++;
526 }
527 lp->options |= options;
f14f5c11 528 mutex_unlock(lp->indirect_mutex);
92744989 529
807540ba 530 return 0;
92744989
GL		 531}
532
421f91d2 533/* Initialize temac */
92744989
GL		 534static void temac_device_reset(struct net_device *ndev)
535{
536 struct temac_local *lp = netdev_priv(ndev);
537 u32 timeout;
538 u32 val;
539
540 /* Perform a software reset */
541
542 /* 0x300 host enable bit ? */
543 /* reset PHY through control register ?:1 */
544
545 dev_dbg(&ndev->dev, "%s()\n", __func__);
546
f14f5c11 547 mutex_lock(lp->indirect_mutex);
92744989
GL		 548 /* Reset the receiver and wait for it to finish reset */
549 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
550 timeout = 1000;
551 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
552 udelay(1);
553 if (--timeout == 0) {
554 dev_err(&ndev->dev,
555 "temac_device_reset RX reset timeout!!\n");
556 break;
557 }
558 }
559
560 /* Reset the transmitter and wait for it to finish reset */
561 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
562 timeout = 1000;
563 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
564 udelay(1);
565 if (--timeout == 0) {
566 dev_err(&ndev->dev,
567 "temac_device_reset TX reset timeout!!\n");
568 break;
569 }
570 }
571
572 /* Disable the receiver */
573 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
574 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
575
576 /* Reset Local Link (DMA) */
e44171f1 577 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 578 timeout = 1000;
e44171f1 579 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 580 udelay(1);
581 if (--timeout == 0) {
582 dev_err(&ndev->dev,
583 "temac_device_reset DMA reset timeout!!\n");
584 break;
585 }
586 }
e44171f1 587 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 588
fe62c298
DK		 589 if (temac_dma_bd_init(ndev)) {
590 dev_err(&ndev->dev,
591 "temac_device_reset descriptor allocation failed\n");
592 }
92744989
GL		 593
594 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
595 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
596 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
597 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
598
f14f5c11 599 mutex_unlock(lp->indirect_mutex);
92744989
GL		 600
601 /* Sync default options with HW
602 * but leave receiver and transmitter disabled. */
603 temac_setoptions(ndev,
604 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
605
04e406dc 606 temac_do_set_mac_address(ndev);
92744989
GL		 607
608 /* Set address filter table */
609 temac_set_multicast_list(ndev);
610 if (temac_setoptions(ndev, lp->options))
611 dev_err(&ndev->dev, "Error setting TEMAC options\n");
612
613 /* Init Driver variable */
860e9538 614 netif_trans_update(ndev); /* prevent tx timeout */
92744989
GL		 615}
616
84ea0ded 617static void temac_adjust_link(struct net_device *ndev)
92744989
GL		 618{
619 struct temac_local *lp = netdev_priv(ndev);
31abbe34 620 struct phy_device *phy = ndev->phydev;
92744989
GL		 621 u32 mii_speed;
622 int link_state;
623
624 /* hash together the state values to decide if something has changed */
625 link_state = phy->speed | (phy->duplex << 1) | phy->link;
626
f14f5c11 627 mutex_lock(lp->indirect_mutex);
92744989
GL		 628 if (lp->last_link != link_state) {
629 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
630 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
631
632 switch (phy->speed) {
633 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
634 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
635 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
636 }
637
638 /* Write new speed setting out to TEMAC */
639 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
640 lp->last_link = link_state;
641 phy_print_status(phy);
642 }
f14f5c11 643 mutex_unlock(lp->indirect_mutex);
92744989
GL		 644}
645
d84aec42
EH		 646#ifdef CONFIG_64BIT
647
6e05b833 648static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
d84aec42
EH		 649{
650 bd->app3 = (u32)(((u64)p) >> 32);
651 bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
652}
653
6e05b833 654static void *ptr_from_txbd(struct cdmac_bd *bd)
d84aec42
EH		 655{
656 return (void *)(((u64)(bd->app3) << 32) | bd->app4);
657}
658
659#else
660
6e05b833 661static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
d84aec42
EH		 662{
663 bd->app4 = (u32)p;
664}
665
6e05b833 666static void *ptr_from_txbd(struct cdmac_bd *bd)
d84aec42
EH		 667{
668 return (void *)(bd->app4);
669}
670
671#endif
672
92744989
GL		 673static void temac_start_xmit_done(struct net_device *ndev)
674{
675 struct temac_local *lp = netdev_priv(ndev);
676 struct cdmac_bd *cur_p;
677 unsigned int stat = 0;
d84aec42 678 struct sk_buff *skb;
92744989
GL		 679
680 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
fdd7454e 681 stat = be32_to_cpu(cur_p->app0);
92744989
GL		 682
683 while (stat & STS_CTRL_APP0_CMPLT) {
fdd7454e
EH		 684 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
685 be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
d84aec42
EH		 686 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
687 if (skb)
688 dev_consume_skb_irq(skb);
92744989 689 cur_p->app0 = 0;
23ecc4bd
BH		 690 cur_p->app1 = 0;
691 cur_p->app2 = 0;
692 cur_p->app3 = 0;
693 cur_p->app4 = 0;
92744989
GL		 694
695 ndev->stats.tx_packets++;
fdd7454e 696 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
92744989
GL		 697
698 lp->tx_bd_ci++;
699 if (lp->tx_bd_ci >= TX_BD_NUM)
700 lp->tx_bd_ci = 0;
701
702 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
fdd7454e 703 stat = be32_to_cpu(cur_p->app0);
92744989
GL		 704 }
705
706 netif_wake_queue(ndev);
707}
708
23ecc4bd
BH		 709static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
710{
711 struct cdmac_bd *cur_p;
712 int tail;
713
714 tail = lp->tx_bd_tail;
715 cur_p = &lp->tx_bd_v[tail];
716
717 do {
718 if (cur_p->app0)
719 return NETDEV_TX_BUSY;
720
721 tail++;
722 if (tail >= TX_BD_NUM)
723 tail = 0;
724
725 cur_p = &lp->tx_bd_v[tail];
726 num_frag--;
727 } while (num_frag >= 0);
728
729 return 0;
730}
731
81255af8
Y		 732static netdev_tx_t
733temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
92744989
GL		 734{
735 struct temac_local *lp = netdev_priv(ndev);
736 struct cdmac_bd *cur_p;
fdd7454e 737 dma_addr_t start_p, tail_p, skb_dma_addr;
92744989
GL		 738 int ii;
739 unsigned long num_frag;
740 skb_frag_t *frag;
741
742 num_frag = skb_shinfo(skb)->nr_frags;
743 frag = &skb_shinfo(skb)->frags[0];
744 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
745 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
746
2c9938e7 747 if (temac_check_tx_bd_space(lp, num_frag + 1)) {
3824246d 748 if (!netif_queue_stopped(ndev))
92744989 749 netif_stop_queue(ndev);
92744989
GL		 750 return NETDEV_TX_BUSY;
751 }
752
753 cur_p->app0 = 0;
754 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 755 unsigned int csum_start_off = skb_checksum_start_offset(skb);
23ecc4bd
BH		 756 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
757
fdd7454e
EH		 758 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
759 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
760 | csum_index_off);
23ecc4bd 761 cur_p->app2 = 0; /* initial checksum seed */
92744989 762 }
23ecc4bd 763
fdd7454e
EH		 764 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
765 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
766 skb_headlen(skb), DMA_TO_DEVICE);
767 cur_p->len = cpu_to_be32(skb_headlen(skb));
768 cur_p->phys = cpu_to_be32(skb_dma_addr);
d84aec42 769 ptr_to_txbd((void *)skb, cur_p);
92744989
GL		 770
771 for (ii = 0; ii < num_frag; ii++) {
772 lp->tx_bd_tail++;
773 if (lp->tx_bd_tail >= TX_BD_NUM)
774 lp->tx_bd_tail = 0;
775
776 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
fdd7454e
EH		 777 skb_dma_addr = dma_map_single(ndev->dev.parent,
778 skb_frag_address(frag),
779 skb_frag_size(frag),
780 DMA_TO_DEVICE);
781 cur_p->phys = cpu_to_be32(skb_dma_addr);
782 cur_p->len = cpu_to_be32(skb_frag_size(frag));
92744989
GL		 783 cur_p->app0 = 0;
784 frag++;
785 }
fdd7454e 786 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
92744989
GL		 787
788 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
789 lp->tx_bd_tail++;
790 if (lp->tx_bd_tail >= TX_BD_NUM)
791 lp->tx_bd_tail = 0;
792
93e0ed15
RC		 793 skb_tx_timestamp(skb);
794
92744989 795 /* Kick off the transfer */
73f7375d 796 wmb();
e44171f1 797 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 798
6ed10654 799 return NETDEV_TX_OK;
92744989
GL		 800}
801
802
803static void ll_temac_recv(struct net_device *ndev)
804{
805 struct temac_local *lp = netdev_priv(ndev);
806 struct sk_buff *skb, *new_skb;
807 unsigned int bdstat;
808 struct cdmac_bd *cur_p;
fdd7454e 809 dma_addr_t tail_p, skb_dma_addr;
92744989 810 int length;
92744989
GL		 811 unsigned long flags;
812
813 spin_lock_irqsave(&lp->rx_lock, flags);
814
815 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
816 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
817
fdd7454e 818 bdstat = be32_to_cpu(cur_p->app0);
92744989
GL		 819 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
820
821 skb = lp->rx_skb[lp->rx_bd_ci];
fdd7454e 822 length = be32_to_cpu(cur_p->app4) & 0x3FFF;
92744989 823
fdd7454e 824 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
a8c9bd3b 825 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
92744989
GL		 826
827 skb_put(skb, length);
92744989 828 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 829 skb_checksum_none_assert(skb);
92744989 830
23ecc4bd
BH		 831 /* if we're doing rx csum offload, set it up */
832 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
ceffc4ac
JP		 833 (skb->protocol == htons(ETH_P_IP)) &&
834 (skb->len > 64)) {
23ecc4bd 835
fdd7454e
EH		 836 /* Convert from device endianness (be32) to cpu
837 * endiannes, and if necessary swap the bytes
838 * (back) for proper IP checksum byte order
839 * (be16).
840 */
841 skb->csum = htons(be32_to_cpu(cur_p->app3) & 0xFFFF);
23ecc4bd
BH		 842 skb->ip_summed = CHECKSUM_COMPLETE;
843 }
844
93e0ed15
RC		 845 if (!skb_defer_rx_timestamp(skb))
846 netif_rx(skb);
92744989
GL		 847
848 ndev->stats.rx_packets++;
849 ndev->stats.rx_bytes += length;
850
e44171f1
JL		 851 new_skb = netdev_alloc_skb_ip_align(ndev,
852 XTE_MAX_JUMBO_FRAME_SIZE);
720a43ef 853 if (!new_skb) {
92744989
GL		 854 spin_unlock_irqrestore(&lp->rx_lock, flags);
855 return;
856 }
857
fdd7454e
EH		 858 cur_p->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
859 skb_dma_addr = dma_map_single(ndev->dev.parent, new_skb->data,
860 XTE_MAX_JUMBO_FRAME_SIZE,
861 DMA_FROM_DEVICE);
862 cur_p->phys = cpu_to_be32(skb_dma_addr);
863 cur_p->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
92744989
GL		 864 lp->rx_skb[lp->rx_bd_ci] = new_skb;
865
866 lp->rx_bd_ci++;
867 if (lp->rx_bd_ci >= RX_BD_NUM)
868 lp->rx_bd_ci = 0;
869
870 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
fdd7454e 871 bdstat = be32_to_cpu(cur_p->app0);
92744989 872 }
e44171f1 873 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 874
875 spin_unlock_irqrestore(&lp->rx_lock, flags);
876}
877
878static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
879{
880 struct net_device *ndev = _ndev;
881 struct temac_local *lp = netdev_priv(ndev);
882 unsigned int status;
883
e44171f1
JL		 884 status = lp->dma_in(lp, TX_IRQ_REG);
885 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 886
887 if (status & (IRQ_COAL | IRQ_DLY))
888 temac_start_xmit_done(lp->ndev);
5db9c740
EH		 889 if (status & (IRQ_ERR | IRQ_DMAERR))
890 dev_err_ratelimited(&ndev->dev,
891 "TX error 0x%x TX_CHNL_STS=0x%08x\n",
892 status, lp->dma_in(lp, TX_CHNL_STS));
92744989
GL		 893
894 return IRQ_HANDLED;
895}
896
897static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
898{
899 struct net_device *ndev = _ndev;
900 struct temac_local *lp = netdev_priv(ndev);
901 unsigned int status;
902
903 /* Read and clear the status registers */
e44171f1
JL		 904 status = lp->dma_in(lp, RX_IRQ_REG);
905 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 906
907 if (status & (IRQ_COAL | IRQ_DLY))
908 ll_temac_recv(lp->ndev);
5db9c740
EH		 909 if (status & (IRQ_ERR | IRQ_DMAERR))
910 dev_err_ratelimited(&ndev->dev,
911 "RX error 0x%x RX_CHNL_STS=0x%08x\n",
912 status, lp->dma_in(lp, RX_CHNL_STS));
92744989
GL		 913
914 return IRQ_HANDLED;
915}
916
917static int temac_open(struct net_device *ndev)
918{
919 struct temac_local *lp = netdev_priv(ndev);
31abbe34 920 struct phy_device *phydev = NULL;
92744989
GL		 921 int rc;
922
923 dev_dbg(&ndev->dev, "temac_open()\n");
924
925 if (lp->phy_node) {
31abbe34
PR		 926 phydev = of_phy_connect(lp->ndev, lp->phy_node,
927 temac_adjust_link, 0, 0);
928 if (!phydev) {
92744989
GL		 929 dev_err(lp->dev, "of_phy_connect() failed\n");
930 return -ENODEV;
931 }
8425c41d
EH		 932 phy_start(phydev);
933 } else if (strlen(lp->phy_name) > 0) {
934 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
935 lp->phy_interface);
1ffc4b7c 936 if (IS_ERR(phydev)) {
8425c41d 937 dev_err(lp->dev, "phy_connect() failed\n");
1ffc4b7c 938 return PTR_ERR(phydev);
8425c41d 939 }
31abbe34 940 phy_start(phydev);
92744989
GL		 941 }
942
50ec1538
RR		 943 temac_device_reset(ndev);
944
92744989
GL		 945 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
946 if (rc)
947 goto err_tx_irq;
948 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
949 if (rc)
950 goto err_rx_irq;
951
92744989
GL		 952 return 0;
953
954 err_rx_irq:
955 free_irq(lp->tx_irq, ndev);
956 err_tx_irq:
31abbe34
PR		 957 if (phydev)
958 phy_disconnect(phydev);
92744989
GL		 959 dev_err(lp->dev, "request_irq() failed\n");
960 return rc;
961}
962
963static int temac_stop(struct net_device *ndev)
964{
965 struct temac_local *lp = netdev_priv(ndev);
31abbe34 966 struct phy_device *phydev = ndev->phydev;
92744989
GL		 967
968 dev_dbg(&ndev->dev, "temac_close()\n");
969
970 free_irq(lp->tx_irq, ndev);
971 free_irq(lp->rx_irq, ndev);
972
31abbe34
PR		 973 if (phydev)
974 phy_disconnect(phydev);
92744989 975
301e9d96
DK		 976 temac_dma_bd_release(ndev);
977
92744989
GL		 978 return 0;
979}
980
981#ifdef CONFIG_NET_POLL_CONTROLLER
982static void
983temac_poll_controller(struct net_device *ndev)
984{
985 struct temac_local *lp = netdev_priv(ndev);
986
987 disable_irq(lp->tx_irq);
988 disable_irq(lp->rx_irq);
989
8539992f
MS		 990 ll_temac_rx_irq(lp->tx_irq, ndev);
991 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 992
993 enable_irq(lp->tx_irq);
994 enable_irq(lp->rx_irq);
995}
996#endif
997
8d8bdfe8
RR		 998static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
999{
8d8bdfe8
RR		 1000 if (!netif_running(ndev))
1001 return -EINVAL;
1002
31abbe34 1003 if (!ndev->phydev)
8d8bdfe8
RR		 1004 return -EINVAL;
1005
31abbe34 1006 return phy_mii_ioctl(ndev->phydev, rq, cmd);
8d8bdfe8
RR		 1007}
1008
92744989
GL		 1009static const struct net_device_ops temac_netdev_ops = {
1010 .ndo_open = temac_open,
1011 .ndo_stop = temac_stop,
1012 .ndo_start_xmit = temac_start_xmit,
04e406dc 1013 .ndo_set_mac_address = temac_set_mac_address,
60eb5fd1 1014 .ndo_validate_addr = eth_validate_addr,
8d8bdfe8 1015 .ndo_do_ioctl = temac_ioctl,
92744989
GL		 1016#ifdef CONFIG_NET_POLL_CONTROLLER
1017 .ndo_poll_controller = temac_poll_controller,
1018#endif
1019};
1020
1021/* ---------------------------------------------------------------------
1022 * SYSFS device attributes
1023 */
1024static ssize_t temac_show_llink_regs(struct device *dev,
1025 struct device_attribute *attr, char *buf)
1026{
1027 struct net_device *ndev = dev_get_drvdata(dev);
1028 struct temac_local *lp = netdev_priv(ndev);
1029 int i, len = 0;
1030
1031 for (i = 0; i < 0x11; i++)
e44171f1 1032 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 1033 (i % 8) == 7 ? "\n" : " ");
1034 len += sprintf(buf + len, "\n");
1035
1036 return len;
1037}
1038
1039static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1040
1041static struct attribute *temac_device_attrs[] = {
1042 &dev_attr_llink_regs.attr,
1043 NULL,
1044};
1045
1046static const struct attribute_group temac_attr_group = {
1047 .attrs = temac_device_attrs,
1048};
1049
9eac2d4d 1050/* ethtool support */
9eac2d4d 1051static const struct ethtool_ops temac_ethtool_ops = {
16250527 1052 .nway_reset = phy_ethtool_nway_reset,
9eac2d4d 1053 .get_link = ethtool_op_get_link,
f85e5ea2 1054 .get_ts_info = ethtool_op_get_ts_info,
e6dab902
PR		 1055 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1056 .set_link_ksettings = phy_ethtool_set_link_ksettings,
9eac2d4d
RR		 1057};
1058
8425c41d 1059static int temac_probe(struct platform_device *pdev)
92744989 1060{
8425c41d
EH		 1061 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1062 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
92744989
GL		 1063 struct temac_local *lp;
1064 struct net_device *ndev;
8425c41d 1065 struct resource *res;
92744989 1066 const void *addr;
23ecc4bd 1067 __be32 *p;
a3246dc4 1068 bool little_endian;
06205472 1069 int rc = 0;
92744989
GL		 1070
1071 /* Init network device structure */
a63625d2 1072 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
41de8d4c 1073 if (!ndev)
92744989 1074 return -ENOMEM;
41de8d4c 1075
8425c41d
EH		 1076 platform_set_drvdata(pdev, ndev);
1077 SET_NETDEV_DEV(ndev, &pdev->dev);
92744989 1078 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
28e24c62 1079 ndev->features = NETIF_F_SG;
92744989 1080 ndev->netdev_ops = &temac_netdev_ops;
9eac2d4d 1081 ndev->ethtool_ops = &temac_ethtool_ops;
92744989
GL		 1082#if 0
1083 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1084 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1085 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1086 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
f646968f
PM		 1087 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1088 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1089 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
92744989
GL		 1090 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1091 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1092 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1093 ndev->features |= NETIF_F_LRO; /* large receive offload */
1094#endif
1095
1096 /* setup temac private info structure */
1097 lp = netdev_priv(ndev);
1098 lp->ndev = ndev;
8425c41d 1099 lp->dev = &pdev->dev;
92744989
GL		 1100 lp->options = XTE_OPTION_DEFAULTS;
1101 spin_lock_init(&lp->rx_lock);
f14f5c11
EH		 1102
1103 /* Setup mutex for synchronization of indirect register access */
1104 if (pdata) {
1105 if (!pdata->indirect_mutex) {
1106 dev_err(&pdev->dev,
1107 "indirect_mutex missing in platform_data\n");
1108 return -EINVAL;
1109 }
1110 lp->indirect_mutex = pdata->indirect_mutex;
1111 } else {
1112 lp->indirect_mutex = devm_kmalloc(&pdev->dev,
1113 sizeof(*lp->indirect_mutex),
1114 GFP_KERNEL);
1115 mutex_init(lp->indirect_mutex);
1116 }
92744989
GL		 1117
1118 /* map device registers */
8425c41d
EH		 1119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 lp->regs = devm_ioremap_nocache(&pdev->dev, res->start,
1121 resource_size(res));
1122 if (IS_ERR(lp->regs)) {
1123 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1124 return PTR_ERR(lp->regs);
92744989
GL		 1125 }
1126
a3246dc4
EH		 1127 /* Select register access functions with the specified
1128 * endianness mode. Default for OF devices is big-endian.
1129 */
1130 little_endian = false;
1131 if (temac_np) {
1132 if (of_get_property(temac_np, "little-endian", NULL))
1133 little_endian = true;
1134 } else if (pdata) {
1135 little_endian = pdata->reg_little_endian;
1136 }
1137 if (little_endian) {
1138 lp->temac_ior = _temac_ior_le;
1139 lp->temac_iow = _temac_iow_le;
1140 } else {
1141 lp->temac_ior = _temac_ior_be;
1142 lp->temac_iow = _temac_iow_be;
1143 }
1144
23ecc4bd
BH		 1145 /* Setup checksum offload, but default to off if not specified */
1146 lp->temac_features = 0;
8425c41d
EH		 1147 if (temac_np) {
1148 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1149 if (p && be32_to_cpu(*p))
1150 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1151 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1152 if (p && be32_to_cpu(*p))
1153 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1154 } else if (pdata) {
1155 if (pdata->txcsum)
1156 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1157 if (pdata->rxcsum)
1158 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1159 }
1160 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
23ecc4bd
BH		 1161 /* Can checksum TCP/UDP over IPv4. */
1162 ndev->features |= NETIF_F_IP_CSUM;
92744989 1163
8425c41d
EH		 1164 /* Setup LocalLink DMA */
1165 if (temac_np) {
1166 /* Find the DMA node, map the DMA registers, and
1167 * decode the DMA IRQs.
1168 */
1169 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1170 if (!dma_np) {
1171 dev_err(&pdev->dev, "could not find DMA node\n");
1172 return -ENODEV;
1173 }
e44171f1 1174
8425c41d
EH		 1175 /* Setup the DMA register accesses, could be DCR or
1176 * memory mapped.
1177 */
1178 if (temac_dcr_setup(lp, pdev, dma_np)) {
1179 /* no DCR in the device tree, try non-DCR */
1180 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1181 NULL);
1182 if (IS_ERR(lp->sdma_regs)) {
1183 dev_err(&pdev->dev,
1184 "unable to map DMA registers\n");
1185 of_node_put(dma_np);
1186 return PTR_ERR(lp->sdma_regs);
1187 }
a3246dc4
EH		 1188 if (of_get_property(dma_np, "little-endian", NULL)) {
1189 lp->dma_in = temac_dma_in32_le;
1190 lp->dma_out = temac_dma_out32_le;
1191 } else {
1192 lp->dma_in = temac_dma_in32_be;
1193 lp->dma_out = temac_dma_out32_be;
1194 }
8425c41d 1195 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
e44171f1 1196 }
7cc36f6f 1197
8425c41d
EH		 1198 /* Get DMA RX and TX interrupts */
1199 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1200 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1201
7e97a194
EH		 1202 /* Use defaults for IRQ delay/coalescing setup. These
1203 * are configuration values, so does not belong in
1204 * device-tree.
1205 */
1206 lp->tx_chnl_ctrl = 0x10220000;
1207 lp->rx_chnl_ctrl = 0xff070000;
1208
8425c41d
EH		 1209 /* Finished with the DMA node; drop the reference */
1210 of_node_put(dma_np);
1211 } else if (pdata) {
1212 /* 2nd memory resource specifies DMA registers */
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1214 lp->sdma_regs = devm_ioremap_nocache(&pdev->dev, res->start,
1215 resource_size(res));
1216 if (IS_ERR(lp->sdma_regs)) {
1217 dev_err(&pdev->dev,
1218 "could not map DMA registers\n");
1219 return PTR_ERR(lp->sdma_regs);
1220 }
a3246dc4
EH		 1221 if (pdata->dma_little_endian) {
1222 lp->dma_in = temac_dma_in32_le;
1223 lp->dma_out = temac_dma_out32_le;
1224 } else {
1225 lp->dma_in = temac_dma_in32_be;
1226 lp->dma_out = temac_dma_out32_be;
1227 }
7cc36f6f 1228
8425c41d
EH		 1229 /* Get DMA RX and TX interrupts */
1230 lp->rx_irq = platform_get_irq(pdev, 0);
1231 lp->tx_irq = platform_get_irq(pdev, 1);
7e97a194
EH		 1232
1233 /* IRQ delay/coalescing setup */
1234 if (pdata->tx_irq_timeout || pdata->tx_irq_count)
1235 lp->tx_chnl_ctrl = (pdata->tx_irq_timeout << 24) |
1236 (pdata->tx_irq_count << 16);
1237 else
1238 lp->tx_chnl_ctrl = 0x10220000;
1239 if (pdata->rx_irq_timeout || pdata->rx_irq_count)
1240 lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) |
1241 (pdata->rx_irq_count << 16);
1242 else
1243 lp->rx_chnl_ctrl = 0xff070000;
92744989
GL		 1244 }
1245
8425c41d
EH		 1246 /* Error handle returned DMA RX and TX interrupts */
1247 if (lp->rx_irq < 0) {
1248 if (lp->rx_irq != -EPROBE_DEFER)
1249 dev_err(&pdev->dev, "could not get DMA RX irq\n");
1250 return lp->rx_irq;
1251 }
1252 if (lp->tx_irq < 0) {
1253 if (lp->tx_irq != -EPROBE_DEFER)
1254 dev_err(&pdev->dev, "could not get DMA TX irq\n");
1255 return lp->tx_irq;
1256 }
92744989 1257
8425c41d
EH		 1258 if (temac_np) {
1259 /* Retrieve the MAC address */
1260 addr = of_get_mac_address(temac_np);
a51645f7 1261 if (IS_ERR(addr)) {
8425c41d
EH		 1262 dev_err(&pdev->dev, "could not find MAC address\n");
1263 return -ENODEV;
1264 }
1265 temac_init_mac_address(ndev, addr);
1266 } else if (pdata) {
1267 temac_init_mac_address(ndev, pdata->mac_addr);
92744989 1268 }
92744989 1269
a63625d2 1270 rc = temac_mdio_setup(lp, pdev);
92744989 1271 if (rc)
8425c41d
EH		 1272 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1273
1274 if (temac_np) {
1275 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1276 if (lp->phy_node)
1277 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1278 } else if (pdata) {
1279 snprintf(lp->phy_name, sizeof(lp->phy_name),
1280 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1281 lp->phy_interface = pdata->phy_interface;
1282 }
92744989
GL		 1283
1284 /* Add the device attributes */
1285 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1286 if (rc) {
1287 dev_err(lp->dev, "Error creating sysfs files\n");
a63625d2 1288 goto err_sysfs_create;
92744989
GL		 1289 }
1290
1291 rc = register_netdev(lp->ndev);
1292 if (rc) {
1293 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1294 goto err_register_ndev;
1295 }
1296
1297 return 0;
1298
a63625d2 1299err_register_ndev:
92744989 1300 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
a63625d2 1301err_sysfs_create:
8425c41d
EH		 1302 if (lp->phy_node)
1303 of_node_put(lp->phy_node);
a63625d2 1304 temac_mdio_teardown(lp);
92744989
GL		 1305 return rc;
1306}
1307
8425c41d 1308static int temac_remove(struct platform_device *pdev)
92744989 1309{
8425c41d 1310 struct net_device *ndev = platform_get_drvdata(pdev);
92744989
GL		 1311 struct temac_local *lp = netdev_priv(ndev);
1312
92744989
GL		 1313 unregister_netdev(ndev);
1314 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
8425c41d
EH		 1315 if (lp->phy_node)
1316 of_node_put(lp->phy_node);
a63625d2 1317 temac_mdio_teardown(lp);
92744989
GL		 1318 return 0;
1319}
1320
74847f23 1321static const struct of_device_id temac_of_match[] = {
92744989 1322 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1323 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1324 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1325 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1326 {},
1327};
1328MODULE_DEVICE_TABLE(of, temac_of_match);
1329
8425c41d
EH		 1330static struct platform_driver temac_driver = {
1331 .probe = temac_probe,
1332 .remove = temac_remove,
92744989 1333 .driver = {
92744989 1334 .name = "xilinx_temac",
4018294b 1335 .of_match_table = temac_of_match,
92744989
GL		 1336 },
1337};
1338
8425c41d 1339module_platform_driver(temac_driver);
92744989
GL		 1340
1341MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1342MODULE_AUTHOR("Yoshio Kashiwagi");
1343MODULE_LICENSE("GPL");
Ubuntu Jammy Linux kernel mirror