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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1da177e4 LT |
2 | /****************************************************************************** |
3 | * | |
4 | * (C)Copyright 1998,1999 SysKonnect, | |
5 | * a business unit of Schneider & Koch & Co. Datensysteme GmbH. | |
6 | * | |
1da177e4 LT |
7 | * The information in this file is provided "AS IS" without warranty. |
8 | * | |
9 | ******************************************************************************/ | |
10 | ||
11 | #ifndef _SKFBI_H_ | |
12 | #define _SKFBI_H_ | |
13 | ||
1da177e4 | 14 | /* |
af096046 | 15 | * FDDI-Fx (x := {I(SA), P(CI)}) |
1da177e4 LT |
16 | * address calculation & function defines |
17 | */ | |
18 | ||
1da177e4 LT |
19 | /*--------------------------------------------------------------------------*/ |
20 | #ifdef PCI | |
21 | ||
22 | /* | |
23 | * (DV) = only defined for Da Vinci | |
24 | * (ML) = only defined for Monalisa | |
25 | */ | |
26 | ||
27 | /* | |
28 | * Configuration Space header | |
29 | */ | |
30 | #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */ | |
31 | #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */ | |
32 | #define PCI_COMMAND 0x04 /* 16 bit Command */ | |
33 | #define PCI_STATUS 0x06 /* 16 bit Status */ | |
34 | #define PCI_REV_ID 0x08 /* 8 bit Revision ID */ | |
35 | #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ | |
36 | #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ | |
37 | #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */ | |
38 | #define PCI_HEADER_T 0x0e /* 8 bit Header Type */ | |
39 | #define PCI_BIST 0x0f /* 8 bit Built-in selftest */ | |
40 | #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ | |
41 | #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ | |
42 | /* Byte 18..2b: Reserved */ | |
43 | #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ | |
44 | #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ | |
45 | #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ | |
46 | /* Byte 34..33: Reserved */ | |
47 | #define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */ | |
48 | /* Byte 35..3b: Reserved */ | |
49 | #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ | |
50 | #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ | |
51 | #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ | |
52 | #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ | |
53 | /* Device Dependent Region */ | |
54 | #define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */ | |
55 | #define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */ | |
56 | #define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */ | |
57 | /* Power Management Region */ | |
58 | #define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */ | |
59 | #define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */ | |
60 | #define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */ | |
61 | #define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */ | |
62 | /* Byte 0x4e: Reserved */ | |
63 | #define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */ | |
64 | /* VPD Region */ | |
65 | #define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */ | |
66 | #define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */ | |
67 | #define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */ | |
68 | #define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */ | |
69 | /* Byte 58..ff: Reserved */ | |
70 | ||
71 | /* | |
72 | * I2C Address (PCI Config) | |
73 | * | |
74 | * Note: The temperature and voltage sensors are relocated on a different | |
75 | * I2C bus. | |
76 | */ | |
77 | #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ | |
78 | ||
79 | /* | |
80 | * Define Bits and Values of the registers | |
81 | */ | |
82 | /* PCI_VENDOR_ID 16 bit Vendor ID */ | |
83 | /* PCI_DEVICE_ID 16 bit Device ID */ | |
84 | /* Values for Vendor ID and Device ID shall be patched into the code */ | |
85 | /* PCI_COMMAND 16 bit Command */ | |
86 | #define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */ | |
87 | #define PCI_SERREN 0x0100 /* Bit 8: SERR enable */ | |
88 | #define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */ | |
89 | #define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */ | |
90 | #define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */ | |
91 | #define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */ | |
92 | #define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */ | |
93 | #define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */ | |
94 | #define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */ | |
95 | #define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */ | |
96 | ||
97 | /* PCI_STATUS 16 bit Status */ | |
98 | #define PCI_PERR 0x8000 /* Bit 15: Parity Error */ | |
99 | #define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */ | |
100 | #define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */ | |
101 | #define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */ | |
102 | #define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */ | |
103 | #define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */ | |
104 | #define PCI_DEV_FAST (0<<9) /* fast */ | |
105 | #define PCI_DEV_MEDIUM (1<<9) /* medium */ | |
106 | #define PCI_DEV_SLOW (2<<9) /* slow */ | |
107 | #define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */ | |
108 | #define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */ | |
109 | #define PCI_UDF 0x0040 /* Bit 6: User Defined Features */ | |
110 | #define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */ | |
111 | #define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */ | |
112 | ||
113 | #define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR) | |
114 | ||
115 | /* PCI_REV_ID 8 bit Revision ID */ | |
116 | /* PCI_CLASS_CODE 24 bit Class Code */ | |
117 | /* Byte 2: Base Class (02) */ | |
118 | /* Byte 1: SubClass (02) */ | |
119 | /* Byte 0: Programming Interface (00) */ | |
120 | ||
121 | /* PCI_CACHE_LSZ 8 bit Cache Line Size */ | |
122 | /* Possible values: 0,2,4,8,16 */ | |
123 | ||
124 | /* PCI_LAT_TIM 8 bit Latency Timer */ | |
125 | ||
126 | /* PCI_HEADER_T 8 bit Header Type */ | |
127 | #define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */ | |
128 | #define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ | |
129 | ||
130 | /* PCI_BIST 8 bit Built-in selftest */ | |
131 | #define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */ | |
132 | #define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */ | |
133 | #define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */ | |
134 | ||
135 | /* PCI_BASE_1ST 32 bit 1st Base address */ | |
136 | #define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */ | |
137 | #define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */ | |
138 | #define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */ | |
139 | #define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */ | |
140 | #define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */ | |
141 | #define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */ | |
142 | #define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */ | |
143 | #define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */ | |
144 | #define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */ | |
145 | ||
1da177e4 LT |
146 | /* PCI_SUB_VID 16 bit Subsystem Vendor ID */ |
147 | /* PCI_SUB_ID 16 bit Subsystem ID */ | |
148 | ||
149 | /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ | |
150 | #define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */ | |
151 | #define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */ | |
152 | #define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */ | |
153 | #define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */ | |
154 | ||
155 | /* PCI_CAP_PTR 8 bit New Capabilities Pointers */ | |
156 | /* PCI_IRQ_LINE 8 bit Interrupt Line */ | |
157 | /* PCI_IRQ_PIN 8 bit Interrupt Pin */ | |
158 | /* PCI_MIN_GNT 8 bit Min_Gnt */ | |
159 | /* PCI_MAX_LAT 8 bit Max_Lat */ | |
160 | /* Device Dependent Region */ | |
161 | /* PCI_OUR_REG (DV) 32 bit Our Register */ | |
162 | /* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */ | |
163 | /* Bit 31..29: reserved */ | |
164 | #define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */ | |
165 | #define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */ | |
166 | #define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */ | |
167 | /* 1 = output */ | |
168 | #define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */ | |
169 | #define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */ | |
170 | #define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */ | |
171 | #define PCI_VIO (1L<<25) /*(ML) */ | |
172 | #define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */ | |
173 | /* 1 = Don't boot with ROM */ | |
174 | /* 0 = Boot with ROM */ | |
175 | #define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */ | |
176 | #define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */ | |
177 | /* 1 = Map Flash to Memory */ | |
178 | /* 0 = Disable all addr. decoding */ | |
179 | #define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */ | |
180 | #define PCI_PAGE_16 (0L<<20) /* 16 k pages */ | |
181 | #define PCI_PAGE_32K (1L<<20) /* 32 k pages */ | |
182 | #define PCI_PAGE_64K (2L<<20) /* 64 k pages */ | |
183 | #define PCI_PAGE_128K (3L<<20) /* 128 k pages */ | |
184 | /* Bit 19: reserved (ML) and (DV) */ | |
185 | #define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ | |
186 | /* Bit 15: reserved */ | |
187 | #define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */ | |
188 | #define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */ | |
189 | #define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */ | |
190 | #define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */ | |
191 | #define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */ | |
192 | #define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */ | |
193 | #define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */ | |
194 | #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */ | |
195 | #define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */ | |
196 | ||
197 | /* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */ | |
198 | #define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */ | |
199 | #define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */ | |
200 | #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */ | |
201 | /* Bit 12..13 reserved */ | |
202 | #define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */ | |
203 | #define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */ | |
204 | #define PCI_PATCH_DIR_3 (1L<<9) | |
205 | #define PCI_PATCH_DIR_4 (1L<<10) | |
206 | #define PCI_PATCH_DIR_5 (1L<<11) | |
207 | #define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */ | |
208 | #define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */ | |
209 | #define PCI_EXT_PATCH_3 (1L<<5) | |
210 | #define PCI_EXT_PATCH_4 (1L<<6) | |
211 | #define PCI_EXT_PATCH_5 (1L<<7) | |
212 | #define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */ | |
213 | #define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */ | |
214 | #define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */ | |
215 | #define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/ | |
216 | ||
217 | /* Power Management Region */ | |
218 | /* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */ | |
219 | /* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */ | |
220 | /* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/ | |
221 | #define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/ | |
222 | #define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */ | |
223 | #define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */ | |
224 | /* Bit 6..8 reserved */ | |
225 | #define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/ | |
226 | #define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */ | |
227 | #define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */ | |
228 | #define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */ | |
229 | ||
230 | /* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */ | |
231 | #define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/ | |
232 | #define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */ | |
233 | #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */ | |
234 | /* Bit 7.. 2 reserved */ | |
235 | #define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */ | |
236 | #define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */ | |
237 | #define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */ | |
238 | #define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */ | |
239 | #define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */ | |
240 | ||
241 | /* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */ | |
242 | /* VPD Region */ | |
243 | /* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */ | |
244 | /* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */ | |
245 | /* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */ | |
246 | #define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/ | |
247 | ||
248 | /* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */ | |
249 | ||
250 | /* | |
251 | * Control Register File: | |
252 | * Bank 0 | |
253 | */ | |
254 | #define B0_RAP 0x0000 /* 8 bit register address port */ | |
255 | /* 0x0001 - 0x0003: reserved */ | |
256 | #define B0_CTRL 0x0004 /* 8 bit control register */ | |
257 | #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ | |
258 | #define B0_LED 0x0006 /* 8 Bit LED register */ | |
259 | #define B0_TST_CTRL 0x0007 /* 8 bit test control register */ | |
260 | #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ | |
261 | #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */ | |
262 | ||
263 | /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ | |
264 | #define B0_CMDREG1 0x0010 /* write command reg 1 instruction */ | |
265 | #define B0_CMDREG2 0x0014 /* write command reg 2 instruction */ | |
266 | #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */ | |
267 | #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */ | |
268 | #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */ | |
269 | #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */ | |
270 | ||
271 | #define B0_MARR 0x0020 /* r/w the memory read addr register */ | |
272 | #define B0_MARW 0x0024 /* r/w the memory write addr register*/ | |
273 | #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */ | |
274 | #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */ | |
275 | ||
276 | #define B0_MDREG3 0x0030 /* r/w Mode Register 3 */ | |
277 | #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */ | |
278 | #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */ | |
279 | #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */ | |
280 | #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */ | |
281 | #define B0_IVR 0x0044 /* read Interrupt Vector register */ | |
282 | #define B0_IMR 0x0048 /* r/w Interrupt mask register */ | |
283 | /* 0x4c Hidden */ | |
284 | ||
285 | #define B0_CNTRL_A 0x0050 /* control register A (r/w) */ | |
286 | #define B0_CNTRL_B 0x0054 /* control register B (r/w) */ | |
287 | #define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */ | |
288 | #define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */ | |
289 | ||
290 | #define B0_STATUS_A 0x0060 /* status register A (read only) */ | |
291 | #define B0_STATUS_B 0x0064 /* status register B (read only) */ | |
292 | #define B0_CNTRL_C 0x0068 /* control register C (r/w) */ | |
293 | #define B0_MDREG1 0x006c /* r/w Mode Register 1 */ | |
294 | ||
295 | #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ | |
296 | #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ | |
297 | #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ | |
298 | #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ | |
299 | ||
300 | /* | |
301 | * Bank 1 | |
302 | * - completely empty (this is the RAP Block window) | |
303 | * Note: if RAP = 1 this page is reserved | |
304 | */ | |
305 | ||
306 | /* | |
307 | * Bank 2 | |
308 | */ | |
309 | #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */ | |
310 | #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */ | |
311 | #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */ | |
312 | #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */ | |
313 | #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */ | |
314 | #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */ | |
315 | #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */ | |
316 | #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */ | |
317 | ||
318 | #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */ | |
319 | #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */ | |
320 | /* 0x010a - 0x010b: reserved */ | |
321 | /* Eprom registers are currently of no use */ | |
322 | #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */ | |
323 | #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */ | |
324 | #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */ | |
325 | #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */ | |
326 | #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */ | |
327 | #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */ | |
328 | /* 0x0115 - 0x0117: reserved */ | |
329 | #define B2_LD_CRTL 0x0118 /* 8 bit loader control */ | |
330 | #define B2_LD_TEST 0x0119 /* 8 bit loader test */ | |
331 | /* 0x011a - 0x011f: reserved */ | |
332 | #define B2_TI_INI 0x0120 /* 32 bit Timer init value */ | |
333 | #define B2_TI_VAL 0x0124 /* 32 bit Timer value */ | |
334 | #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */ | |
335 | #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */ | |
336 | /* 0x012a - 0x012f: reserved */ | |
337 | #define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */ | |
338 | #define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */ | |
339 | #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */ | |
340 | #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */ | |
341 | /* 0x013a - 0x013f: reserved */ | |
342 | #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */ | |
343 | #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */ | |
344 | #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */ | |
345 | #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */ | |
346 | ||
347 | #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */ | |
348 | #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */ | |
349 | #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */ | |
350 | #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */ | |
351 | /* 0x0156: reserved */ | |
352 | #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */ | |
353 | #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */ | |
354 | #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */ | |
355 | ||
356 | #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */ | |
357 | #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */ | |
358 | #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */ | |
359 | #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */ | |
360 | /* 0x016a - 0x017f: reserved */ | |
361 | ||
362 | /* | |
363 | * Bank 3 | |
364 | */ | |
365 | /* | |
366 | * This is a copy of the Configuration register file (lower half) | |
367 | */ | |
368 | #define B3_CFG_SPC 0x180 | |
369 | ||
370 | /* | |
371 | * Bank 4 | |
372 | */ | |
373 | #define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */ | |
374 | #define B4_R1_DA 0x0210 /* 32 bit current rec desc address */ | |
375 | #define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */ | |
376 | #define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */ | |
377 | #define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */ | |
378 | #define B4_R1_F 0x0220 /* 32 bit flag register */ | |
379 | #define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */ | |
380 | #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */ | |
381 | #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */ | |
382 | #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */ | |
383 | #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */ | |
384 | #define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */ | |
385 | #define B4_R1_T3 0x022c /* 32 bit Test Register 3 */ | |
386 | #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */ | |
387 | #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */ | |
388 | /* 0x0238 - 0x023f: reserved */ | |
389 | /* Receive queue 2 is removed on Monalisa */ | |
390 | #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */ | |
391 | #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */ | |
392 | #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */ | |
393 | #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */ | |
394 | #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */ | |
395 | #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */ | |
396 | #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */ | |
397 | #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */ | |
398 | #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */ | |
399 | #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */ | |
400 | #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */ | |
401 | #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */ | |
402 | #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */ | |
403 | /* 0x0270 - 0x027c: reserved */ | |
404 | ||
405 | /* | |
406 | * Bank 5 | |
407 | */ | |
408 | #define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */ | |
409 | #define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */ | |
410 | #define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */ | |
411 | #define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */ | |
412 | #define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */ | |
413 | #define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */ | |
414 | #define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */ | |
415 | #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */ | |
416 | #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */ | |
417 | #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */ | |
418 | #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */ | |
419 | #define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */ | |
420 | #define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */ | |
421 | #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */ | |
422 | #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */ | |
423 | /* 0x02b8 - 0x02bc: reserved */ | |
424 | #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */ | |
425 | #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */ | |
426 | #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */ | |
427 | #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */ | |
428 | #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ | |
429 | #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */ | |
430 | #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */ | |
431 | #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */ | |
432 | #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */ | |
433 | #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */ | |
434 | #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */ | |
435 | #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */ | |
436 | #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */ | |
437 | #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */ | |
438 | #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */ | |
439 | /* 0x02f8 - 0x02fc: reserved */ | |
440 | ||
441 | /* | |
442 | * Bank 6 | |
443 | */ | |
444 | /* External PLC-S registers (SN2 compatibility for DV) */ | |
445 | /* External registers (ML) */ | |
446 | #define B6_EXT_REG 0x300 | |
447 | ||
448 | /* | |
449 | * Bank 7 | |
450 | */ | |
451 | /* DAS PLC-S Registers */ | |
452 | ||
453 | /* | |
454 | * Bank 8 - 15 | |
455 | */ | |
456 | /* IFCP registers */ | |
457 | ||
458 | /*---------------------------------------------------------------------------*/ | |
459 | /* Definitions of the Bits in the registers */ | |
460 | ||
461 | /* B0_RAP 16 bit register address port */ | |
462 | #define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */ | |
463 | ||
464 | /* B0_CTRL 8 bit control register */ | |
465 | #define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */ | |
466 | #define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */ | |
467 | #define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */ | |
468 | #define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */ | |
469 | #define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */ | |
470 | #define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */ | |
471 | #define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */ | |
472 | #define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */ | |
473 | ||
474 | /* B0_DAS 8 Bit control register (DAS) */ | |
475 | #define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */ | |
476 | #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/ | |
477 | /* Bit 5..4: reserved */ | |
478 | #define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */ | |
479 | #define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */ | |
480 | #define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */ | |
481 | #define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */ | |
482 | ||
483 | /* B0_LED 8 Bit LED register */ | |
484 | /* Bit 7..6: reserved */ | |
485 | #define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/ | |
486 | #define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */ | |
487 | #define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/ | |
488 | #define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */ | |
489 | #define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/ | |
490 | #define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */ | |
491 | /* This hardware defines are very ugly therefore we define some others */ | |
492 | ||
493 | #define LED_GA_ON LED_2_ON /* S port = A port */ | |
494 | #define LED_GA_OFF LED_2_OFF /* S port = A port */ | |
495 | #define LED_MY_ON LED_1_ON | |
496 | #define LED_MY_OFF LED_1_OFF | |
497 | #define LED_GB_ON LED_0_ON | |
498 | #define LED_GB_OFF LED_0_OFF | |
499 | ||
500 | /* B0_TST_CTRL 8 bit test control register */ | |
501 | #define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */ | |
502 | #define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */ | |
503 | #define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */ | |
504 | #define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */ | |
505 | #define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */ | |
506 | #define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */ | |
507 | #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ | |
508 | #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */ | |
509 | ||
510 | /* B0_ISRC 32 bit Interrupt source register */ | |
511 | /* Bit 31..28: reserved */ | |
512 | #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ | |
513 | #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ | |
514 | #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ | |
515 | #define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ | |
516 | /* PERR, RMABORT, RTABORT DATAPERR */ | |
517 | #define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ | |
518 | /* RMABORT, RTABORT, DATAPERR */ | |
519 | #define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */ | |
520 | #define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */ | |
521 | /* | |
522 | * Note: The DAS is our First Port (!=PA) | |
523 | */ | |
524 | #define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */ | |
525 | #define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ | |
526 | #define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ | |
527 | #define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ | |
528 | #define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ | |
529 | /* Receive Queue 1 */ | |
530 | #define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ | |
531 | #define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ | |
532 | #define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ | |
533 | #define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ | |
534 | /* Receive Queue 2 */ | |
535 | #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ | |
536 | #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ | |
537 | #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ | |
538 | #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ | |
539 | /* Asynchronous Transmit queue */ | |
540 | /* Bit 7: reserved */ | |
541 | #define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ | |
542 | #define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ | |
543 | #define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ | |
544 | /* Synchronous Transmit queue */ | |
545 | /* Bit 3: reserved */ | |
546 | #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ | |
547 | #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ | |
548 | #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ | |
549 | ||
550 | /* | |
551 | * Define all valid interrupt source Bits from GET_ISR () | |
552 | */ | |
553 | #define ALL_IRSR 0x01ffff77L /* (DV) */ | |
554 | #define ALL_IRSR_ML 0x0ffff077L /* (ML) */ | |
555 | ||
556 | ||
557 | /* B0_IMSK 32 bit Interrupt mask register */ | |
558 | /* | |
559 | * The Bit definnition of this register are the same as of the interrupt | |
560 | * source register. These definition are directly derived from the Hardware | |
561 | * spec. | |
562 | */ | |
563 | /* Bit 31..28: reserved */ | |
564 | #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ | |
565 | #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ | |
566 | #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ | |
567 | #define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ | |
568 | /* PERR, RMABORT, RTABORT DATAPERR */ | |
569 | #define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ | |
570 | /* RMABORT, RTABORT, DATAPERR */ | |
571 | #define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */ | |
572 | #define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */ | |
573 | #define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */ | |
574 | #define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ | |
575 | #define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ | |
576 | #define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ | |
577 | #define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ | |
578 | /* Receive Queue 1 */ | |
579 | #define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ | |
580 | #define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ | |
581 | #define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ | |
582 | #define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ | |
583 | /* Receive Queue 2 */ | |
584 | #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ | |
585 | #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ | |
586 | #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ | |
587 | #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ | |
588 | /* Asynchronous Transmit queue */ | |
589 | /* Bit 7: reserved */ | |
590 | #define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ | |
591 | #define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ | |
592 | #define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ | |
593 | /* Synchronous Transmit queue */ | |
594 | /* Bit 3: reserved */ | |
595 | #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ | |
596 | #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ | |
597 | #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ | |
598 | ||
599 | /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ | |
600 | /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ | |
601 | /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ | |
602 | /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ | |
603 | /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ | |
604 | /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ | |
605 | ||
606 | /* B2_MAC_0 8 bit MAC address Byte 0 */ | |
607 | /* B2_MAC_1 8 bit MAC address Byte 1 */ | |
608 | /* B2_MAC_2 8 bit MAC address Byte 2 */ | |
609 | /* B2_MAC_3 8 bit MAC address Byte 3 */ | |
610 | /* B2_MAC_4 8 bit MAC address Byte 4 */ | |
611 | /* B2_MAC_5 8 bit MAC address Byte 5 */ | |
612 | /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ | |
613 | /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ | |
614 | ||
615 | /* B2_CONN_TYP 8 bit Connector type */ | |
616 | /* B2_PMD_TYP 8 bit PMD type */ | |
617 | /* Values of connector and PMD type comply to SysKonnect internal std */ | |
618 | ||
619 | /* The EPROM register are currently of no use */ | |
620 | /* B2_E_0 8 bit EPROM Byte 0 */ | |
621 | /* B2_E_1 8 bit EPROM Byte 1 */ | |
622 | /* B2_E_2 8 bit EPROM Byte 2 */ | |
623 | /* B2_E_3 8 bit EPROM Byte 3 */ | |
624 | ||
625 | /* B2_FAR 32 bit Flash-Prom Address Register/Counter */ | |
626 | #define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */ | |
627 | ||
628 | /* B2_FDP 8 bit Flash-Prom Data Port */ | |
629 | ||
630 | /* B2_LD_CRTL 8 bit loader control */ | |
631 | /* Bits are currently reserved */ | |
632 | ||
633 | /* B2_LD_TEST 8 bit loader test */ | |
634 | #define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */ | |
635 | #define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */ | |
636 | #define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */ | |
637 | #define LD_START (1<<0) /* Bit 0: Start loading FPROM */ | |
638 | ||
639 | /* B2_TI_INI 32 bit Timer init value */ | |
640 | /* B2_TI_VAL 32 bit Timer value */ | |
641 | /* B2_TI_CRTL 8 bit Timer control */ | |
642 | /* B2_TI_TEST 8 Bit Timer Test */ | |
643 | /* B2_WDOG_INI 32 bit Watchdog init value */ | |
644 | /* B2_WDOG_VAL 32 bit Watchdog value */ | |
645 | /* B2_WDOG_CRTL 8 bit Watchdog control */ | |
646 | /* B2_WDOG_TEST 8 Bit Watchdog Test */ | |
647 | /* B2_RTM_INI 32 bit RTM init value */ | |
648 | /* B2_RTM_VAL 32 bit RTM value */ | |
649 | /* B2_RTM_CRTL 8 bit RTM control */ | |
650 | /* B2_RTM_TEST 8 Bit RTM Test */ | |
651 | /* B2_<TIM>_CRTL 8 bit <TIM> control */ | |
652 | /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ | |
653 | /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ | |
654 | /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ | |
655 | /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ | |
656 | #define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */ | |
657 | #define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */ | |
658 | #define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */ | |
659 | #define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/ | |
660 | #define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */ | |
661 | #define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */ | |
662 | /* B2_<TIM>_TEST 8 Bit <TIM> Test */ | |
663 | #define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */ | |
664 | #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */ | |
665 | #define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */ | |
666 | ||
667 | /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ | |
668 | /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ | |
669 | /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ | |
670 | /* Bit 7..5: reserved */ | |
671 | #define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */ | |
672 | #define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */ | |
673 | #define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */ | |
674 | #define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */ | |
675 | #define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/ | |
676 | ||
677 | /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ | |
678 | /* Bit 7..3: reserved */ | |
679 | #define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/ | |
680 | #define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */ | |
681 | #define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */ | |
682 | ||
683 | /* 0x0156: reserved */ | |
684 | /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ | |
685 | /* Bit 7..4: reserved */ | |
686 | /* force the following error on */ | |
687 | /* the next master read/write */ | |
688 | #define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */ | |
689 | #define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */ | |
690 | #define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */ | |
691 | #define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */ | |
692 | ||
693 | /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ | |
694 | #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */ | |
695 | #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/ | |
696 | #define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */ | |
697 | /* Bit 5.. 8: reserved */ | |
698 | #define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */ | |
699 | #define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */ | |
700 | #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/ | |
701 | #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ | |
702 | #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ | |
703 | #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ | |
704 | #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ | |
705 | #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ | |
706 | #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ | |
707 | #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ | |
708 | #define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */ | |
709 | ||
710 | /* | |
711 | * I2C Addresses | |
712 | * | |
713 | * The temperature sensor and the voltage sensor are on the same I2C bus. | |
714 | * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 | |
715 | * in PCI_OUR_REG 1. | |
716 | */ | |
717 | #define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */ | |
718 | ||
719 | /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ | |
720 | ||
721 | /* B4_R1_D 4*32 bit current receive Descriptor (q1) */ | |
722 | /* B4_R1_DA 32 bit current rec desc address (q1) */ | |
723 | /* B4_R1_AC 32 bit current receive Address Count (q1) */ | |
724 | /* B4_R1_BC 32 bit current receive Byte Counter (q1) */ | |
725 | /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ | |
726 | /* B4_R1_F 32 bit flag register (q1) */ | |
727 | /* B4_R1_T1 32 bit Test Register 1 (q1) */ | |
728 | /* B4_R1_T2 32 bit Test Register 2 (q1) */ | |
729 | /* B4_R1_T3 32 bit Test Register 3 (q1) */ | |
730 | /* B4_R2_D 4*32 bit current receive Descriptor (q2) */ | |
731 | /* B4_R2_DA 32 bit current rec desc address (q2) */ | |
732 | /* B4_R2_AC 32 bit current receive Address Count (q2) */ | |
733 | /* B4_R2_BC 32 bit current receive Byte Counter (q2) */ | |
734 | /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ | |
735 | /* B4_R2_F 32 bit flag register (q2) */ | |
736 | /* B4_R2_T1 32 bit Test Register 1 (q2) */ | |
737 | /* B4_R2_T2 32 bit Test Register 2 (q2) */ | |
738 | /* B4_R2_T3 32 bit Test Register 3 (q2) */ | |
739 | /* B5_XA_D 4*32 bit current receive Descriptor (xa) */ | |
740 | /* B5_XA_DA 32 bit current rec desc address (xa) */ | |
741 | /* B5_XA_AC 32 bit current receive Address Count (xa) */ | |
742 | /* B5_XA_BC 32 bit current receive Byte Counter (xa) */ | |
743 | /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ | |
744 | /* B5_XA_F 32 bit flag register (xa) */ | |
745 | /* B5_XA_T1 32 bit Test Register 1 (xa) */ | |
746 | /* B5_XA_T2 32 bit Test Register 2 (xa) */ | |
747 | /* B5_XA_T3 32 bit Test Register 3 (xa) */ | |
748 | /* B5_XS_D 4*32 bit current receive Descriptor (xs) */ | |
749 | /* B5_XS_DA 32 bit current rec desc address (xs) */ | |
750 | /* B5_XS_AC 32 bit current receive Address Count (xs) */ | |
751 | /* B5_XS_BC 32 bit current receive Byte Counter (xs) */ | |
752 | /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ | |
753 | /* B5_XS_F 32 bit flag register (xs) */ | |
754 | /* B5_XS_T1 32 bit Test Register 1 (xs) */ | |
755 | /* B5_XS_T2 32 bit Test Register 2 (xs) */ | |
756 | /* B5_XS_T3 32 bit Test Register 3 (xs) */ | |
757 | /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ | |
758 | #define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */ | |
759 | #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */ | |
760 | #define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */ | |
761 | #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */ | |
762 | #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */ | |
763 | #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */ | |
764 | #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */ | |
765 | #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */ | |
766 | #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */ | |
767 | #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */ | |
768 | #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */ | |
769 | #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */ | |
770 | #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */ | |
771 | #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */ | |
772 | /* Bit 7..5: reserved */ | |
773 | #define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */ | |
774 | #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */ | |
775 | #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */ | |
776 | #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */ | |
777 | #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */ | |
778 | ||
779 | #define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\ | |
780 | CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST) | |
781 | #define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\ | |
782 | CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN) | |
783 | ||
784 | ||
785 | /* B5_<xx>_F 32 bit flag register (xx) */ | |
786 | /* Bit 28..31: reserved */ | |
787 | #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */ | |
788 | #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */ | |
789 | #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */ | |
790 | #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/ | |
791 | /* Bit 23: reserved */ | |
792 | #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/ | |
793 | /* Bit 8..15: reserved */ | |
794 | #define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */ | |
795 | #define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/ | |
796 | ||
797 | /* B5_<xx>_T1 32 bit Test Register 1 (xx) */ | |
798 | /* Holds four State Machine control Bytes */ | |
799 | #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ | |
800 | #define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ | |
801 | #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */ | |
802 | #define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */ | |
803 | ||
804 | /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ | |
805 | /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ | |
806 | /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ | |
807 | /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ | |
808 | /* The control status byte of each machine looks like ... */ | |
809 | #define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */ | |
810 | #define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */ | |
811 | #define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */ | |
812 | #define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */ | |
813 | #define SM_STEP 0x01 /* Bit 0: Step the State Machine */ | |
814 | ||
815 | /* The coding of the states */ | |
816 | #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */ | |
817 | #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */ | |
818 | #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */ | |
819 | #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */ | |
820 | #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */ | |
821 | #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */ | |
822 | #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */ | |
823 | ||
824 | #define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */ | |
825 | #define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */ | |
826 | #define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */ | |
827 | #define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */ | |
828 | #define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */ | |
829 | #define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */ | |
830 | ||
831 | #define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */ | |
832 | #define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */ | |
833 | #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */ | |
834 | #define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */ | |
835 | #define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */ | |
836 | ||
837 | #define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */ | |
838 | #define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */ | |
839 | #define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */ | |
840 | #define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */ | |
841 | #define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */ | |
842 | #define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */ | |
843 | #define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */ | |
844 | #define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */ | |
845 | #define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */ | |
846 | #define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */ | |
847 | #define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */ | |
848 | #define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */ | |
849 | #define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */ | |
850 | #define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */ | |
851 | #define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */ | |
852 | #define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */ | |
853 | ||
854 | /* B5_<xx>_T2 32 bit Test Register 2 (xx) */ | |
855 | /* Note: This register is only defined for the transmit queues */ | |
856 | /* Bit 31..8: reserved */ | |
857 | #define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */ | |
858 | #define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/ | |
859 | #define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */ | |
860 | #define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */ | |
861 | #define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */ | |
862 | #define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */ | |
863 | #define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */ | |
864 | #define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */ | |
865 | ||
866 | /* B5_<xx>_T3 32 bit Test Register 3 (xx) */ | |
867 | /* Note: This register is only defined for the transmit queues */ | |
868 | /* Bit 31..8: reserved */ | |
869 | #define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */ | |
870 | #define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */ | |
871 | #define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */ | |
872 | #define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */ | |
873 | #define T3_MUX (3<<2) /* Bit 3..2: Mux position */ | |
874 | #define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */ | |
875 | ||
876 | /* PCI card IDs */ | |
877 | /* | |
878 | * Note: The following 4 byte definitions shall not be used! Use OEM Concept! | |
879 | */ | |
880 | #define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */ | |
881 | #define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */ | |
882 | /* (High byte) */ | |
883 | #define PCI_DEV_ID0 0x00 /* PCI device ID */ | |
884 | #define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */ | |
885 | ||
886 | /*#define PCI_CLASS 0x02*/ /* PCI class code: network device */ | |
887 | #define PCI_NW_CLASS 0x02 /* PCI class code: network device */ | |
888 | #define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */ | |
889 | #define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */ | |
890 | ||
891 | /* | |
892 | * address transmission from logical to physical offset address on board | |
893 | */ | |
894 | #define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ | |
895 | #define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ | |
896 | #define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ | |
897 | #define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ | |
898 | ||
899 | /* | |
900 | * FlashProm specification | |
901 | */ | |
902 | #define MAX_PAGES 0x20000L /* Every byte has a single page */ | |
903 | #define MAX_FADDR 1 /* 1 byte per page */ | |
904 | ||
905 | /* | |
906 | * Receive / Transmit Buffer Control word | |
907 | */ | |
908 | #define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */ | |
909 | #define BMU_STF (1L<<30) /* Start of Frame ? */ | |
910 | #define BMU_EOF (1L<<29) /* End of Frame ? */ | |
911 | #define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */ | |
912 | #define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */ | |
913 | #define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */ | |
914 | #define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */ | |
915 | #define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */ | |
916 | #define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */ | |
917 | #define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */ | |
918 | #define BMU_CHECK 0x00550000L /* To identify the control word */ | |
919 | #define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */ | |
920 | ||
921 | /* | |
922 | * physical address offset + IO-Port base address | |
923 | */ | |
924 | #ifdef MEM_MAPPED_IO | |
925 | #define ADDR(a) (char far *) smc->hw.iop+(a) | |
926 | #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) | |
927 | #else | |
928 | #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ | |
929 | (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ | |
930 | (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) | |
931 | #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ | |
932 | ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ | |
933 | ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) | |
934 | #endif | |
935 | ||
936 | /* | |
937 | * Define a macro to access the configuration space | |
938 | */ | |
939 | #define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ | |
940 | ||
941 | #define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ | |
942 | ||
943 | /* | |
944 | * Define some values needed for the MAC address (PROM) | |
945 | */ | |
946 | #define SA_MAC (0) /* start addr. MAC_AD within the PROM */ | |
947 | #define PRA_OFF (0) /* offset correction when 4th byte reading */ | |
948 | ||
949 | #define SKFDDI_PSZ 8 /* address PROM size */ | |
950 | ||
951 | #define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ | |
952 | #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ | |
953 | #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ | |
954 | #define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ | |
955 | ||
956 | /* | |
957 | * Macro to read the PROM | |
958 | */ | |
959 | #define READ_PROM(a) ((u_char)inp(a)) | |
960 | ||
961 | #define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) | |
962 | #define VPP_ON() | |
963 | #define VPP_OFF() | |
964 | ||
965 | /* | |
966 | * Note: Values of the Interrupt Source Register are defined above | |
967 | */ | |
968 | #define ISR_A ADDR(B0_ISRC) | |
969 | #define GET_ISR() inpd(ISR_A) | |
970 | #define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC) | |
971 | #define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK))) | |
972 | #define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK)) | |
973 | ||
974 | #define BUS_CHECK() | |
975 | ||
976 | /* | |
977 | * CLI_FBI: Disable Board Interrupts | |
978 | * STI_FBI: Enable Board Interrupts | |
979 | */ | |
980 | #ifndef UNIX | |
981 | #define CLI_FBI() outpd(ADDR(B0_IMSK),0) | |
982 | #else | |
983 | #define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0) | |
984 | #endif | |
985 | ||
986 | #ifndef UNIX | |
987 | #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask) | |
988 | #else | |
989 | #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask) | |
990 | #endif | |
991 | ||
992 | #define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0) | |
993 | #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask) | |
994 | ||
995 | #endif /* PCI */ | |
996 | /*--------------------------------------------------------------------------*/ | |
997 | ||
998 | /* | |
999 | * 12 bit transfer (dword) counter: | |
1000 | * (ISA: 2*trc = number of byte) | |
1001 | * (EISA: 4*trc = number of byte) | |
1002 | * (MCA: 4*trc = number of byte) | |
1003 | */ | |
1004 | #define MAX_TRANS (0x0fff) | |
1005 | ||
1006 | /* | |
1007 | * PC PIC | |
1008 | */ | |
1009 | #define MST_8259 (0x20) | |
1010 | #define SLV_8259 (0xA0) | |
1011 | ||
1012 | #define TPS (18) /* ticks per second */ | |
1013 | ||
1014 | /* | |
1015 | * error timer defs | |
1016 | */ | |
1017 | #define TN (4) /* number of supported timer = TN+1 */ | |
1018 | #define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ | |
1019 | ||
1020 | #define MAC_AD 0x405a0000 | |
1021 | ||
1022 | #define MODR1 FM_A(FM_MDREG1) /* mode register 1 */ | |
1023 | #define MODR2 FM_A(FM_MDREG2) /* mode register 2 */ | |
1024 | ||
1025 | #define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ | |
1026 | #define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ | |
1027 | ||
1028 | ||
1029 | /* | |
1030 | * function defines | |
1031 | */ | |
1032 | #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) | |
1033 | #define SET(io,mask) outpw((io),inpw(io)|(mask)) | |
1034 | #define GET(io,mask) (inpw(io)&(mask)) | |
1035 | #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) | |
1036 | ||
1037 | /* | |
1038 | * PHY Port A (PA) = PLC 1 | |
1039 | * With SuperNet 3 PHY-A and PHY S are identical. | |
1040 | */ | |
1041 | #define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) | |
1042 | ||
1043 | /* | |
1044 | * set memory address register for write and read | |
1045 | */ | |
1046 | #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) | |
1047 | #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) | |
1048 | ||
1049 | /* | |
1050 | * read/write from/to memory data register | |
1051 | */ | |
1052 | /* write double word */ | |
1053 | #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\ | |
1054 | outpw(FM_A(FM_MDRL),(unsigned int)(dd)) | |
1055 | ||
1056 | #ifndef WINNT | |
1057 | /* read double word */ | |
1058 | #define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) | |
1059 | ||
1060 | /* read FORMAC+ 32-bit status register */ | |
1061 | #define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) | |
1062 | #define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) | |
1063 | #ifdef SUPERNET_3 | |
1064 | #define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L))) | |
1065 | #endif | |
1066 | #else | |
1067 | /* read double word */ | |
1068 | #define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL))) | |
1069 | ||
1070 | /* read FORMAC+ 32-bit status register */ | |
1071 | #define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L))) | |
1072 | #define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L))) | |
1073 | #ifdef SUPERNET_3 | |
1074 | #define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L))) | |
1075 | #endif | |
1076 | #endif | |
1077 | ||
1078 | /* Special timer macro for 82c54 */ | |
1079 | /* timer access over data bus bit 8..15 */ | |
1080 | #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) | |
1081 | #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) | |
1082 | ||
1083 | ||
1084 | #ifdef DEBUG | |
1085 | #define DB_MAC(mac,st) {if (debug_mac & 0x1)\ | |
1086 | printf("M") ;\ | |
1087 | if (debug_mac & 0x2)\ | |
1088 | printf("\tMAC %d status 0x%08lx\n",mac,st) ;\ | |
1089 | if (debug_mac & 0x4)\ | |
1090 | dp_mac(mac,st) ;\ | |
1091 | } | |
1092 | ||
1093 | #define DB_PLC(p,iev) { if (debug_plc & 0x1)\ | |
1094 | printf("P") ;\ | |
1095 | if (debug_plc & 0x2)\ | |
1096 | printf("\tPLC %s Int 0x%04x\n", \ | |
1097 | (p == PA) ? "A" : "B", iev) ;\ | |
1098 | if (debug_plc & 0x4)\ | |
1099 | dp_plc(p,iev) ;\ | |
1100 | } | |
1101 | ||
1102 | #define DB_TIMER() { if (debug_timer & 0x1)\ | |
1103 | printf("T") ;\ | |
1104 | if (debug_timer & 0x2)\ | |
1105 | printf("\tTimer ISR\n") ;\ | |
1106 | } | |
1107 | ||
1108 | #else /* no DEBUG */ | |
1109 | ||
1110 | #define DB_MAC(mac,st) | |
1111 | #define DB_PLC(p,iev) | |
1112 | #define DB_TIMER() | |
1113 | ||
1114 | #endif /* no DEBUG */ | |
1115 | ||
1116 | #define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp | |
1117 | /* | |
1118 | * timer defs | |
1119 | */ | |
1120 | #define COUNT(t) ((t)<<6) /* counter */ | |
1121 | #define RW_OP(o) ((o)<<4) /* read/write operation */ | |
1122 | #define TMODE(m) ((m)<<1) /* timer mode */ | |
1123 | ||
1124 | #endif |