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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
6f501b17 SH |
39 | #include <linux/io.h> |
40 | #include <linux/irq.h> | |
196719ec | 41 | #include <linux/clk.h> |
1da177e4 | 42 | |
080853af | 43 | #include <asm/cacheflush.h> |
196719ec SH |
44 | |
45 | #ifndef CONFIG_ARCH_MXC | |
1da177e4 LT |
46 | #include <asm/coldfire.h> |
47 | #include <asm/mcfsim.h> | |
196719ec | 48 | #endif |
6f501b17 | 49 | |
1da177e4 | 50 | #include "fec.h" |
1da177e4 LT |
51 | |
52 | #if defined(CONFIG_FEC2) | |
53 | #define FEC_MAX_PORTS 2 | |
54 | #else | |
55 | #define FEC_MAX_PORTS 1 | |
56 | #endif | |
57 | ||
196719ec SH |
58 | #ifdef CONFIG_ARCH_MXC |
59 | #include <mach/hardware.h> | |
60 | #define FEC_ALIGNMENT 0xf | |
61 | #else | |
62 | #define FEC_ALIGNMENT 0x3 | |
63 | #endif | |
64 | ||
87f4abb4 | 65 | #if defined(CONFIG_M5272) |
c1d96156 SS |
66 | #define HAVE_mii_link_interrupt |
67 | #endif | |
68 | ||
1da177e4 LT |
69 | /* |
70 | * Define the fixed address of the FEC hardware. | |
71 | */ | |
72 | static unsigned int fec_hw[] = { | |
73 | #if defined(CONFIG_M5272) | |
74 | (MCF_MBAR + 0x840), | |
75 | #elif defined(CONFIG_M527x) | |
76 | (MCF_MBAR + 0x1000), | |
77 | (MCF_MBAR + 0x1800), | |
7dd6a2aa | 78 | #elif defined(CONFIG_M523x) || defined(CONFIG_M528x) |
1da177e4 | 79 | (MCF_MBAR + 0x1000), |
562d2f8c GU |
80 | #elif defined(CONFIG_M520x) |
81 | (MCF_MBAR+0x30000), | |
6b265293 MW |
82 | #elif defined(CONFIG_M532x) |
83 | (MCF_MBAR+0xfc030000), | |
1da177e4 LT |
84 | #endif |
85 | }; | |
86 | ||
87 | static unsigned char fec_mac_default[] = { | |
88 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
89 | }; | |
90 | ||
91 | /* | |
92 | * Some hardware gets it MAC address out of local flash memory. | |
93 | * if this is non-zero then assume it is the address to get MAC from. | |
94 | */ | |
95 | #if defined(CONFIG_NETtel) | |
96 | #define FEC_FLASHMAC 0xf0006006 | |
97 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
98 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
99 | #elif defined(CONFIG_CANCam) |
100 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
101 | #elif defined (CONFIG_M5272C3) |
102 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
103 | #elif defined(CONFIG_MOD5272) | |
104 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
105 | #else |
106 | #define FEC_FLASHMAC 0 | |
107 | #endif | |
108 | ||
1da177e4 LT |
109 | /* Forward declarations of some structures to support different PHYs |
110 | */ | |
111 | ||
112 | typedef struct { | |
113 | uint mii_data; | |
114 | void (*funct)(uint mii_reg, struct net_device *dev); | |
115 | } phy_cmd_t; | |
116 | ||
117 | typedef struct { | |
118 | uint id; | |
119 | char *name; | |
120 | ||
121 | const phy_cmd_t *config; | |
122 | const phy_cmd_t *startup; | |
123 | const phy_cmd_t *ack_int; | |
124 | const phy_cmd_t *shutdown; | |
125 | } phy_info_t; | |
126 | ||
127 | /* The number of Tx and Rx buffers. These are allocated from the page | |
128 | * pool. The code may assume these are power of two, so it it best | |
129 | * to keep them that size. | |
130 | * We don't need to allocate pages for the transmitter. We just use | |
131 | * the skbuffer directly. | |
132 | */ | |
133 | #define FEC_ENET_RX_PAGES 8 | |
134 | #define FEC_ENET_RX_FRSIZE 2048 | |
135 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
136 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
137 | #define FEC_ENET_TX_FRSIZE 2048 | |
138 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
139 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
140 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
141 | ||
562d2f8c | 142 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 143 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
144 | #endif |
145 | ||
1da177e4 LT |
146 | /* Interrupt events/masks. |
147 | */ | |
148 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | |
149 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
150 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
151 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
152 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
153 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
154 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
155 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
156 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
157 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
158 | ||
159 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
160 | */ | |
161 | #define PKT_MAXBUF_SIZE 1518 | |
162 | #define PKT_MINBUF_SIZE 64 | |
163 | #define PKT_MAXBLR_SIZE 1520 | |
164 | ||
165 | ||
166 | /* | |
6b265293 | 167 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
168 | * size bits. Other FEC hardware does not, so we need to take that into |
169 | * account when setting it. | |
170 | */ | |
562d2f8c | 171 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
196719ec | 172 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
1da177e4 LT |
173 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
174 | #else | |
175 | #define OPT_FRAME_SIZE 0 | |
176 | #endif | |
177 | ||
178 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
179 | * tx_bd_base always point to the base of the buffer descriptors. The | |
180 | * cur_rx and cur_tx point to the currently available buffer. | |
181 | * The dirty_tx tracks the current buffer that is being sent by the | |
182 | * controller. The cur_tx and dirty_tx are equal under both completely | |
183 | * empty and completely full conditions. The empty/ready indicator in | |
184 | * the buffer descriptor determines the actual condition. | |
185 | */ | |
186 | struct fec_enet_private { | |
187 | /* Hardware registers of the FEC device */ | |
188 | volatile fec_t *hwp; | |
189 | ||
cb84d6e7 GU |
190 | struct net_device *netdev; |
191 | ||
1da177e4 LT |
192 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
193 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
194 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
195 | ushort skb_cur; | |
196 | ushort skb_dirty; | |
197 | ||
198 | /* CPM dual port RAM relative addresses. | |
199 | */ | |
4661e75b | 200 | dma_addr_t bd_dma; |
1da177e4 LT |
201 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ |
202 | cbd_t *tx_bd_base; | |
203 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | |
204 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | |
1da177e4 | 205 | uint tx_full; |
3b2b74ca SS |
206 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
207 | spinlock_t hw_lock; | |
208 | /* hold while accessing the mii_list_t() elements */ | |
209 | spinlock_t mii_lock; | |
1da177e4 LT |
210 | |
211 | uint phy_id; | |
212 | uint phy_id_done; | |
213 | uint phy_status; | |
214 | uint phy_speed; | |
7dd6a2aa | 215 | phy_info_t const *phy; |
1da177e4 LT |
216 | struct work_struct phy_task; |
217 | ||
218 | uint sequence_done; | |
219 | uint mii_phy_task_queued; | |
220 | ||
221 | uint phy_addr; | |
222 | ||
223 | int index; | |
224 | int opened; | |
225 | int link; | |
226 | int old_link; | |
227 | int full_duplex; | |
1da177e4 LT |
228 | }; |
229 | ||
230 | static int fec_enet_open(struct net_device *dev); | |
231 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
232 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 233 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
234 | static void fec_enet_tx(struct net_device *dev); |
235 | static void fec_enet_rx(struct net_device *dev); | |
236 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
237 | static void set_multicast_list(struct net_device *dev); |
238 | static void fec_restart(struct net_device *dev, int duplex); | |
239 | static void fec_stop(struct net_device *dev); | |
240 | static void fec_set_mac_address(struct net_device *dev); | |
241 | ||
242 | ||
243 | /* MII processing. We keep this as simple as possible. Requests are | |
244 | * placed on the list (if there is room). When the request is finished | |
245 | * by the MII, an optional function may be called. | |
246 | */ | |
247 | typedef struct mii_list { | |
248 | uint mii_regval; | |
249 | void (*mii_func)(uint val, struct net_device *dev); | |
250 | struct mii_list *mii_next; | |
251 | } mii_list_t; | |
252 | ||
253 | #define NMII 20 | |
7dd6a2aa GU |
254 | static mii_list_t mii_cmds[NMII]; |
255 | static mii_list_t *mii_free; | |
256 | static mii_list_t *mii_head; | |
257 | static mii_list_t *mii_tail; | |
1da177e4 | 258 | |
6aa20a22 | 259 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
260 | void (*func)(uint, struct net_device *)); |
261 | ||
262 | /* Make MII read/write commands for the FEC. | |
263 | */ | |
264 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
265 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
266 | (VAL & 0xffff)) | |
267 | #define mk_mii_end 0 | |
268 | ||
269 | /* Transmitter timeout. | |
270 | */ | |
271 | #define TX_TIMEOUT (2*HZ) | |
272 | ||
273 | /* Register definitions for the PHY. | |
274 | */ | |
275 | ||
276 | #define MII_REG_CR 0 /* Control Register */ | |
277 | #define MII_REG_SR 1 /* Status Register */ | |
278 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
279 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 280 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
281 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
282 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
283 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
284 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
285 | ||
286 | /* values for phy_status */ | |
287 | ||
288 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
289 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
290 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
291 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 292 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 293 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 294 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
295 | |
296 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
297 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
298 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
299 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
300 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 301 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 302 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 303 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
304 | |
305 | ||
306 | static int | |
307 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
308 | { | |
309 | struct fec_enet_private *fep; | |
310 | volatile fec_t *fecp; | |
311 | volatile cbd_t *bdp; | |
0e702ab3 | 312 | unsigned short status; |
3b2b74ca | 313 | unsigned long flags; |
1da177e4 LT |
314 | |
315 | fep = netdev_priv(dev); | |
316 | fecp = (volatile fec_t*)dev->base_addr; | |
317 | ||
318 | if (!fep->link) { | |
319 | /* Link is down or autonegotiation is in progress. */ | |
320 | return 1; | |
321 | } | |
322 | ||
3b2b74ca | 323 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
324 | /* Fill in a Tx ring entry */ |
325 | bdp = fep->cur_tx; | |
326 | ||
0e702ab3 | 327 | status = bdp->cbd_sc; |
1da177e4 | 328 | #ifndef final_version |
0e702ab3 | 329 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
330 | /* Ooops. All transmit buffers are full. Bail out. |
331 | * This should not happen, since dev->tbusy should be set. | |
332 | */ | |
333 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 334 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
335 | return 1; |
336 | } | |
337 | #endif | |
338 | ||
339 | /* Clear all of the status flags. | |
340 | */ | |
0e702ab3 | 341 | status &= ~BD_ENET_TX_STATS; |
1da177e4 LT |
342 | |
343 | /* Set buffer length and buffer pointer. | |
344 | */ | |
345 | bdp->cbd_bufaddr = __pa(skb->data); | |
346 | bdp->cbd_datlen = skb->len; | |
347 | ||
348 | /* | |
349 | * On some FEC implementations data must be aligned on | |
350 | * 4-byte boundaries. Use bounce buffers to copy data | |
351 | * and get it aligned. Ugh. | |
352 | */ | |
196719ec | 353 | if (bdp->cbd_bufaddr & FEC_ALIGNMENT) { |
1da177e4 LT |
354 | unsigned int index; |
355 | index = bdp - fep->tx_bd_base; | |
6989f512 | 356 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
1da177e4 LT |
357 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); |
358 | } | |
359 | ||
360 | /* Save skb pointer. | |
361 | */ | |
362 | fep->tx_skbuff[fep->skb_cur] = skb; | |
363 | ||
09f75cd7 | 364 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 365 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 366 | |
1da177e4 LT |
367 | /* Push the data cache so the CPM does not get stale memory |
368 | * data. | |
369 | */ | |
ccdc4f19 SH |
370 | dma_sync_single(NULL, bdp->cbd_bufaddr, |
371 | bdp->cbd_datlen, DMA_TO_DEVICE); | |
1da177e4 | 372 | |
0e702ab3 GU |
373 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
374 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 LT |
375 | */ |
376 | ||
0e702ab3 | 377 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 378 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 379 | bdp->cbd_sc = status; |
1da177e4 LT |
380 | |
381 | dev->trans_start = jiffies; | |
382 | ||
383 | /* Trigger transmission start */ | |
0e702ab3 | 384 | fecp->fec_x_des_active = 0; |
1da177e4 LT |
385 | |
386 | /* If this was the last BD in the ring, start at the beginning again. | |
387 | */ | |
0e702ab3 | 388 | if (status & BD_ENET_TX_WRAP) { |
1da177e4 LT |
389 | bdp = fep->tx_bd_base; |
390 | } else { | |
391 | bdp++; | |
392 | } | |
393 | ||
394 | if (bdp == fep->dirty_tx) { | |
395 | fep->tx_full = 1; | |
396 | netif_stop_queue(dev); | |
397 | } | |
398 | ||
399 | fep->cur_tx = (cbd_t *)bdp; | |
400 | ||
3b2b74ca | 401 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static void | |
407 | fec_timeout(struct net_device *dev) | |
408 | { | |
409 | struct fec_enet_private *fep = netdev_priv(dev); | |
410 | ||
411 | printk("%s: transmit timed out.\n", dev->name); | |
09f75cd7 | 412 | dev->stats.tx_errors++; |
1da177e4 LT |
413 | #ifndef final_version |
414 | { | |
415 | int i; | |
416 | cbd_t *bdp; | |
417 | ||
418 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
419 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
420 | (unsigned long)fep->dirty_tx, | |
421 | (unsigned long)fep->cur_rx); | |
422 | ||
423 | bdp = fep->tx_bd_base; | |
424 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
425 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 426 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
427 | (uint) bdp, |
428 | bdp->cbd_sc, | |
429 | bdp->cbd_datlen, | |
430 | (int) bdp->cbd_bufaddr); | |
431 | bdp++; | |
432 | } | |
433 | ||
434 | bdp = fep->rx_bd_base; | |
435 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
436 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
437 | printk(" %08x: %04x %04x %08x\n", | |
438 | (uint) bdp, | |
439 | bdp->cbd_sc, | |
440 | bdp->cbd_datlen, | |
441 | (int) bdp->cbd_bufaddr); | |
442 | bdp++; | |
443 | } | |
444 | } | |
445 | #endif | |
7dd6a2aa | 446 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
447 | netif_wake_queue(dev); |
448 | } | |
449 | ||
450 | /* The interrupt handler. | |
451 | * This is called from the MPC core interrupt. | |
452 | */ | |
453 | static irqreturn_t | |
7d12e780 | 454 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
455 | { |
456 | struct net_device *dev = dev_id; | |
457 | volatile fec_t *fecp; | |
458 | uint int_events; | |
3b2b74ca | 459 | irqreturn_t ret = IRQ_NONE; |
1da177e4 LT |
460 | |
461 | fecp = (volatile fec_t*)dev->base_addr; | |
462 | ||
463 | /* Get the interrupt events that caused us to be here. | |
464 | */ | |
3b2b74ca SS |
465 | do { |
466 | int_events = fecp->fec_ievent; | |
1da177e4 LT |
467 | fecp->fec_ievent = int_events; |
468 | ||
469 | /* Handle receive event in its own function. | |
470 | */ | |
471 | if (int_events & FEC_ENET_RXF) { | |
3b2b74ca | 472 | ret = IRQ_HANDLED; |
1da177e4 LT |
473 | fec_enet_rx(dev); |
474 | } | |
475 | ||
476 | /* Transmit OK, or non-fatal error. Update the buffer | |
477 | descriptors. FEC handles all errors, we just discover | |
478 | them as part of the transmit process. | |
479 | */ | |
480 | if (int_events & FEC_ENET_TXF) { | |
3b2b74ca | 481 | ret = IRQ_HANDLED; |
1da177e4 LT |
482 | fec_enet_tx(dev); |
483 | } | |
484 | ||
485 | if (int_events & FEC_ENET_MII) { | |
3b2b74ca | 486 | ret = IRQ_HANDLED; |
1da177e4 LT |
487 | fec_enet_mii(dev); |
488 | } | |
6aa20a22 | 489 | |
3b2b74ca SS |
490 | } while (int_events); |
491 | ||
492 | return ret; | |
1da177e4 LT |
493 | } |
494 | ||
495 | ||
496 | static void | |
497 | fec_enet_tx(struct net_device *dev) | |
498 | { | |
499 | struct fec_enet_private *fep; | |
500 | volatile cbd_t *bdp; | |
0e702ab3 | 501 | unsigned short status; |
1da177e4 LT |
502 | struct sk_buff *skb; |
503 | ||
504 | fep = netdev_priv(dev); | |
3b2b74ca | 505 | spin_lock_irq(&fep->hw_lock); |
1da177e4 LT |
506 | bdp = fep->dirty_tx; |
507 | ||
0e702ab3 | 508 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
509 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
510 | ||
511 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
512 | /* Check for errors. */ | |
0e702ab3 | 513 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
514 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
515 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 516 | dev->stats.tx_errors++; |
0e702ab3 | 517 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 518 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 519 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 520 | dev->stats.tx_window_errors++; |
0e702ab3 | 521 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 522 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 523 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 524 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 525 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 526 | dev->stats.tx_carrier_errors++; |
1da177e4 | 527 | } else { |
09f75cd7 | 528 | dev->stats.tx_packets++; |
1da177e4 LT |
529 | } |
530 | ||
531 | #ifndef final_version | |
0e702ab3 | 532 | if (status & BD_ENET_TX_READY) |
1da177e4 LT |
533 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
534 | #endif | |
535 | /* Deferred means some collisions occurred during transmit, | |
536 | * but we eventually sent the packet OK. | |
537 | */ | |
0e702ab3 | 538 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 539 | dev->stats.collisions++; |
6aa20a22 | 540 | |
1da177e4 LT |
541 | /* Free the sk buffer associated with this last transmit. |
542 | */ | |
543 | dev_kfree_skb_any(skb); | |
544 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
545 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 546 | |
1da177e4 LT |
547 | /* Update pointer to next buffer descriptor to be transmitted. |
548 | */ | |
0e702ab3 | 549 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
550 | bdp = fep->tx_bd_base; |
551 | else | |
552 | bdp++; | |
6aa20a22 | 553 | |
1da177e4 LT |
554 | /* Since we have freed up a buffer, the ring is no longer |
555 | * full. | |
556 | */ | |
557 | if (fep->tx_full) { | |
558 | fep->tx_full = 0; | |
559 | if (netif_queue_stopped(dev)) | |
560 | netif_wake_queue(dev); | |
561 | } | |
562 | } | |
563 | fep->dirty_tx = (cbd_t *)bdp; | |
3b2b74ca | 564 | spin_unlock_irq(&fep->hw_lock); |
1da177e4 LT |
565 | } |
566 | ||
567 | ||
568 | /* During a receive, the cur_rx points to the current incoming buffer. | |
569 | * When we update through the ring, if the next incoming buffer has | |
570 | * not been given to the system, we just set the empty indicator, | |
571 | * effectively tossing the packet. | |
572 | */ | |
573 | static void | |
574 | fec_enet_rx(struct net_device *dev) | |
575 | { | |
576 | struct fec_enet_private *fep; | |
577 | volatile fec_t *fecp; | |
578 | volatile cbd_t *bdp; | |
0e702ab3 | 579 | unsigned short status; |
1da177e4 LT |
580 | struct sk_buff *skb; |
581 | ushort pkt_len; | |
582 | __u8 *data; | |
6aa20a22 | 583 | |
0e702ab3 GU |
584 | #ifdef CONFIG_M532x |
585 | flush_cache_all(); | |
6aa20a22 | 586 | #endif |
1da177e4 LT |
587 | |
588 | fep = netdev_priv(dev); | |
589 | fecp = (volatile fec_t*)dev->base_addr; | |
590 | ||
3b2b74ca SS |
591 | spin_lock_irq(&fep->hw_lock); |
592 | ||
1da177e4 LT |
593 | /* First, grab all of the stats for the incoming packet. |
594 | * These get messed up if we get called due to a busy condition. | |
595 | */ | |
596 | bdp = fep->cur_rx; | |
597 | ||
0e702ab3 | 598 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 LT |
599 | |
600 | #ifndef final_version | |
601 | /* Since we have allocated space to hold a complete frame, | |
602 | * the last indicator should be set. | |
603 | */ | |
0e702ab3 | 604 | if ((status & BD_ENET_RX_LAST) == 0) |
1da177e4 LT |
605 | printk("FEC ENET: rcv is not +last\n"); |
606 | #endif | |
607 | ||
608 | if (!fep->opened) | |
609 | goto rx_processing_done; | |
610 | ||
611 | /* Check for errors. */ | |
0e702ab3 | 612 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
1da177e4 | 613 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
09f75cd7 | 614 | dev->stats.rx_errors++; |
0e702ab3 | 615 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
1da177e4 | 616 | /* Frame too long or too short. */ |
09f75cd7 | 617 | dev->stats.rx_length_errors++; |
1da177e4 | 618 | } |
0e702ab3 | 619 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
09f75cd7 | 620 | dev->stats.rx_frame_errors++; |
0e702ab3 | 621 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
09f75cd7 | 622 | dev->stats.rx_crc_errors++; |
0e702ab3 | 623 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
09f75cd7 | 624 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
625 | } |
626 | ||
627 | /* Report late collisions as a frame error. | |
628 | * On this error, the BD is closed, but we don't know what we | |
629 | * have in the buffer. So, just drop this frame on the floor. | |
630 | */ | |
0e702ab3 | 631 | if (status & BD_ENET_RX_CL) { |
09f75cd7 JG |
632 | dev->stats.rx_errors++; |
633 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
634 | goto rx_processing_done; |
635 | } | |
636 | ||
637 | /* Process the incoming frame. | |
638 | */ | |
09f75cd7 | 639 | dev->stats.rx_packets++; |
1da177e4 | 640 | pkt_len = bdp->cbd_datlen; |
09f75cd7 | 641 | dev->stats.rx_bytes += pkt_len; |
1da177e4 LT |
642 | data = (__u8*)__va(bdp->cbd_bufaddr); |
643 | ||
ccdc4f19 SH |
644 | dma_sync_single(NULL, (unsigned long)__pa(data), |
645 | pkt_len - 4, DMA_FROM_DEVICE); | |
646 | ||
1da177e4 LT |
647 | /* This does 16 byte alignment, exactly what we need. |
648 | * The packet length includes FCS, but we don't want to | |
649 | * include that when passing upstream as it messes up | |
650 | * bridging applications. | |
651 | */ | |
652 | skb = dev_alloc_skb(pkt_len-4); | |
653 | ||
654 | if (skb == NULL) { | |
655 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
09f75cd7 | 656 | dev->stats.rx_dropped++; |
1da177e4 | 657 | } else { |
1da177e4 | 658 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 659 | skb_copy_to_linear_data(skb, data, pkt_len-4); |
1da177e4 LT |
660 | skb->protocol=eth_type_trans(skb,dev); |
661 | netif_rx(skb); | |
662 | } | |
663 | rx_processing_done: | |
664 | ||
665 | /* Clear the status flags for this buffer. | |
666 | */ | |
0e702ab3 | 667 | status &= ~BD_ENET_RX_STATS; |
1da177e4 LT |
668 | |
669 | /* Mark the buffer empty. | |
670 | */ | |
0e702ab3 GU |
671 | status |= BD_ENET_RX_EMPTY; |
672 | bdp->cbd_sc = status; | |
1da177e4 LT |
673 | |
674 | /* Update BD pointer to next entry. | |
675 | */ | |
0e702ab3 | 676 | if (status & BD_ENET_RX_WRAP) |
1da177e4 LT |
677 | bdp = fep->rx_bd_base; |
678 | else | |
679 | bdp++; | |
6aa20a22 | 680 | |
1da177e4 LT |
681 | #if 1 |
682 | /* Doing this here will keep the FEC running while we process | |
683 | * incoming frames. On a heavily loaded network, we should be | |
684 | * able to keep up at the expense of system resources. | |
685 | */ | |
0e702ab3 | 686 | fecp->fec_r_des_active = 0; |
1da177e4 | 687 | #endif |
0e702ab3 | 688 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
1da177e4 LT |
689 | fep->cur_rx = (cbd_t *)bdp; |
690 | ||
691 | #if 0 | |
692 | /* Doing this here will allow us to process all frames in the | |
693 | * ring before the FEC is allowed to put more there. On a heavily | |
694 | * loaded network, some frames may be lost. Unfortunately, this | |
695 | * increases the interrupt overhead since we can potentially work | |
696 | * our way back to the interrupt return only to come right back | |
697 | * here. | |
698 | */ | |
0e702ab3 | 699 | fecp->fec_r_des_active = 0; |
1da177e4 | 700 | #endif |
3b2b74ca SS |
701 | |
702 | spin_unlock_irq(&fep->hw_lock); | |
1da177e4 LT |
703 | } |
704 | ||
705 | ||
0e702ab3 | 706 | /* called from interrupt context */ |
1da177e4 LT |
707 | static void |
708 | fec_enet_mii(struct net_device *dev) | |
709 | { | |
710 | struct fec_enet_private *fep; | |
711 | volatile fec_t *ep; | |
712 | mii_list_t *mip; | |
713 | uint mii_reg; | |
714 | ||
715 | fep = netdev_priv(dev); | |
3b2b74ca SS |
716 | spin_lock_irq(&fep->mii_lock); |
717 | ||
1da177e4 LT |
718 | ep = fep->hwp; |
719 | mii_reg = ep->fec_mii_data; | |
0e702ab3 | 720 | |
1da177e4 LT |
721 | if ((mip = mii_head) == NULL) { |
722 | printk("MII and no head!\n"); | |
0e702ab3 | 723 | goto unlock; |
1da177e4 LT |
724 | } |
725 | ||
726 | if (mip->mii_func != NULL) | |
727 | (*(mip->mii_func))(mii_reg, dev); | |
728 | ||
729 | mii_head = mip->mii_next; | |
730 | mip->mii_next = mii_free; | |
731 | mii_free = mip; | |
732 | ||
733 | if ((mip = mii_head) != NULL) | |
734 | ep->fec_mii_data = mip->mii_regval; | |
0e702ab3 GU |
735 | |
736 | unlock: | |
3b2b74ca | 737 | spin_unlock_irq(&fep->mii_lock); |
1da177e4 LT |
738 | } |
739 | ||
740 | static int | |
741 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
742 | { | |
743 | struct fec_enet_private *fep; | |
744 | unsigned long flags; | |
745 | mii_list_t *mip; | |
746 | int retval; | |
747 | ||
748 | /* Add PHY address to register command. | |
749 | */ | |
750 | fep = netdev_priv(dev); | |
3b2b74ca | 751 | spin_lock_irqsave(&fep->mii_lock, flags); |
1da177e4 | 752 | |
3b2b74ca | 753 | regval |= fep->phy_addr << 23; |
1da177e4 LT |
754 | retval = 0; |
755 | ||
1da177e4 LT |
756 | if ((mip = mii_free) != NULL) { |
757 | mii_free = mip->mii_next; | |
758 | mip->mii_regval = regval; | |
759 | mip->mii_func = func; | |
760 | mip->mii_next = NULL; | |
761 | if (mii_head) { | |
762 | mii_tail->mii_next = mip; | |
763 | mii_tail = mip; | |
f909b1ef | 764 | } else { |
1da177e4 LT |
765 | mii_head = mii_tail = mip; |
766 | fep->hwp->fec_mii_data = regval; | |
767 | } | |
f909b1ef | 768 | } else { |
1da177e4 LT |
769 | retval = 1; |
770 | } | |
771 | ||
3b2b74ca SS |
772 | spin_unlock_irqrestore(&fep->mii_lock, flags); |
773 | return retval; | |
1da177e4 LT |
774 | } |
775 | ||
776 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
777 | { | |
1da177e4 LT |
778 | if(!c) |
779 | return; | |
780 | ||
be6cb66d PDM |
781 | for (; c->mii_data != mk_mii_end; c++) |
782 | mii_queue(dev, c->mii_data, c->funct); | |
1da177e4 LT |
783 | } |
784 | ||
785 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
786 | { | |
787 | struct fec_enet_private *fep = netdev_priv(dev); | |
788 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 789 | uint status; |
1da177e4 | 790 | |
7dd6a2aa | 791 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
792 | |
793 | if (mii_reg & 0x0004) | |
7dd6a2aa | 794 | status |= PHY_STAT_LINK; |
1da177e4 | 795 | if (mii_reg & 0x0010) |
7dd6a2aa | 796 | status |= PHY_STAT_FAULT; |
1da177e4 | 797 | if (mii_reg & 0x0020) |
7dd6a2aa | 798 | status |= PHY_STAT_ANC; |
7dd6a2aa | 799 | *s = status; |
1da177e4 LT |
800 | } |
801 | ||
802 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
803 | { | |
804 | struct fec_enet_private *fep = netdev_priv(dev); | |
805 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 806 | uint status; |
1da177e4 | 807 | |
7dd6a2aa | 808 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
809 | |
810 | if (mii_reg & 0x1000) | |
7dd6a2aa | 811 | status |= PHY_CONF_ANE; |
1da177e4 | 812 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
813 | status |= PHY_CONF_LOOP; |
814 | *s = status; | |
1da177e4 LT |
815 | } |
816 | ||
817 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
818 | { | |
819 | struct fec_enet_private *fep = netdev_priv(dev); | |
820 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 821 | uint status; |
1da177e4 | 822 | |
7dd6a2aa | 823 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
824 | |
825 | if (mii_reg & 0x0020) | |
7dd6a2aa | 826 | status |= PHY_CONF_10HDX; |
1da177e4 | 827 | if (mii_reg & 0x0040) |
7dd6a2aa | 828 | status |= PHY_CONF_10FDX; |
1da177e4 | 829 | if (mii_reg & 0x0080) |
7dd6a2aa | 830 | status |= PHY_CONF_100HDX; |
1da177e4 | 831 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
832 | status |= PHY_CONF_100FDX; |
833 | *s = status; | |
1da177e4 LT |
834 | } |
835 | ||
836 | /* ------------------------------------------------------------------------- */ | |
837 | /* The Level one LXT970 is used by many boards */ | |
838 | ||
839 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
840 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
841 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
842 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
843 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
844 | ||
845 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
846 | { | |
847 | struct fec_enet_private *fep = netdev_priv(dev); | |
848 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 849 | uint status; |
1da177e4 | 850 | |
7dd6a2aa | 851 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
852 | if (mii_reg & 0x0800) { |
853 | if (mii_reg & 0x1000) | |
7dd6a2aa | 854 | status |= PHY_STAT_100FDX; |
1da177e4 | 855 | else |
7dd6a2aa | 856 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
857 | } else { |
858 | if (mii_reg & 0x1000) | |
7dd6a2aa | 859 | status |= PHY_STAT_10FDX; |
1da177e4 | 860 | else |
7dd6a2aa | 861 | status |= PHY_STAT_10HDX; |
1da177e4 | 862 | } |
7dd6a2aa | 863 | *s = status; |
1da177e4 LT |
864 | } |
865 | ||
7dd6a2aa | 866 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
867 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
868 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
869 | { mk_mii_end, } | |
7dd6a2aa GU |
870 | }; |
871 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
872 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
873 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
874 | { mk_mii_end, } | |
7dd6a2aa GU |
875 | }; |
876 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
877 | /* read SR and ISR to acknowledge */ |
878 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
879 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
880 | ||
881 | /* find out the current status */ | |
882 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
883 | { mk_mii_end, } | |
7dd6a2aa GU |
884 | }; |
885 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
886 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
887 | { mk_mii_end, } | |
7dd6a2aa GU |
888 | }; |
889 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 890 | .id = 0x07810000, |
7dd6a2aa GU |
891 | .name = "LXT970", |
892 | .config = phy_cmd_lxt970_config, | |
893 | .startup = phy_cmd_lxt970_startup, | |
894 | .ack_int = phy_cmd_lxt970_ack_int, | |
895 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 896 | }; |
6aa20a22 | 897 | |
1da177e4 LT |
898 | /* ------------------------------------------------------------------------- */ |
899 | /* The Level one LXT971 is used on some of my custom boards */ | |
900 | ||
901 | /* register definitions for the 971 */ | |
902 | ||
903 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
904 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
905 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
906 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
907 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
908 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
909 | ||
6aa20a22 | 910 | /* |
1da177e4 LT |
911 | * I had some nice ideas of running the MDIO faster... |
912 | * The 971 should support 8MHz and I tried it, but things acted really | |
913 | * weird, so 2.5 MHz ought to be enough for anyone... | |
914 | */ | |
915 | ||
916 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
917 | { | |
918 | struct fec_enet_private *fep = netdev_priv(dev); | |
919 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 920 | uint status; |
1da177e4 | 921 | |
7dd6a2aa | 922 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
923 | |
924 | if (mii_reg & 0x0400) { | |
925 | fep->link = 1; | |
7dd6a2aa | 926 | status |= PHY_STAT_LINK; |
1da177e4 LT |
927 | } else { |
928 | fep->link = 0; | |
929 | } | |
930 | if (mii_reg & 0x0080) | |
7dd6a2aa | 931 | status |= PHY_STAT_ANC; |
1da177e4 LT |
932 | if (mii_reg & 0x4000) { |
933 | if (mii_reg & 0x0200) | |
7dd6a2aa | 934 | status |= PHY_STAT_100FDX; |
1da177e4 | 935 | else |
7dd6a2aa | 936 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
937 | } else { |
938 | if (mii_reg & 0x0200) | |
7dd6a2aa | 939 | status |= PHY_STAT_10FDX; |
1da177e4 | 940 | else |
7dd6a2aa | 941 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
942 | } |
943 | if (mii_reg & 0x0008) | |
7dd6a2aa | 944 | status |= PHY_STAT_FAULT; |
1da177e4 | 945 | |
7dd6a2aa GU |
946 | *s = status; |
947 | } | |
6aa20a22 | 948 | |
7dd6a2aa | 949 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 950 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
951 | * doesn't work with 100. */ |
952 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
953 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
954 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
955 | { mk_mii_end, } | |
7dd6a2aa GU |
956 | }; |
957 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
958 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
959 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
960 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
961 | /* Somehow does the 971 tell me that the link is down | |
962 | * the first read after power-up. | |
963 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 964 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 965 | { mk_mii_end, } |
7dd6a2aa GU |
966 | }; |
967 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
968 | /* acknowledge the int before reading status ! */ | |
969 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
970 | /* find out the current status */ |
971 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
972 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 973 | { mk_mii_end, } |
7dd6a2aa GU |
974 | }; |
975 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
976 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
977 | { mk_mii_end, } | |
7dd6a2aa GU |
978 | }; |
979 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 980 | .id = 0x0001378e, |
7dd6a2aa GU |
981 | .name = "LXT971", |
982 | .config = phy_cmd_lxt971_config, | |
983 | .startup = phy_cmd_lxt971_startup, | |
984 | .ack_int = phy_cmd_lxt971_ack_int, | |
985 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
986 | }; |
987 | ||
988 | /* ------------------------------------------------------------------------- */ | |
989 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
990 | ||
991 | /* register definitions */ | |
992 | ||
993 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
994 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
995 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
996 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
997 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
998 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
999 | ||
1000 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
1001 | { | |
1002 | struct fec_enet_private *fep = netdev_priv(dev); | |
1003 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1004 | uint status; |
1da177e4 | 1005 | |
7dd6a2aa | 1006 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
1007 | |
1008 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
1009 | case 1: status |= PHY_STAT_10HDX; break; |
1010 | case 2: status |= PHY_STAT_100HDX; break; | |
1011 | case 5: status |= PHY_STAT_10FDX; break; | |
1012 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
1013 | } |
1014 | ||
7dd6a2aa GU |
1015 | *s = status; |
1016 | } | |
1017 | ||
1018 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 1019 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
1020 | * so send a command to allow operation. |
1021 | */ | |
1022 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
1023 | ||
1024 | /* parse cr and anar to get some info */ | |
1025 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1026 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1027 | { mk_mii_end, } | |
7dd6a2aa GU |
1028 | }; |
1029 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1030 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
1031 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1032 | { mk_mii_end, } | |
7dd6a2aa GU |
1033 | }; |
1034 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
1035 | /* we need to read ISR, SR and ANER to acknowledge */ |
1036 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
1037 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1038 | { mk_mii_read(MII_REG_ANER), NULL }, | |
1039 | ||
1040 | /* read pcr to get info */ | |
1041 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
1042 | { mk_mii_end, } | |
7dd6a2aa GU |
1043 | }; |
1044 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1045 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
1046 | { mk_mii_end, } | |
7dd6a2aa GU |
1047 | }; |
1048 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 1049 | .id = 0x00181440, |
7dd6a2aa GU |
1050 | .name = "QS6612", |
1051 | .config = phy_cmd_qs6612_config, | |
1052 | .startup = phy_cmd_qs6612_startup, | |
1053 | .ack_int = phy_cmd_qs6612_ack_int, | |
1054 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
1055 | }; |
1056 | ||
1057 | /* ------------------------------------------------------------------------- */ | |
1058 | /* AMD AM79C874 phy */ | |
1059 | ||
1060 | /* register definitions for the 874 */ | |
1061 | ||
1062 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
1063 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
1064 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
1065 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
1066 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
1067 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
1068 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
1069 | ||
1070 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
1071 | { | |
1072 | struct fec_enet_private *fep = netdev_priv(dev); | |
1073 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1074 | uint status; |
1da177e4 | 1075 | |
7dd6a2aa | 1076 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1077 | |
1078 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1079 | status |= PHY_STAT_ANC; |
1da177e4 | 1080 | if (mii_reg & 0x0400) |
7dd6a2aa | 1081 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1082 | else |
7dd6a2aa GU |
1083 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1084 | ||
1085 | *s = status; | |
1da177e4 LT |
1086 | } |
1087 | ||
7dd6a2aa | 1088 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1089 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1090 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1091 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1092 | { mk_mii_end, } | |
7dd6a2aa GU |
1093 | }; |
1094 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1095 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1096 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1097 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1098 | { mk_mii_end, } |
7dd6a2aa GU |
1099 | }; |
1100 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1101 | /* find out the current status */ |
1102 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1103 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1104 | /* we only need to read ISR to acknowledge */ | |
1105 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1106 | { mk_mii_end, } | |
7dd6a2aa GU |
1107 | }; |
1108 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1109 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1110 | { mk_mii_end, } | |
7dd6a2aa GU |
1111 | }; |
1112 | static phy_info_t const phy_info_am79c874 = { | |
1113 | .id = 0x00022561, | |
1114 | .name = "AM79C874", | |
1115 | .config = phy_cmd_am79c874_config, | |
1116 | .startup = phy_cmd_am79c874_startup, | |
1117 | .ack_int = phy_cmd_am79c874_ack_int, | |
1118 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1119 | }; |
1120 | ||
7dd6a2aa | 1121 | |
1da177e4 LT |
1122 | /* ------------------------------------------------------------------------- */ |
1123 | /* Kendin KS8721BL phy */ | |
1124 | ||
1125 | /* register definitions for the 8721 */ | |
1126 | ||
1127 | #define MII_KS8721BL_RXERCR 21 | |
43268dce | 1128 | #define MII_KS8721BL_ICSR 27 |
1da177e4 LT |
1129 | #define MII_KS8721BL_PHYCR 31 |
1130 | ||
7dd6a2aa | 1131 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1132 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1133 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1134 | { mk_mii_end, } | |
7dd6a2aa GU |
1135 | }; |
1136 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1137 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1138 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1139 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1140 | { mk_mii_end, } |
7dd6a2aa GU |
1141 | }; |
1142 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1143 | /* find out the current status */ |
1144 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1145 | /* we only need to read ISR to acknowledge */ | |
1146 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1147 | { mk_mii_end, } | |
7dd6a2aa GU |
1148 | }; |
1149 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1150 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1151 | { mk_mii_end, } | |
7dd6a2aa GU |
1152 | }; |
1153 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1154 | .id = 0x00022161, |
7dd6a2aa GU |
1155 | .name = "KS8721BL", |
1156 | .config = phy_cmd_ks8721bl_config, | |
1157 | .startup = phy_cmd_ks8721bl_startup, | |
1158 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1159 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1160 | }; |
1161 | ||
562d2f8c GU |
1162 | /* ------------------------------------------------------------------------- */ |
1163 | /* register definitions for the DP83848 */ | |
1164 | ||
1165 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1166 | ||
1167 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1168 | { | |
4cf1653a | 1169 | struct fec_enet_private *fep = netdev_priv(dev); |
562d2f8c GU |
1170 | volatile uint *s = &(fep->phy_status); |
1171 | ||
1172 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1173 | ||
1174 | /* Link up */ | |
1175 | if (mii_reg & 0x0001) { | |
1176 | fep->link = 1; | |
1177 | *s |= PHY_STAT_LINK; | |
1178 | } else | |
1179 | fep->link = 0; | |
1180 | /* Status of link */ | |
1181 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1182 | *s |= PHY_STAT_ANC; | |
1183 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1184 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1185 | *s |= PHY_STAT_10FDX; | |
1186 | else | |
1187 | *s |= PHY_STAT_10HDX; | |
1188 | } else { /* 100 Mbps? */ | |
1189 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1190 | *s |= PHY_STAT_100FDX; | |
1191 | else | |
1192 | *s |= PHY_STAT_100HDX; | |
1193 | } | |
1194 | if (mii_reg & 0x0008) | |
1195 | *s |= PHY_STAT_FAULT; | |
1196 | } | |
1197 | ||
1198 | static phy_info_t phy_info_dp83848= { | |
1199 | 0x020005c9, | |
1200 | "DP83848", | |
1201 | ||
1202 | (const phy_cmd_t []) { /* config */ | |
1203 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1204 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1205 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1206 | { mk_mii_end, } | |
1207 | }, | |
1208 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1209 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1210 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1211 | { mk_mii_end, } | |
1212 | }, | |
1213 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1214 | { mk_mii_end, } | |
1215 | }, | |
1216 | (const phy_cmd_t []) { /* shutdown */ | |
1217 | { mk_mii_end, } | |
1218 | }, | |
1219 | }; | |
1220 | ||
1da177e4 LT |
1221 | /* ------------------------------------------------------------------------- */ |
1222 | ||
7dd6a2aa | 1223 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1224 | &phy_info_lxt970, |
1225 | &phy_info_lxt971, | |
1226 | &phy_info_qs6612, | |
1227 | &phy_info_am79c874, | |
1228 | &phy_info_ks8721bl, | |
562d2f8c | 1229 | &phy_info_dp83848, |
1da177e4 LT |
1230 | NULL |
1231 | }; | |
1232 | ||
1233 | /* ------------------------------------------------------------------------- */ | |
c1d96156 | 1234 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1235 | static irqreturn_t |
7d12e780 | 1236 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 LT |
1237 | #endif |
1238 | ||
1239 | #if defined(CONFIG_M5272) | |
1da177e4 LT |
1240 | /* |
1241 | * Code specific to Coldfire 5272 setup. | |
1242 | */ | |
1243 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1244 | { | |
1245 | volatile unsigned long *icrp; | |
7dd6a2aa GU |
1246 | static const struct idesc { |
1247 | char *name; | |
1248 | unsigned short irq; | |
7d12e780 | 1249 | irq_handler_t handler; |
7dd6a2aa GU |
1250 | } *idp, id[] = { |
1251 | { "fec(RX)", 86, fec_enet_interrupt }, | |
1252 | { "fec(TX)", 87, fec_enet_interrupt }, | |
1253 | { "fec(OTHER)", 88, fec_enet_interrupt }, | |
1254 | { "fec(MII)", 66, mii_link_interrupt }, | |
1255 | { NULL }, | |
1256 | }; | |
1da177e4 LT |
1257 | |
1258 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1259 | for (idp = id; idp->name; idp++) { |
0a504779 | 1260 | if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1261 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); |
1262 | } | |
1da177e4 LT |
1263 | |
1264 | /* Unmask interrupt at ColdFire 5272 SIM */ | |
1265 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3); | |
1266 | *icrp = 0x00000ddd; | |
1267 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1268 | *icrp = 0x0d000000; |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1272 | { | |
1273 | volatile fec_t *fecp; | |
1274 | ||
1275 | fecp = fep->hwp; | |
1276 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1277 | fecp->fec_x_cntrl = 0x00; | |
1278 | ||
1279 | /* | |
1280 | * Set MII speed to 2.5 MHz | |
1281 | * See 5272 manual section 11.5.8: MSCR | |
1282 | */ | |
1283 | fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2; | |
1284 | fecp->fec_mii_speed = fep->phy_speed; | |
1285 | ||
1286 | fec_restart(dev, 0); | |
1287 | } | |
1288 | ||
1289 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1290 | { | |
1291 | struct fec_enet_private *fep = netdev_priv(dev); | |
1292 | volatile fec_t *fecp; | |
7dd6a2aa | 1293 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1294 | |
1295 | fecp = fep->hwp; | |
1296 | ||
7dd6a2aa | 1297 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1298 | /* |
1299 | * Get MAC address from FLASH. | |
1300 | * If it is all 1's or 0's, use the default. | |
1301 | */ | |
7dd6a2aa | 1302 | iap = (unsigned char *)FEC_FLASHMAC; |
1da177e4 LT |
1303 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1304 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1305 | iap = fec_mac_default; | |
1306 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1307 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1308 | iap = fec_mac_default; | |
1309 | } else { | |
1310 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1311 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1312 | iap = &tmpaddr[0]; | |
1313 | } | |
1314 | ||
7dd6a2aa | 1315 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1316 | |
1317 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1318 | if (iap == fec_mac_default) |
1319 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1320 | } |
1321 | ||
1da177e4 LT |
1322 | static void __inline__ fec_disable_phy_intr(void) |
1323 | { | |
1324 | volatile unsigned long *icrp; | |
1325 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1326 | *icrp = 0x08000000; |
1da177e4 LT |
1327 | } |
1328 | ||
1329 | static void __inline__ fec_phy_ack_intr(void) | |
1330 | { | |
1331 | volatile unsigned long *icrp; | |
1332 | /* Acknowledge the interrupt */ | |
1333 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1334 | *icrp = 0x0d000000; |
1da177e4 LT |
1335 | } |
1336 | ||
1da177e4 LT |
1337 | /* ------------------------------------------------------------------------- */ |
1338 | ||
7dd6a2aa | 1339 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) |
1da177e4 LT |
1340 | |
1341 | /* | |
7dd6a2aa GU |
1342 | * Code specific to Coldfire 5230/5231/5232/5234/5235, |
1343 | * the 5270/5271/5274/5275 and 5280/5282 setups. | |
1da177e4 LT |
1344 | */ |
1345 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1346 | { | |
1347 | struct fec_enet_private *fep; | |
1348 | int b; | |
7dd6a2aa GU |
1349 | static const struct idesc { |
1350 | char *name; | |
1351 | unsigned short irq; | |
1352 | } *idp, id[] = { | |
1353 | { "fec(TXF)", 23 }, | |
7dd6a2aa | 1354 | { "fec(RXF)", 27 }, |
7dd6a2aa | 1355 | { "fec(MII)", 29 }, |
7dd6a2aa GU |
1356 | { NULL }, |
1357 | }; | |
1da177e4 LT |
1358 | |
1359 | fep = netdev_priv(dev); | |
1360 | b = (fep->index) ? 128 : 64; | |
1361 | ||
1362 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1363 | for (idp = id; idp->name; idp++) { |
0a504779 | 1364 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1365 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1366 | } | |
1da177e4 LT |
1367 | |
1368 | /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */ | |
1369 | { | |
1370 | volatile unsigned char *icrp; | |
1371 | volatile unsigned long *imrp; | |
83901fc1 | 1372 | int i, ilip; |
1da177e4 LT |
1373 | |
1374 | b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0; | |
1375 | icrp = (volatile unsigned char *) (MCF_IPSBAR + b + | |
1376 | MCFINTC_ICR0); | |
83901fc1 WC |
1377 | for (i = 23, ilip = 0x28; (i < 36); i++) |
1378 | icrp[i] = ilip--; | |
1da177e4 LT |
1379 | |
1380 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1381 | MCFINTC_IMRH); | |
1382 | *imrp &= ~0x0000000f; | |
1383 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1384 | MCFINTC_IMRL); | |
1385 | *imrp &= ~0xff800001; | |
1386 | } | |
1387 | ||
1388 | #if defined(CONFIG_M528x) | |
1389 | /* Set up gpio outputs for MII lines */ | |
1390 | { | |
7dd6a2aa GU |
1391 | volatile u16 *gpio_paspar; |
1392 | volatile u8 *gpio_pehlpar; | |
6aa20a22 | 1393 | |
7dd6a2aa GU |
1394 | gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056); |
1395 | gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058); | |
1396 | *gpio_paspar |= 0x0f00; | |
1397 | *gpio_pehlpar = 0xc0; | |
1da177e4 LT |
1398 | } |
1399 | #endif | |
b8a94b3d MC |
1400 | |
1401 | #if defined(CONFIG_M527x) | |
1402 | /* Set up gpio outputs for MII lines */ | |
1403 | { | |
1404 | volatile u8 *gpio_par_fec; | |
1405 | volatile u16 *gpio_par_feci2c; | |
1406 | ||
1407 | gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082); | |
1408 | /* Set up gpio outputs for FEC0 MII lines */ | |
1409 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078); | |
1410 | ||
1411 | *gpio_par_feci2c |= 0x0f00; | |
1412 | *gpio_par_fec |= 0xc0; | |
1413 | ||
1414 | #if defined(CONFIG_FEC2) | |
1415 | /* Set up gpio outputs for FEC1 MII lines */ | |
1416 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079); | |
1417 | ||
1418 | *gpio_par_feci2c |= 0x00a0; | |
1419 | *gpio_par_fec |= 0xc0; | |
1420 | #endif /* CONFIG_FEC2 */ | |
1421 | } | |
1422 | #endif /* CONFIG_M527x */ | |
1da177e4 LT |
1423 | } |
1424 | ||
1425 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1426 | { | |
1427 | volatile fec_t *fecp; | |
1428 | ||
1429 | fecp = fep->hwp; | |
1430 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1431 | fecp->fec_x_cntrl = 0x00; | |
1432 | ||
1433 | /* | |
1434 | * Set MII speed to 2.5 MHz | |
1435 | * See 5282 manual section 17.5.4.7: MSCR | |
1436 | */ | |
1437 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1438 | fecp->fec_mii_speed = fep->phy_speed; | |
1439 | ||
1440 | fec_restart(dev, 0); | |
1441 | } | |
1442 | ||
1443 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1444 | { | |
1445 | struct fec_enet_private *fep = netdev_priv(dev); | |
1446 | volatile fec_t *fecp; | |
7dd6a2aa | 1447 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1448 | |
1449 | fecp = fep->hwp; | |
1450 | ||
7dd6a2aa | 1451 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1452 | /* |
1453 | * Get MAC address from FLASH. | |
1454 | * If it is all 1's or 0's, use the default. | |
1455 | */ | |
7dd6a2aa | 1456 | iap = FEC_FLASHMAC; |
1da177e4 LT |
1457 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1458 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1459 | iap = fec_mac_default; | |
1460 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1461 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1462 | iap = fec_mac_default; | |
1463 | } else { | |
1464 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1465 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1466 | iap = &tmpaddr[0]; | |
1467 | } | |
1468 | ||
7dd6a2aa | 1469 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1470 | |
1471 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1472 | if (iap == fec_mac_default) |
1473 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1474 | } |
1475 | ||
1da177e4 LT |
1476 | static void __inline__ fec_disable_phy_intr(void) |
1477 | { | |
1478 | } | |
1479 | ||
1480 | static void __inline__ fec_phy_ack_intr(void) | |
1481 | { | |
1482 | } | |
1483 | ||
1da177e4 LT |
1484 | /* ------------------------------------------------------------------------- */ |
1485 | ||
562d2f8c GU |
1486 | #elif defined(CONFIG_M520x) |
1487 | ||
1488 | /* | |
1489 | * Code specific to Coldfire 520x | |
1490 | */ | |
1491 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1492 | { | |
1493 | struct fec_enet_private *fep; | |
1494 | int b; | |
1495 | static const struct idesc { | |
1496 | char *name; | |
1497 | unsigned short irq; | |
1498 | } *idp, id[] = { | |
1499 | { "fec(TXF)", 23 }, | |
562d2f8c | 1500 | { "fec(RXF)", 27 }, |
562d2f8c | 1501 | { "fec(MII)", 29 }, |
562d2f8c GU |
1502 | { NULL }, |
1503 | }; | |
1504 | ||
1505 | fep = netdev_priv(dev); | |
1506 | b = 64 + 13; | |
1507 | ||
1508 | /* Setup interrupt handlers. */ | |
1509 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1510 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
562d2f8c GU |
1511 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1512 | } | |
1513 | ||
1514 | /* Unmask interrupts at ColdFire interrupt controller */ | |
1515 | { | |
1516 | volatile unsigned char *icrp; | |
1517 | volatile unsigned long *imrp; | |
1518 | ||
1519 | icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1520 | MCFINTC_ICR0); | |
1521 | for (b = 36; (b < 49); b++) | |
1522 | icrp[b] = 0x04; | |
1523 | imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1524 | MCFINTC_IMRH); | |
1525 | *imrp &= ~0x0001FFF0; | |
1526 | } | |
1527 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0; | |
1528 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f; | |
1529 | } | |
1530 | ||
1531 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1532 | { | |
1533 | volatile fec_t *fecp; | |
1534 | ||
1535 | fecp = fep->hwp; | |
1536 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1537 | fecp->fec_x_cntrl = 0x00; | |
1538 | ||
1539 | /* | |
1540 | * Set MII speed to 2.5 MHz | |
1541 | * See 5282 manual section 17.5.4.7: MSCR | |
1542 | */ | |
1543 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1544 | fecp->fec_mii_speed = fep->phy_speed; | |
1545 | ||
1546 | fec_restart(dev, 0); | |
1547 | } | |
1548 | ||
1549 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1550 | { | |
1551 | struct fec_enet_private *fep = netdev_priv(dev); | |
1552 | volatile fec_t *fecp; | |
1553 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1554 | ||
1555 | fecp = fep->hwp; | |
1556 | ||
1557 | if (FEC_FLASHMAC) { | |
1558 | /* | |
1559 | * Get MAC address from FLASH. | |
1560 | * If it is all 1's or 0's, use the default. | |
1561 | */ | |
1562 | iap = FEC_FLASHMAC; | |
1563 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1564 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1565 | iap = fec_mac_default; | |
1566 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1567 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1568 | iap = fec_mac_default; | |
1569 | } else { | |
1570 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1571 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1572 | iap = &tmpaddr[0]; | |
1573 | } | |
1574 | ||
1575 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1576 | ||
1577 | /* Adjust MAC if using default MAC address */ | |
1578 | if (iap == fec_mac_default) | |
1579 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1580 | } | |
1581 | ||
562d2f8c GU |
1582 | static void __inline__ fec_disable_phy_intr(void) |
1583 | { | |
1584 | } | |
1585 | ||
1586 | static void __inline__ fec_phy_ack_intr(void) | |
1587 | { | |
1588 | } | |
1589 | ||
562d2f8c GU |
1590 | /* ------------------------------------------------------------------------- */ |
1591 | ||
6b265293 MW |
1592 | #elif defined(CONFIG_M532x) |
1593 | /* | |
1594 | * Code specific for M532x | |
1595 | */ | |
1596 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1597 | { | |
1598 | struct fec_enet_private *fep; | |
1599 | int b; | |
1600 | static const struct idesc { | |
1601 | char *name; | |
1602 | unsigned short irq; | |
1603 | } *idp, id[] = { | |
1604 | { "fec(TXF)", 36 }, | |
6b265293 | 1605 | { "fec(RXF)", 40 }, |
6b265293 | 1606 | { "fec(MII)", 42 }, |
6b265293 MW |
1607 | { NULL }, |
1608 | }; | |
1609 | ||
1610 | fep = netdev_priv(dev); | |
1611 | b = (fep->index) ? 128 : 64; | |
1612 | ||
1613 | /* Setup interrupt handlers. */ | |
1614 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1615 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
6aa20a22 | 1616 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
6b265293 MW |
1617 | idp->name, b+idp->irq); |
1618 | } | |
1619 | ||
1620 | /* Unmask interrupts */ | |
1621 | MCF_INTC0_ICR36 = 0x2; | |
1622 | MCF_INTC0_ICR37 = 0x2; | |
1623 | MCF_INTC0_ICR38 = 0x2; | |
1624 | MCF_INTC0_ICR39 = 0x2; | |
1625 | MCF_INTC0_ICR40 = 0x2; | |
1626 | MCF_INTC0_ICR41 = 0x2; | |
1627 | MCF_INTC0_ICR42 = 0x2; | |
1628 | MCF_INTC0_ICR43 = 0x2; | |
1629 | MCF_INTC0_ICR44 = 0x2; | |
1630 | MCF_INTC0_ICR45 = 0x2; | |
1631 | MCF_INTC0_ICR46 = 0x2; | |
1632 | MCF_INTC0_ICR47 = 0x2; | |
1633 | MCF_INTC0_ICR48 = 0x2; | |
1634 | ||
1635 | MCF_INTC0_IMRH &= ~( | |
1636 | MCF_INTC_IMRH_INT_MASK36 | | |
1637 | MCF_INTC_IMRH_INT_MASK37 | | |
1638 | MCF_INTC_IMRH_INT_MASK38 | | |
1639 | MCF_INTC_IMRH_INT_MASK39 | | |
1640 | MCF_INTC_IMRH_INT_MASK40 | | |
1641 | MCF_INTC_IMRH_INT_MASK41 | | |
1642 | MCF_INTC_IMRH_INT_MASK42 | | |
1643 | MCF_INTC_IMRH_INT_MASK43 | | |
1644 | MCF_INTC_IMRH_INT_MASK44 | | |
1645 | MCF_INTC_IMRH_INT_MASK45 | | |
1646 | MCF_INTC_IMRH_INT_MASK46 | | |
1647 | MCF_INTC_IMRH_INT_MASK47 | | |
1648 | MCF_INTC_IMRH_INT_MASK48 ); | |
1649 | ||
1650 | /* Set up gpio outputs for MII lines */ | |
1651 | MCF_GPIO_PAR_FECI2C |= (0 | | |
1652 | MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | | |
1653 | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); | |
1654 | MCF_GPIO_PAR_FEC = (0 | | |
1655 | MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | | |
1656 | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); | |
1657 | } | |
1658 | ||
1659 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1660 | { | |
1661 | volatile fec_t *fecp; | |
1662 | ||
1663 | fecp = fep->hwp; | |
1664 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1665 | fecp->fec_x_cntrl = 0x00; | |
1666 | ||
1667 | /* | |
1668 | * Set MII speed to 2.5 MHz | |
1669 | */ | |
1670 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1671 | fecp->fec_mii_speed = fep->phy_speed; | |
1672 | ||
1673 | fec_restart(dev, 0); | |
1674 | } | |
1675 | ||
1676 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1677 | { | |
1678 | struct fec_enet_private *fep = netdev_priv(dev); | |
1679 | volatile fec_t *fecp; | |
1680 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1681 | ||
1682 | fecp = fep->hwp; | |
1683 | ||
1684 | if (FEC_FLASHMAC) { | |
1685 | /* | |
1686 | * Get MAC address from FLASH. | |
1687 | * If it is all 1's or 0's, use the default. | |
1688 | */ | |
1689 | iap = FEC_FLASHMAC; | |
1690 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1691 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1692 | iap = fec_mac_default; | |
1693 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1694 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1695 | iap = fec_mac_default; | |
1696 | } else { | |
1697 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1698 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1699 | iap = &tmpaddr[0]; | |
1700 | } | |
1701 | ||
1702 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1703 | ||
1704 | /* Adjust MAC if using default MAC address */ | |
1705 | if (iap == fec_mac_default) | |
1706 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1707 | } | |
1708 | ||
6b265293 MW |
1709 | static void __inline__ fec_disable_phy_intr(void) |
1710 | { | |
1711 | } | |
1712 | ||
1713 | static void __inline__ fec_phy_ack_intr(void) | |
1714 | { | |
1715 | } | |
1716 | ||
1da177e4 LT |
1717 | #endif |
1718 | ||
1719 | /* ------------------------------------------------------------------------- */ | |
1720 | ||
1721 | static void mii_display_status(struct net_device *dev) | |
1722 | { | |
1723 | struct fec_enet_private *fep = netdev_priv(dev); | |
1724 | volatile uint *s = &(fep->phy_status); | |
1725 | ||
1726 | if (!fep->link && !fep->old_link) { | |
1727 | /* Link is still down - don't print anything */ | |
1728 | return; | |
1729 | } | |
1730 | ||
1731 | printk("%s: status: ", dev->name); | |
1732 | ||
1733 | if (!fep->link) { | |
1734 | printk("link down"); | |
1735 | } else { | |
1736 | printk("link up"); | |
1737 | ||
1738 | switch(*s & PHY_STAT_SPMASK) { | |
1739 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1740 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1741 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1742 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1743 | default: | |
1744 | printk(", Unknown speed/duplex"); | |
1745 | } | |
1746 | ||
1747 | if (*s & PHY_STAT_ANC) | |
1748 | printk(", auto-negotiation complete"); | |
1749 | } | |
1750 | ||
1751 | if (*s & PHY_STAT_FAULT) | |
1752 | printk(", remote fault"); | |
1753 | ||
1754 | printk(".\n"); | |
1755 | } | |
1756 | ||
cb84d6e7 | 1757 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1758 | { |
cb84d6e7 GU |
1759 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1760 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1761 | uint status = fep->phy_status; |
1da177e4 LT |
1762 | |
1763 | /* | |
1764 | ** When we get here, phy_task is already removed from | |
1765 | ** the workqueue. It is thus safe to allow to reuse it. | |
1766 | */ | |
1767 | fep->mii_phy_task_queued = 0; | |
1768 | printk("%s: config: auto-negotiation ", dev->name); | |
1769 | ||
7dd6a2aa | 1770 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1771 | printk("on"); |
1772 | else | |
1773 | printk("off"); | |
1774 | ||
7dd6a2aa | 1775 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1776 | printk(", 100FDX"); |
7dd6a2aa | 1777 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1778 | printk(", 100HDX"); |
7dd6a2aa | 1779 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1780 | printk(", 10FDX"); |
7dd6a2aa | 1781 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1782 | printk(", 10HDX"); |
7dd6a2aa | 1783 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1784 | printk(", No speed/duplex selected?"); |
1785 | ||
7dd6a2aa | 1786 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1787 | printk(", loopback enabled"); |
6aa20a22 | 1788 | |
1da177e4 LT |
1789 | printk(".\n"); |
1790 | ||
1791 | fep->sequence_done = 1; | |
1792 | } | |
1793 | ||
cb84d6e7 | 1794 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1795 | { |
cb84d6e7 GU |
1796 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1797 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1798 | int duplex; |
1799 | ||
1800 | /* | |
1801 | ** When we get here, phy_task is already removed from | |
1802 | ** the workqueue. It is thus safe to allow to reuse it. | |
1803 | */ | |
1804 | fep->mii_phy_task_queued = 0; | |
1805 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1806 | mii_display_status(dev); | |
1807 | fep->old_link = fep->link; | |
1808 | ||
1809 | if (fep->link) { | |
1810 | duplex = 0; | |
6aa20a22 | 1811 | if (fep->phy_status |
1da177e4 LT |
1812 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
1813 | duplex = 1; | |
1814 | fec_restart(dev, duplex); | |
f909b1ef | 1815 | } else |
1da177e4 LT |
1816 | fec_stop(dev); |
1817 | ||
1818 | #if 0 | |
1819 | enable_irq(fep->mii_irq); | |
1820 | #endif | |
1821 | ||
1822 | } | |
1823 | ||
1824 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
1825 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
1826 | { | |
1827 | struct fec_enet_private *fep = netdev_priv(dev); | |
1828 | ||
1829 | /* | |
1830 | ** We cannot queue phy_task twice in the workqueue. It | |
1831 | ** would cause an endless loop in the workqueue. | |
1832 | ** Fortunately, if the last mii_relink entry has not yet been | |
1833 | ** executed now, it will do the job for the current interrupt, | |
1834 | ** which is just what we want. | |
1835 | */ | |
1836 | if (fep->mii_phy_task_queued) | |
1837 | return; | |
1838 | ||
1839 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1840 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
1841 | schedule_work(&fep->phy_task); |
1842 | } | |
1843 | ||
7dd6a2aa | 1844 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
1845 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
1846 | { | |
1847 | struct fec_enet_private *fep = netdev_priv(dev); | |
1848 | ||
1849 | if (fep->mii_phy_task_queued) | |
1850 | return; | |
1851 | ||
1852 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1853 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
1854 | schedule_work(&fep->phy_task); |
1855 | } | |
1856 | ||
7dd6a2aa GU |
1857 | phy_cmd_t const phy_cmd_relink[] = { |
1858 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
1859 | { mk_mii_end, } | |
1860 | }; | |
1861 | phy_cmd_t const phy_cmd_config[] = { | |
1862 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
1863 | { mk_mii_end, } | |
1864 | }; | |
1da177e4 LT |
1865 | |
1866 | /* Read remainder of PHY ID. | |
1867 | */ | |
1868 | static void | |
1869 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
1870 | { | |
1871 | struct fec_enet_private *fep; | |
1872 | int i; | |
1873 | ||
1874 | fep = netdev_priv(dev); | |
1875 | fep->phy_id |= (mii_reg & 0xffff); | |
1876 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
1877 | ||
1878 | for(i = 0; phy_info[i]; i++) { | |
1879 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
1880 | break; | |
1881 | } | |
1882 | ||
1883 | if (phy_info[i]) | |
1884 | printk(" -- %s\n", phy_info[i]->name); | |
1885 | else | |
1886 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 1887 | |
1da177e4 LT |
1888 | fep->phy = phy_info[i]; |
1889 | fep->phy_id_done = 1; | |
1890 | } | |
1891 | ||
1892 | /* Scan all of the MII PHY addresses looking for someone to respond | |
1893 | * with a valid ID. This usually happens quickly. | |
1894 | */ | |
1895 | static void | |
1896 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
1897 | { | |
1898 | struct fec_enet_private *fep; | |
1899 | volatile fec_t *fecp; | |
1900 | uint phytype; | |
1901 | ||
1902 | fep = netdev_priv(dev); | |
1903 | fecp = fep->hwp; | |
1904 | ||
1905 | if (fep->phy_addr < 32) { | |
1906 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 1907 | |
1da177e4 LT |
1908 | /* Got first part of ID, now get remainder. |
1909 | */ | |
1910 | fep->phy_id = phytype << 16; | |
1911 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
1912 | mii_discover_phy3); | |
f909b1ef | 1913 | } else { |
1da177e4 LT |
1914 | fep->phy_addr++; |
1915 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
1916 | mii_discover_phy); | |
1917 | } | |
1918 | } else { | |
1919 | printk("FEC: No PHY device found.\n"); | |
1920 | /* Disable external MII interface */ | |
1921 | fecp->fec_mii_speed = fep->phy_speed = 0; | |
1922 | fec_disable_phy_intr(); | |
1923 | } | |
1924 | } | |
1925 | ||
1926 | /* This interrupt occurs when the PHY detects a link change. | |
1927 | */ | |
c1d96156 | 1928 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1929 | static irqreturn_t |
7d12e780 | 1930 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
1931 | { |
1932 | struct net_device *dev = dev_id; | |
1933 | struct fec_enet_private *fep = netdev_priv(dev); | |
1934 | ||
1935 | fec_phy_ack_intr(); | |
1936 | ||
1937 | #if 0 | |
1938 | disable_irq(fep->mii_irq); /* disable now, enable later */ | |
1939 | #endif | |
1940 | ||
1941 | mii_do_cmd(dev, fep->phy->ack_int); | |
1942 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
1943 | ||
1944 | return IRQ_HANDLED; | |
1945 | } | |
c1d96156 | 1946 | #endif |
1da177e4 LT |
1947 | |
1948 | static int | |
1949 | fec_enet_open(struct net_device *dev) | |
1950 | { | |
1951 | struct fec_enet_private *fep = netdev_priv(dev); | |
1952 | ||
1953 | /* I should reset the ring buffers here, but I don't yet know | |
1954 | * a simple way to do that. | |
1955 | */ | |
1956 | fec_set_mac_address(dev); | |
1957 | ||
1958 | fep->sequence_done = 0; | |
1959 | fep->link = 0; | |
1960 | ||
1961 | if (fep->phy) { | |
1962 | mii_do_cmd(dev, fep->phy->ack_int); | |
1963 | mii_do_cmd(dev, fep->phy->config); | |
1964 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
1965 | ||
6b265293 MW |
1966 | /* Poll until the PHY tells us its configuration |
1967 | * (not link state). | |
1968 | * Request is initiated by mii_do_cmd above, but answer | |
1969 | * comes by interrupt. | |
1970 | * This should take about 25 usec per register at 2.5 MHz, | |
1971 | * and we read approximately 5 registers. | |
1da177e4 LT |
1972 | */ |
1973 | while(!fep->sequence_done) | |
1974 | schedule(); | |
1975 | ||
1976 | mii_do_cmd(dev, fep->phy->startup); | |
1977 | ||
1978 | /* Set the initial link state to true. A lot of hardware | |
1979 | * based on this device does not implement a PHY interrupt, | |
1980 | * so we are never notified of link change. | |
1981 | */ | |
1982 | fep->link = 1; | |
1983 | } else { | |
1984 | fep->link = 1; /* lets just try it and see */ | |
1985 | /* no phy, go full duplex, it's most likely a hub chip */ | |
1986 | fec_restart(dev, 1); | |
1987 | } | |
1988 | ||
1989 | netif_start_queue(dev); | |
1990 | fep->opened = 1; | |
1991 | return 0; /* Success */ | |
1992 | } | |
1993 | ||
1994 | static int | |
1995 | fec_enet_close(struct net_device *dev) | |
1996 | { | |
1997 | struct fec_enet_private *fep = netdev_priv(dev); | |
1998 | ||
1999 | /* Don't know what to do yet. | |
2000 | */ | |
2001 | fep->opened = 0; | |
2002 | netif_stop_queue(dev); | |
2003 | fec_stop(dev); | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
1da177e4 LT |
2008 | /* Set or clear the multicast filter for this adaptor. |
2009 | * Skeleton taken from sunlance driver. | |
2010 | * The CPM Ethernet implementation allows Multicast as well as individual | |
2011 | * MAC address filtering. Some of the drivers check to make sure it is | |
2012 | * a group multicast address, and discard those that are not. I guess I | |
2013 | * will do the same for now, but just remove the test if you want | |
2014 | * individual filtering as well (do the upper net layers want or support | |
2015 | * this kind of feature?). | |
2016 | */ | |
2017 | ||
2018 | #define HASH_BITS 6 /* #bits in hash */ | |
2019 | #define CRC32_POLY 0xEDB88320 | |
2020 | ||
2021 | static void set_multicast_list(struct net_device *dev) | |
2022 | { | |
2023 | struct fec_enet_private *fep; | |
2024 | volatile fec_t *ep; | |
2025 | struct dev_mc_list *dmi; | |
2026 | unsigned int i, j, bit, data, crc; | |
2027 | unsigned char hash; | |
2028 | ||
2029 | fep = netdev_priv(dev); | |
2030 | ep = fep->hwp; | |
2031 | ||
2032 | if (dev->flags&IFF_PROMISC) { | |
1da177e4 LT |
2033 | ep->fec_r_cntrl |= 0x0008; |
2034 | } else { | |
2035 | ||
2036 | ep->fec_r_cntrl &= ~0x0008; | |
2037 | ||
2038 | if (dev->flags & IFF_ALLMULTI) { | |
2039 | /* Catch all multicast addresses, so set the | |
2040 | * filter to all 1's. | |
2041 | */ | |
cc462f7d GU |
2042 | ep->fec_grp_hash_table_high = 0xffffffff; |
2043 | ep->fec_grp_hash_table_low = 0xffffffff; | |
1da177e4 LT |
2044 | } else { |
2045 | /* Clear filter and add the addresses in hash register. | |
2046 | */ | |
cc462f7d GU |
2047 | ep->fec_grp_hash_table_high = 0; |
2048 | ep->fec_grp_hash_table_low = 0; | |
6aa20a22 | 2049 | |
1da177e4 LT |
2050 | dmi = dev->mc_list; |
2051 | ||
2052 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) | |
2053 | { | |
2054 | /* Only support group multicast for now. | |
2055 | */ | |
2056 | if (!(dmi->dmi_addr[0] & 1)) | |
2057 | continue; | |
6aa20a22 | 2058 | |
1da177e4 LT |
2059 | /* calculate crc32 value of mac address |
2060 | */ | |
2061 | crc = 0xffffffff; | |
2062 | ||
2063 | for (i = 0; i < dmi->dmi_addrlen; i++) | |
2064 | { | |
2065 | data = dmi->dmi_addr[i]; | |
2066 | for (bit = 0; bit < 8; bit++, data >>= 1) | |
2067 | { | |
2068 | crc = (crc >> 1) ^ | |
2069 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | /* only upper 6 bits (HASH_BITS) are used | |
2074 | which point to specific bit in he hash registers | |
2075 | */ | |
2076 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
6aa20a22 | 2077 | |
1da177e4 | 2078 | if (hash > 31) |
cc462f7d | 2079 | ep->fec_grp_hash_table_high |= 1 << (hash - 32); |
1da177e4 | 2080 | else |
cc462f7d | 2081 | ep->fec_grp_hash_table_low |= 1 << hash; |
1da177e4 LT |
2082 | } |
2083 | } | |
2084 | } | |
2085 | } | |
2086 | ||
2087 | /* Set a MAC change in hardware. | |
2088 | */ | |
2089 | static void | |
2090 | fec_set_mac_address(struct net_device *dev) | |
2091 | { | |
1da177e4 LT |
2092 | volatile fec_t *fecp; |
2093 | ||
7dd6a2aa | 2094 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; |
1da177e4 LT |
2095 | |
2096 | /* Set station address. */ | |
7dd6a2aa GU |
2097 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
2098 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); | |
2099 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | | |
2100 | (dev->dev_addr[4] << 24); | |
1da177e4 LT |
2101 | |
2102 | } | |
2103 | ||
2104 | /* Initialize the FEC Ethernet on 860T (or ColdFire 5272). | |
2105 | */ | |
2106 | /* | |
2107 | * XXX: We need to clean up on failure exits here. | |
2108 | */ | |
2109 | int __init fec_enet_init(struct net_device *dev) | |
2110 | { | |
2111 | struct fec_enet_private *fep = netdev_priv(dev); | |
2112 | unsigned long mem_addr; | |
2113 | volatile cbd_t *bdp; | |
2114 | cbd_t *cbd_base; | |
2115 | volatile fec_t *fecp; | |
2116 | int i, j; | |
2117 | static int index = 0; | |
2118 | ||
2119 | /* Only allow us to be probed once. */ | |
2120 | if (index >= FEC_MAX_PORTS) | |
2121 | return -ENXIO; | |
2122 | ||
562d2f8c GU |
2123 | /* Allocate memory for buffer descriptors. |
2124 | */ | |
4661e75b SH |
2125 | mem_addr = (unsigned long)dma_alloc_coherent(NULL, PAGE_SIZE, |
2126 | &fep->bd_dma, GFP_KERNEL); | |
562d2f8c GU |
2127 | if (mem_addr == 0) { |
2128 | printk("FEC: allocate descriptor memory failed?\n"); | |
2129 | return -ENOMEM; | |
2130 | } | |
2131 | ||
3b2b74ca SS |
2132 | spin_lock_init(&fep->hw_lock); |
2133 | spin_lock_init(&fep->mii_lock); | |
2134 | ||
1da177e4 LT |
2135 | /* Create an Ethernet device instance. |
2136 | */ | |
2137 | fecp = (volatile fec_t *) fec_hw[index]; | |
2138 | ||
2139 | fep->index = index; | |
2140 | fep->hwp = fecp; | |
cb84d6e7 | 2141 | fep->netdev = dev; |
1da177e4 LT |
2142 | |
2143 | /* Whack a reset. We should wait for this. | |
2144 | */ | |
2145 | fecp->fec_ecntrl = 1; | |
2146 | udelay(10); | |
2147 | ||
1da177e4 LT |
2148 | /* Set the Ethernet address. If using multiple Enets on the 8xx, |
2149 | * this needs some work to get unique addresses. | |
2150 | * | |
2151 | * This is our default MAC address unless the user changes | |
2152 | * it via eth_mac_addr (our dev->set_mac_addr handler). | |
2153 | */ | |
2154 | fec_get_mac(dev); | |
2155 | ||
1da177e4 LT |
2156 | cbd_base = (cbd_t *)mem_addr; |
2157 | /* XXX: missing check for allocation failure */ | |
2158 | ||
1da177e4 LT |
2159 | /* Set receive and transmit descriptor base. |
2160 | */ | |
2161 | fep->rx_bd_base = cbd_base; | |
2162 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
2163 | ||
2164 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2165 | fep->cur_rx = fep->rx_bd_base; | |
2166 | ||
2167 | fep->skb_cur = fep->skb_dirty = 0; | |
2168 | ||
2169 | /* Initialize the receive buffer descriptors. | |
2170 | */ | |
2171 | bdp = fep->rx_bd_base; | |
2172 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
2173 | ||
2174 | /* Allocate a page. | |
2175 | */ | |
2176 | mem_addr = __get_free_page(GFP_KERNEL); | |
2177 | /* XXX: missing check for allocation failure */ | |
2178 | ||
1da177e4 LT |
2179 | /* Initialize the BD for every fragment in the page. |
2180 | */ | |
2181 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | |
2182 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2183 | bdp->cbd_bufaddr = __pa(mem_addr); | |
2184 | mem_addr += FEC_ENET_RX_FRSIZE; | |
2185 | bdp++; | |
2186 | } | |
2187 | } | |
2188 | ||
2189 | /* Set the last buffer to wrap. | |
2190 | */ | |
2191 | bdp--; | |
2192 | bdp->cbd_sc |= BD_SC_WRAP; | |
2193 | ||
2194 | /* ...and the same for transmmit. | |
2195 | */ | |
2196 | bdp = fep->tx_bd_base; | |
2197 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
2198 | if (j >= FEC_ENET_TX_FRPPG) { | |
2199 | mem_addr = __get_free_page(GFP_KERNEL); | |
2200 | j = 1; | |
2201 | } else { | |
2202 | mem_addr += FEC_ENET_TX_FRSIZE; | |
2203 | j++; | |
2204 | } | |
2205 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
2206 | ||
2207 | /* Initialize the BD for every fragment in the page. | |
2208 | */ | |
2209 | bdp->cbd_sc = 0; | |
2210 | bdp->cbd_bufaddr = 0; | |
2211 | bdp++; | |
2212 | } | |
2213 | ||
2214 | /* Set the last buffer to wrap. | |
2215 | */ | |
2216 | bdp--; | |
2217 | bdp->cbd_sc |= BD_SC_WRAP; | |
2218 | ||
2219 | /* Set receive and transmit descriptor base. | |
2220 | */ | |
4661e75b SH |
2221 | fecp->fec_r_des_start = fep->bd_dma; |
2222 | fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t) | |
2223 | * RX_RING_SIZE; | |
1da177e4 LT |
2224 | |
2225 | /* Install our interrupt handlers. This varies depending on | |
2226 | * the architecture. | |
2227 | */ | |
2228 | fec_request_intrs(dev); | |
2229 | ||
cc462f7d GU |
2230 | fecp->fec_grp_hash_table_high = 0; |
2231 | fecp->fec_grp_hash_table_low = 0; | |
562d2f8c GU |
2232 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
2233 | fecp->fec_ecntrl = 2; | |
6b265293 | 2234 | fecp->fec_r_des_active = 0; |
cc462f7d GU |
2235 | #ifndef CONFIG_M5272 |
2236 | fecp->fec_hash_table_high = 0; | |
2237 | fecp->fec_hash_table_low = 0; | |
2238 | #endif | |
562d2f8c | 2239 | |
1da177e4 LT |
2240 | dev->base_addr = (unsigned long)fecp; |
2241 | ||
2242 | /* The FEC Ethernet specific entries in the device structure. */ | |
2243 | dev->open = fec_enet_open; | |
2244 | dev->hard_start_xmit = fec_enet_start_xmit; | |
2245 | dev->tx_timeout = fec_timeout; | |
2246 | dev->watchdog_timeo = TX_TIMEOUT; | |
2247 | dev->stop = fec_enet_close; | |
1da177e4 LT |
2248 | dev->set_multicast_list = set_multicast_list; |
2249 | ||
2250 | for (i=0; i<NMII-1; i++) | |
2251 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
2252 | mii_free = mii_cmds; | |
2253 | ||
2254 | /* setup MII interface */ | |
2255 | fec_set_mii(dev, fep); | |
2256 | ||
6b265293 MW |
2257 | /* Clear and enable interrupts */ |
2258 | fecp->fec_ievent = 0xffc00000; | |
398ec922 | 2259 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
6b265293 | 2260 | |
1da177e4 LT |
2261 | /* Queue up command to detect the PHY and initialize the |
2262 | * remainder of the interface. | |
2263 | */ | |
2264 | fep->phy_id_done = 0; | |
2265 | fep->phy_addr = 0; | |
2266 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
2267 | ||
2268 | index++; | |
2269 | return 0; | |
2270 | } | |
2271 | ||
2272 | /* This function is called to start or restart the FEC during a link | |
2273 | * change. This only happens when switching between half and full | |
2274 | * duplex. | |
2275 | */ | |
2276 | static void | |
2277 | fec_restart(struct net_device *dev, int duplex) | |
2278 | { | |
2279 | struct fec_enet_private *fep; | |
2280 | volatile cbd_t *bdp; | |
2281 | volatile fec_t *fecp; | |
2282 | int i; | |
2283 | ||
2284 | fep = netdev_priv(dev); | |
2285 | fecp = fep->hwp; | |
2286 | ||
2287 | /* Whack a reset. We should wait for this. | |
2288 | */ | |
2289 | fecp->fec_ecntrl = 1; | |
2290 | udelay(10); | |
2291 | ||
1da177e4 LT |
2292 | /* Clear any outstanding interrupt. |
2293 | */ | |
7dd6a2aa | 2294 | fecp->fec_ievent = 0xffc00000; |
1da177e4 LT |
2295 | |
2296 | /* Set station address. | |
2297 | */ | |
7dd6a2aa | 2298 | fec_set_mac_address(dev); |
1da177e4 LT |
2299 | |
2300 | /* Reset all multicast. | |
2301 | */ | |
cc462f7d GU |
2302 | fecp->fec_grp_hash_table_high = 0; |
2303 | fecp->fec_grp_hash_table_low = 0; | |
1da177e4 LT |
2304 | |
2305 | /* Set maximum receive buffer size. | |
2306 | */ | |
2307 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | |
2308 | ||
1da177e4 LT |
2309 | /* Set receive and transmit descriptor base. |
2310 | */ | |
4661e75b SH |
2311 | fecp->fec_r_des_start = fep->bd_dma; |
2312 | fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t) | |
2313 | * RX_RING_SIZE; | |
1da177e4 LT |
2314 | |
2315 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2316 | fep->cur_rx = fep->rx_bd_base; | |
2317 | ||
2318 | /* Reset SKB transmit buffers. | |
2319 | */ | |
2320 | fep->skb_cur = fep->skb_dirty = 0; | |
2321 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | |
2322 | if (fep->tx_skbuff[i] != NULL) { | |
2323 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
2324 | fep->tx_skbuff[i] = NULL; | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | /* Initialize the receive buffer descriptors. | |
2329 | */ | |
2330 | bdp = fep->rx_bd_base; | |
2331 | for (i=0; i<RX_RING_SIZE; i++) { | |
2332 | ||
2333 | /* Initialize the BD for every fragment in the page. | |
2334 | */ | |
2335 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2336 | bdp++; | |
2337 | } | |
2338 | ||
2339 | /* Set the last buffer to wrap. | |
2340 | */ | |
2341 | bdp--; | |
2342 | bdp->cbd_sc |= BD_SC_WRAP; | |
2343 | ||
2344 | /* ...and the same for transmmit. | |
2345 | */ | |
2346 | bdp = fep->tx_bd_base; | |
2347 | for (i=0; i<TX_RING_SIZE; i++) { | |
2348 | ||
2349 | /* Initialize the BD for every fragment in the page. | |
2350 | */ | |
2351 | bdp->cbd_sc = 0; | |
2352 | bdp->cbd_bufaddr = 0; | |
2353 | bdp++; | |
2354 | } | |
2355 | ||
2356 | /* Set the last buffer to wrap. | |
2357 | */ | |
2358 | bdp--; | |
2359 | bdp->cbd_sc |= BD_SC_WRAP; | |
2360 | ||
2361 | /* Enable MII mode. | |
2362 | */ | |
2363 | if (duplex) { | |
2364 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ | |
2365 | fecp->fec_x_cntrl = 0x04; /* FD enable */ | |
f909b1ef | 2366 | } else { |
1da177e4 LT |
2367 | /* MII enable|No Rcv on Xmit */ |
2368 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; | |
2369 | fecp->fec_x_cntrl = 0x00; | |
2370 | } | |
2371 | fep->full_duplex = duplex; | |
2372 | ||
2373 | /* Set MII speed. | |
2374 | */ | |
2375 | fecp->fec_mii_speed = fep->phy_speed; | |
2376 | ||
2377 | /* And last, enable the transmit and receive processing. | |
2378 | */ | |
2379 | fecp->fec_ecntrl = 2; | |
6b265293 MW |
2380 | fecp->fec_r_des_active = 0; |
2381 | ||
2382 | /* Enable interrupts we wish to service. | |
2383 | */ | |
398ec922 | 2384 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
1da177e4 LT |
2385 | } |
2386 | ||
2387 | static void | |
2388 | fec_stop(struct net_device *dev) | |
2389 | { | |
2390 | volatile fec_t *fecp; | |
2391 | struct fec_enet_private *fep; | |
2392 | ||
2393 | fep = netdev_priv(dev); | |
2394 | fecp = fep->hwp; | |
2395 | ||
677177c5 PDM |
2396 | /* |
2397 | ** We cannot expect a graceful transmit stop without link !!! | |
2398 | */ | |
2399 | if (fep->link) | |
2400 | { | |
2401 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | |
2402 | udelay(10); | |
2403 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) | |
2404 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
2405 | } | |
1da177e4 LT |
2406 | |
2407 | /* Whack a reset. We should wait for this. | |
2408 | */ | |
2409 | fecp->fec_ecntrl = 1; | |
2410 | udelay(10); | |
2411 | ||
2412 | /* Clear outstanding MII command interrupts. | |
2413 | */ | |
2414 | fecp->fec_ievent = FEC_ENET_MII; | |
1da177e4 LT |
2415 | |
2416 | fecp->fec_imask = FEC_ENET_MII; | |
2417 | fecp->fec_mii_speed = fep->phy_speed; | |
2418 | } | |
2419 | ||
2420 | static int __init fec_enet_module_init(void) | |
2421 | { | |
2422 | struct net_device *dev; | |
c1d96156 | 2423 | int i, err; |
7dd6a2aa GU |
2424 | |
2425 | printk("FEC ENET Version 0.2\n"); | |
1da177e4 LT |
2426 | |
2427 | for (i = 0; (i < FEC_MAX_PORTS); i++) { | |
2428 | dev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
2429 | if (!dev) | |
2430 | return -ENOMEM; | |
2431 | err = fec_enet_init(dev); | |
2432 | if (err) { | |
2433 | free_netdev(dev); | |
2434 | continue; | |
2435 | } | |
2436 | if (register_netdev(dev) != 0) { | |
2437 | /* XXX: missing cleanup here */ | |
2438 | free_netdev(dev); | |
2439 | return -EIO; | |
2440 | } | |
7dd6a2aa | 2441 | |
e174961c | 2442 | printk("%s: ethernet %pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
2443 | } |
2444 | return 0; | |
2445 | } | |
2446 | ||
2447 | module_init(fec_enet_module_init); | |
2448 | ||
2449 | MODULE_LICENSE("GPL"); |