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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
6f501b17 SH |
39 | #include <linux/io.h> |
40 | #include <linux/irq.h> | |
196719ec | 41 | #include <linux/clk.h> |
ead73183 | 42 | #include <linux/platform_device.h> |
1da177e4 | 43 | |
080853af | 44 | #include <asm/cacheflush.h> |
196719ec SH |
45 | |
46 | #ifndef CONFIG_ARCH_MXC | |
1da177e4 LT |
47 | #include <asm/coldfire.h> |
48 | #include <asm/mcfsim.h> | |
196719ec | 49 | #endif |
6f501b17 | 50 | |
1da177e4 | 51 | #include "fec.h" |
1da177e4 | 52 | |
196719ec SH |
53 | #ifdef CONFIG_ARCH_MXC |
54 | #include <mach/hardware.h> | |
55 | #define FEC_ALIGNMENT 0xf | |
56 | #else | |
57 | #define FEC_ALIGNMENT 0x3 | |
58 | #endif | |
59 | ||
ead73183 SH |
60 | /* |
61 | * Define the fixed address of the FEC hardware. | |
62 | */ | |
87f4abb4 | 63 | #if defined(CONFIG_M5272) |
c1d96156 | 64 | #define HAVE_mii_link_interrupt |
1da177e4 LT |
65 | |
66 | static unsigned char fec_mac_default[] = { | |
67 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
68 | }; | |
69 | ||
70 | /* | |
71 | * Some hardware gets it MAC address out of local flash memory. | |
72 | * if this is non-zero then assume it is the address to get MAC from. | |
73 | */ | |
74 | #if defined(CONFIG_NETtel) | |
75 | #define FEC_FLASHMAC 0xf0006006 | |
76 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
77 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
78 | #elif defined(CONFIG_CANCam) |
79 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
80 | #elif defined (CONFIG_M5272C3) |
81 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
82 | #elif defined(CONFIG_MOD5272) | |
83 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
84 | #else |
85 | #define FEC_FLASHMAC 0 | |
86 | #endif | |
43be6366 | 87 | #endif /* CONFIG_M5272 */ |
ead73183 | 88 | |
22f6b860 | 89 | /* Forward declarations of some structures to support different PHYs */ |
1da177e4 LT |
90 | |
91 | typedef struct { | |
92 | uint mii_data; | |
93 | void (*funct)(uint mii_reg, struct net_device *dev); | |
94 | } phy_cmd_t; | |
95 | ||
96 | typedef struct { | |
97 | uint id; | |
98 | char *name; | |
99 | ||
100 | const phy_cmd_t *config; | |
101 | const phy_cmd_t *startup; | |
102 | const phy_cmd_t *ack_int; | |
103 | const phy_cmd_t *shutdown; | |
104 | } phy_info_t; | |
105 | ||
106 | /* The number of Tx and Rx buffers. These are allocated from the page | |
107 | * pool. The code may assume these are power of two, so it it best | |
108 | * to keep them that size. | |
109 | * We don't need to allocate pages for the transmitter. We just use | |
110 | * the skbuffer directly. | |
111 | */ | |
112 | #define FEC_ENET_RX_PAGES 8 | |
113 | #define FEC_ENET_RX_FRSIZE 2048 | |
114 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
115 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
116 | #define FEC_ENET_TX_FRSIZE 2048 | |
117 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
118 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
119 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
120 | ||
562d2f8c | 121 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 122 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
123 | #endif |
124 | ||
22f6b860 | 125 | /* Interrupt events/masks. */ |
1da177e4 LT |
126 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
127 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
128 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
129 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
130 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
131 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
132 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
133 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
134 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
135 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
136 | ||
137 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
138 | */ | |
139 | #define PKT_MAXBUF_SIZE 1518 | |
140 | #define PKT_MINBUF_SIZE 64 | |
141 | #define PKT_MAXBLR_SIZE 1520 | |
142 | ||
143 | ||
144 | /* | |
6b265293 | 145 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
146 | * size bits. Other FEC hardware does not, so we need to take that into |
147 | * account when setting it. | |
148 | */ | |
562d2f8c | 149 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
196719ec | 150 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
1da177e4 LT |
151 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
152 | #else | |
153 | #define OPT_FRAME_SIZE 0 | |
154 | #endif | |
155 | ||
156 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
157 | * tx_bd_base always point to the base of the buffer descriptors. The | |
158 | * cur_rx and cur_tx point to the currently available buffer. | |
159 | * The dirty_tx tracks the current buffer that is being sent by the | |
160 | * controller. The cur_tx and dirty_tx are equal under both completely | |
161 | * empty and completely full conditions. The empty/ready indicator in | |
162 | * the buffer descriptor determines the actual condition. | |
163 | */ | |
164 | struct fec_enet_private { | |
165 | /* Hardware registers of the FEC device */ | |
f44d6305 | 166 | void __iomem *hwp; |
1da177e4 | 167 | |
cb84d6e7 GU |
168 | struct net_device *netdev; |
169 | ||
ead73183 SH |
170 | struct clk *clk; |
171 | ||
1da177e4 LT |
172 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
173 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
174 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
175 | ushort skb_cur; | |
176 | ushort skb_dirty; | |
177 | ||
22f6b860 | 178 | /* CPM dual port RAM relative addresses */ |
4661e75b | 179 | dma_addr_t bd_dma; |
22f6b860 | 180 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
181 | struct bufdesc *rx_bd_base; |
182 | struct bufdesc *tx_bd_base; | |
183 | /* The next free ring entry */ | |
184 | struct bufdesc *cur_rx, *cur_tx; | |
22f6b860 | 185 | /* The ring entries to be free()ed */ |
2e28532f SH |
186 | struct bufdesc *dirty_tx; |
187 | ||
1da177e4 | 188 | uint tx_full; |
3b2b74ca SS |
189 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
190 | spinlock_t hw_lock; | |
191 | /* hold while accessing the mii_list_t() elements */ | |
192 | spinlock_t mii_lock; | |
1da177e4 LT |
193 | |
194 | uint phy_id; | |
195 | uint phy_id_done; | |
196 | uint phy_status; | |
197 | uint phy_speed; | |
7dd6a2aa | 198 | phy_info_t const *phy; |
1da177e4 LT |
199 | struct work_struct phy_task; |
200 | ||
201 | uint sequence_done; | |
202 | uint mii_phy_task_queued; | |
203 | ||
204 | uint phy_addr; | |
205 | ||
206 | int index; | |
207 | int opened; | |
208 | int link; | |
209 | int old_link; | |
210 | int full_duplex; | |
1da177e4 LT |
211 | }; |
212 | ||
213 | static int fec_enet_open(struct net_device *dev); | |
214 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
215 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 216 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
217 | static void fec_enet_tx(struct net_device *dev); |
218 | static void fec_enet_rx(struct net_device *dev); | |
219 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
220 | static void set_multicast_list(struct net_device *dev); |
221 | static void fec_restart(struct net_device *dev, int duplex); | |
222 | static void fec_stop(struct net_device *dev); | |
223 | static void fec_set_mac_address(struct net_device *dev); | |
224 | ||
225 | ||
226 | /* MII processing. We keep this as simple as possible. Requests are | |
227 | * placed on the list (if there is room). When the request is finished | |
228 | * by the MII, an optional function may be called. | |
229 | */ | |
230 | typedef struct mii_list { | |
231 | uint mii_regval; | |
232 | void (*mii_func)(uint val, struct net_device *dev); | |
233 | struct mii_list *mii_next; | |
234 | } mii_list_t; | |
235 | ||
236 | #define NMII 20 | |
7dd6a2aa GU |
237 | static mii_list_t mii_cmds[NMII]; |
238 | static mii_list_t *mii_free; | |
239 | static mii_list_t *mii_head; | |
240 | static mii_list_t *mii_tail; | |
1da177e4 | 241 | |
6aa20a22 | 242 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
243 | void (*func)(uint, struct net_device *)); |
244 | ||
22f6b860 | 245 | /* Make MII read/write commands for the FEC */ |
1da177e4 LT |
246 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) |
247 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
248 | (VAL & 0xffff)) | |
249 | #define mk_mii_end 0 | |
250 | ||
22f6b860 SH |
251 | /* Transmitter timeout */ |
252 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 253 | |
22f6b860 | 254 | /* Register definitions for the PHY */ |
1da177e4 LT |
255 | |
256 | #define MII_REG_CR 0 /* Control Register */ | |
257 | #define MII_REG_SR 1 /* Status Register */ | |
258 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
259 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 260 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
261 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
262 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
263 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
264 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
265 | ||
266 | /* values for phy_status */ | |
267 | ||
268 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
269 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
270 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
271 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 272 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 273 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 274 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
275 | |
276 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
277 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
278 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
279 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
280 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 281 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 282 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 283 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
284 | |
285 | ||
286 | static int | |
287 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
288 | { | |
f44d6305 | 289 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 290 | struct bufdesc *bdp; |
0e702ab3 | 291 | unsigned short status; |
3b2b74ca | 292 | unsigned long flags; |
1da177e4 | 293 | |
1da177e4 LT |
294 | if (!fep->link) { |
295 | /* Link is down or autonegotiation is in progress. */ | |
296 | return 1; | |
297 | } | |
298 | ||
3b2b74ca | 299 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
300 | /* Fill in a Tx ring entry */ |
301 | bdp = fep->cur_tx; | |
302 | ||
0e702ab3 | 303 | status = bdp->cbd_sc; |
22f6b860 | 304 | |
0e702ab3 | 305 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
306 | /* Ooops. All transmit buffers are full. Bail out. |
307 | * This should not happen, since dev->tbusy should be set. | |
308 | */ | |
309 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 310 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
311 | return 1; |
312 | } | |
1da177e4 | 313 | |
22f6b860 | 314 | /* Clear all of the status flags */ |
0e702ab3 | 315 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 316 | |
22f6b860 | 317 | /* Set buffer length and buffer pointer */ |
1da177e4 LT |
318 | bdp->cbd_bufaddr = __pa(skb->data); |
319 | bdp->cbd_datlen = skb->len; | |
320 | ||
321 | /* | |
22f6b860 SH |
322 | * On some FEC implementations data must be aligned on |
323 | * 4-byte boundaries. Use bounce buffers to copy data | |
324 | * and get it aligned. Ugh. | |
1da177e4 | 325 | */ |
196719ec | 326 | if (bdp->cbd_bufaddr & FEC_ALIGNMENT) { |
1da177e4 LT |
327 | unsigned int index; |
328 | index = bdp - fep->tx_bd_base; | |
6989f512 | 329 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
1da177e4 LT |
330 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); |
331 | } | |
332 | ||
22f6b860 | 333 | /* Save skb pointer */ |
1da177e4 LT |
334 | fep->tx_skbuff[fep->skb_cur] = skb; |
335 | ||
09f75cd7 | 336 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 337 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 338 | |
1da177e4 LT |
339 | /* Push the data cache so the CPM does not get stale memory |
340 | * data. | |
341 | */ | |
ccdc4f19 SH |
342 | dma_sync_single(NULL, bdp->cbd_bufaddr, |
343 | bdp->cbd_datlen, DMA_TO_DEVICE); | |
1da177e4 | 344 | |
0e702ab3 GU |
345 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
346 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 347 | */ |
0e702ab3 | 348 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 349 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 350 | bdp->cbd_sc = status; |
1da177e4 LT |
351 | |
352 | dev->trans_start = jiffies; | |
353 | ||
354 | /* Trigger transmission start */ | |
f44d6305 | 355 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 356 | |
22f6b860 SH |
357 | /* If this was the last BD in the ring, start at the beginning again. */ |
358 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 359 | bdp = fep->tx_bd_base; |
22f6b860 | 360 | else |
1da177e4 | 361 | bdp++; |
1da177e4 LT |
362 | |
363 | if (bdp == fep->dirty_tx) { | |
364 | fep->tx_full = 1; | |
365 | netif_stop_queue(dev); | |
366 | } | |
367 | ||
2e28532f | 368 | fep->cur_tx = bdp; |
1da177e4 | 369 | |
3b2b74ca | 370 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static void | |
376 | fec_timeout(struct net_device *dev) | |
377 | { | |
378 | struct fec_enet_private *fep = netdev_priv(dev); | |
379 | ||
380 | printk("%s: transmit timed out.\n", dev->name); | |
09f75cd7 | 381 | dev->stats.tx_errors++; |
1da177e4 LT |
382 | #ifndef final_version |
383 | { | |
384 | int i; | |
2e28532f | 385 | struct bufdesc *bdp; |
1da177e4 LT |
386 | |
387 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
388 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
389 | (unsigned long)fep->dirty_tx, | |
390 | (unsigned long)fep->cur_rx); | |
391 | ||
392 | bdp = fep->tx_bd_base; | |
393 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
394 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 395 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
396 | (uint) bdp, |
397 | bdp->cbd_sc, | |
398 | bdp->cbd_datlen, | |
399 | (int) bdp->cbd_bufaddr); | |
400 | bdp++; | |
401 | } | |
402 | ||
403 | bdp = fep->rx_bd_base; | |
404 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
405 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
406 | printk(" %08x: %04x %04x %08x\n", | |
407 | (uint) bdp, | |
408 | bdp->cbd_sc, | |
409 | bdp->cbd_datlen, | |
410 | (int) bdp->cbd_bufaddr); | |
411 | bdp++; | |
412 | } | |
413 | } | |
414 | #endif | |
7dd6a2aa | 415 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
416 | netif_wake_queue(dev); |
417 | } | |
418 | ||
1da177e4 | 419 | static irqreturn_t |
7d12e780 | 420 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
421 | { |
422 | struct net_device *dev = dev_id; | |
f44d6305 | 423 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 424 | uint int_events; |
3b2b74ca | 425 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 426 | |
3b2b74ca | 427 | do { |
f44d6305 SH |
428 | int_events = readl(fep->hwp + FEC_IEVENT); |
429 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1da177e4 | 430 | |
1da177e4 | 431 | if (int_events & FEC_ENET_RXF) { |
3b2b74ca | 432 | ret = IRQ_HANDLED; |
1da177e4 LT |
433 | fec_enet_rx(dev); |
434 | } | |
435 | ||
436 | /* Transmit OK, or non-fatal error. Update the buffer | |
f44d6305 SH |
437 | * descriptors. FEC handles all errors, we just discover |
438 | * them as part of the transmit process. | |
439 | */ | |
1da177e4 | 440 | if (int_events & FEC_ENET_TXF) { |
3b2b74ca | 441 | ret = IRQ_HANDLED; |
1da177e4 LT |
442 | fec_enet_tx(dev); |
443 | } | |
444 | ||
445 | if (int_events & FEC_ENET_MII) { | |
3b2b74ca | 446 | ret = IRQ_HANDLED; |
1da177e4 LT |
447 | fec_enet_mii(dev); |
448 | } | |
6aa20a22 | 449 | |
3b2b74ca SS |
450 | } while (int_events); |
451 | ||
452 | return ret; | |
1da177e4 LT |
453 | } |
454 | ||
455 | ||
456 | static void | |
457 | fec_enet_tx(struct net_device *dev) | |
458 | { | |
459 | struct fec_enet_private *fep; | |
2e28532f | 460 | struct bufdesc *bdp; |
0e702ab3 | 461 | unsigned short status; |
1da177e4 LT |
462 | struct sk_buff *skb; |
463 | ||
464 | fep = netdev_priv(dev); | |
3b2b74ca | 465 | spin_lock_irq(&fep->hw_lock); |
1da177e4 LT |
466 | bdp = fep->dirty_tx; |
467 | ||
0e702ab3 | 468 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
469 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
470 | ||
471 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
472 | /* Check for errors. */ | |
0e702ab3 | 473 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
474 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
475 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 476 | dev->stats.tx_errors++; |
0e702ab3 | 477 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 478 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 479 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 480 | dev->stats.tx_window_errors++; |
0e702ab3 | 481 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 482 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 483 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 484 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 485 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 486 | dev->stats.tx_carrier_errors++; |
1da177e4 | 487 | } else { |
09f75cd7 | 488 | dev->stats.tx_packets++; |
1da177e4 LT |
489 | } |
490 | ||
0e702ab3 | 491 | if (status & BD_ENET_TX_READY) |
1da177e4 | 492 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 493 | |
1da177e4 LT |
494 | /* Deferred means some collisions occurred during transmit, |
495 | * but we eventually sent the packet OK. | |
496 | */ | |
0e702ab3 | 497 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 498 | dev->stats.collisions++; |
6aa20a22 | 499 | |
22f6b860 | 500 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
501 | dev_kfree_skb_any(skb); |
502 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
503 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 504 | |
22f6b860 | 505 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 506 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
507 | bdp = fep->tx_bd_base; |
508 | else | |
509 | bdp++; | |
6aa20a22 | 510 | |
22f6b860 | 511 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
512 | */ |
513 | if (fep->tx_full) { | |
514 | fep->tx_full = 0; | |
515 | if (netif_queue_stopped(dev)) | |
516 | netif_wake_queue(dev); | |
517 | } | |
518 | } | |
2e28532f | 519 | fep->dirty_tx = bdp; |
3b2b74ca | 520 | spin_unlock_irq(&fep->hw_lock); |
1da177e4 LT |
521 | } |
522 | ||
523 | ||
524 | /* During a receive, the cur_rx points to the current incoming buffer. | |
525 | * When we update through the ring, if the next incoming buffer has | |
526 | * not been given to the system, we just set the empty indicator, | |
527 | * effectively tossing the packet. | |
528 | */ | |
529 | static void | |
530 | fec_enet_rx(struct net_device *dev) | |
531 | { | |
f44d6305 | 532 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 533 | struct bufdesc *bdp; |
0e702ab3 | 534 | unsigned short status; |
1da177e4 LT |
535 | struct sk_buff *skb; |
536 | ushort pkt_len; | |
537 | __u8 *data; | |
6aa20a22 | 538 | |
0e702ab3 GU |
539 | #ifdef CONFIG_M532x |
540 | flush_cache_all(); | |
6aa20a22 | 541 | #endif |
1da177e4 | 542 | |
3b2b74ca SS |
543 | spin_lock_irq(&fep->hw_lock); |
544 | ||
1da177e4 LT |
545 | /* First, grab all of the stats for the incoming packet. |
546 | * These get messed up if we get called due to a busy condition. | |
547 | */ | |
548 | bdp = fep->cur_rx; | |
549 | ||
22f6b860 | 550 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 551 | |
22f6b860 SH |
552 | /* Since we have allocated space to hold a complete frame, |
553 | * the last indicator should be set. | |
554 | */ | |
555 | if ((status & BD_ENET_RX_LAST) == 0) | |
556 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 557 | |
22f6b860 SH |
558 | if (!fep->opened) |
559 | goto rx_processing_done; | |
1da177e4 | 560 | |
22f6b860 SH |
561 | /* Check for errors. */ |
562 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 563 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
22f6b860 SH |
564 | dev->stats.rx_errors++; |
565 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { | |
566 | /* Frame too long or too short. */ | |
567 | dev->stats.rx_length_errors++; | |
568 | } | |
569 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
570 | dev->stats.rx_frame_errors++; | |
571 | if (status & BD_ENET_RX_CR) /* CRC Error */ | |
572 | dev->stats.rx_crc_errors++; | |
573 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ | |
574 | dev->stats.rx_fifo_errors++; | |
1da177e4 | 575 | } |
1da177e4 | 576 | |
22f6b860 SH |
577 | /* Report late collisions as a frame error. |
578 | * On this error, the BD is closed, but we don't know what we | |
579 | * have in the buffer. So, just drop this frame on the floor. | |
580 | */ | |
581 | if (status & BD_ENET_RX_CL) { | |
582 | dev->stats.rx_errors++; | |
583 | dev->stats.rx_frame_errors++; | |
584 | goto rx_processing_done; | |
585 | } | |
1da177e4 | 586 | |
22f6b860 SH |
587 | /* Process the incoming frame. */ |
588 | dev->stats.rx_packets++; | |
589 | pkt_len = bdp->cbd_datlen; | |
590 | dev->stats.rx_bytes += pkt_len; | |
591 | data = (__u8*)__va(bdp->cbd_bufaddr); | |
1da177e4 | 592 | |
22f6b860 | 593 | dma_sync_single(NULL, (unsigned long)__pa(data), |
ccdc4f19 SH |
594 | pkt_len - 4, DMA_FROM_DEVICE); |
595 | ||
22f6b860 SH |
596 | /* This does 16 byte alignment, exactly what we need. |
597 | * The packet length includes FCS, but we don't want to | |
598 | * include that when passing upstream as it messes up | |
599 | * bridging applications. | |
600 | */ | |
601 | skb = dev_alloc_skb(pkt_len - 4); | |
1da177e4 | 602 | |
22f6b860 SH |
603 | if (skb == NULL) { |
604 | printk("%s: Memory squeeze, dropping packet.\n", | |
605 | dev->name); | |
606 | dev->stats.rx_dropped++; | |
607 | } else { | |
608 | skb_put(skb, pkt_len - 4); /* Make room */ | |
609 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
610 | skb->protocol = eth_type_trans(skb, dev); | |
611 | netif_rx(skb); | |
612 | } | |
613 | rx_processing_done: | |
614 | /* Clear the status flags for this buffer */ | |
615 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 616 | |
22f6b860 SH |
617 | /* Mark the buffer empty */ |
618 | status |= BD_ENET_RX_EMPTY; | |
619 | bdp->cbd_sc = status; | |
6aa20a22 | 620 | |
22f6b860 SH |
621 | /* Update BD pointer to next entry */ |
622 | if (status & BD_ENET_RX_WRAP) | |
623 | bdp = fep->rx_bd_base; | |
624 | else | |
625 | bdp++; | |
626 | /* Doing this here will keep the FEC running while we process | |
627 | * incoming frames. On a heavily loaded network, we should be | |
628 | * able to keep up at the expense of system resources. | |
629 | */ | |
630 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
631 | } | |
2e28532f | 632 | fep->cur_rx = bdp; |
1da177e4 | 633 | |
3b2b74ca | 634 | spin_unlock_irq(&fep->hw_lock); |
1da177e4 LT |
635 | } |
636 | ||
0e702ab3 | 637 | /* called from interrupt context */ |
1da177e4 LT |
638 | static void |
639 | fec_enet_mii(struct net_device *dev) | |
640 | { | |
641 | struct fec_enet_private *fep; | |
1da177e4 | 642 | mii_list_t *mip; |
1da177e4 LT |
643 | |
644 | fep = netdev_priv(dev); | |
3b2b74ca SS |
645 | spin_lock_irq(&fep->mii_lock); |
646 | ||
1da177e4 LT |
647 | if ((mip = mii_head) == NULL) { |
648 | printk("MII and no head!\n"); | |
0e702ab3 | 649 | goto unlock; |
1da177e4 LT |
650 | } |
651 | ||
652 | if (mip->mii_func != NULL) | |
f44d6305 | 653 | (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev); |
1da177e4 LT |
654 | |
655 | mii_head = mip->mii_next; | |
656 | mip->mii_next = mii_free; | |
657 | mii_free = mip; | |
658 | ||
659 | if ((mip = mii_head) != NULL) | |
f44d6305 | 660 | writel(mip->mii_regval, fep->hwp + FEC_MII_DATA); |
0e702ab3 GU |
661 | |
662 | unlock: | |
3b2b74ca | 663 | spin_unlock_irq(&fep->mii_lock); |
1da177e4 LT |
664 | } |
665 | ||
666 | static int | |
667 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
668 | { | |
669 | struct fec_enet_private *fep; | |
670 | unsigned long flags; | |
671 | mii_list_t *mip; | |
672 | int retval; | |
673 | ||
22f6b860 | 674 | /* Add PHY address to register command */ |
1da177e4 | 675 | fep = netdev_priv(dev); |
3b2b74ca | 676 | spin_lock_irqsave(&fep->mii_lock, flags); |
1da177e4 | 677 | |
3b2b74ca | 678 | regval |= fep->phy_addr << 23; |
1da177e4 LT |
679 | retval = 0; |
680 | ||
1da177e4 LT |
681 | if ((mip = mii_free) != NULL) { |
682 | mii_free = mip->mii_next; | |
683 | mip->mii_regval = regval; | |
684 | mip->mii_func = func; | |
685 | mip->mii_next = NULL; | |
686 | if (mii_head) { | |
687 | mii_tail->mii_next = mip; | |
688 | mii_tail = mip; | |
f909b1ef | 689 | } else { |
1da177e4 | 690 | mii_head = mii_tail = mip; |
f44d6305 | 691 | writel(regval, fep->hwp + FEC_MII_DATA); |
1da177e4 | 692 | } |
f909b1ef | 693 | } else { |
1da177e4 LT |
694 | retval = 1; |
695 | } | |
696 | ||
3b2b74ca SS |
697 | spin_unlock_irqrestore(&fep->mii_lock, flags); |
698 | return retval; | |
1da177e4 LT |
699 | } |
700 | ||
701 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
702 | { | |
1da177e4 LT |
703 | if(!c) |
704 | return; | |
705 | ||
be6cb66d PDM |
706 | for (; c->mii_data != mk_mii_end; c++) |
707 | mii_queue(dev, c->mii_data, c->funct); | |
1da177e4 LT |
708 | } |
709 | ||
710 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
711 | { | |
712 | struct fec_enet_private *fep = netdev_priv(dev); | |
713 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 714 | uint status; |
1da177e4 | 715 | |
7dd6a2aa | 716 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
717 | |
718 | if (mii_reg & 0x0004) | |
7dd6a2aa | 719 | status |= PHY_STAT_LINK; |
1da177e4 | 720 | if (mii_reg & 0x0010) |
7dd6a2aa | 721 | status |= PHY_STAT_FAULT; |
1da177e4 | 722 | if (mii_reg & 0x0020) |
7dd6a2aa | 723 | status |= PHY_STAT_ANC; |
7dd6a2aa | 724 | *s = status; |
1da177e4 LT |
725 | } |
726 | ||
727 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
728 | { | |
729 | struct fec_enet_private *fep = netdev_priv(dev); | |
730 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 731 | uint status; |
1da177e4 | 732 | |
7dd6a2aa | 733 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
734 | |
735 | if (mii_reg & 0x1000) | |
7dd6a2aa | 736 | status |= PHY_CONF_ANE; |
1da177e4 | 737 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
738 | status |= PHY_CONF_LOOP; |
739 | *s = status; | |
1da177e4 LT |
740 | } |
741 | ||
742 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
743 | { | |
744 | struct fec_enet_private *fep = netdev_priv(dev); | |
745 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 746 | uint status; |
1da177e4 | 747 | |
7dd6a2aa | 748 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
749 | |
750 | if (mii_reg & 0x0020) | |
7dd6a2aa | 751 | status |= PHY_CONF_10HDX; |
1da177e4 | 752 | if (mii_reg & 0x0040) |
7dd6a2aa | 753 | status |= PHY_CONF_10FDX; |
1da177e4 | 754 | if (mii_reg & 0x0080) |
7dd6a2aa | 755 | status |= PHY_CONF_100HDX; |
1da177e4 | 756 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
757 | status |= PHY_CONF_100FDX; |
758 | *s = status; | |
1da177e4 LT |
759 | } |
760 | ||
761 | /* ------------------------------------------------------------------------- */ | |
762 | /* The Level one LXT970 is used by many boards */ | |
763 | ||
764 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
765 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
766 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
767 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
768 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
769 | ||
770 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
771 | { | |
772 | struct fec_enet_private *fep = netdev_priv(dev); | |
773 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 774 | uint status; |
1da177e4 | 775 | |
7dd6a2aa | 776 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
777 | if (mii_reg & 0x0800) { |
778 | if (mii_reg & 0x1000) | |
7dd6a2aa | 779 | status |= PHY_STAT_100FDX; |
1da177e4 | 780 | else |
7dd6a2aa | 781 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
782 | } else { |
783 | if (mii_reg & 0x1000) | |
7dd6a2aa | 784 | status |= PHY_STAT_10FDX; |
1da177e4 | 785 | else |
7dd6a2aa | 786 | status |= PHY_STAT_10HDX; |
1da177e4 | 787 | } |
7dd6a2aa | 788 | *s = status; |
1da177e4 LT |
789 | } |
790 | ||
7dd6a2aa | 791 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
792 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
793 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
794 | { mk_mii_end, } | |
7dd6a2aa GU |
795 | }; |
796 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
797 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
798 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
799 | { mk_mii_end, } | |
7dd6a2aa GU |
800 | }; |
801 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
802 | /* read SR and ISR to acknowledge */ |
803 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
804 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
805 | ||
806 | /* find out the current status */ | |
807 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
808 | { mk_mii_end, } | |
7dd6a2aa GU |
809 | }; |
810 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
811 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
812 | { mk_mii_end, } | |
7dd6a2aa GU |
813 | }; |
814 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 815 | .id = 0x07810000, |
7dd6a2aa GU |
816 | .name = "LXT970", |
817 | .config = phy_cmd_lxt970_config, | |
818 | .startup = phy_cmd_lxt970_startup, | |
819 | .ack_int = phy_cmd_lxt970_ack_int, | |
820 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 821 | }; |
6aa20a22 | 822 | |
1da177e4 LT |
823 | /* ------------------------------------------------------------------------- */ |
824 | /* The Level one LXT971 is used on some of my custom boards */ | |
825 | ||
826 | /* register definitions for the 971 */ | |
827 | ||
828 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
829 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
830 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
831 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
832 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
833 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
834 | ||
6aa20a22 | 835 | /* |
1da177e4 LT |
836 | * I had some nice ideas of running the MDIO faster... |
837 | * The 971 should support 8MHz and I tried it, but things acted really | |
838 | * weird, so 2.5 MHz ought to be enough for anyone... | |
839 | */ | |
840 | ||
841 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
842 | { | |
843 | struct fec_enet_private *fep = netdev_priv(dev); | |
844 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 845 | uint status; |
1da177e4 | 846 | |
7dd6a2aa | 847 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
848 | |
849 | if (mii_reg & 0x0400) { | |
850 | fep->link = 1; | |
7dd6a2aa | 851 | status |= PHY_STAT_LINK; |
1da177e4 LT |
852 | } else { |
853 | fep->link = 0; | |
854 | } | |
855 | if (mii_reg & 0x0080) | |
7dd6a2aa | 856 | status |= PHY_STAT_ANC; |
1da177e4 LT |
857 | if (mii_reg & 0x4000) { |
858 | if (mii_reg & 0x0200) | |
7dd6a2aa | 859 | status |= PHY_STAT_100FDX; |
1da177e4 | 860 | else |
7dd6a2aa | 861 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
862 | } else { |
863 | if (mii_reg & 0x0200) | |
7dd6a2aa | 864 | status |= PHY_STAT_10FDX; |
1da177e4 | 865 | else |
7dd6a2aa | 866 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
867 | } |
868 | if (mii_reg & 0x0008) | |
7dd6a2aa | 869 | status |= PHY_STAT_FAULT; |
1da177e4 | 870 | |
7dd6a2aa GU |
871 | *s = status; |
872 | } | |
6aa20a22 | 873 | |
7dd6a2aa | 874 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 875 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
876 | * doesn't work with 100. */ |
877 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
878 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
879 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
880 | { mk_mii_end, } | |
7dd6a2aa GU |
881 | }; |
882 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
883 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
884 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
885 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
886 | /* Somehow does the 971 tell me that the link is down | |
887 | * the first read after power-up. | |
888 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 889 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 890 | { mk_mii_end, } |
7dd6a2aa GU |
891 | }; |
892 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
893 | /* acknowledge the int before reading status ! */ | |
894 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
895 | /* find out the current status */ |
896 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
897 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 898 | { mk_mii_end, } |
7dd6a2aa GU |
899 | }; |
900 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
901 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
902 | { mk_mii_end, } | |
7dd6a2aa GU |
903 | }; |
904 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 905 | .id = 0x0001378e, |
7dd6a2aa GU |
906 | .name = "LXT971", |
907 | .config = phy_cmd_lxt971_config, | |
908 | .startup = phy_cmd_lxt971_startup, | |
909 | .ack_int = phy_cmd_lxt971_ack_int, | |
910 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
911 | }; |
912 | ||
913 | /* ------------------------------------------------------------------------- */ | |
914 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
915 | ||
916 | /* register definitions */ | |
917 | ||
918 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
919 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
920 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
921 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
922 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
923 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
924 | ||
925 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
926 | { | |
927 | struct fec_enet_private *fep = netdev_priv(dev); | |
928 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 929 | uint status; |
1da177e4 | 930 | |
7dd6a2aa | 931 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
932 | |
933 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
934 | case 1: status |= PHY_STAT_10HDX; break; |
935 | case 2: status |= PHY_STAT_100HDX; break; | |
936 | case 5: status |= PHY_STAT_10FDX; break; | |
937 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
938 | } |
939 | ||
7dd6a2aa GU |
940 | *s = status; |
941 | } | |
942 | ||
943 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 944 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
945 | * so send a command to allow operation. |
946 | */ | |
947 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
948 | ||
949 | /* parse cr and anar to get some info */ | |
950 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
951 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
952 | { mk_mii_end, } | |
7dd6a2aa GU |
953 | }; |
954 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
955 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
956 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
957 | { mk_mii_end, } | |
7dd6a2aa GU |
958 | }; |
959 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
960 | /* we need to read ISR, SR and ANER to acknowledge */ |
961 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
962 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
963 | { mk_mii_read(MII_REG_ANER), NULL }, | |
964 | ||
965 | /* read pcr to get info */ | |
966 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
967 | { mk_mii_end, } | |
7dd6a2aa GU |
968 | }; |
969 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
970 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
971 | { mk_mii_end, } | |
7dd6a2aa GU |
972 | }; |
973 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 974 | .id = 0x00181440, |
7dd6a2aa GU |
975 | .name = "QS6612", |
976 | .config = phy_cmd_qs6612_config, | |
977 | .startup = phy_cmd_qs6612_startup, | |
978 | .ack_int = phy_cmd_qs6612_ack_int, | |
979 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
980 | }; |
981 | ||
982 | /* ------------------------------------------------------------------------- */ | |
983 | /* AMD AM79C874 phy */ | |
984 | ||
985 | /* register definitions for the 874 */ | |
986 | ||
987 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
988 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
989 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
990 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
991 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
992 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
993 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
994 | ||
995 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
996 | { | |
997 | struct fec_enet_private *fep = netdev_priv(dev); | |
998 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 999 | uint status; |
1da177e4 | 1000 | |
7dd6a2aa | 1001 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1002 | |
1003 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1004 | status |= PHY_STAT_ANC; |
1da177e4 | 1005 | if (mii_reg & 0x0400) |
7dd6a2aa | 1006 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1007 | else |
7dd6a2aa GU |
1008 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1009 | ||
1010 | *s = status; | |
1da177e4 LT |
1011 | } |
1012 | ||
7dd6a2aa | 1013 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1014 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1015 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1016 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1017 | { mk_mii_end, } | |
7dd6a2aa GU |
1018 | }; |
1019 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1020 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1021 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1022 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1023 | { mk_mii_end, } |
7dd6a2aa GU |
1024 | }; |
1025 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1026 | /* find out the current status */ |
1027 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1028 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1029 | /* we only need to read ISR to acknowledge */ | |
1030 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1031 | { mk_mii_end, } | |
7dd6a2aa GU |
1032 | }; |
1033 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1034 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1035 | { mk_mii_end, } | |
7dd6a2aa GU |
1036 | }; |
1037 | static phy_info_t const phy_info_am79c874 = { | |
1038 | .id = 0x00022561, | |
1039 | .name = "AM79C874", | |
1040 | .config = phy_cmd_am79c874_config, | |
1041 | .startup = phy_cmd_am79c874_startup, | |
1042 | .ack_int = phy_cmd_am79c874_ack_int, | |
1043 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1044 | }; |
1045 | ||
7dd6a2aa | 1046 | |
1da177e4 LT |
1047 | /* ------------------------------------------------------------------------- */ |
1048 | /* Kendin KS8721BL phy */ | |
1049 | ||
1050 | /* register definitions for the 8721 */ | |
1051 | ||
1052 | #define MII_KS8721BL_RXERCR 21 | |
43268dce | 1053 | #define MII_KS8721BL_ICSR 27 |
1da177e4 LT |
1054 | #define MII_KS8721BL_PHYCR 31 |
1055 | ||
7dd6a2aa | 1056 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1057 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1058 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1059 | { mk_mii_end, } | |
7dd6a2aa GU |
1060 | }; |
1061 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1062 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1063 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1064 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1065 | { mk_mii_end, } |
7dd6a2aa GU |
1066 | }; |
1067 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1068 | /* find out the current status */ |
1069 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1070 | /* we only need to read ISR to acknowledge */ | |
1071 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1072 | { mk_mii_end, } | |
7dd6a2aa GU |
1073 | }; |
1074 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1075 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1076 | { mk_mii_end, } | |
7dd6a2aa GU |
1077 | }; |
1078 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1079 | .id = 0x00022161, |
7dd6a2aa GU |
1080 | .name = "KS8721BL", |
1081 | .config = phy_cmd_ks8721bl_config, | |
1082 | .startup = phy_cmd_ks8721bl_startup, | |
1083 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1084 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1085 | }; |
1086 | ||
562d2f8c GU |
1087 | /* ------------------------------------------------------------------------- */ |
1088 | /* register definitions for the DP83848 */ | |
1089 | ||
1090 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1091 | ||
1092 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1093 | { | |
4cf1653a | 1094 | struct fec_enet_private *fep = netdev_priv(dev); |
562d2f8c GU |
1095 | volatile uint *s = &(fep->phy_status); |
1096 | ||
1097 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1098 | ||
1099 | /* Link up */ | |
1100 | if (mii_reg & 0x0001) { | |
1101 | fep->link = 1; | |
1102 | *s |= PHY_STAT_LINK; | |
1103 | } else | |
1104 | fep->link = 0; | |
1105 | /* Status of link */ | |
1106 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1107 | *s |= PHY_STAT_ANC; | |
1108 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1109 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1110 | *s |= PHY_STAT_10FDX; | |
1111 | else | |
1112 | *s |= PHY_STAT_10HDX; | |
1113 | } else { /* 100 Mbps? */ | |
1114 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1115 | *s |= PHY_STAT_100FDX; | |
1116 | else | |
1117 | *s |= PHY_STAT_100HDX; | |
1118 | } | |
1119 | if (mii_reg & 0x0008) | |
1120 | *s |= PHY_STAT_FAULT; | |
1121 | } | |
1122 | ||
1123 | static phy_info_t phy_info_dp83848= { | |
1124 | 0x020005c9, | |
1125 | "DP83848", | |
1126 | ||
1127 | (const phy_cmd_t []) { /* config */ | |
1128 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1129 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1130 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1131 | { mk_mii_end, } | |
1132 | }, | |
1133 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1134 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1135 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1136 | { mk_mii_end, } | |
1137 | }, | |
1138 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1139 | { mk_mii_end, } | |
1140 | }, | |
1141 | (const phy_cmd_t []) { /* shutdown */ | |
1142 | { mk_mii_end, } | |
1143 | }, | |
1144 | }; | |
1145 | ||
1da177e4 LT |
1146 | /* ------------------------------------------------------------------------- */ |
1147 | ||
7dd6a2aa | 1148 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1149 | &phy_info_lxt970, |
1150 | &phy_info_lxt971, | |
1151 | &phy_info_qs6612, | |
1152 | &phy_info_am79c874, | |
1153 | &phy_info_ks8721bl, | |
562d2f8c | 1154 | &phy_info_dp83848, |
1da177e4 LT |
1155 | NULL |
1156 | }; | |
1157 | ||
1158 | /* ------------------------------------------------------------------------- */ | |
c1d96156 | 1159 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1160 | static irqreturn_t |
7d12e780 | 1161 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 | 1162 | |
1da177e4 | 1163 | /* |
43be6366 | 1164 | * This is specific to the MII interrupt setup of the M5272EVB. |
1da177e4 | 1165 | */ |
43be6366 | 1166 | static void __inline__ fec_request_mii_intr(struct net_device *dev) |
1da177e4 | 1167 | { |
43be6366 GU |
1168 | if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0) |
1169 | printk("FEC: Could not allocate fec(MII) IRQ(66)!\n"); | |
1da177e4 LT |
1170 | } |
1171 | ||
1da177e4 LT |
1172 | static void __inline__ fec_disable_phy_intr(void) |
1173 | { | |
1174 | volatile unsigned long *icrp; | |
1175 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1176 | *icrp = 0x08000000; |
1da177e4 LT |
1177 | } |
1178 | ||
1179 | static void __inline__ fec_phy_ack_intr(void) | |
1180 | { | |
1181 | volatile unsigned long *icrp; | |
1182 | /* Acknowledge the interrupt */ | |
1183 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1184 | *icrp = 0x0d000000; |
1da177e4 LT |
1185 | } |
1186 | ||
43be6366 | 1187 | #ifdef CONFIG_M5272 |
562d2f8c GU |
1188 | static void __inline__ fec_get_mac(struct net_device *dev) |
1189 | { | |
1190 | struct fec_enet_private *fep = netdev_priv(dev); | |
562d2f8c GU |
1191 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1192 | ||
562d2f8c GU |
1193 | if (FEC_FLASHMAC) { |
1194 | /* | |
1195 | * Get MAC address from FLASH. | |
1196 | * If it is all 1's or 0's, use the default. | |
1197 | */ | |
43be6366 | 1198 | iap = (unsigned char *)FEC_FLASHMAC; |
6b265293 MW |
1199 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1200 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1201 | iap = fec_mac_default; | |
1202 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1203 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1204 | iap = fec_mac_default; | |
1205 | } else { | |
f44d6305 SH |
1206 | *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); |
1207 | *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
6b265293 MW |
1208 | iap = &tmpaddr[0]; |
1209 | } | |
1210 | ||
1211 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1212 | ||
1213 | /* Adjust MAC if using default MAC address */ | |
1214 | if (iap == fec_mac_default) | |
43be6366 | 1215 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
6b265293 | 1216 | } |
1da177e4 LT |
1217 | #endif |
1218 | ||
1219 | /* ------------------------------------------------------------------------- */ | |
1220 | ||
1221 | static void mii_display_status(struct net_device *dev) | |
1222 | { | |
1223 | struct fec_enet_private *fep = netdev_priv(dev); | |
1224 | volatile uint *s = &(fep->phy_status); | |
1225 | ||
1226 | if (!fep->link && !fep->old_link) { | |
1227 | /* Link is still down - don't print anything */ | |
1228 | return; | |
1229 | } | |
1230 | ||
1231 | printk("%s: status: ", dev->name); | |
1232 | ||
1233 | if (!fep->link) { | |
1234 | printk("link down"); | |
1235 | } else { | |
1236 | printk("link up"); | |
1237 | ||
1238 | switch(*s & PHY_STAT_SPMASK) { | |
1239 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1240 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1241 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1242 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1243 | default: | |
1244 | printk(", Unknown speed/duplex"); | |
1245 | } | |
1246 | ||
1247 | if (*s & PHY_STAT_ANC) | |
1248 | printk(", auto-negotiation complete"); | |
1249 | } | |
1250 | ||
1251 | if (*s & PHY_STAT_FAULT) | |
1252 | printk(", remote fault"); | |
1253 | ||
1254 | printk(".\n"); | |
1255 | } | |
1256 | ||
cb84d6e7 | 1257 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1258 | { |
cb84d6e7 GU |
1259 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1260 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1261 | uint status = fep->phy_status; |
1da177e4 LT |
1262 | |
1263 | /* | |
1264 | ** When we get here, phy_task is already removed from | |
1265 | ** the workqueue. It is thus safe to allow to reuse it. | |
1266 | */ | |
1267 | fep->mii_phy_task_queued = 0; | |
1268 | printk("%s: config: auto-negotiation ", dev->name); | |
1269 | ||
7dd6a2aa | 1270 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1271 | printk("on"); |
1272 | else | |
1273 | printk("off"); | |
1274 | ||
7dd6a2aa | 1275 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1276 | printk(", 100FDX"); |
7dd6a2aa | 1277 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1278 | printk(", 100HDX"); |
7dd6a2aa | 1279 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1280 | printk(", 10FDX"); |
7dd6a2aa | 1281 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1282 | printk(", 10HDX"); |
7dd6a2aa | 1283 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1284 | printk(", No speed/duplex selected?"); |
1285 | ||
7dd6a2aa | 1286 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1287 | printk(", loopback enabled"); |
6aa20a22 | 1288 | |
1da177e4 LT |
1289 | printk(".\n"); |
1290 | ||
1291 | fep->sequence_done = 1; | |
1292 | } | |
1293 | ||
cb84d6e7 | 1294 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1295 | { |
cb84d6e7 GU |
1296 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1297 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1298 | int duplex; |
1299 | ||
1300 | /* | |
1301 | ** When we get here, phy_task is already removed from | |
1302 | ** the workqueue. It is thus safe to allow to reuse it. | |
1303 | */ | |
1304 | fep->mii_phy_task_queued = 0; | |
1305 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1306 | mii_display_status(dev); | |
1307 | fep->old_link = fep->link; | |
1308 | ||
1309 | if (fep->link) { | |
1310 | duplex = 0; | |
6aa20a22 | 1311 | if (fep->phy_status |
1da177e4 LT |
1312 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
1313 | duplex = 1; | |
1314 | fec_restart(dev, duplex); | |
f909b1ef | 1315 | } else |
1da177e4 | 1316 | fec_stop(dev); |
1da177e4 LT |
1317 | } |
1318 | ||
1319 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
1320 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
1321 | { | |
1322 | struct fec_enet_private *fep = netdev_priv(dev); | |
1323 | ||
1324 | /* | |
22f6b860 SH |
1325 | * We cannot queue phy_task twice in the workqueue. It |
1326 | * would cause an endless loop in the workqueue. | |
1327 | * Fortunately, if the last mii_relink entry has not yet been | |
1328 | * executed now, it will do the job for the current interrupt, | |
1329 | * which is just what we want. | |
1330 | */ | |
1da177e4 LT |
1331 | if (fep->mii_phy_task_queued) |
1332 | return; | |
1333 | ||
1334 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1335 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
1336 | schedule_work(&fep->phy_task); |
1337 | } | |
1338 | ||
7dd6a2aa | 1339 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
1340 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
1341 | { | |
1342 | struct fec_enet_private *fep = netdev_priv(dev); | |
1343 | ||
1344 | if (fep->mii_phy_task_queued) | |
1345 | return; | |
1346 | ||
1347 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1348 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
1349 | schedule_work(&fep->phy_task); |
1350 | } | |
1351 | ||
7dd6a2aa GU |
1352 | phy_cmd_t const phy_cmd_relink[] = { |
1353 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
1354 | { mk_mii_end, } | |
1355 | }; | |
1356 | phy_cmd_t const phy_cmd_config[] = { | |
1357 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
1358 | { mk_mii_end, } | |
1359 | }; | |
1da177e4 | 1360 | |
22f6b860 | 1361 | /* Read remainder of PHY ID. */ |
1da177e4 LT |
1362 | static void |
1363 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
1364 | { | |
1365 | struct fec_enet_private *fep; | |
1366 | int i; | |
1367 | ||
1368 | fep = netdev_priv(dev); | |
1369 | fep->phy_id |= (mii_reg & 0xffff); | |
1370 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
1371 | ||
1372 | for(i = 0; phy_info[i]; i++) { | |
1373 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | if (phy_info[i]) | |
1378 | printk(" -- %s\n", phy_info[i]->name); | |
1379 | else | |
1380 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 1381 | |
1da177e4 LT |
1382 | fep->phy = phy_info[i]; |
1383 | fep->phy_id_done = 1; | |
1384 | } | |
1385 | ||
1386 | /* Scan all of the MII PHY addresses looking for someone to respond | |
1387 | * with a valid ID. This usually happens quickly. | |
1388 | */ | |
1389 | static void | |
1390 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
1391 | { | |
1392 | struct fec_enet_private *fep; | |
1da177e4 LT |
1393 | uint phytype; |
1394 | ||
1395 | fep = netdev_priv(dev); | |
1da177e4 LT |
1396 | |
1397 | if (fep->phy_addr < 32) { | |
1398 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 1399 | |
22f6b860 | 1400 | /* Got first part of ID, now get remainder */ |
1da177e4 LT |
1401 | fep->phy_id = phytype << 16; |
1402 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
1403 | mii_discover_phy3); | |
f909b1ef | 1404 | } else { |
1da177e4 LT |
1405 | fep->phy_addr++; |
1406 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
1407 | mii_discover_phy); | |
1408 | } | |
1409 | } else { | |
1410 | printk("FEC: No PHY device found.\n"); | |
1411 | /* Disable external MII interface */ | |
f44d6305 SH |
1412 | writel(0, fep->hwp + FEC_MII_SPEED); |
1413 | fep->phy_speed = 0; | |
43be6366 | 1414 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1415 | fec_disable_phy_intr(); |
ead73183 | 1416 | #endif |
1da177e4 LT |
1417 | } |
1418 | } | |
1419 | ||
22f6b860 | 1420 | /* This interrupt occurs when the PHY detects a link change */ |
c1d96156 | 1421 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1422 | static irqreturn_t |
7d12e780 | 1423 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
1424 | { |
1425 | struct net_device *dev = dev_id; | |
1426 | struct fec_enet_private *fep = netdev_priv(dev); | |
1427 | ||
1428 | fec_phy_ack_intr(); | |
1429 | ||
1da177e4 LT |
1430 | mii_do_cmd(dev, fep->phy->ack_int); |
1431 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
1432 | ||
1433 | return IRQ_HANDLED; | |
1434 | } | |
c1d96156 | 1435 | #endif |
1da177e4 LT |
1436 | |
1437 | static int | |
1438 | fec_enet_open(struct net_device *dev) | |
1439 | { | |
1440 | struct fec_enet_private *fep = netdev_priv(dev); | |
1441 | ||
1442 | /* I should reset the ring buffers here, but I don't yet know | |
1443 | * a simple way to do that. | |
1444 | */ | |
1445 | fec_set_mac_address(dev); | |
1446 | ||
1447 | fep->sequence_done = 0; | |
1448 | fep->link = 0; | |
1449 | ||
1450 | if (fep->phy) { | |
1451 | mii_do_cmd(dev, fep->phy->ack_int); | |
1452 | mii_do_cmd(dev, fep->phy->config); | |
1453 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
1454 | ||
6b265293 MW |
1455 | /* Poll until the PHY tells us its configuration |
1456 | * (not link state). | |
1457 | * Request is initiated by mii_do_cmd above, but answer | |
1458 | * comes by interrupt. | |
1459 | * This should take about 25 usec per register at 2.5 MHz, | |
1460 | * and we read approximately 5 registers. | |
1da177e4 LT |
1461 | */ |
1462 | while(!fep->sequence_done) | |
1463 | schedule(); | |
1464 | ||
1465 | mii_do_cmd(dev, fep->phy->startup); | |
1466 | ||
1467 | /* Set the initial link state to true. A lot of hardware | |
1468 | * based on this device does not implement a PHY interrupt, | |
1469 | * so we are never notified of link change. | |
1470 | */ | |
1471 | fep->link = 1; | |
1472 | } else { | |
1473 | fep->link = 1; /* lets just try it and see */ | |
1474 | /* no phy, go full duplex, it's most likely a hub chip */ | |
1475 | fec_restart(dev, 1); | |
1476 | } | |
1477 | ||
1478 | netif_start_queue(dev); | |
1479 | fep->opened = 1; | |
22f6b860 | 1480 | return 0; |
1da177e4 LT |
1481 | } |
1482 | ||
1483 | static int | |
1484 | fec_enet_close(struct net_device *dev) | |
1485 | { | |
1486 | struct fec_enet_private *fep = netdev_priv(dev); | |
1487 | ||
22f6b860 | 1488 | /* Don't know what to do yet. */ |
1da177e4 LT |
1489 | fep->opened = 0; |
1490 | netif_stop_queue(dev); | |
1491 | fec_stop(dev); | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
1da177e4 LT |
1496 | /* Set or clear the multicast filter for this adaptor. |
1497 | * Skeleton taken from sunlance driver. | |
1498 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1499 | * MAC address filtering. Some of the drivers check to make sure it is | |
1500 | * a group multicast address, and discard those that are not. I guess I | |
1501 | * will do the same for now, but just remove the test if you want | |
1502 | * individual filtering as well (do the upper net layers want or support | |
1503 | * this kind of feature?). | |
1504 | */ | |
1505 | ||
1506 | #define HASH_BITS 6 /* #bits in hash */ | |
1507 | #define CRC32_POLY 0xEDB88320 | |
1508 | ||
1509 | static void set_multicast_list(struct net_device *dev) | |
1510 | { | |
f44d6305 | 1511 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1512 | struct dev_mc_list *dmi; |
f44d6305 | 1513 | unsigned int i, j, bit, data, crc, tmp; |
1da177e4 LT |
1514 | unsigned char hash; |
1515 | ||
22f6b860 | 1516 | if (dev->flags & IFF_PROMISC) { |
f44d6305 SH |
1517 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1518 | tmp |= 0x8; | |
1519 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1520 | return; |
1521 | } | |
1da177e4 | 1522 | |
4e831836 SH |
1523 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1524 | tmp &= ~0x8; | |
1525 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1526 | ||
1527 | if (dev->flags & IFF_ALLMULTI) { | |
1528 | /* Catch all multicast addresses, so set the | |
1529 | * filter to all 1's | |
1530 | */ | |
1531 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1532 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1533 | ||
1534 | return; | |
1535 | } | |
1536 | ||
1537 | /* Clear filter and add the addresses in hash register | |
1538 | */ | |
1539 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1540 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1541 | ||
1542 | dmi = dev->mc_list; | |
1543 | ||
1544 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) { | |
1545 | /* Only support group multicast for now */ | |
1546 | if (!(dmi->dmi_addr[0] & 1)) | |
1547 | continue; | |
1548 | ||
1549 | /* calculate crc32 value of mac address */ | |
1550 | crc = 0xffffffff; | |
1551 | ||
1552 | for (i = 0; i < dmi->dmi_addrlen; i++) { | |
1553 | data = dmi->dmi_addr[i]; | |
1554 | for (bit = 0; bit < 8; bit++, data >>= 1) { | |
1555 | crc = (crc >> 1) ^ | |
1556 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1557 | } |
1558 | } | |
4e831836 SH |
1559 | |
1560 | /* only upper 6 bits (HASH_BITS) are used | |
1561 | * which point to specific bit in he hash registers | |
1562 | */ | |
1563 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1564 | ||
1565 | if (hash > 31) { | |
1566 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1567 | tmp |= 1 << (hash - 32); | |
1568 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1569 | } else { | |
1570 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1571 | tmp |= 1 << hash; | |
1572 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1573 | } | |
1da177e4 LT |
1574 | } |
1575 | } | |
1576 | ||
22f6b860 | 1577 | /* Set a MAC change in hardware. */ |
1da177e4 LT |
1578 | static void |
1579 | fec_set_mac_address(struct net_device *dev) | |
1580 | { | |
f44d6305 | 1581 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 LT |
1582 | |
1583 | /* Set station address. */ | |
f44d6305 SH |
1584 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1585 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), | |
1586 | fep->hwp + FEC_ADDR_LOW); | |
1587 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), | |
1588 | fep + FEC_ADDR_HIGH); | |
1da177e4 LT |
1589 | } |
1590 | ||
1da177e4 LT |
1591 | /* |
1592 | * XXX: We need to clean up on failure exits here. | |
ead73183 SH |
1593 | * |
1594 | * index is only used in legacy code | |
1da177e4 | 1595 | */ |
ead73183 | 1596 | int __init fec_enet_init(struct net_device *dev, int index) |
1da177e4 LT |
1597 | { |
1598 | struct fec_enet_private *fep = netdev_priv(dev); | |
1599 | unsigned long mem_addr; | |
2e28532f | 1600 | struct bufdesc *bdp, *cbd_base; |
1da177e4 | 1601 | int i, j; |
1da177e4 | 1602 | |
8d4dd5cf SH |
1603 | /* Allocate memory for buffer descriptors. */ |
1604 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1605 | GFP_KERNEL); | |
1606 | if (!cbd_base) { | |
562d2f8c GU |
1607 | printk("FEC: allocate descriptor memory failed?\n"); |
1608 | return -ENOMEM; | |
1609 | } | |
1610 | ||
3b2b74ca SS |
1611 | spin_lock_init(&fep->hw_lock); |
1612 | spin_lock_init(&fep->mii_lock); | |
1613 | ||
1da177e4 | 1614 | fep->index = index; |
f44d6305 | 1615 | fep->hwp = (void __iomem *)dev->base_addr; |
cb84d6e7 | 1616 | fep->netdev = dev; |
1da177e4 | 1617 | |
ead73183 | 1618 | /* Set the Ethernet address */ |
43be6366 | 1619 | #ifdef CONFIG_M5272 |
1da177e4 | 1620 | fec_get_mac(dev); |
ead73183 SH |
1621 | #else |
1622 | { | |
1623 | unsigned long l; | |
f44d6305 | 1624 | l = readl(fep->hwp + FEC_ADDR_LOW); |
ead73183 SH |
1625 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); |
1626 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1627 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); | |
1628 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); | |
f44d6305 | 1629 | l = readl(fep->hwp + FEC_ADDR_HIGH); |
ead73183 SH |
1630 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); |
1631 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1632 | } | |
1633 | #endif | |
1da177e4 | 1634 | |
8d4dd5cf | 1635 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1636 | fep->rx_bd_base = cbd_base; |
1637 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1638 | ||
22f6b860 | 1639 | /* Initialize the receive buffer descriptors. */ |
1da177e4 LT |
1640 | bdp = fep->rx_bd_base; |
1641 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
1642 | ||
22f6b860 | 1643 | /* Allocate a page */ |
1da177e4 LT |
1644 | mem_addr = __get_free_page(GFP_KERNEL); |
1645 | /* XXX: missing check for allocation failure */ | |
1646 | ||
22f6b860 | 1647 | /* Initialize the BD for every fragment in the page */ |
1da177e4 LT |
1648 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { |
1649 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1650 | bdp->cbd_bufaddr = __pa(mem_addr); | |
1651 | mem_addr += FEC_ENET_RX_FRSIZE; | |
1652 | bdp++; | |
1653 | } | |
1654 | } | |
1655 | ||
22f6b860 | 1656 | /* Set the last buffer to wrap */ |
1da177e4 LT |
1657 | bdp--; |
1658 | bdp->cbd_sc |= BD_SC_WRAP; | |
1659 | ||
22f6b860 | 1660 | /* ...and the same for transmit */ |
1da177e4 LT |
1661 | bdp = fep->tx_bd_base; |
1662 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
1663 | if (j >= FEC_ENET_TX_FRPPG) { | |
1664 | mem_addr = __get_free_page(GFP_KERNEL); | |
1665 | j = 1; | |
1666 | } else { | |
1667 | mem_addr += FEC_ENET_TX_FRSIZE; | |
1668 | j++; | |
1669 | } | |
1670 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
1671 | ||
22f6b860 | 1672 | /* Initialize the BD for every fragment in the page */ |
1da177e4 LT |
1673 | bdp->cbd_sc = 0; |
1674 | bdp->cbd_bufaddr = 0; | |
1675 | bdp++; | |
1676 | } | |
1677 | ||
22f6b860 | 1678 | /* Set the last buffer to wrap */ |
1da177e4 LT |
1679 | bdp--; |
1680 | bdp->cbd_sc |= BD_SC_WRAP; | |
1681 | ||
43be6366 GU |
1682 | #ifdef HAVE_mii_link_interrupt |
1683 | fec_request_mii_intr(dev); | |
ead73183 | 1684 | #endif |
22f6b860 | 1685 | /* The FEC Ethernet specific entries in the device structure */ |
1da177e4 LT |
1686 | dev->open = fec_enet_open; |
1687 | dev->hard_start_xmit = fec_enet_start_xmit; | |
1688 | dev->tx_timeout = fec_timeout; | |
1689 | dev->watchdog_timeo = TX_TIMEOUT; | |
1690 | dev->stop = fec_enet_close; | |
1da177e4 LT |
1691 | dev->set_multicast_list = set_multicast_list; |
1692 | ||
1693 | for (i=0; i<NMII-1; i++) | |
1694 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
1695 | mii_free = mii_cmds; | |
1696 | ||
22f6b860 | 1697 | /* Set MII speed to 2.5 MHz */ |
ead73183 SH |
1698 | fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) |
1699 | / 2500000) / 2) & 0x3F) << 1; | |
ead73183 | 1700 | fec_restart(dev, 0); |
1da177e4 | 1701 | |
1da177e4 LT |
1702 | /* Queue up command to detect the PHY and initialize the |
1703 | * remainder of the interface. | |
1704 | */ | |
1705 | fep->phy_id_done = 0; | |
1706 | fep->phy_addr = 0; | |
1707 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
1708 | ||
1da177e4 LT |
1709 | return 0; |
1710 | } | |
1711 | ||
1712 | /* This function is called to start or restart the FEC during a link | |
1713 | * change. This only happens when switching between half and full | |
1714 | * duplex. | |
1715 | */ | |
1716 | static void | |
1717 | fec_restart(struct net_device *dev, int duplex) | |
1718 | { | |
f44d6305 | 1719 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 1720 | struct bufdesc *bdp; |
1da177e4 LT |
1721 | int i; |
1722 | ||
f44d6305 SH |
1723 | /* Whack a reset. We should wait for this. */ |
1724 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1725 | udelay(10); |
1726 | ||
f44d6305 SH |
1727 | /* Clear any outstanding interrupt. */ |
1728 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1729 | |
f44d6305 | 1730 | /* Set station address. */ |
7dd6a2aa | 1731 | fec_set_mac_address(dev); |
1da177e4 | 1732 | |
f44d6305 SH |
1733 | /* Reset all multicast. */ |
1734 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1735 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
4f1ceb4b SH |
1736 | #ifndef CONFIG_M5272 |
1737 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1738 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1739 | #endif | |
1da177e4 | 1740 | |
f44d6305 SH |
1741 | /* Set maximum receive buffer size. */ |
1742 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 1743 | |
f44d6305 SH |
1744 | /* Set receive and transmit descriptor base. */ |
1745 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
2e28532f | 1746 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1747 | fep->hwp + FEC_X_DES_START); |
1da177e4 LT |
1748 | |
1749 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1750 | fep->cur_rx = fep->rx_bd_base; | |
1751 | ||
f44d6305 | 1752 | /* Reset SKB transmit buffers. */ |
1da177e4 | 1753 | fep->skb_cur = fep->skb_dirty = 0; |
22f6b860 SH |
1754 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
1755 | if (fep->tx_skbuff[i]) { | |
1da177e4 LT |
1756 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
1757 | fep->tx_skbuff[i] = NULL; | |
1758 | } | |
1759 | } | |
1760 | ||
f44d6305 | 1761 | /* Initialize the receive buffer descriptors. */ |
1da177e4 | 1762 | bdp = fep->rx_bd_base; |
22f6b860 | 1763 | for (i = 0; i < RX_RING_SIZE; i++) { |
1da177e4 | 1764 | |
f44d6305 | 1765 | /* Initialize the BD for every fragment in the page. */ |
1da177e4 LT |
1766 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
1767 | bdp++; | |
1768 | } | |
1769 | ||
22f6b860 | 1770 | /* Set the last buffer to wrap */ |
1da177e4 LT |
1771 | bdp--; |
1772 | bdp->cbd_sc |= BD_SC_WRAP; | |
1773 | ||
22f6b860 | 1774 | /* ...and the same for transmit */ |
1da177e4 | 1775 | bdp = fep->tx_bd_base; |
22f6b860 | 1776 | for (i = 0; i < TX_RING_SIZE; i++) { |
1da177e4 | 1777 | |
f44d6305 | 1778 | /* Initialize the BD for every fragment in the page. */ |
1da177e4 LT |
1779 | bdp->cbd_sc = 0; |
1780 | bdp->cbd_bufaddr = 0; | |
1781 | bdp++; | |
1782 | } | |
1783 | ||
22f6b860 | 1784 | /* Set the last buffer to wrap */ |
1da177e4 LT |
1785 | bdp--; |
1786 | bdp->cbd_sc |= BD_SC_WRAP; | |
1787 | ||
22f6b860 | 1788 | /* Enable MII mode */ |
1da177e4 | 1789 | if (duplex) { |
f44d6305 SH |
1790 | /* MII enable / FD enable */ |
1791 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
1792 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
f909b1ef | 1793 | } else { |
f44d6305 SH |
1794 | /* MII enable / No Rcv on Xmit */ |
1795 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
1796 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
1da177e4 LT |
1797 | } |
1798 | fep->full_duplex = duplex; | |
1799 | ||
22f6b860 | 1800 | /* Set MII speed */ |
f44d6305 | 1801 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1802 | |
22f6b860 | 1803 | /* And last, enable the transmit and receive processing */ |
f44d6305 SH |
1804 | writel(2, fep->hwp + FEC_ECNTRL); |
1805 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
6b265293 | 1806 | |
22f6b860 | 1807 | /* Enable interrupts we wish to service */ |
f44d6305 SH |
1808 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, |
1809 | fep->hwp + FEC_IMASK); | |
1da177e4 LT |
1810 | } |
1811 | ||
1812 | static void | |
1813 | fec_stop(struct net_device *dev) | |
1814 | { | |
f44d6305 | 1815 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1816 | |
22f6b860 | 1817 | /* We cannot expect a graceful transmit stop without link !!! */ |
f44d6305 SH |
1818 | if (fep->link) { |
1819 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
677177c5 | 1820 | udelay(10); |
f44d6305 | 1821 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
677177c5 | 1822 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
f44d6305 | 1823 | } |
1da177e4 | 1824 | |
f44d6305 SH |
1825 | /* Whack a reset. We should wait for this. */ |
1826 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1827 | udelay(10); |
1828 | ||
f44d6305 SH |
1829 | /* Clear outstanding MII command interrupts. */ |
1830 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1831 | |
f44d6305 SH |
1832 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); |
1833 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 LT |
1834 | } |
1835 | ||
ead73183 SH |
1836 | static int __devinit |
1837 | fec_probe(struct platform_device *pdev) | |
1838 | { | |
1839 | struct fec_enet_private *fep; | |
1840 | struct net_device *ndev; | |
1841 | int i, irq, ret = 0; | |
1842 | struct resource *r; | |
1843 | ||
1844 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1845 | if (!r) | |
1846 | return -ENXIO; | |
1847 | ||
1848 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1849 | if (!r) | |
1850 | return -EBUSY; | |
1851 | ||
1852 | /* Init network device */ | |
1853 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
1854 | if (!ndev) | |
1855 | return -ENOMEM; | |
1856 | ||
1857 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1858 | ||
1859 | /* setup board info structure */ | |
1860 | fep = netdev_priv(ndev); | |
1861 | memset(fep, 0, sizeof(*fep)); | |
1862 | ||
1863 | ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); | |
1864 | ||
1865 | if (!ndev->base_addr) { | |
1866 | ret = -ENOMEM; | |
1867 | goto failed_ioremap; | |
1868 | } | |
1869 | ||
1870 | platform_set_drvdata(pdev, ndev); | |
1871 | ||
1872 | /* This device has up to three irqs on some platforms */ | |
1873 | for (i = 0; i < 3; i++) { | |
1874 | irq = platform_get_irq(pdev, i); | |
1875 | if (i && irq < 0) | |
1876 | break; | |
1877 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1878 | if (ret) { | |
1879 | while (i >= 0) { | |
1880 | irq = platform_get_irq(pdev, i); | |
1881 | free_irq(irq, ndev); | |
1882 | i--; | |
1883 | } | |
1884 | goto failed_irq; | |
1885 | } | |
1886 | } | |
1887 | ||
1888 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1889 | if (IS_ERR(fep->clk)) { | |
1890 | ret = PTR_ERR(fep->clk); | |
1891 | goto failed_clk; | |
1892 | } | |
1893 | clk_enable(fep->clk); | |
1894 | ||
1895 | ret = fec_enet_init(ndev, 0); | |
1896 | if (ret) | |
1897 | goto failed_init; | |
1898 | ||
1899 | ret = register_netdev(ndev); | |
1900 | if (ret) | |
1901 | goto failed_register; | |
1902 | ||
1903 | return 0; | |
1904 | ||
1905 | failed_register: | |
1906 | failed_init: | |
1907 | clk_disable(fep->clk); | |
1908 | clk_put(fep->clk); | |
1909 | failed_clk: | |
1910 | for (i = 0; i < 3; i++) { | |
1911 | irq = platform_get_irq(pdev, i); | |
1912 | if (irq > 0) | |
1913 | free_irq(irq, ndev); | |
1914 | } | |
1915 | failed_irq: | |
1916 | iounmap((void __iomem *)ndev->base_addr); | |
1917 | failed_ioremap: | |
1918 | free_netdev(ndev); | |
1919 | ||
1920 | return ret; | |
1921 | } | |
1922 | ||
1923 | static int __devexit | |
1924 | fec_drv_remove(struct platform_device *pdev) | |
1925 | { | |
1926 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1927 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1928 | ||
1929 | platform_set_drvdata(pdev, NULL); | |
1930 | ||
1931 | fec_stop(ndev); | |
1932 | clk_disable(fep->clk); | |
1933 | clk_put(fep->clk); | |
1934 | iounmap((void __iomem *)ndev->base_addr); | |
1935 | unregister_netdev(ndev); | |
1936 | free_netdev(ndev); | |
1937 | return 0; | |
1938 | } | |
1939 | ||
1940 | static int | |
1941 | fec_suspend(struct platform_device *dev, pm_message_t state) | |
1942 | { | |
1943 | struct net_device *ndev = platform_get_drvdata(dev); | |
1944 | struct fec_enet_private *fep; | |
1945 | ||
1946 | if (ndev) { | |
1947 | fep = netdev_priv(ndev); | |
1948 | if (netif_running(ndev)) { | |
1949 | netif_device_detach(ndev); | |
1950 | fec_stop(ndev); | |
1951 | } | |
1952 | } | |
1953 | return 0; | |
1954 | } | |
1955 | ||
1956 | static int | |
1957 | fec_resume(struct platform_device *dev) | |
1958 | { | |
1959 | struct net_device *ndev = platform_get_drvdata(dev); | |
1960 | ||
1961 | if (ndev) { | |
1962 | if (netif_running(ndev)) { | |
1963 | fec_enet_init(ndev, 0); | |
1964 | netif_device_attach(ndev); | |
1965 | } | |
1966 | } | |
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | static struct platform_driver fec_driver = { | |
1971 | .driver = { | |
1972 | .name = "fec", | |
1973 | .owner = THIS_MODULE, | |
1974 | }, | |
1975 | .probe = fec_probe, | |
1976 | .remove = __devexit_p(fec_drv_remove), | |
1977 | .suspend = fec_suspend, | |
1978 | .resume = fec_resume, | |
1979 | }; | |
1980 | ||
1981 | static int __init | |
1982 | fec_enet_module_init(void) | |
1983 | { | |
1984 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1985 | ||
1986 | return platform_driver_register(&fec_driver); | |
1987 | } | |
1988 | ||
1989 | static void __exit | |
1990 | fec_enet_cleanup(void) | |
1991 | { | |
1992 | platform_driver_unregister(&fec_driver); | |
1993 | } | |
1994 | ||
1995 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1996 | module_init(fec_enet_module_init); |
1997 | ||
1998 | MODULE_LICENSE("GPL"); |