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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
39 | ||
40 | #include <asm/irq.h> | |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/io.h> | |
43 | #include <asm/pgtable.h> | |
080853af | 44 | #include <asm/cacheflush.h> |
1da177e4 | 45 | |
1da177e4 LT |
46 | #include <asm/coldfire.h> |
47 | #include <asm/mcfsim.h> | |
48 | #include "fec.h" | |
1da177e4 LT |
49 | |
50 | #if defined(CONFIG_FEC2) | |
51 | #define FEC_MAX_PORTS 2 | |
52 | #else | |
53 | #define FEC_MAX_PORTS 1 | |
54 | #endif | |
55 | ||
87f4abb4 | 56 | #if defined(CONFIG_M5272) |
c1d96156 SS |
57 | #define HAVE_mii_link_interrupt |
58 | #endif | |
59 | ||
1da177e4 LT |
60 | /* |
61 | * Define the fixed address of the FEC hardware. | |
62 | */ | |
63 | static unsigned int fec_hw[] = { | |
64 | #if defined(CONFIG_M5272) | |
65 | (MCF_MBAR + 0x840), | |
66 | #elif defined(CONFIG_M527x) | |
67 | (MCF_MBAR + 0x1000), | |
68 | (MCF_MBAR + 0x1800), | |
7dd6a2aa | 69 | #elif defined(CONFIG_M523x) || defined(CONFIG_M528x) |
1da177e4 | 70 | (MCF_MBAR + 0x1000), |
562d2f8c GU |
71 | #elif defined(CONFIG_M520x) |
72 | (MCF_MBAR+0x30000), | |
6b265293 MW |
73 | #elif defined(CONFIG_M532x) |
74 | (MCF_MBAR+0xfc030000), | |
1da177e4 LT |
75 | #endif |
76 | }; | |
77 | ||
78 | static unsigned char fec_mac_default[] = { | |
79 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
80 | }; | |
81 | ||
82 | /* | |
83 | * Some hardware gets it MAC address out of local flash memory. | |
84 | * if this is non-zero then assume it is the address to get MAC from. | |
85 | */ | |
86 | #if defined(CONFIG_NETtel) | |
87 | #define FEC_FLASHMAC 0xf0006006 | |
88 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
89 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
90 | #elif defined(CONFIG_CANCam) |
91 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
92 | #elif defined (CONFIG_M5272C3) |
93 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
94 | #elif defined(CONFIG_MOD5272) | |
95 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
96 | #else |
97 | #define FEC_FLASHMAC 0 | |
98 | #endif | |
99 | ||
1da177e4 LT |
100 | /* Forward declarations of some structures to support different PHYs |
101 | */ | |
102 | ||
103 | typedef struct { | |
104 | uint mii_data; | |
105 | void (*funct)(uint mii_reg, struct net_device *dev); | |
106 | } phy_cmd_t; | |
107 | ||
108 | typedef struct { | |
109 | uint id; | |
110 | char *name; | |
111 | ||
112 | const phy_cmd_t *config; | |
113 | const phy_cmd_t *startup; | |
114 | const phy_cmd_t *ack_int; | |
115 | const phy_cmd_t *shutdown; | |
116 | } phy_info_t; | |
117 | ||
118 | /* The number of Tx and Rx buffers. These are allocated from the page | |
119 | * pool. The code may assume these are power of two, so it it best | |
120 | * to keep them that size. | |
121 | * We don't need to allocate pages for the transmitter. We just use | |
122 | * the skbuffer directly. | |
123 | */ | |
124 | #define FEC_ENET_RX_PAGES 8 | |
125 | #define FEC_ENET_RX_FRSIZE 2048 | |
126 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
127 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
128 | #define FEC_ENET_TX_FRSIZE 2048 | |
129 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
130 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
131 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
132 | ||
562d2f8c | 133 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 134 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
135 | #endif |
136 | ||
1da177e4 LT |
137 | /* Interrupt events/masks. |
138 | */ | |
139 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | |
140 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
141 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
142 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
143 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
144 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
145 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
146 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
147 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
148 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
149 | ||
150 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
151 | */ | |
152 | #define PKT_MAXBUF_SIZE 1518 | |
153 | #define PKT_MINBUF_SIZE 64 | |
154 | #define PKT_MAXBLR_SIZE 1520 | |
155 | ||
156 | ||
157 | /* | |
6b265293 | 158 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
159 | * size bits. Other FEC hardware does not, so we need to take that into |
160 | * account when setting it. | |
161 | */ | |
562d2f8c | 162 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
6b265293 | 163 | defined(CONFIG_M520x) || defined(CONFIG_M532x) |
1da177e4 LT |
164 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
165 | #else | |
166 | #define OPT_FRAME_SIZE 0 | |
167 | #endif | |
168 | ||
169 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
170 | * tx_bd_base always point to the base of the buffer descriptors. The | |
171 | * cur_rx and cur_tx point to the currently available buffer. | |
172 | * The dirty_tx tracks the current buffer that is being sent by the | |
173 | * controller. The cur_tx and dirty_tx are equal under both completely | |
174 | * empty and completely full conditions. The empty/ready indicator in | |
175 | * the buffer descriptor determines the actual condition. | |
176 | */ | |
177 | struct fec_enet_private { | |
178 | /* Hardware registers of the FEC device */ | |
179 | volatile fec_t *hwp; | |
180 | ||
cb84d6e7 GU |
181 | struct net_device *netdev; |
182 | ||
1da177e4 LT |
183 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
184 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
185 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
186 | ushort skb_cur; | |
187 | ushort skb_dirty; | |
188 | ||
189 | /* CPM dual port RAM relative addresses. | |
190 | */ | |
191 | cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */ | |
192 | cbd_t *tx_bd_base; | |
193 | cbd_t *cur_rx, *cur_tx; /* The next free ring entry */ | |
194 | cbd_t *dirty_tx; /* The ring entries to be free()ed. */ | |
1da177e4 | 195 | uint tx_full; |
3b2b74ca SS |
196 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
197 | spinlock_t hw_lock; | |
198 | /* hold while accessing the mii_list_t() elements */ | |
199 | spinlock_t mii_lock; | |
1da177e4 LT |
200 | |
201 | uint phy_id; | |
202 | uint phy_id_done; | |
203 | uint phy_status; | |
204 | uint phy_speed; | |
7dd6a2aa | 205 | phy_info_t const *phy; |
1da177e4 LT |
206 | struct work_struct phy_task; |
207 | ||
208 | uint sequence_done; | |
209 | uint mii_phy_task_queued; | |
210 | ||
211 | uint phy_addr; | |
212 | ||
213 | int index; | |
214 | int opened; | |
215 | int link; | |
216 | int old_link; | |
217 | int full_duplex; | |
1da177e4 LT |
218 | }; |
219 | ||
220 | static int fec_enet_open(struct net_device *dev); | |
221 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
222 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 223 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
224 | static void fec_enet_tx(struct net_device *dev); |
225 | static void fec_enet_rx(struct net_device *dev); | |
226 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
227 | static void set_multicast_list(struct net_device *dev); |
228 | static void fec_restart(struct net_device *dev, int duplex); | |
229 | static void fec_stop(struct net_device *dev); | |
230 | static void fec_set_mac_address(struct net_device *dev); | |
231 | ||
232 | ||
233 | /* MII processing. We keep this as simple as possible. Requests are | |
234 | * placed on the list (if there is room). When the request is finished | |
235 | * by the MII, an optional function may be called. | |
236 | */ | |
237 | typedef struct mii_list { | |
238 | uint mii_regval; | |
239 | void (*mii_func)(uint val, struct net_device *dev); | |
240 | struct mii_list *mii_next; | |
241 | } mii_list_t; | |
242 | ||
243 | #define NMII 20 | |
7dd6a2aa GU |
244 | static mii_list_t mii_cmds[NMII]; |
245 | static mii_list_t *mii_free; | |
246 | static mii_list_t *mii_head; | |
247 | static mii_list_t *mii_tail; | |
1da177e4 | 248 | |
6aa20a22 | 249 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
250 | void (*func)(uint, struct net_device *)); |
251 | ||
252 | /* Make MII read/write commands for the FEC. | |
253 | */ | |
254 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
255 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
256 | (VAL & 0xffff)) | |
257 | #define mk_mii_end 0 | |
258 | ||
259 | /* Transmitter timeout. | |
260 | */ | |
261 | #define TX_TIMEOUT (2*HZ) | |
262 | ||
263 | /* Register definitions for the PHY. | |
264 | */ | |
265 | ||
266 | #define MII_REG_CR 0 /* Control Register */ | |
267 | #define MII_REG_SR 1 /* Status Register */ | |
268 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
269 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 270 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
271 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
272 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
273 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
274 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
275 | ||
276 | /* values for phy_status */ | |
277 | ||
278 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
279 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
280 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
281 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 282 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 283 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 284 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
285 | |
286 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
287 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
288 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
289 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
290 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 291 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 292 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 293 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
294 | |
295 | ||
296 | static int | |
297 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
298 | { | |
299 | struct fec_enet_private *fep; | |
300 | volatile fec_t *fecp; | |
301 | volatile cbd_t *bdp; | |
0e702ab3 | 302 | unsigned short status; |
3b2b74ca | 303 | unsigned long flags; |
1da177e4 LT |
304 | |
305 | fep = netdev_priv(dev); | |
306 | fecp = (volatile fec_t*)dev->base_addr; | |
307 | ||
308 | if (!fep->link) { | |
309 | /* Link is down or autonegotiation is in progress. */ | |
310 | return 1; | |
311 | } | |
312 | ||
3b2b74ca | 313 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
314 | /* Fill in a Tx ring entry */ |
315 | bdp = fep->cur_tx; | |
316 | ||
0e702ab3 | 317 | status = bdp->cbd_sc; |
1da177e4 | 318 | #ifndef final_version |
0e702ab3 | 319 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
320 | /* Ooops. All transmit buffers are full. Bail out. |
321 | * This should not happen, since dev->tbusy should be set. | |
322 | */ | |
323 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 324 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
325 | return 1; |
326 | } | |
327 | #endif | |
328 | ||
329 | /* Clear all of the status flags. | |
330 | */ | |
0e702ab3 | 331 | status &= ~BD_ENET_TX_STATS; |
1da177e4 LT |
332 | |
333 | /* Set buffer length and buffer pointer. | |
334 | */ | |
335 | bdp->cbd_bufaddr = __pa(skb->data); | |
336 | bdp->cbd_datlen = skb->len; | |
337 | ||
338 | /* | |
339 | * On some FEC implementations data must be aligned on | |
340 | * 4-byte boundaries. Use bounce buffers to copy data | |
341 | * and get it aligned. Ugh. | |
342 | */ | |
343 | if (bdp->cbd_bufaddr & 0x3) { | |
344 | unsigned int index; | |
345 | index = bdp - fep->tx_bd_base; | |
346 | memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen); | |
347 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); | |
348 | } | |
349 | ||
350 | /* Save skb pointer. | |
351 | */ | |
352 | fep->tx_skbuff[fep->skb_cur] = skb; | |
353 | ||
09f75cd7 | 354 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 355 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 356 | |
1da177e4 LT |
357 | /* Push the data cache so the CPM does not get stale memory |
358 | * data. | |
359 | */ | |
360 | flush_dcache_range((unsigned long)skb->data, | |
361 | (unsigned long)skb->data + skb->len); | |
362 | ||
0e702ab3 GU |
363 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
364 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 LT |
365 | */ |
366 | ||
0e702ab3 | 367 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 368 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 369 | bdp->cbd_sc = status; |
1da177e4 LT |
370 | |
371 | dev->trans_start = jiffies; | |
372 | ||
373 | /* Trigger transmission start */ | |
0e702ab3 | 374 | fecp->fec_x_des_active = 0; |
1da177e4 LT |
375 | |
376 | /* If this was the last BD in the ring, start at the beginning again. | |
377 | */ | |
0e702ab3 | 378 | if (status & BD_ENET_TX_WRAP) { |
1da177e4 LT |
379 | bdp = fep->tx_bd_base; |
380 | } else { | |
381 | bdp++; | |
382 | } | |
383 | ||
384 | if (bdp == fep->dirty_tx) { | |
385 | fep->tx_full = 1; | |
386 | netif_stop_queue(dev); | |
387 | } | |
388 | ||
389 | fep->cur_tx = (cbd_t *)bdp; | |
390 | ||
3b2b74ca | 391 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void | |
397 | fec_timeout(struct net_device *dev) | |
398 | { | |
399 | struct fec_enet_private *fep = netdev_priv(dev); | |
400 | ||
401 | printk("%s: transmit timed out.\n", dev->name); | |
09f75cd7 | 402 | dev->stats.tx_errors++; |
1da177e4 LT |
403 | #ifndef final_version |
404 | { | |
405 | int i; | |
406 | cbd_t *bdp; | |
407 | ||
408 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
409 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
410 | (unsigned long)fep->dirty_tx, | |
411 | (unsigned long)fep->cur_rx); | |
412 | ||
413 | bdp = fep->tx_bd_base; | |
414 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
415 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 416 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
417 | (uint) bdp, |
418 | bdp->cbd_sc, | |
419 | bdp->cbd_datlen, | |
420 | (int) bdp->cbd_bufaddr); | |
421 | bdp++; | |
422 | } | |
423 | ||
424 | bdp = fep->rx_bd_base; | |
425 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
426 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
427 | printk(" %08x: %04x %04x %08x\n", | |
428 | (uint) bdp, | |
429 | bdp->cbd_sc, | |
430 | bdp->cbd_datlen, | |
431 | (int) bdp->cbd_bufaddr); | |
432 | bdp++; | |
433 | } | |
434 | } | |
435 | #endif | |
7dd6a2aa | 436 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
437 | netif_wake_queue(dev); |
438 | } | |
439 | ||
440 | /* The interrupt handler. | |
441 | * This is called from the MPC core interrupt. | |
442 | */ | |
443 | static irqreturn_t | |
7d12e780 | 444 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
445 | { |
446 | struct net_device *dev = dev_id; | |
447 | volatile fec_t *fecp; | |
448 | uint int_events; | |
3b2b74ca | 449 | irqreturn_t ret = IRQ_NONE; |
1da177e4 LT |
450 | |
451 | fecp = (volatile fec_t*)dev->base_addr; | |
452 | ||
453 | /* Get the interrupt events that caused us to be here. | |
454 | */ | |
3b2b74ca SS |
455 | do { |
456 | int_events = fecp->fec_ievent; | |
1da177e4 LT |
457 | fecp->fec_ievent = int_events; |
458 | ||
459 | /* Handle receive event in its own function. | |
460 | */ | |
461 | if (int_events & FEC_ENET_RXF) { | |
3b2b74ca | 462 | ret = IRQ_HANDLED; |
1da177e4 LT |
463 | fec_enet_rx(dev); |
464 | } | |
465 | ||
466 | /* Transmit OK, or non-fatal error. Update the buffer | |
467 | descriptors. FEC handles all errors, we just discover | |
468 | them as part of the transmit process. | |
469 | */ | |
470 | if (int_events & FEC_ENET_TXF) { | |
3b2b74ca | 471 | ret = IRQ_HANDLED; |
1da177e4 LT |
472 | fec_enet_tx(dev); |
473 | } | |
474 | ||
475 | if (int_events & FEC_ENET_MII) { | |
3b2b74ca | 476 | ret = IRQ_HANDLED; |
1da177e4 LT |
477 | fec_enet_mii(dev); |
478 | } | |
6aa20a22 | 479 | |
3b2b74ca SS |
480 | } while (int_events); |
481 | ||
482 | return ret; | |
1da177e4 LT |
483 | } |
484 | ||
485 | ||
486 | static void | |
487 | fec_enet_tx(struct net_device *dev) | |
488 | { | |
489 | struct fec_enet_private *fep; | |
490 | volatile cbd_t *bdp; | |
0e702ab3 | 491 | unsigned short status; |
1da177e4 LT |
492 | struct sk_buff *skb; |
493 | ||
494 | fep = netdev_priv(dev); | |
3b2b74ca | 495 | spin_lock_irq(&fep->hw_lock); |
1da177e4 LT |
496 | bdp = fep->dirty_tx; |
497 | ||
0e702ab3 | 498 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
499 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
500 | ||
501 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
502 | /* Check for errors. */ | |
0e702ab3 | 503 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
504 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
505 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 506 | dev->stats.tx_errors++; |
0e702ab3 | 507 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 508 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 509 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 510 | dev->stats.tx_window_errors++; |
0e702ab3 | 511 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 512 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 513 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 514 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 515 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 516 | dev->stats.tx_carrier_errors++; |
1da177e4 | 517 | } else { |
09f75cd7 | 518 | dev->stats.tx_packets++; |
1da177e4 LT |
519 | } |
520 | ||
521 | #ifndef final_version | |
0e702ab3 | 522 | if (status & BD_ENET_TX_READY) |
1da177e4 LT |
523 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
524 | #endif | |
525 | /* Deferred means some collisions occurred during transmit, | |
526 | * but we eventually sent the packet OK. | |
527 | */ | |
0e702ab3 | 528 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 529 | dev->stats.collisions++; |
6aa20a22 | 530 | |
1da177e4 LT |
531 | /* Free the sk buffer associated with this last transmit. |
532 | */ | |
533 | dev_kfree_skb_any(skb); | |
534 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
535 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 536 | |
1da177e4 LT |
537 | /* Update pointer to next buffer descriptor to be transmitted. |
538 | */ | |
0e702ab3 | 539 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
540 | bdp = fep->tx_bd_base; |
541 | else | |
542 | bdp++; | |
6aa20a22 | 543 | |
1da177e4 LT |
544 | /* Since we have freed up a buffer, the ring is no longer |
545 | * full. | |
546 | */ | |
547 | if (fep->tx_full) { | |
548 | fep->tx_full = 0; | |
549 | if (netif_queue_stopped(dev)) | |
550 | netif_wake_queue(dev); | |
551 | } | |
552 | } | |
553 | fep->dirty_tx = (cbd_t *)bdp; | |
3b2b74ca | 554 | spin_unlock_irq(&fep->hw_lock); |
1da177e4 LT |
555 | } |
556 | ||
557 | ||
558 | /* During a receive, the cur_rx points to the current incoming buffer. | |
559 | * When we update through the ring, if the next incoming buffer has | |
560 | * not been given to the system, we just set the empty indicator, | |
561 | * effectively tossing the packet. | |
562 | */ | |
563 | static void | |
564 | fec_enet_rx(struct net_device *dev) | |
565 | { | |
566 | struct fec_enet_private *fep; | |
567 | volatile fec_t *fecp; | |
568 | volatile cbd_t *bdp; | |
0e702ab3 | 569 | unsigned short status; |
1da177e4 LT |
570 | struct sk_buff *skb; |
571 | ushort pkt_len; | |
572 | __u8 *data; | |
6aa20a22 | 573 | |
0e702ab3 GU |
574 | #ifdef CONFIG_M532x |
575 | flush_cache_all(); | |
6aa20a22 | 576 | #endif |
1da177e4 LT |
577 | |
578 | fep = netdev_priv(dev); | |
579 | fecp = (volatile fec_t*)dev->base_addr; | |
580 | ||
3b2b74ca SS |
581 | spin_lock_irq(&fep->hw_lock); |
582 | ||
1da177e4 LT |
583 | /* First, grab all of the stats for the incoming packet. |
584 | * These get messed up if we get called due to a busy condition. | |
585 | */ | |
586 | bdp = fep->cur_rx; | |
587 | ||
0e702ab3 | 588 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 LT |
589 | |
590 | #ifndef final_version | |
591 | /* Since we have allocated space to hold a complete frame, | |
592 | * the last indicator should be set. | |
593 | */ | |
0e702ab3 | 594 | if ((status & BD_ENET_RX_LAST) == 0) |
1da177e4 LT |
595 | printk("FEC ENET: rcv is not +last\n"); |
596 | #endif | |
597 | ||
598 | if (!fep->opened) | |
599 | goto rx_processing_done; | |
600 | ||
601 | /* Check for errors. */ | |
0e702ab3 | 602 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
1da177e4 | 603 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
09f75cd7 | 604 | dev->stats.rx_errors++; |
0e702ab3 | 605 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
1da177e4 | 606 | /* Frame too long or too short. */ |
09f75cd7 | 607 | dev->stats.rx_length_errors++; |
1da177e4 | 608 | } |
0e702ab3 | 609 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
09f75cd7 | 610 | dev->stats.rx_frame_errors++; |
0e702ab3 | 611 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
09f75cd7 | 612 | dev->stats.rx_crc_errors++; |
0e702ab3 | 613 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
09f75cd7 | 614 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
615 | } |
616 | ||
617 | /* Report late collisions as a frame error. | |
618 | * On this error, the BD is closed, but we don't know what we | |
619 | * have in the buffer. So, just drop this frame on the floor. | |
620 | */ | |
0e702ab3 | 621 | if (status & BD_ENET_RX_CL) { |
09f75cd7 JG |
622 | dev->stats.rx_errors++; |
623 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
624 | goto rx_processing_done; |
625 | } | |
626 | ||
627 | /* Process the incoming frame. | |
628 | */ | |
09f75cd7 | 629 | dev->stats.rx_packets++; |
1da177e4 | 630 | pkt_len = bdp->cbd_datlen; |
09f75cd7 | 631 | dev->stats.rx_bytes += pkt_len; |
1da177e4 LT |
632 | data = (__u8*)__va(bdp->cbd_bufaddr); |
633 | ||
634 | /* This does 16 byte alignment, exactly what we need. | |
635 | * The packet length includes FCS, but we don't want to | |
636 | * include that when passing upstream as it messes up | |
637 | * bridging applications. | |
638 | */ | |
639 | skb = dev_alloc_skb(pkt_len-4); | |
640 | ||
641 | if (skb == NULL) { | |
642 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
09f75cd7 | 643 | dev->stats.rx_dropped++; |
1da177e4 | 644 | } else { |
1da177e4 | 645 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 646 | skb_copy_to_linear_data(skb, data, pkt_len-4); |
1da177e4 LT |
647 | skb->protocol=eth_type_trans(skb,dev); |
648 | netif_rx(skb); | |
649 | } | |
650 | rx_processing_done: | |
651 | ||
652 | /* Clear the status flags for this buffer. | |
653 | */ | |
0e702ab3 | 654 | status &= ~BD_ENET_RX_STATS; |
1da177e4 LT |
655 | |
656 | /* Mark the buffer empty. | |
657 | */ | |
0e702ab3 GU |
658 | status |= BD_ENET_RX_EMPTY; |
659 | bdp->cbd_sc = status; | |
1da177e4 LT |
660 | |
661 | /* Update BD pointer to next entry. | |
662 | */ | |
0e702ab3 | 663 | if (status & BD_ENET_RX_WRAP) |
1da177e4 LT |
664 | bdp = fep->rx_bd_base; |
665 | else | |
666 | bdp++; | |
6aa20a22 | 667 | |
1da177e4 LT |
668 | #if 1 |
669 | /* Doing this here will keep the FEC running while we process | |
670 | * incoming frames. On a heavily loaded network, we should be | |
671 | * able to keep up at the expense of system resources. | |
672 | */ | |
0e702ab3 | 673 | fecp->fec_r_des_active = 0; |
1da177e4 | 674 | #endif |
0e702ab3 | 675 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
1da177e4 LT |
676 | fep->cur_rx = (cbd_t *)bdp; |
677 | ||
678 | #if 0 | |
679 | /* Doing this here will allow us to process all frames in the | |
680 | * ring before the FEC is allowed to put more there. On a heavily | |
681 | * loaded network, some frames may be lost. Unfortunately, this | |
682 | * increases the interrupt overhead since we can potentially work | |
683 | * our way back to the interrupt return only to come right back | |
684 | * here. | |
685 | */ | |
0e702ab3 | 686 | fecp->fec_r_des_active = 0; |
1da177e4 | 687 | #endif |
3b2b74ca SS |
688 | |
689 | spin_unlock_irq(&fep->hw_lock); | |
1da177e4 LT |
690 | } |
691 | ||
692 | ||
0e702ab3 | 693 | /* called from interrupt context */ |
1da177e4 LT |
694 | static void |
695 | fec_enet_mii(struct net_device *dev) | |
696 | { | |
697 | struct fec_enet_private *fep; | |
698 | volatile fec_t *ep; | |
699 | mii_list_t *mip; | |
700 | uint mii_reg; | |
701 | ||
702 | fep = netdev_priv(dev); | |
3b2b74ca SS |
703 | spin_lock_irq(&fep->mii_lock); |
704 | ||
1da177e4 LT |
705 | ep = fep->hwp; |
706 | mii_reg = ep->fec_mii_data; | |
0e702ab3 | 707 | |
1da177e4 LT |
708 | if ((mip = mii_head) == NULL) { |
709 | printk("MII and no head!\n"); | |
0e702ab3 | 710 | goto unlock; |
1da177e4 LT |
711 | } |
712 | ||
713 | if (mip->mii_func != NULL) | |
714 | (*(mip->mii_func))(mii_reg, dev); | |
715 | ||
716 | mii_head = mip->mii_next; | |
717 | mip->mii_next = mii_free; | |
718 | mii_free = mip; | |
719 | ||
720 | if ((mip = mii_head) != NULL) | |
721 | ep->fec_mii_data = mip->mii_regval; | |
0e702ab3 GU |
722 | |
723 | unlock: | |
3b2b74ca | 724 | spin_unlock_irq(&fep->mii_lock); |
1da177e4 LT |
725 | } |
726 | ||
727 | static int | |
728 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
729 | { | |
730 | struct fec_enet_private *fep; | |
731 | unsigned long flags; | |
732 | mii_list_t *mip; | |
733 | int retval; | |
734 | ||
735 | /* Add PHY address to register command. | |
736 | */ | |
737 | fep = netdev_priv(dev); | |
3b2b74ca | 738 | spin_lock_irqsave(&fep->mii_lock, flags); |
1da177e4 | 739 | |
3b2b74ca | 740 | regval |= fep->phy_addr << 23; |
1da177e4 LT |
741 | retval = 0; |
742 | ||
1da177e4 LT |
743 | if ((mip = mii_free) != NULL) { |
744 | mii_free = mip->mii_next; | |
745 | mip->mii_regval = regval; | |
746 | mip->mii_func = func; | |
747 | mip->mii_next = NULL; | |
748 | if (mii_head) { | |
749 | mii_tail->mii_next = mip; | |
750 | mii_tail = mip; | |
f909b1ef | 751 | } else { |
1da177e4 LT |
752 | mii_head = mii_tail = mip; |
753 | fep->hwp->fec_mii_data = regval; | |
754 | } | |
f909b1ef | 755 | } else { |
1da177e4 LT |
756 | retval = 1; |
757 | } | |
758 | ||
3b2b74ca SS |
759 | spin_unlock_irqrestore(&fep->mii_lock, flags); |
760 | return retval; | |
1da177e4 LT |
761 | } |
762 | ||
763 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
764 | { | |
1da177e4 LT |
765 | if(!c) |
766 | return; | |
767 | ||
be6cb66d PDM |
768 | for (; c->mii_data != mk_mii_end; c++) |
769 | mii_queue(dev, c->mii_data, c->funct); | |
1da177e4 LT |
770 | } |
771 | ||
772 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
773 | { | |
774 | struct fec_enet_private *fep = netdev_priv(dev); | |
775 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 776 | uint status; |
1da177e4 | 777 | |
7dd6a2aa | 778 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
779 | |
780 | if (mii_reg & 0x0004) | |
7dd6a2aa | 781 | status |= PHY_STAT_LINK; |
1da177e4 | 782 | if (mii_reg & 0x0010) |
7dd6a2aa | 783 | status |= PHY_STAT_FAULT; |
1da177e4 | 784 | if (mii_reg & 0x0020) |
7dd6a2aa | 785 | status |= PHY_STAT_ANC; |
7dd6a2aa | 786 | *s = status; |
1da177e4 LT |
787 | } |
788 | ||
789 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
790 | { | |
791 | struct fec_enet_private *fep = netdev_priv(dev); | |
792 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 793 | uint status; |
1da177e4 | 794 | |
7dd6a2aa | 795 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
796 | |
797 | if (mii_reg & 0x1000) | |
7dd6a2aa | 798 | status |= PHY_CONF_ANE; |
1da177e4 | 799 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
800 | status |= PHY_CONF_LOOP; |
801 | *s = status; | |
1da177e4 LT |
802 | } |
803 | ||
804 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
805 | { | |
806 | struct fec_enet_private *fep = netdev_priv(dev); | |
807 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 808 | uint status; |
1da177e4 | 809 | |
7dd6a2aa | 810 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
811 | |
812 | if (mii_reg & 0x0020) | |
7dd6a2aa | 813 | status |= PHY_CONF_10HDX; |
1da177e4 | 814 | if (mii_reg & 0x0040) |
7dd6a2aa | 815 | status |= PHY_CONF_10FDX; |
1da177e4 | 816 | if (mii_reg & 0x0080) |
7dd6a2aa | 817 | status |= PHY_CONF_100HDX; |
1da177e4 | 818 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
819 | status |= PHY_CONF_100FDX; |
820 | *s = status; | |
1da177e4 LT |
821 | } |
822 | ||
823 | /* ------------------------------------------------------------------------- */ | |
824 | /* The Level one LXT970 is used by many boards */ | |
825 | ||
826 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
827 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
828 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
829 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
830 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
831 | ||
832 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
833 | { | |
834 | struct fec_enet_private *fep = netdev_priv(dev); | |
835 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 836 | uint status; |
1da177e4 | 837 | |
7dd6a2aa | 838 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
839 | if (mii_reg & 0x0800) { |
840 | if (mii_reg & 0x1000) | |
7dd6a2aa | 841 | status |= PHY_STAT_100FDX; |
1da177e4 | 842 | else |
7dd6a2aa | 843 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
844 | } else { |
845 | if (mii_reg & 0x1000) | |
7dd6a2aa | 846 | status |= PHY_STAT_10FDX; |
1da177e4 | 847 | else |
7dd6a2aa | 848 | status |= PHY_STAT_10HDX; |
1da177e4 | 849 | } |
7dd6a2aa | 850 | *s = status; |
1da177e4 LT |
851 | } |
852 | ||
7dd6a2aa | 853 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
854 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
855 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
856 | { mk_mii_end, } | |
7dd6a2aa GU |
857 | }; |
858 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
859 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
860 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
861 | { mk_mii_end, } | |
7dd6a2aa GU |
862 | }; |
863 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
864 | /* read SR and ISR to acknowledge */ |
865 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
866 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
867 | ||
868 | /* find out the current status */ | |
869 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
870 | { mk_mii_end, } | |
7dd6a2aa GU |
871 | }; |
872 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
873 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
874 | { mk_mii_end, } | |
7dd6a2aa GU |
875 | }; |
876 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 877 | .id = 0x07810000, |
7dd6a2aa GU |
878 | .name = "LXT970", |
879 | .config = phy_cmd_lxt970_config, | |
880 | .startup = phy_cmd_lxt970_startup, | |
881 | .ack_int = phy_cmd_lxt970_ack_int, | |
882 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 883 | }; |
6aa20a22 | 884 | |
1da177e4 LT |
885 | /* ------------------------------------------------------------------------- */ |
886 | /* The Level one LXT971 is used on some of my custom boards */ | |
887 | ||
888 | /* register definitions for the 971 */ | |
889 | ||
890 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
891 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
892 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
893 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
894 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
895 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
896 | ||
6aa20a22 | 897 | /* |
1da177e4 LT |
898 | * I had some nice ideas of running the MDIO faster... |
899 | * The 971 should support 8MHz and I tried it, but things acted really | |
900 | * weird, so 2.5 MHz ought to be enough for anyone... | |
901 | */ | |
902 | ||
903 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
904 | { | |
905 | struct fec_enet_private *fep = netdev_priv(dev); | |
906 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 907 | uint status; |
1da177e4 | 908 | |
7dd6a2aa | 909 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
910 | |
911 | if (mii_reg & 0x0400) { | |
912 | fep->link = 1; | |
7dd6a2aa | 913 | status |= PHY_STAT_LINK; |
1da177e4 LT |
914 | } else { |
915 | fep->link = 0; | |
916 | } | |
917 | if (mii_reg & 0x0080) | |
7dd6a2aa | 918 | status |= PHY_STAT_ANC; |
1da177e4 LT |
919 | if (mii_reg & 0x4000) { |
920 | if (mii_reg & 0x0200) | |
7dd6a2aa | 921 | status |= PHY_STAT_100FDX; |
1da177e4 | 922 | else |
7dd6a2aa | 923 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
924 | } else { |
925 | if (mii_reg & 0x0200) | |
7dd6a2aa | 926 | status |= PHY_STAT_10FDX; |
1da177e4 | 927 | else |
7dd6a2aa | 928 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
929 | } |
930 | if (mii_reg & 0x0008) | |
7dd6a2aa | 931 | status |= PHY_STAT_FAULT; |
1da177e4 | 932 | |
7dd6a2aa GU |
933 | *s = status; |
934 | } | |
6aa20a22 | 935 | |
7dd6a2aa | 936 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 937 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
938 | * doesn't work with 100. */ |
939 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
940 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
941 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
942 | { mk_mii_end, } | |
7dd6a2aa GU |
943 | }; |
944 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
945 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
946 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
947 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
948 | /* Somehow does the 971 tell me that the link is down | |
949 | * the first read after power-up. | |
950 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 951 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 952 | { mk_mii_end, } |
7dd6a2aa GU |
953 | }; |
954 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
955 | /* acknowledge the int before reading status ! */ | |
956 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
957 | /* find out the current status */ |
958 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
959 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 960 | { mk_mii_end, } |
7dd6a2aa GU |
961 | }; |
962 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
963 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
964 | { mk_mii_end, } | |
7dd6a2aa GU |
965 | }; |
966 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 967 | .id = 0x0001378e, |
7dd6a2aa GU |
968 | .name = "LXT971", |
969 | .config = phy_cmd_lxt971_config, | |
970 | .startup = phy_cmd_lxt971_startup, | |
971 | .ack_int = phy_cmd_lxt971_ack_int, | |
972 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
973 | }; |
974 | ||
975 | /* ------------------------------------------------------------------------- */ | |
976 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
977 | ||
978 | /* register definitions */ | |
979 | ||
980 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
981 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
982 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
983 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
984 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
985 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
986 | ||
987 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
988 | { | |
989 | struct fec_enet_private *fep = netdev_priv(dev); | |
990 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 991 | uint status; |
1da177e4 | 992 | |
7dd6a2aa | 993 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
994 | |
995 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
996 | case 1: status |= PHY_STAT_10HDX; break; |
997 | case 2: status |= PHY_STAT_100HDX; break; | |
998 | case 5: status |= PHY_STAT_10FDX; break; | |
999 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
1000 | } |
1001 | ||
7dd6a2aa GU |
1002 | *s = status; |
1003 | } | |
1004 | ||
1005 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 1006 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
1007 | * so send a command to allow operation. |
1008 | */ | |
1009 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
1010 | ||
1011 | /* parse cr and anar to get some info */ | |
1012 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1013 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1014 | { mk_mii_end, } | |
7dd6a2aa GU |
1015 | }; |
1016 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1017 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
1018 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1019 | { mk_mii_end, } | |
7dd6a2aa GU |
1020 | }; |
1021 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
1022 | /* we need to read ISR, SR and ANER to acknowledge */ |
1023 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
1024 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1025 | { mk_mii_read(MII_REG_ANER), NULL }, | |
1026 | ||
1027 | /* read pcr to get info */ | |
1028 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
1029 | { mk_mii_end, } | |
7dd6a2aa GU |
1030 | }; |
1031 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1032 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
1033 | { mk_mii_end, } | |
7dd6a2aa GU |
1034 | }; |
1035 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 1036 | .id = 0x00181440, |
7dd6a2aa GU |
1037 | .name = "QS6612", |
1038 | .config = phy_cmd_qs6612_config, | |
1039 | .startup = phy_cmd_qs6612_startup, | |
1040 | .ack_int = phy_cmd_qs6612_ack_int, | |
1041 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
1042 | }; |
1043 | ||
1044 | /* ------------------------------------------------------------------------- */ | |
1045 | /* AMD AM79C874 phy */ | |
1046 | ||
1047 | /* register definitions for the 874 */ | |
1048 | ||
1049 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
1050 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
1051 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
1052 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
1053 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
1054 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
1055 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
1056 | ||
1057 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
1058 | { | |
1059 | struct fec_enet_private *fep = netdev_priv(dev); | |
1060 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1061 | uint status; |
1da177e4 | 1062 | |
7dd6a2aa | 1063 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1064 | |
1065 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1066 | status |= PHY_STAT_ANC; |
1da177e4 | 1067 | if (mii_reg & 0x0400) |
7dd6a2aa | 1068 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1069 | else |
7dd6a2aa GU |
1070 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1071 | ||
1072 | *s = status; | |
1da177e4 LT |
1073 | } |
1074 | ||
7dd6a2aa | 1075 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1076 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1077 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1078 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1079 | { mk_mii_end, } | |
7dd6a2aa GU |
1080 | }; |
1081 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1082 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1083 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1084 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1085 | { mk_mii_end, } |
7dd6a2aa GU |
1086 | }; |
1087 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1088 | /* find out the current status */ |
1089 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1090 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1091 | /* we only need to read ISR to acknowledge */ | |
1092 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1093 | { mk_mii_end, } | |
7dd6a2aa GU |
1094 | }; |
1095 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1096 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1097 | { mk_mii_end, } | |
7dd6a2aa GU |
1098 | }; |
1099 | static phy_info_t const phy_info_am79c874 = { | |
1100 | .id = 0x00022561, | |
1101 | .name = "AM79C874", | |
1102 | .config = phy_cmd_am79c874_config, | |
1103 | .startup = phy_cmd_am79c874_startup, | |
1104 | .ack_int = phy_cmd_am79c874_ack_int, | |
1105 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1106 | }; |
1107 | ||
7dd6a2aa | 1108 | |
1da177e4 LT |
1109 | /* ------------------------------------------------------------------------- */ |
1110 | /* Kendin KS8721BL phy */ | |
1111 | ||
1112 | /* register definitions for the 8721 */ | |
1113 | ||
1114 | #define MII_KS8721BL_RXERCR 21 | |
1115 | #define MII_KS8721BL_ICSR 22 | |
1116 | #define MII_KS8721BL_PHYCR 31 | |
1117 | ||
7dd6a2aa | 1118 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1119 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1120 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1121 | { mk_mii_end, } | |
7dd6a2aa GU |
1122 | }; |
1123 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1124 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1125 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1126 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1127 | { mk_mii_end, } |
7dd6a2aa GU |
1128 | }; |
1129 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1130 | /* find out the current status */ |
1131 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1132 | /* we only need to read ISR to acknowledge */ | |
1133 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1134 | { mk_mii_end, } | |
7dd6a2aa GU |
1135 | }; |
1136 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1137 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1138 | { mk_mii_end, } | |
7dd6a2aa GU |
1139 | }; |
1140 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1141 | .id = 0x00022161, |
7dd6a2aa GU |
1142 | .name = "KS8721BL", |
1143 | .config = phy_cmd_ks8721bl_config, | |
1144 | .startup = phy_cmd_ks8721bl_startup, | |
1145 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1146 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1147 | }; |
1148 | ||
562d2f8c GU |
1149 | /* ------------------------------------------------------------------------- */ |
1150 | /* register definitions for the DP83848 */ | |
1151 | ||
1152 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1153 | ||
1154 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1155 | { | |
4cf1653a | 1156 | struct fec_enet_private *fep = netdev_priv(dev); |
562d2f8c GU |
1157 | volatile uint *s = &(fep->phy_status); |
1158 | ||
1159 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1160 | ||
1161 | /* Link up */ | |
1162 | if (mii_reg & 0x0001) { | |
1163 | fep->link = 1; | |
1164 | *s |= PHY_STAT_LINK; | |
1165 | } else | |
1166 | fep->link = 0; | |
1167 | /* Status of link */ | |
1168 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1169 | *s |= PHY_STAT_ANC; | |
1170 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1171 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1172 | *s |= PHY_STAT_10FDX; | |
1173 | else | |
1174 | *s |= PHY_STAT_10HDX; | |
1175 | } else { /* 100 Mbps? */ | |
1176 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1177 | *s |= PHY_STAT_100FDX; | |
1178 | else | |
1179 | *s |= PHY_STAT_100HDX; | |
1180 | } | |
1181 | if (mii_reg & 0x0008) | |
1182 | *s |= PHY_STAT_FAULT; | |
1183 | } | |
1184 | ||
1185 | static phy_info_t phy_info_dp83848= { | |
1186 | 0x020005c9, | |
1187 | "DP83848", | |
1188 | ||
1189 | (const phy_cmd_t []) { /* config */ | |
1190 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1191 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1192 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1193 | { mk_mii_end, } | |
1194 | }, | |
1195 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1196 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1197 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1198 | { mk_mii_end, } | |
1199 | }, | |
1200 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1201 | { mk_mii_end, } | |
1202 | }, | |
1203 | (const phy_cmd_t []) { /* shutdown */ | |
1204 | { mk_mii_end, } | |
1205 | }, | |
1206 | }; | |
1207 | ||
1da177e4 LT |
1208 | /* ------------------------------------------------------------------------- */ |
1209 | ||
7dd6a2aa | 1210 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1211 | &phy_info_lxt970, |
1212 | &phy_info_lxt971, | |
1213 | &phy_info_qs6612, | |
1214 | &phy_info_am79c874, | |
1215 | &phy_info_ks8721bl, | |
562d2f8c | 1216 | &phy_info_dp83848, |
1da177e4 LT |
1217 | NULL |
1218 | }; | |
1219 | ||
1220 | /* ------------------------------------------------------------------------- */ | |
c1d96156 | 1221 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1222 | static irqreturn_t |
7d12e780 | 1223 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 LT |
1224 | #endif |
1225 | ||
1226 | #if defined(CONFIG_M5272) | |
1da177e4 LT |
1227 | /* |
1228 | * Code specific to Coldfire 5272 setup. | |
1229 | */ | |
1230 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1231 | { | |
1232 | volatile unsigned long *icrp; | |
7dd6a2aa GU |
1233 | static const struct idesc { |
1234 | char *name; | |
1235 | unsigned short irq; | |
7d12e780 | 1236 | irq_handler_t handler; |
7dd6a2aa GU |
1237 | } *idp, id[] = { |
1238 | { "fec(RX)", 86, fec_enet_interrupt }, | |
1239 | { "fec(TX)", 87, fec_enet_interrupt }, | |
1240 | { "fec(OTHER)", 88, fec_enet_interrupt }, | |
1241 | { "fec(MII)", 66, mii_link_interrupt }, | |
1242 | { NULL }, | |
1243 | }; | |
1da177e4 LT |
1244 | |
1245 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1246 | for (idp = id; idp->name; idp++) { |
0a504779 | 1247 | if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1248 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); |
1249 | } | |
1da177e4 LT |
1250 | |
1251 | /* Unmask interrupt at ColdFire 5272 SIM */ | |
1252 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3); | |
1253 | *icrp = 0x00000ddd; | |
1254 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1255 | *icrp = 0x0d000000; |
1da177e4 LT |
1256 | } |
1257 | ||
1258 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1259 | { | |
1260 | volatile fec_t *fecp; | |
1261 | ||
1262 | fecp = fep->hwp; | |
1263 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1264 | fecp->fec_x_cntrl = 0x00; | |
1265 | ||
1266 | /* | |
1267 | * Set MII speed to 2.5 MHz | |
1268 | * See 5272 manual section 11.5.8: MSCR | |
1269 | */ | |
1270 | fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2; | |
1271 | fecp->fec_mii_speed = fep->phy_speed; | |
1272 | ||
1273 | fec_restart(dev, 0); | |
1274 | } | |
1275 | ||
1276 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1277 | { | |
1278 | struct fec_enet_private *fep = netdev_priv(dev); | |
1279 | volatile fec_t *fecp; | |
7dd6a2aa | 1280 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1281 | |
1282 | fecp = fep->hwp; | |
1283 | ||
7dd6a2aa | 1284 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1285 | /* |
1286 | * Get MAC address from FLASH. | |
1287 | * If it is all 1's or 0's, use the default. | |
1288 | */ | |
7dd6a2aa | 1289 | iap = (unsigned char *)FEC_FLASHMAC; |
1da177e4 LT |
1290 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1291 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1292 | iap = fec_mac_default; | |
1293 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1294 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1295 | iap = fec_mac_default; | |
1296 | } else { | |
1297 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1298 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1299 | iap = &tmpaddr[0]; | |
1300 | } | |
1301 | ||
7dd6a2aa | 1302 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1303 | |
1304 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1305 | if (iap == fec_mac_default) |
1306 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1307 | } |
1308 | ||
1da177e4 LT |
1309 | static void __inline__ fec_disable_phy_intr(void) |
1310 | { | |
1311 | volatile unsigned long *icrp; | |
1312 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1313 | *icrp = 0x08000000; |
1da177e4 LT |
1314 | } |
1315 | ||
1316 | static void __inline__ fec_phy_ack_intr(void) | |
1317 | { | |
1318 | volatile unsigned long *icrp; | |
1319 | /* Acknowledge the interrupt */ | |
1320 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1321 | *icrp = 0x0d000000; |
1da177e4 LT |
1322 | } |
1323 | ||
1da177e4 LT |
1324 | /* ------------------------------------------------------------------------- */ |
1325 | ||
7dd6a2aa | 1326 | #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) |
1da177e4 LT |
1327 | |
1328 | /* | |
7dd6a2aa GU |
1329 | * Code specific to Coldfire 5230/5231/5232/5234/5235, |
1330 | * the 5270/5271/5274/5275 and 5280/5282 setups. | |
1da177e4 LT |
1331 | */ |
1332 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1333 | { | |
1334 | struct fec_enet_private *fep; | |
1335 | int b; | |
7dd6a2aa GU |
1336 | static const struct idesc { |
1337 | char *name; | |
1338 | unsigned short irq; | |
1339 | } *idp, id[] = { | |
1340 | { "fec(TXF)", 23 }, | |
7dd6a2aa | 1341 | { "fec(RXF)", 27 }, |
7dd6a2aa | 1342 | { "fec(MII)", 29 }, |
7dd6a2aa GU |
1343 | { NULL }, |
1344 | }; | |
1da177e4 LT |
1345 | |
1346 | fep = netdev_priv(dev); | |
1347 | b = (fep->index) ? 128 : 64; | |
1348 | ||
1349 | /* Setup interrupt handlers. */ | |
7dd6a2aa | 1350 | for (idp = id; idp->name; idp++) { |
0a504779 | 1351 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0) |
7dd6a2aa GU |
1352 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1353 | } | |
1da177e4 LT |
1354 | |
1355 | /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */ | |
1356 | { | |
1357 | volatile unsigned char *icrp; | |
1358 | volatile unsigned long *imrp; | |
83901fc1 | 1359 | int i, ilip; |
1da177e4 LT |
1360 | |
1361 | b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0; | |
1362 | icrp = (volatile unsigned char *) (MCF_IPSBAR + b + | |
1363 | MCFINTC_ICR0); | |
83901fc1 WC |
1364 | for (i = 23, ilip = 0x28; (i < 36); i++) |
1365 | icrp[i] = ilip--; | |
1da177e4 LT |
1366 | |
1367 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1368 | MCFINTC_IMRH); | |
1369 | *imrp &= ~0x0000000f; | |
1370 | imrp = (volatile unsigned long *) (MCF_IPSBAR + b + | |
1371 | MCFINTC_IMRL); | |
1372 | *imrp &= ~0xff800001; | |
1373 | } | |
1374 | ||
1375 | #if defined(CONFIG_M528x) | |
1376 | /* Set up gpio outputs for MII lines */ | |
1377 | { | |
7dd6a2aa GU |
1378 | volatile u16 *gpio_paspar; |
1379 | volatile u8 *gpio_pehlpar; | |
6aa20a22 | 1380 | |
7dd6a2aa GU |
1381 | gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056); |
1382 | gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058); | |
1383 | *gpio_paspar |= 0x0f00; | |
1384 | *gpio_pehlpar = 0xc0; | |
1da177e4 LT |
1385 | } |
1386 | #endif | |
b8a94b3d MC |
1387 | |
1388 | #if defined(CONFIG_M527x) | |
1389 | /* Set up gpio outputs for MII lines */ | |
1390 | { | |
1391 | volatile u8 *gpio_par_fec; | |
1392 | volatile u16 *gpio_par_feci2c; | |
1393 | ||
1394 | gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082); | |
1395 | /* Set up gpio outputs for FEC0 MII lines */ | |
1396 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078); | |
1397 | ||
1398 | *gpio_par_feci2c |= 0x0f00; | |
1399 | *gpio_par_fec |= 0xc0; | |
1400 | ||
1401 | #if defined(CONFIG_FEC2) | |
1402 | /* Set up gpio outputs for FEC1 MII lines */ | |
1403 | gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079); | |
1404 | ||
1405 | *gpio_par_feci2c |= 0x00a0; | |
1406 | *gpio_par_fec |= 0xc0; | |
1407 | #endif /* CONFIG_FEC2 */ | |
1408 | } | |
1409 | #endif /* CONFIG_M527x */ | |
1da177e4 LT |
1410 | } |
1411 | ||
1412 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1413 | { | |
1414 | volatile fec_t *fecp; | |
1415 | ||
1416 | fecp = fep->hwp; | |
1417 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1418 | fecp->fec_x_cntrl = 0x00; | |
1419 | ||
1420 | /* | |
1421 | * Set MII speed to 2.5 MHz | |
1422 | * See 5282 manual section 17.5.4.7: MSCR | |
1423 | */ | |
1424 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1425 | fecp->fec_mii_speed = fep->phy_speed; | |
1426 | ||
1427 | fec_restart(dev, 0); | |
1428 | } | |
1429 | ||
1430 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1431 | { | |
1432 | struct fec_enet_private *fep = netdev_priv(dev); | |
1433 | volatile fec_t *fecp; | |
7dd6a2aa | 1434 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 LT |
1435 | |
1436 | fecp = fep->hwp; | |
1437 | ||
7dd6a2aa | 1438 | if (FEC_FLASHMAC) { |
1da177e4 LT |
1439 | /* |
1440 | * Get MAC address from FLASH. | |
1441 | * If it is all 1's or 0's, use the default. | |
1442 | */ | |
7dd6a2aa | 1443 | iap = FEC_FLASHMAC; |
1da177e4 LT |
1444 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1445 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1446 | iap = fec_mac_default; | |
1447 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1448 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1449 | iap = fec_mac_default; | |
1450 | } else { | |
1451 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1452 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1453 | iap = &tmpaddr[0]; | |
1454 | } | |
1455 | ||
7dd6a2aa | 1456 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 LT |
1457 | |
1458 | /* Adjust MAC if using default MAC address */ | |
7dd6a2aa GU |
1459 | if (iap == fec_mac_default) |
1460 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1da177e4 LT |
1461 | } |
1462 | ||
1da177e4 LT |
1463 | static void __inline__ fec_disable_phy_intr(void) |
1464 | { | |
1465 | } | |
1466 | ||
1467 | static void __inline__ fec_phy_ack_intr(void) | |
1468 | { | |
1469 | } | |
1470 | ||
1da177e4 LT |
1471 | /* ------------------------------------------------------------------------- */ |
1472 | ||
562d2f8c GU |
1473 | #elif defined(CONFIG_M520x) |
1474 | ||
1475 | /* | |
1476 | * Code specific to Coldfire 520x | |
1477 | */ | |
1478 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1479 | { | |
1480 | struct fec_enet_private *fep; | |
1481 | int b; | |
1482 | static const struct idesc { | |
1483 | char *name; | |
1484 | unsigned short irq; | |
1485 | } *idp, id[] = { | |
1486 | { "fec(TXF)", 23 }, | |
562d2f8c | 1487 | { "fec(RXF)", 27 }, |
562d2f8c | 1488 | { "fec(MII)", 29 }, |
562d2f8c GU |
1489 | { NULL }, |
1490 | }; | |
1491 | ||
1492 | fep = netdev_priv(dev); | |
1493 | b = 64 + 13; | |
1494 | ||
1495 | /* Setup interrupt handlers. */ | |
1496 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1497 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
562d2f8c GU |
1498 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1499 | } | |
1500 | ||
1501 | /* Unmask interrupts at ColdFire interrupt controller */ | |
1502 | { | |
1503 | volatile unsigned char *icrp; | |
1504 | volatile unsigned long *imrp; | |
1505 | ||
1506 | icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1507 | MCFINTC_ICR0); | |
1508 | for (b = 36; (b < 49); b++) | |
1509 | icrp[b] = 0x04; | |
1510 | imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + | |
1511 | MCFINTC_IMRH); | |
1512 | *imrp &= ~0x0001FFF0; | |
1513 | } | |
1514 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0; | |
1515 | *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f; | |
1516 | } | |
1517 | ||
1518 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1519 | { | |
1520 | volatile fec_t *fecp; | |
1521 | ||
1522 | fecp = fep->hwp; | |
1523 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1524 | fecp->fec_x_cntrl = 0x00; | |
1525 | ||
1526 | /* | |
1527 | * Set MII speed to 2.5 MHz | |
1528 | * See 5282 manual section 17.5.4.7: MSCR | |
1529 | */ | |
1530 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1531 | fecp->fec_mii_speed = fep->phy_speed; | |
1532 | ||
1533 | fec_restart(dev, 0); | |
1534 | } | |
1535 | ||
1536 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1537 | { | |
1538 | struct fec_enet_private *fep = netdev_priv(dev); | |
1539 | volatile fec_t *fecp; | |
1540 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1541 | ||
1542 | fecp = fep->hwp; | |
1543 | ||
1544 | if (FEC_FLASHMAC) { | |
1545 | /* | |
1546 | * Get MAC address from FLASH. | |
1547 | * If it is all 1's or 0's, use the default. | |
1548 | */ | |
1549 | iap = FEC_FLASHMAC; | |
1550 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1551 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1552 | iap = fec_mac_default; | |
1553 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1554 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1555 | iap = fec_mac_default; | |
1556 | } else { | |
1557 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1558 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1559 | iap = &tmpaddr[0]; | |
1560 | } | |
1561 | ||
1562 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1563 | ||
1564 | /* Adjust MAC if using default MAC address */ | |
1565 | if (iap == fec_mac_default) | |
1566 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1567 | } | |
1568 | ||
562d2f8c GU |
1569 | static void __inline__ fec_disable_phy_intr(void) |
1570 | { | |
1571 | } | |
1572 | ||
1573 | static void __inline__ fec_phy_ack_intr(void) | |
1574 | { | |
1575 | } | |
1576 | ||
562d2f8c GU |
1577 | /* ------------------------------------------------------------------------- */ |
1578 | ||
6b265293 MW |
1579 | #elif defined(CONFIG_M532x) |
1580 | /* | |
1581 | * Code specific for M532x | |
1582 | */ | |
1583 | static void __inline__ fec_request_intrs(struct net_device *dev) | |
1584 | { | |
1585 | struct fec_enet_private *fep; | |
1586 | int b; | |
1587 | static const struct idesc { | |
1588 | char *name; | |
1589 | unsigned short irq; | |
1590 | } *idp, id[] = { | |
1591 | { "fec(TXF)", 36 }, | |
6b265293 | 1592 | { "fec(RXF)", 40 }, |
6b265293 | 1593 | { "fec(MII)", 42 }, |
6b265293 MW |
1594 | { NULL }, |
1595 | }; | |
1596 | ||
1597 | fep = netdev_priv(dev); | |
1598 | b = (fep->index) ? 128 : 64; | |
1599 | ||
1600 | /* Setup interrupt handlers. */ | |
1601 | for (idp = id; idp->name; idp++) { | |
0a504779 | 1602 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
6aa20a22 | 1603 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
6b265293 MW |
1604 | idp->name, b+idp->irq); |
1605 | } | |
1606 | ||
1607 | /* Unmask interrupts */ | |
1608 | MCF_INTC0_ICR36 = 0x2; | |
1609 | MCF_INTC0_ICR37 = 0x2; | |
1610 | MCF_INTC0_ICR38 = 0x2; | |
1611 | MCF_INTC0_ICR39 = 0x2; | |
1612 | MCF_INTC0_ICR40 = 0x2; | |
1613 | MCF_INTC0_ICR41 = 0x2; | |
1614 | MCF_INTC0_ICR42 = 0x2; | |
1615 | MCF_INTC0_ICR43 = 0x2; | |
1616 | MCF_INTC0_ICR44 = 0x2; | |
1617 | MCF_INTC0_ICR45 = 0x2; | |
1618 | MCF_INTC0_ICR46 = 0x2; | |
1619 | MCF_INTC0_ICR47 = 0x2; | |
1620 | MCF_INTC0_ICR48 = 0x2; | |
1621 | ||
1622 | MCF_INTC0_IMRH &= ~( | |
1623 | MCF_INTC_IMRH_INT_MASK36 | | |
1624 | MCF_INTC_IMRH_INT_MASK37 | | |
1625 | MCF_INTC_IMRH_INT_MASK38 | | |
1626 | MCF_INTC_IMRH_INT_MASK39 | | |
1627 | MCF_INTC_IMRH_INT_MASK40 | | |
1628 | MCF_INTC_IMRH_INT_MASK41 | | |
1629 | MCF_INTC_IMRH_INT_MASK42 | | |
1630 | MCF_INTC_IMRH_INT_MASK43 | | |
1631 | MCF_INTC_IMRH_INT_MASK44 | | |
1632 | MCF_INTC_IMRH_INT_MASK45 | | |
1633 | MCF_INTC_IMRH_INT_MASK46 | | |
1634 | MCF_INTC_IMRH_INT_MASK47 | | |
1635 | MCF_INTC_IMRH_INT_MASK48 ); | |
1636 | ||
1637 | /* Set up gpio outputs for MII lines */ | |
1638 | MCF_GPIO_PAR_FECI2C |= (0 | | |
1639 | MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | | |
1640 | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); | |
1641 | MCF_GPIO_PAR_FEC = (0 | | |
1642 | MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | | |
1643 | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); | |
1644 | } | |
1645 | ||
1646 | static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep) | |
1647 | { | |
1648 | volatile fec_t *fecp; | |
1649 | ||
1650 | fecp = fep->hwp; | |
1651 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04; | |
1652 | fecp->fec_x_cntrl = 0x00; | |
1653 | ||
1654 | /* | |
1655 | * Set MII speed to 2.5 MHz | |
1656 | */ | |
1657 | fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2; | |
1658 | fecp->fec_mii_speed = fep->phy_speed; | |
1659 | ||
1660 | fec_restart(dev, 0); | |
1661 | } | |
1662 | ||
1663 | static void __inline__ fec_get_mac(struct net_device *dev) | |
1664 | { | |
1665 | struct fec_enet_private *fep = netdev_priv(dev); | |
1666 | volatile fec_t *fecp; | |
1667 | unsigned char *iap, tmpaddr[ETH_ALEN]; | |
1668 | ||
1669 | fecp = fep->hwp; | |
1670 | ||
1671 | if (FEC_FLASHMAC) { | |
1672 | /* | |
1673 | * Get MAC address from FLASH. | |
1674 | * If it is all 1's or 0's, use the default. | |
1675 | */ | |
1676 | iap = FEC_FLASHMAC; | |
1677 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && | |
1678 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1679 | iap = fec_mac_default; | |
1680 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1681 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1682 | iap = fec_mac_default; | |
1683 | } else { | |
1684 | *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low; | |
1685 | *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16); | |
1686 | iap = &tmpaddr[0]; | |
1687 | } | |
1688 | ||
1689 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1690 | ||
1691 | /* Adjust MAC if using default MAC address */ | |
1692 | if (iap == fec_mac_default) | |
1693 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; | |
1694 | } | |
1695 | ||
6b265293 MW |
1696 | static void __inline__ fec_disable_phy_intr(void) |
1697 | { | |
1698 | } | |
1699 | ||
1700 | static void __inline__ fec_phy_ack_intr(void) | |
1701 | { | |
1702 | } | |
1703 | ||
1da177e4 LT |
1704 | #endif |
1705 | ||
1706 | /* ------------------------------------------------------------------------- */ | |
1707 | ||
1708 | static void mii_display_status(struct net_device *dev) | |
1709 | { | |
1710 | struct fec_enet_private *fep = netdev_priv(dev); | |
1711 | volatile uint *s = &(fep->phy_status); | |
1712 | ||
1713 | if (!fep->link && !fep->old_link) { | |
1714 | /* Link is still down - don't print anything */ | |
1715 | return; | |
1716 | } | |
1717 | ||
1718 | printk("%s: status: ", dev->name); | |
1719 | ||
1720 | if (!fep->link) { | |
1721 | printk("link down"); | |
1722 | } else { | |
1723 | printk("link up"); | |
1724 | ||
1725 | switch(*s & PHY_STAT_SPMASK) { | |
1726 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1727 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1728 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1729 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1730 | default: | |
1731 | printk(", Unknown speed/duplex"); | |
1732 | } | |
1733 | ||
1734 | if (*s & PHY_STAT_ANC) | |
1735 | printk(", auto-negotiation complete"); | |
1736 | } | |
1737 | ||
1738 | if (*s & PHY_STAT_FAULT) | |
1739 | printk(", remote fault"); | |
1740 | ||
1741 | printk(".\n"); | |
1742 | } | |
1743 | ||
cb84d6e7 | 1744 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1745 | { |
cb84d6e7 GU |
1746 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1747 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1748 | uint status = fep->phy_status; |
1da177e4 LT |
1749 | |
1750 | /* | |
1751 | ** When we get here, phy_task is already removed from | |
1752 | ** the workqueue. It is thus safe to allow to reuse it. | |
1753 | */ | |
1754 | fep->mii_phy_task_queued = 0; | |
1755 | printk("%s: config: auto-negotiation ", dev->name); | |
1756 | ||
7dd6a2aa | 1757 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1758 | printk("on"); |
1759 | else | |
1760 | printk("off"); | |
1761 | ||
7dd6a2aa | 1762 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1763 | printk(", 100FDX"); |
7dd6a2aa | 1764 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1765 | printk(", 100HDX"); |
7dd6a2aa | 1766 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1767 | printk(", 10FDX"); |
7dd6a2aa | 1768 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1769 | printk(", 10HDX"); |
7dd6a2aa | 1770 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1771 | printk(", No speed/duplex selected?"); |
1772 | ||
7dd6a2aa | 1773 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1774 | printk(", loopback enabled"); |
6aa20a22 | 1775 | |
1da177e4 LT |
1776 | printk(".\n"); |
1777 | ||
1778 | fep->sequence_done = 1; | |
1779 | } | |
1780 | ||
cb84d6e7 | 1781 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1782 | { |
cb84d6e7 GU |
1783 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1784 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1785 | int duplex; |
1786 | ||
1787 | /* | |
1788 | ** When we get here, phy_task is already removed from | |
1789 | ** the workqueue. It is thus safe to allow to reuse it. | |
1790 | */ | |
1791 | fep->mii_phy_task_queued = 0; | |
1792 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1793 | mii_display_status(dev); | |
1794 | fep->old_link = fep->link; | |
1795 | ||
1796 | if (fep->link) { | |
1797 | duplex = 0; | |
6aa20a22 | 1798 | if (fep->phy_status |
1da177e4 LT |
1799 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
1800 | duplex = 1; | |
1801 | fec_restart(dev, duplex); | |
f909b1ef | 1802 | } else |
1da177e4 LT |
1803 | fec_stop(dev); |
1804 | ||
1805 | #if 0 | |
1806 | enable_irq(fep->mii_irq); | |
1807 | #endif | |
1808 | ||
1809 | } | |
1810 | ||
1811 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
1812 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
1813 | { | |
1814 | struct fec_enet_private *fep = netdev_priv(dev); | |
1815 | ||
1816 | /* | |
1817 | ** We cannot queue phy_task twice in the workqueue. It | |
1818 | ** would cause an endless loop in the workqueue. | |
1819 | ** Fortunately, if the last mii_relink entry has not yet been | |
1820 | ** executed now, it will do the job for the current interrupt, | |
1821 | ** which is just what we want. | |
1822 | */ | |
1823 | if (fep->mii_phy_task_queued) | |
1824 | return; | |
1825 | ||
1826 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1827 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
1828 | schedule_work(&fep->phy_task); |
1829 | } | |
1830 | ||
7dd6a2aa | 1831 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
1832 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
1833 | { | |
1834 | struct fec_enet_private *fep = netdev_priv(dev); | |
1835 | ||
1836 | if (fep->mii_phy_task_queued) | |
1837 | return; | |
1838 | ||
1839 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1840 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
1841 | schedule_work(&fep->phy_task); |
1842 | } | |
1843 | ||
7dd6a2aa GU |
1844 | phy_cmd_t const phy_cmd_relink[] = { |
1845 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
1846 | { mk_mii_end, } | |
1847 | }; | |
1848 | phy_cmd_t const phy_cmd_config[] = { | |
1849 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
1850 | { mk_mii_end, } | |
1851 | }; | |
1da177e4 LT |
1852 | |
1853 | /* Read remainder of PHY ID. | |
1854 | */ | |
1855 | static void | |
1856 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
1857 | { | |
1858 | struct fec_enet_private *fep; | |
1859 | int i; | |
1860 | ||
1861 | fep = netdev_priv(dev); | |
1862 | fep->phy_id |= (mii_reg & 0xffff); | |
1863 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
1864 | ||
1865 | for(i = 0; phy_info[i]; i++) { | |
1866 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
1867 | break; | |
1868 | } | |
1869 | ||
1870 | if (phy_info[i]) | |
1871 | printk(" -- %s\n", phy_info[i]->name); | |
1872 | else | |
1873 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 1874 | |
1da177e4 LT |
1875 | fep->phy = phy_info[i]; |
1876 | fep->phy_id_done = 1; | |
1877 | } | |
1878 | ||
1879 | /* Scan all of the MII PHY addresses looking for someone to respond | |
1880 | * with a valid ID. This usually happens quickly. | |
1881 | */ | |
1882 | static void | |
1883 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
1884 | { | |
1885 | struct fec_enet_private *fep; | |
1886 | volatile fec_t *fecp; | |
1887 | uint phytype; | |
1888 | ||
1889 | fep = netdev_priv(dev); | |
1890 | fecp = fep->hwp; | |
1891 | ||
1892 | if (fep->phy_addr < 32) { | |
1893 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 1894 | |
1da177e4 LT |
1895 | /* Got first part of ID, now get remainder. |
1896 | */ | |
1897 | fep->phy_id = phytype << 16; | |
1898 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
1899 | mii_discover_phy3); | |
f909b1ef | 1900 | } else { |
1da177e4 LT |
1901 | fep->phy_addr++; |
1902 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
1903 | mii_discover_phy); | |
1904 | } | |
1905 | } else { | |
1906 | printk("FEC: No PHY device found.\n"); | |
1907 | /* Disable external MII interface */ | |
1908 | fecp->fec_mii_speed = fep->phy_speed = 0; | |
1909 | fec_disable_phy_intr(); | |
1910 | } | |
1911 | } | |
1912 | ||
1913 | /* This interrupt occurs when the PHY detects a link change. | |
1914 | */ | |
c1d96156 | 1915 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1916 | static irqreturn_t |
7d12e780 | 1917 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
1918 | { |
1919 | struct net_device *dev = dev_id; | |
1920 | struct fec_enet_private *fep = netdev_priv(dev); | |
1921 | ||
1922 | fec_phy_ack_intr(); | |
1923 | ||
1924 | #if 0 | |
1925 | disable_irq(fep->mii_irq); /* disable now, enable later */ | |
1926 | #endif | |
1927 | ||
1928 | mii_do_cmd(dev, fep->phy->ack_int); | |
1929 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
1930 | ||
1931 | return IRQ_HANDLED; | |
1932 | } | |
c1d96156 | 1933 | #endif |
1da177e4 LT |
1934 | |
1935 | static int | |
1936 | fec_enet_open(struct net_device *dev) | |
1937 | { | |
1938 | struct fec_enet_private *fep = netdev_priv(dev); | |
1939 | ||
1940 | /* I should reset the ring buffers here, but I don't yet know | |
1941 | * a simple way to do that. | |
1942 | */ | |
1943 | fec_set_mac_address(dev); | |
1944 | ||
1945 | fep->sequence_done = 0; | |
1946 | fep->link = 0; | |
1947 | ||
1948 | if (fep->phy) { | |
1949 | mii_do_cmd(dev, fep->phy->ack_int); | |
1950 | mii_do_cmd(dev, fep->phy->config); | |
1951 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
1952 | ||
6b265293 MW |
1953 | /* Poll until the PHY tells us its configuration |
1954 | * (not link state). | |
1955 | * Request is initiated by mii_do_cmd above, but answer | |
1956 | * comes by interrupt. | |
1957 | * This should take about 25 usec per register at 2.5 MHz, | |
1958 | * and we read approximately 5 registers. | |
1da177e4 LT |
1959 | */ |
1960 | while(!fep->sequence_done) | |
1961 | schedule(); | |
1962 | ||
1963 | mii_do_cmd(dev, fep->phy->startup); | |
1964 | ||
1965 | /* Set the initial link state to true. A lot of hardware | |
1966 | * based on this device does not implement a PHY interrupt, | |
1967 | * so we are never notified of link change. | |
1968 | */ | |
1969 | fep->link = 1; | |
1970 | } else { | |
1971 | fep->link = 1; /* lets just try it and see */ | |
1972 | /* no phy, go full duplex, it's most likely a hub chip */ | |
1973 | fec_restart(dev, 1); | |
1974 | } | |
1975 | ||
1976 | netif_start_queue(dev); | |
1977 | fep->opened = 1; | |
1978 | return 0; /* Success */ | |
1979 | } | |
1980 | ||
1981 | static int | |
1982 | fec_enet_close(struct net_device *dev) | |
1983 | { | |
1984 | struct fec_enet_private *fep = netdev_priv(dev); | |
1985 | ||
1986 | /* Don't know what to do yet. | |
1987 | */ | |
1988 | fep->opened = 0; | |
1989 | netif_stop_queue(dev); | |
1990 | fec_stop(dev); | |
1991 | ||
1992 | return 0; | |
1993 | } | |
1994 | ||
1da177e4 LT |
1995 | /* Set or clear the multicast filter for this adaptor. |
1996 | * Skeleton taken from sunlance driver. | |
1997 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1998 | * MAC address filtering. Some of the drivers check to make sure it is | |
1999 | * a group multicast address, and discard those that are not. I guess I | |
2000 | * will do the same for now, but just remove the test if you want | |
2001 | * individual filtering as well (do the upper net layers want or support | |
2002 | * this kind of feature?). | |
2003 | */ | |
2004 | ||
2005 | #define HASH_BITS 6 /* #bits in hash */ | |
2006 | #define CRC32_POLY 0xEDB88320 | |
2007 | ||
2008 | static void set_multicast_list(struct net_device *dev) | |
2009 | { | |
2010 | struct fec_enet_private *fep; | |
2011 | volatile fec_t *ep; | |
2012 | struct dev_mc_list *dmi; | |
2013 | unsigned int i, j, bit, data, crc; | |
2014 | unsigned char hash; | |
2015 | ||
2016 | fep = netdev_priv(dev); | |
2017 | ep = fep->hwp; | |
2018 | ||
2019 | if (dev->flags&IFF_PROMISC) { | |
1da177e4 LT |
2020 | ep->fec_r_cntrl |= 0x0008; |
2021 | } else { | |
2022 | ||
2023 | ep->fec_r_cntrl &= ~0x0008; | |
2024 | ||
2025 | if (dev->flags & IFF_ALLMULTI) { | |
2026 | /* Catch all multicast addresses, so set the | |
2027 | * filter to all 1's. | |
2028 | */ | |
cc462f7d GU |
2029 | ep->fec_grp_hash_table_high = 0xffffffff; |
2030 | ep->fec_grp_hash_table_low = 0xffffffff; | |
1da177e4 LT |
2031 | } else { |
2032 | /* Clear filter and add the addresses in hash register. | |
2033 | */ | |
cc462f7d GU |
2034 | ep->fec_grp_hash_table_high = 0; |
2035 | ep->fec_grp_hash_table_low = 0; | |
6aa20a22 | 2036 | |
1da177e4 LT |
2037 | dmi = dev->mc_list; |
2038 | ||
2039 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) | |
2040 | { | |
2041 | /* Only support group multicast for now. | |
2042 | */ | |
2043 | if (!(dmi->dmi_addr[0] & 1)) | |
2044 | continue; | |
6aa20a22 | 2045 | |
1da177e4 LT |
2046 | /* calculate crc32 value of mac address |
2047 | */ | |
2048 | crc = 0xffffffff; | |
2049 | ||
2050 | for (i = 0; i < dmi->dmi_addrlen; i++) | |
2051 | { | |
2052 | data = dmi->dmi_addr[i]; | |
2053 | for (bit = 0; bit < 8; bit++, data >>= 1) | |
2054 | { | |
2055 | crc = (crc >> 1) ^ | |
2056 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
2057 | } | |
2058 | } | |
2059 | ||
2060 | /* only upper 6 bits (HASH_BITS) are used | |
2061 | which point to specific bit in he hash registers | |
2062 | */ | |
2063 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
6aa20a22 | 2064 | |
1da177e4 | 2065 | if (hash > 31) |
cc462f7d | 2066 | ep->fec_grp_hash_table_high |= 1 << (hash - 32); |
1da177e4 | 2067 | else |
cc462f7d | 2068 | ep->fec_grp_hash_table_low |= 1 << hash; |
1da177e4 LT |
2069 | } |
2070 | } | |
2071 | } | |
2072 | } | |
2073 | ||
2074 | /* Set a MAC change in hardware. | |
2075 | */ | |
2076 | static void | |
2077 | fec_set_mac_address(struct net_device *dev) | |
2078 | { | |
1da177e4 LT |
2079 | volatile fec_t *fecp; |
2080 | ||
7dd6a2aa | 2081 | fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp; |
1da177e4 LT |
2082 | |
2083 | /* Set station address. */ | |
7dd6a2aa GU |
2084 | fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
2085 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24); | |
2086 | fecp->fec_addr_high = (dev->dev_addr[5] << 16) | | |
2087 | (dev->dev_addr[4] << 24); | |
1da177e4 LT |
2088 | |
2089 | } | |
2090 | ||
2091 | /* Initialize the FEC Ethernet on 860T (or ColdFire 5272). | |
2092 | */ | |
2093 | /* | |
2094 | * XXX: We need to clean up on failure exits here. | |
2095 | */ | |
2096 | int __init fec_enet_init(struct net_device *dev) | |
2097 | { | |
2098 | struct fec_enet_private *fep = netdev_priv(dev); | |
2099 | unsigned long mem_addr; | |
2100 | volatile cbd_t *bdp; | |
2101 | cbd_t *cbd_base; | |
2102 | volatile fec_t *fecp; | |
2103 | int i, j; | |
2104 | static int index = 0; | |
2105 | ||
2106 | /* Only allow us to be probed once. */ | |
2107 | if (index >= FEC_MAX_PORTS) | |
2108 | return -ENXIO; | |
2109 | ||
562d2f8c GU |
2110 | /* Allocate memory for buffer descriptors. |
2111 | */ | |
2112 | mem_addr = __get_free_page(GFP_KERNEL); | |
2113 | if (mem_addr == 0) { | |
2114 | printk("FEC: allocate descriptor memory failed?\n"); | |
2115 | return -ENOMEM; | |
2116 | } | |
2117 | ||
3b2b74ca SS |
2118 | spin_lock_init(&fep->hw_lock); |
2119 | spin_lock_init(&fep->mii_lock); | |
2120 | ||
1da177e4 LT |
2121 | /* Create an Ethernet device instance. |
2122 | */ | |
2123 | fecp = (volatile fec_t *) fec_hw[index]; | |
2124 | ||
2125 | fep->index = index; | |
2126 | fep->hwp = fecp; | |
cb84d6e7 | 2127 | fep->netdev = dev; |
1da177e4 LT |
2128 | |
2129 | /* Whack a reset. We should wait for this. | |
2130 | */ | |
2131 | fecp->fec_ecntrl = 1; | |
2132 | udelay(10); | |
2133 | ||
1da177e4 LT |
2134 | /* Set the Ethernet address. If using multiple Enets on the 8xx, |
2135 | * this needs some work to get unique addresses. | |
2136 | * | |
2137 | * This is our default MAC address unless the user changes | |
2138 | * it via eth_mac_addr (our dev->set_mac_addr handler). | |
2139 | */ | |
2140 | fec_get_mac(dev); | |
2141 | ||
1da177e4 LT |
2142 | cbd_base = (cbd_t *)mem_addr; |
2143 | /* XXX: missing check for allocation failure */ | |
2144 | ||
1da177e4 LT |
2145 | /* Set receive and transmit descriptor base. |
2146 | */ | |
2147 | fep->rx_bd_base = cbd_base; | |
2148 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
2149 | ||
2150 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2151 | fep->cur_rx = fep->rx_bd_base; | |
2152 | ||
2153 | fep->skb_cur = fep->skb_dirty = 0; | |
2154 | ||
2155 | /* Initialize the receive buffer descriptors. | |
2156 | */ | |
2157 | bdp = fep->rx_bd_base; | |
2158 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
2159 | ||
2160 | /* Allocate a page. | |
2161 | */ | |
2162 | mem_addr = __get_free_page(GFP_KERNEL); | |
2163 | /* XXX: missing check for allocation failure */ | |
2164 | ||
1da177e4 LT |
2165 | /* Initialize the BD for every fragment in the page. |
2166 | */ | |
2167 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | |
2168 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2169 | bdp->cbd_bufaddr = __pa(mem_addr); | |
2170 | mem_addr += FEC_ENET_RX_FRSIZE; | |
2171 | bdp++; | |
2172 | } | |
2173 | } | |
2174 | ||
2175 | /* Set the last buffer to wrap. | |
2176 | */ | |
2177 | bdp--; | |
2178 | bdp->cbd_sc |= BD_SC_WRAP; | |
2179 | ||
2180 | /* ...and the same for transmmit. | |
2181 | */ | |
2182 | bdp = fep->tx_bd_base; | |
2183 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
2184 | if (j >= FEC_ENET_TX_FRPPG) { | |
2185 | mem_addr = __get_free_page(GFP_KERNEL); | |
2186 | j = 1; | |
2187 | } else { | |
2188 | mem_addr += FEC_ENET_TX_FRSIZE; | |
2189 | j++; | |
2190 | } | |
2191 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
2192 | ||
2193 | /* Initialize the BD for every fragment in the page. | |
2194 | */ | |
2195 | bdp->cbd_sc = 0; | |
2196 | bdp->cbd_bufaddr = 0; | |
2197 | bdp++; | |
2198 | } | |
2199 | ||
2200 | /* Set the last buffer to wrap. | |
2201 | */ | |
2202 | bdp--; | |
2203 | bdp->cbd_sc |= BD_SC_WRAP; | |
2204 | ||
2205 | /* Set receive and transmit descriptor base. | |
2206 | */ | |
2207 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2208 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2209 | ||
2210 | /* Install our interrupt handlers. This varies depending on | |
2211 | * the architecture. | |
2212 | */ | |
2213 | fec_request_intrs(dev); | |
2214 | ||
cc462f7d GU |
2215 | fecp->fec_grp_hash_table_high = 0; |
2216 | fecp->fec_grp_hash_table_low = 0; | |
562d2f8c GU |
2217 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
2218 | fecp->fec_ecntrl = 2; | |
6b265293 | 2219 | fecp->fec_r_des_active = 0; |
cc462f7d GU |
2220 | #ifndef CONFIG_M5272 |
2221 | fecp->fec_hash_table_high = 0; | |
2222 | fecp->fec_hash_table_low = 0; | |
2223 | #endif | |
562d2f8c | 2224 | |
1da177e4 LT |
2225 | dev->base_addr = (unsigned long)fecp; |
2226 | ||
2227 | /* The FEC Ethernet specific entries in the device structure. */ | |
2228 | dev->open = fec_enet_open; | |
2229 | dev->hard_start_xmit = fec_enet_start_xmit; | |
2230 | dev->tx_timeout = fec_timeout; | |
2231 | dev->watchdog_timeo = TX_TIMEOUT; | |
2232 | dev->stop = fec_enet_close; | |
1da177e4 LT |
2233 | dev->set_multicast_list = set_multicast_list; |
2234 | ||
2235 | for (i=0; i<NMII-1; i++) | |
2236 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
2237 | mii_free = mii_cmds; | |
2238 | ||
2239 | /* setup MII interface */ | |
2240 | fec_set_mii(dev, fep); | |
2241 | ||
6b265293 MW |
2242 | /* Clear and enable interrupts */ |
2243 | fecp->fec_ievent = 0xffc00000; | |
398ec922 | 2244 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
6b265293 | 2245 | |
1da177e4 LT |
2246 | /* Queue up command to detect the PHY and initialize the |
2247 | * remainder of the interface. | |
2248 | */ | |
2249 | fep->phy_id_done = 0; | |
2250 | fep->phy_addr = 0; | |
2251 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
2252 | ||
2253 | index++; | |
2254 | return 0; | |
2255 | } | |
2256 | ||
2257 | /* This function is called to start or restart the FEC during a link | |
2258 | * change. This only happens when switching between half and full | |
2259 | * duplex. | |
2260 | */ | |
2261 | static void | |
2262 | fec_restart(struct net_device *dev, int duplex) | |
2263 | { | |
2264 | struct fec_enet_private *fep; | |
2265 | volatile cbd_t *bdp; | |
2266 | volatile fec_t *fecp; | |
2267 | int i; | |
2268 | ||
2269 | fep = netdev_priv(dev); | |
2270 | fecp = fep->hwp; | |
2271 | ||
2272 | /* Whack a reset. We should wait for this. | |
2273 | */ | |
2274 | fecp->fec_ecntrl = 1; | |
2275 | udelay(10); | |
2276 | ||
1da177e4 LT |
2277 | /* Clear any outstanding interrupt. |
2278 | */ | |
7dd6a2aa | 2279 | fecp->fec_ievent = 0xffc00000; |
1da177e4 LT |
2280 | |
2281 | /* Set station address. | |
2282 | */ | |
7dd6a2aa | 2283 | fec_set_mac_address(dev); |
1da177e4 LT |
2284 | |
2285 | /* Reset all multicast. | |
2286 | */ | |
cc462f7d GU |
2287 | fecp->fec_grp_hash_table_high = 0; |
2288 | fecp->fec_grp_hash_table_low = 0; | |
1da177e4 LT |
2289 | |
2290 | /* Set maximum receive buffer size. | |
2291 | */ | |
2292 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; | |
2293 | ||
1da177e4 LT |
2294 | /* Set receive and transmit descriptor base. |
2295 | */ | |
2296 | fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base)); | |
2297 | fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base)); | |
2298 | ||
2299 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
2300 | fep->cur_rx = fep->rx_bd_base; | |
2301 | ||
2302 | /* Reset SKB transmit buffers. | |
2303 | */ | |
2304 | fep->skb_cur = fep->skb_dirty = 0; | |
2305 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | |
2306 | if (fep->tx_skbuff[i] != NULL) { | |
2307 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
2308 | fep->tx_skbuff[i] = NULL; | |
2309 | } | |
2310 | } | |
2311 | ||
2312 | /* Initialize the receive buffer descriptors. | |
2313 | */ | |
2314 | bdp = fep->rx_bd_base; | |
2315 | for (i=0; i<RX_RING_SIZE; i++) { | |
2316 | ||
2317 | /* Initialize the BD for every fragment in the page. | |
2318 | */ | |
2319 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
2320 | bdp++; | |
2321 | } | |
2322 | ||
2323 | /* Set the last buffer to wrap. | |
2324 | */ | |
2325 | bdp--; | |
2326 | bdp->cbd_sc |= BD_SC_WRAP; | |
2327 | ||
2328 | /* ...and the same for transmmit. | |
2329 | */ | |
2330 | bdp = fep->tx_bd_base; | |
2331 | for (i=0; i<TX_RING_SIZE; i++) { | |
2332 | ||
2333 | /* Initialize the BD for every fragment in the page. | |
2334 | */ | |
2335 | bdp->cbd_sc = 0; | |
2336 | bdp->cbd_bufaddr = 0; | |
2337 | bdp++; | |
2338 | } | |
2339 | ||
2340 | /* Set the last buffer to wrap. | |
2341 | */ | |
2342 | bdp--; | |
2343 | bdp->cbd_sc |= BD_SC_WRAP; | |
2344 | ||
2345 | /* Enable MII mode. | |
2346 | */ | |
2347 | if (duplex) { | |
2348 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */ | |
2349 | fecp->fec_x_cntrl = 0x04; /* FD enable */ | |
f909b1ef | 2350 | } else { |
1da177e4 LT |
2351 | /* MII enable|No Rcv on Xmit */ |
2352 | fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06; | |
2353 | fecp->fec_x_cntrl = 0x00; | |
2354 | } | |
2355 | fep->full_duplex = duplex; | |
2356 | ||
2357 | /* Set MII speed. | |
2358 | */ | |
2359 | fecp->fec_mii_speed = fep->phy_speed; | |
2360 | ||
2361 | /* And last, enable the transmit and receive processing. | |
2362 | */ | |
2363 | fecp->fec_ecntrl = 2; | |
6b265293 MW |
2364 | fecp->fec_r_des_active = 0; |
2365 | ||
2366 | /* Enable interrupts we wish to service. | |
2367 | */ | |
398ec922 | 2368 | fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII); |
1da177e4 LT |
2369 | } |
2370 | ||
2371 | static void | |
2372 | fec_stop(struct net_device *dev) | |
2373 | { | |
2374 | volatile fec_t *fecp; | |
2375 | struct fec_enet_private *fep; | |
2376 | ||
2377 | fep = netdev_priv(dev); | |
2378 | fecp = fep->hwp; | |
2379 | ||
677177c5 PDM |
2380 | /* |
2381 | ** We cannot expect a graceful transmit stop without link !!! | |
2382 | */ | |
2383 | if (fep->link) | |
2384 | { | |
2385 | fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */ | |
2386 | udelay(10); | |
2387 | if (!(fecp->fec_ievent & FEC_ENET_GRA)) | |
2388 | printk("fec_stop : Graceful transmit stop did not complete !\n"); | |
2389 | } | |
1da177e4 LT |
2390 | |
2391 | /* Whack a reset. We should wait for this. | |
2392 | */ | |
2393 | fecp->fec_ecntrl = 1; | |
2394 | udelay(10); | |
2395 | ||
2396 | /* Clear outstanding MII command interrupts. | |
2397 | */ | |
2398 | fecp->fec_ievent = FEC_ENET_MII; | |
1da177e4 LT |
2399 | |
2400 | fecp->fec_imask = FEC_ENET_MII; | |
2401 | fecp->fec_mii_speed = fep->phy_speed; | |
2402 | } | |
2403 | ||
2404 | static int __init fec_enet_module_init(void) | |
2405 | { | |
2406 | struct net_device *dev; | |
c1d96156 | 2407 | int i, err; |
7dd6a2aa GU |
2408 | |
2409 | printk("FEC ENET Version 0.2\n"); | |
1da177e4 LT |
2410 | |
2411 | for (i = 0; (i < FEC_MAX_PORTS); i++) { | |
2412 | dev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
2413 | if (!dev) | |
2414 | return -ENOMEM; | |
2415 | err = fec_enet_init(dev); | |
2416 | if (err) { | |
2417 | free_netdev(dev); | |
2418 | continue; | |
2419 | } | |
2420 | if (register_netdev(dev) != 0) { | |
2421 | /* XXX: missing cleanup here */ | |
2422 | free_netdev(dev); | |
2423 | return -EIO; | |
2424 | } | |
7dd6a2aa | 2425 | |
e174961c | 2426 | printk("%s: ethernet %pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
2427 | } |
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | module_init(fec_enet_module_init); | |
2432 | ||
2433 | MODULE_LICENSE("GPL"); |