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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
6f501b17 SH |
39 | #include <linux/io.h> |
40 | #include <linux/irq.h> | |
196719ec | 41 | #include <linux/clk.h> |
ead73183 | 42 | #include <linux/platform_device.h> |
1da177e4 | 43 | |
080853af | 44 | #include <asm/cacheflush.h> |
196719ec SH |
45 | |
46 | #ifndef CONFIG_ARCH_MXC | |
1da177e4 LT |
47 | #include <asm/coldfire.h> |
48 | #include <asm/mcfsim.h> | |
196719ec | 49 | #endif |
6f501b17 | 50 | |
1da177e4 | 51 | #include "fec.h" |
1da177e4 | 52 | |
196719ec SH |
53 | #ifdef CONFIG_ARCH_MXC |
54 | #include <mach/hardware.h> | |
55 | #define FEC_ALIGNMENT 0xf | |
56 | #else | |
57 | #define FEC_ALIGNMENT 0x3 | |
58 | #endif | |
59 | ||
ead73183 SH |
60 | /* |
61 | * Define the fixed address of the FEC hardware. | |
62 | */ | |
87f4abb4 | 63 | #if defined(CONFIG_M5272) |
c1d96156 | 64 | #define HAVE_mii_link_interrupt |
1da177e4 LT |
65 | |
66 | static unsigned char fec_mac_default[] = { | |
67 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
68 | }; | |
69 | ||
70 | /* | |
71 | * Some hardware gets it MAC address out of local flash memory. | |
72 | * if this is non-zero then assume it is the address to get MAC from. | |
73 | */ | |
74 | #if defined(CONFIG_NETtel) | |
75 | #define FEC_FLASHMAC 0xf0006006 | |
76 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
77 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
78 | #elif defined(CONFIG_CANCam) |
79 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
80 | #elif defined (CONFIG_M5272C3) |
81 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
82 | #elif defined(CONFIG_MOD5272) | |
83 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
84 | #else |
85 | #define FEC_FLASHMAC 0 | |
86 | #endif | |
43be6366 | 87 | #endif /* CONFIG_M5272 */ |
ead73183 | 88 | |
1da177e4 LT |
89 | /* Forward declarations of some structures to support different PHYs |
90 | */ | |
91 | ||
92 | typedef struct { | |
93 | uint mii_data; | |
94 | void (*funct)(uint mii_reg, struct net_device *dev); | |
95 | } phy_cmd_t; | |
96 | ||
97 | typedef struct { | |
98 | uint id; | |
99 | char *name; | |
100 | ||
101 | const phy_cmd_t *config; | |
102 | const phy_cmd_t *startup; | |
103 | const phy_cmd_t *ack_int; | |
104 | const phy_cmd_t *shutdown; | |
105 | } phy_info_t; | |
106 | ||
107 | /* The number of Tx and Rx buffers. These are allocated from the page | |
108 | * pool. The code may assume these are power of two, so it it best | |
109 | * to keep them that size. | |
110 | * We don't need to allocate pages for the transmitter. We just use | |
111 | * the skbuffer directly. | |
112 | */ | |
113 | #define FEC_ENET_RX_PAGES 8 | |
114 | #define FEC_ENET_RX_FRSIZE 2048 | |
115 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
116 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
117 | #define FEC_ENET_TX_FRSIZE 2048 | |
118 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
119 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
120 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
121 | ||
562d2f8c | 122 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 123 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
124 | #endif |
125 | ||
1da177e4 LT |
126 | /* Interrupt events/masks. |
127 | */ | |
128 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ | |
129 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
130 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
131 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
132 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
133 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
134 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
135 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
136 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
137 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
138 | ||
139 | /* The FEC stores dest/src/type, data, and checksum for receive packets. | |
140 | */ | |
141 | #define PKT_MAXBUF_SIZE 1518 | |
142 | #define PKT_MINBUF_SIZE 64 | |
143 | #define PKT_MAXBLR_SIZE 1520 | |
144 | ||
145 | ||
146 | /* | |
6b265293 | 147 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
148 | * size bits. Other FEC hardware does not, so we need to take that into |
149 | * account when setting it. | |
150 | */ | |
562d2f8c | 151 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
196719ec | 152 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
1da177e4 LT |
153 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
154 | #else | |
155 | #define OPT_FRAME_SIZE 0 | |
156 | #endif | |
157 | ||
158 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
159 | * tx_bd_base always point to the base of the buffer descriptors. The | |
160 | * cur_rx and cur_tx point to the currently available buffer. | |
161 | * The dirty_tx tracks the current buffer that is being sent by the | |
162 | * controller. The cur_tx and dirty_tx are equal under both completely | |
163 | * empty and completely full conditions. The empty/ready indicator in | |
164 | * the buffer descriptor determines the actual condition. | |
165 | */ | |
166 | struct fec_enet_private { | |
167 | /* Hardware registers of the FEC device */ | |
f44d6305 | 168 | void __iomem *hwp; |
1da177e4 | 169 | |
cb84d6e7 GU |
170 | struct net_device *netdev; |
171 | ||
ead73183 SH |
172 | struct clk *clk; |
173 | ||
1da177e4 LT |
174 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
175 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
176 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
177 | ushort skb_cur; | |
178 | ushort skb_dirty; | |
179 | ||
180 | /* CPM dual port RAM relative addresses. | |
181 | */ | |
4661e75b | 182 | dma_addr_t bd_dma; |
2e28532f SH |
183 | /* Address of Rx and Tx buffers. */ |
184 | struct bufdesc *rx_bd_base; | |
185 | struct bufdesc *tx_bd_base; | |
186 | /* The next free ring entry */ | |
187 | struct bufdesc *cur_rx, *cur_tx; | |
188 | /* The ring entries to be free()ed. */ | |
189 | struct bufdesc *dirty_tx; | |
190 | ||
1da177e4 | 191 | uint tx_full; |
3b2b74ca SS |
192 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
193 | spinlock_t hw_lock; | |
194 | /* hold while accessing the mii_list_t() elements */ | |
195 | spinlock_t mii_lock; | |
1da177e4 LT |
196 | |
197 | uint phy_id; | |
198 | uint phy_id_done; | |
199 | uint phy_status; | |
200 | uint phy_speed; | |
7dd6a2aa | 201 | phy_info_t const *phy; |
1da177e4 LT |
202 | struct work_struct phy_task; |
203 | ||
204 | uint sequence_done; | |
205 | uint mii_phy_task_queued; | |
206 | ||
207 | uint phy_addr; | |
208 | ||
209 | int index; | |
210 | int opened; | |
211 | int link; | |
212 | int old_link; | |
213 | int full_duplex; | |
1da177e4 LT |
214 | }; |
215 | ||
216 | static int fec_enet_open(struct net_device *dev); | |
217 | static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
218 | static void fec_enet_mii(struct net_device *dev); | |
7d12e780 | 219 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
220 | static void fec_enet_tx(struct net_device *dev); |
221 | static void fec_enet_rx(struct net_device *dev); | |
222 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
223 | static void set_multicast_list(struct net_device *dev); |
224 | static void fec_restart(struct net_device *dev, int duplex); | |
225 | static void fec_stop(struct net_device *dev); | |
226 | static void fec_set_mac_address(struct net_device *dev); | |
227 | ||
228 | ||
229 | /* MII processing. We keep this as simple as possible. Requests are | |
230 | * placed on the list (if there is room). When the request is finished | |
231 | * by the MII, an optional function may be called. | |
232 | */ | |
233 | typedef struct mii_list { | |
234 | uint mii_regval; | |
235 | void (*mii_func)(uint val, struct net_device *dev); | |
236 | struct mii_list *mii_next; | |
237 | } mii_list_t; | |
238 | ||
239 | #define NMII 20 | |
7dd6a2aa GU |
240 | static mii_list_t mii_cmds[NMII]; |
241 | static mii_list_t *mii_free; | |
242 | static mii_list_t *mii_head; | |
243 | static mii_list_t *mii_tail; | |
1da177e4 | 244 | |
6aa20a22 | 245 | static int mii_queue(struct net_device *dev, int request, |
1da177e4 LT |
246 | void (*func)(uint, struct net_device *)); |
247 | ||
248 | /* Make MII read/write commands for the FEC. | |
249 | */ | |
250 | #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) | |
251 | #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \ | |
252 | (VAL & 0xffff)) | |
253 | #define mk_mii_end 0 | |
254 | ||
255 | /* Transmitter timeout. | |
256 | */ | |
257 | #define TX_TIMEOUT (2*HZ) | |
258 | ||
259 | /* Register definitions for the PHY. | |
260 | */ | |
261 | ||
262 | #define MII_REG_CR 0 /* Control Register */ | |
263 | #define MII_REG_SR 1 /* Status Register */ | |
264 | #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */ | |
265 | #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */ | |
6aa20a22 | 266 | #define MII_REG_ANAR 4 /* A-N Advertisement Register */ |
1da177e4 LT |
267 | #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */ |
268 | #define MII_REG_ANER 6 /* A-N Expansion Register */ | |
269 | #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */ | |
270 | #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */ | |
271 | ||
272 | /* values for phy_status */ | |
273 | ||
274 | #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */ | |
275 | #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */ | |
276 | #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */ | |
277 | #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */ | |
6aa20a22 | 278 | #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */ |
1da177e4 | 279 | #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */ |
6aa20a22 | 280 | #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */ |
1da177e4 LT |
281 | |
282 | #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */ | |
283 | #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */ | |
284 | #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */ | |
285 | #define PHY_STAT_SPMASK 0xf000 /* mask for speed */ | |
286 | #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */ | |
6aa20a22 | 287 | #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */ |
1da177e4 | 288 | #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
6aa20a22 | 289 | #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */ |
1da177e4 LT |
290 | |
291 | ||
292 | static int | |
293 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
294 | { | |
f44d6305 | 295 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 296 | struct bufdesc *bdp; |
0e702ab3 | 297 | unsigned short status; |
3b2b74ca | 298 | unsigned long flags; |
1da177e4 | 299 | |
1da177e4 LT |
300 | if (!fep->link) { |
301 | /* Link is down or autonegotiation is in progress. */ | |
302 | return 1; | |
303 | } | |
304 | ||
3b2b74ca | 305 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
306 | /* Fill in a Tx ring entry */ |
307 | bdp = fep->cur_tx; | |
308 | ||
0e702ab3 | 309 | status = bdp->cbd_sc; |
1da177e4 | 310 | #ifndef final_version |
0e702ab3 | 311 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
312 | /* Ooops. All transmit buffers are full. Bail out. |
313 | * This should not happen, since dev->tbusy should be set. | |
314 | */ | |
315 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 316 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
317 | return 1; |
318 | } | |
319 | #endif | |
320 | ||
321 | /* Clear all of the status flags. | |
322 | */ | |
0e702ab3 | 323 | status &= ~BD_ENET_TX_STATS; |
1da177e4 LT |
324 | |
325 | /* Set buffer length and buffer pointer. | |
326 | */ | |
327 | bdp->cbd_bufaddr = __pa(skb->data); | |
328 | bdp->cbd_datlen = skb->len; | |
329 | ||
330 | /* | |
331 | * On some FEC implementations data must be aligned on | |
332 | * 4-byte boundaries. Use bounce buffers to copy data | |
333 | * and get it aligned. Ugh. | |
334 | */ | |
196719ec | 335 | if (bdp->cbd_bufaddr & FEC_ALIGNMENT) { |
1da177e4 LT |
336 | unsigned int index; |
337 | index = bdp - fep->tx_bd_base; | |
6989f512 | 338 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
1da177e4 LT |
339 | bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]); |
340 | } | |
341 | ||
342 | /* Save skb pointer. | |
343 | */ | |
344 | fep->tx_skbuff[fep->skb_cur] = skb; | |
345 | ||
09f75cd7 | 346 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 347 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 348 | |
1da177e4 LT |
349 | /* Push the data cache so the CPM does not get stale memory |
350 | * data. | |
351 | */ | |
ccdc4f19 SH |
352 | dma_sync_single(NULL, bdp->cbd_bufaddr, |
353 | bdp->cbd_datlen, DMA_TO_DEVICE); | |
1da177e4 | 354 | |
0e702ab3 GU |
355 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
356 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 LT |
357 | */ |
358 | ||
0e702ab3 | 359 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 360 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 361 | bdp->cbd_sc = status; |
1da177e4 LT |
362 | |
363 | dev->trans_start = jiffies; | |
364 | ||
365 | /* Trigger transmission start */ | |
f44d6305 | 366 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 LT |
367 | |
368 | /* If this was the last BD in the ring, start at the beginning again. | |
369 | */ | |
0e702ab3 | 370 | if (status & BD_ENET_TX_WRAP) { |
1da177e4 LT |
371 | bdp = fep->tx_bd_base; |
372 | } else { | |
373 | bdp++; | |
374 | } | |
375 | ||
376 | if (bdp == fep->dirty_tx) { | |
377 | fep->tx_full = 1; | |
378 | netif_stop_queue(dev); | |
379 | } | |
380 | ||
2e28532f | 381 | fep->cur_tx = bdp; |
1da177e4 | 382 | |
3b2b74ca | 383 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 LT |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static void | |
389 | fec_timeout(struct net_device *dev) | |
390 | { | |
391 | struct fec_enet_private *fep = netdev_priv(dev); | |
392 | ||
393 | printk("%s: transmit timed out.\n", dev->name); | |
09f75cd7 | 394 | dev->stats.tx_errors++; |
1da177e4 LT |
395 | #ifndef final_version |
396 | { | |
397 | int i; | |
2e28532f | 398 | struct bufdesc *bdp; |
1da177e4 LT |
399 | |
400 | printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n", | |
401 | (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "", | |
402 | (unsigned long)fep->dirty_tx, | |
403 | (unsigned long)fep->cur_rx); | |
404 | ||
405 | bdp = fep->tx_bd_base; | |
406 | printk(" tx: %u buffers\n", TX_RING_SIZE); | |
407 | for (i = 0 ; i < TX_RING_SIZE; i++) { | |
6aa20a22 | 408 | printk(" %08x: %04x %04x %08x\n", |
1da177e4 LT |
409 | (uint) bdp, |
410 | bdp->cbd_sc, | |
411 | bdp->cbd_datlen, | |
412 | (int) bdp->cbd_bufaddr); | |
413 | bdp++; | |
414 | } | |
415 | ||
416 | bdp = fep->rx_bd_base; | |
417 | printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE); | |
418 | for (i = 0 ; i < RX_RING_SIZE; i++) { | |
419 | printk(" %08x: %04x %04x %08x\n", | |
420 | (uint) bdp, | |
421 | bdp->cbd_sc, | |
422 | bdp->cbd_datlen, | |
423 | (int) bdp->cbd_bufaddr); | |
424 | bdp++; | |
425 | } | |
426 | } | |
427 | #endif | |
7dd6a2aa | 428 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
429 | netif_wake_queue(dev); |
430 | } | |
431 | ||
432 | /* The interrupt handler. | |
433 | * This is called from the MPC core interrupt. | |
434 | */ | |
435 | static irqreturn_t | |
7d12e780 | 436 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
437 | { |
438 | struct net_device *dev = dev_id; | |
f44d6305 | 439 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 440 | uint int_events; |
3b2b74ca | 441 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 442 | |
f44d6305 | 443 | /* Get the interrupt events that caused us to be here. */ |
3b2b74ca | 444 | do { |
f44d6305 SH |
445 | int_events = readl(fep->hwp + FEC_IEVENT); |
446 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1da177e4 | 447 | |
f44d6305 | 448 | /* Handle receive event in its own function. */ |
1da177e4 | 449 | if (int_events & FEC_ENET_RXF) { |
3b2b74ca | 450 | ret = IRQ_HANDLED; |
1da177e4 LT |
451 | fec_enet_rx(dev); |
452 | } | |
453 | ||
454 | /* Transmit OK, or non-fatal error. Update the buffer | |
f44d6305 SH |
455 | * descriptors. FEC handles all errors, we just discover |
456 | * them as part of the transmit process. | |
457 | */ | |
1da177e4 | 458 | if (int_events & FEC_ENET_TXF) { |
3b2b74ca | 459 | ret = IRQ_HANDLED; |
1da177e4 LT |
460 | fec_enet_tx(dev); |
461 | } | |
462 | ||
463 | if (int_events & FEC_ENET_MII) { | |
3b2b74ca | 464 | ret = IRQ_HANDLED; |
1da177e4 LT |
465 | fec_enet_mii(dev); |
466 | } | |
6aa20a22 | 467 | |
3b2b74ca SS |
468 | } while (int_events); |
469 | ||
470 | return ret; | |
1da177e4 LT |
471 | } |
472 | ||
473 | ||
474 | static void | |
475 | fec_enet_tx(struct net_device *dev) | |
476 | { | |
477 | struct fec_enet_private *fep; | |
2e28532f | 478 | struct bufdesc *bdp; |
0e702ab3 | 479 | unsigned short status; |
1da177e4 LT |
480 | struct sk_buff *skb; |
481 | ||
482 | fep = netdev_priv(dev); | |
3b2b74ca | 483 | spin_lock_irq(&fep->hw_lock); |
1da177e4 LT |
484 | bdp = fep->dirty_tx; |
485 | ||
0e702ab3 | 486 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
1da177e4 LT |
487 | if (bdp == fep->cur_tx && fep->tx_full == 0) break; |
488 | ||
489 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
490 | /* Check for errors. */ | |
0e702ab3 | 491 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
492 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
493 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 494 | dev->stats.tx_errors++; |
0e702ab3 | 495 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 496 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 497 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 498 | dev->stats.tx_window_errors++; |
0e702ab3 | 499 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 500 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 501 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 502 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 503 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 504 | dev->stats.tx_carrier_errors++; |
1da177e4 | 505 | } else { |
09f75cd7 | 506 | dev->stats.tx_packets++; |
1da177e4 LT |
507 | } |
508 | ||
509 | #ifndef final_version | |
0e702ab3 | 510 | if (status & BD_ENET_TX_READY) |
1da177e4 LT |
511 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
512 | #endif | |
513 | /* Deferred means some collisions occurred during transmit, | |
514 | * but we eventually sent the packet OK. | |
515 | */ | |
0e702ab3 | 516 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 517 | dev->stats.collisions++; |
6aa20a22 | 518 | |
1da177e4 LT |
519 | /* Free the sk buffer associated with this last transmit. |
520 | */ | |
521 | dev_kfree_skb_any(skb); | |
522 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
523 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 524 | |
1da177e4 LT |
525 | /* Update pointer to next buffer descriptor to be transmitted. |
526 | */ | |
0e702ab3 | 527 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
528 | bdp = fep->tx_bd_base; |
529 | else | |
530 | bdp++; | |
6aa20a22 | 531 | |
1da177e4 LT |
532 | /* Since we have freed up a buffer, the ring is no longer |
533 | * full. | |
534 | */ | |
535 | if (fep->tx_full) { | |
536 | fep->tx_full = 0; | |
537 | if (netif_queue_stopped(dev)) | |
538 | netif_wake_queue(dev); | |
539 | } | |
540 | } | |
2e28532f | 541 | fep->dirty_tx = bdp; |
3b2b74ca | 542 | spin_unlock_irq(&fep->hw_lock); |
1da177e4 LT |
543 | } |
544 | ||
545 | ||
546 | /* During a receive, the cur_rx points to the current incoming buffer. | |
547 | * When we update through the ring, if the next incoming buffer has | |
548 | * not been given to the system, we just set the empty indicator, | |
549 | * effectively tossing the packet. | |
550 | */ | |
551 | static void | |
552 | fec_enet_rx(struct net_device *dev) | |
553 | { | |
f44d6305 | 554 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 555 | struct bufdesc *bdp; |
0e702ab3 | 556 | unsigned short status; |
1da177e4 LT |
557 | struct sk_buff *skb; |
558 | ushort pkt_len; | |
559 | __u8 *data; | |
6aa20a22 | 560 | |
0e702ab3 GU |
561 | #ifdef CONFIG_M532x |
562 | flush_cache_all(); | |
6aa20a22 | 563 | #endif |
1da177e4 | 564 | |
3b2b74ca SS |
565 | spin_lock_irq(&fep->hw_lock); |
566 | ||
1da177e4 LT |
567 | /* First, grab all of the stats for the incoming packet. |
568 | * These get messed up if we get called due to a busy condition. | |
569 | */ | |
570 | bdp = fep->cur_rx; | |
571 | ||
0e702ab3 | 572 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 LT |
573 | |
574 | #ifndef final_version | |
575 | /* Since we have allocated space to hold a complete frame, | |
576 | * the last indicator should be set. | |
577 | */ | |
0e702ab3 | 578 | if ((status & BD_ENET_RX_LAST) == 0) |
1da177e4 LT |
579 | printk("FEC ENET: rcv is not +last\n"); |
580 | #endif | |
581 | ||
582 | if (!fep->opened) | |
583 | goto rx_processing_done; | |
584 | ||
585 | /* Check for errors. */ | |
0e702ab3 | 586 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | |
1da177e4 | 587 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
09f75cd7 | 588 | dev->stats.rx_errors++; |
0e702ab3 | 589 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
1da177e4 | 590 | /* Frame too long or too short. */ |
09f75cd7 | 591 | dev->stats.rx_length_errors++; |
1da177e4 | 592 | } |
0e702ab3 | 593 | if (status & BD_ENET_RX_NO) /* Frame alignment */ |
09f75cd7 | 594 | dev->stats.rx_frame_errors++; |
0e702ab3 | 595 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
09f75cd7 | 596 | dev->stats.rx_crc_errors++; |
0e702ab3 | 597 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
09f75cd7 | 598 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
599 | } |
600 | ||
601 | /* Report late collisions as a frame error. | |
602 | * On this error, the BD is closed, but we don't know what we | |
603 | * have in the buffer. So, just drop this frame on the floor. | |
604 | */ | |
0e702ab3 | 605 | if (status & BD_ENET_RX_CL) { |
09f75cd7 JG |
606 | dev->stats.rx_errors++; |
607 | dev->stats.rx_frame_errors++; | |
1da177e4 LT |
608 | goto rx_processing_done; |
609 | } | |
610 | ||
611 | /* Process the incoming frame. | |
612 | */ | |
09f75cd7 | 613 | dev->stats.rx_packets++; |
1da177e4 | 614 | pkt_len = bdp->cbd_datlen; |
09f75cd7 | 615 | dev->stats.rx_bytes += pkt_len; |
1da177e4 LT |
616 | data = (__u8*)__va(bdp->cbd_bufaddr); |
617 | ||
ccdc4f19 SH |
618 | dma_sync_single(NULL, (unsigned long)__pa(data), |
619 | pkt_len - 4, DMA_FROM_DEVICE); | |
620 | ||
1da177e4 LT |
621 | /* This does 16 byte alignment, exactly what we need. |
622 | * The packet length includes FCS, but we don't want to | |
623 | * include that when passing upstream as it messes up | |
624 | * bridging applications. | |
625 | */ | |
626 | skb = dev_alloc_skb(pkt_len-4); | |
627 | ||
628 | if (skb == NULL) { | |
629 | printk("%s: Memory squeeze, dropping packet.\n", dev->name); | |
09f75cd7 | 630 | dev->stats.rx_dropped++; |
1da177e4 | 631 | } else { |
1da177e4 | 632 | skb_put(skb,pkt_len-4); /* Make room */ |
8c7b7faa | 633 | skb_copy_to_linear_data(skb, data, pkt_len-4); |
1da177e4 LT |
634 | skb->protocol=eth_type_trans(skb,dev); |
635 | netif_rx(skb); | |
636 | } | |
637 | rx_processing_done: | |
638 | ||
639 | /* Clear the status flags for this buffer. | |
640 | */ | |
0e702ab3 | 641 | status &= ~BD_ENET_RX_STATS; |
1da177e4 LT |
642 | |
643 | /* Mark the buffer empty. | |
644 | */ | |
0e702ab3 GU |
645 | status |= BD_ENET_RX_EMPTY; |
646 | bdp->cbd_sc = status; | |
1da177e4 LT |
647 | |
648 | /* Update BD pointer to next entry. | |
649 | */ | |
0e702ab3 | 650 | if (status & BD_ENET_RX_WRAP) |
1da177e4 LT |
651 | bdp = fep->rx_bd_base; |
652 | else | |
653 | bdp++; | |
6aa20a22 | 654 | |
1da177e4 LT |
655 | #if 1 |
656 | /* Doing this here will keep the FEC running while we process | |
657 | * incoming frames. On a heavily loaded network, we should be | |
658 | * able to keep up at the expense of system resources. | |
659 | */ | |
f44d6305 | 660 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
1da177e4 | 661 | #endif |
0e702ab3 | 662 | } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */ |
2e28532f | 663 | fep->cur_rx = bdp; |
1da177e4 LT |
664 | |
665 | #if 0 | |
666 | /* Doing this here will allow us to process all frames in the | |
667 | * ring before the FEC is allowed to put more there. On a heavily | |
668 | * loaded network, some frames may be lost. Unfortunately, this | |
669 | * increases the interrupt overhead since we can potentially work | |
670 | * our way back to the interrupt return only to come right back | |
671 | * here. | |
672 | */ | |
0e702ab3 | 673 | fecp->fec_r_des_active = 0; |
1da177e4 | 674 | #endif |
3b2b74ca SS |
675 | |
676 | spin_unlock_irq(&fep->hw_lock); | |
1da177e4 LT |
677 | } |
678 | ||
679 | ||
0e702ab3 | 680 | /* called from interrupt context */ |
1da177e4 LT |
681 | static void |
682 | fec_enet_mii(struct net_device *dev) | |
683 | { | |
684 | struct fec_enet_private *fep; | |
1da177e4 | 685 | mii_list_t *mip; |
1da177e4 LT |
686 | |
687 | fep = netdev_priv(dev); | |
3b2b74ca SS |
688 | spin_lock_irq(&fep->mii_lock); |
689 | ||
1da177e4 LT |
690 | if ((mip = mii_head) == NULL) { |
691 | printk("MII and no head!\n"); | |
0e702ab3 | 692 | goto unlock; |
1da177e4 LT |
693 | } |
694 | ||
695 | if (mip->mii_func != NULL) | |
f44d6305 | 696 | (*(mip->mii_func))(readl(fep->hwp + FEC_MII_DATA), dev); |
1da177e4 LT |
697 | |
698 | mii_head = mip->mii_next; | |
699 | mip->mii_next = mii_free; | |
700 | mii_free = mip; | |
701 | ||
702 | if ((mip = mii_head) != NULL) | |
f44d6305 | 703 | writel(mip->mii_regval, fep->hwp + FEC_MII_DATA); |
0e702ab3 GU |
704 | |
705 | unlock: | |
3b2b74ca | 706 | spin_unlock_irq(&fep->mii_lock); |
1da177e4 LT |
707 | } |
708 | ||
709 | static int | |
710 | mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *)) | |
711 | { | |
712 | struct fec_enet_private *fep; | |
713 | unsigned long flags; | |
714 | mii_list_t *mip; | |
715 | int retval; | |
716 | ||
717 | /* Add PHY address to register command. | |
718 | */ | |
719 | fep = netdev_priv(dev); | |
3b2b74ca | 720 | spin_lock_irqsave(&fep->mii_lock, flags); |
1da177e4 | 721 | |
3b2b74ca | 722 | regval |= fep->phy_addr << 23; |
1da177e4 LT |
723 | retval = 0; |
724 | ||
1da177e4 LT |
725 | if ((mip = mii_free) != NULL) { |
726 | mii_free = mip->mii_next; | |
727 | mip->mii_regval = regval; | |
728 | mip->mii_func = func; | |
729 | mip->mii_next = NULL; | |
730 | if (mii_head) { | |
731 | mii_tail->mii_next = mip; | |
732 | mii_tail = mip; | |
f909b1ef | 733 | } else { |
1da177e4 | 734 | mii_head = mii_tail = mip; |
f44d6305 | 735 | writel(regval, fep->hwp + FEC_MII_DATA); |
1da177e4 | 736 | } |
f909b1ef | 737 | } else { |
1da177e4 LT |
738 | retval = 1; |
739 | } | |
740 | ||
3b2b74ca SS |
741 | spin_unlock_irqrestore(&fep->mii_lock, flags); |
742 | return retval; | |
1da177e4 LT |
743 | } |
744 | ||
745 | static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c) | |
746 | { | |
1da177e4 LT |
747 | if(!c) |
748 | return; | |
749 | ||
be6cb66d PDM |
750 | for (; c->mii_data != mk_mii_end; c++) |
751 | mii_queue(dev, c->mii_data, c->funct); | |
1da177e4 LT |
752 | } |
753 | ||
754 | static void mii_parse_sr(uint mii_reg, struct net_device *dev) | |
755 | { | |
756 | struct fec_enet_private *fep = netdev_priv(dev); | |
757 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 758 | uint status; |
1da177e4 | 759 | |
7dd6a2aa | 760 | status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC); |
1da177e4 LT |
761 | |
762 | if (mii_reg & 0x0004) | |
7dd6a2aa | 763 | status |= PHY_STAT_LINK; |
1da177e4 | 764 | if (mii_reg & 0x0010) |
7dd6a2aa | 765 | status |= PHY_STAT_FAULT; |
1da177e4 | 766 | if (mii_reg & 0x0020) |
7dd6a2aa | 767 | status |= PHY_STAT_ANC; |
7dd6a2aa | 768 | *s = status; |
1da177e4 LT |
769 | } |
770 | ||
771 | static void mii_parse_cr(uint mii_reg, struct net_device *dev) | |
772 | { | |
773 | struct fec_enet_private *fep = netdev_priv(dev); | |
774 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 775 | uint status; |
1da177e4 | 776 | |
7dd6a2aa | 777 | status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP); |
1da177e4 LT |
778 | |
779 | if (mii_reg & 0x1000) | |
7dd6a2aa | 780 | status |= PHY_CONF_ANE; |
1da177e4 | 781 | if (mii_reg & 0x4000) |
7dd6a2aa GU |
782 | status |= PHY_CONF_LOOP; |
783 | *s = status; | |
1da177e4 LT |
784 | } |
785 | ||
786 | static void mii_parse_anar(uint mii_reg, struct net_device *dev) | |
787 | { | |
788 | struct fec_enet_private *fep = netdev_priv(dev); | |
789 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 790 | uint status; |
1da177e4 | 791 | |
7dd6a2aa | 792 | status = *s & ~(PHY_CONF_SPMASK); |
1da177e4 LT |
793 | |
794 | if (mii_reg & 0x0020) | |
7dd6a2aa | 795 | status |= PHY_CONF_10HDX; |
1da177e4 | 796 | if (mii_reg & 0x0040) |
7dd6a2aa | 797 | status |= PHY_CONF_10FDX; |
1da177e4 | 798 | if (mii_reg & 0x0080) |
7dd6a2aa | 799 | status |= PHY_CONF_100HDX; |
1da177e4 | 800 | if (mii_reg & 0x00100) |
7dd6a2aa GU |
801 | status |= PHY_CONF_100FDX; |
802 | *s = status; | |
1da177e4 LT |
803 | } |
804 | ||
805 | /* ------------------------------------------------------------------------- */ | |
806 | /* The Level one LXT970 is used by many boards */ | |
807 | ||
808 | #define MII_LXT970_MIRROR 16 /* Mirror register */ | |
809 | #define MII_LXT970_IER 17 /* Interrupt Enable Register */ | |
810 | #define MII_LXT970_ISR 18 /* Interrupt Status Register */ | |
811 | #define MII_LXT970_CONFIG 19 /* Configuration Register */ | |
812 | #define MII_LXT970_CSR 20 /* Chip Status Register */ | |
813 | ||
814 | static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev) | |
815 | { | |
816 | struct fec_enet_private *fep = netdev_priv(dev); | |
817 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 818 | uint status; |
1da177e4 | 819 | |
7dd6a2aa | 820 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
821 | if (mii_reg & 0x0800) { |
822 | if (mii_reg & 0x1000) | |
7dd6a2aa | 823 | status |= PHY_STAT_100FDX; |
1da177e4 | 824 | else |
7dd6a2aa | 825 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
826 | } else { |
827 | if (mii_reg & 0x1000) | |
7dd6a2aa | 828 | status |= PHY_STAT_10FDX; |
1da177e4 | 829 | else |
7dd6a2aa | 830 | status |= PHY_STAT_10HDX; |
1da177e4 | 831 | } |
7dd6a2aa | 832 | *s = status; |
1da177e4 LT |
833 | } |
834 | ||
7dd6a2aa | 835 | static phy_cmd_t const phy_cmd_lxt970_config[] = { |
1da177e4 LT |
836 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
837 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
838 | { mk_mii_end, } | |
7dd6a2aa GU |
839 | }; |
840 | static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
841 | { mk_mii_write(MII_LXT970_IER, 0x0002), NULL }, |
842 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
843 | { mk_mii_end, } | |
7dd6a2aa GU |
844 | }; |
845 | static phy_cmd_t const phy_cmd_lxt970_ack_int[] = { | |
1da177e4 LT |
846 | /* read SR and ISR to acknowledge */ |
847 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
848 | { mk_mii_read(MII_LXT970_ISR), NULL }, | |
849 | ||
850 | /* find out the current status */ | |
851 | { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr }, | |
852 | { mk_mii_end, } | |
7dd6a2aa GU |
853 | }; |
854 | static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
855 | { mk_mii_write(MII_LXT970_IER, 0x0000), NULL }, |
856 | { mk_mii_end, } | |
7dd6a2aa GU |
857 | }; |
858 | static phy_info_t const phy_info_lxt970 = { | |
6aa20a22 | 859 | .id = 0x07810000, |
7dd6a2aa GU |
860 | .name = "LXT970", |
861 | .config = phy_cmd_lxt970_config, | |
862 | .startup = phy_cmd_lxt970_startup, | |
863 | .ack_int = phy_cmd_lxt970_ack_int, | |
864 | .shutdown = phy_cmd_lxt970_shutdown | |
1da177e4 | 865 | }; |
6aa20a22 | 866 | |
1da177e4 LT |
867 | /* ------------------------------------------------------------------------- */ |
868 | /* The Level one LXT971 is used on some of my custom boards */ | |
869 | ||
870 | /* register definitions for the 971 */ | |
871 | ||
872 | #define MII_LXT971_PCR 16 /* Port Control Register */ | |
873 | #define MII_LXT971_SR2 17 /* Status Register 2 */ | |
874 | #define MII_LXT971_IER 18 /* Interrupt Enable Register */ | |
875 | #define MII_LXT971_ISR 19 /* Interrupt Status Register */ | |
876 | #define MII_LXT971_LCR 20 /* LED Control Register */ | |
877 | #define MII_LXT971_TCR 30 /* Transmit Control Register */ | |
878 | ||
6aa20a22 | 879 | /* |
1da177e4 LT |
880 | * I had some nice ideas of running the MDIO faster... |
881 | * The 971 should support 8MHz and I tried it, but things acted really | |
882 | * weird, so 2.5 MHz ought to be enough for anyone... | |
883 | */ | |
884 | ||
885 | static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev) | |
886 | { | |
887 | struct fec_enet_private *fep = netdev_priv(dev); | |
888 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 889 | uint status; |
1da177e4 | 890 | |
7dd6a2aa | 891 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); |
1da177e4 LT |
892 | |
893 | if (mii_reg & 0x0400) { | |
894 | fep->link = 1; | |
7dd6a2aa | 895 | status |= PHY_STAT_LINK; |
1da177e4 LT |
896 | } else { |
897 | fep->link = 0; | |
898 | } | |
899 | if (mii_reg & 0x0080) | |
7dd6a2aa | 900 | status |= PHY_STAT_ANC; |
1da177e4 LT |
901 | if (mii_reg & 0x4000) { |
902 | if (mii_reg & 0x0200) | |
7dd6a2aa | 903 | status |= PHY_STAT_100FDX; |
1da177e4 | 904 | else |
7dd6a2aa | 905 | status |= PHY_STAT_100HDX; |
1da177e4 LT |
906 | } else { |
907 | if (mii_reg & 0x0200) | |
7dd6a2aa | 908 | status |= PHY_STAT_10FDX; |
1da177e4 | 909 | else |
7dd6a2aa | 910 | status |= PHY_STAT_10HDX; |
1da177e4 LT |
911 | } |
912 | if (mii_reg & 0x0008) | |
7dd6a2aa | 913 | status |= PHY_STAT_FAULT; |
1da177e4 | 914 | |
7dd6a2aa GU |
915 | *s = status; |
916 | } | |
6aa20a22 | 917 | |
7dd6a2aa | 918 | static phy_cmd_t const phy_cmd_lxt971_config[] = { |
6aa20a22 | 919 | /* limit to 10MBit because my prototype board |
1da177e4 LT |
920 | * doesn't work with 100. */ |
921 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
922 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
923 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
924 | { mk_mii_end, } | |
7dd6a2aa GU |
925 | }; |
926 | static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
927 | { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL }, |
928 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
929 | { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */ | |
930 | /* Somehow does the 971 tell me that the link is down | |
931 | * the first read after power-up. | |
932 | * read here to get a valid value in ack_int */ | |
6aa20a22 | 933 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 934 | { mk_mii_end, } |
7dd6a2aa GU |
935 | }; |
936 | static phy_cmd_t const phy_cmd_lxt971_ack_int[] = { | |
937 | /* acknowledge the int before reading status ! */ | |
938 | { mk_mii_read(MII_LXT971_ISR), NULL }, | |
1da177e4 LT |
939 | /* find out the current status */ |
940 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
941 | { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 }, | |
1da177e4 | 942 | { mk_mii_end, } |
7dd6a2aa GU |
943 | }; |
944 | static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
945 | { mk_mii_write(MII_LXT971_IER, 0x0000), NULL }, |
946 | { mk_mii_end, } | |
7dd6a2aa GU |
947 | }; |
948 | static phy_info_t const phy_info_lxt971 = { | |
6aa20a22 | 949 | .id = 0x0001378e, |
7dd6a2aa GU |
950 | .name = "LXT971", |
951 | .config = phy_cmd_lxt971_config, | |
952 | .startup = phy_cmd_lxt971_startup, | |
953 | .ack_int = phy_cmd_lxt971_ack_int, | |
954 | .shutdown = phy_cmd_lxt971_shutdown | |
1da177e4 LT |
955 | }; |
956 | ||
957 | /* ------------------------------------------------------------------------- */ | |
958 | /* The Quality Semiconductor QS6612 is used on the RPX CLLF */ | |
959 | ||
960 | /* register definitions */ | |
961 | ||
962 | #define MII_QS6612_MCR 17 /* Mode Control Register */ | |
963 | #define MII_QS6612_FTR 27 /* Factory Test Register */ | |
964 | #define MII_QS6612_MCO 28 /* Misc. Control Register */ | |
965 | #define MII_QS6612_ISR 29 /* Interrupt Source Register */ | |
966 | #define MII_QS6612_IMR 30 /* Interrupt Mask Register */ | |
967 | #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ | |
968 | ||
969 | static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev) | |
970 | { | |
971 | struct fec_enet_private *fep = netdev_priv(dev); | |
972 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 973 | uint status; |
1da177e4 | 974 | |
7dd6a2aa | 975 | status = *s & ~(PHY_STAT_SPMASK); |
1da177e4 LT |
976 | |
977 | switch((mii_reg >> 2) & 7) { | |
7dd6a2aa GU |
978 | case 1: status |= PHY_STAT_10HDX; break; |
979 | case 2: status |= PHY_STAT_100HDX; break; | |
980 | case 5: status |= PHY_STAT_10FDX; break; | |
981 | case 6: status |= PHY_STAT_100FDX; break; | |
1da177e4 LT |
982 | } |
983 | ||
7dd6a2aa GU |
984 | *s = status; |
985 | } | |
986 | ||
987 | static phy_cmd_t const phy_cmd_qs6612_config[] = { | |
6aa20a22 | 988 | /* The PHY powers up isolated on the RPX, |
1da177e4 LT |
989 | * so send a command to allow operation. |
990 | */ | |
991 | { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL }, | |
992 | ||
993 | /* parse cr and anar to get some info */ | |
994 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
995 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
996 | { mk_mii_end, } | |
7dd6a2aa GU |
997 | }; |
998 | static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
999 | { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL }, |
1000 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1001 | { mk_mii_end, } | |
7dd6a2aa GU |
1002 | }; |
1003 | static phy_cmd_t const phy_cmd_qs6612_ack_int[] = { | |
1da177e4 LT |
1004 | /* we need to read ISR, SR and ANER to acknowledge */ |
1005 | { mk_mii_read(MII_QS6612_ISR), NULL }, | |
1006 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1007 | { mk_mii_read(MII_REG_ANER), NULL }, | |
1008 | ||
1009 | /* read pcr to get info */ | |
1010 | { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr }, | |
1011 | { mk_mii_end, } | |
7dd6a2aa GU |
1012 | }; |
1013 | static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1014 | { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL }, |
1015 | { mk_mii_end, } | |
7dd6a2aa GU |
1016 | }; |
1017 | static phy_info_t const phy_info_qs6612 = { | |
6aa20a22 | 1018 | .id = 0x00181440, |
7dd6a2aa GU |
1019 | .name = "QS6612", |
1020 | .config = phy_cmd_qs6612_config, | |
1021 | .startup = phy_cmd_qs6612_startup, | |
1022 | .ack_int = phy_cmd_qs6612_ack_int, | |
1023 | .shutdown = phy_cmd_qs6612_shutdown | |
1da177e4 LT |
1024 | }; |
1025 | ||
1026 | /* ------------------------------------------------------------------------- */ | |
1027 | /* AMD AM79C874 phy */ | |
1028 | ||
1029 | /* register definitions for the 874 */ | |
1030 | ||
1031 | #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */ | |
1032 | #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */ | |
1033 | #define MII_AM79C874_DR 18 /* Diagnostic Register */ | |
1034 | #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */ | |
1035 | #define MII_AM79C874_MCR 21 /* ModeControl Register */ | |
1036 | #define MII_AM79C874_DC 23 /* Disconnect Counter */ | |
1037 | #define MII_AM79C874_REC 24 /* Recieve Error Counter */ | |
1038 | ||
1039 | static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev) | |
1040 | { | |
1041 | struct fec_enet_private *fep = netdev_priv(dev); | |
1042 | volatile uint *s = &(fep->phy_status); | |
7dd6a2aa | 1043 | uint status; |
1da177e4 | 1044 | |
7dd6a2aa | 1045 | status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC); |
1da177e4 LT |
1046 | |
1047 | if (mii_reg & 0x0080) | |
7dd6a2aa | 1048 | status |= PHY_STAT_ANC; |
1da177e4 | 1049 | if (mii_reg & 0x0400) |
7dd6a2aa | 1050 | status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX); |
1da177e4 | 1051 | else |
7dd6a2aa GU |
1052 | status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX); |
1053 | ||
1054 | *s = status; | |
1da177e4 LT |
1055 | } |
1056 | ||
7dd6a2aa | 1057 | static phy_cmd_t const phy_cmd_am79c874_config[] = { |
1da177e4 LT |
1058 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1059 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1060 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1061 | { mk_mii_end, } | |
7dd6a2aa GU |
1062 | }; |
1063 | static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1064 | { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL }, |
1065 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1066 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1067 | { mk_mii_end, } |
7dd6a2aa GU |
1068 | }; |
1069 | static phy_cmd_t const phy_cmd_am79c874_ack_int[] = { | |
1da177e4 LT |
1070 | /* find out the current status */ |
1071 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1072 | { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr }, | |
1073 | /* we only need to read ISR to acknowledge */ | |
1074 | { mk_mii_read(MII_AM79C874_ICSR), NULL }, | |
1075 | { mk_mii_end, } | |
7dd6a2aa GU |
1076 | }; |
1077 | static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1078 | { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL }, |
1079 | { mk_mii_end, } | |
7dd6a2aa GU |
1080 | }; |
1081 | static phy_info_t const phy_info_am79c874 = { | |
1082 | .id = 0x00022561, | |
1083 | .name = "AM79C874", | |
1084 | .config = phy_cmd_am79c874_config, | |
1085 | .startup = phy_cmd_am79c874_startup, | |
1086 | .ack_int = phy_cmd_am79c874_ack_int, | |
1087 | .shutdown = phy_cmd_am79c874_shutdown | |
1da177e4 LT |
1088 | }; |
1089 | ||
7dd6a2aa | 1090 | |
1da177e4 LT |
1091 | /* ------------------------------------------------------------------------- */ |
1092 | /* Kendin KS8721BL phy */ | |
1093 | ||
1094 | /* register definitions for the 8721 */ | |
1095 | ||
1096 | #define MII_KS8721BL_RXERCR 21 | |
43268dce | 1097 | #define MII_KS8721BL_ICSR 27 |
1da177e4 LT |
1098 | #define MII_KS8721BL_PHYCR 31 |
1099 | ||
7dd6a2aa | 1100 | static phy_cmd_t const phy_cmd_ks8721bl_config[] = { |
1da177e4 LT |
1101 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, |
1102 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1103 | { mk_mii_end, } | |
7dd6a2aa GU |
1104 | }; |
1105 | static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */ | |
1da177e4 LT |
1106 | { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, |
1107 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
6aa20a22 | 1108 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, |
1da177e4 | 1109 | { mk_mii_end, } |
7dd6a2aa GU |
1110 | }; |
1111 | static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = { | |
1da177e4 LT |
1112 | /* find out the current status */ |
1113 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1114 | /* we only need to read ISR to acknowledge */ | |
1115 | { mk_mii_read(MII_KS8721BL_ICSR), NULL }, | |
1116 | { mk_mii_end, } | |
7dd6a2aa GU |
1117 | }; |
1118 | static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */ | |
1da177e4 LT |
1119 | { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL }, |
1120 | { mk_mii_end, } | |
7dd6a2aa GU |
1121 | }; |
1122 | static phy_info_t const phy_info_ks8721bl = { | |
6aa20a22 | 1123 | .id = 0x00022161, |
7dd6a2aa GU |
1124 | .name = "KS8721BL", |
1125 | .config = phy_cmd_ks8721bl_config, | |
1126 | .startup = phy_cmd_ks8721bl_startup, | |
1127 | .ack_int = phy_cmd_ks8721bl_ack_int, | |
1128 | .shutdown = phy_cmd_ks8721bl_shutdown | |
1da177e4 LT |
1129 | }; |
1130 | ||
562d2f8c GU |
1131 | /* ------------------------------------------------------------------------- */ |
1132 | /* register definitions for the DP83848 */ | |
1133 | ||
1134 | #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */ | |
1135 | ||
1136 | static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev) | |
1137 | { | |
4cf1653a | 1138 | struct fec_enet_private *fep = netdev_priv(dev); |
562d2f8c GU |
1139 | volatile uint *s = &(fep->phy_status); |
1140 | ||
1141 | *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC); | |
1142 | ||
1143 | /* Link up */ | |
1144 | if (mii_reg & 0x0001) { | |
1145 | fep->link = 1; | |
1146 | *s |= PHY_STAT_LINK; | |
1147 | } else | |
1148 | fep->link = 0; | |
1149 | /* Status of link */ | |
1150 | if (mii_reg & 0x0010) /* Autonegotioation complete */ | |
1151 | *s |= PHY_STAT_ANC; | |
1152 | if (mii_reg & 0x0002) { /* 10MBps? */ | |
1153 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1154 | *s |= PHY_STAT_10FDX; | |
1155 | else | |
1156 | *s |= PHY_STAT_10HDX; | |
1157 | } else { /* 100 Mbps? */ | |
1158 | if (mii_reg & 0x0004) /* Full Duplex? */ | |
1159 | *s |= PHY_STAT_100FDX; | |
1160 | else | |
1161 | *s |= PHY_STAT_100HDX; | |
1162 | } | |
1163 | if (mii_reg & 0x0008) | |
1164 | *s |= PHY_STAT_FAULT; | |
1165 | } | |
1166 | ||
1167 | static phy_info_t phy_info_dp83848= { | |
1168 | 0x020005c9, | |
1169 | "DP83848", | |
1170 | ||
1171 | (const phy_cmd_t []) { /* config */ | |
1172 | { mk_mii_read(MII_REG_CR), mii_parse_cr }, | |
1173 | { mk_mii_read(MII_REG_ANAR), mii_parse_anar }, | |
1174 | { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 }, | |
1175 | { mk_mii_end, } | |
1176 | }, | |
1177 | (const phy_cmd_t []) { /* startup - enable interrupts */ | |
1178 | { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */ | |
1179 | { mk_mii_read(MII_REG_SR), mii_parse_sr }, | |
1180 | { mk_mii_end, } | |
1181 | }, | |
1182 | (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */ | |
1183 | { mk_mii_end, } | |
1184 | }, | |
1185 | (const phy_cmd_t []) { /* shutdown */ | |
1186 | { mk_mii_end, } | |
1187 | }, | |
1188 | }; | |
1189 | ||
1da177e4 LT |
1190 | /* ------------------------------------------------------------------------- */ |
1191 | ||
7dd6a2aa | 1192 | static phy_info_t const * const phy_info[] = { |
1da177e4 LT |
1193 | &phy_info_lxt970, |
1194 | &phy_info_lxt971, | |
1195 | &phy_info_qs6612, | |
1196 | &phy_info_am79c874, | |
1197 | &phy_info_ks8721bl, | |
562d2f8c | 1198 | &phy_info_dp83848, |
1da177e4 LT |
1199 | NULL |
1200 | }; | |
1201 | ||
1202 | /* ------------------------------------------------------------------------- */ | |
c1d96156 | 1203 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1204 | static irqreturn_t |
7d12e780 | 1205 | mii_link_interrupt(int irq, void * dev_id); |
1da177e4 | 1206 | |
1da177e4 | 1207 | /* |
43be6366 | 1208 | * This is specific to the MII interrupt setup of the M5272EVB. |
1da177e4 | 1209 | */ |
43be6366 | 1210 | static void __inline__ fec_request_mii_intr(struct net_device *dev) |
1da177e4 | 1211 | { |
43be6366 GU |
1212 | if (request_irq(66, mii_link_interrupt, IRQF_DISABLED, "fec(MII)", dev) != 0) |
1213 | printk("FEC: Could not allocate fec(MII) IRQ(66)!\n"); | |
1da177e4 LT |
1214 | } |
1215 | ||
1da177e4 LT |
1216 | static void __inline__ fec_disable_phy_intr(void) |
1217 | { | |
1218 | volatile unsigned long *icrp; | |
1219 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1220 | *icrp = 0x08000000; |
1da177e4 LT |
1221 | } |
1222 | ||
1223 | static void __inline__ fec_phy_ack_intr(void) | |
1224 | { | |
1225 | volatile unsigned long *icrp; | |
1226 | /* Acknowledge the interrupt */ | |
1227 | icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); | |
f861d62e | 1228 | *icrp = 0x0d000000; |
1da177e4 LT |
1229 | } |
1230 | ||
43be6366 | 1231 | #ifdef CONFIG_M5272 |
562d2f8c GU |
1232 | static void __inline__ fec_get_mac(struct net_device *dev) |
1233 | { | |
1234 | struct fec_enet_private *fep = netdev_priv(dev); | |
562d2f8c GU |
1235 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1236 | ||
562d2f8c GU |
1237 | if (FEC_FLASHMAC) { |
1238 | /* | |
1239 | * Get MAC address from FLASH. | |
1240 | * If it is all 1's or 0's, use the default. | |
1241 | */ | |
43be6366 | 1242 | iap = (unsigned char *)FEC_FLASHMAC; |
6b265293 MW |
1243 | if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && |
1244 | (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) | |
1245 | iap = fec_mac_default; | |
1246 | if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && | |
1247 | (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) | |
1248 | iap = fec_mac_default; | |
1249 | } else { | |
f44d6305 SH |
1250 | *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); |
1251 | *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
6b265293 MW |
1252 | iap = &tmpaddr[0]; |
1253 | } | |
1254 | ||
1255 | memcpy(dev->dev_addr, iap, ETH_ALEN); | |
1256 | ||
1257 | /* Adjust MAC if using default MAC address */ | |
1258 | if (iap == fec_mac_default) | |
43be6366 | 1259 | dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; |
6b265293 | 1260 | } |
1da177e4 LT |
1261 | #endif |
1262 | ||
1263 | /* ------------------------------------------------------------------------- */ | |
1264 | ||
1265 | static void mii_display_status(struct net_device *dev) | |
1266 | { | |
1267 | struct fec_enet_private *fep = netdev_priv(dev); | |
1268 | volatile uint *s = &(fep->phy_status); | |
1269 | ||
1270 | if (!fep->link && !fep->old_link) { | |
1271 | /* Link is still down - don't print anything */ | |
1272 | return; | |
1273 | } | |
1274 | ||
1275 | printk("%s: status: ", dev->name); | |
1276 | ||
1277 | if (!fep->link) { | |
1278 | printk("link down"); | |
1279 | } else { | |
1280 | printk("link up"); | |
1281 | ||
1282 | switch(*s & PHY_STAT_SPMASK) { | |
1283 | case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break; | |
1284 | case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break; | |
1285 | case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break; | |
1286 | case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break; | |
1287 | default: | |
1288 | printk(", Unknown speed/duplex"); | |
1289 | } | |
1290 | ||
1291 | if (*s & PHY_STAT_ANC) | |
1292 | printk(", auto-negotiation complete"); | |
1293 | } | |
1294 | ||
1295 | if (*s & PHY_STAT_FAULT) | |
1296 | printk(", remote fault"); | |
1297 | ||
1298 | printk(".\n"); | |
1299 | } | |
1300 | ||
cb84d6e7 | 1301 | static void mii_display_config(struct work_struct *work) |
1da177e4 | 1302 | { |
cb84d6e7 GU |
1303 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1304 | struct net_device *dev = fep->netdev; | |
7dd6a2aa | 1305 | uint status = fep->phy_status; |
1da177e4 LT |
1306 | |
1307 | /* | |
1308 | ** When we get here, phy_task is already removed from | |
1309 | ** the workqueue. It is thus safe to allow to reuse it. | |
1310 | */ | |
1311 | fep->mii_phy_task_queued = 0; | |
1312 | printk("%s: config: auto-negotiation ", dev->name); | |
1313 | ||
7dd6a2aa | 1314 | if (status & PHY_CONF_ANE) |
1da177e4 LT |
1315 | printk("on"); |
1316 | else | |
1317 | printk("off"); | |
1318 | ||
7dd6a2aa | 1319 | if (status & PHY_CONF_100FDX) |
1da177e4 | 1320 | printk(", 100FDX"); |
7dd6a2aa | 1321 | if (status & PHY_CONF_100HDX) |
1da177e4 | 1322 | printk(", 100HDX"); |
7dd6a2aa | 1323 | if (status & PHY_CONF_10FDX) |
1da177e4 | 1324 | printk(", 10FDX"); |
7dd6a2aa | 1325 | if (status & PHY_CONF_10HDX) |
1da177e4 | 1326 | printk(", 10HDX"); |
7dd6a2aa | 1327 | if (!(status & PHY_CONF_SPMASK)) |
1da177e4 LT |
1328 | printk(", No speed/duplex selected?"); |
1329 | ||
7dd6a2aa | 1330 | if (status & PHY_CONF_LOOP) |
1da177e4 | 1331 | printk(", loopback enabled"); |
6aa20a22 | 1332 | |
1da177e4 LT |
1333 | printk(".\n"); |
1334 | ||
1335 | fep->sequence_done = 1; | |
1336 | } | |
1337 | ||
cb84d6e7 | 1338 | static void mii_relink(struct work_struct *work) |
1da177e4 | 1339 | { |
cb84d6e7 GU |
1340 | struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task); |
1341 | struct net_device *dev = fep->netdev; | |
1da177e4 LT |
1342 | int duplex; |
1343 | ||
1344 | /* | |
1345 | ** When we get here, phy_task is already removed from | |
1346 | ** the workqueue. It is thus safe to allow to reuse it. | |
1347 | */ | |
1348 | fep->mii_phy_task_queued = 0; | |
1349 | fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0; | |
1350 | mii_display_status(dev); | |
1351 | fep->old_link = fep->link; | |
1352 | ||
1353 | if (fep->link) { | |
1354 | duplex = 0; | |
6aa20a22 | 1355 | if (fep->phy_status |
1da177e4 LT |
1356 | & (PHY_STAT_100FDX | PHY_STAT_10FDX)) |
1357 | duplex = 1; | |
1358 | fec_restart(dev, duplex); | |
f909b1ef | 1359 | } else |
1da177e4 LT |
1360 | fec_stop(dev); |
1361 | ||
1362 | #if 0 | |
1363 | enable_irq(fep->mii_irq); | |
1364 | #endif | |
1365 | ||
1366 | } | |
1367 | ||
1368 | /* mii_queue_relink is called in interrupt context from mii_link_interrupt */ | |
1369 | static void mii_queue_relink(uint mii_reg, struct net_device *dev) | |
1370 | { | |
1371 | struct fec_enet_private *fep = netdev_priv(dev); | |
1372 | ||
1373 | /* | |
1374 | ** We cannot queue phy_task twice in the workqueue. It | |
1375 | ** would cause an endless loop in the workqueue. | |
1376 | ** Fortunately, if the last mii_relink entry has not yet been | |
1377 | ** executed now, it will do the job for the current interrupt, | |
1378 | ** which is just what we want. | |
1379 | */ | |
1380 | if (fep->mii_phy_task_queued) | |
1381 | return; | |
1382 | ||
1383 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1384 | INIT_WORK(&fep->phy_task, mii_relink); |
1da177e4 LT |
1385 | schedule_work(&fep->phy_task); |
1386 | } | |
1387 | ||
7dd6a2aa | 1388 | /* mii_queue_config is called in interrupt context from fec_enet_mii */ |
1da177e4 LT |
1389 | static void mii_queue_config(uint mii_reg, struct net_device *dev) |
1390 | { | |
1391 | struct fec_enet_private *fep = netdev_priv(dev); | |
1392 | ||
1393 | if (fep->mii_phy_task_queued) | |
1394 | return; | |
1395 | ||
1396 | fep->mii_phy_task_queued = 1; | |
cb84d6e7 | 1397 | INIT_WORK(&fep->phy_task, mii_display_config); |
1da177e4 LT |
1398 | schedule_work(&fep->phy_task); |
1399 | } | |
1400 | ||
7dd6a2aa GU |
1401 | phy_cmd_t const phy_cmd_relink[] = { |
1402 | { mk_mii_read(MII_REG_CR), mii_queue_relink }, | |
1403 | { mk_mii_end, } | |
1404 | }; | |
1405 | phy_cmd_t const phy_cmd_config[] = { | |
1406 | { mk_mii_read(MII_REG_CR), mii_queue_config }, | |
1407 | { mk_mii_end, } | |
1408 | }; | |
1da177e4 LT |
1409 | |
1410 | /* Read remainder of PHY ID. | |
1411 | */ | |
1412 | static void | |
1413 | mii_discover_phy3(uint mii_reg, struct net_device *dev) | |
1414 | { | |
1415 | struct fec_enet_private *fep; | |
1416 | int i; | |
1417 | ||
1418 | fep = netdev_priv(dev); | |
1419 | fep->phy_id |= (mii_reg & 0xffff); | |
1420 | printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id); | |
1421 | ||
1422 | for(i = 0; phy_info[i]; i++) { | |
1423 | if(phy_info[i]->id == (fep->phy_id >> 4)) | |
1424 | break; | |
1425 | } | |
1426 | ||
1427 | if (phy_info[i]) | |
1428 | printk(" -- %s\n", phy_info[i]->name); | |
1429 | else | |
1430 | printk(" -- unknown PHY!\n"); | |
6aa20a22 | 1431 | |
1da177e4 LT |
1432 | fep->phy = phy_info[i]; |
1433 | fep->phy_id_done = 1; | |
1434 | } | |
1435 | ||
1436 | /* Scan all of the MII PHY addresses looking for someone to respond | |
1437 | * with a valid ID. This usually happens quickly. | |
1438 | */ | |
1439 | static void | |
1440 | mii_discover_phy(uint mii_reg, struct net_device *dev) | |
1441 | { | |
1442 | struct fec_enet_private *fep; | |
1da177e4 LT |
1443 | uint phytype; |
1444 | ||
1445 | fep = netdev_priv(dev); | |
1da177e4 LT |
1446 | |
1447 | if (fep->phy_addr < 32) { | |
1448 | if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) { | |
6aa20a22 | 1449 | |
1da177e4 LT |
1450 | /* Got first part of ID, now get remainder. |
1451 | */ | |
1452 | fep->phy_id = phytype << 16; | |
1453 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), | |
1454 | mii_discover_phy3); | |
f909b1ef | 1455 | } else { |
1da177e4 LT |
1456 | fep->phy_addr++; |
1457 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), | |
1458 | mii_discover_phy); | |
1459 | } | |
1460 | } else { | |
1461 | printk("FEC: No PHY device found.\n"); | |
1462 | /* Disable external MII interface */ | |
f44d6305 SH |
1463 | writel(0, fep->hwp + FEC_MII_SPEED); |
1464 | fep->phy_speed = 0; | |
43be6366 | 1465 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1466 | fec_disable_phy_intr(); |
ead73183 | 1467 | #endif |
1da177e4 LT |
1468 | } |
1469 | } | |
1470 | ||
1471 | /* This interrupt occurs when the PHY detects a link change. | |
1472 | */ | |
c1d96156 | 1473 | #ifdef HAVE_mii_link_interrupt |
1da177e4 | 1474 | static irqreturn_t |
7d12e780 | 1475 | mii_link_interrupt(int irq, void * dev_id) |
1da177e4 LT |
1476 | { |
1477 | struct net_device *dev = dev_id; | |
1478 | struct fec_enet_private *fep = netdev_priv(dev); | |
1479 | ||
1480 | fec_phy_ack_intr(); | |
1481 | ||
1482 | #if 0 | |
1483 | disable_irq(fep->mii_irq); /* disable now, enable later */ | |
1484 | #endif | |
1485 | ||
1486 | mii_do_cmd(dev, fep->phy->ack_int); | |
1487 | mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ | |
1488 | ||
1489 | return IRQ_HANDLED; | |
1490 | } | |
c1d96156 | 1491 | #endif |
1da177e4 LT |
1492 | |
1493 | static int | |
1494 | fec_enet_open(struct net_device *dev) | |
1495 | { | |
1496 | struct fec_enet_private *fep = netdev_priv(dev); | |
1497 | ||
1498 | /* I should reset the ring buffers here, but I don't yet know | |
1499 | * a simple way to do that. | |
1500 | */ | |
1501 | fec_set_mac_address(dev); | |
1502 | ||
1503 | fep->sequence_done = 0; | |
1504 | fep->link = 0; | |
1505 | ||
1506 | if (fep->phy) { | |
1507 | mii_do_cmd(dev, fep->phy->ack_int); | |
1508 | mii_do_cmd(dev, fep->phy->config); | |
1509 | mii_do_cmd(dev, phy_cmd_config); /* display configuration */ | |
1510 | ||
6b265293 MW |
1511 | /* Poll until the PHY tells us its configuration |
1512 | * (not link state). | |
1513 | * Request is initiated by mii_do_cmd above, but answer | |
1514 | * comes by interrupt. | |
1515 | * This should take about 25 usec per register at 2.5 MHz, | |
1516 | * and we read approximately 5 registers. | |
1da177e4 LT |
1517 | */ |
1518 | while(!fep->sequence_done) | |
1519 | schedule(); | |
1520 | ||
1521 | mii_do_cmd(dev, fep->phy->startup); | |
1522 | ||
1523 | /* Set the initial link state to true. A lot of hardware | |
1524 | * based on this device does not implement a PHY interrupt, | |
1525 | * so we are never notified of link change. | |
1526 | */ | |
1527 | fep->link = 1; | |
1528 | } else { | |
1529 | fep->link = 1; /* lets just try it and see */ | |
1530 | /* no phy, go full duplex, it's most likely a hub chip */ | |
1531 | fec_restart(dev, 1); | |
1532 | } | |
1533 | ||
1534 | netif_start_queue(dev); | |
1535 | fep->opened = 1; | |
1536 | return 0; /* Success */ | |
1537 | } | |
1538 | ||
1539 | static int | |
1540 | fec_enet_close(struct net_device *dev) | |
1541 | { | |
1542 | struct fec_enet_private *fep = netdev_priv(dev); | |
1543 | ||
1544 | /* Don't know what to do yet. | |
1545 | */ | |
1546 | fep->opened = 0; | |
1547 | netif_stop_queue(dev); | |
1548 | fec_stop(dev); | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
1da177e4 LT |
1553 | /* Set or clear the multicast filter for this adaptor. |
1554 | * Skeleton taken from sunlance driver. | |
1555 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1556 | * MAC address filtering. Some of the drivers check to make sure it is | |
1557 | * a group multicast address, and discard those that are not. I guess I | |
1558 | * will do the same for now, but just remove the test if you want | |
1559 | * individual filtering as well (do the upper net layers want or support | |
1560 | * this kind of feature?). | |
1561 | */ | |
1562 | ||
1563 | #define HASH_BITS 6 /* #bits in hash */ | |
1564 | #define CRC32_POLY 0xEDB88320 | |
1565 | ||
1566 | static void set_multicast_list(struct net_device *dev) | |
1567 | { | |
f44d6305 | 1568 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1569 | struct dev_mc_list *dmi; |
f44d6305 | 1570 | unsigned int i, j, bit, data, crc, tmp; |
1da177e4 LT |
1571 | unsigned char hash; |
1572 | ||
1da177e4 | 1573 | if (dev->flags&IFF_PROMISC) { |
f44d6305 SH |
1574 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1575 | tmp |= 0x8; | |
1576 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1da177e4 | 1577 | } else { |
f44d6305 SH |
1578 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1579 | tmp &= ~0x8; | |
1580 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1da177e4 LT |
1581 | |
1582 | if (dev->flags & IFF_ALLMULTI) { | |
1583 | /* Catch all multicast addresses, so set the | |
1584 | * filter to all 1's. | |
1585 | */ | |
f44d6305 SH |
1586 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1587 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1da177e4 LT |
1588 | } else { |
1589 | /* Clear filter and add the addresses in hash register. | |
1590 | */ | |
f44d6305 SH |
1591 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1592 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
6aa20a22 | 1593 | |
1da177e4 LT |
1594 | dmi = dev->mc_list; |
1595 | ||
1596 | for (j = 0; j < dev->mc_count; j++, dmi = dmi->next) | |
1597 | { | |
1598 | /* Only support group multicast for now. | |
1599 | */ | |
1600 | if (!(dmi->dmi_addr[0] & 1)) | |
1601 | continue; | |
6aa20a22 | 1602 | |
1da177e4 LT |
1603 | /* calculate crc32 value of mac address |
1604 | */ | |
1605 | crc = 0xffffffff; | |
1606 | ||
1607 | for (i = 0; i < dmi->dmi_addrlen; i++) | |
1608 | { | |
1609 | data = dmi->dmi_addr[i]; | |
1610 | for (bit = 0; bit < 8; bit++, data >>= 1) | |
1611 | { | |
1612 | crc = (crc >> 1) ^ | |
1613 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | /* only upper 6 bits (HASH_BITS) are used | |
1618 | which point to specific bit in he hash registers | |
1619 | */ | |
1620 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
6aa20a22 | 1621 | |
f44d6305 SH |
1622 | if (hash > 31) { |
1623 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1624 | tmp |= 1 << (hash - 32); | |
1625 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1626 | } else { | |
1627 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1628 | tmp |= 1 << hash; | |
1629 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1630 | } | |
1da177e4 LT |
1631 | } |
1632 | } | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | /* Set a MAC change in hardware. | |
1637 | */ | |
1638 | static void | |
1639 | fec_set_mac_address(struct net_device *dev) | |
1640 | { | |
f44d6305 | 1641 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 LT |
1642 | |
1643 | /* Set station address. */ | |
f44d6305 SH |
1644 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1645 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), | |
1646 | fep->hwp + FEC_ADDR_LOW); | |
1647 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), | |
1648 | fep + FEC_ADDR_HIGH); | |
1da177e4 LT |
1649 | } |
1650 | ||
1da177e4 LT |
1651 | /* |
1652 | * XXX: We need to clean up on failure exits here. | |
ead73183 SH |
1653 | * |
1654 | * index is only used in legacy code | |
1da177e4 | 1655 | */ |
ead73183 | 1656 | int __init fec_enet_init(struct net_device *dev, int index) |
1da177e4 LT |
1657 | { |
1658 | struct fec_enet_private *fep = netdev_priv(dev); | |
1659 | unsigned long mem_addr; | |
2e28532f | 1660 | struct bufdesc *bdp, *cbd_base; |
1da177e4 | 1661 | int i, j; |
1da177e4 | 1662 | |
8d4dd5cf SH |
1663 | /* Allocate memory for buffer descriptors. */ |
1664 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1665 | GFP_KERNEL); | |
1666 | if (!cbd_base) { | |
562d2f8c GU |
1667 | printk("FEC: allocate descriptor memory failed?\n"); |
1668 | return -ENOMEM; | |
1669 | } | |
1670 | ||
3b2b74ca SS |
1671 | spin_lock_init(&fep->hw_lock); |
1672 | spin_lock_init(&fep->mii_lock); | |
1673 | ||
1da177e4 | 1674 | fep->index = index; |
f44d6305 | 1675 | fep->hwp = (void __iomem *)dev->base_addr; |
cb84d6e7 | 1676 | fep->netdev = dev; |
1da177e4 LT |
1677 | |
1678 | /* Whack a reset. We should wait for this. | |
1679 | */ | |
f44d6305 | 1680 | writel(1, fep->hwp + FEC_ECNTRL); |
1da177e4 LT |
1681 | udelay(10); |
1682 | ||
ead73183 | 1683 | /* Set the Ethernet address */ |
43be6366 | 1684 | #ifdef CONFIG_M5272 |
1da177e4 | 1685 | fec_get_mac(dev); |
ead73183 SH |
1686 | #else |
1687 | { | |
1688 | unsigned long l; | |
f44d6305 | 1689 | l = readl(fep->hwp + FEC_ADDR_LOW); |
ead73183 SH |
1690 | dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); |
1691 | dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1692 | dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); | |
1693 | dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); | |
f44d6305 | 1694 | l = readl(fep->hwp + FEC_ADDR_HIGH); |
ead73183 SH |
1695 | dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); |
1696 | dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); | |
1697 | } | |
1698 | #endif | |
1da177e4 | 1699 | |
8d4dd5cf | 1700 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1701 | fep->rx_bd_base = cbd_base; |
1702 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1703 | ||
1704 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1705 | fep->cur_rx = fep->rx_bd_base; | |
1706 | ||
1707 | fep->skb_cur = fep->skb_dirty = 0; | |
1708 | ||
1709 | /* Initialize the receive buffer descriptors. | |
1710 | */ | |
1711 | bdp = fep->rx_bd_base; | |
1712 | for (i=0; i<FEC_ENET_RX_PAGES; i++) { | |
1713 | ||
1714 | /* Allocate a page. | |
1715 | */ | |
1716 | mem_addr = __get_free_page(GFP_KERNEL); | |
1717 | /* XXX: missing check for allocation failure */ | |
1718 | ||
1da177e4 LT |
1719 | /* Initialize the BD for every fragment in the page. |
1720 | */ | |
1721 | for (j=0; j<FEC_ENET_RX_FRPPG; j++) { | |
1722 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
1723 | bdp->cbd_bufaddr = __pa(mem_addr); | |
1724 | mem_addr += FEC_ENET_RX_FRSIZE; | |
1725 | bdp++; | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | /* Set the last buffer to wrap. | |
1730 | */ | |
1731 | bdp--; | |
1732 | bdp->cbd_sc |= BD_SC_WRAP; | |
1733 | ||
1734 | /* ...and the same for transmmit. | |
1735 | */ | |
1736 | bdp = fep->tx_bd_base; | |
1737 | for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) { | |
1738 | if (j >= FEC_ENET_TX_FRPPG) { | |
1739 | mem_addr = __get_free_page(GFP_KERNEL); | |
1740 | j = 1; | |
1741 | } else { | |
1742 | mem_addr += FEC_ENET_TX_FRSIZE; | |
1743 | j++; | |
1744 | } | |
1745 | fep->tx_bounce[i] = (unsigned char *) mem_addr; | |
1746 | ||
1747 | /* Initialize the BD for every fragment in the page. | |
1748 | */ | |
1749 | bdp->cbd_sc = 0; | |
1750 | bdp->cbd_bufaddr = 0; | |
1751 | bdp++; | |
1752 | } | |
1753 | ||
1754 | /* Set the last buffer to wrap. | |
1755 | */ | |
1756 | bdp--; | |
1757 | bdp->cbd_sc |= BD_SC_WRAP; | |
1758 | ||
1759 | /* Set receive and transmit descriptor base. | |
1760 | */ | |
f44d6305 | 1761 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); |
2e28532f | 1762 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1763 | fep->hwp + FEC_X_DES_START); |
1da177e4 | 1764 | |
43be6366 GU |
1765 | #ifdef HAVE_mii_link_interrupt |
1766 | fec_request_mii_intr(dev); | |
ead73183 | 1767 | #endif |
1da177e4 | 1768 | |
f44d6305 SH |
1769 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); |
1770 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1771 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1772 | writel(2, fep->hwp + FEC_ECNTRL); | |
1773 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
cc462f7d | 1774 | #ifndef CONFIG_M5272 |
f44d6305 SH |
1775 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); |
1776 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
cc462f7d | 1777 | #endif |
562d2f8c | 1778 | |
1da177e4 LT |
1779 | /* The FEC Ethernet specific entries in the device structure. */ |
1780 | dev->open = fec_enet_open; | |
1781 | dev->hard_start_xmit = fec_enet_start_xmit; | |
1782 | dev->tx_timeout = fec_timeout; | |
1783 | dev->watchdog_timeo = TX_TIMEOUT; | |
1784 | dev->stop = fec_enet_close; | |
1da177e4 LT |
1785 | dev->set_multicast_list = set_multicast_list; |
1786 | ||
1787 | for (i=0; i<NMII-1; i++) | |
1788 | mii_cmds[i].mii_next = &mii_cmds[i+1]; | |
1789 | mii_free = mii_cmds; | |
1790 | ||
1791 | /* setup MII interface */ | |
f44d6305 SH |
1792 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); |
1793 | writel(0, fep->hwp + FEC_X_CNTRL); | |
ead73183 SH |
1794 | |
1795 | /* | |
1796 | * Set MII speed to 2.5 MHz | |
1797 | */ | |
1798 | fep->phy_speed = ((((clk_get_rate(fep->clk) / 2 + 4999999) | |
1799 | / 2500000) / 2) & 0x3F) << 1; | |
f44d6305 | 1800 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
ead73183 | 1801 | fec_restart(dev, 0); |
1da177e4 | 1802 | |
6b265293 | 1803 | /* Clear and enable interrupts */ |
f44d6305 SH |
1804 | writel(0xffc00000, fep->hwp + FEC_IEVENT); |
1805 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, | |
1806 | fep->hwp + FEC_IMASK); | |
6b265293 | 1807 | |
1da177e4 LT |
1808 | /* Queue up command to detect the PHY and initialize the |
1809 | * remainder of the interface. | |
1810 | */ | |
1811 | fep->phy_id_done = 0; | |
1812 | fep->phy_addr = 0; | |
1813 | mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy); | |
1814 | ||
1da177e4 LT |
1815 | return 0; |
1816 | } | |
1817 | ||
1818 | /* This function is called to start or restart the FEC during a link | |
1819 | * change. This only happens when switching between half and full | |
1820 | * duplex. | |
1821 | */ | |
1822 | static void | |
1823 | fec_restart(struct net_device *dev, int duplex) | |
1824 | { | |
f44d6305 | 1825 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 1826 | struct bufdesc *bdp; |
1da177e4 LT |
1827 | int i; |
1828 | ||
f44d6305 SH |
1829 | /* Whack a reset. We should wait for this. */ |
1830 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1831 | udelay(10); |
1832 | ||
f44d6305 SH |
1833 | /* Clear any outstanding interrupt. */ |
1834 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1835 | |
f44d6305 | 1836 | /* Set station address. */ |
7dd6a2aa | 1837 | fec_set_mac_address(dev); |
1da177e4 | 1838 | |
f44d6305 SH |
1839 | /* Reset all multicast. */ |
1840 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1841 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1da177e4 | 1842 | |
f44d6305 SH |
1843 | /* Set maximum receive buffer size. */ |
1844 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 1845 | |
f44d6305 SH |
1846 | /* Set receive and transmit descriptor base. */ |
1847 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
2e28532f | 1848 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1849 | fep->hwp + FEC_X_DES_START); |
1da177e4 LT |
1850 | |
1851 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1852 | fep->cur_rx = fep->rx_bd_base; | |
1853 | ||
f44d6305 | 1854 | /* Reset SKB transmit buffers. */ |
1da177e4 LT |
1855 | fep->skb_cur = fep->skb_dirty = 0; |
1856 | for (i=0; i<=TX_RING_MOD_MASK; i++) { | |
1857 | if (fep->tx_skbuff[i] != NULL) { | |
1858 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
1859 | fep->tx_skbuff[i] = NULL; | |
1860 | } | |
1861 | } | |
1862 | ||
f44d6305 | 1863 | /* Initialize the receive buffer descriptors. */ |
1da177e4 LT |
1864 | bdp = fep->rx_bd_base; |
1865 | for (i=0; i<RX_RING_SIZE; i++) { | |
1866 | ||
f44d6305 | 1867 | /* Initialize the BD for every fragment in the page. */ |
1da177e4 LT |
1868 | bdp->cbd_sc = BD_ENET_RX_EMPTY; |
1869 | bdp++; | |
1870 | } | |
1871 | ||
f44d6305 | 1872 | /* Set the last buffer to wrap. */ |
1da177e4 LT |
1873 | bdp--; |
1874 | bdp->cbd_sc |= BD_SC_WRAP; | |
1875 | ||
f44d6305 | 1876 | /* ...and the same for transmmit. */ |
1da177e4 LT |
1877 | bdp = fep->tx_bd_base; |
1878 | for (i=0; i<TX_RING_SIZE; i++) { | |
1879 | ||
f44d6305 | 1880 | /* Initialize the BD for every fragment in the page. */ |
1da177e4 LT |
1881 | bdp->cbd_sc = 0; |
1882 | bdp->cbd_bufaddr = 0; | |
1883 | bdp++; | |
1884 | } | |
1885 | ||
f44d6305 | 1886 | /* Set the last buffer to wrap. */ |
1da177e4 LT |
1887 | bdp--; |
1888 | bdp->cbd_sc |= BD_SC_WRAP; | |
1889 | ||
f44d6305 | 1890 | /* Enable MII mode. */ |
1da177e4 | 1891 | if (duplex) { |
f44d6305 SH |
1892 | /* MII enable / FD enable */ |
1893 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
1894 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
f909b1ef | 1895 | } else { |
f44d6305 SH |
1896 | /* MII enable / No Rcv on Xmit */ |
1897 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
1898 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
1da177e4 LT |
1899 | } |
1900 | fep->full_duplex = duplex; | |
1901 | ||
f44d6305 SH |
1902 | /* Set MII speed. */ |
1903 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 1904 | |
f44d6305 SH |
1905 | /* And last, enable the transmit and receive processing. */ |
1906 | writel(2, fep->hwp + FEC_ECNTRL); | |
1907 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
6b265293 | 1908 | |
f44d6305 SH |
1909 | /* Enable interrupts we wish to service. */ |
1910 | writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII, | |
1911 | fep->hwp + FEC_IMASK); | |
1da177e4 LT |
1912 | } |
1913 | ||
1914 | static void | |
1915 | fec_stop(struct net_device *dev) | |
1916 | { | |
f44d6305 | 1917 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1918 | |
677177c5 PDM |
1919 | /* |
1920 | ** We cannot expect a graceful transmit stop without link !!! | |
1921 | */ | |
f44d6305 SH |
1922 | if (fep->link) { |
1923 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
677177c5 | 1924 | udelay(10); |
f44d6305 | 1925 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
677177c5 | 1926 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
f44d6305 | 1927 | } |
1da177e4 | 1928 | |
f44d6305 SH |
1929 | /* Whack a reset. We should wait for this. */ |
1930 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1931 | udelay(10); |
1932 | ||
f44d6305 SH |
1933 | /* Clear outstanding MII command interrupts. */ |
1934 | writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1935 | |
f44d6305 SH |
1936 | writel(FEC_ENET_MII, fep->hwp + FEC_IMASK); |
1937 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 LT |
1938 | } |
1939 | ||
ead73183 SH |
1940 | static int __devinit |
1941 | fec_probe(struct platform_device *pdev) | |
1942 | { | |
1943 | struct fec_enet_private *fep; | |
1944 | struct net_device *ndev; | |
1945 | int i, irq, ret = 0; | |
1946 | struct resource *r; | |
1947 | ||
1948 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1949 | if (!r) | |
1950 | return -ENXIO; | |
1951 | ||
1952 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1953 | if (!r) | |
1954 | return -EBUSY; | |
1955 | ||
1956 | /* Init network device */ | |
1957 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
1958 | if (!ndev) | |
1959 | return -ENOMEM; | |
1960 | ||
1961 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1962 | ||
1963 | /* setup board info structure */ | |
1964 | fep = netdev_priv(ndev); | |
1965 | memset(fep, 0, sizeof(*fep)); | |
1966 | ||
1967 | ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); | |
1968 | ||
1969 | if (!ndev->base_addr) { | |
1970 | ret = -ENOMEM; | |
1971 | goto failed_ioremap; | |
1972 | } | |
1973 | ||
1974 | platform_set_drvdata(pdev, ndev); | |
1975 | ||
1976 | /* This device has up to three irqs on some platforms */ | |
1977 | for (i = 0; i < 3; i++) { | |
1978 | irq = platform_get_irq(pdev, i); | |
1979 | if (i && irq < 0) | |
1980 | break; | |
1981 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1982 | if (ret) { | |
1983 | while (i >= 0) { | |
1984 | irq = platform_get_irq(pdev, i); | |
1985 | free_irq(irq, ndev); | |
1986 | i--; | |
1987 | } | |
1988 | goto failed_irq; | |
1989 | } | |
1990 | } | |
1991 | ||
1992 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1993 | if (IS_ERR(fep->clk)) { | |
1994 | ret = PTR_ERR(fep->clk); | |
1995 | goto failed_clk; | |
1996 | } | |
1997 | clk_enable(fep->clk); | |
1998 | ||
1999 | ret = fec_enet_init(ndev, 0); | |
2000 | if (ret) | |
2001 | goto failed_init; | |
2002 | ||
2003 | ret = register_netdev(ndev); | |
2004 | if (ret) | |
2005 | goto failed_register; | |
2006 | ||
2007 | return 0; | |
2008 | ||
2009 | failed_register: | |
2010 | failed_init: | |
2011 | clk_disable(fep->clk); | |
2012 | clk_put(fep->clk); | |
2013 | failed_clk: | |
2014 | for (i = 0; i < 3; i++) { | |
2015 | irq = platform_get_irq(pdev, i); | |
2016 | if (irq > 0) | |
2017 | free_irq(irq, ndev); | |
2018 | } | |
2019 | failed_irq: | |
2020 | iounmap((void __iomem *)ndev->base_addr); | |
2021 | failed_ioremap: | |
2022 | free_netdev(ndev); | |
2023 | ||
2024 | return ret; | |
2025 | } | |
2026 | ||
2027 | static int __devexit | |
2028 | fec_drv_remove(struct platform_device *pdev) | |
2029 | { | |
2030 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2031 | struct fec_enet_private *fep = netdev_priv(ndev); | |
2032 | ||
2033 | platform_set_drvdata(pdev, NULL); | |
2034 | ||
2035 | fec_stop(ndev); | |
2036 | clk_disable(fep->clk); | |
2037 | clk_put(fep->clk); | |
2038 | iounmap((void __iomem *)ndev->base_addr); | |
2039 | unregister_netdev(ndev); | |
2040 | free_netdev(ndev); | |
2041 | return 0; | |
2042 | } | |
2043 | ||
2044 | static int | |
2045 | fec_suspend(struct platform_device *dev, pm_message_t state) | |
2046 | { | |
2047 | struct net_device *ndev = platform_get_drvdata(dev); | |
2048 | struct fec_enet_private *fep; | |
2049 | ||
2050 | if (ndev) { | |
2051 | fep = netdev_priv(ndev); | |
2052 | if (netif_running(ndev)) { | |
2053 | netif_device_detach(ndev); | |
2054 | fec_stop(ndev); | |
2055 | } | |
2056 | } | |
2057 | return 0; | |
2058 | } | |
2059 | ||
2060 | static int | |
2061 | fec_resume(struct platform_device *dev) | |
2062 | { | |
2063 | struct net_device *ndev = platform_get_drvdata(dev); | |
2064 | ||
2065 | if (ndev) { | |
2066 | if (netif_running(ndev)) { | |
2067 | fec_enet_init(ndev, 0); | |
2068 | netif_device_attach(ndev); | |
2069 | } | |
2070 | } | |
2071 | return 0; | |
2072 | } | |
2073 | ||
2074 | static struct platform_driver fec_driver = { | |
2075 | .driver = { | |
2076 | .name = "fec", | |
2077 | .owner = THIS_MODULE, | |
2078 | }, | |
2079 | .probe = fec_probe, | |
2080 | .remove = __devexit_p(fec_drv_remove), | |
2081 | .suspend = fec_suspend, | |
2082 | .resume = fec_resume, | |
2083 | }; | |
2084 | ||
2085 | static int __init | |
2086 | fec_enet_module_init(void) | |
2087 | { | |
2088 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
2089 | ||
2090 | return platform_driver_register(&fec_driver); | |
2091 | } | |
2092 | ||
2093 | static void __exit | |
2094 | fec_enet_cleanup(void) | |
2095 | { | |
2096 | platform_driver_unregister(&fec_driver); | |
2097 | } | |
2098 | ||
2099 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
2100 | module_init(fec_enet_module_init); |
2101 | ||
2102 | MODULE_LICENSE("GPL"); |