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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
6 | * and Andrew de Quincey. It's neither supported nor endorsed | |
7 | * by NVIDIA Corp. Use at your own risk. | |
8 | * | |
9 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
10 | * trademarks of NVIDIA Corporation in the United States and other | |
11 | * countries. | |
12 | * | |
1836098f | 13 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
14 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
15 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
16 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
17 | * Copyright (c) 2004 NVIDIA Corporation | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation; either version 2 of the License, or | |
22 | * (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
32 | * | |
33 | * Changelog: | |
34 | * 0.01: 05 Oct 2003: First release that compiles without warnings. | |
35 | * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. | |
36 | * Check all PCI BARs for the register window. | |
37 | * udelay added to mii_rw. | |
38 | * 0.03: 06 Oct 2003: Initialize dev->irq. | |
39 | * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. | |
40 | * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. | |
41 | * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, | |
42 | * irq mask updated | |
43 | * 0.07: 14 Oct 2003: Further irq mask updates. | |
44 | * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill | |
45 | * added into irq handler, NULL check for drain_ring. | |
46 | * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the | |
47 | * requested interrupt sources. | |
48 | * 0.10: 20 Oct 2003: First cleanup for release. | |
49 | * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. | |
50 | * MAC Address init fix, set_multicast cleanup. | |
51 | * 0.12: 23 Oct 2003: Cleanups for release. | |
52 | * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. | |
53 | * Set link speed correctly. start rx before starting | |
54 | * tx (nv_start_rx sets the link speed). | |
55 | * 0.14: 25 Oct 2003: Nic dependant irq mask. | |
56 | * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during | |
57 | * open. | |
58 | * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size | |
59 | * increased to 1628 bytes. | |
60 | * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from | |
61 | * the tx length. | |
62 | * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats | |
63 | * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac | |
64 | * addresses, really stop rx if already running | |
65 | * in nv_start_rx, clean up a bit. | |
66 | * 0.20: 07 Dec 2003: alloc fixes | |
67 | * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. | |
68 | * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup | |
69 | * on close. | |
70 | * 0.23: 26 Jan 2004: various small cleanups | |
71 | * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces | |
72 | * 0.25: 09 Mar 2004: wol support | |
73 | * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes | |
74 | * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, | |
75 | * added CK804/MCP04 device IDs, code fixes | |
76 | * for registers, link status and other minor fixes. | |
77 | * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe | |
78 | * 0.29: 31 Aug 2004: Add backup timer for link change notification. | |
79 | * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset | |
80 | * into nv_close, otherwise reenabling for wol can | |
81 | * cause DMA to kfree'd memory. | |
82 | * 0.31: 14 Nov 2004: ethtool support for getting/setting link | |
4ea7f299 | 83 | * capabilities. |
22c6d143 | 84 | * 0.32: 16 Apr 2005: RX_ERROR4 handling added. |
8f767fc8 MS |
85 | * 0.33: 16 May 2005: Support for MCP51 added. |
86 | * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. | |
f49d16ef | 87 | * 0.35: 26 Jun 2005: Support for MCP55 added. |
dc8216c1 MS |
88 | * 0.36: 28 Jun 2005: Add jumbo frame support. |
89 | * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list | |
c2dba06d MS |
90 | * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of |
91 | * per-packet flags. | |
4ea7f299 AA |
92 | * 0.39: 18 Jul 2005: Add 64bit descriptor support. |
93 | * 0.40: 19 Jul 2005: Add support for mac address change. | |
94 | * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead | |
b3df9f81 | 95 | * of nv_remove |
4ea7f299 | 96 | * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
1b1b3c9b | 97 | * in the second (and later) nv_open call |
4ea7f299 AA |
98 | * 0.43: 10 Aug 2005: Add support for tx checksum. |
99 | * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. | |
100 | * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check | |
a971c324 | 101 | * 0.46: 20 Oct 2005: Add irq optimization modes. |
7a33e45a | 102 | * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. |
1836098f | 103 | * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single |
fa45459e | 104 | * 0.49: 10 Dec 2005: Fix tso for large buffers. |
ee407b02 | 105 | * 0.50: 20 Jan 2006: Add 8021pq tagging support. |
0832b25a | 106 | * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. |
d33a73c8 | 107 | * 0.52: 20 Jan 2006: Add MSI/MSIX support. |
86a0f043 | 108 | * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
1da177e4 LT |
109 | * |
110 | * Known bugs: | |
111 | * We suspect that on some hardware no TX done interrupts are generated. | |
112 | * This means recovery from netif_stop_queue only happens if the hw timer | |
113 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
114 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
115 | * If your hardware reliably generates tx done interrupts, then you can remove | |
116 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
117 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
118 | * superfluous timer interrupts from the nic. | |
119 | */ | |
f34ba4e1 | 120 | #define FORCEDETH_VERSION "0.53" |
1da177e4 LT |
121 | #define DRV_NAME "forcedeth" |
122 | ||
123 | #include <linux/module.h> | |
124 | #include <linux/types.h> | |
125 | #include <linux/pci.h> | |
126 | #include <linux/interrupt.h> | |
127 | #include <linux/netdevice.h> | |
128 | #include <linux/etherdevice.h> | |
129 | #include <linux/delay.h> | |
130 | #include <linux/spinlock.h> | |
131 | #include <linux/ethtool.h> | |
132 | #include <linux/timer.h> | |
133 | #include <linux/skbuff.h> | |
134 | #include <linux/mii.h> | |
135 | #include <linux/random.h> | |
136 | #include <linux/init.h> | |
22c6d143 | 137 | #include <linux/if_vlan.h> |
910638ae | 138 | #include <linux/dma-mapping.h> |
1da177e4 LT |
139 | |
140 | #include <asm/irq.h> | |
141 | #include <asm/io.h> | |
142 | #include <asm/uaccess.h> | |
143 | #include <asm/system.h> | |
144 | ||
145 | #if 0 | |
146 | #define dprintk printk | |
147 | #else | |
148 | #define dprintk(x...) do { } while (0) | |
149 | #endif | |
150 | ||
151 | ||
152 | /* | |
153 | * Hardware access: | |
154 | */ | |
155 | ||
c2dba06d MS |
156 | #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */ |
157 | #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ | |
158 | #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ | |
ee73362c | 159 | #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
8a4ae7f2 | 160 | #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ |
ee407b02 | 161 | #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */ |
d33a73c8 AA |
162 | #define DEV_HAS_MSI 0x0040 /* device supports MSI */ |
163 | #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */ | |
86a0f043 | 164 | #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */ |
1da177e4 LT |
165 | |
166 | enum { | |
167 | NvRegIrqStatus = 0x000, | |
168 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
169 | #define NVREG_IRQSTAT_MASK 0x1ff | |
170 | NvRegIrqMask = 0x004, | |
171 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
172 | #define NVREG_IRQ_RX 0x0002 | |
173 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
174 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 175 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
176 | #define NVREG_IRQ_TIMER 0x0020 |
177 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
178 | #define NVREG_IRQ_RX_FORCED 0x0080 |
179 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
a971c324 AA |
180 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
181 | #define NVREG_IRQMASK_CPU 0x0040 | |
d33a73c8 AA |
182 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
183 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
184 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) | |
c2dba06d MS |
185 | |
186 | #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ | |
d33a73c8 AA |
187 | NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
188 | NVREG_IRQ_TX_FORCED)) | |
1da177e4 LT |
189 | |
190 | NvRegUnknownSetupReg6 = 0x008, | |
191 | #define NVREG_UNKSETUP6_VAL 3 | |
192 | ||
193 | /* | |
194 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
195 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
196 | */ | |
197 | NvRegPollingInterval = 0x00c, | |
a971c324 AA |
198 | #define NVREG_POLL_DEFAULT_THROUGHPUT 970 |
199 | #define NVREG_POLL_DEFAULT_CPU 13 | |
d33a73c8 AA |
200 | NvRegMSIMap0 = 0x020, |
201 | NvRegMSIMap1 = 0x024, | |
202 | NvRegMSIIrqMask = 0x030, | |
203 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 LT |
204 | NvRegMisc1 = 0x080, |
205 | #define NVREG_MISC1_HD 0x02 | |
206 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
207 | ||
86a0f043 AA |
208 | NvRegMacReset = 0x3c, |
209 | #define NVREG_MAC_RESET_ASSERT 0x0F3 | |
1da177e4 LT |
210 | NvRegTransmitterControl = 0x084, |
211 | #define NVREG_XMITCTL_START 0x01 | |
212 | NvRegTransmitterStatus = 0x088, | |
213 | #define NVREG_XMITSTAT_BUSY 0x01 | |
214 | ||
215 | NvRegPacketFilterFlags = 0x8c, | |
216 | #define NVREG_PFF_ALWAYS 0x7F0008 | |
217 | #define NVREG_PFF_PROMISC 0x80 | |
218 | #define NVREG_PFF_MYADDR 0x20 | |
219 | ||
220 | NvRegOffloadConfig = 0x90, | |
221 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
222 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
223 | NvRegReceiverControl = 0x094, | |
224 | #define NVREG_RCVCTL_START 0x01 | |
225 | NvRegReceiverStatus = 0x98, | |
226 | #define NVREG_RCVSTAT_BUSY 0x01 | |
227 | ||
228 | NvRegRandomSeed = 0x9c, | |
229 | #define NVREG_RNDSEED_MASK 0x00ff | |
230 | #define NVREG_RNDSEED_FORCE 0x7f00 | |
231 | #define NVREG_RNDSEED_FORCE2 0x2d00 | |
232 | #define NVREG_RNDSEED_FORCE3 0x7400 | |
233 | ||
234 | NvRegUnknownSetupReg1 = 0xA0, | |
235 | #define NVREG_UNKSETUP1_VAL 0x16070f | |
236 | NvRegUnknownSetupReg2 = 0xA4, | |
237 | #define NVREG_UNKSETUP2_VAL 0x16 | |
238 | NvRegMacAddrA = 0xA8, | |
239 | NvRegMacAddrB = 0xAC, | |
240 | NvRegMulticastAddrA = 0xB0, | |
241 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
242 | NvRegMulticastAddrB = 0xB4, | |
243 | NvRegMulticastMaskA = 0xB8, | |
244 | NvRegMulticastMaskB = 0xBC, | |
245 | ||
246 | NvRegPhyInterface = 0xC0, | |
247 | #define PHY_RGMII 0x10000000 | |
248 | ||
249 | NvRegTxRingPhysAddr = 0x100, | |
250 | NvRegRxRingPhysAddr = 0x104, | |
251 | NvRegRingSizes = 0x108, | |
252 | #define NVREG_RINGSZ_TXSHIFT 0 | |
253 | #define NVREG_RINGSZ_RXSHIFT 16 | |
254 | NvRegUnknownTransmitterReg = 0x10c, | |
255 | NvRegLinkSpeed = 0x110, | |
256 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
257 | #define NVREG_LINKSPEED_10 1000 | |
258 | #define NVREG_LINKSPEED_100 100 | |
259 | #define NVREG_LINKSPEED_1000 50 | |
260 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
261 | NvRegUnknownSetupReg5 = 0x130, | |
262 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
263 | NvRegUnknownSetupReg3 = 0x13c, | |
264 | #define NVREG_UNKSETUP3_VAL1 0x200010 | |
265 | NvRegTxRxControl = 0x144, | |
266 | #define NVREG_TXRXCTL_KICK 0x0001 | |
267 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
268 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
269 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
270 | #define NVREG_TXRXCTL_RESET 0x0010 | |
271 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 MS |
272 | #define NVREG_TXRXCTL_DESC_1 0 |
273 | #define NVREG_TXRXCTL_DESC_2 0x02100 | |
274 | #define NVREG_TXRXCTL_DESC_3 0x02200 | |
ee407b02 AA |
275 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
276 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
277 | NvRegTxRingPhysAddrHigh = 0x148, |
278 | NvRegRxRingPhysAddrHigh = 0x14C, | |
1da177e4 LT |
279 | NvRegMIIStatus = 0x180, |
280 | #define NVREG_MIISTAT_ERROR 0x0001 | |
281 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
282 | #define NVREG_MIISTAT_MASK 0x000f | |
283 | #define NVREG_MIISTAT_MASK2 0x000f | |
284 | NvRegUnknownSetupReg4 = 0x184, | |
285 | #define NVREG_UNKSETUP4_VAL 8 | |
286 | ||
287 | NvRegAdapterControl = 0x188, | |
288 | #define NVREG_ADAPTCTL_START 0x02 | |
289 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
290 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
291 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
292 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
293 | NvRegMIISpeed = 0x18c, | |
294 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
295 | #define NVREG_MIIDELAY 5 | |
296 | NvRegMIIControl = 0x190, | |
297 | #define NVREG_MIICTL_INUSE 0x08000 | |
298 | #define NVREG_MIICTL_WRITE 0x00400 | |
299 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
300 | NvRegMIIData = 0x194, | |
301 | NvRegWakeUpFlags = 0x200, | |
302 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
303 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
304 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
305 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
306 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
307 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
308 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
309 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
310 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
311 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
312 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
313 | ||
314 | NvRegPatternCRC = 0x204, | |
315 | NvRegPatternMask = 0x208, | |
316 | NvRegPowerCap = 0x268, | |
317 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
318 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
319 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
320 | NvRegPowerState = 0x26c, | |
321 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
322 | #define NVREG_POWERSTATE_VALID 0x0100 | |
323 | #define NVREG_POWERSTATE_MASK 0x0003 | |
324 | #define NVREG_POWERSTATE_D0 0x0000 | |
325 | #define NVREG_POWERSTATE_D1 0x0001 | |
326 | #define NVREG_POWERSTATE_D2 0x0002 | |
327 | #define NVREG_POWERSTATE_D3 0x0003 | |
ee407b02 AA |
328 | NvRegVlanControl = 0x300, |
329 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
330 | NvRegMSIXMap0 = 0x3e0, |
331 | NvRegMSIXMap1 = 0x3e4, | |
332 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
333 | |
334 | NvRegPowerState2 = 0x600, | |
335 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 | |
336 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 | |
1da177e4 LT |
337 | }; |
338 | ||
339 | /* Big endian: should work, but is untested */ | |
340 | struct ring_desc { | |
341 | u32 PacketBuffer; | |
342 | u32 FlagLen; | |
343 | }; | |
344 | ||
ee73362c MS |
345 | struct ring_desc_ex { |
346 | u32 PacketBufferHigh; | |
347 | u32 PacketBufferLow; | |
ee407b02 | 348 | u32 TxVlan; |
ee73362c MS |
349 | u32 FlagLen; |
350 | }; | |
351 | ||
352 | typedef union _ring_type { | |
353 | struct ring_desc* orig; | |
354 | struct ring_desc_ex* ex; | |
355 | } ring_type; | |
356 | ||
1da177e4 LT |
357 | #define FLAG_MASK_V1 0xffff0000 |
358 | #define FLAG_MASK_V2 0xffffc000 | |
359 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
360 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
361 | ||
362 | #define NV_TX_LASTPACKET (1<<16) | |
363 | #define NV_TX_RETRYERROR (1<<19) | |
c2dba06d | 364 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
365 | #define NV_TX_DEFERRED (1<<26) |
366 | #define NV_TX_CARRIERLOST (1<<27) | |
367 | #define NV_TX_LATECOLLISION (1<<28) | |
368 | #define NV_TX_UNDERFLOW (1<<29) | |
369 | #define NV_TX_ERROR (1<<30) | |
370 | #define NV_TX_VALID (1<<31) | |
371 | ||
372 | #define NV_TX2_LASTPACKET (1<<29) | |
373 | #define NV_TX2_RETRYERROR (1<<18) | |
c2dba06d | 374 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
375 | #define NV_TX2_DEFERRED (1<<25) |
376 | #define NV_TX2_CARRIERLOST (1<<26) | |
377 | #define NV_TX2_LATECOLLISION (1<<27) | |
378 | #define NV_TX2_UNDERFLOW (1<<28) | |
379 | /* error and valid are the same for both */ | |
380 | #define NV_TX2_ERROR (1<<30) | |
381 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
382 | #define NV_TX2_TSO (1<<28) |
383 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
384 | #define NV_TX2_TSO_MAX_SHIFT 14 |
385 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
386 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
387 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 388 | |
ee407b02 AA |
389 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
390 | ||
1da177e4 LT |
391 | #define NV_RX_DESCRIPTORVALID (1<<16) |
392 | #define NV_RX_MISSEDFRAME (1<<17) | |
393 | #define NV_RX_SUBSTRACT1 (1<<18) | |
394 | #define NV_RX_ERROR1 (1<<23) | |
395 | #define NV_RX_ERROR2 (1<<24) | |
396 | #define NV_RX_ERROR3 (1<<25) | |
397 | #define NV_RX_ERROR4 (1<<26) | |
398 | #define NV_RX_CRCERR (1<<27) | |
399 | #define NV_RX_OVERFLOW (1<<28) | |
400 | #define NV_RX_FRAMINGERR (1<<29) | |
401 | #define NV_RX_ERROR (1<<30) | |
402 | #define NV_RX_AVAIL (1<<31) | |
403 | ||
404 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
405 | #define NV_RX2_CHECKSUMOK1 (0x10000000) | |
406 | #define NV_RX2_CHECKSUMOK2 (0x14000000) | |
407 | #define NV_RX2_CHECKSUMOK3 (0x18000000) | |
408 | #define NV_RX2_DESCRIPTORVALID (1<<29) | |
409 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
410 | #define NV_RX2_ERROR1 (1<<18) | |
411 | #define NV_RX2_ERROR2 (1<<19) | |
412 | #define NV_RX2_ERROR3 (1<<20) | |
413 | #define NV_RX2_ERROR4 (1<<21) | |
414 | #define NV_RX2_CRCERR (1<<22) | |
415 | #define NV_RX2_OVERFLOW (1<<23) | |
416 | #define NV_RX2_FRAMINGERR (1<<24) | |
417 | /* error and avail are the same for both */ | |
418 | #define NV_RX2_ERROR (1<<30) | |
419 | #define NV_RX2_AVAIL (1<<31) | |
420 | ||
ee407b02 AA |
421 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
422 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
423 | ||
1da177e4 | 424 | /* Miscelaneous hardware related defines: */ |
86a0f043 AA |
425 | #define NV_PCI_REGSZ_VER1 0x270 |
426 | #define NV_PCI_REGSZ_VER2 0x604 | |
1da177e4 LT |
427 | |
428 | /* various timeout delays: all in usec */ | |
429 | #define NV_TXRX_RESET_DELAY 4 | |
430 | #define NV_TXSTOP_DELAY1 10 | |
431 | #define NV_TXSTOP_DELAY1MAX 500000 | |
432 | #define NV_TXSTOP_DELAY2 100 | |
433 | #define NV_RXSTOP_DELAY1 10 | |
434 | #define NV_RXSTOP_DELAY1MAX 500000 | |
435 | #define NV_RXSTOP_DELAY2 100 | |
436 | #define NV_SETUP5_DELAY 5 | |
437 | #define NV_SETUP5_DELAYMAX 50000 | |
438 | #define NV_POWERUP_DELAY 5 | |
439 | #define NV_POWERUP_DELAYMAX 5000 | |
440 | #define NV_MIIBUSY_DELAY 50 | |
441 | #define NV_MIIPHY_DELAY 10 | |
442 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 443 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
444 | |
445 | #define NV_WAKEUPPATTERNS 5 | |
446 | #define NV_WAKEUPMASKENTRIES 4 | |
447 | ||
448 | /* General driver defaults */ | |
449 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
450 | ||
451 | #define RX_RING 128 | |
fa45459e | 452 | #define TX_RING 256 |
1da177e4 LT |
453 | /* |
454 | * If your nic mysteriously hangs then try to reduce the limits | |
455 | * to 1/0: It might be required to set NV_TX_LASTPACKET in the | |
456 | * last valid ring entry. But this would be impossible to | |
457 | * implement - probably a disassembly error. | |
458 | */ | |
fa45459e AA |
459 | #define TX_LIMIT_STOP 255 |
460 | #define TX_LIMIT_START 254 | |
1da177e4 LT |
461 | |
462 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
463 | #define NV_RX_HEADERS (64) |
464 | /* even more slack. */ | |
465 | #define NV_RX_ALLOC_PAD (64) | |
466 | ||
467 | /* maximum mtu size */ | |
468 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
469 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
470 | |
471 | #define OOM_REFILL (1+HZ/20) | |
472 | #define POLL_WAIT (1+HZ/100) | |
473 | #define LINK_TIMEOUT (3*HZ) | |
474 | ||
475 | /* | |
476 | * desc_ver values: | |
8a4ae7f2 MS |
477 | * The nic supports three different descriptor types: |
478 | * - DESC_VER_1: Original | |
479 | * - DESC_VER_2: support for jumbo frames. | |
480 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 481 | */ |
8a4ae7f2 MS |
482 | #define DESC_VER_1 1 |
483 | #define DESC_VER_2 2 | |
484 | #define DESC_VER_3 3 | |
1da177e4 LT |
485 | |
486 | /* PHY defines */ | |
487 | #define PHY_OUI_MARVELL 0x5043 | |
488 | #define PHY_OUI_CICADA 0x03f1 | |
489 | #define PHYID1_OUI_MASK 0x03ff | |
490 | #define PHYID1_OUI_SHFT 6 | |
491 | #define PHYID2_OUI_MASK 0xfc00 | |
492 | #define PHYID2_OUI_SHFT 10 | |
493 | #define PHY_INIT1 0x0f000 | |
494 | #define PHY_INIT2 0x0e00 | |
495 | #define PHY_INIT3 0x01000 | |
496 | #define PHY_INIT4 0x0200 | |
497 | #define PHY_INIT5 0x0004 | |
498 | #define PHY_INIT6 0x02000 | |
499 | #define PHY_GIGABIT 0x0100 | |
500 | ||
501 | #define PHY_TIMEOUT 0x1 | |
502 | #define PHY_ERROR 0x2 | |
503 | ||
504 | #define PHY_100 0x1 | |
505 | #define PHY_1000 0x2 | |
506 | #define PHY_HALF 0x100 | |
507 | ||
508 | /* FIXME: MII defines that should be added to <linux/mii.h> */ | |
509 | #define MII_1000BT_CR 0x09 | |
510 | #define MII_1000BT_SR 0x0a | |
511 | #define ADVERTISE_1000FULL 0x0200 | |
512 | #define ADVERTISE_1000HALF 0x0100 | |
513 | #define LPA_1000FULL 0x0800 | |
514 | #define LPA_1000HALF 0x0400 | |
515 | ||
d33a73c8 AA |
516 | /* MSI/MSI-X defines */ |
517 | #define NV_MSI_X_MAX_VECTORS 8 | |
518 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
519 | #define NV_MSI_CAPABLE 0x0010 | |
520 | #define NV_MSI_X_CAPABLE 0x0020 | |
521 | #define NV_MSI_ENABLED 0x0040 | |
522 | #define NV_MSI_X_ENABLED 0x0080 | |
523 | ||
524 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
525 | #define NV_MSI_X_VECTOR_RX 0x0 | |
526 | #define NV_MSI_X_VECTOR_TX 0x1 | |
527 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 LT |
528 | |
529 | /* | |
530 | * SMP locking: | |
531 | * All hardware access under dev->priv->lock, except the performance | |
532 | * critical parts: | |
533 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
534 | * by the arch code for interrupts. | |
535 | * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission | |
536 | * needs dev->priv->lock :-( | |
537 | * - set_multicast_list: preparation lockless, relies on dev->xmit_lock. | |
538 | */ | |
539 | ||
540 | /* in dev: base, irq */ | |
541 | struct fe_priv { | |
542 | spinlock_t lock; | |
543 | ||
544 | /* General data: | |
545 | * Locking: spin_lock(&np->lock); */ | |
546 | struct net_device_stats stats; | |
547 | int in_shutdown; | |
548 | u32 linkspeed; | |
549 | int duplex; | |
550 | int autoneg; | |
551 | int fixed_mode; | |
552 | int phyaddr; | |
553 | int wolenabled; | |
554 | unsigned int phy_oui; | |
555 | u16 gigabit; | |
556 | ||
557 | /* General data: RO fields */ | |
558 | dma_addr_t ring_addr; | |
559 | struct pci_dev *pci_dev; | |
560 | u32 orig_mac[2]; | |
561 | u32 irqmask; | |
562 | u32 desc_ver; | |
8a4ae7f2 | 563 | u32 txrxctl_bits; |
ee407b02 | 564 | u32 vlanctl_bits; |
86a0f043 AA |
565 | u32 driver_data; |
566 | u32 register_size; | |
1da177e4 LT |
567 | |
568 | void __iomem *base; | |
569 | ||
570 | /* rx specific fields. | |
571 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
572 | */ | |
ee73362c | 573 | ring_type rx_ring; |
1da177e4 LT |
574 | unsigned int cur_rx, refill_rx; |
575 | struct sk_buff *rx_skbuff[RX_RING]; | |
576 | dma_addr_t rx_dma[RX_RING]; | |
577 | unsigned int rx_buf_sz; | |
d81c0983 | 578 | unsigned int pkt_limit; |
1da177e4 LT |
579 | struct timer_list oom_kick; |
580 | struct timer_list nic_poll; | |
d33a73c8 | 581 | u32 nic_poll_irq; |
1da177e4 LT |
582 | |
583 | /* media detection workaround. | |
584 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
585 | */ | |
586 | int need_linktimer; | |
587 | unsigned long link_timeout; | |
588 | /* | |
589 | * tx specific fields. | |
590 | */ | |
ee73362c | 591 | ring_type tx_ring; |
1da177e4 LT |
592 | unsigned int next_tx, nic_tx; |
593 | struct sk_buff *tx_skbuff[TX_RING]; | |
594 | dma_addr_t tx_dma[TX_RING]; | |
fa45459e | 595 | unsigned int tx_dma_len[TX_RING]; |
1da177e4 | 596 | u32 tx_flags; |
ee407b02 AA |
597 | |
598 | /* vlan fields */ | |
599 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
600 | |
601 | /* msi/msi-x fields */ | |
602 | u32 msi_flags; | |
603 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
1da177e4 LT |
604 | }; |
605 | ||
606 | /* | |
607 | * Maximum number of loops until we assume that a bit in the irq mask | |
608 | * is stuck. Overridable with module param. | |
609 | */ | |
610 | static int max_interrupt_work = 5; | |
611 | ||
a971c324 AA |
612 | /* |
613 | * Optimization can be either throuput mode or cpu mode | |
614 | * | |
615 | * Throughput Mode: Every tx and rx packet will generate an interrupt. | |
616 | * CPU Mode: Interrupts are controlled by a timer. | |
617 | */ | |
618 | #define NV_OPTIMIZATION_MODE_THROUGHPUT 0 | |
619 | #define NV_OPTIMIZATION_MODE_CPU 1 | |
620 | static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
621 | ||
622 | /* | |
623 | * Poll interval for timer irq | |
624 | * | |
625 | * This interval determines how frequent an interrupt is generated. | |
626 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
627 | * Min = 0, and Max = 65535 | |
628 | */ | |
629 | static int poll_interval = -1; | |
630 | ||
d33a73c8 AA |
631 | /* |
632 | * Disable MSI interrupts | |
633 | */ | |
634 | static int disable_msi = 0; | |
635 | ||
636 | /* | |
637 | * Disable MSIX interrupts | |
638 | */ | |
639 | static int disable_msix = 0; | |
640 | ||
1da177e4 LT |
641 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
642 | { | |
643 | return netdev_priv(dev); | |
644 | } | |
645 | ||
646 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
647 | { | |
ac9c1897 | 648 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
649 | } |
650 | ||
651 | static inline void pci_push(u8 __iomem *base) | |
652 | { | |
653 | /* force out pending posted writes */ | |
654 | readl(base); | |
655 | } | |
656 | ||
657 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
658 | { | |
659 | return le32_to_cpu(prd->FlagLen) | |
660 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); | |
661 | } | |
662 | ||
ee73362c MS |
663 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
664 | { | |
665 | return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2; | |
666 | } | |
667 | ||
1da177e4 LT |
668 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
669 | int delay, int delaymax, const char *msg) | |
670 | { | |
671 | u8 __iomem *base = get_hwbase(dev); | |
672 | ||
673 | pci_push(base); | |
674 | do { | |
675 | udelay(delay); | |
676 | delaymax -= delay; | |
677 | if (delaymax < 0) { | |
678 | if (msg) | |
679 | printk(msg); | |
680 | return 1; | |
681 | } | |
682 | } while ((readl(base + offset) & mask) != target); | |
683 | return 0; | |
684 | } | |
685 | ||
0832b25a AA |
686 | #define NV_SETUP_RX_RING 0x01 |
687 | #define NV_SETUP_TX_RING 0x02 | |
688 | ||
689 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) | |
690 | { | |
691 | struct fe_priv *np = get_nvpriv(dev); | |
692 | u8 __iomem *base = get_hwbase(dev); | |
693 | ||
694 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
695 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
696 | writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); | |
697 | } | |
698 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
699 | writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); | |
700 | } | |
701 | } else { | |
702 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
703 | writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); | |
704 | writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh); | |
705 | } | |
706 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
707 | writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); | |
708 | writel((u32) (cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh); | |
709 | } | |
710 | } | |
711 | } | |
712 | ||
1da177e4 LT |
713 | #define MII_READ (-1) |
714 | /* mii_rw: read/write a register on the PHY. | |
715 | * | |
716 | * Caller must guarantee serialization | |
717 | */ | |
718 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
719 | { | |
720 | u8 __iomem *base = get_hwbase(dev); | |
721 | u32 reg; | |
722 | int retval; | |
723 | ||
724 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
725 | ||
726 | reg = readl(base + NvRegMIIControl); | |
727 | if (reg & NVREG_MIICTL_INUSE) { | |
728 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
729 | udelay(NV_MIIBUSY_DELAY); | |
730 | } | |
731 | ||
732 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
733 | if (value != MII_READ) { | |
734 | writel(value, base + NvRegMIIData); | |
735 | reg |= NVREG_MIICTL_WRITE; | |
736 | } | |
737 | writel(reg, base + NvRegMIIControl); | |
738 | ||
739 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
740 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | |
741 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | |
742 | dev->name, miireg, addr); | |
743 | retval = -1; | |
744 | } else if (value != MII_READ) { | |
745 | /* it was a write operation - fewer failures are detectable */ | |
746 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | |
747 | dev->name, value, miireg, addr); | |
748 | retval = 0; | |
749 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
750 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | |
751 | dev->name, miireg, addr); | |
752 | retval = -1; | |
753 | } else { | |
754 | retval = readl(base + NvRegMIIData); | |
755 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | |
756 | dev->name, miireg, addr, retval); | |
757 | } | |
758 | ||
759 | return retval; | |
760 | } | |
761 | ||
762 | static int phy_reset(struct net_device *dev) | |
763 | { | |
ac9c1897 | 764 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
765 | u32 miicontrol; |
766 | unsigned int tries = 0; | |
767 | ||
768 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
769 | miicontrol |= BMCR_RESET; | |
770 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { | |
771 | return -1; | |
772 | } | |
773 | ||
774 | /* wait for 500ms */ | |
775 | msleep(500); | |
776 | ||
777 | /* must wait till reset is deasserted */ | |
778 | while (miicontrol & BMCR_RESET) { | |
779 | msleep(10); | |
780 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
781 | /* FIXME: 100 tries seem excessive */ | |
782 | if (tries++ > 100) | |
783 | return -1; | |
784 | } | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static int phy_init(struct net_device *dev) | |
789 | { | |
790 | struct fe_priv *np = get_nvpriv(dev); | |
791 | u8 __iomem *base = get_hwbase(dev); | |
792 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; | |
793 | ||
794 | /* set advertise register */ | |
795 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
796 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400); | |
797 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { | |
798 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | |
799 | return PHY_ERROR; | |
800 | } | |
801 | ||
802 | /* get phy interface type */ | |
803 | phyinterface = readl(base + NvRegPhyInterface); | |
804 | ||
805 | /* see if gigabit phy */ | |
806 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
807 | if (mii_status & PHY_GIGABIT) { | |
808 | np->gigabit = PHY_GIGABIT; | |
809 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); | |
810 | mii_control_1000 &= ~ADVERTISE_1000HALF; | |
811 | if (phyinterface & PHY_RGMII) | |
812 | mii_control_1000 |= ADVERTISE_1000FULL; | |
813 | else | |
814 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
815 | ||
816 | if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) { | |
817 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
818 | return PHY_ERROR; | |
819 | } | |
820 | } | |
821 | else | |
822 | np->gigabit = 0; | |
823 | ||
824 | /* reset the phy */ | |
825 | if (phy_reset(dev)) { | |
826 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); | |
827 | return PHY_ERROR; | |
828 | } | |
829 | ||
830 | /* phy vendor specific configuration */ | |
831 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { | |
832 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
833 | phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); | |
834 | phy_reserved |= (PHY_INIT3 | PHY_INIT4); | |
835 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { | |
836 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
837 | return PHY_ERROR; | |
838 | } | |
839 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
840 | phy_reserved |= PHY_INIT5; | |
841 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { | |
842 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
843 | return PHY_ERROR; | |
844 | } | |
845 | } | |
846 | if (np->phy_oui == PHY_OUI_CICADA) { | |
847 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
848 | phy_reserved |= PHY_INIT6; | |
849 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { | |
850 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
851 | return PHY_ERROR; | |
852 | } | |
853 | } | |
854 | ||
855 | /* restart auto negotiation */ | |
856 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
857 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
858 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
859 | return PHY_ERROR; | |
860 | } | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
865 | static void nv_start_rx(struct net_device *dev) | |
866 | { | |
ac9c1897 | 867 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
868 | u8 __iomem *base = get_hwbase(dev); |
869 | ||
870 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | |
871 | /* Already running? Stop it. */ | |
872 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
873 | writel(0, base + NvRegReceiverControl); | |
874 | pci_push(base); | |
875 | } | |
876 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
877 | pci_push(base); | |
878 | writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); | |
879 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", | |
880 | dev->name, np->duplex, np->linkspeed); | |
881 | pci_push(base); | |
882 | } | |
883 | ||
884 | static void nv_stop_rx(struct net_device *dev) | |
885 | { | |
886 | u8 __iomem *base = get_hwbase(dev); | |
887 | ||
888 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | |
889 | writel(0, base + NvRegReceiverControl); | |
890 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, | |
891 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | |
892 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | |
893 | ||
894 | udelay(NV_RXSTOP_DELAY2); | |
895 | writel(0, base + NvRegLinkSpeed); | |
896 | } | |
897 | ||
898 | static void nv_start_tx(struct net_device *dev) | |
899 | { | |
900 | u8 __iomem *base = get_hwbase(dev); | |
901 | ||
902 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | |
903 | writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); | |
904 | pci_push(base); | |
905 | } | |
906 | ||
907 | static void nv_stop_tx(struct net_device *dev) | |
908 | { | |
909 | u8 __iomem *base = get_hwbase(dev); | |
910 | ||
911 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | |
912 | writel(0, base + NvRegTransmitterControl); | |
913 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, | |
914 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | |
915 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | |
916 | ||
917 | udelay(NV_TXSTOP_DELAY2); | |
918 | writel(0, base + NvRegUnknownTransmitterReg); | |
919 | } | |
920 | ||
921 | static void nv_txrx_reset(struct net_device *dev) | |
922 | { | |
ac9c1897 | 923 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
924 | u8 __iomem *base = get_hwbase(dev); |
925 | ||
926 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | |
8a4ae7f2 | 927 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
928 | pci_push(base); |
929 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 930 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
931 | pci_push(base); |
932 | } | |
933 | ||
86a0f043 AA |
934 | static void nv_mac_reset(struct net_device *dev) |
935 | { | |
936 | struct fe_priv *np = netdev_priv(dev); | |
937 | u8 __iomem *base = get_hwbase(dev); | |
938 | ||
939 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | |
940 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); | |
941 | pci_push(base); | |
942 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); | |
943 | pci_push(base); | |
944 | udelay(NV_MAC_RESET_DELAY); | |
945 | writel(0, base + NvRegMacReset); | |
946 | pci_push(base); | |
947 | udelay(NV_MAC_RESET_DELAY); | |
948 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); | |
949 | pci_push(base); | |
950 | } | |
951 | ||
1da177e4 LT |
952 | /* |
953 | * nv_get_stats: dev->get_stats function | |
954 | * Get latest stats value from the nic. | |
955 | * Called with read_lock(&dev_base_lock) held for read - | |
956 | * only synchronized against unregister_netdevice. | |
957 | */ | |
958 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
959 | { | |
ac9c1897 | 960 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
961 | |
962 | /* It seems that the nic always generates interrupts and doesn't | |
963 | * accumulate errors internally. Thus the current values in np->stats | |
964 | * are already up to date. | |
965 | */ | |
966 | return &np->stats; | |
967 | } | |
968 | ||
969 | /* | |
970 | * nv_alloc_rx: fill rx ring entries. | |
971 | * Return 1 if the allocations for the skbs failed and the | |
972 | * rx engine is without Available descriptors | |
973 | */ | |
974 | static int nv_alloc_rx(struct net_device *dev) | |
975 | { | |
ac9c1897 | 976 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
977 | unsigned int refill_rx = np->refill_rx; |
978 | int nr; | |
979 | ||
980 | while (np->cur_rx != refill_rx) { | |
981 | struct sk_buff *skb; | |
982 | ||
983 | nr = refill_rx % RX_RING; | |
984 | if (np->rx_skbuff[nr] == NULL) { | |
985 | ||
d81c0983 | 986 | skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
1da177e4 LT |
987 | if (!skb) |
988 | break; | |
989 | ||
990 | skb->dev = dev; | |
991 | np->rx_skbuff[nr] = skb; | |
992 | } else { | |
993 | skb = np->rx_skbuff[nr]; | |
994 | } | |
1836098f MS |
995 | np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, |
996 | skb->end-skb->data, PCI_DMA_FROMDEVICE); | |
ee73362c MS |
997 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
998 | np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); | |
999 | wmb(); | |
1000 | np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
1001 | } else { | |
1002 | np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32; | |
1003 | np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; | |
1004 | wmb(); | |
1005 | np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
1006 | } | |
1da177e4 LT |
1007 | dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
1008 | dev->name, refill_rx); | |
1009 | refill_rx++; | |
1010 | } | |
1011 | np->refill_rx = refill_rx; | |
1012 | if (np->cur_rx - refill_rx == RX_RING) | |
1013 | return 1; | |
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | static void nv_do_rx_refill(unsigned long data) | |
1018 | { | |
1019 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 1020 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1021 | |
f34ba4e1 AM |
1022 | |
1023 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1024 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1025 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
1026 | disable_irq(dev->irq); | |
d33a73c8 AA |
1027 | } else { |
1028 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1029 | } | |
1da177e4 | 1030 | if (nv_alloc_rx(dev)) { |
f34ba4e1 | 1031 | spin_lock(&np->lock); |
1da177e4 LT |
1032 | if (!np->in_shutdown) |
1033 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
f34ba4e1 | 1034 | spin_unlock(&np->lock); |
1da177e4 | 1035 | } |
f34ba4e1 AM |
1036 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
1037 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1038 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
1039 | enable_irq(dev->irq); | |
d33a73c8 AA |
1040 | } else { |
1041 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1042 | } | |
1da177e4 LT |
1043 | } |
1044 | ||
d81c0983 | 1045 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1046 | { |
ac9c1897 | 1047 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1048 | int i; |
1049 | ||
1da177e4 LT |
1050 | np->cur_rx = RX_RING; |
1051 | np->refill_rx = 0; | |
1052 | for (i = 0; i < RX_RING; i++) | |
ee73362c MS |
1053 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1054 | np->rx_ring.orig[i].FlagLen = 0; | |
1055 | else | |
1056 | np->rx_ring.ex[i].FlagLen = 0; | |
d81c0983 MS |
1057 | } |
1058 | ||
1059 | static void nv_init_tx(struct net_device *dev) | |
1060 | { | |
ac9c1897 | 1061 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
1062 | int i; |
1063 | ||
1064 | np->next_tx = np->nic_tx = 0; | |
ac9c1897 | 1065 | for (i = 0; i < TX_RING; i++) { |
ee73362c MS |
1066 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1067 | np->tx_ring.orig[i].FlagLen = 0; | |
1068 | else | |
1069 | np->tx_ring.ex[i].FlagLen = 0; | |
ac9c1897 | 1070 | np->tx_skbuff[i] = NULL; |
fa45459e | 1071 | np->tx_dma[i] = 0; |
ac9c1897 | 1072 | } |
d81c0983 MS |
1073 | } |
1074 | ||
1075 | static int nv_init_ring(struct net_device *dev) | |
1076 | { | |
1077 | nv_init_tx(dev); | |
1078 | nv_init_rx(dev); | |
1da177e4 LT |
1079 | return nv_alloc_rx(dev); |
1080 | } | |
1081 | ||
fa45459e | 1082 | static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
ac9c1897 AA |
1083 | { |
1084 | struct fe_priv *np = netdev_priv(dev); | |
fa45459e AA |
1085 | |
1086 | dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", | |
1087 | dev->name, skbnr); | |
1088 | ||
1089 | if (np->tx_dma[skbnr]) { | |
1090 | pci_unmap_page(np->pci_dev, np->tx_dma[skbnr], | |
1091 | np->tx_dma_len[skbnr], | |
1092 | PCI_DMA_TODEVICE); | |
1093 | np->tx_dma[skbnr] = 0; | |
1094 | } | |
1095 | ||
1096 | if (np->tx_skbuff[skbnr]) { | |
d33a73c8 | 1097 | dev_kfree_skb_any(np->tx_skbuff[skbnr]); |
fa45459e AA |
1098 | np->tx_skbuff[skbnr] = NULL; |
1099 | return 1; | |
1100 | } else { | |
1101 | return 0; | |
ac9c1897 | 1102 | } |
ac9c1897 AA |
1103 | } |
1104 | ||
1da177e4 LT |
1105 | static void nv_drain_tx(struct net_device *dev) |
1106 | { | |
ac9c1897 AA |
1107 | struct fe_priv *np = netdev_priv(dev); |
1108 | unsigned int i; | |
1109 | ||
1da177e4 | 1110 | for (i = 0; i < TX_RING; i++) { |
ee73362c MS |
1111 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1112 | np->tx_ring.orig[i].FlagLen = 0; | |
1113 | else | |
1114 | np->tx_ring.ex[i].FlagLen = 0; | |
fa45459e | 1115 | if (nv_release_txskb(dev, i)) |
1da177e4 | 1116 | np->stats.tx_dropped++; |
1da177e4 LT |
1117 | } |
1118 | } | |
1119 | ||
1120 | static void nv_drain_rx(struct net_device *dev) | |
1121 | { | |
ac9c1897 | 1122 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1123 | int i; |
1124 | for (i = 0; i < RX_RING; i++) { | |
ee73362c MS |
1125 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1126 | np->rx_ring.orig[i].FlagLen = 0; | |
1127 | else | |
1128 | np->rx_ring.ex[i].FlagLen = 0; | |
1da177e4 LT |
1129 | wmb(); |
1130 | if (np->rx_skbuff[i]) { | |
1131 | pci_unmap_single(np->pci_dev, np->rx_dma[i], | |
1836098f | 1132 | np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
1da177e4 LT |
1133 | PCI_DMA_FROMDEVICE); |
1134 | dev_kfree_skb(np->rx_skbuff[i]); | |
1135 | np->rx_skbuff[i] = NULL; | |
1136 | } | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | static void drain_ring(struct net_device *dev) | |
1141 | { | |
1142 | nv_drain_tx(dev); | |
1143 | nv_drain_rx(dev); | |
1144 | } | |
1145 | ||
1146 | /* | |
1147 | * nv_start_xmit: dev->hard_start_xmit function | |
1148 | * Called with dev->xmit_lock held. | |
1149 | */ | |
1150 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1151 | { | |
ac9c1897 | 1152 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 1153 | u32 tx_flags = 0; |
ac9c1897 AA |
1154 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
1155 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
fa45459e AA |
1156 | unsigned int nr = (np->next_tx - 1) % TX_RING; |
1157 | unsigned int start_nr = np->next_tx % TX_RING; | |
ac9c1897 | 1158 | unsigned int i; |
fa45459e AA |
1159 | u32 offset = 0; |
1160 | u32 bcnt; | |
1161 | u32 size = skb->len-skb->data_len; | |
1162 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
ee407b02 | 1163 | u32 tx_flags_vlan = 0; |
fa45459e AA |
1164 | |
1165 | /* add fragments to entries count */ | |
1166 | for (i = 0; i < fragments; i++) { | |
1167 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
1168 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
1169 | } | |
ac9c1897 AA |
1170 | |
1171 | spin_lock_irq(&np->lock); | |
1172 | ||
fa45459e | 1173 | if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) { |
ac9c1897 AA |
1174 | spin_unlock_irq(&np->lock); |
1175 | netif_stop_queue(dev); | |
1176 | return NETDEV_TX_BUSY; | |
1177 | } | |
1da177e4 | 1178 | |
fa45459e AA |
1179 | /* setup the header buffer */ |
1180 | do { | |
1181 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
1182 | nr = (nr + 1) % TX_RING; | |
1183 | ||
1184 | np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
1185 | PCI_DMA_TODEVICE); | |
1186 | np->tx_dma_len[nr] = bcnt; | |
1187 | ||
1188 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
1189 | np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); | |
1190 | np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); | |
1191 | } else { | |
1192 | np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; | |
1193 | np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; | |
1194 | np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); | |
1195 | } | |
1196 | tx_flags = np->tx_flags; | |
1197 | offset += bcnt; | |
1198 | size -= bcnt; | |
1199 | } while(size); | |
1200 | ||
1201 | /* setup the fragments */ | |
1202 | for (i = 0; i < fragments; i++) { | |
1203 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1204 | u32 size = frag->size; | |
1205 | offset = 0; | |
1206 | ||
1207 | do { | |
1208 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
1209 | nr = (nr + 1) % TX_RING; | |
1210 | ||
1211 | np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
1212 | PCI_DMA_TODEVICE); | |
1213 | np->tx_dma_len[nr] = bcnt; | |
1da177e4 | 1214 | |
ac9c1897 AA |
1215 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1216 | np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); | |
fa45459e | 1217 | np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
ac9c1897 AA |
1218 | } else { |
1219 | np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; | |
1220 | np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; | |
fa45459e | 1221 | np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
ac9c1897 | 1222 | } |
fa45459e AA |
1223 | offset += bcnt; |
1224 | size -= bcnt; | |
1225 | } while (size); | |
1226 | } | |
ac9c1897 | 1227 | |
fa45459e AA |
1228 | /* set last fragment flag */ |
1229 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
1230 | np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra); | |
1231 | } else { | |
1232 | np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra); | |
ac9c1897 AA |
1233 | } |
1234 | ||
fa45459e AA |
1235 | np->tx_skbuff[nr] = skb; |
1236 | ||
ac9c1897 AA |
1237 | #ifdef NETIF_F_TSO |
1238 | if (skb_shinfo(skb)->tso_size) | |
fa45459e | 1239 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 AA |
1240 | else |
1241 | #endif | |
fa45459e | 1242 | tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
ac9c1897 | 1243 | |
ee407b02 AA |
1244 | /* vlan tag */ |
1245 | if (np->vlangrp && vlan_tx_tag_present(skb)) { | |
1246 | tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb); | |
1247 | } | |
1248 | ||
fa45459e | 1249 | /* set tx flags */ |
ac9c1897 | 1250 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
fa45459e | 1251 | np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
ac9c1897 | 1252 | } else { |
ee407b02 | 1253 | np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan); |
fa45459e | 1254 | np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
ac9c1897 | 1255 | } |
1da177e4 | 1256 | |
fa45459e AA |
1257 | dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", |
1258 | dev->name, np->next_tx, entries, tx_flags_extra); | |
1da177e4 LT |
1259 | { |
1260 | int j; | |
1261 | for (j=0; j<64; j++) { | |
1262 | if ((j%16) == 0) | |
1263 | dprintk("\n%03x:", j); | |
1264 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
1265 | } | |
1266 | dprintk("\n"); | |
1267 | } | |
1268 | ||
fa45459e | 1269 | np->next_tx += entries; |
1da177e4 LT |
1270 | |
1271 | dev->trans_start = jiffies; | |
1da177e4 | 1272 | spin_unlock_irq(&np->lock); |
8a4ae7f2 | 1273 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
1da177e4 | 1274 | pci_push(get_hwbase(dev)); |
ac9c1897 | 1275 | return NETDEV_TX_OK; |
1da177e4 LT |
1276 | } |
1277 | ||
1278 | /* | |
1279 | * nv_tx_done: check for completed packets, release the skbs. | |
1280 | * | |
1281 | * Caller must own np->lock. | |
1282 | */ | |
1283 | static void nv_tx_done(struct net_device *dev) | |
1284 | { | |
ac9c1897 | 1285 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1286 | u32 Flags; |
ac9c1897 AA |
1287 | unsigned int i; |
1288 | struct sk_buff *skb; | |
1da177e4 LT |
1289 | |
1290 | while (np->nic_tx != np->next_tx) { | |
1291 | i = np->nic_tx % TX_RING; | |
1292 | ||
ee73362c MS |
1293 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1294 | Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen); | |
1295 | else | |
1296 | Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen); | |
1da177e4 LT |
1297 | |
1298 | dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", | |
1299 | dev->name, np->nic_tx, Flags); | |
1300 | if (Flags & NV_TX_VALID) | |
1301 | break; | |
1302 | if (np->desc_ver == DESC_VER_1) { | |
ac9c1897 AA |
1303 | if (Flags & NV_TX_LASTPACKET) { |
1304 | skb = np->tx_skbuff[i]; | |
1305 | if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| | |
1306 | NV_TX_UNDERFLOW|NV_TX_ERROR)) { | |
1307 | if (Flags & NV_TX_UNDERFLOW) | |
1308 | np->stats.tx_fifo_errors++; | |
1309 | if (Flags & NV_TX_CARRIERLOST) | |
1310 | np->stats.tx_carrier_errors++; | |
1311 | np->stats.tx_errors++; | |
1312 | } else { | |
1313 | np->stats.tx_packets++; | |
1314 | np->stats.tx_bytes += skb->len; | |
1315 | } | |
1da177e4 LT |
1316 | } |
1317 | } else { | |
ac9c1897 AA |
1318 | if (Flags & NV_TX2_LASTPACKET) { |
1319 | skb = np->tx_skbuff[i]; | |
1320 | if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| | |
1321 | NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { | |
1322 | if (Flags & NV_TX2_UNDERFLOW) | |
1323 | np->stats.tx_fifo_errors++; | |
1324 | if (Flags & NV_TX2_CARRIERLOST) | |
1325 | np->stats.tx_carrier_errors++; | |
1326 | np->stats.tx_errors++; | |
1327 | } else { | |
1328 | np->stats.tx_packets++; | |
1329 | np->stats.tx_bytes += skb->len; | |
1330 | } | |
1da177e4 LT |
1331 | } |
1332 | } | |
fa45459e | 1333 | nv_release_txskb(dev, i); |
1da177e4 LT |
1334 | np->nic_tx++; |
1335 | } | |
1336 | if (np->next_tx - np->nic_tx < TX_LIMIT_START) | |
1337 | netif_wake_queue(dev); | |
1338 | } | |
1339 | ||
1340 | /* | |
1341 | * nv_tx_timeout: dev->tx_timeout function | |
1342 | * Called with dev->xmit_lock held. | |
1343 | */ | |
1344 | static void nv_tx_timeout(struct net_device *dev) | |
1345 | { | |
ac9c1897 | 1346 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1347 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
1348 | u32 status; |
1349 | ||
1350 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1351 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
1352 | else | |
1353 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 1354 | |
d33a73c8 | 1355 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
1da177e4 | 1356 | |
c2dba06d MS |
1357 | { |
1358 | int i; | |
1359 | ||
1360 | printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n", | |
1361 | dev->name, (unsigned long)np->ring_addr, | |
1362 | np->next_tx, np->nic_tx); | |
1363 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); | |
86a0f043 | 1364 | for (i=0;i<=np->register_size;i+= 32) { |
c2dba06d MS |
1365 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
1366 | i, | |
1367 | readl(base + i + 0), readl(base + i + 4), | |
1368 | readl(base + i + 8), readl(base + i + 12), | |
1369 | readl(base + i + 16), readl(base + i + 20), | |
1370 | readl(base + i + 24), readl(base + i + 28)); | |
1371 | } | |
1372 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | |
1373 | for (i=0;i<TX_RING;i+= 4) { | |
ee73362c MS |
1374 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1375 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", | |
1376 | i, | |
1377 | le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), | |
1378 | le32_to_cpu(np->tx_ring.orig[i].FlagLen), | |
1379 | le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), | |
1380 | le32_to_cpu(np->tx_ring.orig[i+1].FlagLen), | |
1381 | le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer), | |
1382 | le32_to_cpu(np->tx_ring.orig[i+2].FlagLen), | |
1383 | le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer), | |
1384 | le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); | |
1385 | } else { | |
1386 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
1387 | i, | |
1388 | le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), | |
1389 | le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), | |
1390 | le32_to_cpu(np->tx_ring.ex[i].FlagLen), | |
1391 | le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh), | |
1392 | le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow), | |
1393 | le32_to_cpu(np->tx_ring.ex[i+1].FlagLen), | |
1394 | le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh), | |
1395 | le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow), | |
1396 | le32_to_cpu(np->tx_ring.ex[i+2].FlagLen), | |
1397 | le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh), | |
1398 | le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow), | |
1399 | le32_to_cpu(np->tx_ring.ex[i+3].FlagLen)); | |
1400 | } | |
c2dba06d MS |
1401 | } |
1402 | } | |
1403 | ||
1da177e4 LT |
1404 | spin_lock_irq(&np->lock); |
1405 | ||
1406 | /* 1) stop tx engine */ | |
1407 | nv_stop_tx(dev); | |
1408 | ||
1409 | /* 2) check that the packets were not sent already: */ | |
1410 | nv_tx_done(dev); | |
1411 | ||
1412 | /* 3) if there are dead entries: clear everything */ | |
1413 | if (np->next_tx != np->nic_tx) { | |
1414 | printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); | |
1415 | nv_drain_tx(dev); | |
1416 | np->next_tx = np->nic_tx = 0; | |
0832b25a | 1417 | setup_hw_rings(dev, NV_SETUP_TX_RING); |
1da177e4 LT |
1418 | netif_wake_queue(dev); |
1419 | } | |
1420 | ||
1421 | /* 4) restart tx engine */ | |
1422 | nv_start_tx(dev); | |
1423 | spin_unlock_irq(&np->lock); | |
1424 | } | |
1425 | ||
22c6d143 MS |
1426 | /* |
1427 | * Called when the nic notices a mismatch between the actual data len on the | |
1428 | * wire and the len indicated in the 802 header | |
1429 | */ | |
1430 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
1431 | { | |
1432 | int hdrlen; /* length of the 802 header */ | |
1433 | int protolen; /* length as stored in the proto field */ | |
1434 | ||
1435 | /* 1) calculate len according to header */ | |
1436 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { | |
1437 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); | |
1438 | hdrlen = VLAN_HLEN; | |
1439 | } else { | |
1440 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | |
1441 | hdrlen = ETH_HLEN; | |
1442 | } | |
1443 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | |
1444 | dev->name, datalen, protolen, hdrlen); | |
1445 | if (protolen > ETH_DATA_LEN) | |
1446 | return datalen; /* Value in proto field not a len, no checks possible */ | |
1447 | ||
1448 | protolen += hdrlen; | |
1449 | /* consistency checks: */ | |
1450 | if (datalen > ETH_ZLEN) { | |
1451 | if (datalen >= protolen) { | |
1452 | /* more data on wire than in 802 header, trim of | |
1453 | * additional data. | |
1454 | */ | |
1455 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
1456 | dev->name, protolen); | |
1457 | return protolen; | |
1458 | } else { | |
1459 | /* less data on wire than mentioned in header. | |
1460 | * Discard the packet. | |
1461 | */ | |
1462 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | |
1463 | dev->name); | |
1464 | return -1; | |
1465 | } | |
1466 | } else { | |
1467 | /* short packet. Accept only if 802 values are also short */ | |
1468 | if (protolen > ETH_ZLEN) { | |
1469 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | |
1470 | dev->name); | |
1471 | return -1; | |
1472 | } | |
1473 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
1474 | dev->name, datalen); | |
1475 | return datalen; | |
1476 | } | |
1477 | } | |
1478 | ||
1da177e4 LT |
1479 | static void nv_rx_process(struct net_device *dev) |
1480 | { | |
ac9c1897 | 1481 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1482 | u32 Flags; |
ee407b02 AA |
1483 | u32 vlanflags = 0; |
1484 | ||
1da177e4 LT |
1485 | |
1486 | for (;;) { | |
1487 | struct sk_buff *skb; | |
1488 | int len; | |
1489 | int i; | |
1490 | if (np->cur_rx - np->refill_rx >= RX_RING) | |
1491 | break; /* we scanned the whole ring - do not continue */ | |
1492 | ||
1493 | i = np->cur_rx % RX_RING; | |
ee73362c MS |
1494 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1495 | Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen); | |
1496 | len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); | |
1497 | } else { | |
1498 | Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen); | |
1499 | len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); | |
ee407b02 | 1500 | vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow); |
ee73362c | 1501 | } |
1da177e4 LT |
1502 | |
1503 | dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", | |
1504 | dev->name, np->cur_rx, Flags); | |
1505 | ||
1506 | if (Flags & NV_RX_AVAIL) | |
1507 | break; /* still owned by hardware, */ | |
1508 | ||
1509 | /* | |
1510 | * the packet is for us - immediately tear down the pci mapping. | |
1511 | * TODO: check if a prefetch of the first cacheline improves | |
1512 | * the performance. | |
1513 | */ | |
1514 | pci_unmap_single(np->pci_dev, np->rx_dma[i], | |
1836098f | 1515 | np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
1da177e4 LT |
1516 | PCI_DMA_FROMDEVICE); |
1517 | ||
1518 | { | |
1519 | int j; | |
1520 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags); | |
1521 | for (j=0; j<64; j++) { | |
1522 | if ((j%16) == 0) | |
1523 | dprintk("\n%03x:", j); | |
1524 | dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); | |
1525 | } | |
1526 | dprintk("\n"); | |
1527 | } | |
1528 | /* look at what we actually got: */ | |
1529 | if (np->desc_ver == DESC_VER_1) { | |
1530 | if (!(Flags & NV_RX_DESCRIPTORVALID)) | |
1531 | goto next_pkt; | |
1532 | ||
a971c324 AA |
1533 | if (Flags & NV_RX_ERROR) { |
1534 | if (Flags & NV_RX_MISSEDFRAME) { | |
1535 | np->stats.rx_missed_errors++; | |
1da177e4 LT |
1536 | np->stats.rx_errors++; |
1537 | goto next_pkt; | |
1538 | } | |
a971c324 AA |
1539 | if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
1540 | np->stats.rx_errors++; | |
1541 | goto next_pkt; | |
1542 | } | |
1543 | if (Flags & NV_RX_CRCERR) { | |
1544 | np->stats.rx_crc_errors++; | |
1545 | np->stats.rx_errors++; | |
1546 | goto next_pkt; | |
1547 | } | |
1548 | if (Flags & NV_RX_OVERFLOW) { | |
1549 | np->stats.rx_over_errors++; | |
1550 | np->stats.rx_errors++; | |
1551 | goto next_pkt; | |
1552 | } | |
1553 | if (Flags & NV_RX_ERROR4) { | |
1554 | len = nv_getlen(dev, np->rx_skbuff[i]->data, len); | |
1555 | if (len < 0) { | |
1556 | np->stats.rx_errors++; | |
1557 | goto next_pkt; | |
1558 | } | |
1559 | } | |
1560 | /* framing errors are soft errors. */ | |
1561 | if (Flags & NV_RX_FRAMINGERR) { | |
1562 | if (Flags & NV_RX_SUBSTRACT1) { | |
1563 | len--; | |
1564 | } | |
22c6d143 MS |
1565 | } |
1566 | } | |
1da177e4 LT |
1567 | } else { |
1568 | if (!(Flags & NV_RX2_DESCRIPTORVALID)) | |
1569 | goto next_pkt; | |
1570 | ||
a971c324 AA |
1571 | if (Flags & NV_RX2_ERROR) { |
1572 | if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { | |
1da177e4 LT |
1573 | np->stats.rx_errors++; |
1574 | goto next_pkt; | |
1575 | } | |
a971c324 AA |
1576 | if (Flags & NV_RX2_CRCERR) { |
1577 | np->stats.rx_crc_errors++; | |
1578 | np->stats.rx_errors++; | |
1579 | goto next_pkt; | |
1580 | } | |
1581 | if (Flags & NV_RX2_OVERFLOW) { | |
1582 | np->stats.rx_over_errors++; | |
1583 | np->stats.rx_errors++; | |
1584 | goto next_pkt; | |
1585 | } | |
1586 | if (Flags & NV_RX2_ERROR4) { | |
1587 | len = nv_getlen(dev, np->rx_skbuff[i]->data, len); | |
1588 | if (len < 0) { | |
1589 | np->stats.rx_errors++; | |
1590 | goto next_pkt; | |
1591 | } | |
1592 | } | |
1593 | /* framing errors are soft errors */ | |
1594 | if (Flags & NV_RX2_FRAMINGERR) { | |
1595 | if (Flags & NV_RX2_SUBSTRACT1) { | |
1596 | len--; | |
1597 | } | |
22c6d143 MS |
1598 | } |
1599 | } | |
1da177e4 LT |
1600 | Flags &= NV_RX2_CHECKSUMMASK; |
1601 | if (Flags == NV_RX2_CHECKSUMOK1 || | |
1602 | Flags == NV_RX2_CHECKSUMOK2 || | |
1603 | Flags == NV_RX2_CHECKSUMOK3) { | |
1604 | dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); | |
1605 | np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; | |
1606 | } else { | |
1607 | dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); | |
1608 | } | |
1609 | } | |
1610 | /* got a valid packet - forward it to the network core */ | |
1611 | skb = np->rx_skbuff[i]; | |
1612 | np->rx_skbuff[i] = NULL; | |
1613 | ||
1614 | skb_put(skb, len); | |
1615 | skb->protocol = eth_type_trans(skb, dev); | |
1616 | dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", | |
1617 | dev->name, np->cur_rx, len, skb->protocol); | |
ee407b02 AA |
1618 | if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) { |
1619 | vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); | |
1620 | } else { | |
1621 | netif_rx(skb); | |
1622 | } | |
1da177e4 LT |
1623 | dev->last_rx = jiffies; |
1624 | np->stats.rx_packets++; | |
1625 | np->stats.rx_bytes += len; | |
1626 | next_pkt: | |
1627 | np->cur_rx++; | |
1628 | } | |
1629 | } | |
1630 | ||
d81c0983 MS |
1631 | static void set_bufsize(struct net_device *dev) |
1632 | { | |
1633 | struct fe_priv *np = netdev_priv(dev); | |
1634 | ||
1635 | if (dev->mtu <= ETH_DATA_LEN) | |
1636 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
1637 | else | |
1638 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
1639 | } | |
1640 | ||
1da177e4 LT |
1641 | /* |
1642 | * nv_change_mtu: dev->change_mtu function | |
1643 | * Called with dev_base_lock held for read. | |
1644 | */ | |
1645 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
1646 | { | |
ac9c1897 | 1647 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
1648 | int old_mtu; |
1649 | ||
1650 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 1651 | return -EINVAL; |
d81c0983 MS |
1652 | |
1653 | old_mtu = dev->mtu; | |
1da177e4 | 1654 | dev->mtu = new_mtu; |
d81c0983 MS |
1655 | |
1656 | /* return early if the buffer sizes will not change */ | |
1657 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
1658 | return 0; | |
1659 | if (old_mtu == new_mtu) | |
1660 | return 0; | |
1661 | ||
1662 | /* synchronized against open : rtnl_lock() held by caller */ | |
1663 | if (netif_running(dev)) { | |
25097d4b | 1664 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
1665 | /* |
1666 | * It seems that the nic preloads valid ring entries into an | |
1667 | * internal buffer. The procedure for flushing everything is | |
1668 | * guessed, there is probably a simpler approach. | |
1669 | * Changing the MTU is a rare event, it shouldn't matter. | |
1670 | */ | |
f34ba4e1 AM |
1671 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
1672 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1673 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
1674 | disable_irq(dev->irq); | |
1675 | } else { | |
1676 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1677 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1678 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1679 | } | |
d81c0983 MS |
1680 | spin_lock_bh(&dev->xmit_lock); |
1681 | spin_lock(&np->lock); | |
1682 | /* stop engines */ | |
1683 | nv_stop_rx(dev); | |
1684 | nv_stop_tx(dev); | |
1685 | nv_txrx_reset(dev); | |
1686 | /* drain rx queue */ | |
1687 | nv_drain_rx(dev); | |
1688 | nv_drain_tx(dev); | |
1689 | /* reinit driver view of the rx queue */ | |
1690 | nv_init_rx(dev); | |
1691 | nv_init_tx(dev); | |
1692 | /* alloc new rx buffers */ | |
1693 | set_bufsize(dev); | |
1694 | if (nv_alloc_rx(dev)) { | |
1695 | if (!np->in_shutdown) | |
1696 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
1697 | } | |
1698 | /* reinit nic view of the rx queue */ | |
1699 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 1700 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
d81c0983 MS |
1701 | writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
1702 | base + NvRegRingSizes); | |
1703 | pci_push(base); | |
8a4ae7f2 | 1704 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
1705 | pci_push(base); |
1706 | ||
1707 | /* restart rx engine */ | |
1708 | nv_start_rx(dev); | |
1709 | nv_start_tx(dev); | |
1710 | spin_unlock(&np->lock); | |
1711 | spin_unlock_bh(&dev->xmit_lock); | |
f34ba4e1 AM |
1712 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
1713 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1714 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
1715 | enable_irq(dev->irq); | |
1716 | } else { | |
1717 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1718 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1719 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1720 | } | |
d81c0983 | 1721 | } |
1da177e4 LT |
1722 | return 0; |
1723 | } | |
1724 | ||
72b31782 MS |
1725 | static void nv_copy_mac_to_hw(struct net_device *dev) |
1726 | { | |
25097d4b | 1727 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
1728 | u32 mac[2]; |
1729 | ||
1730 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
1731 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
1732 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
1733 | ||
1734 | writel(mac[0], base + NvRegMacAddrA); | |
1735 | writel(mac[1], base + NvRegMacAddrB); | |
1736 | } | |
1737 | ||
1738 | /* | |
1739 | * nv_set_mac_address: dev->set_mac_address function | |
1740 | * Called with rtnl_lock() held. | |
1741 | */ | |
1742 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
1743 | { | |
ac9c1897 | 1744 | struct fe_priv *np = netdev_priv(dev); |
72b31782 MS |
1745 | struct sockaddr *macaddr = (struct sockaddr*)addr; |
1746 | ||
1747 | if(!is_valid_ether_addr(macaddr->sa_data)) | |
1748 | return -EADDRNOTAVAIL; | |
1749 | ||
1750 | /* synchronized against open : rtnl_lock() held by caller */ | |
1751 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
1752 | ||
1753 | if (netif_running(dev)) { | |
1754 | spin_lock_bh(&dev->xmit_lock); | |
1755 | spin_lock_irq(&np->lock); | |
1756 | ||
1757 | /* stop rx engine */ | |
1758 | nv_stop_rx(dev); | |
1759 | ||
1760 | /* set mac address */ | |
1761 | nv_copy_mac_to_hw(dev); | |
1762 | ||
1763 | /* restart rx engine */ | |
1764 | nv_start_rx(dev); | |
1765 | spin_unlock_irq(&np->lock); | |
1766 | spin_unlock_bh(&dev->xmit_lock); | |
1767 | } else { | |
1768 | nv_copy_mac_to_hw(dev); | |
1769 | } | |
1770 | return 0; | |
1771 | } | |
1772 | ||
1da177e4 LT |
1773 | /* |
1774 | * nv_set_multicast: dev->set_multicast function | |
1775 | * Called with dev->xmit_lock held. | |
1776 | */ | |
1777 | static void nv_set_multicast(struct net_device *dev) | |
1778 | { | |
ac9c1897 | 1779 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1780 | u8 __iomem *base = get_hwbase(dev); |
1781 | u32 addr[2]; | |
1782 | u32 mask[2]; | |
1783 | u32 pff; | |
1784 | ||
1785 | memset(addr, 0, sizeof(addr)); | |
1786 | memset(mask, 0, sizeof(mask)); | |
1787 | ||
1788 | if (dev->flags & IFF_PROMISC) { | |
1789 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); | |
1790 | pff = NVREG_PFF_PROMISC; | |
1791 | } else { | |
1792 | pff = NVREG_PFF_MYADDR; | |
1793 | ||
1794 | if (dev->flags & IFF_ALLMULTI || dev->mc_list) { | |
1795 | u32 alwaysOff[2]; | |
1796 | u32 alwaysOn[2]; | |
1797 | ||
1798 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
1799 | if (dev->flags & IFF_ALLMULTI) { | |
1800 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
1801 | } else { | |
1802 | struct dev_mc_list *walk; | |
1803 | ||
1804 | walk = dev->mc_list; | |
1805 | while (walk != NULL) { | |
1806 | u32 a, b; | |
1807 | a = le32_to_cpu(*(u32 *) walk->dmi_addr); | |
1808 | b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); | |
1809 | alwaysOn[0] &= a; | |
1810 | alwaysOff[0] &= ~a; | |
1811 | alwaysOn[1] &= b; | |
1812 | alwaysOff[1] &= ~b; | |
1813 | walk = walk->next; | |
1814 | } | |
1815 | } | |
1816 | addr[0] = alwaysOn[0]; | |
1817 | addr[1] = alwaysOn[1]; | |
1818 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
1819 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
1820 | } | |
1821 | } | |
1822 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
1823 | pff |= NVREG_PFF_ALWAYS; | |
1824 | spin_lock_irq(&np->lock); | |
1825 | nv_stop_rx(dev); | |
1826 | writel(addr[0], base + NvRegMulticastAddrA); | |
1827 | writel(addr[1], base + NvRegMulticastAddrB); | |
1828 | writel(mask[0], base + NvRegMulticastMaskA); | |
1829 | writel(mask[1], base + NvRegMulticastMaskB); | |
1830 | writel(pff, base + NvRegPacketFilterFlags); | |
1831 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | |
1832 | dev->name); | |
1833 | nv_start_rx(dev); | |
1834 | spin_unlock_irq(&np->lock); | |
1835 | } | |
1836 | ||
4ea7f299 AA |
1837 | /** |
1838 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
1839 | * @dev: Network device to be configured | |
1840 | * | |
1841 | * The function queries the PHY and checks if there is a link partner. | |
1842 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
1843 | * set to 10 MBit HD. | |
1844 | * | |
1845 | * The function returns 0 if there is no link partner and 1 if there is | |
1846 | * a good link partner. | |
1847 | */ | |
1da177e4 LT |
1848 | static int nv_update_linkspeed(struct net_device *dev) |
1849 | { | |
ac9c1897 | 1850 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1851 | u8 __iomem *base = get_hwbase(dev); |
1852 | int adv, lpa; | |
1853 | int newls = np->linkspeed; | |
1854 | int newdup = np->duplex; | |
1855 | int mii_status; | |
1856 | int retval = 0; | |
1857 | u32 control_1000, status_1000, phyreg; | |
1858 | ||
1859 | /* BMSR_LSTATUS is latched, read it twice: | |
1860 | * we want the current value. | |
1861 | */ | |
1862 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1863 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1864 | ||
1865 | if (!(mii_status & BMSR_LSTATUS)) { | |
1866 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | |
1867 | dev->name); | |
1868 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1869 | newdup = 0; | |
1870 | retval = 0; | |
1871 | goto set_speed; | |
1872 | } | |
1873 | ||
1874 | if (np->autoneg == 0) { | |
1875 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | |
1876 | dev->name, np->fixed_mode); | |
1877 | if (np->fixed_mode & LPA_100FULL) { | |
1878 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
1879 | newdup = 1; | |
1880 | } else if (np->fixed_mode & LPA_100HALF) { | |
1881 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
1882 | newdup = 0; | |
1883 | } else if (np->fixed_mode & LPA_10FULL) { | |
1884 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1885 | newdup = 1; | |
1886 | } else { | |
1887 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1888 | newdup = 0; | |
1889 | } | |
1890 | retval = 1; | |
1891 | goto set_speed; | |
1892 | } | |
1893 | /* check auto negotiation is complete */ | |
1894 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
1895 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
1896 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1897 | newdup = 0; | |
1898 | retval = 0; | |
1899 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | |
1900 | goto set_speed; | |
1901 | } | |
1902 | ||
1903 | retval = 1; | |
1904 | if (np->gigabit == PHY_GIGABIT) { | |
1905 | control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); | |
1906 | status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ); | |
1907 | ||
1908 | if ((control_1000 & ADVERTISE_1000FULL) && | |
1909 | (status_1000 & LPA_1000FULL)) { | |
1910 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | |
1911 | dev->name); | |
1912 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | |
1913 | newdup = 1; | |
1914 | goto set_speed; | |
1915 | } | |
1916 | } | |
1917 | ||
1918 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
1919 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
1920 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | |
1921 | dev->name, adv, lpa); | |
1922 | ||
1923 | /* FIXME: handle parallel detection properly */ | |
1924 | lpa = lpa & adv; | |
1925 | if (lpa & LPA_100FULL) { | |
1926 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
1927 | newdup = 1; | |
1928 | } else if (lpa & LPA_100HALF) { | |
1929 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
1930 | newdup = 0; | |
1931 | } else if (lpa & LPA_10FULL) { | |
1932 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1933 | newdup = 1; | |
1934 | } else if (lpa & LPA_10HALF) { | |
1935 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1936 | newdup = 0; | |
1937 | } else { | |
1938 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa); | |
1939 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
1940 | newdup = 0; | |
1941 | } | |
1942 | ||
1943 | set_speed: | |
1944 | if (np->duplex == newdup && np->linkspeed == newls) | |
1945 | return retval; | |
1946 | ||
1947 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | |
1948 | dev->name, np->linkspeed, np->duplex, newls, newdup); | |
1949 | ||
1950 | np->duplex = newdup; | |
1951 | np->linkspeed = newls; | |
1952 | ||
1953 | if (np->gigabit == PHY_GIGABIT) { | |
1954 | phyreg = readl(base + NvRegRandomSeed); | |
1955 | phyreg &= ~(0x3FF00); | |
1956 | if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) | |
1957 | phyreg |= NVREG_RNDSEED_FORCE3; | |
1958 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) | |
1959 | phyreg |= NVREG_RNDSEED_FORCE2; | |
1960 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) | |
1961 | phyreg |= NVREG_RNDSEED_FORCE; | |
1962 | writel(phyreg, base + NvRegRandomSeed); | |
1963 | } | |
1964 | ||
1965 | phyreg = readl(base + NvRegPhyInterface); | |
1966 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
1967 | if (np->duplex == 0) | |
1968 | phyreg |= PHY_HALF; | |
1969 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
1970 | phyreg |= PHY_100; | |
1971 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
1972 | phyreg |= PHY_1000; | |
1973 | writel(phyreg, base + NvRegPhyInterface); | |
1974 | ||
1975 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), | |
1976 | base + NvRegMisc1); | |
1977 | pci_push(base); | |
1978 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1979 | pci_push(base); | |
1980 | ||
1981 | return retval; | |
1982 | } | |
1983 | ||
1984 | static void nv_linkchange(struct net_device *dev) | |
1985 | { | |
1986 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 1987 | if (!netif_carrier_ok(dev)) { |
1da177e4 LT |
1988 | netif_carrier_on(dev); |
1989 | printk(KERN_INFO "%s: link up.\n", dev->name); | |
4ea7f299 | 1990 | nv_start_rx(dev); |
1da177e4 | 1991 | } |
1da177e4 LT |
1992 | } else { |
1993 | if (netif_carrier_ok(dev)) { | |
1994 | netif_carrier_off(dev); | |
1995 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
1996 | nv_stop_rx(dev); | |
1997 | } | |
1998 | } | |
1999 | } | |
2000 | ||
2001 | static void nv_link_irq(struct net_device *dev) | |
2002 | { | |
2003 | u8 __iomem *base = get_hwbase(dev); | |
2004 | u32 miistat; | |
2005 | ||
2006 | miistat = readl(base + NvRegMIIStatus); | |
2007 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
2008 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); | |
2009 | ||
2010 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
2011 | nv_linkchange(dev); | |
2012 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | |
2013 | } | |
2014 | ||
2015 | static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) | |
2016 | { | |
2017 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 2018 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2019 | u8 __iomem *base = get_hwbase(dev); |
2020 | u32 events; | |
2021 | int i; | |
2022 | ||
2023 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | |
2024 | ||
2025 | for (i=0; ; i++) { | |
d33a73c8 AA |
2026 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
2027 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
2028 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
2029 | } else { | |
2030 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2031 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
2032 | } | |
1da177e4 LT |
2033 | pci_push(base); |
2034 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
2035 | if (!(events & np->irqmask)) | |
2036 | break; | |
2037 | ||
a971c324 AA |
2038 | spin_lock(&np->lock); |
2039 | nv_tx_done(dev); | |
2040 | spin_unlock(&np->lock); | |
2041 | ||
2042 | nv_rx_process(dev); | |
2043 | if (nv_alloc_rx(dev)) { | |
1da177e4 | 2044 | spin_lock(&np->lock); |
a971c324 AA |
2045 | if (!np->in_shutdown) |
2046 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
1da177e4 LT |
2047 | spin_unlock(&np->lock); |
2048 | } | |
a971c324 | 2049 | |
1da177e4 LT |
2050 | if (events & NVREG_IRQ_LINK) { |
2051 | spin_lock(&np->lock); | |
2052 | nv_link_irq(dev); | |
2053 | spin_unlock(&np->lock); | |
2054 | } | |
2055 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
2056 | spin_lock(&np->lock); | |
2057 | nv_linkchange(dev); | |
2058 | spin_unlock(&np->lock); | |
2059 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
2060 | } | |
2061 | if (events & (NVREG_IRQ_TX_ERR)) { | |
2062 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", | |
2063 | dev->name, events); | |
2064 | } | |
2065 | if (events & (NVREG_IRQ_UNKNOWN)) { | |
2066 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", | |
2067 | dev->name, events); | |
2068 | } | |
2069 | if (i > max_interrupt_work) { | |
2070 | spin_lock(&np->lock); | |
2071 | /* disable interrupts on the nic */ | |
d33a73c8 AA |
2072 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
2073 | writel(0, base + NvRegIrqMask); | |
2074 | else | |
2075 | writel(np->irqmask, base + NvRegIrqMask); | |
1da177e4 LT |
2076 | pci_push(base); |
2077 | ||
d33a73c8 AA |
2078 | if (!np->in_shutdown) { |
2079 | np->nic_poll_irq = np->irqmask; | |
1da177e4 | 2080 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
d33a73c8 | 2081 | } |
1da177e4 LT |
2082 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
2083 | spin_unlock(&np->lock); | |
2084 | break; | |
2085 | } | |
2086 | ||
2087 | } | |
2088 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); | |
2089 | ||
2090 | return IRQ_RETVAL(i); | |
2091 | } | |
2092 | ||
d33a73c8 AA |
2093 | static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs) |
2094 | { | |
2095 | struct net_device *dev = (struct net_device *) data; | |
2096 | struct fe_priv *np = netdev_priv(dev); | |
2097 | u8 __iomem *base = get_hwbase(dev); | |
2098 | u32 events; | |
2099 | int i; | |
2100 | ||
2101 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | |
2102 | ||
2103 | for (i=0; ; i++) { | |
2104 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; | |
2105 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
2106 | pci_push(base); | |
2107 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); | |
2108 | if (!(events & np->irqmask)) | |
2109 | break; | |
2110 | ||
f34ba4e1 | 2111 | spin_lock(&np->lock); |
d33a73c8 | 2112 | nv_tx_done(dev); |
f34ba4e1 | 2113 | spin_unlock(&np->lock); |
d33a73c8 AA |
2114 | |
2115 | if (events & (NVREG_IRQ_TX_ERR)) { | |
2116 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", | |
2117 | dev->name, events); | |
2118 | } | |
2119 | if (i > max_interrupt_work) { | |
f34ba4e1 | 2120 | spin_lock(&np->lock); |
d33a73c8 AA |
2121 | /* disable interrupts on the nic */ |
2122 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
2123 | pci_push(base); | |
2124 | ||
2125 | if (!np->in_shutdown) { | |
2126 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
2127 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2128 | } | |
2129 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); | |
f34ba4e1 | 2130 | spin_unlock(&np->lock); |
d33a73c8 AA |
2131 | break; |
2132 | } | |
2133 | ||
2134 | } | |
2135 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | |
2136 | ||
2137 | return IRQ_RETVAL(i); | |
2138 | } | |
2139 | ||
2140 | static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) | |
2141 | { | |
2142 | struct net_device *dev = (struct net_device *) data; | |
2143 | struct fe_priv *np = netdev_priv(dev); | |
2144 | u8 __iomem *base = get_hwbase(dev); | |
2145 | u32 events; | |
2146 | int i; | |
2147 | ||
2148 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | |
2149 | ||
2150 | for (i=0; ; i++) { | |
2151 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
2152 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
2153 | pci_push(base); | |
2154 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); | |
2155 | if (!(events & np->irqmask)) | |
2156 | break; | |
2157 | ||
2158 | nv_rx_process(dev); | |
2159 | if (nv_alloc_rx(dev)) { | |
f34ba4e1 | 2160 | spin_lock(&np->lock); |
d33a73c8 AA |
2161 | if (!np->in_shutdown) |
2162 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
f34ba4e1 | 2163 | spin_unlock(&np->lock); |
d33a73c8 AA |
2164 | } |
2165 | ||
2166 | if (i > max_interrupt_work) { | |
f34ba4e1 | 2167 | spin_lock(&np->lock); |
d33a73c8 AA |
2168 | /* disable interrupts on the nic */ |
2169 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
2170 | pci_push(base); | |
2171 | ||
2172 | if (!np->in_shutdown) { | |
2173 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
2174 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2175 | } | |
2176 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); | |
f34ba4e1 | 2177 | spin_unlock(&np->lock); |
d33a73c8 AA |
2178 | break; |
2179 | } | |
2180 | ||
2181 | } | |
2182 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | |
2183 | ||
2184 | return IRQ_RETVAL(i); | |
2185 | } | |
2186 | ||
2187 | static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) | |
2188 | { | |
2189 | struct net_device *dev = (struct net_device *) data; | |
2190 | struct fe_priv *np = netdev_priv(dev); | |
2191 | u8 __iomem *base = get_hwbase(dev); | |
2192 | u32 events; | |
2193 | int i; | |
2194 | ||
2195 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | |
2196 | ||
2197 | for (i=0; ; i++) { | |
2198 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; | |
2199 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
2200 | pci_push(base); | |
2201 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
2202 | if (!(events & np->irqmask)) | |
2203 | break; | |
2204 | ||
2205 | if (events & NVREG_IRQ_LINK) { | |
f34ba4e1 | 2206 | spin_lock(&np->lock); |
d33a73c8 | 2207 | nv_link_irq(dev); |
f34ba4e1 | 2208 | spin_unlock(&np->lock); |
d33a73c8 AA |
2209 | } |
2210 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
f34ba4e1 | 2211 | spin_lock(&np->lock); |
d33a73c8 | 2212 | nv_linkchange(dev); |
f34ba4e1 | 2213 | spin_unlock(&np->lock); |
d33a73c8 AA |
2214 | np->link_timeout = jiffies + LINK_TIMEOUT; |
2215 | } | |
2216 | if (events & (NVREG_IRQ_UNKNOWN)) { | |
2217 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", | |
2218 | dev->name, events); | |
2219 | } | |
2220 | if (i > max_interrupt_work) { | |
f34ba4e1 | 2221 | spin_lock(&np->lock); |
d33a73c8 AA |
2222 | /* disable interrupts on the nic */ |
2223 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
2224 | pci_push(base); | |
2225 | ||
2226 | if (!np->in_shutdown) { | |
2227 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
2228 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
2229 | } | |
2230 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); | |
f34ba4e1 | 2231 | spin_unlock(&np->lock); |
d33a73c8 AA |
2232 | break; |
2233 | } | |
2234 | ||
2235 | } | |
2236 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | |
2237 | ||
2238 | return IRQ_RETVAL(i); | |
2239 | } | |
2240 | ||
1da177e4 LT |
2241 | static void nv_do_nic_poll(unsigned long data) |
2242 | { | |
2243 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 2244 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2245 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2246 | u32 mask = 0; |
1da177e4 | 2247 | |
1da177e4 | 2248 | /* |
d33a73c8 | 2249 | * First disable irq(s) and then |
1da177e4 LT |
2250 | * reenable interrupts on the nic, we have to do this before calling |
2251 | * nv_nic_irq because that may decide to do otherwise | |
2252 | */ | |
d33a73c8 | 2253 | |
f34ba4e1 AM |
2254 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
2255 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
2256 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
2257 | disable_irq(dev->irq); | |
d33a73c8 AA |
2258 | mask = np->irqmask; |
2259 | } else { | |
2260 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
2261 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
2262 | mask |= NVREG_IRQ_RX_ALL; | |
2263 | } | |
2264 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
2265 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
2266 | mask |= NVREG_IRQ_TX_ALL; | |
2267 | } | |
2268 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
2269 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
2270 | mask |= NVREG_IRQ_OTHER; | |
2271 | } | |
2272 | } | |
2273 | np->nic_poll_irq = 0; | |
2274 | ||
2275 | /* FIXME: Do we need synchronize_irq(dev->irq) here? */ | |
2276 | ||
2277 | writel(mask, base + NvRegIrqMask); | |
1da177e4 | 2278 | pci_push(base); |
d33a73c8 | 2279 | |
f34ba4e1 AM |
2280 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
2281 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
2282 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) { | |
d33a73c8 | 2283 | nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); |
f34ba4e1 | 2284 | enable_irq(dev->irq); |
d33a73c8 AA |
2285 | } else { |
2286 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
2287 | nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL); | |
2288 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
2289 | } | |
2290 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
2291 | nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL); | |
2292 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
2293 | } | |
2294 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
2295 | nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL); | |
2296 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
2297 | } | |
2298 | } | |
1da177e4 LT |
2299 | } |
2300 | ||
2918c35d MS |
2301 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2302 | static void nv_poll_controller(struct net_device *dev) | |
2303 | { | |
2304 | nv_do_nic_poll((unsigned long) dev); | |
2305 | } | |
2306 | #endif | |
2307 | ||
1da177e4 LT |
2308 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
2309 | { | |
ac9c1897 | 2310 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2311 | strcpy(info->driver, "forcedeth"); |
2312 | strcpy(info->version, FORCEDETH_VERSION); | |
2313 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
2314 | } | |
2315 | ||
2316 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
2317 | { | |
ac9c1897 | 2318 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2319 | wolinfo->supported = WAKE_MAGIC; |
2320 | ||
2321 | spin_lock_irq(&np->lock); | |
2322 | if (np->wolenabled) | |
2323 | wolinfo->wolopts = WAKE_MAGIC; | |
2324 | spin_unlock_irq(&np->lock); | |
2325 | } | |
2326 | ||
2327 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
2328 | { | |
ac9c1897 | 2329 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2330 | u8 __iomem *base = get_hwbase(dev); |
2331 | ||
2332 | spin_lock_irq(&np->lock); | |
2333 | if (wolinfo->wolopts == 0) { | |
2334 | writel(0, base + NvRegWakeUpFlags); | |
2335 | np->wolenabled = 0; | |
2336 | } | |
2337 | if (wolinfo->wolopts & WAKE_MAGIC) { | |
2338 | writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags); | |
2339 | np->wolenabled = 1; | |
2340 | } | |
2341 | spin_unlock_irq(&np->lock); | |
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2346 | { | |
2347 | struct fe_priv *np = netdev_priv(dev); | |
2348 | int adv; | |
2349 | ||
2350 | spin_lock_irq(&np->lock); | |
2351 | ecmd->port = PORT_MII; | |
2352 | if (!netif_running(dev)) { | |
2353 | /* We do not track link speed / duplex setting if the | |
2354 | * interface is disabled. Force a link check */ | |
2355 | nv_update_linkspeed(dev); | |
2356 | } | |
2357 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { | |
2358 | case NVREG_LINKSPEED_10: | |
2359 | ecmd->speed = SPEED_10; | |
2360 | break; | |
2361 | case NVREG_LINKSPEED_100: | |
2362 | ecmd->speed = SPEED_100; | |
2363 | break; | |
2364 | case NVREG_LINKSPEED_1000: | |
2365 | ecmd->speed = SPEED_1000; | |
2366 | break; | |
2367 | } | |
2368 | ecmd->duplex = DUPLEX_HALF; | |
2369 | if (np->duplex) | |
2370 | ecmd->duplex = DUPLEX_FULL; | |
2371 | ||
2372 | ecmd->autoneg = np->autoneg; | |
2373 | ||
2374 | ecmd->advertising = ADVERTISED_MII; | |
2375 | if (np->autoneg) { | |
2376 | ecmd->advertising |= ADVERTISED_Autoneg; | |
2377 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
2378 | } else { | |
2379 | adv = np->fixed_mode; | |
2380 | } | |
2381 | if (adv & ADVERTISE_10HALF) | |
2382 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
2383 | if (adv & ADVERTISE_10FULL) | |
2384 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
2385 | if (adv & ADVERTISE_100HALF) | |
2386 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
2387 | if (adv & ADVERTISE_100FULL) | |
2388 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
2389 | if (np->autoneg && np->gigabit == PHY_GIGABIT) { | |
2390 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); | |
2391 | if (adv & ADVERTISE_1000FULL) | |
2392 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
2393 | } | |
2394 | ||
2395 | ecmd->supported = (SUPPORTED_Autoneg | | |
2396 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
2397 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
2398 | SUPPORTED_MII); | |
2399 | if (np->gigabit == PHY_GIGABIT) | |
2400 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
2401 | ||
2402 | ecmd->phy_address = np->phyaddr; | |
2403 | ecmd->transceiver = XCVR_EXTERNAL; | |
2404 | ||
2405 | /* ignore maxtxpkt, maxrxpkt for now */ | |
2406 | spin_unlock_irq(&np->lock); | |
2407 | return 0; | |
2408 | } | |
2409 | ||
2410 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2411 | { | |
2412 | struct fe_priv *np = netdev_priv(dev); | |
2413 | ||
2414 | if (ecmd->port != PORT_MII) | |
2415 | return -EINVAL; | |
2416 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
2417 | return -EINVAL; | |
2418 | if (ecmd->phy_address != np->phyaddr) { | |
2419 | /* TODO: support switching between multiple phys. Should be | |
2420 | * trivial, but not enabled due to lack of test hardware. */ | |
2421 | return -EINVAL; | |
2422 | } | |
2423 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2424 | u32 mask; | |
2425 | ||
2426 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
2427 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
2428 | if (np->gigabit == PHY_GIGABIT) | |
2429 | mask |= ADVERTISED_1000baseT_Full; | |
2430 | ||
2431 | if ((ecmd->advertising & mask) == 0) | |
2432 | return -EINVAL; | |
2433 | ||
2434 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
2435 | /* Note: autonegotiation disable, speed 1000 intentionally | |
2436 | * forbidden - noone should need that. */ | |
2437 | ||
2438 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
2439 | return -EINVAL; | |
2440 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
2441 | return -EINVAL; | |
2442 | } else { | |
2443 | return -EINVAL; | |
2444 | } | |
2445 | ||
2446 | spin_lock_irq(&np->lock); | |
2447 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2448 | int adv, bmcr; | |
2449 | ||
2450 | np->autoneg = 1; | |
2451 | ||
2452 | /* advertise only what has been requested */ | |
2453 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
2454 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); | |
2455 | if (ecmd->advertising & ADVERTISED_10baseT_Half) | |
2456 | adv |= ADVERTISE_10HALF; | |
2457 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
2458 | adv |= ADVERTISE_10FULL; | |
2459 | if (ecmd->advertising & ADVERTISED_100baseT_Half) | |
2460 | adv |= ADVERTISE_100HALF; | |
2461 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
2462 | adv |= ADVERTISE_100FULL; | |
2463 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
2464 | ||
2465 | if (np->gigabit == PHY_GIGABIT) { | |
2466 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); | |
2467 | adv &= ~ADVERTISE_1000FULL; | |
2468 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
2469 | adv |= ADVERTISE_1000FULL; | |
2470 | mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); | |
2471 | } | |
2472 | ||
2473 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
2474 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
2475 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
2476 | ||
2477 | } else { | |
2478 | int adv, bmcr; | |
2479 | ||
2480 | np->autoneg = 0; | |
2481 | ||
2482 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
2483 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); | |
2484 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) | |
2485 | adv |= ADVERTISE_10HALF; | |
2486 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
2487 | adv |= ADVERTISE_10FULL; | |
2488 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) | |
2489 | adv |= ADVERTISE_100HALF; | |
2490 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
2491 | adv |= ADVERTISE_100FULL; | |
2492 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
2493 | np->fixed_mode = adv; | |
2494 | ||
2495 | if (np->gigabit == PHY_GIGABIT) { | |
2496 | adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); | |
2497 | adv &= ~ADVERTISE_1000FULL; | |
2498 | mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); | |
2499 | } | |
2500 | ||
2501 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
2502 | bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX); | |
2503 | if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
2504 | bmcr |= BMCR_FULLDPLX; | |
2505 | if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL)) | |
2506 | bmcr |= BMCR_SPEED100; | |
2507 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
2508 | ||
2509 | if (netif_running(dev)) { | |
2510 | /* Wait a bit and then reconfigure the nic. */ | |
2511 | udelay(10); | |
2512 | nv_linkchange(dev); | |
2513 | } | |
2514 | } | |
2515 | spin_unlock_irq(&np->lock); | |
2516 | ||
2517 | return 0; | |
2518 | } | |
2519 | ||
dc8216c1 | 2520 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
2521 | |
2522 | static int nv_get_regs_len(struct net_device *dev) | |
2523 | { | |
86a0f043 AA |
2524 | struct fe_priv *np = netdev_priv(dev); |
2525 | return np->register_size; | |
dc8216c1 MS |
2526 | } |
2527 | ||
2528 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
2529 | { | |
ac9c1897 | 2530 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
2531 | u8 __iomem *base = get_hwbase(dev); |
2532 | u32 *rbuf = buf; | |
2533 | int i; | |
2534 | ||
2535 | regs->version = FORCEDETH_REGS_VER; | |
2536 | spin_lock_irq(&np->lock); | |
86a0f043 | 2537 | for (i = 0;i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
2538 | rbuf[i] = readl(base + i*sizeof(u32)); |
2539 | spin_unlock_irq(&np->lock); | |
2540 | } | |
2541 | ||
2542 | static int nv_nway_reset(struct net_device *dev) | |
2543 | { | |
ac9c1897 | 2544 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
2545 | int ret; |
2546 | ||
2547 | spin_lock_irq(&np->lock); | |
2548 | if (np->autoneg) { | |
2549 | int bmcr; | |
2550 | ||
2551 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
2552 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
2553 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
2554 | ||
2555 | ret = 0; | |
2556 | } else { | |
2557 | ret = -EINVAL; | |
2558 | } | |
2559 | spin_unlock_irq(&np->lock); | |
2560 | ||
2561 | return ret; | |
2562 | } | |
2563 | ||
1da177e4 LT |
2564 | static struct ethtool_ops ops = { |
2565 | .get_drvinfo = nv_get_drvinfo, | |
2566 | .get_link = ethtool_op_get_link, | |
2567 | .get_wol = nv_get_wol, | |
2568 | .set_wol = nv_set_wol, | |
2569 | .get_settings = nv_get_settings, | |
2570 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
2571 | .get_regs_len = nv_get_regs_len, |
2572 | .get_regs = nv_get_regs, | |
2573 | .nway_reset = nv_nway_reset, | |
c704b856 | 2574 | .get_perm_addr = ethtool_op_get_perm_addr, |
1da177e4 LT |
2575 | }; |
2576 | ||
ee407b02 AA |
2577 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
2578 | { | |
2579 | struct fe_priv *np = get_nvpriv(dev); | |
2580 | ||
2581 | spin_lock_irq(&np->lock); | |
2582 | ||
2583 | /* save vlan group */ | |
2584 | np->vlangrp = grp; | |
2585 | ||
2586 | if (grp) { | |
2587 | /* enable vlan on MAC */ | |
2588 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
2589 | } else { | |
2590 | /* disable vlan on MAC */ | |
2591 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
2592 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
2593 | } | |
2594 | ||
2595 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2596 | ||
2597 | spin_unlock_irq(&np->lock); | |
2598 | }; | |
2599 | ||
2600 | static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
2601 | { | |
2602 | /* nothing to do */ | |
2603 | }; | |
2604 | ||
d33a73c8 AA |
2605 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
2606 | { | |
2607 | u8 __iomem *base = get_hwbase(dev); | |
2608 | int i; | |
2609 | u32 msixmap = 0; | |
2610 | ||
2611 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
2612 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
2613 | * the remaining 8 interrupts. | |
2614 | */ | |
2615 | for (i = 0; i < 8; i++) { | |
2616 | if ((irqmask >> i) & 0x1) { | |
2617 | msixmap |= vector << (i << 2); | |
2618 | } | |
2619 | } | |
2620 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
2621 | ||
2622 | msixmap = 0; | |
2623 | for (i = 0; i < 8; i++) { | |
2624 | if ((irqmask >> (i + 8)) & 0x1) { | |
2625 | msixmap |= vector << (i << 2); | |
2626 | } | |
2627 | } | |
2628 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
2629 | } | |
2630 | ||
1da177e4 LT |
2631 | static int nv_open(struct net_device *dev) |
2632 | { | |
ac9c1897 | 2633 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2634 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
2635 | int ret = 1; |
2636 | int oom, i; | |
1da177e4 LT |
2637 | |
2638 | dprintk(KERN_DEBUG "nv_open: begin\n"); | |
2639 | ||
2640 | /* 1) erase previous misconfiguration */ | |
86a0f043 AA |
2641 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
2642 | nv_mac_reset(dev); | |
1da177e4 LT |
2643 | /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ |
2644 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
2645 | writel(0, base + NvRegMulticastAddrB); | |
2646 | writel(0, base + NvRegMulticastMaskA); | |
2647 | writel(0, base + NvRegMulticastMaskB); | |
2648 | writel(0, base + NvRegPacketFilterFlags); | |
2649 | ||
2650 | writel(0, base + NvRegTransmitterControl); | |
2651 | writel(0, base + NvRegReceiverControl); | |
2652 | ||
2653 | writel(0, base + NvRegAdapterControl); | |
2654 | ||
2655 | /* 2) initialize descriptor rings */ | |
d81c0983 | 2656 | set_bufsize(dev); |
1da177e4 LT |
2657 | oom = nv_init_ring(dev); |
2658 | ||
2659 | writel(0, base + NvRegLinkSpeed); | |
2660 | writel(0, base + NvRegUnknownTransmitterReg); | |
2661 | nv_txrx_reset(dev); | |
2662 | writel(0, base + NvRegUnknownSetupReg6); | |
2663 | ||
2664 | np->in_shutdown = 0; | |
2665 | ||
2666 | /* 3) set mac address */ | |
72b31782 | 2667 | nv_copy_mac_to_hw(dev); |
1da177e4 LT |
2668 | |
2669 | /* 4) give hw rings */ | |
0832b25a | 2670 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
1da177e4 LT |
2671 | writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
2672 | base + NvRegRingSizes); | |
2673 | ||
2674 | /* 5) continue setup */ | |
2675 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
2676 | writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); | |
8a4ae7f2 | 2677 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 2678 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 2679 | pci_push(base); |
8a4ae7f2 | 2680 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
2681 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
2682 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | |
2683 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | |
2684 | ||
2685 | writel(0, base + NvRegUnknownSetupReg4); | |
2686 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
2687 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); | |
2688 | ||
2689 | /* 6) continue setup */ | |
2690 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); | |
2691 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
2692 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 2693 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
2694 | |
2695 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
2696 | get_random_bytes(&i, sizeof(i)); | |
2697 | writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); | |
2698 | writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); | |
2699 | writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); | |
a971c324 AA |
2700 | if (poll_interval == -1) { |
2701 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
2702 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
2703 | else | |
2704 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
2705 | } | |
2706 | else | |
2707 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); | |
1da177e4 LT |
2708 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
2709 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
2710 | base + NvRegAdapterControl); | |
2711 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
2712 | writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); | |
2713 | writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); | |
2714 | ||
2715 | i = readl(base + NvRegPowerState); | |
2716 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) | |
2717 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); | |
2718 | ||
2719 | pci_push(base); | |
2720 | udelay(10); | |
2721 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
2722 | ||
f34ba4e1 | 2723 | writel(0, base + NvRegIrqMask); |
1da177e4 LT |
2724 | pci_push(base); |
2725 | writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); | |
2726 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
2727 | pci_push(base); | |
2728 | ||
d33a73c8 AA |
2729 | if (np->msi_flags & NV_MSI_X_CAPABLE) { |
2730 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
2731 | np->msi_x_entry[i].entry = i; | |
2732 | } | |
2733 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { | |
2734 | np->msi_flags |= NV_MSI_X_ENABLED; | |
2735 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { | |
2736 | /* Request irq for rx handling */ | |
2737 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) { | |
2738 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); | |
2739 | pci_disable_msix(np->pci_dev); | |
2740 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
2741 | goto out_drain; | |
2742 | } | |
2743 | /* Request irq for tx handling */ | |
2744 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) { | |
2745 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); | |
2746 | pci_disable_msix(np->pci_dev); | |
2747 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
2748 | goto out_drain; | |
2749 | } | |
2750 | /* Request irq for link and timer handling */ | |
2751 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) { | |
2752 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); | |
2753 | pci_disable_msix(np->pci_dev); | |
2754 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
2755 | goto out_drain; | |
2756 | } | |
2757 | ||
2758 | /* map interrupts to their respective vector */ | |
2759 | writel(0, base + NvRegMSIXMap0); | |
2760 | writel(0, base + NvRegMSIXMap1); | |
2761 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
2762 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
2763 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
2764 | } else { | |
2765 | /* Request irq for all interrupts */ | |
2766 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { | |
2767 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); | |
2768 | pci_disable_msix(np->pci_dev); | |
2769 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
2770 | goto out_drain; | |
2771 | } | |
2772 | ||
2773 | /* map interrupts to vector 0 */ | |
2774 | writel(0, base + NvRegMSIXMap0); | |
2775 | writel(0, base + NvRegMSIXMap1); | |
2776 | } | |
2777 | } | |
2778 | } | |
2779 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
2780 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | |
2781 | np->msi_flags |= NV_MSI_ENABLED; | |
2782 | if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { | |
2783 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); | |
2784 | pci_disable_msi(np->pci_dev); | |
2785 | np->msi_flags &= ~NV_MSI_ENABLED; | |
2786 | goto out_drain; | |
2787 | } | |
2788 | ||
2789 | /* map interrupts to vector 0 */ | |
2790 | writel(0, base + NvRegMSIMap0); | |
2791 | writel(0, base + NvRegMSIMap1); | |
2792 | /* enable msi vector 0 */ | |
2793 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
2794 | } | |
2795 | } | |
2796 | if (ret != 0) { | |
2797 | if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) | |
2798 | goto out_drain; | |
2799 | } | |
1da177e4 LT |
2800 | |
2801 | /* ask for interrupts */ | |
f34ba4e1 | 2802 | writel(np->irqmask, base + NvRegIrqMask); |
1da177e4 LT |
2803 | |
2804 | spin_lock_irq(&np->lock); | |
2805 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
2806 | writel(0, base + NvRegMulticastAddrB); | |
2807 | writel(0, base + NvRegMulticastMaskA); | |
2808 | writel(0, base + NvRegMulticastMaskB); | |
2809 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); | |
2810 | /* One manual link speed update: Interrupts are enabled, future link | |
2811 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
2812 | */ | |
2813 | { | |
2814 | u32 miistat; | |
2815 | miistat = readl(base + NvRegMIIStatus); | |
2816 | writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); | |
2817 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); | |
2818 | } | |
1b1b3c9b MS |
2819 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
2820 | * to init hw */ | |
2821 | np->linkspeed = 0; | |
1da177e4 LT |
2822 | ret = nv_update_linkspeed(dev); |
2823 | nv_start_rx(dev); | |
2824 | nv_start_tx(dev); | |
2825 | netif_start_queue(dev); | |
2826 | if (ret) { | |
2827 | netif_carrier_on(dev); | |
2828 | } else { | |
2829 | printk("%s: no link during initialization.\n", dev->name); | |
2830 | netif_carrier_off(dev); | |
2831 | } | |
2832 | if (oom) | |
2833 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2834 | spin_unlock_irq(&np->lock); | |
2835 | ||
2836 | return 0; | |
2837 | out_drain: | |
2838 | drain_ring(dev); | |
2839 | return ret; | |
2840 | } | |
2841 | ||
2842 | static int nv_close(struct net_device *dev) | |
2843 | { | |
ac9c1897 | 2844 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2845 | u8 __iomem *base; |
f34ba4e1 | 2846 | int i; |
1da177e4 LT |
2847 | |
2848 | spin_lock_irq(&np->lock); | |
2849 | np->in_shutdown = 1; | |
2850 | spin_unlock_irq(&np->lock); | |
2851 | synchronize_irq(dev->irq); | |
2852 | ||
2853 | del_timer_sync(&np->oom_kick); | |
2854 | del_timer_sync(&np->nic_poll); | |
2855 | ||
2856 | netif_stop_queue(dev); | |
2857 | spin_lock_irq(&np->lock); | |
2858 | nv_stop_tx(dev); | |
2859 | nv_stop_rx(dev); | |
2860 | nv_txrx_reset(dev); | |
2861 | ||
2862 | /* disable interrupts on the nic or we will lock up */ | |
2863 | base = get_hwbase(dev); | |
f34ba4e1 AM |
2864 | if (np->msi_flags & NV_MSI_X_ENABLED) { |
2865 | writel(np->irqmask, base + NvRegIrqMask); | |
2866 | } else { | |
2867 | if (np->msi_flags & NV_MSI_ENABLED) | |
2868 | writel(0, base + NvRegMSIIrqMask); | |
2869 | writel(0, base + NvRegIrqMask); | |
2870 | } | |
1da177e4 LT |
2871 | pci_push(base); |
2872 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | |
2873 | ||
2874 | spin_unlock_irq(&np->lock); | |
2875 | ||
f34ba4e1 AM |
2876 | if (np->msi_flags & NV_MSI_X_ENABLED) { |
2877 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
2878 | free_irq(np->msi_x_entry[i].vector, dev); | |
2879 | } | |
2880 | pci_disable_msix(np->pci_dev); | |
2881 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
2882 | } else { | |
2883 | free_irq(np->pci_dev->irq, dev); | |
2884 | if (np->msi_flags & NV_MSI_ENABLED) { | |
2885 | pci_disable_msi(np->pci_dev); | |
2886 | np->msi_flags &= ~NV_MSI_ENABLED; | |
2887 | } | |
2888 | } | |
1da177e4 LT |
2889 | |
2890 | drain_ring(dev); | |
2891 | ||
2892 | if (np->wolenabled) | |
2893 | nv_start_rx(dev); | |
2894 | ||
b3df9f81 MS |
2895 | /* special op: write back the misordered MAC address - otherwise |
2896 | * the next nv_probe would see a wrong address. | |
2897 | */ | |
2898 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
2899 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |
2900 | ||
1da177e4 LT |
2901 | /* FIXME: power down nic */ |
2902 | ||
2903 | return 0; | |
2904 | } | |
2905 | ||
2906 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) | |
2907 | { | |
2908 | struct net_device *dev; | |
2909 | struct fe_priv *np; | |
2910 | unsigned long addr; | |
2911 | u8 __iomem *base; | |
2912 | int err, i; | |
86a0f043 | 2913 | u32 powerstate; |
1da177e4 LT |
2914 | |
2915 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
2916 | err = -ENOMEM; | |
2917 | if (!dev) | |
2918 | goto out; | |
2919 | ||
ac9c1897 | 2920 | np = netdev_priv(dev); |
1da177e4 LT |
2921 | np->pci_dev = pci_dev; |
2922 | spin_lock_init(&np->lock); | |
2923 | SET_MODULE_OWNER(dev); | |
2924 | SET_NETDEV_DEV(dev, &pci_dev->dev); | |
2925 | ||
2926 | init_timer(&np->oom_kick); | |
2927 | np->oom_kick.data = (unsigned long) dev; | |
2928 | np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ | |
2929 | init_timer(&np->nic_poll); | |
2930 | np->nic_poll.data = (unsigned long) dev; | |
2931 | np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ | |
2932 | ||
2933 | err = pci_enable_device(pci_dev); | |
2934 | if (err) { | |
2935 | printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", | |
2936 | err, pci_name(pci_dev)); | |
2937 | goto out_free; | |
2938 | } | |
2939 | ||
2940 | pci_set_master(pci_dev); | |
2941 | ||
2942 | err = pci_request_regions(pci_dev, DRV_NAME); | |
2943 | if (err < 0) | |
2944 | goto out_disable; | |
2945 | ||
86a0f043 AA |
2946 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL)) |
2947 | np->register_size = NV_PCI_REGSZ_VER2; | |
2948 | else | |
2949 | np->register_size = NV_PCI_REGSZ_VER1; | |
2950 | ||
1da177e4 LT |
2951 | err = -EINVAL; |
2952 | addr = 0; | |
2953 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2954 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | |
2955 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), | |
2956 | pci_resource_len(pci_dev, i), | |
2957 | pci_resource_flags(pci_dev, i)); | |
2958 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | |
86a0f043 | 2959 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
2960 | addr = pci_resource_start(pci_dev, i); |
2961 | break; | |
2962 | } | |
2963 | } | |
2964 | if (i == DEVICE_COUNT_RESOURCE) { | |
2965 | printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", | |
2966 | pci_name(pci_dev)); | |
2967 | goto out_relreg; | |
2968 | } | |
2969 | ||
86a0f043 AA |
2970 | /* copy of driver data */ |
2971 | np->driver_data = id->driver_data; | |
2972 | ||
1da177e4 | 2973 | /* handle different descriptor versions */ |
ee73362c MS |
2974 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
2975 | /* packet format 3: supports 40-bit addressing */ | |
2976 | np->desc_ver = DESC_VER_3; | |
910638ae | 2977 | if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
ee73362c MS |
2978 | printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", |
2979 | pci_name(pci_dev)); | |
ac9c1897 | 2980 | } else { |
f34ba4e1 AM |
2981 | if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) { |
2982 | printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n", | |
2983 | pci_name(pci_dev)); | |
2984 | goto out_relreg; | |
2985 | } else { | |
2986 | dev->features |= NETIF_F_HIGHDMA; | |
2987 | printk(KERN_INFO "forcedeth: using HIGHDMA\n"); | |
2988 | } | |
ee73362c | 2989 | } |
f34ba4e1 | 2990 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
ee73362c MS |
2991 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
2992 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 2993 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 2994 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
2995 | } else { |
2996 | /* original packet format */ | |
2997 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 2998 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 2999 | } |
ee73362c MS |
3000 | |
3001 | np->pkt_limit = NV_PKTLIMIT_1; | |
3002 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
3003 | np->pkt_limit = NV_PKTLIMIT_2; | |
3004 | ||
8a4ae7f2 MS |
3005 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
3006 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
ac9c1897 AA |
3007 | dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
3008 | #ifdef NETIF_F_TSO | |
fa45459e | 3009 | dev->features |= NETIF_F_TSO; |
ac9c1897 AA |
3010 | #endif |
3011 | } | |
8a4ae7f2 | 3012 | |
ee407b02 AA |
3013 | np->vlanctl_bits = 0; |
3014 | if (id->driver_data & DEV_HAS_VLAN) { | |
3015 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
3016 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
3017 | dev->vlan_rx_register = nv_vlan_rx_register; | |
3018 | dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; | |
3019 | } | |
3020 | ||
d33a73c8 AA |
3021 | np->msi_flags = 0; |
3022 | if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) { | |
3023 | np->msi_flags |= NV_MSI_CAPABLE; | |
3024 | } | |
3025 | if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) { | |
3026 | np->msi_flags |= NV_MSI_X_CAPABLE; | |
3027 | } | |
3028 | ||
1da177e4 | 3029 | err = -ENOMEM; |
86a0f043 | 3030 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
3031 | if (!np->base) |
3032 | goto out_relreg; | |
3033 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 3034 | |
1da177e4 | 3035 | dev->irq = pci_dev->irq; |
ee73362c MS |
3036 | |
3037 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { | |
3038 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, | |
3039 | sizeof(struct ring_desc) * (RX_RING + TX_RING), | |
3040 | &np->ring_addr); | |
3041 | if (!np->rx_ring.orig) | |
3042 | goto out_unmap; | |
3043 | np->tx_ring.orig = &np->rx_ring.orig[RX_RING]; | |
3044 | } else { | |
3045 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
3046 | sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), | |
3047 | &np->ring_addr); | |
3048 | if (!np->rx_ring.ex) | |
3049 | goto out_unmap; | |
3050 | np->tx_ring.ex = &np->rx_ring.ex[RX_RING]; | |
3051 | } | |
1da177e4 LT |
3052 | |
3053 | dev->open = nv_open; | |
3054 | dev->stop = nv_close; | |
3055 | dev->hard_start_xmit = nv_start_xmit; | |
3056 | dev->get_stats = nv_get_stats; | |
3057 | dev->change_mtu = nv_change_mtu; | |
72b31782 | 3058 | dev->set_mac_address = nv_set_mac_address; |
1da177e4 | 3059 | dev->set_multicast_list = nv_set_multicast; |
2918c35d MS |
3060 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3061 | dev->poll_controller = nv_poll_controller; | |
3062 | #endif | |
1da177e4 LT |
3063 | SET_ETHTOOL_OPS(dev, &ops); |
3064 | dev->tx_timeout = nv_tx_timeout; | |
3065 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; | |
3066 | ||
3067 | pci_set_drvdata(pci_dev, dev); | |
3068 | ||
3069 | /* read the mac address */ | |
3070 | base = get_hwbase(dev); | |
3071 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
3072 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
3073 | ||
3074 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
3075 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
3076 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
3077 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
3078 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
3079 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
c704b856 | 3080 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 3081 | |
c704b856 | 3082 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
3083 | /* |
3084 | * Bad mac address. At least one bios sets the mac address | |
3085 | * to 01:23:45:67:89:ab | |
3086 | */ | |
3087 | printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3088 | pci_name(pci_dev), | |
3089 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3090 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3091 | printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
3092 | dev->dev_addr[0] = 0x00; | |
3093 | dev->dev_addr[1] = 0x00; | |
3094 | dev->dev_addr[2] = 0x6c; | |
3095 | get_random_bytes(&dev->dev_addr[3], 3); | |
3096 | } | |
3097 | ||
3098 | dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), | |
3099 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3100 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3101 | ||
3102 | /* disable WOL */ | |
3103 | writel(0, base + NvRegWakeUpFlags); | |
3104 | np->wolenabled = 0; | |
3105 | ||
86a0f043 AA |
3106 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
3107 | u8 revision_id; | |
3108 | pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id); | |
3109 | ||
3110 | /* take phy and nic out of low power mode */ | |
3111 | powerstate = readl(base + NvRegPowerState2); | |
3112 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3113 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || | |
3114 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && | |
3115 | revision_id >= 0xA3) | |
3116 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; | |
3117 | writel(powerstate, base + NvRegPowerState2); | |
3118 | } | |
3119 | ||
1da177e4 | 3120 | if (np->desc_ver == DESC_VER_1) { |
ac9c1897 | 3121 | np->tx_flags = NV_TX_VALID; |
1da177e4 | 3122 | } else { |
ac9c1897 | 3123 | np->tx_flags = NV_TX2_VALID; |
1da177e4 | 3124 | } |
d33a73c8 | 3125 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
a971c324 | 3126 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
d33a73c8 AA |
3127 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
3128 | np->msi_flags |= 0x0003; | |
3129 | } else { | |
a971c324 | 3130 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
3131 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
3132 | np->msi_flags |= 0x0001; | |
3133 | } | |
a971c324 | 3134 | |
1da177e4 LT |
3135 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
3136 | np->irqmask |= NVREG_IRQ_TIMER; | |
3137 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
3138 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | |
3139 | np->need_linktimer = 1; | |
3140 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3141 | } else { | |
3142 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | |
3143 | np->need_linktimer = 0; | |
3144 | } | |
3145 | ||
3146 | /* find a suitable phy */ | |
7a33e45a | 3147 | for (i = 1; i <= 32; i++) { |
1da177e4 | 3148 | int id1, id2; |
7a33e45a | 3149 | int phyaddr = i & 0x1F; |
1da177e4 LT |
3150 | |
3151 | spin_lock_irq(&np->lock); | |
7a33e45a | 3152 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
3153 | spin_unlock_irq(&np->lock); |
3154 | if (id1 < 0 || id1 == 0xffff) | |
3155 | continue; | |
3156 | spin_lock_irq(&np->lock); | |
7a33e45a | 3157 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
3158 | spin_unlock_irq(&np->lock); |
3159 | if (id2 < 0 || id2 == 0xffff) | |
3160 | continue; | |
3161 | ||
3162 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; | |
3163 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
3164 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | |
7a33e45a AA |
3165 | pci_name(pci_dev), id1, id2, phyaddr); |
3166 | np->phyaddr = phyaddr; | |
1da177e4 LT |
3167 | np->phy_oui = id1 | id2; |
3168 | break; | |
3169 | } | |
7a33e45a | 3170 | if (i == 33) { |
1da177e4 | 3171 | printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
7a33e45a AA |
3172 | pci_name(pci_dev)); |
3173 | goto out_freering; | |
1da177e4 | 3174 | } |
7a33e45a AA |
3175 | |
3176 | /* reset it */ | |
3177 | phy_init(dev); | |
1da177e4 LT |
3178 | |
3179 | /* set default link speed settings */ | |
3180 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3181 | np->duplex = 0; | |
3182 | np->autoneg = 1; | |
3183 | ||
3184 | err = register_netdev(dev); | |
3185 | if (err) { | |
3186 | printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); | |
3187 | goto out_freering; | |
3188 | } | |
3189 | printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", | |
3190 | dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, | |
3191 | pci_name(pci_dev)); | |
3192 | ||
3193 | return 0; | |
3194 | ||
3195 | out_freering: | |
ee73362c MS |
3196 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
3197 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), | |
3198 | np->rx_ring.orig, np->ring_addr); | |
3199 | else | |
3200 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), | |
3201 | np->rx_ring.ex, np->ring_addr); | |
1da177e4 LT |
3202 | pci_set_drvdata(pci_dev, NULL); |
3203 | out_unmap: | |
3204 | iounmap(get_hwbase(dev)); | |
3205 | out_relreg: | |
3206 | pci_release_regions(pci_dev); | |
3207 | out_disable: | |
3208 | pci_disable_device(pci_dev); | |
3209 | out_free: | |
3210 | free_netdev(dev); | |
3211 | out: | |
3212 | return err; | |
3213 | } | |
3214 | ||
3215 | static void __devexit nv_remove(struct pci_dev *pci_dev) | |
3216 | { | |
3217 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
ac9c1897 | 3218 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3219 | |
3220 | unregister_netdev(dev); | |
3221 | ||
1da177e4 | 3222 | /* free all structures */ |
ee73362c MS |
3223 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
3224 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr); | |
3225 | else | |
3226 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr); | |
1da177e4 LT |
3227 | iounmap(get_hwbase(dev)); |
3228 | pci_release_regions(pci_dev); | |
3229 | pci_disable_device(pci_dev); | |
3230 | free_netdev(dev); | |
3231 | pci_set_drvdata(pci_dev, NULL); | |
3232 | } | |
3233 | ||
3234 | static struct pci_device_id pci_tbl[] = { | |
3235 | { /* nForce Ethernet Controller */ | |
dc8216c1 | 3236 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
c2dba06d | 3237 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
3238 | }, |
3239 | { /* nForce2 Ethernet Controller */ | |
dc8216c1 | 3240 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
c2dba06d | 3241 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
3242 | }, |
3243 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 3244 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
c2dba06d | 3245 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
3246 | }, |
3247 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 3248 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
8a4ae7f2 | 3249 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
3250 | }, |
3251 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 3252 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
8a4ae7f2 | 3253 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
3254 | }, |
3255 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 3256 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
8a4ae7f2 | 3257 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
3258 | }, |
3259 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 3260 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
8a4ae7f2 | 3261 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
3262 | }, |
3263 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 3264 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
8a4ae7f2 | 3265 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
3266 | }, |
3267 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 3268 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
8a4ae7f2 | 3269 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
3270 | }, |
3271 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 3272 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
8a4ae7f2 | 3273 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 LT |
3274 | }, |
3275 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 3276 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
8a4ae7f2 | 3277 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
1da177e4 | 3278 | }, |
9992d4aa | 3279 | { /* MCP51 Ethernet Controller */ |
dc8216c1 | 3280 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
86a0f043 | 3281 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
9992d4aa MS |
3282 | }, |
3283 | { /* MCP51 Ethernet Controller */ | |
dc8216c1 | 3284 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
86a0f043 | 3285 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
9992d4aa | 3286 | }, |
f49d16ef | 3287 | { /* MCP55 Ethernet Controller */ |
dc8216c1 | 3288 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
86a0f043 | 3289 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
f49d16ef MS |
3290 | }, |
3291 | { /* MCP55 Ethernet Controller */ | |
dc8216c1 | 3292 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
86a0f043 | 3293 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
f49d16ef | 3294 | }, |
1da177e4 LT |
3295 | {0,}, |
3296 | }; | |
3297 | ||
3298 | static struct pci_driver driver = { | |
3299 | .name = "forcedeth", | |
3300 | .id_table = pci_tbl, | |
3301 | .probe = nv_probe, | |
3302 | .remove = __devexit_p(nv_remove), | |
3303 | }; | |
3304 | ||
3305 | ||
3306 | static int __init init_nic(void) | |
3307 | { | |
3308 | printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); | |
3309 | return pci_module_init(&driver); | |
3310 | } | |
3311 | ||
3312 | static void __exit exit_nic(void) | |
3313 | { | |
3314 | pci_unregister_driver(&driver); | |
3315 | } | |
3316 | ||
3317 | module_param(max_interrupt_work, int, 0); | |
3318 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); | |
a971c324 AA |
3319 | module_param(optimization_mode, int, 0); |
3320 | MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); | |
3321 | module_param(poll_interval, int, 0); | |
3322 | MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); | |
d33a73c8 AA |
3323 | module_param(disable_msi, int, 0); |
3324 | MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1."); | |
3325 | module_param(disable_msix, int, 0); | |
3326 | MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1."); | |
1da177e4 LT |
3327 | |
3328 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); | |
3329 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); | |
3330 | MODULE_LICENSE("GPL"); | |
3331 | ||
3332 | MODULE_DEVICE_TABLE(pci, pci_tbl); | |
3333 | ||
3334 | module_init(init_nic); | |
3335 | module_exit(exit_nic); |