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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
1da177e4 LT |
32 | * Known bugs: |
33 | * We suspect that on some hardware no TX done interrupts are generated. | |
34 | * This means recovery from netif_stop_queue only happens if the hw timer | |
35 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
36 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
37 | * If your hardware reliably generates tx done interrupts, then you can remove | |
38 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
40 | * superfluous timer interrupts from the nic. | |
41 | */ | |
f1405d32 | 42 | #define FORCEDETH_VERSION "0.62" |
1da177e4 LT |
43 | #define DRV_NAME "forcedeth" |
44 | ||
45 | #include <linux/module.h> | |
46 | #include <linux/types.h> | |
47 | #include <linux/pci.h> | |
48 | #include <linux/interrupt.h> | |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/etherdevice.h> | |
51 | #include <linux/delay.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/ethtool.h> | |
54 | #include <linux/timer.h> | |
55 | #include <linux/skbuff.h> | |
56 | #include <linux/mii.h> | |
57 | #include <linux/random.h> | |
58 | #include <linux/init.h> | |
22c6d143 | 59 | #include <linux/if_vlan.h> |
910638ae | 60 | #include <linux/dma-mapping.h> |
1da177e4 LT |
61 | |
62 | #include <asm/irq.h> | |
63 | #include <asm/io.h> | |
64 | #include <asm/uaccess.h> | |
65 | #include <asm/system.h> | |
66 | ||
67 | #if 0 | |
68 | #define dprintk printk | |
69 | #else | |
70 | #define dprintk(x...) do { } while (0) | |
71 | #endif | |
72 | ||
bea3348e SH |
73 | #define TX_WORK_PER_LOOP 64 |
74 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
75 | |
76 | /* | |
77 | * Hardware access: | |
78 | */ | |
79 | ||
9c662435 AA |
80 | #define DEV_NEED_TIMERIRQ 0x000001 /* set the timer irq flag in the irq mask */ |
81 | #define DEV_NEED_LINKTIMER 0x000002 /* poll link settings. Relies on the timer irq */ | |
82 | #define DEV_HAS_LARGEDESC 0x000004 /* device supports jumbo frames and needs packet format 2 */ | |
83 | #define DEV_HAS_HIGH_DMA 0x000008 /* device supports 64bit dma */ | |
84 | #define DEV_HAS_CHECKSUM 0x000010 /* device supports tx and rx checksum offloads */ | |
85 | #define DEV_HAS_VLAN 0x000020 /* device supports vlan tagging and striping */ | |
86 | #define DEV_HAS_MSI 0x000040 /* device supports MSI */ | |
87 | #define DEV_HAS_MSI_X 0x000080 /* device supports MSI-X */ | |
88 | #define DEV_HAS_POWER_CNTRL 0x000100 /* device supports power savings */ | |
89 | #define DEV_HAS_STATISTICS_V1 0x000200 /* device supports hw statistics version 1 */ | |
90 | #define DEV_HAS_STATISTICS_V2 0x000400 /* device supports hw statistics version 2 */ | |
91 | #define DEV_HAS_STATISTICS_V3 0x000800 /* device supports hw statistics version 3 */ | |
92 | #define DEV_HAS_TEST_EXTENDED 0x001000 /* device supports extended diagnostic test */ | |
93 | #define DEV_HAS_MGMT_UNIT 0x002000 /* device supports management unit */ | |
94 | #define DEV_HAS_CORRECT_MACADDR 0x004000 /* device supports correct mac address order */ | |
95 | #define DEV_HAS_COLLISION_FIX 0x008000 /* device supports tx collision fix */ | |
96 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x010000 /* device supports tx pause frames version 1 */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x020000 /* device supports tx pause frames version 2 */ | |
98 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x040000 /* device supports tx pause frames version 3 */ | |
99 | #define DEV_NEED_TX_LIMIT 0x080000 /* device needs to limit tx */ | |
100 | #define DEV_HAS_GEAR_MODE 0x100000 /* device supports gear mode */ | |
1da177e4 LT |
101 | |
102 | enum { | |
103 | NvRegIrqStatus = 0x000, | |
104 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
c5cf9101 | 105 | #define NVREG_IRQSTAT_MASK 0x81ff |
1da177e4 LT |
106 | NvRegIrqMask = 0x004, |
107 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
108 | #define NVREG_IRQ_RX 0x0002 | |
109 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
110 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 111 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
112 | #define NVREG_IRQ_TIMER 0x0020 |
113 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
114 | #define NVREG_IRQ_RX_FORCED 0x0080 |
115 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
c5cf9101 | 116 | #define NVREG_IRQ_RECOVER_ERROR 0x8000 |
a971c324 | 117 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 118 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
119 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
120 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 121 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d MS |
122 | |
123 | #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ | |
d33a73c8 | 124 | NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
c5cf9101 | 125 | NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR)) |
1da177e4 LT |
126 | |
127 | NvRegUnknownSetupReg6 = 0x008, | |
128 | #define NVREG_UNKSETUP6_VAL 3 | |
129 | ||
130 | /* | |
131 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
132 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
133 | */ | |
134 | NvRegPollingInterval = 0x00c, | |
4e16ed1b | 135 | #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */ |
a971c324 | 136 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
137 | NvRegMSIMap0 = 0x020, |
138 | NvRegMSIMap1 = 0x024, | |
139 | NvRegMSIIrqMask = 0x030, | |
140 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 141 | NvRegMisc1 = 0x080, |
eb91f61b | 142 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
143 | #define NVREG_MISC1_HD 0x02 |
144 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
145 | ||
0a62677b | 146 | NvRegMacReset = 0x34, |
86a0f043 | 147 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
148 | NvRegTransmitterControl = 0x084, |
149 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
150 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
151 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
152 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
153 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
154 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
155 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
156 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
157 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
158 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 159 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
160 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
161 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
162 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
163 | NvRegTransmitterStatus = 0x088, |
164 | #define NVREG_XMITSTAT_BUSY 0x01 | |
165 | ||
166 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
167 | #define NVREG_PFF_PAUSE_RX 0x08 |
168 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
169 | #define NVREG_PFF_PROMISC 0x80 |
170 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 171 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
172 | |
173 | NvRegOffloadConfig = 0x90, | |
174 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
175 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
176 | NvRegReceiverControl = 0x094, | |
177 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 178 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
179 | NvRegReceiverStatus = 0x98, |
180 | #define NVREG_RCVSTAT_BUSY 0x01 | |
181 | ||
a433686c AA |
182 | NvRegSlotTime = 0x9c, |
183 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
184 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
185 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 | |
186 | #define NVREG_SLOTTIME_HALF 0x0000ff00 | |
187 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 | |
188 | #define NVREG_SLOTTIME_MASK 0x000000ff | |
1da177e4 | 189 | |
9744e218 | 190 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
191 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
192 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
193 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
194 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
195 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
196 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
197 | NvRegRxDeferral = 0xA4, |
198 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
199 | NvRegMacAddrA = 0xA8, |
200 | NvRegMacAddrB = 0xAC, | |
201 | NvRegMulticastAddrA = 0xB0, | |
202 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
203 | NvRegMulticastAddrB = 0xB4, | |
204 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 205 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 206 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 207 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
208 | |
209 | NvRegPhyInterface = 0xC0, | |
210 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
211 | NvRegBackOffControl = 0xC4, |
212 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
213 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
214 | #define NVREG_BKOFFCTRL_SELECT 24 | |
215 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
216 | |
217 | NvRegTxRingPhysAddr = 0x100, | |
218 | NvRegRxRingPhysAddr = 0x104, | |
219 | NvRegRingSizes = 0x108, | |
220 | #define NVREG_RINGSZ_TXSHIFT 0 | |
221 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
222 | NvRegTransmitPoll = 0x10c, |
223 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
224 | NvRegLinkSpeed = 0x110, |
225 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
226 | #define NVREG_LINKSPEED_10 1000 | |
227 | #define NVREG_LINKSPEED_100 100 | |
228 | #define NVREG_LINKSPEED_1000 50 | |
229 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
230 | NvRegUnknownSetupReg5 = 0x130, | |
231 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
232 | NvRegTxWatermark = 0x13c, |
233 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
234 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
235 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
236 | NvRegTxRxControl = 0x144, |
237 | #define NVREG_TXRXCTL_KICK 0x0001 | |
238 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
239 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
240 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
241 | #define NVREG_TXRXCTL_RESET 0x0010 | |
242 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 243 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
244 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
245 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
246 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
247 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
248 | NvRegTxRingPhysAddrHigh = 0x148, |
249 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 250 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
251 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
252 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
253 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
254 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
255 | NvRegTxPauseFrameLimit = 0x174, |
256 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
257 | NvRegMIIStatus = 0x180, |
258 | #define NVREG_MIISTAT_ERROR 0x0001 | |
259 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
260 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
261 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
262 | NvRegMIIMask = 0x184, |
263 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
264 | |
265 | NvRegAdapterControl = 0x188, | |
266 | #define NVREG_ADAPTCTL_START 0x02 | |
267 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
268 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
269 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
270 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
271 | NvRegMIISpeed = 0x18c, | |
272 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
273 | #define NVREG_MIIDELAY 5 | |
274 | NvRegMIIControl = 0x190, | |
275 | #define NVREG_MIICTL_INUSE 0x08000 | |
276 | #define NVREG_MIICTL_WRITE 0x00400 | |
277 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
278 | NvRegMIIData = 0x194, | |
9c662435 AA |
279 | NvRegTxUnicast = 0x1a0, |
280 | NvRegTxMulticast = 0x1a4, | |
281 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
282 | NvRegWakeUpFlags = 0x200, |
283 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
284 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
285 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
286 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
287 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
288 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
289 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
290 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
291 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
292 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
293 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
294 | ||
cac1c52c AA |
295 | NvRegMgmtUnitGetVersion = 0x204, |
296 | #define NVREG_MGMTUNITGETVERSION 0x01 | |
297 | NvRegMgmtUnitVersion = 0x208, | |
298 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
299 | NvRegPowerCap = 0x268, |
300 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
301 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
302 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
303 | NvRegPowerState = 0x26c, | |
304 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
305 | #define NVREG_POWERSTATE_VALID 0x0100 | |
306 | #define NVREG_POWERSTATE_MASK 0x0003 | |
307 | #define NVREG_POWERSTATE_D0 0x0000 | |
308 | #define NVREG_POWERSTATE_D1 0x0001 | |
309 | #define NVREG_POWERSTATE_D2 0x0002 | |
310 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
311 | NvRegMgmtUnitControl = 0x278, |
312 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
313 | NvRegTxCnt = 0x280, |
314 | NvRegTxZeroReXmt = 0x284, | |
315 | NvRegTxOneReXmt = 0x288, | |
316 | NvRegTxManyReXmt = 0x28c, | |
317 | NvRegTxLateCol = 0x290, | |
318 | NvRegTxUnderflow = 0x294, | |
319 | NvRegTxLossCarrier = 0x298, | |
320 | NvRegTxExcessDef = 0x29c, | |
321 | NvRegTxRetryErr = 0x2a0, | |
322 | NvRegRxFrameErr = 0x2a4, | |
323 | NvRegRxExtraByte = 0x2a8, | |
324 | NvRegRxLateCol = 0x2ac, | |
325 | NvRegRxRunt = 0x2b0, | |
326 | NvRegRxFrameTooLong = 0x2b4, | |
327 | NvRegRxOverflow = 0x2b8, | |
328 | NvRegRxFCSErr = 0x2bc, | |
329 | NvRegRxFrameAlignErr = 0x2c0, | |
330 | NvRegRxLenErr = 0x2c4, | |
331 | NvRegRxUnicast = 0x2c8, | |
332 | NvRegRxMulticast = 0x2cc, | |
333 | NvRegRxBroadcast = 0x2d0, | |
334 | NvRegTxDef = 0x2d4, | |
335 | NvRegTxFrame = 0x2d8, | |
336 | NvRegRxCnt = 0x2dc, | |
337 | NvRegTxPause = 0x2e0, | |
338 | NvRegRxPause = 0x2e4, | |
339 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
340 | NvRegVlanControl = 0x300, |
341 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
342 | NvRegMSIXMap0 = 0x3e0, |
343 | NvRegMSIXMap1 = 0x3e4, | |
344 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
345 | |
346 | NvRegPowerState2 = 0x600, | |
1545e205 | 347 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 348 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 349 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
1da177e4 LT |
350 | }; |
351 | ||
352 | /* Big endian: should work, but is untested */ | |
353 | struct ring_desc { | |
a8bed49e SH |
354 | __le32 buf; |
355 | __le32 flaglen; | |
1da177e4 LT |
356 | }; |
357 | ||
ee73362c | 358 | struct ring_desc_ex { |
a8bed49e SH |
359 | __le32 bufhigh; |
360 | __le32 buflow; | |
361 | __le32 txvlan; | |
362 | __le32 flaglen; | |
ee73362c MS |
363 | }; |
364 | ||
f82a9352 | 365 | union ring_type { |
ee73362c MS |
366 | struct ring_desc* orig; |
367 | struct ring_desc_ex* ex; | |
f82a9352 | 368 | }; |
ee73362c | 369 | |
1da177e4 LT |
370 | #define FLAG_MASK_V1 0xffff0000 |
371 | #define FLAG_MASK_V2 0xffffc000 | |
372 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
373 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
374 | ||
375 | #define NV_TX_LASTPACKET (1<<16) | |
376 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 377 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 378 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
379 | #define NV_TX_DEFERRED (1<<26) |
380 | #define NV_TX_CARRIERLOST (1<<27) | |
381 | #define NV_TX_LATECOLLISION (1<<28) | |
382 | #define NV_TX_UNDERFLOW (1<<29) | |
383 | #define NV_TX_ERROR (1<<30) | |
384 | #define NV_TX_VALID (1<<31) | |
385 | ||
386 | #define NV_TX2_LASTPACKET (1<<29) | |
387 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 388 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 389 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
390 | #define NV_TX2_DEFERRED (1<<25) |
391 | #define NV_TX2_CARRIERLOST (1<<26) | |
392 | #define NV_TX2_LATECOLLISION (1<<27) | |
393 | #define NV_TX2_UNDERFLOW (1<<28) | |
394 | /* error and valid are the same for both */ | |
395 | #define NV_TX2_ERROR (1<<30) | |
396 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
397 | #define NV_TX2_TSO (1<<28) |
398 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
399 | #define NV_TX2_TSO_MAX_SHIFT 14 |
400 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
401 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
402 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 403 | |
ee407b02 AA |
404 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
405 | ||
1da177e4 LT |
406 | #define NV_RX_DESCRIPTORVALID (1<<16) |
407 | #define NV_RX_MISSEDFRAME (1<<17) | |
408 | #define NV_RX_SUBSTRACT1 (1<<18) | |
409 | #define NV_RX_ERROR1 (1<<23) | |
410 | #define NV_RX_ERROR2 (1<<24) | |
411 | #define NV_RX_ERROR3 (1<<25) | |
412 | #define NV_RX_ERROR4 (1<<26) | |
413 | #define NV_RX_CRCERR (1<<27) | |
414 | #define NV_RX_OVERFLOW (1<<28) | |
415 | #define NV_RX_FRAMINGERR (1<<29) | |
416 | #define NV_RX_ERROR (1<<30) | |
417 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 418 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
419 | |
420 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
421 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
422 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
423 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 LT |
424 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
425 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
426 | #define NV_RX2_ERROR1 (1<<18) | |
427 | #define NV_RX2_ERROR2 (1<<19) | |
428 | #define NV_RX2_ERROR3 (1<<20) | |
429 | #define NV_RX2_ERROR4 (1<<21) | |
430 | #define NV_RX2_CRCERR (1<<22) | |
431 | #define NV_RX2_OVERFLOW (1<<23) | |
432 | #define NV_RX2_FRAMINGERR (1<<24) | |
433 | /* error and avail are the same for both */ | |
434 | #define NV_RX2_ERROR (1<<30) | |
435 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 436 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 437 | |
ee407b02 AA |
438 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
439 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
440 | ||
1da177e4 | 441 | /* Miscelaneous hardware related defines: */ |
86a0f043 | 442 | #define NV_PCI_REGSZ_VER1 0x270 |
57fff698 AA |
443 | #define NV_PCI_REGSZ_VER2 0x2d4 |
444 | #define NV_PCI_REGSZ_VER3 0x604 | |
1a1ca861 | 445 | #define NV_PCI_REGSZ_MAX 0x604 |
1da177e4 LT |
446 | |
447 | /* various timeout delays: all in usec */ | |
448 | #define NV_TXRX_RESET_DELAY 4 | |
449 | #define NV_TXSTOP_DELAY1 10 | |
450 | #define NV_TXSTOP_DELAY1MAX 500000 | |
451 | #define NV_TXSTOP_DELAY2 100 | |
452 | #define NV_RXSTOP_DELAY1 10 | |
453 | #define NV_RXSTOP_DELAY1MAX 500000 | |
454 | #define NV_RXSTOP_DELAY2 100 | |
455 | #define NV_SETUP5_DELAY 5 | |
456 | #define NV_SETUP5_DELAYMAX 50000 | |
457 | #define NV_POWERUP_DELAY 5 | |
458 | #define NV_POWERUP_DELAYMAX 5000 | |
459 | #define NV_MIIBUSY_DELAY 50 | |
460 | #define NV_MIIPHY_DELAY 10 | |
461 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 462 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
463 | |
464 | #define NV_WAKEUPPATTERNS 5 | |
465 | #define NV_WAKEUPMASKENTRIES 4 | |
466 | ||
467 | /* General driver defaults */ | |
468 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
469 | ||
eafa59f6 AA |
470 | #define RX_RING_DEFAULT 128 |
471 | #define TX_RING_DEFAULT 256 | |
472 | #define RX_RING_MIN 128 | |
473 | #define TX_RING_MIN 64 | |
474 | #define RING_MAX_DESC_VER_1 1024 | |
475 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
476 | |
477 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
478 | #define NV_RX_HEADERS (64) |
479 | /* even more slack. */ | |
480 | #define NV_RX_ALLOC_PAD (64) | |
481 | ||
482 | /* maximum mtu size */ | |
483 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
484 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
485 | |
486 | #define OOM_REFILL (1+HZ/20) | |
487 | #define POLL_WAIT (1+HZ/100) | |
488 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 489 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 490 | |
f3b197ac | 491 | /* |
1da177e4 | 492 | * desc_ver values: |
8a4ae7f2 MS |
493 | * The nic supports three different descriptor types: |
494 | * - DESC_VER_1: Original | |
495 | * - DESC_VER_2: support for jumbo frames. | |
496 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 497 | */ |
8a4ae7f2 MS |
498 | #define DESC_VER_1 1 |
499 | #define DESC_VER_2 2 | |
500 | #define DESC_VER_3 3 | |
1da177e4 LT |
501 | |
502 | /* PHY defines */ | |
9f3f7910 AA |
503 | #define PHY_OUI_MARVELL 0x5043 |
504 | #define PHY_OUI_CICADA 0x03f1 | |
505 | #define PHY_OUI_VITESSE 0x01c1 | |
506 | #define PHY_OUI_REALTEK 0x0732 | |
507 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
508 | #define PHYID1_OUI_MASK 0x03ff |
509 | #define PHYID1_OUI_SHFT 6 | |
510 | #define PHYID2_OUI_MASK 0xfc00 | |
511 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 512 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
513 | #define PHY_MODEL_REALTEK_8211 0x0110 |
514 | #define PHY_REV_MASK 0x0001 | |
515 | #define PHY_REV_REALTEK_8211B 0x0000 | |
516 | #define PHY_REV_REALTEK_8211C 0x0001 | |
517 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
518 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 519 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
520 | #define PHY_CICADA_INIT1 0x0f000 |
521 | #define PHY_CICADA_INIT2 0x0e00 | |
522 | #define PHY_CICADA_INIT3 0x01000 | |
523 | #define PHY_CICADA_INIT4 0x0200 | |
524 | #define PHY_CICADA_INIT5 0x0004 | |
525 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
526 | #define PHY_VITESSE_INIT_REG1 0x1f |
527 | #define PHY_VITESSE_INIT_REG2 0x10 | |
528 | #define PHY_VITESSE_INIT_REG3 0x11 | |
529 | #define PHY_VITESSE_INIT_REG4 0x12 | |
530 | #define PHY_VITESSE_INIT_MSK1 0xc | |
531 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
532 | #define PHY_VITESSE_INIT1 0x52b5 | |
533 | #define PHY_VITESSE_INIT2 0xaf8a | |
534 | #define PHY_VITESSE_INIT3 0x8 | |
535 | #define PHY_VITESSE_INIT4 0x8f8a | |
536 | #define PHY_VITESSE_INIT5 0xaf86 | |
537 | #define PHY_VITESSE_INIT6 0x8f86 | |
538 | #define PHY_VITESSE_INIT7 0xaf82 | |
539 | #define PHY_VITESSE_INIT8 0x0100 | |
540 | #define PHY_VITESSE_INIT9 0x8f82 | |
541 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
542 | #define PHY_REALTEK_INIT_REG1 0x1f |
543 | #define PHY_REALTEK_INIT_REG2 0x19 | |
544 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
545 | #define PHY_REALTEK_INIT_REG4 0x14 |
546 | #define PHY_REALTEK_INIT_REG5 0x18 | |
547 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 548 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
549 | #define PHY_REALTEK_INIT1 0x0000 |
550 | #define PHY_REALTEK_INIT2 0x8e00 | |
551 | #define PHY_REALTEK_INIT3 0x0001 | |
552 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
553 | #define PHY_REALTEK_INIT5 0xfb54 |
554 | #define PHY_REALTEK_INIT6 0xf5c7 | |
555 | #define PHY_REALTEK_INIT7 0x1000 | |
556 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
557 | #define PHY_REALTEK_INIT9 0x0008 |
558 | #define PHY_REALTEK_INIT10 0x0005 | |
559 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 560 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 561 | |
1da177e4 LT |
562 | #define PHY_GIGABIT 0x0100 |
563 | ||
564 | #define PHY_TIMEOUT 0x1 | |
565 | #define PHY_ERROR 0x2 | |
566 | ||
567 | #define PHY_100 0x1 | |
568 | #define PHY_1000 0x2 | |
569 | #define PHY_HALF 0x100 | |
570 | ||
eb91f61b AA |
571 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
572 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
573 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
574 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
575 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
576 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
577 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 578 | |
d33a73c8 AA |
579 | /* MSI/MSI-X defines */ |
580 | #define NV_MSI_X_MAX_VECTORS 8 | |
581 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
582 | #define NV_MSI_CAPABLE 0x0010 | |
583 | #define NV_MSI_X_CAPABLE 0x0020 | |
584 | #define NV_MSI_ENABLED 0x0040 | |
585 | #define NV_MSI_X_ENABLED 0x0080 | |
586 | ||
587 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
588 | #define NV_MSI_X_VECTOR_RX 0x0 | |
589 | #define NV_MSI_X_VECTOR_TX 0x1 | |
590 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 591 | |
b6e4405b AA |
592 | #define NV_MSI_PRIV_OFFSET 0x68 |
593 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
594 | ||
b2976d23 AA |
595 | #define NV_RESTART_TX 0x1 |
596 | #define NV_RESTART_RX 0x2 | |
597 | ||
3b446c3e AA |
598 | #define NV_TX_LIMIT_COUNT 16 |
599 | ||
52da3578 AA |
600 | /* statistics */ |
601 | struct nv_ethtool_str { | |
602 | char name[ETH_GSTRING_LEN]; | |
603 | }; | |
604 | ||
605 | static const struct nv_ethtool_str nv_estats_str[] = { | |
606 | { "tx_bytes" }, | |
607 | { "tx_zero_rexmt" }, | |
608 | { "tx_one_rexmt" }, | |
609 | { "tx_many_rexmt" }, | |
610 | { "tx_late_collision" }, | |
611 | { "tx_fifo_errors" }, | |
612 | { "tx_carrier_errors" }, | |
613 | { "tx_excess_deferral" }, | |
614 | { "tx_retry_error" }, | |
52da3578 AA |
615 | { "rx_frame_error" }, |
616 | { "rx_extra_byte" }, | |
617 | { "rx_late_collision" }, | |
618 | { "rx_runt" }, | |
619 | { "rx_frame_too_long" }, | |
620 | { "rx_over_errors" }, | |
621 | { "rx_crc_errors" }, | |
622 | { "rx_frame_align_error" }, | |
623 | { "rx_length_error" }, | |
624 | { "rx_unicast" }, | |
625 | { "rx_multicast" }, | |
626 | { "rx_broadcast" }, | |
57fff698 AA |
627 | { "rx_packets" }, |
628 | { "rx_errors_total" }, | |
629 | { "tx_errors_total" }, | |
630 | ||
631 | /* version 2 stats */ | |
632 | { "tx_deferral" }, | |
633 | { "tx_packets" }, | |
52da3578 | 634 | { "rx_bytes" }, |
57fff698 | 635 | { "tx_pause" }, |
52da3578 | 636 | { "rx_pause" }, |
9c662435 AA |
637 | { "rx_drop_frame" }, |
638 | ||
639 | /* version 3 stats */ | |
640 | { "tx_unicast" }, | |
641 | { "tx_multicast" }, | |
642 | { "tx_broadcast" } | |
52da3578 AA |
643 | }; |
644 | ||
645 | struct nv_ethtool_stats { | |
646 | u64 tx_bytes; | |
647 | u64 tx_zero_rexmt; | |
648 | u64 tx_one_rexmt; | |
649 | u64 tx_many_rexmt; | |
650 | u64 tx_late_collision; | |
651 | u64 tx_fifo_errors; | |
652 | u64 tx_carrier_errors; | |
653 | u64 tx_excess_deferral; | |
654 | u64 tx_retry_error; | |
52da3578 AA |
655 | u64 rx_frame_error; |
656 | u64 rx_extra_byte; | |
657 | u64 rx_late_collision; | |
658 | u64 rx_runt; | |
659 | u64 rx_frame_too_long; | |
660 | u64 rx_over_errors; | |
661 | u64 rx_crc_errors; | |
662 | u64 rx_frame_align_error; | |
663 | u64 rx_length_error; | |
664 | u64 rx_unicast; | |
665 | u64 rx_multicast; | |
666 | u64 rx_broadcast; | |
57fff698 AA |
667 | u64 rx_packets; |
668 | u64 rx_errors_total; | |
669 | u64 tx_errors_total; | |
670 | ||
671 | /* version 2 stats */ | |
672 | u64 tx_deferral; | |
673 | u64 tx_packets; | |
52da3578 | 674 | u64 rx_bytes; |
57fff698 | 675 | u64 tx_pause; |
52da3578 AA |
676 | u64 rx_pause; |
677 | u64 rx_drop_frame; | |
9c662435 AA |
678 | |
679 | /* version 3 stats */ | |
680 | u64 tx_unicast; | |
681 | u64 tx_multicast; | |
682 | u64 tx_broadcast; | |
52da3578 AA |
683 | }; |
684 | ||
9c662435 AA |
685 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
686 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
687 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
688 | ||
9589c77a AA |
689 | /* diagnostics */ |
690 | #define NV_TEST_COUNT_BASE 3 | |
691 | #define NV_TEST_COUNT_EXTENDED 4 | |
692 | ||
693 | static const struct nv_ethtool_str nv_etests_str[] = { | |
694 | { "link (online/offline)" }, | |
695 | { "register (offline) " }, | |
696 | { "interrupt (offline) " }, | |
697 | { "loopback (offline) " } | |
698 | }; | |
699 | ||
700 | struct register_test { | |
5bb7ea26 AV |
701 | __u32 reg; |
702 | __u32 mask; | |
9589c77a AA |
703 | }; |
704 | ||
705 | static const struct register_test nv_registers_test[] = { | |
706 | { NvRegUnknownSetupReg6, 0x01 }, | |
707 | { NvRegMisc1, 0x03c }, | |
708 | { NvRegOffloadConfig, 0x03ff }, | |
709 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 710 | { NvRegTxWatermark, 0x0ff }, |
9589c77a AA |
711 | { NvRegWakeUpFlags, 0x07777 }, |
712 | { 0,0 } | |
713 | }; | |
714 | ||
761fcd9e AA |
715 | struct nv_skb_map { |
716 | struct sk_buff *skb; | |
717 | dma_addr_t dma; | |
718 | unsigned int dma_len; | |
3b446c3e AA |
719 | struct ring_desc_ex *first_tx_desc; |
720 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
721 | }; |
722 | ||
1da177e4 LT |
723 | /* |
724 | * SMP locking: | |
b74ca3a8 | 725 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
726 | * critical parts: |
727 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
728 | * by the arch code for interrupts. | |
932ff279 | 729 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 730 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 731 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
732 | */ |
733 | ||
734 | /* in dev: base, irq */ | |
735 | struct fe_priv { | |
736 | spinlock_t lock; | |
737 | ||
bea3348e SH |
738 | struct net_device *dev; |
739 | struct napi_struct napi; | |
740 | ||
1da177e4 LT |
741 | /* General data: |
742 | * Locking: spin_lock(&np->lock); */ | |
52da3578 | 743 | struct nv_ethtool_stats estats; |
1da177e4 LT |
744 | int in_shutdown; |
745 | u32 linkspeed; | |
746 | int duplex; | |
747 | int autoneg; | |
748 | int fixed_mode; | |
749 | int phyaddr; | |
750 | int wolenabled; | |
751 | unsigned int phy_oui; | |
edf7e5ec | 752 | unsigned int phy_model; |
9f3f7910 | 753 | unsigned int phy_rev; |
1da177e4 | 754 | u16 gigabit; |
9589c77a | 755 | int intr_test; |
c5cf9101 | 756 | int recover_error; |
1da177e4 LT |
757 | |
758 | /* General data: RO fields */ | |
759 | dma_addr_t ring_addr; | |
760 | struct pci_dev *pci_dev; | |
761 | u32 orig_mac[2]; | |
762 | u32 irqmask; | |
763 | u32 desc_ver; | |
8a4ae7f2 | 764 | u32 txrxctl_bits; |
ee407b02 | 765 | u32 vlanctl_bits; |
86a0f043 | 766 | u32 driver_data; |
9f3f7910 | 767 | u32 device_id; |
86a0f043 | 768 | u32 register_size; |
f2ad2d9b | 769 | int rx_csum; |
7e680c22 | 770 | u32 mac_in_use; |
cac1c52c AA |
771 | int mgmt_version; |
772 | int mgmt_sema; | |
1da177e4 LT |
773 | |
774 | void __iomem *base; | |
775 | ||
776 | /* rx specific fields. | |
777 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
778 | */ | |
761fcd9e AA |
779 | union ring_type get_rx, put_rx, first_rx, last_rx; |
780 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
781 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
782 | struct nv_skb_map *rx_skb; | |
783 | ||
f82a9352 | 784 | union ring_type rx_ring; |
1da177e4 | 785 | unsigned int rx_buf_sz; |
d81c0983 | 786 | unsigned int pkt_limit; |
1da177e4 LT |
787 | struct timer_list oom_kick; |
788 | struct timer_list nic_poll; | |
52da3578 | 789 | struct timer_list stats_poll; |
d33a73c8 | 790 | u32 nic_poll_irq; |
eafa59f6 | 791 | int rx_ring_size; |
1da177e4 LT |
792 | |
793 | /* media detection workaround. | |
794 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
795 | */ | |
796 | int need_linktimer; | |
797 | unsigned long link_timeout; | |
798 | /* | |
799 | * tx specific fields. | |
800 | */ | |
761fcd9e AA |
801 | union ring_type get_tx, put_tx, first_tx, last_tx; |
802 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
803 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
804 | struct nv_skb_map *tx_skb; | |
805 | ||
f82a9352 | 806 | union ring_type tx_ring; |
1da177e4 | 807 | u32 tx_flags; |
eafa59f6 | 808 | int tx_ring_size; |
3b446c3e AA |
809 | int tx_limit; |
810 | u32 tx_pkts_in_progress; | |
811 | struct nv_skb_map *tx_change_owner; | |
812 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 813 | int tx_stop; |
ee407b02 AA |
814 | |
815 | /* vlan fields */ | |
816 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
817 | |
818 | /* msi/msi-x fields */ | |
819 | u32 msi_flags; | |
820 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
821 | |
822 | /* flow control */ | |
823 | u32 pause_flags; | |
1a1ca861 TD |
824 | |
825 | /* power saved state */ | |
826 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
827 | |
828 | /* for different msi-x irq type */ | |
829 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
830 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
831 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
832 | }; |
833 | ||
834 | /* | |
835 | * Maximum number of loops until we assume that a bit in the irq mask | |
836 | * is stuck. Overridable with module param. | |
837 | */ | |
dccd547e | 838 | static int max_interrupt_work = 15; |
1da177e4 | 839 | |
a971c324 AA |
840 | /* |
841 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 842 | * |
a971c324 AA |
843 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
844 | * CPU Mode: Interrupts are controlled by a timer. | |
845 | */ | |
69fe3fd7 AA |
846 | enum { |
847 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
848 | NV_OPTIMIZATION_MODE_CPU | |
849 | }; | |
a971c324 AA |
850 | static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
851 | ||
852 | /* | |
853 | * Poll interval for timer irq | |
854 | * | |
855 | * This interval determines how frequent an interrupt is generated. | |
856 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
857 | * Min = 0, and Max = 65535 | |
858 | */ | |
859 | static int poll_interval = -1; | |
860 | ||
d33a73c8 | 861 | /* |
69fe3fd7 | 862 | * MSI interrupts |
d33a73c8 | 863 | */ |
69fe3fd7 AA |
864 | enum { |
865 | NV_MSI_INT_DISABLED, | |
866 | NV_MSI_INT_ENABLED | |
867 | }; | |
868 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
869 | |
870 | /* | |
69fe3fd7 | 871 | * MSIX interrupts |
d33a73c8 | 872 | */ |
69fe3fd7 AA |
873 | enum { |
874 | NV_MSIX_INT_DISABLED, | |
875 | NV_MSIX_INT_ENABLED | |
876 | }; | |
39482791 | 877 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
878 | |
879 | /* | |
880 | * DMA 64bit | |
881 | */ | |
882 | enum { | |
883 | NV_DMA_64BIT_DISABLED, | |
884 | NV_DMA_64BIT_ENABLED | |
885 | }; | |
886 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 887 | |
9f3f7910 AA |
888 | /* |
889 | * Crossover Detection | |
890 | * Realtek 8201 phy + some OEM boards do not work properly. | |
891 | */ | |
892 | enum { | |
893 | NV_CROSSOVER_DETECTION_DISABLED, | |
894 | NV_CROSSOVER_DETECTION_ENABLED | |
895 | }; | |
896 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
897 | ||
1da177e4 LT |
898 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
899 | { | |
900 | return netdev_priv(dev); | |
901 | } | |
902 | ||
903 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
904 | { | |
ac9c1897 | 905 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
906 | } |
907 | ||
908 | static inline void pci_push(u8 __iomem *base) | |
909 | { | |
910 | /* force out pending posted writes */ | |
911 | readl(base); | |
912 | } | |
913 | ||
914 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
915 | { | |
f82a9352 | 916 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
917 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
918 | } | |
919 | ||
ee73362c MS |
920 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
921 | { | |
f82a9352 | 922 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
923 | } |
924 | ||
36b30ea9 JG |
925 | static bool nv_optimized(struct fe_priv *np) |
926 | { | |
927 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
928 | return false; | |
929 | return true; | |
930 | } | |
931 | ||
1da177e4 LT |
932 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
933 | int delay, int delaymax, const char *msg) | |
934 | { | |
935 | u8 __iomem *base = get_hwbase(dev); | |
936 | ||
937 | pci_push(base); | |
938 | do { | |
939 | udelay(delay); | |
940 | delaymax -= delay; | |
941 | if (delaymax < 0) { | |
942 | if (msg) | |
943 | printk(msg); | |
944 | return 1; | |
945 | } | |
946 | } while ((readl(base + offset) & mask) != target); | |
947 | return 0; | |
948 | } | |
949 | ||
0832b25a AA |
950 | #define NV_SETUP_RX_RING 0x01 |
951 | #define NV_SETUP_TX_RING 0x02 | |
952 | ||
5bb7ea26 AV |
953 | static inline u32 dma_low(dma_addr_t addr) |
954 | { | |
955 | return addr; | |
956 | } | |
957 | ||
958 | static inline u32 dma_high(dma_addr_t addr) | |
959 | { | |
960 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
961 | } | |
962 | ||
0832b25a AA |
963 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
964 | { | |
965 | struct fe_priv *np = get_nvpriv(dev); | |
966 | u8 __iomem *base = get_hwbase(dev); | |
967 | ||
36b30ea9 | 968 | if (!nv_optimized(np)) { |
0832b25a | 969 | if (rxtx_flags & NV_SETUP_RX_RING) { |
5bb7ea26 | 970 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
0832b25a AA |
971 | } |
972 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 | 973 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
974 | } |
975 | } else { | |
976 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
977 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
978 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
979 | } |
980 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
981 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
982 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
983 | } |
984 | } | |
985 | } | |
986 | ||
eafa59f6 AA |
987 | static void free_rings(struct net_device *dev) |
988 | { | |
989 | struct fe_priv *np = get_nvpriv(dev); | |
990 | ||
36b30ea9 | 991 | if (!nv_optimized(np)) { |
f82a9352 | 992 | if (np->rx_ring.orig) |
eafa59f6 AA |
993 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
994 | np->rx_ring.orig, np->ring_addr); | |
995 | } else { | |
996 | if (np->rx_ring.ex) | |
997 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
998 | np->rx_ring.ex, np->ring_addr); | |
999 | } | |
761fcd9e AA |
1000 | if (np->rx_skb) |
1001 | kfree(np->rx_skb); | |
1002 | if (np->tx_skb) | |
1003 | kfree(np->tx_skb); | |
eafa59f6 AA |
1004 | } |
1005 | ||
84b3932b AA |
1006 | static int using_multi_irqs(struct net_device *dev) |
1007 | { | |
1008 | struct fe_priv *np = get_nvpriv(dev); | |
1009 | ||
1010 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1011 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1012 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1013 | return 0; | |
1014 | else | |
1015 | return 1; | |
1016 | } | |
1017 | ||
1018 | static void nv_enable_irq(struct net_device *dev) | |
1019 | { | |
1020 | struct fe_priv *np = get_nvpriv(dev); | |
1021 | ||
1022 | if (!using_multi_irqs(dev)) { | |
1023 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1024 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1025 | else | |
a7475906 | 1026 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1027 | } else { |
1028 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1029 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1030 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | static void nv_disable_irq(struct net_device *dev) | |
1035 | { | |
1036 | struct fe_priv *np = get_nvpriv(dev); | |
1037 | ||
1038 | if (!using_multi_irqs(dev)) { | |
1039 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1040 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1041 | else | |
a7475906 | 1042 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1043 | } else { |
1044 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1045 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1046 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1051 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1052 | { | |
1053 | u8 __iomem *base = get_hwbase(dev); | |
1054 | ||
1055 | writel(mask, base + NvRegIrqMask); | |
1056 | } | |
1057 | ||
1058 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1059 | { | |
1060 | struct fe_priv *np = get_nvpriv(dev); | |
1061 | u8 __iomem *base = get_hwbase(dev); | |
1062 | ||
1063 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1064 | writel(mask, base + NvRegIrqMask); | |
1065 | } else { | |
1066 | if (np->msi_flags & NV_MSI_ENABLED) | |
1067 | writel(0, base + NvRegMSIIrqMask); | |
1068 | writel(0, base + NvRegIrqMask); | |
1069 | } | |
1070 | } | |
1071 | ||
1da177e4 LT |
1072 | #define MII_READ (-1) |
1073 | /* mii_rw: read/write a register on the PHY. | |
1074 | * | |
1075 | * Caller must guarantee serialization | |
1076 | */ | |
1077 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1078 | { | |
1079 | u8 __iomem *base = get_hwbase(dev); | |
1080 | u32 reg; | |
1081 | int retval; | |
1082 | ||
eb798428 | 1083 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1084 | |
1085 | reg = readl(base + NvRegMIIControl); | |
1086 | if (reg & NVREG_MIICTL_INUSE) { | |
1087 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1088 | udelay(NV_MIIBUSY_DELAY); | |
1089 | } | |
1090 | ||
1091 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1092 | if (value != MII_READ) { | |
1093 | writel(value, base + NvRegMIIData); | |
1094 | reg |= NVREG_MIICTL_WRITE; | |
1095 | } | |
1096 | writel(reg, base + NvRegMIIControl); | |
1097 | ||
1098 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
1099 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | |
1100 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | |
1101 | dev->name, miireg, addr); | |
1102 | retval = -1; | |
1103 | } else if (value != MII_READ) { | |
1104 | /* it was a write operation - fewer failures are detectable */ | |
1105 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | |
1106 | dev->name, value, miireg, addr); | |
1107 | retval = 0; | |
1108 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1109 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | |
1110 | dev->name, miireg, addr); | |
1111 | retval = -1; | |
1112 | } else { | |
1113 | retval = readl(base + NvRegMIIData); | |
1114 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | |
1115 | dev->name, miireg, addr, retval); | |
1116 | } | |
1117 | ||
1118 | return retval; | |
1119 | } | |
1120 | ||
edf7e5ec | 1121 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1122 | { |
ac9c1897 | 1123 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1124 | u32 miicontrol; |
1125 | unsigned int tries = 0; | |
1126 | ||
edf7e5ec | 1127 | miicontrol = BMCR_RESET | bmcr_setup; |
1da177e4 LT |
1128 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
1129 | return -1; | |
1130 | } | |
1131 | ||
1132 | /* wait for 500ms */ | |
1133 | msleep(500); | |
1134 | ||
1135 | /* must wait till reset is deasserted */ | |
1136 | while (miicontrol & BMCR_RESET) { | |
1137 | msleep(10); | |
1138 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1139 | /* FIXME: 100 tries seem excessive */ | |
1140 | if (tries++ > 100) | |
1141 | return -1; | |
1142 | } | |
1143 | return 0; | |
1144 | } | |
1145 | ||
1146 | static int phy_init(struct net_device *dev) | |
1147 | { | |
1148 | struct fe_priv *np = get_nvpriv(dev); | |
1149 | u8 __iomem *base = get_hwbase(dev); | |
1150 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; | |
1151 | ||
edf7e5ec AA |
1152 | /* phy errata for E3016 phy */ |
1153 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1154 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1155 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1156 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1157 | printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); | |
1158 | return PHY_ERROR; | |
1159 | } | |
1160 | } | |
c5e3ae88 | 1161 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1162 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1163 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1164 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1165 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1166 | return PHY_ERROR; | |
1167 | } | |
1168 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1169 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1170 | return PHY_ERROR; | |
1171 | } | |
1172 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1173 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1174 | return PHY_ERROR; | |
1175 | } | |
1176 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1177 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1178 | return PHY_ERROR; | |
1179 | } | |
1180 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | |
1181 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1182 | return PHY_ERROR; | |
1183 | } | |
1184 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | |
1185 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1186 | return PHY_ERROR; | |
1187 | } | |
1188 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1189 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1190 | return PHY_ERROR; | |
1191 | } | |
c5e3ae88 | 1192 | } |
22ae03a1 AA |
1193 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1194 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1195 | u32 powerstate = readl(base + NvRegPowerState2); | |
1196 | ||
1197 | /* need to perform hw phy reset */ | |
1198 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1199 | writel(powerstate, base + NvRegPowerState2); | |
1200 | msleep(25); | |
1201 | ||
1202 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1203 | writel(powerstate, base + NvRegPowerState2); | |
1204 | msleep(25); | |
1205 | ||
1206 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1207 | reg |= PHY_REALTEK_INIT9; | |
1208 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { | |
1209 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1210 | return PHY_ERROR; | |
1211 | } | |
1212 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { | |
1213 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1214 | return PHY_ERROR; | |
1215 | } | |
1216 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1217 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1218 | reg |= PHY_REALTEK_INIT11; | |
1219 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { | |
1220 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1221 | return PHY_ERROR; | |
1222 | } | |
1223 | } | |
1224 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1225 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1226 | return PHY_ERROR; | |
1227 | } | |
1228 | } | |
9f3f7910 AA |
1229 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1230 | if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || | |
1231 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 || | |
1232 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 || | |
1233 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 || | |
1234 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 || | |
1235 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 || | |
1236 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 || | |
1237 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) { | |
1238 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1239 | phy_reserved |= PHY_REALTEK_INIT7; | |
1240 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1241 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1242 | return PHY_ERROR; | |
1243 | } | |
1244 | } | |
c5e3ae88 AA |
1245 | } |
1246 | } | |
edf7e5ec | 1247 | |
1da177e4 LT |
1248 | /* set advertise register */ |
1249 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 1250 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1da177e4 LT |
1251 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1252 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | |
1253 | return PHY_ERROR; | |
1254 | } | |
1255 | ||
1256 | /* get phy interface type */ | |
1257 | phyinterface = readl(base + NvRegPhyInterface); | |
1258 | ||
1259 | /* see if gigabit phy */ | |
1260 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1261 | if (mii_status & PHY_GIGABIT) { | |
1262 | np->gigabit = PHY_GIGABIT; | |
eb91f61b | 1263 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
1264 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1265 | if (phyinterface & PHY_RGMII) | |
1266 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1267 | else | |
1268 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1269 | ||
eb91f61b | 1270 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1da177e4 LT |
1271 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1272 | return PHY_ERROR; | |
1273 | } | |
1274 | } | |
1275 | else | |
1276 | np->gigabit = 0; | |
1277 | ||
edf7e5ec AA |
1278 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1279 | mii_control |= BMCR_ANENABLE; | |
1280 | ||
22ae03a1 AA |
1281 | if (np->phy_oui == PHY_OUI_REALTEK && |
1282 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1283 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1284 | /* start autoneg since we already performed hw reset above */ | |
1285 | mii_control |= BMCR_ANRESTART; | |
1286 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1287 | printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev)); | |
1288 | return PHY_ERROR; | |
1289 | } | |
1290 | } else { | |
1291 | /* reset the phy | |
1292 | * (certain phys need bmcr to be setup with reset) | |
1293 | */ | |
1294 | if (phy_reset(dev, mii_control)) { | |
1295 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); | |
1296 | return PHY_ERROR; | |
1297 | } | |
1da177e4 LT |
1298 | } |
1299 | ||
1300 | /* phy vendor specific configuration */ | |
1301 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { | |
1302 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
14a67f3c AA |
1303 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1304 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1da177e4 LT |
1305 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1306 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1307 | return PHY_ERROR; | |
1308 | } | |
1309 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
14a67f3c | 1310 | phy_reserved |= PHY_CICADA_INIT5; |
1da177e4 LT |
1311 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1312 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1313 | return PHY_ERROR; | |
1314 | } | |
1315 | } | |
1316 | if (np->phy_oui == PHY_OUI_CICADA) { | |
1317 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
14a67f3c | 1318 | phy_reserved |= PHY_CICADA_INIT6; |
1da177e4 LT |
1319 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1320 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1321 | return PHY_ERROR; | |
1322 | } | |
1323 | } | |
d215d8a2 AA |
1324 | if (np->phy_oui == PHY_OUI_VITESSE) { |
1325 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | |
1326 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1327 | return PHY_ERROR; | |
1328 | } | |
1329 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | |
1330 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1331 | return PHY_ERROR; | |
1332 | } | |
1333 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1334 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1335 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1336 | return PHY_ERROR; | |
1337 | } | |
1338 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1339 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1340 | phy_reserved |= PHY_VITESSE_INIT3; | |
1341 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1342 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1343 | return PHY_ERROR; | |
1344 | } | |
1345 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | |
1346 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1347 | return PHY_ERROR; | |
1348 | } | |
1349 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | |
1350 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1351 | return PHY_ERROR; | |
1352 | } | |
1353 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1354 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1355 | phy_reserved |= PHY_VITESSE_INIT3; | |
1356 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1357 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1358 | return PHY_ERROR; | |
1359 | } | |
1360 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1361 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1362 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1363 | return PHY_ERROR; | |
1364 | } | |
1365 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | |
1366 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1367 | return PHY_ERROR; | |
1368 | } | |
1369 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | |
1370 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1371 | return PHY_ERROR; | |
1372 | } | |
1373 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1374 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1375 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1376 | return PHY_ERROR; | |
1377 | } | |
1378 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1379 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1380 | phy_reserved |= PHY_VITESSE_INIT8; | |
1381 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1382 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1383 | return PHY_ERROR; | |
1384 | } | |
1385 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | |
1386 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1387 | return PHY_ERROR; | |
1388 | } | |
1389 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | |
1390 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1391 | return PHY_ERROR; | |
1392 | } | |
1393 | } | |
c5e3ae88 | 1394 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1395 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1396 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1397 | /* reset could have cleared these out, set them back */ | |
1398 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1399 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1400 | return PHY_ERROR; | |
1401 | } | |
1402 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1403 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1404 | return PHY_ERROR; | |
1405 | } | |
1406 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1407 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1408 | return PHY_ERROR; | |
1409 | } | |
1410 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1411 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1412 | return PHY_ERROR; | |
1413 | } | |
1414 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { | |
1415 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1416 | return PHY_ERROR; | |
1417 | } | |
1418 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { | |
1419 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1420 | return PHY_ERROR; | |
1421 | } | |
1422 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1423 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1424 | return PHY_ERROR; | |
1425 | } | |
c5e3ae88 | 1426 | } |
9f3f7910 AA |
1427 | if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1428 | if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || | |
1429 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 || | |
1430 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_34 || | |
1431 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_35 || | |
1432 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_36 || | |
1433 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_37 || | |
1434 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_38 || | |
1435 | np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_39) { | |
1436 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1437 | phy_reserved |= PHY_REALTEK_INIT7; | |
1438 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { | |
1439 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1440 | return PHY_ERROR; | |
1441 | } | |
1442 | } | |
1443 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1444 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1445 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1446 | return PHY_ERROR; | |
1447 | } | |
1448 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
1449 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1450 | phy_reserved |= PHY_REALTEK_INIT3; | |
1451 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { | |
1452 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1453 | return PHY_ERROR; | |
1454 | } | |
1455 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1456 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1457 | return PHY_ERROR; | |
1458 | } | |
1459 | } | |
c5e3ae88 AA |
1460 | } |
1461 | } | |
1462 | ||
eb91f61b AA |
1463 | /* some phys clear out pause advertisment on reset, set it back */ |
1464 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); | |
1da177e4 | 1465 | |
cb52deba | 1466 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1467 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
cb52deba | 1468 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE | BMCR_PDOWN); |
1da177e4 LT |
1469 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
1470 | return PHY_ERROR; | |
1471 | } | |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static void nv_start_rx(struct net_device *dev) | |
1477 | { | |
ac9c1897 | 1478 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1479 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1480 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1481 | |
1482 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | |
1483 | /* Already running? Stop it. */ | |
f35723ec AA |
1484 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1485 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1486 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1487 | pci_push(base); |
1488 | } | |
1489 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1490 | pci_push(base); | |
f35723ec AA |
1491 | rx_ctrl |= NVREG_RCVCTL_START; |
1492 | if (np->mac_in_use) | |
1493 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; | |
1494 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1495 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1496 | dev->name, np->duplex, np->linkspeed); | |
1497 | pci_push(base); | |
1498 | } | |
1499 | ||
1500 | static void nv_stop_rx(struct net_device *dev) | |
1501 | { | |
f35723ec | 1502 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1503 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1504 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1505 | |
1506 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | |
f35723ec AA |
1507 | if (!np->mac_in_use) |
1508 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1509 | else | |
1510 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1511 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1512 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1513 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | |
1514 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | |
1515 | ||
1516 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1517 | if (!np->mac_in_use) |
1518 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1519 | } |
1520 | ||
1521 | static void nv_start_tx(struct net_device *dev) | |
1522 | { | |
f35723ec | 1523 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1524 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1525 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1526 | |
1527 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | |
f35723ec AA |
1528 | tx_ctrl |= NVREG_XMITCTL_START; |
1529 | if (np->mac_in_use) | |
1530 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1531 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1532 | pci_push(base); |
1533 | } | |
1534 | ||
1535 | static void nv_stop_tx(struct net_device *dev) | |
1536 | { | |
f35723ec | 1537 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1538 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1539 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1540 | |
1541 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | |
f35723ec AA |
1542 | if (!np->mac_in_use) |
1543 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1544 | else | |
1545 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1546 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1547 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1548 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | |
1549 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | |
1550 | ||
1551 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1552 | if (!np->mac_in_use) |
1553 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1554 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1555 | } |
1556 | ||
36b30ea9 JG |
1557 | static void nv_start_rxtx(struct net_device *dev) |
1558 | { | |
1559 | nv_start_rx(dev); | |
1560 | nv_start_tx(dev); | |
1561 | } | |
1562 | ||
1563 | static void nv_stop_rxtx(struct net_device *dev) | |
1564 | { | |
1565 | nv_stop_rx(dev); | |
1566 | nv_stop_tx(dev); | |
1567 | } | |
1568 | ||
1da177e4 LT |
1569 | static void nv_txrx_reset(struct net_device *dev) |
1570 | { | |
ac9c1897 | 1571 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1572 | u8 __iomem *base = get_hwbase(dev); |
1573 | ||
1574 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | |
8a4ae7f2 | 1575 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1576 | pci_push(base); |
1577 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1578 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1579 | pci_push(base); |
1580 | } | |
1581 | ||
86a0f043 AA |
1582 | static void nv_mac_reset(struct net_device *dev) |
1583 | { | |
1584 | struct fe_priv *np = netdev_priv(dev); | |
1585 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1586 | u32 temp1, temp2, temp3; |
86a0f043 AA |
1587 | |
1588 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | |
4e84f9b1 | 1589 | |
86a0f043 AA |
1590 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1591 | pci_push(base); | |
4e84f9b1 AA |
1592 | |
1593 | /* save registers since they will be cleared on reset */ | |
1594 | temp1 = readl(base + NvRegMacAddrA); | |
1595 | temp2 = readl(base + NvRegMacAddrB); | |
1596 | temp3 = readl(base + NvRegTransmitPoll); | |
1597 | ||
86a0f043 AA |
1598 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1599 | pci_push(base); | |
1600 | udelay(NV_MAC_RESET_DELAY); | |
1601 | writel(0, base + NvRegMacReset); | |
1602 | pci_push(base); | |
1603 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1604 | |
1605 | /* restore saved registers */ | |
1606 | writel(temp1, base + NvRegMacAddrA); | |
1607 | writel(temp2, base + NvRegMacAddrB); | |
1608 | writel(temp3, base + NvRegTransmitPoll); | |
1609 | ||
86a0f043 AA |
1610 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1611 | pci_push(base); | |
1612 | } | |
1613 | ||
57fff698 AA |
1614 | static void nv_get_hw_stats(struct net_device *dev) |
1615 | { | |
1616 | struct fe_priv *np = netdev_priv(dev); | |
1617 | u8 __iomem *base = get_hwbase(dev); | |
1618 | ||
1619 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
1620 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1621 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1622 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1623 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1624 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1625 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1626 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1627 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1628 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1629 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1630 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1631 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1632 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1633 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1634 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1635 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1636 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1637 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1638 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1639 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1640 | np->estats.rx_packets = | |
1641 | np->estats.rx_unicast + | |
1642 | np->estats.rx_multicast + | |
1643 | np->estats.rx_broadcast; | |
1644 | np->estats.rx_errors_total = | |
1645 | np->estats.rx_crc_errors + | |
1646 | np->estats.rx_over_errors + | |
1647 | np->estats.rx_frame_error + | |
1648 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1649 | np->estats.rx_late_collision + | |
1650 | np->estats.rx_runt + | |
1651 | np->estats.rx_frame_too_long; | |
1652 | np->estats.tx_errors_total = | |
1653 | np->estats.tx_late_collision + | |
1654 | np->estats.tx_fifo_errors + | |
1655 | np->estats.tx_carrier_errors + | |
1656 | np->estats.tx_excess_deferral + | |
1657 | np->estats.tx_retry_error; | |
1658 | ||
1659 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1660 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1661 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1662 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1663 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1664 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1665 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
1666 | } | |
9c662435 AA |
1667 | |
1668 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1669 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1670 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1671 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1672 | } | |
57fff698 AA |
1673 | } |
1674 | ||
1da177e4 LT |
1675 | /* |
1676 | * nv_get_stats: dev->get_stats function | |
1677 | * Get latest stats value from the nic. | |
1678 | * Called with read_lock(&dev_base_lock) held for read - | |
1679 | * only synchronized against unregister_netdevice. | |
1680 | */ | |
1681 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1682 | { | |
ac9c1897 | 1683 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1684 | |
21828163 | 1685 | /* If the nic supports hw counters then retrieve latest values */ |
9c662435 | 1686 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) { |
21828163 AA |
1687 | nv_get_hw_stats(dev); |
1688 | ||
1689 | /* copy to net_device stats */ | |
8148ff45 JG |
1690 | dev->stats.tx_bytes = np->estats.tx_bytes; |
1691 | dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors; | |
1692 | dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors; | |
1693 | dev->stats.rx_crc_errors = np->estats.rx_crc_errors; | |
1694 | dev->stats.rx_over_errors = np->estats.rx_over_errors; | |
1695 | dev->stats.rx_errors = np->estats.rx_errors_total; | |
1696 | dev->stats.tx_errors = np->estats.tx_errors_total; | |
21828163 | 1697 | } |
8148ff45 JG |
1698 | |
1699 | return &dev->stats; | |
1da177e4 LT |
1700 | } |
1701 | ||
1702 | /* | |
1703 | * nv_alloc_rx: fill rx ring entries. | |
1704 | * Return 1 if the allocations for the skbs failed and the | |
1705 | * rx engine is without Available descriptors | |
1706 | */ | |
1707 | static int nv_alloc_rx(struct net_device *dev) | |
1708 | { | |
ac9c1897 | 1709 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1710 | struct ring_desc* less_rx; |
1da177e4 | 1711 | |
86b22b0d AA |
1712 | less_rx = np->get_rx.orig; |
1713 | if (less_rx-- == np->first_rx.orig) | |
1714 | less_rx = np->last_rx.orig; | |
761fcd9e | 1715 | |
86b22b0d AA |
1716 | while (np->put_rx.orig != less_rx) { |
1717 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1718 | if (skb) { | |
86b22b0d | 1719 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1720 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1721 | skb->data, | |
8b5be268 | 1722 | skb_tailroom(skb), |
4305b541 | 1723 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1724 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1725 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1726 | wmb(); | |
1727 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1728 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1729 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1730 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1731 | np->put_rx_ctx = np->first_rx_ctx; |
761fcd9e | 1732 | } else { |
86b22b0d | 1733 | return 1; |
761fcd9e | 1734 | } |
86b22b0d AA |
1735 | } |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1740 | { | |
1741 | struct fe_priv *np = netdev_priv(dev); | |
1742 | struct ring_desc_ex* less_rx; | |
1743 | ||
1744 | less_rx = np->get_rx.ex; | |
1745 | if (less_rx-- == np->first_rx.ex) | |
1746 | less_rx = np->last_rx.ex; | |
761fcd9e | 1747 | |
86b22b0d AA |
1748 | while (np->put_rx.ex != less_rx) { |
1749 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1750 | if (skb) { |
761fcd9e | 1751 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1752 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1753 | skb->data, | |
8b5be268 | 1754 | skb_tailroom(skb), |
4305b541 | 1755 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1756 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1757 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1758 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1759 | wmb(); |
1760 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1761 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1762 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1763 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1764 | np->put_rx_ctx = np->first_rx_ctx; |
1da177e4 | 1765 | } else { |
0d63fb32 | 1766 | return 1; |
ee73362c | 1767 | } |
1da177e4 | 1768 | } |
1da177e4 LT |
1769 | return 0; |
1770 | } | |
1771 | ||
e27cdba5 SH |
1772 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
1773 | #ifdef CONFIG_FORCEDETH_NAPI | |
1774 | static void nv_do_rx_refill(unsigned long data) | |
1775 | { | |
1776 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1777 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1778 | |
1779 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1780 | napi_schedule(&np->napi); |
e27cdba5 SH |
1781 | } |
1782 | #else | |
1da177e4 LT |
1783 | static void nv_do_rx_refill(unsigned long data) |
1784 | { | |
1785 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 1786 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1787 | int retcode; |
1da177e4 | 1788 | |
84b3932b AA |
1789 | if (!using_multi_irqs(dev)) { |
1790 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1791 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1792 | else | |
a7475906 | 1793 | disable_irq(np->pci_dev->irq); |
d33a73c8 AA |
1794 | } else { |
1795 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1796 | } | |
36b30ea9 | 1797 | if (!nv_optimized(np)) |
86b22b0d AA |
1798 | retcode = nv_alloc_rx(dev); |
1799 | else | |
1800 | retcode = nv_alloc_rx_optimized(dev); | |
1801 | if (retcode) { | |
84b3932b | 1802 | spin_lock_irq(&np->lock); |
1da177e4 LT |
1803 | if (!np->in_shutdown) |
1804 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
84b3932b | 1805 | spin_unlock_irq(&np->lock); |
1da177e4 | 1806 | } |
84b3932b AA |
1807 | if (!using_multi_irqs(dev)) { |
1808 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1809 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1810 | else | |
a7475906 | 1811 | enable_irq(np->pci_dev->irq); |
d33a73c8 AA |
1812 | } else { |
1813 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1814 | } | |
1da177e4 | 1815 | } |
e27cdba5 | 1816 | #endif |
1da177e4 | 1817 | |
f3b197ac | 1818 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1819 | { |
ac9c1897 | 1820 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1821 | int i; |
36b30ea9 | 1822 | |
761fcd9e | 1823 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1824 | |
1825 | if (!nv_optimized(np)) | |
761fcd9e AA |
1826 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1827 | else | |
1828 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1829 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1830 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1831 | |
761fcd9e | 1832 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1833 | if (!nv_optimized(np)) { |
f82a9352 | 1834 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1835 | np->rx_ring.orig[i].buf = 0; |
1836 | } else { | |
f82a9352 | 1837 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1838 | np->rx_ring.ex[i].txvlan = 0; |
1839 | np->rx_ring.ex[i].bufhigh = 0; | |
1840 | np->rx_ring.ex[i].buflow = 0; | |
1841 | } | |
1842 | np->rx_skb[i].skb = NULL; | |
1843 | np->rx_skb[i].dma = 0; | |
1844 | } | |
d81c0983 MS |
1845 | } |
1846 | ||
1847 | static void nv_init_tx(struct net_device *dev) | |
1848 | { | |
ac9c1897 | 1849 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1850 | int i; |
36b30ea9 | 1851 | |
761fcd9e | 1852 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1853 | |
1854 | if (!nv_optimized(np)) | |
761fcd9e AA |
1855 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1856 | else | |
1857 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1858 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1859 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
3b446c3e AA |
1860 | np->tx_pkts_in_progress = 0; |
1861 | np->tx_change_owner = NULL; | |
1862 | np->tx_end_flip = NULL; | |
d81c0983 | 1863 | |
eafa59f6 | 1864 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1865 | if (!nv_optimized(np)) { |
f82a9352 | 1866 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1867 | np->tx_ring.orig[i].buf = 0; |
1868 | } else { | |
f82a9352 | 1869 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1870 | np->tx_ring.ex[i].txvlan = 0; |
1871 | np->tx_ring.ex[i].bufhigh = 0; | |
1872 | np->tx_ring.ex[i].buflow = 0; | |
1873 | } | |
1874 | np->tx_skb[i].skb = NULL; | |
1875 | np->tx_skb[i].dma = 0; | |
3b446c3e AA |
1876 | np->tx_skb[i].dma_len = 0; |
1877 | np->tx_skb[i].first_tx_desc = NULL; | |
1878 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1879 | } |
d81c0983 MS |
1880 | } |
1881 | ||
1882 | static int nv_init_ring(struct net_device *dev) | |
1883 | { | |
86b22b0d AA |
1884 | struct fe_priv *np = netdev_priv(dev); |
1885 | ||
d81c0983 MS |
1886 | nv_init_tx(dev); |
1887 | nv_init_rx(dev); | |
36b30ea9 JG |
1888 | |
1889 | if (!nv_optimized(np)) | |
86b22b0d AA |
1890 | return nv_alloc_rx(dev); |
1891 | else | |
1892 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1893 | } |
1894 | ||
761fcd9e | 1895 | static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb) |
ac9c1897 AA |
1896 | { |
1897 | struct fe_priv *np = netdev_priv(dev); | |
fa45459e | 1898 | |
761fcd9e AA |
1899 | if (tx_skb->dma) { |
1900 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1901 | tx_skb->dma_len, | |
fa45459e | 1902 | PCI_DMA_TODEVICE); |
761fcd9e | 1903 | tx_skb->dma = 0; |
fa45459e | 1904 | } |
761fcd9e AA |
1905 | if (tx_skb->skb) { |
1906 | dev_kfree_skb_any(tx_skb->skb); | |
1907 | tx_skb->skb = NULL; | |
fa45459e AA |
1908 | return 1; |
1909 | } else { | |
1910 | return 0; | |
ac9c1897 | 1911 | } |
ac9c1897 AA |
1912 | } |
1913 | ||
1da177e4 LT |
1914 | static void nv_drain_tx(struct net_device *dev) |
1915 | { | |
ac9c1897 AA |
1916 | struct fe_priv *np = netdev_priv(dev); |
1917 | unsigned int i; | |
f3b197ac | 1918 | |
eafa59f6 | 1919 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1920 | if (!nv_optimized(np)) { |
f82a9352 | 1921 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1922 | np->tx_ring.orig[i].buf = 0; |
1923 | } else { | |
f82a9352 | 1924 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1925 | np->tx_ring.ex[i].txvlan = 0; |
1926 | np->tx_ring.ex[i].bufhigh = 0; | |
1927 | np->tx_ring.ex[i].buflow = 0; | |
1928 | } | |
1929 | if (nv_release_txskb(dev, &np->tx_skb[i])) | |
8148ff45 | 1930 | dev->stats.tx_dropped++; |
3b446c3e AA |
1931 | np->tx_skb[i].dma = 0; |
1932 | np->tx_skb[i].dma_len = 0; | |
1933 | np->tx_skb[i].first_tx_desc = NULL; | |
1934 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 1935 | } |
3b446c3e AA |
1936 | np->tx_pkts_in_progress = 0; |
1937 | np->tx_change_owner = NULL; | |
1938 | np->tx_end_flip = NULL; | |
1da177e4 LT |
1939 | } |
1940 | ||
1941 | static void nv_drain_rx(struct net_device *dev) | |
1942 | { | |
ac9c1897 | 1943 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1944 | int i; |
761fcd9e | 1945 | |
eafa59f6 | 1946 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1947 | if (!nv_optimized(np)) { |
f82a9352 | 1948 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1949 | np->rx_ring.orig[i].buf = 0; |
1950 | } else { | |
f82a9352 | 1951 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1952 | np->rx_ring.ex[i].txvlan = 0; |
1953 | np->rx_ring.ex[i].bufhigh = 0; | |
1954 | np->rx_ring.ex[i].buflow = 0; | |
1955 | } | |
1da177e4 | 1956 | wmb(); |
761fcd9e AA |
1957 | if (np->rx_skb[i].skb) { |
1958 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
1959 | (skb_end_pointer(np->rx_skb[i].skb) - |
1960 | np->rx_skb[i].skb->data), | |
1961 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
1962 | dev_kfree_skb(np->rx_skb[i].skb); |
1963 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1964 | } |
1965 | } | |
1966 | } | |
1967 | ||
36b30ea9 | 1968 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
1969 | { |
1970 | nv_drain_tx(dev); | |
1971 | nv_drain_rx(dev); | |
1972 | } | |
1973 | ||
761fcd9e AA |
1974 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1975 | { | |
1976 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1977 | } | |
1978 | ||
a433686c AA |
1979 | static void nv_legacybackoff_reseed(struct net_device *dev) |
1980 | { | |
1981 | u8 __iomem *base = get_hwbase(dev); | |
1982 | u32 reg; | |
1983 | u32 low; | |
1984 | int tx_status = 0; | |
1985 | ||
1986 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
1987 | get_random_bytes(&low, sizeof(low)); | |
1988 | reg |= low & NVREG_SLOTTIME_MASK; | |
1989 | ||
1990 | /* Need to stop tx before change takes effect. | |
1991 | * Caller has already gained np->lock. | |
1992 | */ | |
1993 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
1994 | if (tx_status) | |
1995 | nv_stop_tx(dev); | |
1996 | nv_stop_rx(dev); | |
1997 | writel(reg, base + NvRegSlotTime); | |
1998 | if (tx_status) | |
1999 | nv_start_tx(dev); | |
2000 | nv_start_rx(dev); | |
2001 | } | |
2002 | ||
2003 | /* Gear Backoff Seeds */ | |
2004 | #define BACKOFF_SEEDSET_ROWS 8 | |
2005 | #define BACKOFF_SEEDSET_LFSRS 15 | |
2006 | ||
2007 | /* Known Good seed sets */ | |
2008 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
2009 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2010 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2011 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2012 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2013 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2014 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2015 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2016 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}}; | |
2017 | ||
2018 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
2019 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2020 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2021 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2022 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2023 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2024 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2025 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2026 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}}; | |
2027 | ||
2028 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2029 | { | |
2030 | u8 __iomem *base = get_hwbase(dev); | |
2031 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2032 | u32 temp, seedset, combinedSeed; | |
2033 | int i; | |
2034 | ||
2035 | /* Setup seed for free running LFSR */ | |
2036 | /* We are going to read the time stamp counter 3 times | |
2037 | and swizzle bits around to increase randomness */ | |
2038 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2039 | miniseed1 &= 0x0fff; | |
2040 | if (miniseed1 == 0) | |
2041 | miniseed1 = 0xabc; | |
2042 | ||
2043 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2044 | miniseed2 &= 0x0fff; | |
2045 | if (miniseed2 == 0) | |
2046 | miniseed2 = 0xabc; | |
2047 | miniseed2_reversed = | |
2048 | ((miniseed2 & 0xF00) >> 8) | | |
2049 | (miniseed2 & 0x0F0) | | |
2050 | ((miniseed2 & 0x00F) << 8); | |
2051 | ||
2052 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2053 | miniseed3 &= 0x0fff; | |
2054 | if (miniseed3 == 0) | |
2055 | miniseed3 = 0xabc; | |
2056 | miniseed3_reversed = | |
2057 | ((miniseed3 & 0xF00) >> 8) | | |
2058 | (miniseed3 & 0x0F0) | | |
2059 | ((miniseed3 & 0x00F) << 8); | |
2060 | ||
2061 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2062 | (miniseed2 ^ miniseed3_reversed); | |
2063 | ||
2064 | /* Seeds can not be zero */ | |
2065 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2066 | combinedSeed |= 0x08; | |
2067 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2068 | combinedSeed |= 0x8000; | |
2069 | ||
2070 | /* No need to disable tx here */ | |
2071 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2072 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2073 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
2074 | writel(temp,base + NvRegBackOffControl); | |
2075 | ||
2076 | /* Setup seeds for all gear LFSRs. */ | |
2077 | get_random_bytes(&seedset, sizeof(seedset)); | |
2078 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
2079 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) | |
2080 | { | |
2081 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); | |
2082 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2083 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2084 | writel(temp, base + NvRegBackOffControl); | |
2085 | } | |
2086 | } | |
2087 | ||
1da177e4 LT |
2088 | /* |
2089 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2090 | * Called with netif_tx_lock held. |
1da177e4 LT |
2091 | */ |
2092 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
2093 | { | |
ac9c1897 | 2094 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2095 | u32 tx_flags = 0; |
ac9c1897 AA |
2096 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2097 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2098 | unsigned int i; |
fa45459e AA |
2099 | u32 offset = 0; |
2100 | u32 bcnt; | |
2101 | u32 size = skb->len-skb->data_len; | |
2102 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
761fcd9e | 2103 | u32 empty_slots; |
86b22b0d AA |
2104 | struct ring_desc* put_tx; |
2105 | struct ring_desc* start_tx; | |
2106 | struct ring_desc* prev_tx; | |
761fcd9e | 2107 | struct nv_skb_map* prev_tx_ctx; |
bd6ca637 | 2108 | unsigned long flags; |
fa45459e AA |
2109 | |
2110 | /* add fragments to entries count */ | |
2111 | for (i = 0; i < fragments; i++) { | |
2112 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2113 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2114 | } | |
ac9c1897 | 2115 | |
001eb84b | 2116 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2117 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2118 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2119 | netif_stop_queue(dev); |
aaa37d2d | 2120 | np->tx_stop = 1; |
bd6ca637 | 2121 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2122 | return NETDEV_TX_BUSY; |
2123 | } | |
001eb84b | 2124 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2125 | |
86b22b0d | 2126 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2127 | |
fa45459e AA |
2128 | /* setup the header buffer */ |
2129 | do { | |
761fcd9e AA |
2130 | prev_tx = put_tx; |
2131 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2132 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 2133 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 2134 | PCI_DMA_TODEVICE); |
761fcd9e | 2135 | np->put_tx_ctx->dma_len = bcnt; |
86b22b0d AA |
2136 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2137 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2138 | |
fa45459e AA |
2139 | tx_flags = np->tx_flags; |
2140 | offset += bcnt; | |
2141 | size -= bcnt; | |
445583b8 | 2142 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2143 | put_tx = np->first_tx.orig; |
445583b8 | 2144 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2145 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 2146 | } while (size); |
fa45459e AA |
2147 | |
2148 | /* setup the fragments */ | |
2149 | for (i = 0; i < fragments; i++) { | |
2150 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2151 | u32 size = frag->size; | |
2152 | offset = 0; | |
2153 | ||
2154 | do { | |
761fcd9e AA |
2155 | prev_tx = put_tx; |
2156 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 2157 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
2158 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2159 | PCI_DMA_TODEVICE); | |
2160 | np->put_tx_ctx->dma_len = bcnt; | |
86b22b0d AA |
2161 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2162 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2163 | |
fa45459e AA |
2164 | offset += bcnt; |
2165 | size -= bcnt; | |
445583b8 | 2166 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 2167 | put_tx = np->first_tx.orig; |
445583b8 | 2168 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2169 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
2170 | } while (size); |
2171 | } | |
ac9c1897 | 2172 | |
fa45459e | 2173 | /* set last fragment flag */ |
86b22b0d | 2174 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2175 | |
761fcd9e AA |
2176 | /* save skb in this slot's context area */ |
2177 | prev_tx_ctx->skb = skb; | |
fa45459e | 2178 | |
89114afd | 2179 | if (skb_is_gso(skb)) |
7967168c | 2180 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2181 | else |
1d39ed56 | 2182 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2183 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2184 | |
bd6ca637 | 2185 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2186 | |
fa45459e | 2187 | /* set tx flags */ |
86b22b0d AA |
2188 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2189 | np->put_tx.orig = put_tx; | |
1da177e4 | 2190 | |
bd6ca637 | 2191 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e AA |
2192 | |
2193 | dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n", | |
2194 | dev->name, entries, tx_flags_extra); | |
1da177e4 LT |
2195 | { |
2196 | int j; | |
2197 | for (j=0; j<64; j++) { | |
2198 | if ((j%16) == 0) | |
2199 | dprintk("\n%03x:", j); | |
2200 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2201 | } | |
2202 | dprintk("\n"); | |
2203 | } | |
2204 | ||
1da177e4 | 2205 | dev->trans_start = jiffies; |
8a4ae7f2 | 2206 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2207 | return NETDEV_TX_OK; |
1da177e4 LT |
2208 | } |
2209 | ||
86b22b0d AA |
2210 | static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) |
2211 | { | |
2212 | struct fe_priv *np = netdev_priv(dev); | |
2213 | u32 tx_flags = 0; | |
445583b8 | 2214 | u32 tx_flags_extra; |
86b22b0d AA |
2215 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2216 | unsigned int i; | |
2217 | u32 offset = 0; | |
2218 | u32 bcnt; | |
2219 | u32 size = skb->len-skb->data_len; | |
2220 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2221 | u32 empty_slots; | |
86b22b0d AA |
2222 | struct ring_desc_ex* put_tx; |
2223 | struct ring_desc_ex* start_tx; | |
2224 | struct ring_desc_ex* prev_tx; | |
2225 | struct nv_skb_map* prev_tx_ctx; | |
3b446c3e | 2226 | struct nv_skb_map* start_tx_ctx; |
bd6ca637 | 2227 | unsigned long flags; |
86b22b0d AA |
2228 | |
2229 | /* add fragments to entries count */ | |
2230 | for (i = 0; i < fragments; i++) { | |
2231 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2232 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2233 | } | |
2234 | ||
001eb84b | 2235 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2236 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2237 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2238 | netif_stop_queue(dev); |
aaa37d2d | 2239 | np->tx_stop = 1; |
bd6ca637 | 2240 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2241 | return NETDEV_TX_BUSY; |
2242 | } | |
001eb84b | 2243 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2244 | |
2245 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2246 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2247 | |
2248 | /* setup the header buffer */ | |
2249 | do { | |
2250 | prev_tx = put_tx; | |
2251 | prev_tx_ctx = np->put_tx_ctx; | |
2252 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2253 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2254 | PCI_DMA_TODEVICE); | |
2255 | np->put_tx_ctx->dma_len = bcnt; | |
5bb7ea26 AV |
2256 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2257 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2258 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2259 | |
2260 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2261 | offset += bcnt; |
2262 | size -= bcnt; | |
445583b8 | 2263 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2264 | put_tx = np->first_tx.ex; |
445583b8 | 2265 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2266 | np->put_tx_ctx = np->first_tx_ctx; |
2267 | } while (size); | |
2268 | ||
2269 | /* setup the fragments */ | |
2270 | for (i = 0; i < fragments; i++) { | |
2271 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2272 | u32 size = frag->size; | |
2273 | offset = 0; | |
2274 | ||
2275 | do { | |
2276 | prev_tx = put_tx; | |
2277 | prev_tx_ctx = np->put_tx_ctx; | |
2278 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2279 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
2280 | PCI_DMA_TODEVICE); | |
2281 | np->put_tx_ctx->dma_len = bcnt; | |
5bb7ea26 AV |
2282 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2283 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2284 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2285 | |
86b22b0d AA |
2286 | offset += bcnt; |
2287 | size -= bcnt; | |
445583b8 | 2288 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2289 | put_tx = np->first_tx.ex; |
445583b8 | 2290 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2291 | np->put_tx_ctx = np->first_tx_ctx; |
2292 | } while (size); | |
2293 | } | |
2294 | ||
2295 | /* set last fragment flag */ | |
445583b8 | 2296 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2297 | |
2298 | /* save skb in this slot's context area */ | |
2299 | prev_tx_ctx->skb = skb; | |
2300 | ||
2301 | if (skb_is_gso(skb)) | |
2302 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2303 | else | |
2304 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2305 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2306 | ||
2307 | /* vlan tag */ | |
445583b8 AA |
2308 | if (likely(!np->vlangrp)) { |
2309 | start_tx->txvlan = 0; | |
2310 | } else { | |
2311 | if (vlan_tx_tag_present(skb)) | |
2312 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb)); | |
2313 | else | |
2314 | start_tx->txvlan = 0; | |
86b22b0d AA |
2315 | } |
2316 | ||
bd6ca637 | 2317 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2318 | |
3b446c3e AA |
2319 | if (np->tx_limit) { |
2320 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2321 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2322 | * to that descriptor and also for next skb_map element. | |
2323 | */ | |
2324 | ||
2325 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2326 | if (!np->tx_change_owner) | |
2327 | np->tx_change_owner = start_tx_ctx; | |
2328 | ||
2329 | /* remove VALID bit */ | |
2330 | tx_flags &= ~NV_TX2_VALID; | |
2331 | start_tx_ctx->first_tx_desc = start_tx; | |
2332 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2333 | np->tx_end_flip = np->put_tx_ctx; | |
2334 | } else { | |
2335 | np->tx_pkts_in_progress++; | |
2336 | } | |
2337 | } | |
2338 | ||
86b22b0d | 2339 | /* set tx flags */ |
86b22b0d AA |
2340 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2341 | np->put_tx.ex = put_tx; | |
2342 | ||
bd6ca637 | 2343 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2344 | |
2345 | dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n", | |
2346 | dev->name, entries, tx_flags_extra); | |
2347 | { | |
2348 | int j; | |
2349 | for (j=0; j<64; j++) { | |
2350 | if ((j%16) == 0) | |
2351 | dprintk("\n%03x:", j); | |
2352 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2353 | } | |
2354 | dprintk("\n"); | |
2355 | } | |
2356 | ||
2357 | dev->trans_start = jiffies; | |
2358 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
86b22b0d AA |
2359 | return NETDEV_TX_OK; |
2360 | } | |
2361 | ||
3b446c3e AA |
2362 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2363 | { | |
2364 | struct fe_priv *np = netdev_priv(dev); | |
2365 | ||
2366 | np->tx_pkts_in_progress--; | |
2367 | if (np->tx_change_owner) { | |
30ecce90 AV |
2368 | np->tx_change_owner->first_tx_desc->flaglen |= |
2369 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2370 | np->tx_pkts_in_progress++; |
2371 | ||
2372 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2373 | if (np->tx_change_owner == np->tx_end_flip) | |
2374 | np->tx_change_owner = NULL; | |
2375 | ||
2376 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2377 | } | |
2378 | } | |
2379 | ||
1da177e4 LT |
2380 | /* |
2381 | * nv_tx_done: check for completed packets, release the skbs. | |
2382 | * | |
2383 | * Caller must own np->lock. | |
2384 | */ | |
2385 | static void nv_tx_done(struct net_device *dev) | |
2386 | { | |
ac9c1897 | 2387 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2388 | u32 flags; |
aaa37d2d | 2389 | struct ring_desc* orig_get_tx = np->get_tx.orig; |
1da177e4 | 2390 | |
445583b8 AA |
2391 | while ((np->get_tx.orig != np->put_tx.orig) && |
2392 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) { | |
1da177e4 | 2393 | |
761fcd9e AA |
2394 | dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n", |
2395 | dev->name, flags); | |
445583b8 AA |
2396 | |
2397 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
2398 | np->get_tx_ctx->dma_len, | |
2399 | PCI_DMA_TODEVICE); | |
2400 | np->get_tx_ctx->dma = 0; | |
2401 | ||
1da177e4 | 2402 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2403 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2404 | if (flags & NV_TX_ERROR) { |
f82a9352 | 2405 | if (flags & NV_TX_UNDERFLOW) |
8148ff45 | 2406 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2407 | if (flags & NV_TX_CARRIERLOST) |
8148ff45 | 2408 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2409 | if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK)) |
2410 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2411 | dev->stats.tx_errors++; |
ac9c1897 | 2412 | } else { |
8148ff45 JG |
2413 | dev->stats.tx_packets++; |
2414 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
ac9c1897 | 2415 | } |
445583b8 AA |
2416 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2417 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
2418 | } |
2419 | } else { | |
f82a9352 | 2420 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2421 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 2422 | if (flags & NV_TX2_UNDERFLOW) |
8148ff45 | 2423 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2424 | if (flags & NV_TX2_CARRIERLOST) |
8148ff45 | 2425 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2426 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) |
2427 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2428 | dev->stats.tx_errors++; |
ac9c1897 | 2429 | } else { |
8148ff45 JG |
2430 | dev->stats.tx_packets++; |
2431 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
f3b197ac | 2432 | } |
445583b8 AA |
2433 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2434 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
2435 | } |
2436 | } | |
445583b8 | 2437 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2438 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2439 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2440 | np->get_tx_ctx = np->first_tx_ctx; |
2441 | } | |
445583b8 | 2442 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2443 | np->tx_stop = 0; |
86b22b0d | 2444 | netif_wake_queue(dev); |
aaa37d2d | 2445 | } |
86b22b0d AA |
2446 | } |
2447 | ||
4e16ed1b | 2448 | static void nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2449 | { |
2450 | struct fe_priv *np = netdev_priv(dev); | |
2451 | u32 flags; | |
aaa37d2d | 2452 | struct ring_desc_ex* orig_get_tx = np->get_tx.ex; |
86b22b0d | 2453 | |
445583b8 | 2454 | while ((np->get_tx.ex != np->put_tx.ex) && |
4e16ed1b AA |
2455 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) && |
2456 | (limit-- > 0)) { | |
86b22b0d AA |
2457 | |
2458 | dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n", | |
2459 | dev->name, flags); | |
445583b8 AA |
2460 | |
2461 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
2462 | np->get_tx_ctx->dma_len, | |
2463 | PCI_DMA_TODEVICE); | |
2464 | np->get_tx_ctx->dma = 0; | |
2465 | ||
86b22b0d | 2466 | if (flags & NV_TX2_LASTPACKET) { |
21828163 | 2467 | if (!(flags & NV_TX2_ERROR)) |
8148ff45 | 2468 | dev->stats.tx_packets++; |
a433686c AA |
2469 | else { |
2470 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
2471 | if (np->driver_data & DEV_HAS_GEAR_MODE) | |
2472 | nv_gear_backoff_reseed(dev); | |
2473 | else | |
2474 | nv_legacybackoff_reseed(dev); | |
2475 | } | |
2476 | } | |
2477 | ||
445583b8 AA |
2478 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2479 | np->get_tx_ctx->skb = NULL; | |
3b446c3e AA |
2480 | |
2481 | if (np->tx_limit) { | |
2482 | nv_tx_flip_ownership(dev); | |
2483 | } | |
761fcd9e | 2484 | } |
445583b8 | 2485 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2486 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2487 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2488 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2489 | } |
445583b8 | 2490 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2491 | np->tx_stop = 0; |
1da177e4 | 2492 | netif_wake_queue(dev); |
aaa37d2d | 2493 | } |
1da177e4 LT |
2494 | } |
2495 | ||
2496 | /* | |
2497 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2498 | * Called with netif_tx_lock held. |
1da177e4 LT |
2499 | */ |
2500 | static void nv_tx_timeout(struct net_device *dev) | |
2501 | { | |
ac9c1897 | 2502 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2503 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
2504 | u32 status; |
2505 | ||
2506 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2507 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2508 | else | |
2509 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2510 | |
d33a73c8 | 2511 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
1da177e4 | 2512 | |
c2dba06d MS |
2513 | { |
2514 | int i; | |
2515 | ||
761fcd9e AA |
2516 | printk(KERN_INFO "%s: Ring at %lx\n", |
2517 | dev->name, (unsigned long)np->ring_addr); | |
c2dba06d | 2518 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
86a0f043 | 2519 | for (i=0;i<=np->register_size;i+= 32) { |
c2dba06d MS |
2520 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2521 | i, | |
2522 | readl(base + i + 0), readl(base + i + 4), | |
2523 | readl(base + i + 8), readl(base + i + 12), | |
2524 | readl(base + i + 16), readl(base + i + 20), | |
2525 | readl(base + i + 24), readl(base + i + 28)); | |
2526 | } | |
2527 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | |
eafa59f6 | 2528 | for (i=0;i<np->tx_ring_size;i+= 4) { |
36b30ea9 | 2529 | if (!nv_optimized(np)) { |
ee73362c | 2530 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
f3b197ac | 2531 | i, |
f82a9352 SH |
2532 | le32_to_cpu(np->tx_ring.orig[i].buf), |
2533 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2534 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2535 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2536 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2537 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2538 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2539 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
ee73362c MS |
2540 | } else { |
2541 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
f3b197ac | 2542 | i, |
f82a9352 SH |
2543 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
2544 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2545 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2546 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2547 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2548 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2549 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2550 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2551 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2552 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2553 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2554 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
ee73362c | 2555 | } |
c2dba06d MS |
2556 | } |
2557 | } | |
2558 | ||
1da177e4 LT |
2559 | spin_lock_irq(&np->lock); |
2560 | ||
2561 | /* 1) stop tx engine */ | |
2562 | nv_stop_tx(dev); | |
2563 | ||
2564 | /* 2) check that the packets were not sent already: */ | |
36b30ea9 | 2565 | if (!nv_optimized(np)) |
86b22b0d AA |
2566 | nv_tx_done(dev); |
2567 | else | |
4e16ed1b | 2568 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 LT |
2569 | |
2570 | /* 3) if there are dead entries: clear everything */ | |
761fcd9e | 2571 | if (np->get_tx_ctx != np->put_tx_ctx) { |
1da177e4 LT |
2572 | printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
2573 | nv_drain_tx(dev); | |
761fcd9e | 2574 | nv_init_tx(dev); |
0832b25a | 2575 | setup_hw_rings(dev, NV_SETUP_TX_RING); |
1da177e4 LT |
2576 | } |
2577 | ||
3ba4d093 AA |
2578 | netif_wake_queue(dev); |
2579 | ||
1da177e4 LT |
2580 | /* 4) restart tx engine */ |
2581 | nv_start_tx(dev); | |
2582 | spin_unlock_irq(&np->lock); | |
2583 | } | |
2584 | ||
22c6d143 MS |
2585 | /* |
2586 | * Called when the nic notices a mismatch between the actual data len on the | |
2587 | * wire and the len indicated in the 802 header | |
2588 | */ | |
2589 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2590 | { | |
2591 | int hdrlen; /* length of the 802 header */ | |
2592 | int protolen; /* length as stored in the proto field */ | |
2593 | ||
2594 | /* 1) calculate len according to header */ | |
f82a9352 | 2595 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
22c6d143 MS |
2596 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
2597 | hdrlen = VLAN_HLEN; | |
2598 | } else { | |
2599 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | |
2600 | hdrlen = ETH_HLEN; | |
2601 | } | |
2602 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | |
2603 | dev->name, datalen, protolen, hdrlen); | |
2604 | if (protolen > ETH_DATA_LEN) | |
2605 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2606 | ||
2607 | protolen += hdrlen; | |
2608 | /* consistency checks: */ | |
2609 | if (datalen > ETH_ZLEN) { | |
2610 | if (datalen >= protolen) { | |
2611 | /* more data on wire than in 802 header, trim of | |
2612 | * additional data. | |
2613 | */ | |
2614 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2615 | dev->name, protolen); | |
2616 | return protolen; | |
2617 | } else { | |
2618 | /* less data on wire than mentioned in header. | |
2619 | * Discard the packet. | |
2620 | */ | |
2621 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | |
2622 | dev->name); | |
2623 | return -1; | |
2624 | } | |
2625 | } else { | |
2626 | /* short packet. Accept only if 802 values are also short */ | |
2627 | if (protolen > ETH_ZLEN) { | |
2628 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | |
2629 | dev->name); | |
2630 | return -1; | |
2631 | } | |
2632 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2633 | dev->name, datalen); | |
2634 | return datalen; | |
2635 | } | |
2636 | } | |
2637 | ||
e27cdba5 | 2638 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2639 | { |
ac9c1897 | 2640 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2641 | u32 flags; |
bcb5febb | 2642 | int rx_work = 0; |
b01867cb AA |
2643 | struct sk_buff *skb; |
2644 | int len; | |
1da177e4 | 2645 | |
b01867cb AA |
2646 | while((np->get_rx.orig != np->put_rx.orig) && |
2647 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && | |
bcb5febb | 2648 | (rx_work < limit)) { |
1da177e4 | 2649 | |
761fcd9e AA |
2650 | dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n", |
2651 | dev->name, flags); | |
1da177e4 | 2652 | |
1da177e4 LT |
2653 | /* |
2654 | * the packet is for us - immediately tear down the pci mapping. | |
2655 | * TODO: check if a prefetch of the first cacheline improves | |
2656 | * the performance. | |
2657 | */ | |
761fcd9e AA |
2658 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2659 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2660 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2661 | skb = np->get_rx_ctx->skb; |
2662 | np->get_rx_ctx->skb = NULL; | |
1da177e4 LT |
2663 | |
2664 | { | |
2665 | int j; | |
f82a9352 | 2666 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); |
1da177e4 LT |
2667 | for (j=0; j<64; j++) { |
2668 | if ((j%16) == 0) | |
2669 | dprintk("\n%03x:", j); | |
0d63fb32 | 2670 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
1da177e4 LT |
2671 | } |
2672 | dprintk("\n"); | |
2673 | } | |
2674 | /* look at what we actually got: */ | |
2675 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2676 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2677 | len = flags & LEN_MASK_V1; | |
2678 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2679 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2680 | len = nv_getlen(dev, skb->data, len); |
2681 | if (len < 0) { | |
8148ff45 | 2682 | dev->stats.rx_errors++; |
b01867cb AA |
2683 | dev_kfree_skb(skb); |
2684 | goto next_pkt; | |
2685 | } | |
2686 | } | |
2687 | /* framing errors are soft errors */ | |
1ef6841b | 2688 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
b01867cb AA |
2689 | if (flags & NV_RX_SUBSTRACT1) { |
2690 | len--; | |
2691 | } | |
2692 | } | |
2693 | /* the rest are hard errors */ | |
2694 | else { | |
2695 | if (flags & NV_RX_MISSEDFRAME) | |
8148ff45 | 2696 | dev->stats.rx_missed_errors++; |
b01867cb | 2697 | if (flags & NV_RX_CRCERR) |
8148ff45 | 2698 | dev->stats.rx_crc_errors++; |
b01867cb | 2699 | if (flags & NV_RX_OVERFLOW) |
8148ff45 JG |
2700 | dev->stats.rx_over_errors++; |
2701 | dev->stats.rx_errors++; | |
0d63fb32 | 2702 | dev_kfree_skb(skb); |
a971c324 AA |
2703 | goto next_pkt; |
2704 | } | |
2705 | } | |
b01867cb | 2706 | } else { |
0d63fb32 | 2707 | dev_kfree_skb(skb); |
1da177e4 | 2708 | goto next_pkt; |
0d63fb32 | 2709 | } |
b01867cb AA |
2710 | } else { |
2711 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2712 | len = flags & LEN_MASK_V2; | |
2713 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2714 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2715 | len = nv_getlen(dev, skb->data, len); |
2716 | if (len < 0) { | |
8148ff45 | 2717 | dev->stats.rx_errors++; |
b01867cb AA |
2718 | dev_kfree_skb(skb); |
2719 | goto next_pkt; | |
2720 | } | |
2721 | } | |
2722 | /* framing errors are soft errors */ | |
1ef6841b | 2723 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
b01867cb AA |
2724 | if (flags & NV_RX2_SUBSTRACT1) { |
2725 | len--; | |
2726 | } | |
2727 | } | |
2728 | /* the rest are hard errors */ | |
2729 | else { | |
2730 | if (flags & NV_RX2_CRCERR) | |
8148ff45 | 2731 | dev->stats.rx_crc_errors++; |
b01867cb | 2732 | if (flags & NV_RX2_OVERFLOW) |
8148ff45 JG |
2733 | dev->stats.rx_over_errors++; |
2734 | dev->stats.rx_errors++; | |
0d63fb32 | 2735 | dev_kfree_skb(skb); |
a971c324 AA |
2736 | goto next_pkt; |
2737 | } | |
2738 | } | |
bfaffe8f AA |
2739 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2740 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2741 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2742 | } else { |
2743 | dev_kfree_skb(skb); | |
2744 | goto next_pkt; | |
1da177e4 LT |
2745 | } |
2746 | } | |
2747 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2748 | skb_put(skb, len); |
2749 | skb->protocol = eth_type_trans(skb, dev); | |
761fcd9e AA |
2750 | dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n", |
2751 | dev->name, len, skb->protocol); | |
e27cdba5 | 2752 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2753 | netif_receive_skb(skb); |
e27cdba5 | 2754 | #else |
b01867cb | 2755 | netif_rx(skb); |
e27cdba5 | 2756 | #endif |
8148ff45 JG |
2757 | dev->stats.rx_packets++; |
2758 | dev->stats.rx_bytes += len; | |
1da177e4 | 2759 | next_pkt: |
b01867cb | 2760 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2761 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2762 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2763 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2764 | |
2765 | rx_work++; | |
86b22b0d AA |
2766 | } |
2767 | ||
bcb5febb | 2768 | return rx_work; |
86b22b0d AA |
2769 | } |
2770 | ||
2771 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2772 | { | |
2773 | struct fe_priv *np = netdev_priv(dev); | |
2774 | u32 flags; | |
2775 | u32 vlanflags = 0; | |
c1b7151a | 2776 | int rx_work = 0; |
b01867cb AA |
2777 | struct sk_buff *skb; |
2778 | int len; | |
86b22b0d | 2779 | |
b01867cb AA |
2780 | while((np->get_rx.ex != np->put_rx.ex) && |
2781 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && | |
c1b7151a | 2782 | (rx_work < limit)) { |
86b22b0d AA |
2783 | |
2784 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n", | |
2785 | dev->name, flags); | |
2786 | ||
86b22b0d AA |
2787 | /* |
2788 | * the packet is for us - immediately tear down the pci mapping. | |
2789 | * TODO: check if a prefetch of the first cacheline improves | |
2790 | * the performance. | |
2791 | */ | |
2792 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2793 | np->get_rx_ctx->dma_len, | |
2794 | PCI_DMA_FROMDEVICE); | |
2795 | skb = np->get_rx_ctx->skb; | |
2796 | np->get_rx_ctx->skb = NULL; | |
2797 | ||
2798 | { | |
2799 | int j; | |
2800 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); | |
2801 | for (j=0; j<64; j++) { | |
2802 | if ((j%16) == 0) | |
2803 | dprintk("\n%03x:", j); | |
2804 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2805 | } | |
2806 | dprintk("\n"); | |
761fcd9e | 2807 | } |
86b22b0d | 2808 | /* look at what we actually got: */ |
b01867cb AA |
2809 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2810 | len = flags & LEN_MASK_V2; | |
2811 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2812 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2813 | len = nv_getlen(dev, skb->data, len); |
2814 | if (len < 0) { | |
b01867cb AA |
2815 | dev_kfree_skb(skb); |
2816 | goto next_pkt; | |
2817 | } | |
2818 | } | |
2819 | /* framing errors are soft errors */ | |
1ef6841b | 2820 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
b01867cb AA |
2821 | if (flags & NV_RX2_SUBSTRACT1) { |
2822 | len--; | |
2823 | } | |
2824 | } | |
2825 | /* the rest are hard errors */ | |
2826 | else { | |
86b22b0d AA |
2827 | dev_kfree_skb(skb); |
2828 | goto next_pkt; | |
2829 | } | |
2830 | } | |
b01867cb | 2831 | |
bfaffe8f AA |
2832 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2833 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2834 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2835 | |
2836 | /* got a valid packet - forward it to the network core */ | |
2837 | skb_put(skb, len); | |
2838 | skb->protocol = eth_type_trans(skb, dev); | |
2839 | prefetch(skb->data); | |
2840 | ||
2841 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n", | |
2842 | dev->name, len, skb->protocol); | |
2843 | ||
2844 | if (likely(!np->vlangrp)) { | |
86b22b0d | 2845 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2846 | netif_receive_skb(skb); |
86b22b0d | 2847 | #else |
b01867cb | 2848 | netif_rx(skb); |
86b22b0d | 2849 | #endif |
b01867cb AA |
2850 | } else { |
2851 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2852 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
2853 | #ifdef CONFIG_FORCEDETH_NAPI | |
2854 | vlan_hwaccel_receive_skb(skb, np->vlangrp, | |
2855 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2856 | #else | |
2857 | vlan_hwaccel_rx(skb, np->vlangrp, | |
2858 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2859 | #endif | |
2860 | } else { | |
2861 | #ifdef CONFIG_FORCEDETH_NAPI | |
2862 | netif_receive_skb(skb); | |
2863 | #else | |
2864 | netif_rx(skb); | |
2865 | #endif | |
2866 | } | |
2867 | } | |
2868 | ||
8148ff45 JG |
2869 | dev->stats.rx_packets++; |
2870 | dev->stats.rx_bytes += len; | |
b01867cb AA |
2871 | } else { |
2872 | dev_kfree_skb(skb); | |
2873 | } | |
86b22b0d | 2874 | next_pkt: |
b01867cb | 2875 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2876 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2877 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2878 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2879 | |
2880 | rx_work++; | |
1da177e4 | 2881 | } |
e27cdba5 | 2882 | |
c1b7151a | 2883 | return rx_work; |
1da177e4 LT |
2884 | } |
2885 | ||
d81c0983 MS |
2886 | static void set_bufsize(struct net_device *dev) |
2887 | { | |
2888 | struct fe_priv *np = netdev_priv(dev); | |
2889 | ||
2890 | if (dev->mtu <= ETH_DATA_LEN) | |
2891 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2892 | else | |
2893 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2894 | } | |
2895 | ||
1da177e4 LT |
2896 | /* |
2897 | * nv_change_mtu: dev->change_mtu function | |
2898 | * Called with dev_base_lock held for read. | |
2899 | */ | |
2900 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2901 | { | |
ac9c1897 | 2902 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2903 | int old_mtu; |
2904 | ||
2905 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2906 | return -EINVAL; |
d81c0983 MS |
2907 | |
2908 | old_mtu = dev->mtu; | |
1da177e4 | 2909 | dev->mtu = new_mtu; |
d81c0983 MS |
2910 | |
2911 | /* return early if the buffer sizes will not change */ | |
2912 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2913 | return 0; | |
2914 | if (old_mtu == new_mtu) | |
2915 | return 0; | |
2916 | ||
2917 | /* synchronized against open : rtnl_lock() held by caller */ | |
2918 | if (netif_running(dev)) { | |
25097d4b | 2919 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2920 | /* |
2921 | * It seems that the nic preloads valid ring entries into an | |
2922 | * internal buffer. The procedure for flushing everything is | |
2923 | * guessed, there is probably a simpler approach. | |
2924 | * Changing the MTU is a rare event, it shouldn't matter. | |
2925 | */ | |
84b3932b | 2926 | nv_disable_irq(dev); |
932ff279 | 2927 | netif_tx_lock_bh(dev); |
e308a5d8 | 2928 | netif_addr_lock(dev); |
d81c0983 MS |
2929 | spin_lock(&np->lock); |
2930 | /* stop engines */ | |
36b30ea9 | 2931 | nv_stop_rxtx(dev); |
d81c0983 MS |
2932 | nv_txrx_reset(dev); |
2933 | /* drain rx queue */ | |
36b30ea9 | 2934 | nv_drain_rxtx(dev); |
d81c0983 | 2935 | /* reinit driver view of the rx queue */ |
d81c0983 | 2936 | set_bufsize(dev); |
eafa59f6 | 2937 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2938 | if (!np->in_shutdown) |
2939 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2940 | } | |
2941 | /* reinit nic view of the rx queue */ | |
2942 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2943 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 2944 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2945 | base + NvRegRingSizes); |
2946 | pci_push(base); | |
8a4ae7f2 | 2947 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2948 | pci_push(base); |
2949 | ||
2950 | /* restart rx engine */ | |
36b30ea9 | 2951 | nv_start_rxtx(dev); |
d81c0983 | 2952 | spin_unlock(&np->lock); |
e308a5d8 | 2953 | netif_addr_unlock(dev); |
932ff279 | 2954 | netif_tx_unlock_bh(dev); |
84b3932b | 2955 | nv_enable_irq(dev); |
d81c0983 | 2956 | } |
1da177e4 LT |
2957 | return 0; |
2958 | } | |
2959 | ||
72b31782 MS |
2960 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2961 | { | |
25097d4b | 2962 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2963 | u32 mac[2]; |
2964 | ||
2965 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2966 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2967 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2968 | ||
2969 | writel(mac[0], base + NvRegMacAddrA); | |
2970 | writel(mac[1], base + NvRegMacAddrB); | |
2971 | } | |
2972 | ||
2973 | /* | |
2974 | * nv_set_mac_address: dev->set_mac_address function | |
2975 | * Called with rtnl_lock() held. | |
2976 | */ | |
2977 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2978 | { | |
ac9c1897 | 2979 | struct fe_priv *np = netdev_priv(dev); |
72b31782 MS |
2980 | struct sockaddr *macaddr = (struct sockaddr*)addr; |
2981 | ||
f82a9352 | 2982 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2983 | return -EADDRNOTAVAIL; |
2984 | ||
2985 | /* synchronized against open : rtnl_lock() held by caller */ | |
2986 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2987 | ||
2988 | if (netif_running(dev)) { | |
932ff279 | 2989 | netif_tx_lock_bh(dev); |
e308a5d8 | 2990 | netif_addr_lock(dev); |
72b31782 MS |
2991 | spin_lock_irq(&np->lock); |
2992 | ||
2993 | /* stop rx engine */ | |
2994 | nv_stop_rx(dev); | |
2995 | ||
2996 | /* set mac address */ | |
2997 | nv_copy_mac_to_hw(dev); | |
2998 | ||
2999 | /* restart rx engine */ | |
3000 | nv_start_rx(dev); | |
3001 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 3002 | netif_addr_unlock(dev); |
932ff279 | 3003 | netif_tx_unlock_bh(dev); |
72b31782 MS |
3004 | } else { |
3005 | nv_copy_mac_to_hw(dev); | |
3006 | } | |
3007 | return 0; | |
3008 | } | |
3009 | ||
1da177e4 LT |
3010 | /* |
3011 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 3012 | * Called with netif_tx_lock held. |
1da177e4 LT |
3013 | */ |
3014 | static void nv_set_multicast(struct net_device *dev) | |
3015 | { | |
ac9c1897 | 3016 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3017 | u8 __iomem *base = get_hwbase(dev); |
3018 | u32 addr[2]; | |
3019 | u32 mask[2]; | |
b6d0773f | 3020 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
3021 | |
3022 | memset(addr, 0, sizeof(addr)); | |
3023 | memset(mask, 0, sizeof(mask)); | |
3024 | ||
3025 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 3026 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 3027 | } else { |
b6d0773f | 3028 | pff |= NVREG_PFF_MYADDR; |
1da177e4 LT |
3029 | |
3030 | if (dev->flags & IFF_ALLMULTI || dev->mc_list) { | |
3031 | u32 alwaysOff[2]; | |
3032 | u32 alwaysOn[2]; | |
3033 | ||
3034 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
3035 | if (dev->flags & IFF_ALLMULTI) { | |
3036 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
3037 | } else { | |
3038 | struct dev_mc_list *walk; | |
3039 | ||
3040 | walk = dev->mc_list; | |
3041 | while (walk != NULL) { | |
3042 | u32 a, b; | |
5bb7ea26 AV |
3043 | a = le32_to_cpu(*(__le32 *) walk->dmi_addr); |
3044 | b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4])); | |
1da177e4 LT |
3045 | alwaysOn[0] &= a; |
3046 | alwaysOff[0] &= ~a; | |
3047 | alwaysOn[1] &= b; | |
3048 | alwaysOff[1] &= ~b; | |
3049 | walk = walk->next; | |
3050 | } | |
3051 | } | |
3052 | addr[0] = alwaysOn[0]; | |
3053 | addr[1] = alwaysOn[1]; | |
3054 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
3055 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
3056 | } else { |
3057 | mask[0] = NVREG_MCASTMASKA_NONE; | |
3058 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
3059 | } |
3060 | } | |
3061 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
3062 | pff |= NVREG_PFF_ALWAYS; | |
3063 | spin_lock_irq(&np->lock); | |
3064 | nv_stop_rx(dev); | |
3065 | writel(addr[0], base + NvRegMulticastAddrA); | |
3066 | writel(addr[1], base + NvRegMulticastAddrB); | |
3067 | writel(mask[0], base + NvRegMulticastMaskA); | |
3068 | writel(mask[1], base + NvRegMulticastMaskB); | |
3069 | writel(pff, base + NvRegPacketFilterFlags); | |
3070 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | |
3071 | dev->name); | |
3072 | nv_start_rx(dev); | |
3073 | spin_unlock_irq(&np->lock); | |
3074 | } | |
3075 | ||
c7985051 | 3076 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
3077 | { |
3078 | struct fe_priv *np = netdev_priv(dev); | |
3079 | u8 __iomem *base = get_hwbase(dev); | |
3080 | ||
3081 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
3082 | ||
3083 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
3084 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
3085 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
3086 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
3087 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3088 | } else { | |
3089 | writel(pff, base + NvRegPacketFilterFlags); | |
3090 | } | |
3091 | } | |
3092 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3093 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3094 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3095 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3096 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3097 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3098 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3099 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3100 | /* limit the number of tx pause frames to a default of 8 */ |
3101 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3102 | } | |
5289b4c4 | 3103 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3104 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3105 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3106 | } else { | |
3107 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3108 | writel(regmisc, base + NvRegMisc1); | |
3109 | } | |
3110 | } | |
3111 | } | |
3112 | ||
4ea7f299 AA |
3113 | /** |
3114 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
3115 | * @dev: Network device to be configured | |
3116 | * | |
3117 | * The function queries the PHY and checks if there is a link partner. | |
3118 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3119 | * set to 10 MBit HD. | |
3120 | * | |
3121 | * The function returns 0 if there is no link partner and 1 if there is | |
3122 | * a good link partner. | |
3123 | */ | |
1da177e4 LT |
3124 | static int nv_update_linkspeed(struct net_device *dev) |
3125 | { | |
ac9c1897 | 3126 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3127 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3128 | int adv = 0; |
3129 | int lpa = 0; | |
3130 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3131 | int newls = np->linkspeed; |
3132 | int newdup = np->duplex; | |
3133 | int mii_status; | |
3134 | int retval = 0; | |
9744e218 | 3135 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3136 | u32 txrxFlags = 0; |
fd9b558c | 3137 | u32 phy_exp; |
1da177e4 LT |
3138 | |
3139 | /* BMSR_LSTATUS is latched, read it twice: | |
3140 | * we want the current value. | |
3141 | */ | |
3142 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3143 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3144 | ||
3145 | if (!(mii_status & BMSR_LSTATUS)) { | |
3146 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | |
3147 | dev->name); | |
3148 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3149 | newdup = 0; | |
3150 | retval = 0; | |
3151 | goto set_speed; | |
3152 | } | |
3153 | ||
3154 | if (np->autoneg == 0) { | |
3155 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | |
3156 | dev->name, np->fixed_mode); | |
3157 | if (np->fixed_mode & LPA_100FULL) { | |
3158 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3159 | newdup = 1; | |
3160 | } else if (np->fixed_mode & LPA_100HALF) { | |
3161 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3162 | newdup = 0; | |
3163 | } else if (np->fixed_mode & LPA_10FULL) { | |
3164 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3165 | newdup = 1; | |
3166 | } else { | |
3167 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3168 | newdup = 0; | |
3169 | } | |
3170 | retval = 1; | |
3171 | goto set_speed; | |
3172 | } | |
3173 | /* check auto negotiation is complete */ | |
3174 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3175 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3176 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3177 | newdup = 0; | |
3178 | retval = 0; | |
3179 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | |
3180 | goto set_speed; | |
3181 | } | |
3182 | ||
b6d0773f AA |
3183 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3184 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
3185 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | |
3186 | dev->name, adv, lpa); | |
3187 | ||
1da177e4 LT |
3188 | retval = 1; |
3189 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3190 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3191 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3192 | |
3193 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3194 | (status_1000 & LPA_1000FULL)) { | |
3195 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | |
3196 | dev->name); | |
3197 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | |
3198 | newdup = 1; | |
3199 | goto set_speed; | |
3200 | } | |
3201 | } | |
3202 | ||
1da177e4 | 3203 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3204 | adv_lpa = lpa & adv; |
3205 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3206 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3207 | newdup = 1; | |
eb91f61b | 3208 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3209 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3210 | newdup = 0; | |
eb91f61b | 3211 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3212 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3213 | newdup = 1; | |
eb91f61b | 3214 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3215 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3216 | newdup = 0; | |
3217 | } else { | |
eb91f61b | 3218 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); |
1da177e4 LT |
3219 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3220 | newdup = 0; | |
3221 | } | |
3222 | ||
3223 | set_speed: | |
3224 | if (np->duplex == newdup && np->linkspeed == newls) | |
3225 | return retval; | |
3226 | ||
3227 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | |
3228 | dev->name, np->linkspeed, np->duplex, newls, newdup); | |
3229 | ||
3230 | np->duplex = newdup; | |
3231 | np->linkspeed = newls; | |
3232 | ||
b2976d23 AA |
3233 | /* The transmitter and receiver must be restarted for safe update */ |
3234 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3235 | txrxFlags |= NV_RESTART_TX; | |
3236 | nv_stop_tx(dev); | |
3237 | } | |
3238 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3239 | txrxFlags |= NV_RESTART_RX; | |
3240 | nv_stop_rx(dev); | |
3241 | } | |
3242 | ||
1da177e4 | 3243 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3244 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3245 | phyreg &= ~(0x3FF00); |
a433686c AA |
3246 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3247 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3248 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3249 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3250 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3251 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3252 | } |
3253 | ||
3254 | phyreg = readl(base + NvRegPhyInterface); | |
3255 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3256 | if (np->duplex == 0) | |
3257 | phyreg |= PHY_HALF; | |
3258 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3259 | phyreg |= PHY_100; | |
3260 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3261 | phyreg |= PHY_1000; | |
3262 | writel(phyreg, base + NvRegPhyInterface); | |
3263 | ||
fd9b558c | 3264 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3265 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3266 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3267 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3268 | } else { |
3269 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3270 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3271 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3272 | else | |
3273 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3274 | } else { | |
3275 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3276 | } | |
3277 | } | |
9744e218 | 3278 | } else { |
fd9b558c AA |
3279 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3280 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3281 | else | |
3282 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3283 | } |
3284 | writel(txreg, base + NvRegTxDeferral); | |
3285 | ||
95d161cb AA |
3286 | if (np->desc_ver == DESC_VER_1) { |
3287 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3288 | } else { | |
3289 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3290 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3291 | else | |
3292 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3293 | } | |
3294 | writel(txreg, base + NvRegTxWatermark); | |
3295 | ||
1da177e4 LT |
3296 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
3297 | base + NvRegMisc1); | |
3298 | pci_push(base); | |
3299 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3300 | pci_push(base); | |
3301 | ||
b6d0773f AA |
3302 | pause_flags = 0; |
3303 | /* setup pause frame */ | |
eb91f61b | 3304 | if (np->duplex != 0) { |
b6d0773f AA |
3305 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
3306 | adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); | |
3307 | lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); | |
3308 | ||
3309 | switch (adv_pause) { | |
f82a9352 | 3310 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3311 | if (lpa_pause & LPA_PAUSE_CAP) { |
3312 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3313 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3314 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3315 | } | |
3316 | break; | |
f82a9352 | 3317 | case ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
3318 | if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) |
3319 | { | |
3320 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3321 | } | |
3322 | break; | |
f82a9352 | 3323 | case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
3324 | if (lpa_pause & LPA_PAUSE_CAP) |
3325 | { | |
3326 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3327 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3328 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3329 | } | |
3330 | if (lpa_pause == LPA_PAUSE_ASYM) | |
3331 | { | |
3332 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3333 | } | |
3334 | break; | |
f3b197ac | 3335 | } |
eb91f61b | 3336 | } else { |
b6d0773f | 3337 | pause_flags = np->pause_flags; |
eb91f61b AA |
3338 | } |
3339 | } | |
b6d0773f | 3340 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3341 | |
b2976d23 AA |
3342 | if (txrxFlags & NV_RESTART_TX) |
3343 | nv_start_tx(dev); | |
3344 | if (txrxFlags & NV_RESTART_RX) | |
3345 | nv_start_rx(dev); | |
3346 | ||
1da177e4 LT |
3347 | return retval; |
3348 | } | |
3349 | ||
3350 | static void nv_linkchange(struct net_device *dev) | |
3351 | { | |
3352 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3353 | if (!netif_carrier_ok(dev)) { |
1da177e4 LT |
3354 | netif_carrier_on(dev); |
3355 | printk(KERN_INFO "%s: link up.\n", dev->name); | |
4ea7f299 | 3356 | nv_start_rx(dev); |
1da177e4 | 3357 | } |
1da177e4 LT |
3358 | } else { |
3359 | if (netif_carrier_ok(dev)) { | |
3360 | netif_carrier_off(dev); | |
3361 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
3362 | nv_stop_rx(dev); | |
3363 | } | |
3364 | } | |
3365 | } | |
3366 | ||
3367 | static void nv_link_irq(struct net_device *dev) | |
3368 | { | |
3369 | u8 __iomem *base = get_hwbase(dev); | |
3370 | u32 miistat; | |
3371 | ||
3372 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3373 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3374 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
3375 | ||
3376 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3377 | nv_linkchange(dev); | |
3378 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | |
3379 | } | |
3380 | ||
4db0ee17 AA |
3381 | static void nv_msi_workaround(struct fe_priv *np) |
3382 | { | |
3383 | ||
3384 | /* Need to toggle the msi irq mask within the ethernet device, | |
3385 | * otherwise, future interrupts will not be detected. | |
3386 | */ | |
3387 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3388 | u8 __iomem *base = np->base; | |
3389 | ||
3390 | writel(0, base + NvRegMSIIrqMask); | |
3391 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3392 | } | |
3393 | } | |
3394 | ||
7d12e780 | 3395 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3396 | { |
3397 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3398 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3399 | u8 __iomem *base = get_hwbase(dev); |
3400 | u32 events; | |
3401 | int i; | |
3402 | ||
3403 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | |
3404 | ||
3405 | for (i=0; ; i++) { | |
d33a73c8 AA |
3406 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3407 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3408 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3409 | } else { | |
3410 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3411 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
3412 | } | |
1da177e4 LT |
3413 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3414 | if (!(events & np->irqmask)) | |
3415 | break; | |
3416 | ||
4db0ee17 AA |
3417 | nv_msi_workaround(np); |
3418 | ||
a971c324 AA |
3419 | spin_lock(&np->lock); |
3420 | nv_tx_done(dev); | |
3421 | spin_unlock(&np->lock); | |
f3b197ac | 3422 | |
f0734ab6 AA |
3423 | #ifdef CONFIG_FORCEDETH_NAPI |
3424 | if (events & NVREG_IRQ_RX_ALL) { | |
eb10a781 | 3425 | spin_lock(&np->lock); |
288379f0 | 3426 | napi_schedule(&np->napi); |
f0734ab6 AA |
3427 | |
3428 | /* Disable furthur receive irq's */ | |
f0734ab6 AA |
3429 | np->irqmask &= ~NVREG_IRQ_RX_ALL; |
3430 | ||
3431 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3432 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3433 | else | |
3434 | writel(np->irqmask, base + NvRegIrqMask); | |
3435 | spin_unlock(&np->lock); | |
3436 | } | |
3437 | #else | |
bea3348e | 3438 | if (nv_rx_process(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3439 | if (unlikely(nv_alloc_rx(dev))) { |
3440 | spin_lock(&np->lock); | |
3441 | if (!np->in_shutdown) | |
3442 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3443 | spin_unlock(&np->lock); | |
3444 | } | |
3445 | } | |
3446 | #endif | |
3447 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
1da177e4 LT |
3448 | spin_lock(&np->lock); |
3449 | nv_link_irq(dev); | |
3450 | spin_unlock(&np->lock); | |
3451 | } | |
f0734ab6 | 3452 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
1da177e4 LT |
3453 | spin_lock(&np->lock); |
3454 | nv_linkchange(dev); | |
3455 | spin_unlock(&np->lock); | |
3456 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3457 | } | |
f0734ab6 | 3458 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
1da177e4 LT |
3459 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3460 | dev->name, events); | |
3461 | } | |
f0734ab6 | 3462 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
1da177e4 LT |
3463 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
3464 | dev->name, events); | |
3465 | } | |
c5cf9101 AA |
3466 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { |
3467 | spin_lock(&np->lock); | |
3468 | /* disable interrupts on the nic */ | |
3469 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3470 | writel(0, base + NvRegIrqMask); | |
3471 | else | |
3472 | writel(np->irqmask, base + NvRegIrqMask); | |
3473 | pci_push(base); | |
3474 | ||
3475 | if (!np->in_shutdown) { | |
3476 | np->nic_poll_irq = np->irqmask; | |
3477 | np->recover_error = 1; | |
3478 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3479 | } | |
3480 | spin_unlock(&np->lock); | |
3481 | break; | |
3482 | } | |
f0734ab6 | 3483 | if (unlikely(i > max_interrupt_work)) { |
1da177e4 LT |
3484 | spin_lock(&np->lock); |
3485 | /* disable interrupts on the nic */ | |
d33a73c8 AA |
3486 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
3487 | writel(0, base + NvRegIrqMask); | |
3488 | else | |
3489 | writel(np->irqmask, base + NvRegIrqMask); | |
1da177e4 LT |
3490 | pci_push(base); |
3491 | ||
d33a73c8 AA |
3492 | if (!np->in_shutdown) { |
3493 | np->nic_poll_irq = np->irqmask; | |
1da177e4 | 3494 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
d33a73c8 | 3495 | } |
1da177e4 | 3496 | spin_unlock(&np->lock); |
1a2b7330 | 3497 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
1da177e4 LT |
3498 | break; |
3499 | } | |
3500 | ||
3501 | } | |
3502 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); | |
3503 | ||
3504 | return IRQ_RETVAL(i); | |
3505 | } | |
3506 | ||
f0734ab6 AA |
3507 | /** |
3508 | * All _optimized functions are used to help increase performance | |
3509 | * (reduce CPU and increase throughput). They use descripter version 3, | |
3510 | * compiler directives, and reduce memory accesses. | |
3511 | */ | |
86b22b0d AA |
3512 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3513 | { | |
3514 | struct net_device *dev = (struct net_device *) data; | |
3515 | struct fe_priv *np = netdev_priv(dev); | |
3516 | u8 __iomem *base = get_hwbase(dev); | |
3517 | u32 events; | |
3518 | int i; | |
3519 | ||
3520 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name); | |
3521 | ||
3522 | for (i=0; ; i++) { | |
3523 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3524 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3525 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3526 | } else { | |
3527 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3528 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
3529 | } | |
86b22b0d AA |
3530 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3531 | if (!(events & np->irqmask)) | |
3532 | break; | |
3533 | ||
4db0ee17 AA |
3534 | nv_msi_workaround(np); |
3535 | ||
86b22b0d | 3536 | spin_lock(&np->lock); |
4e16ed1b | 3537 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
86b22b0d AA |
3538 | spin_unlock(&np->lock); |
3539 | ||
f0734ab6 AA |
3540 | #ifdef CONFIG_FORCEDETH_NAPI |
3541 | if (events & NVREG_IRQ_RX_ALL) { | |
eb10a781 | 3542 | spin_lock(&np->lock); |
288379f0 | 3543 | napi_schedule(&np->napi); |
f0734ab6 AA |
3544 | |
3545 | /* Disable furthur receive irq's */ | |
f0734ab6 AA |
3546 | np->irqmask &= ~NVREG_IRQ_RX_ALL; |
3547 | ||
3548 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3549 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3550 | else | |
3551 | writel(np->irqmask, base + NvRegIrqMask); | |
3552 | spin_unlock(&np->lock); | |
3553 | } | |
3554 | #else | |
bea3348e | 3555 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3556 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3557 | spin_lock(&np->lock); | |
3558 | if (!np->in_shutdown) | |
3559 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3560 | spin_unlock(&np->lock); | |
3561 | } | |
3562 | } | |
3563 | #endif | |
3564 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
86b22b0d AA |
3565 | spin_lock(&np->lock); |
3566 | nv_link_irq(dev); | |
3567 | spin_unlock(&np->lock); | |
3568 | } | |
f0734ab6 | 3569 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
86b22b0d AA |
3570 | spin_lock(&np->lock); |
3571 | nv_linkchange(dev); | |
3572 | spin_unlock(&np->lock); | |
3573 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3574 | } | |
f0734ab6 | 3575 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
86b22b0d AA |
3576 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3577 | dev->name, events); | |
3578 | } | |
f0734ab6 | 3579 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
86b22b0d AA |
3580 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
3581 | dev->name, events); | |
3582 | } | |
3583 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { | |
3584 | spin_lock(&np->lock); | |
3585 | /* disable interrupts on the nic */ | |
3586 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3587 | writel(0, base + NvRegIrqMask); | |
3588 | else | |
3589 | writel(np->irqmask, base + NvRegIrqMask); | |
3590 | pci_push(base); | |
3591 | ||
3592 | if (!np->in_shutdown) { | |
3593 | np->nic_poll_irq = np->irqmask; | |
3594 | np->recover_error = 1; | |
3595 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3596 | } | |
3597 | spin_unlock(&np->lock); | |
3598 | break; | |
3599 | } | |
3600 | ||
f0734ab6 | 3601 | if (unlikely(i > max_interrupt_work)) { |
86b22b0d AA |
3602 | spin_lock(&np->lock); |
3603 | /* disable interrupts on the nic */ | |
3604 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3605 | writel(0, base + NvRegIrqMask); | |
3606 | else | |
3607 | writel(np->irqmask, base + NvRegIrqMask); | |
3608 | pci_push(base); | |
3609 | ||
3610 | if (!np->in_shutdown) { | |
3611 | np->nic_poll_irq = np->irqmask; | |
3612 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3613 | } | |
86b22b0d | 3614 | spin_unlock(&np->lock); |
1a2b7330 | 3615 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
86b22b0d AA |
3616 | break; |
3617 | } | |
3618 | ||
3619 | } | |
3620 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name); | |
3621 | ||
3622 | return IRQ_RETVAL(i); | |
3623 | } | |
3624 | ||
7d12e780 | 3625 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3626 | { |
3627 | struct net_device *dev = (struct net_device *) data; | |
3628 | struct fe_priv *np = netdev_priv(dev); | |
3629 | u8 __iomem *base = get_hwbase(dev); | |
3630 | u32 events; | |
3631 | int i; | |
0a07bc64 | 3632 | unsigned long flags; |
d33a73c8 AA |
3633 | |
3634 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | |
3635 | ||
3636 | for (i=0; ; i++) { | |
3637 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; | |
3638 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3639 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
3640 | if (!(events & np->irqmask)) | |
3641 | break; | |
3642 | ||
0a07bc64 | 3643 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3644 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3645 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3646 | |
f0734ab6 | 3647 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
d33a73c8 AA |
3648 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3649 | dev->name, events); | |
3650 | } | |
f0734ab6 | 3651 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3652 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3653 | /* disable interrupts on the nic */ |
3654 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3655 | pci_push(base); | |
3656 | ||
3657 | if (!np->in_shutdown) { | |
3658 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3659 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3660 | } | |
0a07bc64 | 3661 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3662 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
d33a73c8 AA |
3663 | break; |
3664 | } | |
3665 | ||
3666 | } | |
3667 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | |
3668 | ||
3669 | return IRQ_RETVAL(i); | |
3670 | } | |
3671 | ||
e27cdba5 | 3672 | #ifdef CONFIG_FORCEDETH_NAPI |
bea3348e | 3673 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3674 | { |
bea3348e SH |
3675 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3676 | struct net_device *dev = np->dev; | |
e27cdba5 | 3677 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3678 | unsigned long flags; |
bea3348e | 3679 | int pkts, retcode; |
e27cdba5 | 3680 | |
36b30ea9 | 3681 | if (!nv_optimized(np)) { |
bea3348e | 3682 | pkts = nv_rx_process(dev, budget); |
e0379a14 AA |
3683 | retcode = nv_alloc_rx(dev); |
3684 | } else { | |
bea3348e | 3685 | pkts = nv_rx_process_optimized(dev, budget); |
e0379a14 AA |
3686 | retcode = nv_alloc_rx_optimized(dev); |
3687 | } | |
e27cdba5 | 3688 | |
e0379a14 | 3689 | if (retcode) { |
d15e9c4d | 3690 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3691 | if (!np->in_shutdown) |
3692 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3693 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3694 | } |
3695 | ||
bea3348e | 3696 | if (pkts < budget) { |
e27cdba5 | 3697 | /* re-enable receive interrupts */ |
d15e9c4d FR |
3698 | spin_lock_irqsave(&np->lock, flags); |
3699 | ||
288379f0 | 3700 | __napi_complete(napi); |
bea3348e | 3701 | |
e27cdba5 SH |
3702 | np->irqmask |= NVREG_IRQ_RX_ALL; |
3703 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3704 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3705 | else | |
3706 | writel(np->irqmask, base + NvRegIrqMask); | |
d15e9c4d FR |
3707 | |
3708 | spin_unlock_irqrestore(&np->lock, flags); | |
e27cdba5 | 3709 | } |
bea3348e | 3710 | return pkts; |
e27cdba5 SH |
3711 | } |
3712 | #endif | |
3713 | ||
3714 | #ifdef CONFIG_FORCEDETH_NAPI | |
7d12e780 | 3715 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
e27cdba5 SH |
3716 | { |
3717 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 3718 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
3719 | u8 __iomem *base = get_hwbase(dev); |
3720 | u32 events; | |
3721 | ||
3722 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
e27cdba5 SH |
3723 | |
3724 | if (events) { | |
e27cdba5 SH |
3725 | /* disable receive interrupts on the nic */ |
3726 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3727 | pci_push(base); | |
0335ef5d YL |
3728 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
3729 | napi_schedule(&np->napi); | |
e27cdba5 SH |
3730 | } |
3731 | return IRQ_HANDLED; | |
3732 | } | |
3733 | #else | |
7d12e780 | 3734 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3735 | { |
3736 | struct net_device *dev = (struct net_device *) data; | |
3737 | struct fe_priv *np = netdev_priv(dev); | |
3738 | u8 __iomem *base = get_hwbase(dev); | |
3739 | u32 events; | |
3740 | int i; | |
0a07bc64 | 3741 | unsigned long flags; |
d33a73c8 AA |
3742 | |
3743 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | |
3744 | ||
3745 | for (i=0; ; i++) { | |
3746 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
3747 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3748 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
3749 | if (!(events & np->irqmask)) | |
3750 | break; | |
f3b197ac | 3751 | |
bea3348e | 3752 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3753 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3754 | spin_lock_irqsave(&np->lock, flags); | |
3755 | if (!np->in_shutdown) | |
3756 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3757 | spin_unlock_irqrestore(&np->lock, flags); | |
3758 | } | |
d33a73c8 | 3759 | } |
f3b197ac | 3760 | |
f0734ab6 | 3761 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3762 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3763 | /* disable interrupts on the nic */ |
3764 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3765 | pci_push(base); | |
3766 | ||
3767 | if (!np->in_shutdown) { | |
3768 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3769 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3770 | } | |
0a07bc64 | 3771 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3772 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
d33a73c8 AA |
3773 | break; |
3774 | } | |
d33a73c8 AA |
3775 | } |
3776 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | |
3777 | ||
3778 | return IRQ_RETVAL(i); | |
3779 | } | |
e27cdba5 | 3780 | #endif |
d33a73c8 | 3781 | |
7d12e780 | 3782 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3783 | { |
3784 | struct net_device *dev = (struct net_device *) data; | |
3785 | struct fe_priv *np = netdev_priv(dev); | |
3786 | u8 __iomem *base = get_hwbase(dev); | |
3787 | u32 events; | |
3788 | int i; | |
0a07bc64 | 3789 | unsigned long flags; |
d33a73c8 AA |
3790 | |
3791 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | |
3792 | ||
3793 | for (i=0; ; i++) { | |
3794 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; | |
3795 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3796 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3797 | if (!(events & np->irqmask)) | |
3798 | break; | |
f3b197ac | 3799 | |
4e16ed1b AA |
3800 | /* check tx in case we reached max loop limit in tx isr */ |
3801 | spin_lock_irqsave(&np->lock, flags); | |
3802 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3803 | spin_unlock_irqrestore(&np->lock, flags); | |
3804 | ||
d33a73c8 | 3805 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3806 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3807 | nv_link_irq(dev); |
0a07bc64 | 3808 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3809 | } |
3810 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3811 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3812 | nv_linkchange(dev); |
0a07bc64 | 3813 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3814 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3815 | } | |
c5cf9101 AA |
3816 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3817 | spin_lock_irq(&np->lock); | |
3818 | /* disable interrupts on the nic */ | |
3819 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3820 | pci_push(base); | |
3821 | ||
3822 | if (!np->in_shutdown) { | |
3823 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3824 | np->recover_error = 1; | |
3825 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3826 | } | |
3827 | spin_unlock_irq(&np->lock); | |
3828 | break; | |
3829 | } | |
d33a73c8 AA |
3830 | if (events & (NVREG_IRQ_UNKNOWN)) { |
3831 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", | |
3832 | dev->name, events); | |
3833 | } | |
f0734ab6 | 3834 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3835 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3836 | /* disable interrupts on the nic */ |
3837 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3838 | pci_push(base); | |
3839 | ||
3840 | if (!np->in_shutdown) { | |
3841 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3842 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3843 | } | |
0a07bc64 | 3844 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3845 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
d33a73c8 AA |
3846 | break; |
3847 | } | |
3848 | ||
3849 | } | |
3850 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | |
3851 | ||
3852 | return IRQ_RETVAL(i); | |
3853 | } | |
3854 | ||
7d12e780 | 3855 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3856 | { |
3857 | struct net_device *dev = (struct net_device *) data; | |
3858 | struct fe_priv *np = netdev_priv(dev); | |
3859 | u8 __iomem *base = get_hwbase(dev); | |
3860 | u32 events; | |
3861 | ||
3862 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); | |
3863 | ||
3864 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3865 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3866 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3867 | } else { | |
3868 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3869 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3870 | } | |
3871 | pci_push(base); | |
3872 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
3873 | if (!(events & NVREG_IRQ_TIMER)) | |
3874 | return IRQ_RETVAL(0); | |
3875 | ||
4db0ee17 AA |
3876 | nv_msi_workaround(np); |
3877 | ||
9589c77a AA |
3878 | spin_lock(&np->lock); |
3879 | np->intr_test = 1; | |
3880 | spin_unlock(&np->lock); | |
3881 | ||
3882 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); | |
3883 | ||
3884 | return IRQ_RETVAL(1); | |
3885 | } | |
3886 | ||
7a1854b7 AA |
3887 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3888 | { | |
3889 | u8 __iomem *base = get_hwbase(dev); | |
3890 | int i; | |
3891 | u32 msixmap = 0; | |
3892 | ||
3893 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3894 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3895 | * the remaining 8 interrupts. | |
3896 | */ | |
3897 | for (i = 0; i < 8; i++) { | |
3898 | if ((irqmask >> i) & 0x1) { | |
3899 | msixmap |= vector << (i << 2); | |
3900 | } | |
3901 | } | |
3902 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3903 | ||
3904 | msixmap = 0; | |
3905 | for (i = 0; i < 8; i++) { | |
3906 | if ((irqmask >> (i + 8)) & 0x1) { | |
3907 | msixmap |= vector << (i << 2); | |
3908 | } | |
3909 | } | |
3910 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3911 | } | |
3912 | ||
9589c77a | 3913 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3914 | { |
3915 | struct fe_priv *np = get_nvpriv(dev); | |
3916 | u8 __iomem *base = get_hwbase(dev); | |
3917 | int ret = 1; | |
3918 | int i; | |
86b22b0d AA |
3919 | irqreturn_t (*handler)(int foo, void *data); |
3920 | ||
3921 | if (intr_test) { | |
3922 | handler = nv_nic_irq_test; | |
3923 | } else { | |
36b30ea9 | 3924 | if (nv_optimized(np)) |
86b22b0d AA |
3925 | handler = nv_nic_irq_optimized; |
3926 | else | |
3927 | handler = nv_nic_irq; | |
3928 | } | |
7a1854b7 AA |
3929 | |
3930 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
3931 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
3932 | np->msi_x_entry[i].entry = i; | |
3933 | } | |
3934 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { | |
3935 | np->msi_flags |= NV_MSI_X_ENABLED; | |
9589c77a | 3936 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3937 | /* Request irq for rx handling */ |
ddb213f0 YL |
3938 | sprintf(np->name_rx, "%s-rx", dev->name); |
3939 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, | |
3940 | &nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { | |
7a1854b7 AA |
3941 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3942 | pci_disable_msix(np->pci_dev); | |
3943 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3944 | goto out_err; | |
3945 | } | |
3946 | /* Request irq for tx handling */ | |
ddb213f0 YL |
3947 | sprintf(np->name_tx, "%s-tx", dev->name); |
3948 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, | |
3949 | &nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { | |
7a1854b7 AA |
3950 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3951 | pci_disable_msix(np->pci_dev); | |
3952 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3953 | goto out_free_rx; | |
3954 | } | |
3955 | /* Request irq for link and timer handling */ | |
ddb213f0 YL |
3956 | sprintf(np->name_other, "%s-other", dev->name); |
3957 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, | |
3958 | &nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { | |
7a1854b7 AA |
3959 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3960 | pci_disable_msix(np->pci_dev); | |
3961 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3962 | goto out_free_tx; | |
3963 | } | |
3964 | /* map interrupts to their respective vector */ | |
3965 | writel(0, base + NvRegMSIXMap0); | |
3966 | writel(0, base + NvRegMSIXMap1); | |
3967 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3968 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3969 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3970 | } else { | |
3971 | /* Request irq for all interrupts */ | |
86b22b0d | 3972 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3973 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3974 | pci_disable_msix(np->pci_dev); | |
3975 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3976 | goto out_err; | |
3977 | } | |
3978 | ||
3979 | /* map interrupts to vector 0 */ | |
3980 | writel(0, base + NvRegMSIXMap0); | |
3981 | writel(0, base + NvRegMSIXMap1); | |
3982 | } | |
3983 | } | |
3984 | } | |
3985 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
3986 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | |
3987 | np->msi_flags |= NV_MSI_ENABLED; | |
a7475906 | 3988 | dev->irq = np->pci_dev->irq; |
86b22b0d | 3989 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3990 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3991 | pci_disable_msi(np->pci_dev); | |
3992 | np->msi_flags &= ~NV_MSI_ENABLED; | |
a7475906 | 3993 | dev->irq = np->pci_dev->irq; |
7a1854b7 AA |
3994 | goto out_err; |
3995 | } | |
3996 | ||
3997 | /* map interrupts to vector 0 */ | |
3998 | writel(0, base + NvRegMSIMap0); | |
3999 | writel(0, base + NvRegMSIMap1); | |
4000 | /* enable msi vector 0 */ | |
4001 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
4002 | } | |
4003 | } | |
4004 | if (ret != 0) { | |
86b22b0d | 4005 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 4006 | goto out_err; |
9589c77a | 4007 | |
7a1854b7 AA |
4008 | } |
4009 | ||
4010 | return 0; | |
4011 | out_free_tx: | |
4012 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
4013 | out_free_rx: | |
4014 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
4015 | out_err: | |
4016 | return 1; | |
4017 | } | |
4018 | ||
4019 | static void nv_free_irq(struct net_device *dev) | |
4020 | { | |
4021 | struct fe_priv *np = get_nvpriv(dev); | |
4022 | int i; | |
4023 | ||
4024 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
4025 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
4026 | free_irq(np->msi_x_entry[i].vector, dev); | |
4027 | } | |
4028 | pci_disable_msix(np->pci_dev); | |
4029 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
4030 | } else { | |
4031 | free_irq(np->pci_dev->irq, dev); | |
4032 | if (np->msi_flags & NV_MSI_ENABLED) { | |
4033 | pci_disable_msi(np->pci_dev); | |
4034 | np->msi_flags &= ~NV_MSI_ENABLED; | |
4035 | } | |
4036 | } | |
4037 | } | |
4038 | ||
1da177e4 LT |
4039 | static void nv_do_nic_poll(unsigned long data) |
4040 | { | |
4041 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 4042 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4043 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 4044 | u32 mask = 0; |
1da177e4 | 4045 | |
1da177e4 | 4046 | /* |
d33a73c8 | 4047 | * First disable irq(s) and then |
1da177e4 LT |
4048 | * reenable interrupts on the nic, we have to do this before calling |
4049 | * nv_nic_irq because that may decide to do otherwise | |
4050 | */ | |
d33a73c8 | 4051 | |
84b3932b AA |
4052 | if (!using_multi_irqs(dev)) { |
4053 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 4054 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 4055 | else |
a7475906 | 4056 | disable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
4057 | mask = np->irqmask; |
4058 | } else { | |
4059 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 4060 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
4061 | mask |= NVREG_IRQ_RX_ALL; |
4062 | } | |
4063 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 4064 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
4065 | mask |= NVREG_IRQ_TX_ALL; |
4066 | } | |
4067 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 4068 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
4069 | mask |= NVREG_IRQ_OTHER; |
4070 | } | |
4071 | } | |
a7475906 MS |
4072 | /* disable_irq() contains synchronize_irq, thus no irq handler can run now */ |
4073 | ||
c5cf9101 AA |
4074 | if (np->recover_error) { |
4075 | np->recover_error = 0; | |
4076 | printk(KERN_INFO "forcedeth: MAC in recoverable error state\n"); | |
4077 | if (netif_running(dev)) { | |
4078 | netif_tx_lock_bh(dev); | |
e308a5d8 | 4079 | netif_addr_lock(dev); |
c5cf9101 AA |
4080 | spin_lock(&np->lock); |
4081 | /* stop engines */ | |
36b30ea9 | 4082 | nv_stop_rxtx(dev); |
c5cf9101 AA |
4083 | nv_txrx_reset(dev); |
4084 | /* drain rx queue */ | |
36b30ea9 | 4085 | nv_drain_rxtx(dev); |
c5cf9101 AA |
4086 | /* reinit driver view of the rx queue */ |
4087 | set_bufsize(dev); | |
4088 | if (nv_init_ring(dev)) { | |
4089 | if (!np->in_shutdown) | |
4090 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4091 | } | |
4092 | /* reinit nic view of the rx queue */ | |
4093 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4094 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4095 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4096 | base + NvRegRingSizes); | |
4097 | pci_push(base); | |
4098 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4099 | pci_push(base); | |
4100 | ||
4101 | /* restart rx engine */ | |
36b30ea9 | 4102 | nv_start_rxtx(dev); |
c5cf9101 | 4103 | spin_unlock(&np->lock); |
e308a5d8 | 4104 | netif_addr_unlock(dev); |
c5cf9101 AA |
4105 | netif_tx_unlock_bh(dev); |
4106 | } | |
4107 | } | |
4108 | ||
d33a73c8 | 4109 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 4110 | pci_push(base); |
d33a73c8 | 4111 | |
84b3932b | 4112 | if (!using_multi_irqs(dev)) { |
79d30a58 | 4113 | np->nic_poll_irq = 0; |
36b30ea9 | 4114 | if (nv_optimized(np)) |
fcc5f266 AA |
4115 | nv_nic_irq_optimized(0, dev); |
4116 | else | |
4117 | nv_nic_irq(0, dev); | |
84b3932b | 4118 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 4119 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 4120 | else |
a7475906 | 4121 | enable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
4122 | } else { |
4123 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 4124 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 4125 | nv_nic_irq_rx(0, dev); |
8688cfce | 4126 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
4127 | } |
4128 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 4129 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 4130 | nv_nic_irq_tx(0, dev); |
8688cfce | 4131 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
4132 | } |
4133 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 4134 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 4135 | nv_nic_irq_other(0, dev); |
8688cfce | 4136 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
4137 | } |
4138 | } | |
79d30a58 | 4139 | |
1da177e4 LT |
4140 | } |
4141 | ||
2918c35d MS |
4142 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4143 | static void nv_poll_controller(struct net_device *dev) | |
4144 | { | |
4145 | nv_do_nic_poll((unsigned long) dev); | |
4146 | } | |
4147 | #endif | |
4148 | ||
52da3578 AA |
4149 | static void nv_do_stats_poll(unsigned long data) |
4150 | { | |
4151 | struct net_device *dev = (struct net_device *) data; | |
4152 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 4153 | |
57fff698 | 4154 | nv_get_hw_stats(dev); |
52da3578 AA |
4155 | |
4156 | if (!np->in_shutdown) | |
bfebbb88 DD |
4157 | mod_timer(&np->stats_poll, |
4158 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
4159 | } |
4160 | ||
1da177e4 LT |
4161 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4162 | { | |
ac9c1897 | 4163 | struct fe_priv *np = netdev_priv(dev); |
3f88ce49 | 4164 | strcpy(info->driver, DRV_NAME); |
1da177e4 LT |
4165 | strcpy(info->version, FORCEDETH_VERSION); |
4166 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
4167 | } | |
4168 | ||
4169 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4170 | { | |
ac9c1897 | 4171 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4172 | wolinfo->supported = WAKE_MAGIC; |
4173 | ||
4174 | spin_lock_irq(&np->lock); | |
4175 | if (np->wolenabled) | |
4176 | wolinfo->wolopts = WAKE_MAGIC; | |
4177 | spin_unlock_irq(&np->lock); | |
4178 | } | |
4179 | ||
4180 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4181 | { | |
ac9c1897 | 4182 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4183 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 4184 | u32 flags = 0; |
1da177e4 | 4185 | |
1da177e4 | 4186 | if (wolinfo->wolopts == 0) { |
1da177e4 | 4187 | np->wolenabled = 0; |
c42d9df9 | 4188 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 4189 | np->wolenabled = 1; |
c42d9df9 AA |
4190 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
4191 | } | |
4192 | if (netif_running(dev)) { | |
4193 | spin_lock_irq(&np->lock); | |
4194 | writel(flags, base + NvRegWakeUpFlags); | |
4195 | spin_unlock_irq(&np->lock); | |
1da177e4 | 4196 | } |
1da177e4 LT |
4197 | return 0; |
4198 | } | |
4199 | ||
4200 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4201 | { | |
4202 | struct fe_priv *np = netdev_priv(dev); | |
4203 | int adv; | |
4204 | ||
4205 | spin_lock_irq(&np->lock); | |
4206 | ecmd->port = PORT_MII; | |
4207 | if (!netif_running(dev)) { | |
4208 | /* We do not track link speed / duplex setting if the | |
4209 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
4210 | if (nv_update_linkspeed(dev)) { |
4211 | if (!netif_carrier_ok(dev)) | |
4212 | netif_carrier_on(dev); | |
4213 | } else { | |
4214 | if (netif_carrier_ok(dev)) | |
4215 | netif_carrier_off(dev); | |
4216 | } | |
1da177e4 | 4217 | } |
f9430a01 AA |
4218 | |
4219 | if (netif_carrier_ok(dev)) { | |
4220 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { | |
1da177e4 LT |
4221 | case NVREG_LINKSPEED_10: |
4222 | ecmd->speed = SPEED_10; | |
4223 | break; | |
4224 | case NVREG_LINKSPEED_100: | |
4225 | ecmd->speed = SPEED_100; | |
4226 | break; | |
4227 | case NVREG_LINKSPEED_1000: | |
4228 | ecmd->speed = SPEED_1000; | |
4229 | break; | |
f9430a01 AA |
4230 | } |
4231 | ecmd->duplex = DUPLEX_HALF; | |
4232 | if (np->duplex) | |
4233 | ecmd->duplex = DUPLEX_FULL; | |
4234 | } else { | |
4235 | ecmd->speed = -1; | |
4236 | ecmd->duplex = -1; | |
1da177e4 | 4237 | } |
1da177e4 LT |
4238 | |
4239 | ecmd->autoneg = np->autoneg; | |
4240 | ||
4241 | ecmd->advertising = ADVERTISED_MII; | |
4242 | if (np->autoneg) { | |
4243 | ecmd->advertising |= ADVERTISED_Autoneg; | |
4244 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
4245 | if (adv & ADVERTISE_10HALF) |
4246 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
4247 | if (adv & ADVERTISE_10FULL) | |
4248 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
4249 | if (adv & ADVERTISE_100HALF) | |
4250 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
4251 | if (adv & ADVERTISE_100FULL) | |
4252 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
4253 | if (np->gigabit == PHY_GIGABIT) { | |
4254 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4255 | if (adv & ADVERTISE_1000FULL) | |
4256 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
4257 | } | |
1da177e4 | 4258 | } |
1da177e4 LT |
4259 | ecmd->supported = (SUPPORTED_Autoneg | |
4260 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
4261 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4262 | SUPPORTED_MII); | |
4263 | if (np->gigabit == PHY_GIGABIT) | |
4264 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
4265 | ||
4266 | ecmd->phy_address = np->phyaddr; | |
4267 | ecmd->transceiver = XCVR_EXTERNAL; | |
4268 | ||
4269 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4270 | spin_unlock_irq(&np->lock); | |
4271 | return 0; | |
4272 | } | |
4273 | ||
4274 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4275 | { | |
4276 | struct fe_priv *np = netdev_priv(dev); | |
4277 | ||
4278 | if (ecmd->port != PORT_MII) | |
4279 | return -EINVAL; | |
4280 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
4281 | return -EINVAL; | |
4282 | if (ecmd->phy_address != np->phyaddr) { | |
4283 | /* TODO: support switching between multiple phys. Should be | |
4284 | * trivial, but not enabled due to lack of test hardware. */ | |
4285 | return -EINVAL; | |
4286 | } | |
4287 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
4288 | u32 mask; | |
4289 | ||
4290 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4291 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4292 | if (np->gigabit == PHY_GIGABIT) | |
4293 | mask |= ADVERTISED_1000baseT_Full; | |
4294 | ||
4295 | if ((ecmd->advertising & mask) == 0) | |
4296 | return -EINVAL; | |
4297 | ||
4298 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
4299 | /* Note: autonegotiation disable, speed 1000 intentionally | |
4300 | * forbidden - noone should need that. */ | |
4301 | ||
4302 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
4303 | return -EINVAL; | |
4304 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
4305 | return -EINVAL; | |
4306 | } else { | |
4307 | return -EINVAL; | |
4308 | } | |
4309 | ||
f9430a01 AA |
4310 | netif_carrier_off(dev); |
4311 | if (netif_running(dev)) { | |
97bff095 TD |
4312 | unsigned long flags; |
4313 | ||
f9430a01 | 4314 | nv_disable_irq(dev); |
58dfd9c1 | 4315 | netif_tx_lock_bh(dev); |
e308a5d8 | 4316 | netif_addr_lock(dev); |
97bff095 TD |
4317 | /* with plain spinlock lockdep complains */ |
4318 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4319 | /* stop engines */ |
97bff095 TD |
4320 | /* FIXME: |
4321 | * this can take some time, and interrupts are disabled | |
4322 | * due to spin_lock_irqsave, but let's hope no daemon | |
4323 | * is going to change the settings very often... | |
4324 | * Worst case: | |
4325 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4326 | * + some minor delays, which is up to a second approximately | |
4327 | */ | |
36b30ea9 | 4328 | nv_stop_rxtx(dev); |
97bff095 | 4329 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4330 | netif_addr_unlock(dev); |
58dfd9c1 | 4331 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4332 | } |
4333 | ||
1da177e4 LT |
4334 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
4335 | int adv, bmcr; | |
4336 | ||
4337 | np->autoneg = 1; | |
4338 | ||
4339 | /* advertise only what has been requested */ | |
4340 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4341 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4342 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
4343 | adv |= ADVERTISE_10HALF; | |
4344 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 4345 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4346 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
4347 | adv |= ADVERTISE_100HALF; | |
4348 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f AA |
4349 | adv |= ADVERTISE_100FULL; |
4350 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4351 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4352 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4353 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4354 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4355 | ||
4356 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4357 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
4358 | adv &= ~ADVERTISE_1000FULL; |
4359 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
4360 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 4361 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4362 | } |
4363 | ||
f9430a01 AA |
4364 | if (netif_running(dev)) |
4365 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
1da177e4 | 4366 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4367 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4368 | bmcr |= BMCR_ANENABLE; | |
4369 | /* reset the phy in order for settings to stick, | |
4370 | * and cause autoneg to start */ | |
4371 | if (phy_reset(dev, bmcr)) { | |
4372 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4373 | return -EINVAL; | |
4374 | } | |
4375 | } else { | |
4376 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4377 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4378 | } | |
1da177e4 LT |
4379 | } else { |
4380 | int adv, bmcr; | |
4381 | ||
4382 | np->autoneg = 0; | |
4383 | ||
4384 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4385 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4386 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
4387 | adv |= ADVERTISE_10HALF; | |
4388 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f | 4389 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4390 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
4391 | adv |= ADVERTISE_100HALF; | |
4392 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f AA |
4393 | adv |= ADVERTISE_100FULL; |
4394 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4395 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ | |
4396 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4397 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4398 | } | |
4399 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4400 | adv |= ADVERTISE_PAUSE_ASYM; | |
4401 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4402 | } | |
1da177e4 LT |
4403 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4404 | np->fixed_mode = adv; | |
4405 | ||
4406 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4407 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4408 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4409 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4410 | } |
4411 | ||
4412 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4413 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4414 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4415 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4416 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4417 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4418 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4419 | /* reset the phy in order for forced mode settings to stick */ |
4420 | if (phy_reset(dev, bmcr)) { | |
f9430a01 AA |
4421 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4422 | return -EINVAL; | |
4423 | } | |
edf7e5ec AA |
4424 | } else { |
4425 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4426 | if (netif_running(dev)) { | |
4427 | /* Wait a bit and then reconfigure the nic. */ | |
4428 | udelay(10); | |
4429 | nv_linkchange(dev); | |
4430 | } | |
1da177e4 LT |
4431 | } |
4432 | } | |
f9430a01 AA |
4433 | |
4434 | if (netif_running(dev)) { | |
36b30ea9 | 4435 | nv_start_rxtx(dev); |
f9430a01 AA |
4436 | nv_enable_irq(dev); |
4437 | } | |
1da177e4 LT |
4438 | |
4439 | return 0; | |
4440 | } | |
4441 | ||
dc8216c1 | 4442 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4443 | |
4444 | static int nv_get_regs_len(struct net_device *dev) | |
4445 | { | |
86a0f043 AA |
4446 | struct fe_priv *np = netdev_priv(dev); |
4447 | return np->register_size; | |
dc8216c1 MS |
4448 | } |
4449 | ||
4450 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4451 | { | |
ac9c1897 | 4452 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4453 | u8 __iomem *base = get_hwbase(dev); |
4454 | u32 *rbuf = buf; | |
4455 | int i; | |
4456 | ||
4457 | regs->version = FORCEDETH_REGS_VER; | |
4458 | spin_lock_irq(&np->lock); | |
86a0f043 | 4459 | for (i = 0;i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4460 | rbuf[i] = readl(base + i*sizeof(u32)); |
4461 | spin_unlock_irq(&np->lock); | |
4462 | } | |
4463 | ||
4464 | static int nv_nway_reset(struct net_device *dev) | |
4465 | { | |
ac9c1897 | 4466 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4467 | int ret; |
4468 | ||
dc8216c1 MS |
4469 | if (np->autoneg) { |
4470 | int bmcr; | |
4471 | ||
f9430a01 AA |
4472 | netif_carrier_off(dev); |
4473 | if (netif_running(dev)) { | |
4474 | nv_disable_irq(dev); | |
58dfd9c1 | 4475 | netif_tx_lock_bh(dev); |
e308a5d8 | 4476 | netif_addr_lock(dev); |
f9430a01 AA |
4477 | spin_lock(&np->lock); |
4478 | /* stop engines */ | |
36b30ea9 | 4479 | nv_stop_rxtx(dev); |
f9430a01 | 4480 | spin_unlock(&np->lock); |
e308a5d8 | 4481 | netif_addr_unlock(dev); |
58dfd9c1 | 4482 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4483 | printk(KERN_INFO "%s: link down.\n", dev->name); |
4484 | } | |
4485 | ||
dc8216c1 | 4486 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4487 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4488 | bmcr |= BMCR_ANENABLE; | |
4489 | /* reset the phy in order for settings to stick*/ | |
4490 | if (phy_reset(dev, bmcr)) { | |
4491 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4492 | return -EINVAL; | |
4493 | } | |
4494 | } else { | |
4495 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4496 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4497 | } | |
dc8216c1 | 4498 | |
f9430a01 | 4499 | if (netif_running(dev)) { |
36b30ea9 | 4500 | nv_start_rxtx(dev); |
f9430a01 AA |
4501 | nv_enable_irq(dev); |
4502 | } | |
dc8216c1 MS |
4503 | ret = 0; |
4504 | } else { | |
4505 | ret = -EINVAL; | |
4506 | } | |
dc8216c1 MS |
4507 | |
4508 | return ret; | |
4509 | } | |
4510 | ||
0674d594 ZA |
4511 | static int nv_set_tso(struct net_device *dev, u32 value) |
4512 | { | |
4513 | struct fe_priv *np = netdev_priv(dev); | |
4514 | ||
4515 | if ((np->driver_data & DEV_HAS_CHECKSUM)) | |
4516 | return ethtool_op_set_tso(dev, value); | |
4517 | else | |
6a78814f | 4518 | return -EOPNOTSUPP; |
0674d594 | 4519 | } |
0674d594 | 4520 | |
eafa59f6 AA |
4521 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4522 | { | |
4523 | struct fe_priv *np = netdev_priv(dev); | |
4524 | ||
4525 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4526 | ring->rx_mini_max_pending = 0; | |
4527 | ring->rx_jumbo_max_pending = 0; | |
4528 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4529 | ||
4530 | ring->rx_pending = np->rx_ring_size; | |
4531 | ring->rx_mini_pending = 0; | |
4532 | ring->rx_jumbo_pending = 0; | |
4533 | ring->tx_pending = np->tx_ring_size; | |
4534 | } | |
4535 | ||
4536 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4537 | { | |
4538 | struct fe_priv *np = netdev_priv(dev); | |
4539 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4540 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4541 | dma_addr_t ring_addr; |
4542 | ||
4543 | if (ring->rx_pending < RX_RING_MIN || | |
4544 | ring->tx_pending < TX_RING_MIN || | |
4545 | ring->rx_mini_pending != 0 || | |
4546 | ring->rx_jumbo_pending != 0 || | |
4547 | (np->desc_ver == DESC_VER_1 && | |
4548 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4549 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4550 | (np->desc_ver != DESC_VER_1 && | |
4551 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4552 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4553 | return -EINVAL; | |
4554 | } | |
4555 | ||
4556 | /* allocate new rings */ | |
36b30ea9 | 4557 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4558 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4559 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4560 | &ring_addr); | |
4561 | } else { | |
4562 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4563 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4564 | &ring_addr); | |
4565 | } | |
761fcd9e AA |
4566 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4567 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4568 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4569 | /* fall back to old rings */ |
36b30ea9 | 4570 | if (!nv_optimized(np)) { |
f82a9352 | 4571 | if (rxtx_ring) |
eafa59f6 AA |
4572 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4573 | rxtx_ring, ring_addr); | |
4574 | } else { | |
4575 | if (rxtx_ring) | |
4576 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4577 | rxtx_ring, ring_addr); | |
4578 | } | |
4579 | if (rx_skbuff) | |
4580 | kfree(rx_skbuff); | |
eafa59f6 AA |
4581 | if (tx_skbuff) |
4582 | kfree(tx_skbuff); | |
eafa59f6 AA |
4583 | goto exit; |
4584 | } | |
4585 | ||
4586 | if (netif_running(dev)) { | |
4587 | nv_disable_irq(dev); | |
58dfd9c1 | 4588 | netif_tx_lock_bh(dev); |
e308a5d8 | 4589 | netif_addr_lock(dev); |
eafa59f6 AA |
4590 | spin_lock(&np->lock); |
4591 | /* stop engines */ | |
36b30ea9 | 4592 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4593 | nv_txrx_reset(dev); |
4594 | /* drain queues */ | |
36b30ea9 | 4595 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4596 | /* delete queues */ |
4597 | free_rings(dev); | |
4598 | } | |
4599 | ||
4600 | /* set new values */ | |
4601 | np->rx_ring_size = ring->rx_pending; | |
4602 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4603 | |
4604 | if (!nv_optimized(np)) { | |
eafa59f6 AA |
4605 | np->rx_ring.orig = (struct ring_desc*)rxtx_ring; |
4606 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; | |
4607 | } else { | |
4608 | np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; | |
4609 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; | |
4610 | } | |
761fcd9e AA |
4611 | np->rx_skb = (struct nv_skb_map*)rx_skbuff; |
4612 | np->tx_skb = (struct nv_skb_map*)tx_skbuff; | |
eafa59f6 AA |
4613 | np->ring_addr = ring_addr; |
4614 | ||
761fcd9e AA |
4615 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4616 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4617 | |
4618 | if (netif_running(dev)) { | |
4619 | /* reinit driver view of the queues */ | |
4620 | set_bufsize(dev); | |
4621 | if (nv_init_ring(dev)) { | |
4622 | if (!np->in_shutdown) | |
4623 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4624 | } | |
4625 | ||
4626 | /* reinit nic view of the queues */ | |
4627 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4628 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4629 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4630 | base + NvRegRingSizes); | |
4631 | pci_push(base); | |
4632 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4633 | pci_push(base); | |
4634 | ||
4635 | /* restart engines */ | |
36b30ea9 | 4636 | nv_start_rxtx(dev); |
eafa59f6 | 4637 | spin_unlock(&np->lock); |
e308a5d8 | 4638 | netif_addr_unlock(dev); |
58dfd9c1 | 4639 | netif_tx_unlock_bh(dev); |
eafa59f6 AA |
4640 | nv_enable_irq(dev); |
4641 | } | |
4642 | return 0; | |
4643 | exit: | |
4644 | return -ENOMEM; | |
4645 | } | |
4646 | ||
b6d0773f AA |
4647 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4648 | { | |
4649 | struct fe_priv *np = netdev_priv(dev); | |
4650 | ||
4651 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4652 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4653 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4654 | } | |
4655 | ||
4656 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4657 | { | |
4658 | struct fe_priv *np = netdev_priv(dev); | |
4659 | int adv, bmcr; | |
4660 | ||
4661 | if ((!np->autoneg && np->duplex == 0) || | |
4662 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
4663 | printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", | |
4664 | dev->name); | |
4665 | return -EINVAL; | |
4666 | } | |
4667 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
4668 | printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); | |
4669 | return -EINVAL; | |
4670 | } | |
4671 | ||
4672 | netif_carrier_off(dev); | |
4673 | if (netif_running(dev)) { | |
4674 | nv_disable_irq(dev); | |
58dfd9c1 | 4675 | netif_tx_lock_bh(dev); |
e308a5d8 | 4676 | netif_addr_lock(dev); |
b6d0773f AA |
4677 | spin_lock(&np->lock); |
4678 | /* stop engines */ | |
36b30ea9 | 4679 | nv_stop_rxtx(dev); |
b6d0773f | 4680 | spin_unlock(&np->lock); |
e308a5d8 | 4681 | netif_addr_unlock(dev); |
58dfd9c1 | 4682 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4683 | } |
4684 | ||
4685 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4686 | if (pause->rx_pause) | |
4687 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4688 | if (pause->tx_pause) | |
4689 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4690 | ||
4691 | if (np->autoneg && pause->autoneg) { | |
4692 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4693 | ||
4694 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4695 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
4696 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4697 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4698 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4699 | adv |= ADVERTISE_PAUSE_ASYM; | |
4700 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4701 | ||
4702 | if (netif_running(dev)) | |
4703 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
4704 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4705 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4706 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4707 | } else { | |
4708 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4709 | if (pause->rx_pause) | |
4710 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4711 | if (pause->tx_pause) | |
4712 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4713 | ||
4714 | if (!netif_running(dev)) | |
4715 | nv_update_linkspeed(dev); | |
4716 | else | |
4717 | nv_update_pause(dev, np->pause_flags); | |
4718 | } | |
4719 | ||
4720 | if (netif_running(dev)) { | |
36b30ea9 | 4721 | nv_start_rxtx(dev); |
b6d0773f AA |
4722 | nv_enable_irq(dev); |
4723 | } | |
4724 | return 0; | |
4725 | } | |
4726 | ||
5ed2616f AA |
4727 | static u32 nv_get_rx_csum(struct net_device *dev) |
4728 | { | |
4729 | struct fe_priv *np = netdev_priv(dev); | |
f2ad2d9b | 4730 | return (np->rx_csum) != 0; |
5ed2616f AA |
4731 | } |
4732 | ||
4733 | static int nv_set_rx_csum(struct net_device *dev, u32 data) | |
4734 | { | |
4735 | struct fe_priv *np = netdev_priv(dev); | |
4736 | u8 __iomem *base = get_hwbase(dev); | |
4737 | int retcode = 0; | |
4738 | ||
4739 | if (np->driver_data & DEV_HAS_CHECKSUM) { | |
5ed2616f | 4740 | if (data) { |
f2ad2d9b | 4741 | np->rx_csum = 1; |
5ed2616f | 4742 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5ed2616f | 4743 | } else { |
f2ad2d9b AA |
4744 | np->rx_csum = 0; |
4745 | /* vlan is dependent on rx checksum offload */ | |
4746 | if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) | |
4747 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4748 | } |
5ed2616f AA |
4749 | if (netif_running(dev)) { |
4750 | spin_lock_irq(&np->lock); | |
4751 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
4752 | spin_unlock_irq(&np->lock); | |
4753 | } | |
4754 | } else { | |
4755 | return -EINVAL; | |
4756 | } | |
4757 | ||
4758 | return retcode; | |
4759 | } | |
4760 | ||
4761 | static int nv_set_tx_csum(struct net_device *dev, u32 data) | |
4762 | { | |
4763 | struct fe_priv *np = netdev_priv(dev); | |
4764 | ||
4765 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4766 | return ethtool_op_set_tx_hw_csum(dev, data); | |
4767 | else | |
4768 | return -EOPNOTSUPP; | |
4769 | } | |
4770 | ||
4771 | static int nv_set_sg(struct net_device *dev, u32 data) | |
4772 | { | |
4773 | struct fe_priv *np = netdev_priv(dev); | |
4774 | ||
4775 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4776 | return ethtool_op_set_sg(dev, data); | |
4777 | else | |
4778 | return -EOPNOTSUPP; | |
4779 | } | |
4780 | ||
b9f2c044 | 4781 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4782 | { |
4783 | struct fe_priv *np = netdev_priv(dev); | |
4784 | ||
b9f2c044 JG |
4785 | switch (sset) { |
4786 | case ETH_SS_TEST: | |
4787 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4788 | return NV_TEST_COUNT_EXTENDED; | |
4789 | else | |
4790 | return NV_TEST_COUNT_BASE; | |
4791 | case ETH_SS_STATS: | |
4792 | if (np->driver_data & DEV_HAS_STATISTICS_V1) | |
4793 | return NV_DEV_STATISTICS_V1_COUNT; | |
4794 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) | |
4795 | return NV_DEV_STATISTICS_V2_COUNT; | |
9c662435 AA |
4796 | else if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4797 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4798 | else |
4799 | return 0; | |
4800 | default: | |
4801 | return -EOPNOTSUPP; | |
4802 | } | |
52da3578 AA |
4803 | } |
4804 | ||
4805 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4806 | { | |
4807 | struct fe_priv *np = netdev_priv(dev); | |
4808 | ||
4809 | /* update stats */ | |
4810 | nv_do_stats_poll((unsigned long)dev); | |
4811 | ||
b9f2c044 | 4812 | memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); |
9589c77a AA |
4813 | } |
4814 | ||
4815 | static int nv_link_test(struct net_device *dev) | |
4816 | { | |
4817 | struct fe_priv *np = netdev_priv(dev); | |
4818 | int mii_status; | |
4819 | ||
4820 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4821 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4822 | ||
4823 | /* check phy link status */ | |
4824 | if (!(mii_status & BMSR_LSTATUS)) | |
4825 | return 0; | |
4826 | else | |
4827 | return 1; | |
4828 | } | |
4829 | ||
4830 | static int nv_register_test(struct net_device *dev) | |
4831 | { | |
4832 | u8 __iomem *base = get_hwbase(dev); | |
4833 | int i = 0; | |
4834 | u32 orig_read, new_read; | |
4835 | ||
4836 | do { | |
4837 | orig_read = readl(base + nv_registers_test[i].reg); | |
4838 | ||
4839 | /* xor with mask to toggle bits */ | |
4840 | orig_read ^= nv_registers_test[i].mask; | |
4841 | ||
4842 | writel(orig_read, base + nv_registers_test[i].reg); | |
4843 | ||
4844 | new_read = readl(base + nv_registers_test[i].reg); | |
4845 | ||
4846 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4847 | return 0; | |
4848 | ||
4849 | /* restore original value */ | |
4850 | orig_read ^= nv_registers_test[i].mask; | |
4851 | writel(orig_read, base + nv_registers_test[i].reg); | |
4852 | ||
4853 | } while (nv_registers_test[++i].reg != 0); | |
4854 | ||
4855 | return 1; | |
4856 | } | |
4857 | ||
4858 | static int nv_interrupt_test(struct net_device *dev) | |
4859 | { | |
4860 | struct fe_priv *np = netdev_priv(dev); | |
4861 | u8 __iomem *base = get_hwbase(dev); | |
4862 | int ret = 1; | |
4863 | int testcnt; | |
4864 | u32 save_msi_flags, save_poll_interval = 0; | |
4865 | ||
4866 | if (netif_running(dev)) { | |
4867 | /* free current irq */ | |
4868 | nv_free_irq(dev); | |
4869 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4870 | } | |
4871 | ||
4872 | /* flag to test interrupt handler */ | |
4873 | np->intr_test = 0; | |
4874 | ||
4875 | /* setup test irq */ | |
4876 | save_msi_flags = np->msi_flags; | |
4877 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4878 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4879 | if (nv_request_irq(dev, 1)) | |
4880 | return 0; | |
4881 | ||
4882 | /* setup timer interrupt */ | |
4883 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4884 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4885 | ||
4886 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4887 | ||
4888 | /* wait for at least one interrupt */ | |
4889 | msleep(100); | |
4890 | ||
4891 | spin_lock_irq(&np->lock); | |
4892 | ||
4893 | /* flag should be set within ISR */ | |
4894 | testcnt = np->intr_test; | |
4895 | if (!testcnt) | |
4896 | ret = 2; | |
4897 | ||
4898 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4899 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4900 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4901 | else | |
4902 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4903 | ||
4904 | spin_unlock_irq(&np->lock); | |
4905 | ||
4906 | nv_free_irq(dev); | |
4907 | ||
4908 | np->msi_flags = save_msi_flags; | |
4909 | ||
4910 | if (netif_running(dev)) { | |
4911 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4912 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4913 | /* restore original irq */ | |
4914 | if (nv_request_irq(dev, 0)) | |
4915 | return 0; | |
4916 | } | |
4917 | ||
4918 | return ret; | |
4919 | } | |
4920 | ||
4921 | static int nv_loopback_test(struct net_device *dev) | |
4922 | { | |
4923 | struct fe_priv *np = netdev_priv(dev); | |
4924 | u8 __iomem *base = get_hwbase(dev); | |
4925 | struct sk_buff *tx_skb, *rx_skb; | |
4926 | dma_addr_t test_dma_addr; | |
4927 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4928 | u32 flags; |
9589c77a AA |
4929 | int len, i, pkt_len; |
4930 | u8 *pkt_data; | |
4931 | u32 filter_flags = 0; | |
4932 | u32 misc1_flags = 0; | |
4933 | int ret = 1; | |
4934 | ||
4935 | if (netif_running(dev)) { | |
4936 | nv_disable_irq(dev); | |
4937 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4938 | misc1_flags = readl(base + NvRegMisc1); | |
4939 | } else { | |
4940 | nv_txrx_reset(dev); | |
4941 | } | |
4942 | ||
4943 | /* reinit driver view of the rx queue */ | |
4944 | set_bufsize(dev); | |
4945 | nv_init_ring(dev); | |
4946 | ||
4947 | /* setup hardware for loopback */ | |
4948 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4949 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4950 | ||
4951 | /* reinit nic view of the rx queue */ | |
4952 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4953 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4954 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4955 | base + NvRegRingSizes); | |
4956 | pci_push(base); | |
4957 | ||
4958 | /* restart rx engine */ | |
36b30ea9 | 4959 | nv_start_rxtx(dev); |
9589c77a AA |
4960 | |
4961 | /* setup packet for tx */ | |
4962 | pkt_len = ETH_DATA_LEN; | |
4963 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 JJ |
4964 | if (!tx_skb) { |
4965 | printk(KERN_ERR "dev_alloc_skb() failed during loopback test" | |
4966 | " of %s\n", dev->name); | |
4967 | ret = 0; | |
4968 | goto out; | |
4969 | } | |
8b5be268 ACM |
4970 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
4971 | skb_tailroom(tx_skb), | |
4972 | PCI_DMA_FROMDEVICE); | |
9589c77a AA |
4973 | pkt_data = skb_put(tx_skb, pkt_len); |
4974 | for (i = 0; i < pkt_len; i++) | |
4975 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 4976 | |
36b30ea9 | 4977 | if (!nv_optimized(np)) { |
f82a9352 SH |
4978 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4979 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4980 | } else { |
5bb7ea26 AV |
4981 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
4982 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 4983 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
4984 | } |
4985 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4986 | pci_push(get_hwbase(dev)); | |
4987 | ||
4988 | msleep(500); | |
4989 | ||
4990 | /* check for rx of the packet */ | |
36b30ea9 | 4991 | if (!nv_optimized(np)) { |
f82a9352 | 4992 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4993 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4994 | ||
4995 | } else { | |
f82a9352 | 4996 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4997 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4998 | } | |
4999 | ||
f82a9352 | 5000 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
5001 | ret = 0; |
5002 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 5003 | if (flags & NV_RX_ERROR) |
9589c77a AA |
5004 | ret = 0; |
5005 | } else { | |
f82a9352 | 5006 | if (flags & NV_RX2_ERROR) { |
9589c77a AA |
5007 | ret = 0; |
5008 | } | |
5009 | } | |
5010 | ||
5011 | if (ret) { | |
5012 | if (len != pkt_len) { | |
5013 | ret = 0; | |
5014 | dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", | |
5015 | dev->name, len, pkt_len); | |
5016 | } else { | |
761fcd9e | 5017 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
5018 | for (i = 0; i < pkt_len; i++) { |
5019 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
5020 | ret = 0; | |
5021 | dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", | |
5022 | dev->name, i); | |
5023 | break; | |
5024 | } | |
5025 | } | |
5026 | } | |
5027 | } else { | |
5028 | dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); | |
5029 | } | |
5030 | ||
5031 | pci_unmap_page(np->pci_dev, test_dma_addr, | |
4305b541 | 5032 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
5033 | PCI_DMA_TODEVICE); |
5034 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 5035 | out: |
9589c77a | 5036 | /* stop engines */ |
36b30ea9 | 5037 | nv_stop_rxtx(dev); |
9589c77a AA |
5038 | nv_txrx_reset(dev); |
5039 | /* drain rx queue */ | |
36b30ea9 | 5040 | nv_drain_rxtx(dev); |
9589c77a AA |
5041 | |
5042 | if (netif_running(dev)) { | |
5043 | writel(misc1_flags, base + NvRegMisc1); | |
5044 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
5045 | nv_enable_irq(dev); | |
5046 | } | |
5047 | ||
5048 | return ret; | |
5049 | } | |
5050 | ||
5051 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
5052 | { | |
5053 | struct fe_priv *np = netdev_priv(dev); | |
5054 | u8 __iomem *base = get_hwbase(dev); | |
5055 | int result; | |
b9f2c044 | 5056 | memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64)); |
9589c77a AA |
5057 | |
5058 | if (!nv_link_test(dev)) { | |
5059 | test->flags |= ETH_TEST_FL_FAILED; | |
5060 | buffer[0] = 1; | |
5061 | } | |
5062 | ||
5063 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
5064 | if (netif_running(dev)) { | |
5065 | netif_stop_queue(dev); | |
bea3348e SH |
5066 | #ifdef CONFIG_FORCEDETH_NAPI |
5067 | napi_disable(&np->napi); | |
5068 | #endif | |
58dfd9c1 | 5069 | netif_tx_lock_bh(dev); |
e308a5d8 | 5070 | netif_addr_lock(dev); |
9589c77a AA |
5071 | spin_lock_irq(&np->lock); |
5072 | nv_disable_hw_interrupts(dev, np->irqmask); | |
5073 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
5074 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
5075 | } else { | |
5076 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
5077 | } | |
5078 | /* stop engines */ | |
36b30ea9 | 5079 | nv_stop_rxtx(dev); |
9589c77a AA |
5080 | nv_txrx_reset(dev); |
5081 | /* drain rx queue */ | |
36b30ea9 | 5082 | nv_drain_rxtx(dev); |
9589c77a | 5083 | spin_unlock_irq(&np->lock); |
e308a5d8 | 5084 | netif_addr_unlock(dev); |
58dfd9c1 | 5085 | netif_tx_unlock_bh(dev); |
9589c77a AA |
5086 | } |
5087 | ||
5088 | if (!nv_register_test(dev)) { | |
5089 | test->flags |= ETH_TEST_FL_FAILED; | |
5090 | buffer[1] = 1; | |
5091 | } | |
5092 | ||
5093 | result = nv_interrupt_test(dev); | |
5094 | if (result != 1) { | |
5095 | test->flags |= ETH_TEST_FL_FAILED; | |
5096 | buffer[2] = 1; | |
5097 | } | |
5098 | if (result == 0) { | |
5099 | /* bail out */ | |
5100 | return; | |
5101 | } | |
5102 | ||
5103 | if (!nv_loopback_test(dev)) { | |
5104 | test->flags |= ETH_TEST_FL_FAILED; | |
5105 | buffer[3] = 1; | |
5106 | } | |
5107 | ||
5108 | if (netif_running(dev)) { | |
5109 | /* reinit driver view of the rx queue */ | |
5110 | set_bufsize(dev); | |
5111 | if (nv_init_ring(dev)) { | |
5112 | if (!np->in_shutdown) | |
5113 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
5114 | } | |
5115 | /* reinit nic view of the rx queue */ | |
5116 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
5117 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
5118 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
5119 | base + NvRegRingSizes); | |
5120 | pci_push(base); | |
5121 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5122 | pci_push(base); | |
5123 | /* restart rx engine */ | |
36b30ea9 | 5124 | nv_start_rxtx(dev); |
9589c77a | 5125 | netif_start_queue(dev); |
bea3348e SH |
5126 | #ifdef CONFIG_FORCEDETH_NAPI |
5127 | napi_enable(&np->napi); | |
5128 | #endif | |
9589c77a AA |
5129 | nv_enable_hw_interrupts(dev, np->irqmask); |
5130 | } | |
5131 | } | |
5132 | } | |
5133 | ||
52da3578 AA |
5134 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
5135 | { | |
5136 | switch (stringset) { | |
5137 | case ETH_SS_STATS: | |
b9f2c044 | 5138 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 5139 | break; |
9589c77a | 5140 | case ETH_SS_TEST: |
b9f2c044 | 5141 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 5142 | break; |
52da3578 AA |
5143 | } |
5144 | } | |
5145 | ||
7282d491 | 5146 | static const struct ethtool_ops ops = { |
1da177e4 LT |
5147 | .get_drvinfo = nv_get_drvinfo, |
5148 | .get_link = ethtool_op_get_link, | |
5149 | .get_wol = nv_get_wol, | |
5150 | .set_wol = nv_set_wol, | |
5151 | .get_settings = nv_get_settings, | |
5152 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
5153 | .get_regs_len = nv_get_regs_len, |
5154 | .get_regs = nv_get_regs, | |
5155 | .nway_reset = nv_nway_reset, | |
6a78814f | 5156 | .set_tso = nv_set_tso, |
eafa59f6 AA |
5157 | .get_ringparam = nv_get_ringparam, |
5158 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
5159 | .get_pauseparam = nv_get_pauseparam, |
5160 | .set_pauseparam = nv_set_pauseparam, | |
5ed2616f AA |
5161 | .get_rx_csum = nv_get_rx_csum, |
5162 | .set_rx_csum = nv_set_rx_csum, | |
5ed2616f | 5163 | .set_tx_csum = nv_set_tx_csum, |
5ed2616f | 5164 | .set_sg = nv_set_sg, |
52da3578 | 5165 | .get_strings = nv_get_strings, |
52da3578 | 5166 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 5167 | .get_sset_count = nv_get_sset_count, |
9589c77a | 5168 | .self_test = nv_self_test, |
1da177e4 LT |
5169 | }; |
5170 | ||
ee407b02 AA |
5171 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
5172 | { | |
5173 | struct fe_priv *np = get_nvpriv(dev); | |
5174 | ||
5175 | spin_lock_irq(&np->lock); | |
5176 | ||
5177 | /* save vlan group */ | |
5178 | np->vlangrp = grp; | |
5179 | ||
5180 | if (grp) { | |
5181 | /* enable vlan on MAC */ | |
5182 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
5183 | } else { | |
5184 | /* disable vlan on MAC */ | |
5185 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
5186 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
5187 | } | |
5188 | ||
5189 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5190 | ||
5191 | spin_unlock_irq(&np->lock); | |
25805dcf | 5192 | } |
ee407b02 | 5193 | |
7e680c22 AA |
5194 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
5195 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
5196 | { | |
cac1c52c | 5197 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
5198 | u8 __iomem *base = get_hwbase(dev); |
5199 | int i; | |
5200 | u32 tx_ctrl, mgmt_sema; | |
5201 | ||
5202 | for (i = 0; i < 10; i++) { | |
5203 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
5204 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5205 | break; | |
5206 | msleep(500); | |
5207 | } | |
5208 | ||
5209 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5210 | return 0; | |
5211 | ||
5212 | for (i = 0; i < 2; i++) { | |
5213 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5214 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5215 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5216 | ||
5217 | /* verify that semaphore was acquired */ | |
5218 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5219 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
5220 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5221 | np->mgmt_sema = 1; | |
7e680c22 | 5222 | return 1; |
cac1c52c | 5223 | } |
7e680c22 AA |
5224 | else |
5225 | udelay(50); | |
5226 | } | |
5227 | ||
5228 | return 0; | |
5229 | } | |
5230 | ||
cac1c52c AA |
5231 | static void nv_mgmt_release_sema(struct net_device *dev) |
5232 | { | |
5233 | struct fe_priv *np = netdev_priv(dev); | |
5234 | u8 __iomem *base = get_hwbase(dev); | |
5235 | u32 tx_ctrl; | |
5236 | ||
5237 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
5238 | if (np->mgmt_sema) { | |
5239 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5240 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5241 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5242 | } | |
5243 | } | |
5244 | } | |
5245 | ||
5246 | ||
5247 | static int nv_mgmt_get_version(struct net_device *dev) | |
5248 | { | |
5249 | struct fe_priv *np = netdev_priv(dev); | |
5250 | u8 __iomem *base = get_hwbase(dev); | |
5251 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
5252 | u32 data_ready2 = 0; | |
5253 | unsigned long start; | |
5254 | int ready = 0; | |
5255 | ||
5256 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
5257 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
5258 | start = jiffies; | |
5259 | while (time_before(jiffies, start + 5*HZ)) { | |
5260 | data_ready2 = readl(base + NvRegTransmitterControl); | |
5261 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
5262 | ready = 1; | |
5263 | break; | |
5264 | } | |
5265 | schedule_timeout_uninterruptible(1); | |
5266 | } | |
5267 | ||
5268 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
5269 | return 0; | |
5270 | ||
5271 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
5272 | ||
5273 | return 1; | |
5274 | } | |
5275 | ||
1da177e4 LT |
5276 | static int nv_open(struct net_device *dev) |
5277 | { | |
ac9c1897 | 5278 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 5279 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
5280 | int ret = 1; |
5281 | int oom, i; | |
a433686c | 5282 | u32 low; |
1da177e4 LT |
5283 | |
5284 | dprintk(KERN_DEBUG "nv_open: begin\n"); | |
5285 | ||
cb52deba ES |
5286 | /* power up phy */ |
5287 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5288 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
5289 | ||
f1489653 | 5290 | /* erase previous misconfiguration */ |
86a0f043 AA |
5291 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5292 | nv_mac_reset(dev); | |
1da177e4 LT |
5293 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5294 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5295 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5296 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5297 | writel(0, base + NvRegPacketFilterFlags); |
5298 | ||
5299 | writel(0, base + NvRegTransmitterControl); | |
5300 | writel(0, base + NvRegReceiverControl); | |
5301 | ||
5302 | writel(0, base + NvRegAdapterControl); | |
5303 | ||
eb91f61b AA |
5304 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5305 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5306 | ||
f1489653 | 5307 | /* initialize descriptor rings */ |
d81c0983 | 5308 | set_bufsize(dev); |
1da177e4 LT |
5309 | oom = nv_init_ring(dev); |
5310 | ||
5311 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5312 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5313 | nv_txrx_reset(dev); |
5314 | writel(0, base + NvRegUnknownSetupReg6); | |
5315 | ||
5316 | np->in_shutdown = 0; | |
5317 | ||
f1489653 | 5318 | /* give hw rings */ |
0832b25a | 5319 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 5320 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5321 | base + NvRegRingSizes); |
5322 | ||
1da177e4 | 5323 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5324 | if (np->desc_ver == DESC_VER_1) |
5325 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5326 | else | |
5327 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5328 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5329 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5330 | pci_push(base); |
8a4ae7f2 | 5331 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
5332 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
5333 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | |
5334 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | |
5335 | ||
7e680c22 | 5336 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5337 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5338 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5339 | |
1da177e4 LT |
5340 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5341 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5342 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5343 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5344 | |
5345 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5346 | |
5347 | get_random_bytes(&low, sizeof(low)); | |
5348 | low &= NVREG_SLOTTIME_MASK; | |
5349 | if (np->desc_ver == DESC_VER_1) { | |
5350 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5351 | } else { | |
5352 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5353 | /* setup legacy backoff */ | |
5354 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5355 | } else { | |
5356 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5357 | nv_gear_backoff_reseed(dev); | |
5358 | } | |
5359 | } | |
9744e218 AA |
5360 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5361 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5362 | if (poll_interval == -1) { |
5363 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5364 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5365 | else | |
5366 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
5367 | } | |
5368 | else | |
5369 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); | |
1da177e4 LT |
5370 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5371 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5372 | base + NvRegAdapterControl); | |
5373 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5374 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5375 | if (np->wolenabled) |
5376 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5377 | |
5378 | i = readl(base + NvRegPowerState); | |
5379 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) | |
5380 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); | |
5381 | ||
5382 | pci_push(base); | |
5383 | udelay(10); | |
5384 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5385 | ||
84b3932b | 5386 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5387 | pci_push(base); |
eb798428 | 5388 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5389 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5390 | pci_push(base); | |
5391 | ||
9589c77a | 5392 | if (nv_request_irq(dev, 0)) { |
84b3932b | 5393 | goto out_drain; |
d33a73c8 | 5394 | } |
1da177e4 LT |
5395 | |
5396 | /* ask for interrupts */ | |
84b3932b | 5397 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5398 | |
5399 | spin_lock_irq(&np->lock); | |
5400 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5401 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5402 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5403 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5404 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5405 | /* One manual link speed update: Interrupts are enabled, future link | |
5406 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5407 | */ | |
5408 | { | |
5409 | u32 miistat; | |
5410 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5411 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5412 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
5413 | } | |
1b1b3c9b MS |
5414 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5415 | * to init hw */ | |
5416 | np->linkspeed = 0; | |
1da177e4 | 5417 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5418 | nv_start_rxtx(dev); |
1da177e4 | 5419 | netif_start_queue(dev); |
bea3348e SH |
5420 | #ifdef CONFIG_FORCEDETH_NAPI |
5421 | napi_enable(&np->napi); | |
5422 | #endif | |
e27cdba5 | 5423 | |
1da177e4 LT |
5424 | if (ret) { |
5425 | netif_carrier_on(dev); | |
5426 | } else { | |
f7ab697d | 5427 | printk(KERN_INFO "%s: no link during initialization.\n", dev->name); |
1da177e4 LT |
5428 | netif_carrier_off(dev); |
5429 | } | |
5430 | if (oom) | |
5431 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5432 | |
5433 | /* start statistics timer */ | |
9c662435 | 5434 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5435 | mod_timer(&np->stats_poll, |
5436 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5437 | |
1da177e4 LT |
5438 | spin_unlock_irq(&np->lock); |
5439 | ||
5440 | return 0; | |
5441 | out_drain: | |
36b30ea9 | 5442 | nv_drain_rxtx(dev); |
1da177e4 LT |
5443 | return ret; |
5444 | } | |
5445 | ||
5446 | static int nv_close(struct net_device *dev) | |
5447 | { | |
ac9c1897 | 5448 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5449 | u8 __iomem *base; |
5450 | ||
5451 | spin_lock_irq(&np->lock); | |
5452 | np->in_shutdown = 1; | |
5453 | spin_unlock_irq(&np->lock); | |
bea3348e SH |
5454 | #ifdef CONFIG_FORCEDETH_NAPI |
5455 | napi_disable(&np->napi); | |
5456 | #endif | |
a7475906 | 5457 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5458 | |
5459 | del_timer_sync(&np->oom_kick); | |
5460 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5461 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5462 | |
5463 | netif_stop_queue(dev); | |
5464 | spin_lock_irq(&np->lock); | |
36b30ea9 | 5465 | nv_stop_rxtx(dev); |
1da177e4 LT |
5466 | nv_txrx_reset(dev); |
5467 | ||
5468 | /* disable interrupts on the nic or we will lock up */ | |
5469 | base = get_hwbase(dev); | |
84b3932b | 5470 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5471 | pci_push(base); |
5472 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | |
5473 | ||
5474 | spin_unlock_irq(&np->lock); | |
5475 | ||
84b3932b | 5476 | nv_free_irq(dev); |
1da177e4 | 5477 | |
36b30ea9 | 5478 | nv_drain_rxtx(dev); |
1da177e4 | 5479 | |
2cc49a5c TM |
5480 | if (np->wolenabled) { |
5481 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); | |
1da177e4 | 5482 | nv_start_rx(dev); |
cb52deba ES |
5483 | } else { |
5484 | /* power down phy */ | |
5485 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5486 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
2cc49a5c | 5487 | } |
1da177e4 LT |
5488 | |
5489 | /* FIXME: power down nic */ | |
5490 | ||
5491 | return 0; | |
5492 | } | |
5493 | ||
b94426bd SH |
5494 | static const struct net_device_ops nv_netdev_ops = { |
5495 | .ndo_open = nv_open, | |
5496 | .ndo_stop = nv_close, | |
5497 | .ndo_get_stats = nv_get_stats, | |
00829823 SH |
5498 | .ndo_start_xmit = nv_start_xmit, |
5499 | .ndo_tx_timeout = nv_tx_timeout, | |
5500 | .ndo_change_mtu = nv_change_mtu, | |
5501 | .ndo_validate_addr = eth_validate_addr, | |
5502 | .ndo_set_mac_address = nv_set_mac_address, | |
5503 | .ndo_set_multicast_list = nv_set_multicast, | |
5504 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5505 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5506 | .ndo_poll_controller = nv_poll_controller, | |
5507 | #endif | |
5508 | }; | |
5509 | ||
5510 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5511 | .ndo_open = nv_open, | |
5512 | .ndo_stop = nv_close, | |
5513 | .ndo_get_stats = nv_get_stats, | |
5514 | .ndo_start_xmit = nv_start_xmit_optimized, | |
b94426bd SH |
5515 | .ndo_tx_timeout = nv_tx_timeout, |
5516 | .ndo_change_mtu = nv_change_mtu, | |
5517 | .ndo_validate_addr = eth_validate_addr, | |
5518 | .ndo_set_mac_address = nv_set_mac_address, | |
5519 | .ndo_set_multicast_list = nv_set_multicast, | |
5520 | .ndo_vlan_rx_register = nv_vlan_rx_register, | |
5521 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5522 | .ndo_poll_controller = nv_poll_controller, | |
5523 | #endif | |
5524 | }; | |
5525 | ||
1da177e4 LT |
5526 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
5527 | { | |
5528 | struct net_device *dev; | |
5529 | struct fe_priv *np; | |
5530 | unsigned long addr; | |
5531 | u8 __iomem *base; | |
5532 | int err, i; | |
5070d340 | 5533 | u32 powerstate, txreg; |
7e680c22 AA |
5534 | u32 phystate_orig = 0, phystate; |
5535 | int phyinitialized = 0; | |
3f88ce49 JG |
5536 | static int printed_version; |
5537 | ||
5538 | if (!printed_version++) | |
5539 | printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" | |
5540 | " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); | |
1da177e4 LT |
5541 | |
5542 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5543 | err = -ENOMEM; | |
5544 | if (!dev) | |
5545 | goto out; | |
5546 | ||
ac9c1897 | 5547 | np = netdev_priv(dev); |
bea3348e | 5548 | np->dev = dev; |
1da177e4 LT |
5549 | np->pci_dev = pci_dev; |
5550 | spin_lock_init(&np->lock); | |
1da177e4 LT |
5551 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
5552 | ||
5553 | init_timer(&np->oom_kick); | |
5554 | np->oom_kick.data = (unsigned long) dev; | |
5555 | np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ | |
5556 | init_timer(&np->nic_poll); | |
5557 | np->nic_poll.data = (unsigned long) dev; | |
5558 | np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ | |
52da3578 AA |
5559 | init_timer(&np->stats_poll); |
5560 | np->stats_poll.data = (unsigned long) dev; | |
5561 | np->stats_poll.function = &nv_do_stats_poll; /* timer handler */ | |
1da177e4 LT |
5562 | |
5563 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5564 | if (err) |
1da177e4 | 5565 | goto out_free; |
1da177e4 LT |
5566 | |
5567 | pci_set_master(pci_dev); | |
5568 | ||
5569 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5570 | if (err < 0) | |
5571 | goto out_disable; | |
5572 | ||
9c662435 | 5573 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5574 | np->register_size = NV_PCI_REGSZ_VER3; |
5575 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5576 | np->register_size = NV_PCI_REGSZ_VER2; |
5577 | else | |
5578 | np->register_size = NV_PCI_REGSZ_VER1; | |
5579 | ||
1da177e4 LT |
5580 | err = -EINVAL; |
5581 | addr = 0; | |
5582 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
5583 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | |
5584 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), | |
5585 | pci_resource_len(pci_dev, i), | |
5586 | pci_resource_flags(pci_dev, i)); | |
5587 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | |
86a0f043 | 5588 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5589 | addr = pci_resource_start(pci_dev, i); |
5590 | break; | |
5591 | } | |
5592 | } | |
5593 | if (i == DEVICE_COUNT_RESOURCE) { | |
3f88ce49 JG |
5594 | dev_printk(KERN_INFO, &pci_dev->dev, |
5595 | "Couldn't find register window\n"); | |
1da177e4 LT |
5596 | goto out_relreg; |
5597 | } | |
5598 | ||
86a0f043 AA |
5599 | /* copy of driver data */ |
5600 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5601 | /* copy of device id */ |
5602 | np->device_id = id->device; | |
86a0f043 | 5603 | |
1da177e4 | 5604 | /* handle different descriptor versions */ |
ee73362c MS |
5605 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5606 | /* packet format 3: supports 40-bit addressing */ | |
5607 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5608 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5609 | if (dma_64bit) { |
3f88ce49 JG |
5610 | if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) |
5611 | dev_printk(KERN_INFO, &pci_dev->dev, | |
5612 | "64-bit DMA failed, using 32-bit addressing\n"); | |
5613 | else | |
69fe3fd7 | 5614 | dev->features |= NETIF_F_HIGHDMA; |
69fe3fd7 | 5615 | if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
3f88ce49 JG |
5616 | dev_printk(KERN_INFO, &pci_dev->dev, |
5617 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5618 | } |
ee73362c MS |
5619 | } |
5620 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5621 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5622 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5623 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5624 | } else { |
5625 | /* original packet format */ | |
5626 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5627 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5628 | } |
ee73362c MS |
5629 | |
5630 | np->pkt_limit = NV_PKTLIMIT_1; | |
5631 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5632 | np->pkt_limit = NV_PKTLIMIT_2; | |
5633 | ||
8a4ae7f2 | 5634 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
f2ad2d9b | 5635 | np->rx_csum = 1; |
8a4ae7f2 | 5636 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
edcfe5f7 | 5637 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
fa45459e | 5638 | dev->features |= NETIF_F_TSO; |
21828163 | 5639 | } |
8a4ae7f2 | 5640 | |
ee407b02 AA |
5641 | np->vlanctl_bits = 0; |
5642 | if (id->driver_data & DEV_HAS_VLAN) { | |
5643 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
5644 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
ee407b02 AA |
5645 | } |
5646 | ||
d33a73c8 | 5647 | np->msi_flags = 0; |
69fe3fd7 | 5648 | if ((id->driver_data & DEV_HAS_MSI) && msi) { |
d33a73c8 AA |
5649 | np->msi_flags |= NV_MSI_CAPABLE; |
5650 | } | |
69fe3fd7 | 5651 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
d33a73c8 AA |
5652 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5653 | } | |
5654 | ||
b6d0773f | 5655 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5656 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5657 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5658 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5659 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5660 | } |
f3b197ac | 5661 | |
eb91f61b | 5662 | |
1da177e4 | 5663 | err = -ENOMEM; |
86a0f043 | 5664 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5665 | if (!np->base) |
5666 | goto out_relreg; | |
5667 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 5668 | |
1da177e4 | 5669 | dev->irq = pci_dev->irq; |
ee73362c | 5670 | |
eafa59f6 AA |
5671 | np->rx_ring_size = RX_RING_DEFAULT; |
5672 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5673 | |
36b30ea9 | 5674 | if (!nv_optimized(np)) { |
ee73362c | 5675 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5676 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5677 | &np->ring_addr); |
5678 | if (!np->rx_ring.orig) | |
5679 | goto out_unmap; | |
eafa59f6 | 5680 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5681 | } else { |
5682 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5683 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5684 | &np->ring_addr); |
5685 | if (!np->rx_ring.ex) | |
5686 | goto out_unmap; | |
eafa59f6 AA |
5687 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5688 | } | |
dd00cc48 YP |
5689 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5690 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5691 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5692 | goto out_freering; |
1da177e4 | 5693 | |
36b30ea9 | 5694 | if (!nv_optimized(np)) |
00829823 | 5695 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5696 | else |
00829823 | 5697 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5698 | |
e27cdba5 | 5699 | #ifdef CONFIG_FORCEDETH_NAPI |
bea3348e | 5700 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
2918c35d | 5701 | #endif |
1da177e4 | 5702 | SET_ETHTOOL_OPS(dev, &ops); |
1da177e4 LT |
5703 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5704 | ||
5705 | pci_set_drvdata(pci_dev, dev); | |
5706 | ||
5707 | /* read the mac address */ | |
5708 | base = get_hwbase(dev); | |
5709 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5710 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5711 | ||
5070d340 AA |
5712 | /* check the workaround bit for correct mac address order */ |
5713 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5714 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5715 | /* mac address is already in correct order */ |
5716 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5717 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5718 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5719 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5720 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5721 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5722 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5723 | /* mac address is already in correct order */ | |
5724 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5725 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5726 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5727 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5728 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5729 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5730 | /* | |
5731 | * Set orig mac address back to the reversed version. | |
5732 | * This flag will be cleared during low power transition. | |
5733 | * Therefore, we should always put back the reversed address. | |
5734 | */ | |
5735 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5736 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5737 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5738 | } else { |
5739 | /* need to reverse mac address to correct order */ | |
5740 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5741 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5742 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5743 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5744 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5745 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5746 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
f55c21fd | 5747 | printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n"); |
5070d340 | 5748 | } |
c704b856 | 5749 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5750 | |
c704b856 | 5751 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5752 | /* |
5753 | * Bad mac address. At least one bios sets the mac address | |
5754 | * to 01:23:45:67:89:ab | |
5755 | */ | |
3f88ce49 | 5756 | dev_printk(KERN_ERR, &pci_dev->dev, |
e174961c JB |
5757 | "Invalid Mac address detected: %pM\n", |
5758 | dev->dev_addr); | |
3f88ce49 JG |
5759 | dev_printk(KERN_ERR, &pci_dev->dev, |
5760 | "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
1da177e4 LT |
5761 | dev->dev_addr[0] = 0x00; |
5762 | dev->dev_addr[1] = 0x00; | |
5763 | dev->dev_addr[2] = 0x6c; | |
5764 | get_random_bytes(&dev->dev_addr[3], 3); | |
5765 | } | |
5766 | ||
e174961c JB |
5767 | dprintk(KERN_DEBUG "%s: MAC Address %pM\n", |
5768 | pci_name(pci_dev), dev->dev_addr); | |
1da177e4 | 5769 | |
f1489653 AA |
5770 | /* set mac address */ |
5771 | nv_copy_mac_to_hw(dev); | |
5772 | ||
9a60a826 TD |
5773 | /* Workaround current PCI init glitch: wakeup bits aren't |
5774 | * being set from PCI PM capability. | |
5775 | */ | |
5776 | device_init_wakeup(&pci_dev->dev, 1); | |
5777 | ||
1da177e4 LT |
5778 | /* disable WOL */ |
5779 | writel(0, base + NvRegWakeUpFlags); | |
5780 | np->wolenabled = 0; | |
5781 | ||
86a0f043 | 5782 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5783 | |
5784 | /* take phy and nic out of low power mode */ | |
5785 | powerstate = readl(base + NvRegPowerState2); | |
5786 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
5787 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || | |
5788 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && | |
44c10138 | 5789 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5790 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5791 | writel(powerstate, base + NvRegPowerState2); | |
5792 | } | |
5793 | ||
1da177e4 | 5794 | if (np->desc_ver == DESC_VER_1) { |
ac9c1897 | 5795 | np->tx_flags = NV_TX_VALID; |
1da177e4 | 5796 | } else { |
ac9c1897 | 5797 | np->tx_flags = NV_TX2_VALID; |
1da177e4 | 5798 | } |
d33a73c8 | 5799 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
a971c324 | 5800 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
d33a73c8 AA |
5801 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5802 | np->msi_flags |= 0x0003; | |
5803 | } else { | |
a971c324 | 5804 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5805 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5806 | np->msi_flags |= 0x0001; | |
5807 | } | |
a971c324 | 5808 | |
1da177e4 LT |
5809 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5810 | np->irqmask |= NVREG_IRQ_TIMER; | |
5811 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
5812 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | |
5813 | np->need_linktimer = 1; | |
5814 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5815 | } else { | |
5816 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | |
5817 | np->need_linktimer = 0; | |
5818 | } | |
5819 | ||
3b446c3e AA |
5820 | /* Limit the number of tx's outstanding for hw bug */ |
5821 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5822 | np->tx_limit = 1; | |
5823 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 || | |
5824 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 || | |
5825 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 || | |
5826 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 || | |
5827 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 || | |
5828 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 || | |
5829 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 || | |
5830 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) && | |
5831 | pci_dev->revision >= 0xA2) | |
5832 | np->tx_limit = 0; | |
5833 | } | |
5834 | ||
7e680c22 AA |
5835 | /* clear phy state and temporarily halt phy interrupts */ |
5836 | writel(0, base + NvRegMIIMask); | |
5837 | phystate = readl(base + NvRegAdapterControl); | |
5838 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5839 | phystate_orig = 1; | |
5840 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5841 | writel(phystate, base + NvRegAdapterControl); | |
5842 | } | |
eb798428 | 5843 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5844 | |
5845 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5846 | /* management unit running on the mac? */ |
cac1c52c AA |
5847 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5848 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5849 | nv_mgmt_acquire_sema(dev) && | |
5850 | nv_mgmt_get_version(dev)) { | |
5851 | np->mac_in_use = 1; | |
5852 | if (np->mgmt_version > 0) { | |
5853 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; | |
5854 | } | |
5855 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", | |
5856 | pci_name(pci_dev), np->mac_in_use); | |
5857 | /* management unit setup the phy already? */ | |
5858 | if (np->mac_in_use && | |
5859 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5860 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5861 | /* phy is inited by mgmt unit */ | |
5862 | phyinitialized = 1; | |
5863 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", | |
5864 | pci_name(pci_dev)); | |
5865 | } else { | |
5866 | /* we need to init the phy */ | |
7e680c22 AA |
5867 | } |
5868 | } | |
5869 | } | |
5870 | ||
1da177e4 | 5871 | /* find a suitable phy */ |
7a33e45a | 5872 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5873 | int id1, id2; |
7a33e45a | 5874 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5875 | |
5876 | spin_lock_irq(&np->lock); | |
7a33e45a | 5877 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5878 | spin_unlock_irq(&np->lock); |
5879 | if (id1 < 0 || id1 == 0xffff) | |
5880 | continue; | |
5881 | spin_lock_irq(&np->lock); | |
7a33e45a | 5882 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5883 | spin_unlock_irq(&np->lock); |
5884 | if (id2 < 0 || id2 == 0xffff) | |
5885 | continue; | |
5886 | ||
edf7e5ec | 5887 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5888 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5889 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
5890 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | |
7a33e45a AA |
5891 | pci_name(pci_dev), id1, id2, phyaddr); |
5892 | np->phyaddr = phyaddr; | |
1da177e4 | 5893 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5894 | |
5895 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5896 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5897 | np->phy_oui = PHY_OUI_REALTEK; | |
5898 | /* Setup phy revision for Realtek */ | |
5899 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5900 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5901 | ||
1da177e4 LT |
5902 | break; |
5903 | } | |
7a33e45a | 5904 | if (i == 33) { |
3f88ce49 JG |
5905 | dev_printk(KERN_INFO, &pci_dev->dev, |
5906 | "open: Could not find a valid PHY.\n"); | |
eafa59f6 | 5907 | goto out_error; |
1da177e4 | 5908 | } |
f3b197ac | 5909 | |
7e680c22 AA |
5910 | if (!phyinitialized) { |
5911 | /* reset it */ | |
5912 | phy_init(dev); | |
f35723ec AA |
5913 | } else { |
5914 | /* see if it is a gigabit phy */ | |
5915 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
5916 | if (mii_status & PHY_GIGABIT) { | |
5917 | np->gigabit = PHY_GIGABIT; | |
5918 | } | |
7e680c22 | 5919 | } |
1da177e4 LT |
5920 | |
5921 | /* set default link speed settings */ | |
5922 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5923 | np->duplex = 0; | |
5924 | np->autoneg = 1; | |
5925 | ||
5926 | err = register_netdev(dev); | |
5927 | if (err) { | |
3f88ce49 JG |
5928 | dev_printk(KERN_INFO, &pci_dev->dev, |
5929 | "unable to register netdev: %d\n", err); | |
eafa59f6 | 5930 | goto out_error; |
1da177e4 | 5931 | } |
3f88ce49 JG |
5932 | |
5933 | dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " | |
5934 | "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", | |
5935 | dev->name, | |
5936 | np->phy_oui, | |
5937 | np->phyaddr, | |
5938 | dev->dev_addr[0], | |
5939 | dev->dev_addr[1], | |
5940 | dev->dev_addr[2], | |
5941 | dev->dev_addr[3], | |
5942 | dev->dev_addr[4], | |
5943 | dev->dev_addr[5]); | |
5944 | ||
5945 | dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | |
5946 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", | |
edcfe5f7 | 5947 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? |
3f88ce49 JG |
5948 | "csum " : "", |
5949 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? | |
5950 | "vlan " : "", | |
5951 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", | |
5952 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
5953 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5954 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
5955 | np->need_linktimer ? "lnktim " : "", | |
5956 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
5957 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
5958 | np->desc_ver); | |
1da177e4 LT |
5959 | |
5960 | return 0; | |
5961 | ||
eafa59f6 | 5962 | out_error: |
7e680c22 AA |
5963 | if (phystate_orig) |
5964 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5965 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5966 | out_freering: |
5967 | free_rings(dev); | |
1da177e4 LT |
5968 | out_unmap: |
5969 | iounmap(get_hwbase(dev)); | |
5970 | out_relreg: | |
5971 | pci_release_regions(pci_dev); | |
5972 | out_disable: | |
5973 | pci_disable_device(pci_dev); | |
5974 | out_free: | |
5975 | free_netdev(dev); | |
5976 | out: | |
5977 | return err; | |
5978 | } | |
5979 | ||
9f3f7910 AA |
5980 | static void nv_restore_phy(struct net_device *dev) |
5981 | { | |
5982 | struct fe_priv *np = netdev_priv(dev); | |
5983 | u16 phy_reserved, mii_control; | |
5984 | ||
5985 | if (np->phy_oui == PHY_OUI_REALTEK && | |
5986 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
5987 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
5988 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
5989 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
5990 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
5991 | phy_reserved |= PHY_REALTEK_INIT8; | |
5992 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
5993 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
5994 | ||
5995 | /* restart auto negotiation */ | |
5996 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
5997 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
5998 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
5999 | } | |
6000 | } | |
6001 | ||
f55c21fd | 6002 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
6003 | { |
6004 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
6005 | struct fe_priv *np = netdev_priv(dev); |
6006 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 6007 | |
f1489653 AA |
6008 | /* special op: write back the misordered MAC address - otherwise |
6009 | * the next nv_probe would see a wrong address. | |
6010 | */ | |
6011 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
6012 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |
2e3884b5 BS |
6013 | writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, |
6014 | base + NvRegTransmitPoll); | |
f55c21fd YL |
6015 | } |
6016 | ||
6017 | static void __devexit nv_remove(struct pci_dev *pci_dev) | |
6018 | { | |
6019 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
6020 | ||
6021 | unregister_netdev(dev); | |
6022 | ||
6023 | nv_restore_mac_addr(pci_dev); | |
f1489653 | 6024 | |
9f3f7910 AA |
6025 | /* restore any phy related changes */ |
6026 | nv_restore_phy(dev); | |
6027 | ||
cac1c52c AA |
6028 | nv_mgmt_release_sema(dev); |
6029 | ||
1da177e4 | 6030 | /* free all structures */ |
eafa59f6 | 6031 | free_rings(dev); |
1da177e4 LT |
6032 | iounmap(get_hwbase(dev)); |
6033 | pci_release_regions(pci_dev); | |
6034 | pci_disable_device(pci_dev); | |
6035 | free_netdev(dev); | |
6036 | pci_set_drvdata(pci_dev, NULL); | |
6037 | } | |
6038 | ||
a189317f FR |
6039 | #ifdef CONFIG_PM |
6040 | static int nv_suspend(struct pci_dev *pdev, pm_message_t state) | |
6041 | { | |
6042 | struct net_device *dev = pci_get_drvdata(pdev); | |
6043 | struct fe_priv *np = netdev_priv(dev); | |
1a1ca861 TD |
6044 | u8 __iomem *base = get_hwbase(dev); |
6045 | int i; | |
a189317f | 6046 | |
25d90810 TD |
6047 | if (netif_running(dev)) { |
6048 | // Gross. | |
6049 | nv_close(dev); | |
6050 | } | |
a189317f FR |
6051 | netif_device_detach(dev); |
6052 | ||
1a1ca861 TD |
6053 | /* save non-pci configuration space */ |
6054 | for (i = 0;i <= np->register_size/sizeof(u32); i++) | |
6055 | np->saved_config_space[i] = readl(base + i*sizeof(u32)); | |
6056 | ||
a189317f FR |
6057 | pci_save_state(pdev); |
6058 | pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled); | |
25d90810 | 6059 | pci_disable_device(pdev); |
a189317f | 6060 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
a189317f FR |
6061 | return 0; |
6062 | } | |
6063 | ||
6064 | static int nv_resume(struct pci_dev *pdev) | |
6065 | { | |
6066 | struct net_device *dev = pci_get_drvdata(pdev); | |
1a1ca861 | 6067 | struct fe_priv *np = netdev_priv(dev); |
a376e79c | 6068 | u8 __iomem *base = get_hwbase(dev); |
1a1ca861 | 6069 | int i, rc = 0; |
a189317f | 6070 | |
a189317f FR |
6071 | pci_set_power_state(pdev, PCI_D0); |
6072 | pci_restore_state(pdev); | |
25d90810 | 6073 | /* ack any pending wake events, disable PME */ |
a189317f FR |
6074 | pci_enable_wake(pdev, PCI_D0, 0); |
6075 | ||
1a1ca861 TD |
6076 | /* restore non-pci configuration space */ |
6077 | for (i = 0;i <= np->register_size/sizeof(u32); i++) | |
6078 | writel(np->saved_config_space[i], base+i*sizeof(u32)); | |
a376e79c | 6079 | |
b6e4405b AA |
6080 | pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE); |
6081 | ||
25d90810 TD |
6082 | netif_device_attach(dev); |
6083 | if (netif_running(dev)) { | |
6084 | rc = nv_open(dev); | |
6085 | nv_set_multicast(dev); | |
6086 | } | |
a189317f FR |
6087 | return rc; |
6088 | } | |
f735a2a1 TD |
6089 | |
6090 | static void nv_shutdown(struct pci_dev *pdev) | |
6091 | { | |
6092 | struct net_device *dev = pci_get_drvdata(pdev); | |
6093 | struct fe_priv *np = netdev_priv(dev); | |
6094 | ||
6095 | if (netif_running(dev)) | |
6096 | nv_close(dev); | |
6097 | ||
f55c21fd YL |
6098 | nv_restore_mac_addr(pdev); |
6099 | ||
f735a2a1 | 6100 | pci_disable_device(pdev); |
3cb5599a RW |
6101 | if (system_state == SYSTEM_POWER_OFF) { |
6102 | if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled)) | |
6103 | pci_enable_wake(pdev, PCI_D3hot, np->wolenabled); | |
6104 | pci_set_power_state(pdev, PCI_D3hot); | |
6105 | } | |
f735a2a1 | 6106 | } |
a189317f FR |
6107 | #else |
6108 | #define nv_suspend NULL | |
f735a2a1 | 6109 | #define nv_shutdown NULL |
a189317f FR |
6110 | #define nv_resume NULL |
6111 | #endif /* CONFIG_PM */ | |
6112 | ||
1da177e4 LT |
6113 | static struct pci_device_id pci_tbl[] = { |
6114 | { /* nForce Ethernet Controller */ | |
dc8216c1 | 6115 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
c2dba06d | 6116 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6117 | }, |
6118 | { /* nForce2 Ethernet Controller */ | |
dc8216c1 | 6119 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
c2dba06d | 6120 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6121 | }, |
6122 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 6123 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
c2dba06d | 6124 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
6125 | }, |
6126 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 6127 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
8a4ae7f2 | 6128 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6129 | }, |
6130 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 6131 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
8a4ae7f2 | 6132 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6133 | }, |
6134 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 6135 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
8a4ae7f2 | 6136 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6137 | }, |
6138 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 6139 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
8a4ae7f2 | 6140 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
6141 | }, |
6142 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 6143 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
033e97b2 | 6144 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6145 | }, |
6146 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 6147 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
033e97b2 | 6148 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6149 | }, |
6150 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 6151 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
3b446c3e | 6152 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
6153 | }, |
6154 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 6155 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
3b446c3e | 6156 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 | 6157 | }, |
9992d4aa | 6158 | { /* MCP51 Ethernet Controller */ |
dc8216c1 | 6159 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
57fff698 | 6160 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, |
9992d4aa MS |
6161 | }, |
6162 | { /* MCP51 Ethernet Controller */ | |
dc8216c1 | 6163 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
57fff698 | 6164 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, |
9992d4aa | 6165 | }, |
f49d16ef | 6166 | { /* MCP55 Ethernet Controller */ |
dc8216c1 | 6167 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
033e97b2 | 6168 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, |
f49d16ef MS |
6169 | }, |
6170 | { /* MCP55 Ethernet Controller */ | |
dc8216c1 | 6171 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
033e97b2 | 6172 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, |
f49d16ef | 6173 | }, |
c99ce7ee AA |
6174 | { /* MCP61 Ethernet Controller */ |
6175 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), | |
5289b4c4 | 6176 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
6177 | }, |
6178 | { /* MCP61 Ethernet Controller */ | |
6179 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), | |
5289b4c4 | 6180 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
6181 | }, |
6182 | { /* MCP61 Ethernet Controller */ | |
6183 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), | |
5289b4c4 | 6184 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
6185 | }, |
6186 | { /* MCP61 Ethernet Controller */ | |
6187 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), | |
5289b4c4 | 6188 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
6189 | }, |
6190 | { /* MCP65 Ethernet Controller */ | |
6191 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), | |
a433686c | 6192 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
6193 | }, |
6194 | { /* MCP65 Ethernet Controller */ | |
6195 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), | |
a433686c | 6196 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
6197 | }, |
6198 | { /* MCP65 Ethernet Controller */ | |
6199 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), | |
a433686c | 6200 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
6201 | }, |
6202 | { /* MCP65 Ethernet Controller */ | |
6203 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), | |
a433686c | 6204 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee | 6205 | }, |
f4344848 AA |
6206 | { /* MCP67 Ethernet Controller */ |
6207 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), | |
a433686c | 6208 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
6209 | }, |
6210 | { /* MCP67 Ethernet Controller */ | |
6211 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), | |
a433686c | 6212 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
6213 | }, |
6214 | { /* MCP67 Ethernet Controller */ | |
6215 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), | |
a433686c | 6216 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
6217 | }, |
6218 | { /* MCP67 Ethernet Controller */ | |
6219 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), | |
a433686c | 6220 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 | 6221 | }, |
1398661b AA |
6222 | { /* MCP73 Ethernet Controller */ |
6223 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), | |
a433686c | 6224 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
6225 | }, |
6226 | { /* MCP73 Ethernet Controller */ | |
6227 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), | |
a433686c | 6228 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
6229 | }, |
6230 | { /* MCP73 Ethernet Controller */ | |
6231 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), | |
a433686c | 6232 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
6233 | }, |
6234 | { /* MCP73 Ethernet Controller */ | |
6235 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), | |
a433686c | 6236 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b | 6237 | }, |
96fd4cd3 AA |
6238 | { /* MCP77 Ethernet Controller */ |
6239 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), | |
9c662435 | 6240 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
6241 | }, |
6242 | { /* MCP77 Ethernet Controller */ | |
6243 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), | |
9c662435 | 6244 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
6245 | }, |
6246 | { /* MCP77 Ethernet Controller */ | |
6247 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), | |
9c662435 | 6248 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
6249 | }, |
6250 | { /* MCP77 Ethernet Controller */ | |
6251 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), | |
9c662435 | 6252 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 | 6253 | }, |
490dde89 AA |
6254 | { /* MCP79 Ethernet Controller */ |
6255 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), | |
a7ee2f73 | 6256 | .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
6257 | }, |
6258 | { /* MCP79 Ethernet Controller */ | |
6259 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), | |
a7ee2f73 | 6260 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
6261 | }, |
6262 | { /* MCP79 Ethernet Controller */ | |
6263 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), | |
a7ee2f73 | 6264 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
6265 | }, |
6266 | { /* MCP79 Ethernet Controller */ | |
6267 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), | |
a7ee2f73 | 6268 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V3|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 | 6269 | }, |
1da177e4 LT |
6270 | {0,}, |
6271 | }; | |
6272 | ||
6273 | static struct pci_driver driver = { | |
3f88ce49 JG |
6274 | .name = DRV_NAME, |
6275 | .id_table = pci_tbl, | |
6276 | .probe = nv_probe, | |
6277 | .remove = __devexit_p(nv_remove), | |
6278 | .suspend = nv_suspend, | |
6279 | .resume = nv_resume, | |
f735a2a1 | 6280 | .shutdown = nv_shutdown, |
1da177e4 LT |
6281 | }; |
6282 | ||
1da177e4 LT |
6283 | static int __init init_nic(void) |
6284 | { | |
29917620 | 6285 | return pci_register_driver(&driver); |
1da177e4 LT |
6286 | } |
6287 | ||
6288 | static void __exit exit_nic(void) | |
6289 | { | |
6290 | pci_unregister_driver(&driver); | |
6291 | } | |
6292 | ||
6293 | module_param(max_interrupt_work, int, 0); | |
6294 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); | |
a971c324 AA |
6295 | module_param(optimization_mode, int, 0); |
6296 | MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); | |
6297 | module_param(poll_interval, int, 0); | |
6298 | MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); | |
69fe3fd7 AA |
6299 | module_param(msi, int, 0); |
6300 | MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
6301 | module_param(msix, int, 0); | |
6302 | MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
6303 | module_param(dma_64bit, int, 0); | |
6304 | MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); | |
9f3f7910 AA |
6305 | module_param(phy_cross, int, 0); |
6306 | MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0."); | |
1da177e4 LT |
6307 | |
6308 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); | |
6309 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); | |
6310 | MODULE_LICENSE("GPL"); | |
6311 | ||
6312 | MODULE_DEVICE_TABLE(pci, pci_tbl); | |
6313 | ||
6314 | module_init(init_nic); | |
6315 | module_exit(exit_nic); |