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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f648d129 | 16 | * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
1da177e4 LT |
32 | * Known bugs: |
33 | * We suspect that on some hardware no TX done interrupts are generated. | |
34 | * This means recovery from netif_stop_queue only happens if the hw timer | |
35 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
36 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
37 | * If your hardware reliably generates tx done interrupts, then you can remove | |
38 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
39 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
40 | * superfluous timer interrupts from the nic. | |
41 | */ | |
8148ff45 | 42 | #define FORCEDETH_VERSION "0.61" |
1da177e4 LT |
43 | #define DRV_NAME "forcedeth" |
44 | ||
45 | #include <linux/module.h> | |
46 | #include <linux/types.h> | |
47 | #include <linux/pci.h> | |
48 | #include <linux/interrupt.h> | |
49 | #include <linux/netdevice.h> | |
50 | #include <linux/etherdevice.h> | |
51 | #include <linux/delay.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/ethtool.h> | |
54 | #include <linux/timer.h> | |
55 | #include <linux/skbuff.h> | |
56 | #include <linux/mii.h> | |
57 | #include <linux/random.h> | |
58 | #include <linux/init.h> | |
22c6d143 | 59 | #include <linux/if_vlan.h> |
910638ae | 60 | #include <linux/dma-mapping.h> |
1da177e4 LT |
61 | |
62 | #include <asm/irq.h> | |
63 | #include <asm/io.h> | |
64 | #include <asm/uaccess.h> | |
65 | #include <asm/system.h> | |
66 | ||
67 | #if 0 | |
68 | #define dprintk printk | |
69 | #else | |
70 | #define dprintk(x...) do { } while (0) | |
71 | #endif | |
72 | ||
bea3348e SH |
73 | #define TX_WORK_PER_LOOP 64 |
74 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
75 | |
76 | /* | |
77 | * Hardware access: | |
78 | */ | |
79 | ||
5289b4c4 AA |
80 | #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */ |
81 | #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */ | |
82 | #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */ | |
83 | #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */ | |
84 | #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */ | |
85 | #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */ | |
86 | #define DEV_HAS_MSI 0x00040 /* device supports MSI */ | |
87 | #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */ | |
88 | #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */ | |
89 | #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */ | |
90 | #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */ | |
91 | #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */ | |
92 | #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */ | |
93 | #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */ | |
94 | #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */ | |
95 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */ | |
96 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ | |
3b446c3e | 98 | #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ |
a433686c | 99 | #define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */ |
1da177e4 LT |
100 | |
101 | enum { | |
102 | NvRegIrqStatus = 0x000, | |
103 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
c5cf9101 | 104 | #define NVREG_IRQSTAT_MASK 0x81ff |
1da177e4 LT |
105 | NvRegIrqMask = 0x004, |
106 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
107 | #define NVREG_IRQ_RX 0x0002 | |
108 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
109 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 110 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
111 | #define NVREG_IRQ_TIMER 0x0020 |
112 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
113 | #define NVREG_IRQ_RX_FORCED 0x0080 |
114 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
c5cf9101 | 115 | #define NVREG_IRQ_RECOVER_ERROR 0x8000 |
a971c324 | 116 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 117 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
118 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
119 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 120 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d MS |
121 | |
122 | #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ | |
d33a73c8 | 123 | NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
c5cf9101 | 124 | NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR)) |
1da177e4 LT |
125 | |
126 | NvRegUnknownSetupReg6 = 0x008, | |
127 | #define NVREG_UNKSETUP6_VAL 3 | |
128 | ||
129 | /* | |
130 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
131 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
132 | */ | |
133 | NvRegPollingInterval = 0x00c, | |
4e16ed1b | 134 | #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */ |
a971c324 | 135 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
136 | NvRegMSIMap0 = 0x020, |
137 | NvRegMSIMap1 = 0x024, | |
138 | NvRegMSIIrqMask = 0x030, | |
139 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 140 | NvRegMisc1 = 0x080, |
eb91f61b | 141 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
142 | #define NVREG_MISC1_HD 0x02 |
143 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
144 | ||
0a62677b | 145 | NvRegMacReset = 0x34, |
86a0f043 | 146 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
147 | NvRegTransmitterControl = 0x084, |
148 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
149 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
150 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
151 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
152 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
153 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
154 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
155 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
156 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
157 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 158 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
1da177e4 LT |
159 | NvRegTransmitterStatus = 0x088, |
160 | #define NVREG_XMITSTAT_BUSY 0x01 | |
161 | ||
162 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
163 | #define NVREG_PFF_PAUSE_RX 0x08 |
164 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
165 | #define NVREG_PFF_PROMISC 0x80 |
166 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 167 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
168 | |
169 | NvRegOffloadConfig = 0x90, | |
170 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
171 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
172 | NvRegReceiverControl = 0x094, | |
173 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 174 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
175 | NvRegReceiverStatus = 0x98, |
176 | #define NVREG_RCVSTAT_BUSY 0x01 | |
177 | ||
a433686c AA |
178 | NvRegSlotTime = 0x9c, |
179 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
180 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
181 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 | |
182 | #define NVREG_SLOTTIME_HALF 0x0000ff00 | |
183 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 | |
184 | #define NVREG_SLOTTIME_MASK 0x000000ff | |
1da177e4 | 185 | |
9744e218 | 186 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
187 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
188 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
189 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
190 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
191 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
192 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
193 | NvRegRxDeferral = 0xA4, |
194 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
195 | NvRegMacAddrA = 0xA8, |
196 | NvRegMacAddrB = 0xAC, | |
197 | NvRegMulticastAddrA = 0xB0, | |
198 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
199 | NvRegMulticastAddrB = 0xB4, | |
200 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 201 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 202 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 203 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
204 | |
205 | NvRegPhyInterface = 0xC0, | |
206 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
207 | NvRegBackOffControl = 0xC4, |
208 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
209 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
210 | #define NVREG_BKOFFCTRL_SELECT 24 | |
211 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
212 | |
213 | NvRegTxRingPhysAddr = 0x100, | |
214 | NvRegRxRingPhysAddr = 0x104, | |
215 | NvRegRingSizes = 0x108, | |
216 | #define NVREG_RINGSZ_TXSHIFT 0 | |
217 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
218 | NvRegTransmitPoll = 0x10c, |
219 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
220 | NvRegLinkSpeed = 0x110, |
221 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
222 | #define NVREG_LINKSPEED_10 1000 | |
223 | #define NVREG_LINKSPEED_100 100 | |
224 | #define NVREG_LINKSPEED_1000 50 | |
225 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
226 | NvRegUnknownSetupReg5 = 0x130, | |
227 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
228 | NvRegTxWatermark = 0x13c, |
229 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
230 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
231 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
232 | NvRegTxRxControl = 0x144, |
233 | #define NVREG_TXRXCTL_KICK 0x0001 | |
234 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
235 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
236 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
237 | #define NVREG_TXRXCTL_RESET 0x0010 | |
238 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 239 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
240 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
241 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
242 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
243 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
244 | NvRegTxRingPhysAddrHigh = 0x148, |
245 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 246 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
247 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
248 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
249 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
250 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
1da177e4 LT |
251 | NvRegMIIStatus = 0x180, |
252 | #define NVREG_MIISTAT_ERROR 0x0001 | |
253 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
254 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
255 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
256 | NvRegMIIMask = 0x184, |
257 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
258 | |
259 | NvRegAdapterControl = 0x188, | |
260 | #define NVREG_ADAPTCTL_START 0x02 | |
261 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
262 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
263 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
264 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
265 | NvRegMIISpeed = 0x18c, | |
266 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
267 | #define NVREG_MIIDELAY 5 | |
268 | NvRegMIIControl = 0x190, | |
269 | #define NVREG_MIICTL_INUSE 0x08000 | |
270 | #define NVREG_MIICTL_WRITE 0x00400 | |
271 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
272 | NvRegMIIData = 0x194, | |
273 | NvRegWakeUpFlags = 0x200, | |
274 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
275 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
276 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
277 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
278 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
279 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
280 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
281 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
282 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
283 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
284 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
285 | ||
286 | NvRegPatternCRC = 0x204, | |
287 | NvRegPatternMask = 0x208, | |
288 | NvRegPowerCap = 0x268, | |
289 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
290 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
291 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
292 | NvRegPowerState = 0x26c, | |
293 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
294 | #define NVREG_POWERSTATE_VALID 0x0100 | |
295 | #define NVREG_POWERSTATE_MASK 0x0003 | |
296 | #define NVREG_POWERSTATE_D0 0x0000 | |
297 | #define NVREG_POWERSTATE_D1 0x0001 | |
298 | #define NVREG_POWERSTATE_D2 0x0002 | |
299 | #define NVREG_POWERSTATE_D3 0x0003 | |
52da3578 AA |
300 | NvRegTxCnt = 0x280, |
301 | NvRegTxZeroReXmt = 0x284, | |
302 | NvRegTxOneReXmt = 0x288, | |
303 | NvRegTxManyReXmt = 0x28c, | |
304 | NvRegTxLateCol = 0x290, | |
305 | NvRegTxUnderflow = 0x294, | |
306 | NvRegTxLossCarrier = 0x298, | |
307 | NvRegTxExcessDef = 0x29c, | |
308 | NvRegTxRetryErr = 0x2a0, | |
309 | NvRegRxFrameErr = 0x2a4, | |
310 | NvRegRxExtraByte = 0x2a8, | |
311 | NvRegRxLateCol = 0x2ac, | |
312 | NvRegRxRunt = 0x2b0, | |
313 | NvRegRxFrameTooLong = 0x2b4, | |
314 | NvRegRxOverflow = 0x2b8, | |
315 | NvRegRxFCSErr = 0x2bc, | |
316 | NvRegRxFrameAlignErr = 0x2c0, | |
317 | NvRegRxLenErr = 0x2c4, | |
318 | NvRegRxUnicast = 0x2c8, | |
319 | NvRegRxMulticast = 0x2cc, | |
320 | NvRegRxBroadcast = 0x2d0, | |
321 | NvRegTxDef = 0x2d4, | |
322 | NvRegTxFrame = 0x2d8, | |
323 | NvRegRxCnt = 0x2dc, | |
324 | NvRegTxPause = 0x2e0, | |
325 | NvRegRxPause = 0x2e4, | |
326 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
327 | NvRegVlanControl = 0x300, |
328 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
329 | NvRegMSIXMap0 = 0x3e0, |
330 | NvRegMSIXMap1 = 0x3e4, | |
331 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
332 | |
333 | NvRegPowerState2 = 0x600, | |
334 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 | |
335 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 | |
1da177e4 LT |
336 | }; |
337 | ||
338 | /* Big endian: should work, but is untested */ | |
339 | struct ring_desc { | |
a8bed49e SH |
340 | __le32 buf; |
341 | __le32 flaglen; | |
1da177e4 LT |
342 | }; |
343 | ||
ee73362c | 344 | struct ring_desc_ex { |
a8bed49e SH |
345 | __le32 bufhigh; |
346 | __le32 buflow; | |
347 | __le32 txvlan; | |
348 | __le32 flaglen; | |
ee73362c MS |
349 | }; |
350 | ||
f82a9352 | 351 | union ring_type { |
ee73362c MS |
352 | struct ring_desc* orig; |
353 | struct ring_desc_ex* ex; | |
f82a9352 | 354 | }; |
ee73362c | 355 | |
1da177e4 LT |
356 | #define FLAG_MASK_V1 0xffff0000 |
357 | #define FLAG_MASK_V2 0xffffc000 | |
358 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
359 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
360 | ||
361 | #define NV_TX_LASTPACKET (1<<16) | |
362 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 363 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 364 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
365 | #define NV_TX_DEFERRED (1<<26) |
366 | #define NV_TX_CARRIERLOST (1<<27) | |
367 | #define NV_TX_LATECOLLISION (1<<28) | |
368 | #define NV_TX_UNDERFLOW (1<<29) | |
369 | #define NV_TX_ERROR (1<<30) | |
370 | #define NV_TX_VALID (1<<31) | |
371 | ||
372 | #define NV_TX2_LASTPACKET (1<<29) | |
373 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 374 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 375 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
376 | #define NV_TX2_DEFERRED (1<<25) |
377 | #define NV_TX2_CARRIERLOST (1<<26) | |
378 | #define NV_TX2_LATECOLLISION (1<<27) | |
379 | #define NV_TX2_UNDERFLOW (1<<28) | |
380 | /* error and valid are the same for both */ | |
381 | #define NV_TX2_ERROR (1<<30) | |
382 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
383 | #define NV_TX2_TSO (1<<28) |
384 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
385 | #define NV_TX2_TSO_MAX_SHIFT 14 |
386 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
387 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
388 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 389 | |
ee407b02 AA |
390 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
391 | ||
1da177e4 LT |
392 | #define NV_RX_DESCRIPTORVALID (1<<16) |
393 | #define NV_RX_MISSEDFRAME (1<<17) | |
394 | #define NV_RX_SUBSTRACT1 (1<<18) | |
395 | #define NV_RX_ERROR1 (1<<23) | |
396 | #define NV_RX_ERROR2 (1<<24) | |
397 | #define NV_RX_ERROR3 (1<<25) | |
398 | #define NV_RX_ERROR4 (1<<26) | |
399 | #define NV_RX_CRCERR (1<<27) | |
400 | #define NV_RX_OVERFLOW (1<<28) | |
401 | #define NV_RX_FRAMINGERR (1<<29) | |
402 | #define NV_RX_ERROR (1<<30) | |
403 | #define NV_RX_AVAIL (1<<31) | |
404 | ||
405 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
406 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
407 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
408 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 LT |
409 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
410 | #define NV_RX2_SUBSTRACT1 (1<<25) | |
411 | #define NV_RX2_ERROR1 (1<<18) | |
412 | #define NV_RX2_ERROR2 (1<<19) | |
413 | #define NV_RX2_ERROR3 (1<<20) | |
414 | #define NV_RX2_ERROR4 (1<<21) | |
415 | #define NV_RX2_CRCERR (1<<22) | |
416 | #define NV_RX2_OVERFLOW (1<<23) | |
417 | #define NV_RX2_FRAMINGERR (1<<24) | |
418 | /* error and avail are the same for both */ | |
419 | #define NV_RX2_ERROR (1<<30) | |
420 | #define NV_RX2_AVAIL (1<<31) | |
421 | ||
ee407b02 AA |
422 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
423 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
424 | ||
1da177e4 | 425 | /* Miscelaneous hardware related defines: */ |
86a0f043 | 426 | #define NV_PCI_REGSZ_VER1 0x270 |
57fff698 AA |
427 | #define NV_PCI_REGSZ_VER2 0x2d4 |
428 | #define NV_PCI_REGSZ_VER3 0x604 | |
1da177e4 LT |
429 | |
430 | /* various timeout delays: all in usec */ | |
431 | #define NV_TXRX_RESET_DELAY 4 | |
432 | #define NV_TXSTOP_DELAY1 10 | |
433 | #define NV_TXSTOP_DELAY1MAX 500000 | |
434 | #define NV_TXSTOP_DELAY2 100 | |
435 | #define NV_RXSTOP_DELAY1 10 | |
436 | #define NV_RXSTOP_DELAY1MAX 500000 | |
437 | #define NV_RXSTOP_DELAY2 100 | |
438 | #define NV_SETUP5_DELAY 5 | |
439 | #define NV_SETUP5_DELAYMAX 50000 | |
440 | #define NV_POWERUP_DELAY 5 | |
441 | #define NV_POWERUP_DELAYMAX 5000 | |
442 | #define NV_MIIBUSY_DELAY 50 | |
443 | #define NV_MIIPHY_DELAY 10 | |
444 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 445 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
446 | |
447 | #define NV_WAKEUPPATTERNS 5 | |
448 | #define NV_WAKEUPMASKENTRIES 4 | |
449 | ||
450 | /* General driver defaults */ | |
451 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
452 | ||
eafa59f6 AA |
453 | #define RX_RING_DEFAULT 128 |
454 | #define TX_RING_DEFAULT 256 | |
455 | #define RX_RING_MIN 128 | |
456 | #define TX_RING_MIN 64 | |
457 | #define RING_MAX_DESC_VER_1 1024 | |
458 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
459 | |
460 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
461 | #define NV_RX_HEADERS (64) |
462 | /* even more slack. */ | |
463 | #define NV_RX_ALLOC_PAD (64) | |
464 | ||
465 | /* maximum mtu size */ | |
466 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
467 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
468 | |
469 | #define OOM_REFILL (1+HZ/20) | |
470 | #define POLL_WAIT (1+HZ/100) | |
471 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 472 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 473 | |
f3b197ac | 474 | /* |
1da177e4 | 475 | * desc_ver values: |
8a4ae7f2 MS |
476 | * The nic supports three different descriptor types: |
477 | * - DESC_VER_1: Original | |
478 | * - DESC_VER_2: support for jumbo frames. | |
479 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 480 | */ |
8a4ae7f2 MS |
481 | #define DESC_VER_1 1 |
482 | #define DESC_VER_2 2 | |
483 | #define DESC_VER_3 3 | |
1da177e4 LT |
484 | |
485 | /* PHY defines */ | |
486 | #define PHY_OUI_MARVELL 0x5043 | |
487 | #define PHY_OUI_CICADA 0x03f1 | |
d215d8a2 | 488 | #define PHY_OUI_VITESSE 0x01c1 |
ba685fb2 | 489 | #define PHY_OUI_REALTEK 0x0732 |
1da177e4 LT |
490 | #define PHYID1_OUI_MASK 0x03ff |
491 | #define PHYID1_OUI_SHFT 6 | |
492 | #define PHYID2_OUI_MASK 0xfc00 | |
493 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec AA |
494 | #define PHYID2_MODEL_MASK 0x03f0 |
495 | #define PHY_MODEL_MARVELL_E3016 0x220 | |
496 | #define PHY_MARVELL_E3016_INITMASK 0x0300 | |
14a67f3c AA |
497 | #define PHY_CICADA_INIT1 0x0f000 |
498 | #define PHY_CICADA_INIT2 0x0e00 | |
499 | #define PHY_CICADA_INIT3 0x01000 | |
500 | #define PHY_CICADA_INIT4 0x0200 | |
501 | #define PHY_CICADA_INIT5 0x0004 | |
502 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
503 | #define PHY_VITESSE_INIT_REG1 0x1f |
504 | #define PHY_VITESSE_INIT_REG2 0x10 | |
505 | #define PHY_VITESSE_INIT_REG3 0x11 | |
506 | #define PHY_VITESSE_INIT_REG4 0x12 | |
507 | #define PHY_VITESSE_INIT_MSK1 0xc | |
508 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
509 | #define PHY_VITESSE_INIT1 0x52b5 | |
510 | #define PHY_VITESSE_INIT2 0xaf8a | |
511 | #define PHY_VITESSE_INIT3 0x8 | |
512 | #define PHY_VITESSE_INIT4 0x8f8a | |
513 | #define PHY_VITESSE_INIT5 0xaf86 | |
514 | #define PHY_VITESSE_INIT6 0x8f86 | |
515 | #define PHY_VITESSE_INIT7 0xaf82 | |
516 | #define PHY_VITESSE_INIT8 0x0100 | |
517 | #define PHY_VITESSE_INIT9 0x8f82 | |
518 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
519 | #define PHY_REALTEK_INIT_REG1 0x1f |
520 | #define PHY_REALTEK_INIT_REG2 0x19 | |
521 | #define PHY_REALTEK_INIT_REG3 0x13 | |
522 | #define PHY_REALTEK_INIT1 0x0000 | |
523 | #define PHY_REALTEK_INIT2 0x8e00 | |
524 | #define PHY_REALTEK_INIT3 0x0001 | |
525 | #define PHY_REALTEK_INIT4 0xad17 | |
d215d8a2 | 526 | |
1da177e4 LT |
527 | #define PHY_GIGABIT 0x0100 |
528 | ||
529 | #define PHY_TIMEOUT 0x1 | |
530 | #define PHY_ERROR 0x2 | |
531 | ||
532 | #define PHY_100 0x1 | |
533 | #define PHY_1000 0x2 | |
534 | #define PHY_HALF 0x100 | |
535 | ||
eb91f61b AA |
536 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
537 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
538 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
539 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
540 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
541 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
542 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 543 | |
d33a73c8 AA |
544 | /* MSI/MSI-X defines */ |
545 | #define NV_MSI_X_MAX_VECTORS 8 | |
546 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
547 | #define NV_MSI_CAPABLE 0x0010 | |
548 | #define NV_MSI_X_CAPABLE 0x0020 | |
549 | #define NV_MSI_ENABLED 0x0040 | |
550 | #define NV_MSI_X_ENABLED 0x0080 | |
551 | ||
552 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
553 | #define NV_MSI_X_VECTOR_RX 0x0 | |
554 | #define NV_MSI_X_VECTOR_TX 0x1 | |
555 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 556 | |
b2976d23 AA |
557 | #define NV_RESTART_TX 0x1 |
558 | #define NV_RESTART_RX 0x2 | |
559 | ||
3b446c3e AA |
560 | #define NV_TX_LIMIT_COUNT 16 |
561 | ||
52da3578 AA |
562 | /* statistics */ |
563 | struct nv_ethtool_str { | |
564 | char name[ETH_GSTRING_LEN]; | |
565 | }; | |
566 | ||
567 | static const struct nv_ethtool_str nv_estats_str[] = { | |
568 | { "tx_bytes" }, | |
569 | { "tx_zero_rexmt" }, | |
570 | { "tx_one_rexmt" }, | |
571 | { "tx_many_rexmt" }, | |
572 | { "tx_late_collision" }, | |
573 | { "tx_fifo_errors" }, | |
574 | { "tx_carrier_errors" }, | |
575 | { "tx_excess_deferral" }, | |
576 | { "tx_retry_error" }, | |
52da3578 AA |
577 | { "rx_frame_error" }, |
578 | { "rx_extra_byte" }, | |
579 | { "rx_late_collision" }, | |
580 | { "rx_runt" }, | |
581 | { "rx_frame_too_long" }, | |
582 | { "rx_over_errors" }, | |
583 | { "rx_crc_errors" }, | |
584 | { "rx_frame_align_error" }, | |
585 | { "rx_length_error" }, | |
586 | { "rx_unicast" }, | |
587 | { "rx_multicast" }, | |
588 | { "rx_broadcast" }, | |
57fff698 AA |
589 | { "rx_packets" }, |
590 | { "rx_errors_total" }, | |
591 | { "tx_errors_total" }, | |
592 | ||
593 | /* version 2 stats */ | |
594 | { "tx_deferral" }, | |
595 | { "tx_packets" }, | |
52da3578 | 596 | { "rx_bytes" }, |
57fff698 | 597 | { "tx_pause" }, |
52da3578 | 598 | { "rx_pause" }, |
57fff698 | 599 | { "rx_drop_frame" } |
52da3578 AA |
600 | }; |
601 | ||
602 | struct nv_ethtool_stats { | |
603 | u64 tx_bytes; | |
604 | u64 tx_zero_rexmt; | |
605 | u64 tx_one_rexmt; | |
606 | u64 tx_many_rexmt; | |
607 | u64 tx_late_collision; | |
608 | u64 tx_fifo_errors; | |
609 | u64 tx_carrier_errors; | |
610 | u64 tx_excess_deferral; | |
611 | u64 tx_retry_error; | |
52da3578 AA |
612 | u64 rx_frame_error; |
613 | u64 rx_extra_byte; | |
614 | u64 rx_late_collision; | |
615 | u64 rx_runt; | |
616 | u64 rx_frame_too_long; | |
617 | u64 rx_over_errors; | |
618 | u64 rx_crc_errors; | |
619 | u64 rx_frame_align_error; | |
620 | u64 rx_length_error; | |
621 | u64 rx_unicast; | |
622 | u64 rx_multicast; | |
623 | u64 rx_broadcast; | |
57fff698 AA |
624 | u64 rx_packets; |
625 | u64 rx_errors_total; | |
626 | u64 tx_errors_total; | |
627 | ||
628 | /* version 2 stats */ | |
629 | u64 tx_deferral; | |
630 | u64 tx_packets; | |
52da3578 | 631 | u64 rx_bytes; |
57fff698 | 632 | u64 tx_pause; |
52da3578 AA |
633 | u64 rx_pause; |
634 | u64 rx_drop_frame; | |
52da3578 AA |
635 | }; |
636 | ||
57fff698 AA |
637 | #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
638 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) | |
639 | ||
9589c77a AA |
640 | /* diagnostics */ |
641 | #define NV_TEST_COUNT_BASE 3 | |
642 | #define NV_TEST_COUNT_EXTENDED 4 | |
643 | ||
644 | static const struct nv_ethtool_str nv_etests_str[] = { | |
645 | { "link (online/offline)" }, | |
646 | { "register (offline) " }, | |
647 | { "interrupt (offline) " }, | |
648 | { "loopback (offline) " } | |
649 | }; | |
650 | ||
651 | struct register_test { | |
5bb7ea26 AV |
652 | __u32 reg; |
653 | __u32 mask; | |
9589c77a AA |
654 | }; |
655 | ||
656 | static const struct register_test nv_registers_test[] = { | |
657 | { NvRegUnknownSetupReg6, 0x01 }, | |
658 | { NvRegMisc1, 0x03c }, | |
659 | { NvRegOffloadConfig, 0x03ff }, | |
660 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 661 | { NvRegTxWatermark, 0x0ff }, |
9589c77a AA |
662 | { NvRegWakeUpFlags, 0x07777 }, |
663 | { 0,0 } | |
664 | }; | |
665 | ||
761fcd9e AA |
666 | struct nv_skb_map { |
667 | struct sk_buff *skb; | |
668 | dma_addr_t dma; | |
669 | unsigned int dma_len; | |
3b446c3e AA |
670 | struct ring_desc_ex *first_tx_desc; |
671 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
672 | }; |
673 | ||
1da177e4 LT |
674 | /* |
675 | * SMP locking: | |
676 | * All hardware access under dev->priv->lock, except the performance | |
677 | * critical parts: | |
678 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
679 | * by the arch code for interrupts. | |
932ff279 | 680 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
1da177e4 | 681 | * needs dev->priv->lock :-( |
932ff279 | 682 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
1da177e4 LT |
683 | */ |
684 | ||
685 | /* in dev: base, irq */ | |
686 | struct fe_priv { | |
687 | spinlock_t lock; | |
688 | ||
bea3348e SH |
689 | struct net_device *dev; |
690 | struct napi_struct napi; | |
691 | ||
1da177e4 LT |
692 | /* General data: |
693 | * Locking: spin_lock(&np->lock); */ | |
52da3578 | 694 | struct nv_ethtool_stats estats; |
1da177e4 LT |
695 | int in_shutdown; |
696 | u32 linkspeed; | |
697 | int duplex; | |
698 | int autoneg; | |
699 | int fixed_mode; | |
700 | int phyaddr; | |
701 | int wolenabled; | |
702 | unsigned int phy_oui; | |
edf7e5ec | 703 | unsigned int phy_model; |
1da177e4 | 704 | u16 gigabit; |
9589c77a | 705 | int intr_test; |
c5cf9101 | 706 | int recover_error; |
1da177e4 LT |
707 | |
708 | /* General data: RO fields */ | |
709 | dma_addr_t ring_addr; | |
710 | struct pci_dev *pci_dev; | |
711 | u32 orig_mac[2]; | |
712 | u32 irqmask; | |
713 | u32 desc_ver; | |
8a4ae7f2 | 714 | u32 txrxctl_bits; |
ee407b02 | 715 | u32 vlanctl_bits; |
86a0f043 AA |
716 | u32 driver_data; |
717 | u32 register_size; | |
f2ad2d9b | 718 | int rx_csum; |
7e680c22 | 719 | u32 mac_in_use; |
1da177e4 LT |
720 | |
721 | void __iomem *base; | |
722 | ||
723 | /* rx specific fields. | |
724 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
725 | */ | |
761fcd9e AA |
726 | union ring_type get_rx, put_rx, first_rx, last_rx; |
727 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; | |
728 | struct nv_skb_map *first_rx_ctx, *last_rx_ctx; | |
729 | struct nv_skb_map *rx_skb; | |
730 | ||
f82a9352 | 731 | union ring_type rx_ring; |
1da177e4 | 732 | unsigned int rx_buf_sz; |
d81c0983 | 733 | unsigned int pkt_limit; |
1da177e4 LT |
734 | struct timer_list oom_kick; |
735 | struct timer_list nic_poll; | |
52da3578 | 736 | struct timer_list stats_poll; |
d33a73c8 | 737 | u32 nic_poll_irq; |
eafa59f6 | 738 | int rx_ring_size; |
1da177e4 LT |
739 | |
740 | /* media detection workaround. | |
741 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
742 | */ | |
743 | int need_linktimer; | |
744 | unsigned long link_timeout; | |
745 | /* | |
746 | * tx specific fields. | |
747 | */ | |
761fcd9e AA |
748 | union ring_type get_tx, put_tx, first_tx, last_tx; |
749 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; | |
750 | struct nv_skb_map *first_tx_ctx, *last_tx_ctx; | |
751 | struct nv_skb_map *tx_skb; | |
752 | ||
f82a9352 | 753 | union ring_type tx_ring; |
1da177e4 | 754 | u32 tx_flags; |
eafa59f6 | 755 | int tx_ring_size; |
3b446c3e AA |
756 | int tx_limit; |
757 | u32 tx_pkts_in_progress; | |
758 | struct nv_skb_map *tx_change_owner; | |
759 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 760 | int tx_stop; |
ee407b02 AA |
761 | |
762 | /* vlan fields */ | |
763 | struct vlan_group *vlangrp; | |
d33a73c8 AA |
764 | |
765 | /* msi/msi-x fields */ | |
766 | u32 msi_flags; | |
767 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
768 | |
769 | /* flow control */ | |
770 | u32 pause_flags; | |
1da177e4 LT |
771 | }; |
772 | ||
773 | /* | |
774 | * Maximum number of loops until we assume that a bit in the irq mask | |
775 | * is stuck. Overridable with module param. | |
776 | */ | |
777 | static int max_interrupt_work = 5; | |
778 | ||
a971c324 AA |
779 | /* |
780 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 781 | * |
a971c324 AA |
782 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
783 | * CPU Mode: Interrupts are controlled by a timer. | |
784 | */ | |
69fe3fd7 AA |
785 | enum { |
786 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
787 | NV_OPTIMIZATION_MODE_CPU | |
788 | }; | |
a971c324 AA |
789 | static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
790 | ||
791 | /* | |
792 | * Poll interval for timer irq | |
793 | * | |
794 | * This interval determines how frequent an interrupt is generated. | |
795 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
796 | * Min = 0, and Max = 65535 | |
797 | */ | |
798 | static int poll_interval = -1; | |
799 | ||
d33a73c8 | 800 | /* |
69fe3fd7 | 801 | * MSI interrupts |
d33a73c8 | 802 | */ |
69fe3fd7 AA |
803 | enum { |
804 | NV_MSI_INT_DISABLED, | |
805 | NV_MSI_INT_ENABLED | |
806 | }; | |
807 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
808 | |
809 | /* | |
69fe3fd7 | 810 | * MSIX interrupts |
d33a73c8 | 811 | */ |
69fe3fd7 AA |
812 | enum { |
813 | NV_MSIX_INT_DISABLED, | |
814 | NV_MSIX_INT_ENABLED | |
815 | }; | |
caf96469 | 816 | static int msix = NV_MSIX_INT_DISABLED; |
69fe3fd7 AA |
817 | |
818 | /* | |
819 | * DMA 64bit | |
820 | */ | |
821 | enum { | |
822 | NV_DMA_64BIT_DISABLED, | |
823 | NV_DMA_64BIT_ENABLED | |
824 | }; | |
825 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 826 | |
1da177e4 LT |
827 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
828 | { | |
829 | return netdev_priv(dev); | |
830 | } | |
831 | ||
832 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
833 | { | |
ac9c1897 | 834 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
835 | } |
836 | ||
837 | static inline void pci_push(u8 __iomem *base) | |
838 | { | |
839 | /* force out pending posted writes */ | |
840 | readl(base); | |
841 | } | |
842 | ||
843 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
844 | { | |
f82a9352 | 845 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
846 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
847 | } | |
848 | ||
ee73362c MS |
849 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
850 | { | |
f82a9352 | 851 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
852 | } |
853 | ||
36b30ea9 JG |
854 | static bool nv_optimized(struct fe_priv *np) |
855 | { | |
856 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
857 | return false; | |
858 | return true; | |
859 | } | |
860 | ||
1da177e4 LT |
861 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
862 | int delay, int delaymax, const char *msg) | |
863 | { | |
864 | u8 __iomem *base = get_hwbase(dev); | |
865 | ||
866 | pci_push(base); | |
867 | do { | |
868 | udelay(delay); | |
869 | delaymax -= delay; | |
870 | if (delaymax < 0) { | |
871 | if (msg) | |
872 | printk(msg); | |
873 | return 1; | |
874 | } | |
875 | } while ((readl(base + offset) & mask) != target); | |
876 | return 0; | |
877 | } | |
878 | ||
0832b25a AA |
879 | #define NV_SETUP_RX_RING 0x01 |
880 | #define NV_SETUP_TX_RING 0x02 | |
881 | ||
5bb7ea26 AV |
882 | static inline u32 dma_low(dma_addr_t addr) |
883 | { | |
884 | return addr; | |
885 | } | |
886 | ||
887 | static inline u32 dma_high(dma_addr_t addr) | |
888 | { | |
889 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
890 | } | |
891 | ||
0832b25a AA |
892 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
893 | { | |
894 | struct fe_priv *np = get_nvpriv(dev); | |
895 | u8 __iomem *base = get_hwbase(dev); | |
896 | ||
36b30ea9 | 897 | if (!nv_optimized(np)) { |
0832b25a | 898 | if (rxtx_flags & NV_SETUP_RX_RING) { |
5bb7ea26 | 899 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
0832b25a AA |
900 | } |
901 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 | 902 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
903 | } |
904 | } else { | |
905 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
906 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
907 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
908 | } |
909 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
910 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
911 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
912 | } |
913 | } | |
914 | } | |
915 | ||
eafa59f6 AA |
916 | static void free_rings(struct net_device *dev) |
917 | { | |
918 | struct fe_priv *np = get_nvpriv(dev); | |
919 | ||
36b30ea9 | 920 | if (!nv_optimized(np)) { |
f82a9352 | 921 | if (np->rx_ring.orig) |
eafa59f6 AA |
922 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
923 | np->rx_ring.orig, np->ring_addr); | |
924 | } else { | |
925 | if (np->rx_ring.ex) | |
926 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), | |
927 | np->rx_ring.ex, np->ring_addr); | |
928 | } | |
761fcd9e AA |
929 | if (np->rx_skb) |
930 | kfree(np->rx_skb); | |
931 | if (np->tx_skb) | |
932 | kfree(np->tx_skb); | |
eafa59f6 AA |
933 | } |
934 | ||
84b3932b AA |
935 | static int using_multi_irqs(struct net_device *dev) |
936 | { | |
937 | struct fe_priv *np = get_nvpriv(dev); | |
938 | ||
939 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
940 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
941 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
942 | return 0; | |
943 | else | |
944 | return 1; | |
945 | } | |
946 | ||
947 | static void nv_enable_irq(struct net_device *dev) | |
948 | { | |
949 | struct fe_priv *np = get_nvpriv(dev); | |
950 | ||
951 | if (!using_multi_irqs(dev)) { | |
952 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
953 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
954 | else | |
a7475906 | 955 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
956 | } else { |
957 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
958 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
959 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
960 | } | |
961 | } | |
962 | ||
963 | static void nv_disable_irq(struct net_device *dev) | |
964 | { | |
965 | struct fe_priv *np = get_nvpriv(dev); | |
966 | ||
967 | if (!using_multi_irqs(dev)) { | |
968 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
969 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
970 | else | |
a7475906 | 971 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
972 | } else { |
973 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
974 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
975 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
976 | } | |
977 | } | |
978 | ||
979 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
980 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
981 | { | |
982 | u8 __iomem *base = get_hwbase(dev); | |
983 | ||
984 | writel(mask, base + NvRegIrqMask); | |
985 | } | |
986 | ||
987 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
988 | { | |
989 | struct fe_priv *np = get_nvpriv(dev); | |
990 | u8 __iomem *base = get_hwbase(dev); | |
991 | ||
992 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
993 | writel(mask, base + NvRegIrqMask); | |
994 | } else { | |
995 | if (np->msi_flags & NV_MSI_ENABLED) | |
996 | writel(0, base + NvRegMSIIrqMask); | |
997 | writel(0, base + NvRegIrqMask); | |
998 | } | |
999 | } | |
1000 | ||
1da177e4 LT |
1001 | #define MII_READ (-1) |
1002 | /* mii_rw: read/write a register on the PHY. | |
1003 | * | |
1004 | * Caller must guarantee serialization | |
1005 | */ | |
1006 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1007 | { | |
1008 | u8 __iomem *base = get_hwbase(dev); | |
1009 | u32 reg; | |
1010 | int retval; | |
1011 | ||
eb798428 | 1012 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1013 | |
1014 | reg = readl(base + NvRegMIIControl); | |
1015 | if (reg & NVREG_MIICTL_INUSE) { | |
1016 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1017 | udelay(NV_MIIBUSY_DELAY); | |
1018 | } | |
1019 | ||
1020 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1021 | if (value != MII_READ) { | |
1022 | writel(value, base + NvRegMIIData); | |
1023 | reg |= NVREG_MIICTL_WRITE; | |
1024 | } | |
1025 | writel(reg, base + NvRegMIIControl); | |
1026 | ||
1027 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
1028 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { | |
1029 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", | |
1030 | dev->name, miireg, addr); | |
1031 | retval = -1; | |
1032 | } else if (value != MII_READ) { | |
1033 | /* it was a write operation - fewer failures are detectable */ | |
1034 | dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", | |
1035 | dev->name, value, miireg, addr); | |
1036 | retval = 0; | |
1037 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1038 | dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", | |
1039 | dev->name, miireg, addr); | |
1040 | retval = -1; | |
1041 | } else { | |
1042 | retval = readl(base + NvRegMIIData); | |
1043 | dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", | |
1044 | dev->name, miireg, addr, retval); | |
1045 | } | |
1046 | ||
1047 | return retval; | |
1048 | } | |
1049 | ||
edf7e5ec | 1050 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1051 | { |
ac9c1897 | 1052 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1053 | u32 miicontrol; |
1054 | unsigned int tries = 0; | |
1055 | ||
edf7e5ec | 1056 | miicontrol = BMCR_RESET | bmcr_setup; |
1da177e4 LT |
1057 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
1058 | return -1; | |
1059 | } | |
1060 | ||
1061 | /* wait for 500ms */ | |
1062 | msleep(500); | |
1063 | ||
1064 | /* must wait till reset is deasserted */ | |
1065 | while (miicontrol & BMCR_RESET) { | |
1066 | msleep(10); | |
1067 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1068 | /* FIXME: 100 tries seem excessive */ | |
1069 | if (tries++ > 100) | |
1070 | return -1; | |
1071 | } | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static int phy_init(struct net_device *dev) | |
1076 | { | |
1077 | struct fe_priv *np = get_nvpriv(dev); | |
1078 | u8 __iomem *base = get_hwbase(dev); | |
1079 | u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; | |
1080 | ||
edf7e5ec AA |
1081 | /* phy errata for E3016 phy */ |
1082 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1083 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1084 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1085 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1086 | printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); | |
1087 | return PHY_ERROR; | |
1088 | } | |
1089 | } | |
c5e3ae88 AA |
1090 | if (np->phy_oui == PHY_OUI_REALTEK) { |
1091 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1092 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1093 | return PHY_ERROR; | |
1094 | } | |
1095 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1096 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1097 | return PHY_ERROR; | |
1098 | } | |
1099 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1100 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1101 | return PHY_ERROR; | |
1102 | } | |
1103 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1104 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1105 | return PHY_ERROR; | |
1106 | } | |
1107 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1108 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1109 | return PHY_ERROR; | |
1110 | } | |
1111 | } | |
edf7e5ec | 1112 | |
1da177e4 LT |
1113 | /* set advertise register */ |
1114 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 1115 | reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1da177e4 LT |
1116 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1117 | printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); | |
1118 | return PHY_ERROR; | |
1119 | } | |
1120 | ||
1121 | /* get phy interface type */ | |
1122 | phyinterface = readl(base + NvRegPhyInterface); | |
1123 | ||
1124 | /* see if gigabit phy */ | |
1125 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1126 | if (mii_status & PHY_GIGABIT) { | |
1127 | np->gigabit = PHY_GIGABIT; | |
eb91f61b | 1128 | mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
1129 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1130 | if (phyinterface & PHY_RGMII) | |
1131 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1132 | else | |
1133 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1134 | ||
eb91f61b | 1135 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1da177e4 LT |
1136 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1137 | return PHY_ERROR; | |
1138 | } | |
1139 | } | |
1140 | else | |
1141 | np->gigabit = 0; | |
1142 | ||
edf7e5ec AA |
1143 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1144 | mii_control |= BMCR_ANENABLE; | |
1145 | ||
1146 | /* reset the phy | |
1147 | * (certain phys need bmcr to be setup with reset) | |
1148 | */ | |
1149 | if (phy_reset(dev, mii_control)) { | |
1da177e4 LT |
1150 | printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
1151 | return PHY_ERROR; | |
1152 | } | |
1153 | ||
1154 | /* phy vendor specific configuration */ | |
1155 | if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { | |
1156 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
14a67f3c AA |
1157 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1158 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1da177e4 LT |
1159 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1160 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1161 | return PHY_ERROR; | |
1162 | } | |
1163 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
14a67f3c | 1164 | phy_reserved |= PHY_CICADA_INIT5; |
1da177e4 LT |
1165 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1166 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1167 | return PHY_ERROR; | |
1168 | } | |
1169 | } | |
1170 | if (np->phy_oui == PHY_OUI_CICADA) { | |
1171 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
14a67f3c | 1172 | phy_reserved |= PHY_CICADA_INIT6; |
1da177e4 LT |
1173 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1174 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1175 | return PHY_ERROR; | |
1176 | } | |
1177 | } | |
d215d8a2 AA |
1178 | if (np->phy_oui == PHY_OUI_VITESSE) { |
1179 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { | |
1180 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1181 | return PHY_ERROR; | |
1182 | } | |
1183 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { | |
1184 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1185 | return PHY_ERROR; | |
1186 | } | |
1187 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1188 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1189 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1190 | return PHY_ERROR; | |
1191 | } | |
1192 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1193 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1194 | phy_reserved |= PHY_VITESSE_INIT3; | |
1195 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1196 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1197 | return PHY_ERROR; | |
1198 | } | |
1199 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { | |
1200 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1201 | return PHY_ERROR; | |
1202 | } | |
1203 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { | |
1204 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1205 | return PHY_ERROR; | |
1206 | } | |
1207 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1208 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1209 | phy_reserved |= PHY_VITESSE_INIT3; | |
1210 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1211 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1212 | return PHY_ERROR; | |
1213 | } | |
1214 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1215 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1216 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1217 | return PHY_ERROR; | |
1218 | } | |
1219 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { | |
1220 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1221 | return PHY_ERROR; | |
1222 | } | |
1223 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { | |
1224 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1225 | return PHY_ERROR; | |
1226 | } | |
1227 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); | |
1228 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { | |
1229 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1230 | return PHY_ERROR; | |
1231 | } | |
1232 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); | |
1233 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1234 | phy_reserved |= PHY_VITESSE_INIT8; | |
1235 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { | |
1236 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1237 | return PHY_ERROR; | |
1238 | } | |
1239 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { | |
1240 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1241 | return PHY_ERROR; | |
1242 | } | |
1243 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { | |
1244 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1245 | return PHY_ERROR; | |
1246 | } | |
1247 | } | |
c5e3ae88 AA |
1248 | if (np->phy_oui == PHY_OUI_REALTEK) { |
1249 | /* reset could have cleared these out, set them back */ | |
1250 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1251 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1252 | return PHY_ERROR; | |
1253 | } | |
1254 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { | |
1255 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1256 | return PHY_ERROR; | |
1257 | } | |
1258 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { | |
1259 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1260 | return PHY_ERROR; | |
1261 | } | |
1262 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { | |
1263 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1264 | return PHY_ERROR; | |
1265 | } | |
1266 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { | |
1267 | printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); | |
1268 | return PHY_ERROR; | |
1269 | } | |
1270 | } | |
1271 | ||
eb91f61b AA |
1272 | /* some phys clear out pause advertisment on reset, set it back */ |
1273 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); | |
1da177e4 LT |
1274 | |
1275 | /* restart auto negotiation */ | |
1276 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
1277 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
1278 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1279 | return PHY_ERROR; | |
1280 | } | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static void nv_start_rx(struct net_device *dev) | |
1286 | { | |
ac9c1897 | 1287 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1288 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1289 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1290 | |
1291 | dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); | |
1292 | /* Already running? Stop it. */ | |
f35723ec AA |
1293 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1294 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1295 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1296 | pci_push(base); |
1297 | } | |
1298 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1299 | pci_push(base); | |
f35723ec AA |
1300 | rx_ctrl |= NVREG_RCVCTL_START; |
1301 | if (np->mac_in_use) | |
1302 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; | |
1303 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1304 | dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1305 | dev->name, np->duplex, np->linkspeed); | |
1306 | pci_push(base); | |
1307 | } | |
1308 | ||
1309 | static void nv_stop_rx(struct net_device *dev) | |
1310 | { | |
f35723ec | 1311 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1312 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1313 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 LT |
1314 | |
1315 | dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); | |
f35723ec AA |
1316 | if (!np->mac_in_use) |
1317 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1318 | else | |
1319 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1320 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1321 | reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1322 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, | |
1323 | KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); | |
1324 | ||
1325 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1326 | if (!np->mac_in_use) |
1327 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1328 | } |
1329 | ||
1330 | static void nv_start_tx(struct net_device *dev) | |
1331 | { | |
f35723ec | 1332 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1333 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1334 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1335 | |
1336 | dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); | |
f35723ec AA |
1337 | tx_ctrl |= NVREG_XMITCTL_START; |
1338 | if (np->mac_in_use) | |
1339 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1340 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1341 | pci_push(base); |
1342 | } | |
1343 | ||
1344 | static void nv_stop_tx(struct net_device *dev) | |
1345 | { | |
f35723ec | 1346 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1347 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1348 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 LT |
1349 | |
1350 | dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); | |
f35723ec AA |
1351 | if (!np->mac_in_use) |
1352 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1353 | else | |
1354 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1355 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1356 | reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1357 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, | |
1358 | KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); | |
1359 | ||
1360 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1361 | if (!np->mac_in_use) |
1362 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1363 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1364 | } |
1365 | ||
36b30ea9 JG |
1366 | static void nv_start_rxtx(struct net_device *dev) |
1367 | { | |
1368 | nv_start_rx(dev); | |
1369 | nv_start_tx(dev); | |
1370 | } | |
1371 | ||
1372 | static void nv_stop_rxtx(struct net_device *dev) | |
1373 | { | |
1374 | nv_stop_rx(dev); | |
1375 | nv_stop_tx(dev); | |
1376 | } | |
1377 | ||
1da177e4 LT |
1378 | static void nv_txrx_reset(struct net_device *dev) |
1379 | { | |
ac9c1897 | 1380 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1381 | u8 __iomem *base = get_hwbase(dev); |
1382 | ||
1383 | dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); | |
8a4ae7f2 | 1384 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1385 | pci_push(base); |
1386 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1387 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1388 | pci_push(base); |
1389 | } | |
1390 | ||
86a0f043 AA |
1391 | static void nv_mac_reset(struct net_device *dev) |
1392 | { | |
1393 | struct fe_priv *np = netdev_priv(dev); | |
1394 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1395 | u32 temp1, temp2, temp3; |
86a0f043 AA |
1396 | |
1397 | dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); | |
4e84f9b1 | 1398 | |
86a0f043 AA |
1399 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1400 | pci_push(base); | |
4e84f9b1 AA |
1401 | |
1402 | /* save registers since they will be cleared on reset */ | |
1403 | temp1 = readl(base + NvRegMacAddrA); | |
1404 | temp2 = readl(base + NvRegMacAddrB); | |
1405 | temp3 = readl(base + NvRegTransmitPoll); | |
1406 | ||
86a0f043 AA |
1407 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1408 | pci_push(base); | |
1409 | udelay(NV_MAC_RESET_DELAY); | |
1410 | writel(0, base + NvRegMacReset); | |
1411 | pci_push(base); | |
1412 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1413 | |
1414 | /* restore saved registers */ | |
1415 | writel(temp1, base + NvRegMacAddrA); | |
1416 | writel(temp2, base + NvRegMacAddrB); | |
1417 | writel(temp3, base + NvRegTransmitPoll); | |
1418 | ||
86a0f043 AA |
1419 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1420 | pci_push(base); | |
1421 | } | |
1422 | ||
57fff698 AA |
1423 | static void nv_get_hw_stats(struct net_device *dev) |
1424 | { | |
1425 | struct fe_priv *np = netdev_priv(dev); | |
1426 | u8 __iomem *base = get_hwbase(dev); | |
1427 | ||
1428 | np->estats.tx_bytes += readl(base + NvRegTxCnt); | |
1429 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1430 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1431 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1432 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1433 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1434 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1435 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1436 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1437 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1438 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1439 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1440 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1441 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1442 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1443 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1444 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1445 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1446 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1447 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1448 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1449 | np->estats.rx_packets = | |
1450 | np->estats.rx_unicast + | |
1451 | np->estats.rx_multicast + | |
1452 | np->estats.rx_broadcast; | |
1453 | np->estats.rx_errors_total = | |
1454 | np->estats.rx_crc_errors + | |
1455 | np->estats.rx_over_errors + | |
1456 | np->estats.rx_frame_error + | |
1457 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1458 | np->estats.rx_late_collision + | |
1459 | np->estats.rx_runt + | |
1460 | np->estats.rx_frame_too_long; | |
1461 | np->estats.tx_errors_total = | |
1462 | np->estats.tx_late_collision + | |
1463 | np->estats.tx_fifo_errors + | |
1464 | np->estats.tx_carrier_errors + | |
1465 | np->estats.tx_excess_deferral + | |
1466 | np->estats.tx_retry_error; | |
1467 | ||
1468 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1469 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1470 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1471 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1472 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1473 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1474 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
1475 | } | |
1476 | } | |
1477 | ||
1da177e4 LT |
1478 | /* |
1479 | * nv_get_stats: dev->get_stats function | |
1480 | * Get latest stats value from the nic. | |
1481 | * Called with read_lock(&dev_base_lock) held for read - | |
1482 | * only synchronized against unregister_netdevice. | |
1483 | */ | |
1484 | static struct net_device_stats *nv_get_stats(struct net_device *dev) | |
1485 | { | |
ac9c1897 | 1486 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1487 | |
21828163 AA |
1488 | /* If the nic supports hw counters then retrieve latest values */ |
1489 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) { | |
1490 | nv_get_hw_stats(dev); | |
1491 | ||
1492 | /* copy to net_device stats */ | |
8148ff45 JG |
1493 | dev->stats.tx_bytes = np->estats.tx_bytes; |
1494 | dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors; | |
1495 | dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors; | |
1496 | dev->stats.rx_crc_errors = np->estats.rx_crc_errors; | |
1497 | dev->stats.rx_over_errors = np->estats.rx_over_errors; | |
1498 | dev->stats.rx_errors = np->estats.rx_errors_total; | |
1499 | dev->stats.tx_errors = np->estats.tx_errors_total; | |
21828163 | 1500 | } |
8148ff45 JG |
1501 | |
1502 | return &dev->stats; | |
1da177e4 LT |
1503 | } |
1504 | ||
1505 | /* | |
1506 | * nv_alloc_rx: fill rx ring entries. | |
1507 | * Return 1 if the allocations for the skbs failed and the | |
1508 | * rx engine is without Available descriptors | |
1509 | */ | |
1510 | static int nv_alloc_rx(struct net_device *dev) | |
1511 | { | |
ac9c1897 | 1512 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1513 | struct ring_desc* less_rx; |
1da177e4 | 1514 | |
86b22b0d AA |
1515 | less_rx = np->get_rx.orig; |
1516 | if (less_rx-- == np->first_rx.orig) | |
1517 | less_rx = np->last_rx.orig; | |
761fcd9e | 1518 | |
86b22b0d AA |
1519 | while (np->put_rx.orig != less_rx) { |
1520 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
1521 | if (skb) { | |
86b22b0d | 1522 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1523 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1524 | skb->data, | |
8b5be268 | 1525 | skb_tailroom(skb), |
4305b541 | 1526 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1527 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1528 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1529 | wmb(); | |
1530 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1531 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 1532 | np->put_rx.orig = np->first_rx.orig; |
b01867cb | 1533 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 1534 | np->put_rx_ctx = np->first_rx_ctx; |
761fcd9e | 1535 | } else { |
86b22b0d | 1536 | return 1; |
761fcd9e | 1537 | } |
86b22b0d AA |
1538 | } |
1539 | return 0; | |
1540 | } | |
1541 | ||
1542 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1543 | { | |
1544 | struct fe_priv *np = netdev_priv(dev); | |
1545 | struct ring_desc_ex* less_rx; | |
1546 | ||
1547 | less_rx = np->get_rx.ex; | |
1548 | if (less_rx-- == np->first_rx.ex) | |
1549 | less_rx = np->last_rx.ex; | |
761fcd9e | 1550 | |
86b22b0d AA |
1551 | while (np->put_rx.ex != less_rx) { |
1552 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); | |
0d63fb32 | 1553 | if (skb) { |
761fcd9e | 1554 | np->put_rx_ctx->skb = skb; |
4305b541 ACM |
1555 | np->put_rx_ctx->dma = pci_map_single(np->pci_dev, |
1556 | skb->data, | |
8b5be268 | 1557 | skb_tailroom(skb), |
4305b541 | 1558 | PCI_DMA_FROMDEVICE); |
8b5be268 | 1559 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1560 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1561 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1562 | wmb(); |
1563 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1564 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 1565 | np->put_rx.ex = np->first_rx.ex; |
b01867cb | 1566 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
0d63fb32 | 1567 | np->put_rx_ctx = np->first_rx_ctx; |
1da177e4 | 1568 | } else { |
0d63fb32 | 1569 | return 1; |
ee73362c | 1570 | } |
1da177e4 | 1571 | } |
1da177e4 LT |
1572 | return 0; |
1573 | } | |
1574 | ||
e27cdba5 SH |
1575 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
1576 | #ifdef CONFIG_FORCEDETH_NAPI | |
1577 | static void nv_do_rx_refill(unsigned long data) | |
1578 | { | |
1579 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 1580 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
1581 | |
1582 | /* Just reschedule NAPI rx processing */ | |
bea3348e | 1583 | netif_rx_schedule(dev, &np->napi); |
e27cdba5 SH |
1584 | } |
1585 | #else | |
1da177e4 LT |
1586 | static void nv_do_rx_refill(unsigned long data) |
1587 | { | |
1588 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 1589 | struct fe_priv *np = netdev_priv(dev); |
86b22b0d | 1590 | int retcode; |
1da177e4 | 1591 | |
84b3932b AA |
1592 | if (!using_multi_irqs(dev)) { |
1593 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1594 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1595 | else | |
a7475906 | 1596 | disable_irq(np->pci_dev->irq); |
d33a73c8 AA |
1597 | } else { |
1598 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1599 | } | |
36b30ea9 | 1600 | if (!nv_optimized(np)) |
86b22b0d AA |
1601 | retcode = nv_alloc_rx(dev); |
1602 | else | |
1603 | retcode = nv_alloc_rx_optimized(dev); | |
1604 | if (retcode) { | |
84b3932b | 1605 | spin_lock_irq(&np->lock); |
1da177e4 LT |
1606 | if (!np->in_shutdown) |
1607 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
84b3932b | 1608 | spin_unlock_irq(&np->lock); |
1da177e4 | 1609 | } |
84b3932b AA |
1610 | if (!using_multi_irqs(dev)) { |
1611 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1612 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1613 | else | |
a7475906 | 1614 | enable_irq(np->pci_dev->irq); |
d33a73c8 AA |
1615 | } else { |
1616 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1617 | } | |
1da177e4 | 1618 | } |
e27cdba5 | 1619 | #endif |
1da177e4 | 1620 | |
f3b197ac | 1621 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1622 | { |
ac9c1897 | 1623 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1624 | int i; |
36b30ea9 | 1625 | |
761fcd9e | 1626 | np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
36b30ea9 JG |
1627 | |
1628 | if (!nv_optimized(np)) | |
761fcd9e AA |
1629 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1630 | else | |
1631 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
1632 | np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; | |
1633 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; | |
1da177e4 | 1634 | |
761fcd9e | 1635 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1636 | if (!nv_optimized(np)) { |
f82a9352 | 1637 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1638 | np->rx_ring.orig[i].buf = 0; |
1639 | } else { | |
f82a9352 | 1640 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1641 | np->rx_ring.ex[i].txvlan = 0; |
1642 | np->rx_ring.ex[i].bufhigh = 0; | |
1643 | np->rx_ring.ex[i].buflow = 0; | |
1644 | } | |
1645 | np->rx_skb[i].skb = NULL; | |
1646 | np->rx_skb[i].dma = 0; | |
1647 | } | |
d81c0983 MS |
1648 | } |
1649 | ||
1650 | static void nv_init_tx(struct net_device *dev) | |
1651 | { | |
ac9c1897 | 1652 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1653 | int i; |
36b30ea9 | 1654 | |
761fcd9e | 1655 | np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
36b30ea9 JG |
1656 | |
1657 | if (!nv_optimized(np)) | |
761fcd9e AA |
1658 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1659 | else | |
1660 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
1661 | np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; | |
1662 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; | |
3b446c3e AA |
1663 | np->tx_pkts_in_progress = 0; |
1664 | np->tx_change_owner = NULL; | |
1665 | np->tx_end_flip = NULL; | |
d81c0983 | 1666 | |
eafa59f6 | 1667 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1668 | if (!nv_optimized(np)) { |
f82a9352 | 1669 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1670 | np->tx_ring.orig[i].buf = 0; |
1671 | } else { | |
f82a9352 | 1672 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1673 | np->tx_ring.ex[i].txvlan = 0; |
1674 | np->tx_ring.ex[i].bufhigh = 0; | |
1675 | np->tx_ring.ex[i].buflow = 0; | |
1676 | } | |
1677 | np->tx_skb[i].skb = NULL; | |
1678 | np->tx_skb[i].dma = 0; | |
3b446c3e AA |
1679 | np->tx_skb[i].dma_len = 0; |
1680 | np->tx_skb[i].first_tx_desc = NULL; | |
1681 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1682 | } |
d81c0983 MS |
1683 | } |
1684 | ||
1685 | static int nv_init_ring(struct net_device *dev) | |
1686 | { | |
86b22b0d AA |
1687 | struct fe_priv *np = netdev_priv(dev); |
1688 | ||
d81c0983 MS |
1689 | nv_init_tx(dev); |
1690 | nv_init_rx(dev); | |
36b30ea9 JG |
1691 | |
1692 | if (!nv_optimized(np)) | |
86b22b0d AA |
1693 | return nv_alloc_rx(dev); |
1694 | else | |
1695 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1696 | } |
1697 | ||
761fcd9e | 1698 | static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb) |
ac9c1897 AA |
1699 | { |
1700 | struct fe_priv *np = netdev_priv(dev); | |
fa45459e | 1701 | |
761fcd9e AA |
1702 | if (tx_skb->dma) { |
1703 | pci_unmap_page(np->pci_dev, tx_skb->dma, | |
1704 | tx_skb->dma_len, | |
fa45459e | 1705 | PCI_DMA_TODEVICE); |
761fcd9e | 1706 | tx_skb->dma = 0; |
fa45459e | 1707 | } |
761fcd9e AA |
1708 | if (tx_skb->skb) { |
1709 | dev_kfree_skb_any(tx_skb->skb); | |
1710 | tx_skb->skb = NULL; | |
fa45459e AA |
1711 | return 1; |
1712 | } else { | |
1713 | return 0; | |
ac9c1897 | 1714 | } |
ac9c1897 AA |
1715 | } |
1716 | ||
1da177e4 LT |
1717 | static void nv_drain_tx(struct net_device *dev) |
1718 | { | |
ac9c1897 AA |
1719 | struct fe_priv *np = netdev_priv(dev); |
1720 | unsigned int i; | |
f3b197ac | 1721 | |
eafa59f6 | 1722 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1723 | if (!nv_optimized(np)) { |
f82a9352 | 1724 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1725 | np->tx_ring.orig[i].buf = 0; |
1726 | } else { | |
f82a9352 | 1727 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1728 | np->tx_ring.ex[i].txvlan = 0; |
1729 | np->tx_ring.ex[i].bufhigh = 0; | |
1730 | np->tx_ring.ex[i].buflow = 0; | |
1731 | } | |
1732 | if (nv_release_txskb(dev, &np->tx_skb[i])) | |
8148ff45 | 1733 | dev->stats.tx_dropped++; |
3b446c3e AA |
1734 | np->tx_skb[i].dma = 0; |
1735 | np->tx_skb[i].dma_len = 0; | |
1736 | np->tx_skb[i].first_tx_desc = NULL; | |
1737 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 1738 | } |
3b446c3e AA |
1739 | np->tx_pkts_in_progress = 0; |
1740 | np->tx_change_owner = NULL; | |
1741 | np->tx_end_flip = NULL; | |
1da177e4 LT |
1742 | } |
1743 | ||
1744 | static void nv_drain_rx(struct net_device *dev) | |
1745 | { | |
ac9c1897 | 1746 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1747 | int i; |
761fcd9e | 1748 | |
eafa59f6 | 1749 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1750 | if (!nv_optimized(np)) { |
f82a9352 | 1751 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1752 | np->rx_ring.orig[i].buf = 0; |
1753 | } else { | |
f82a9352 | 1754 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1755 | np->rx_ring.ex[i].txvlan = 0; |
1756 | np->rx_ring.ex[i].bufhigh = 0; | |
1757 | np->rx_ring.ex[i].buflow = 0; | |
1758 | } | |
1da177e4 | 1759 | wmb(); |
761fcd9e AA |
1760 | if (np->rx_skb[i].skb) { |
1761 | pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, | |
4305b541 ACM |
1762 | (skb_end_pointer(np->rx_skb[i].skb) - |
1763 | np->rx_skb[i].skb->data), | |
1764 | PCI_DMA_FROMDEVICE); | |
761fcd9e AA |
1765 | dev_kfree_skb(np->rx_skb[i].skb); |
1766 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
1767 | } |
1768 | } | |
1769 | } | |
1770 | ||
36b30ea9 | 1771 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
1772 | { |
1773 | nv_drain_tx(dev); | |
1774 | nv_drain_rx(dev); | |
1775 | } | |
1776 | ||
761fcd9e AA |
1777 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
1778 | { | |
1779 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
1780 | } | |
1781 | ||
a433686c AA |
1782 | static void nv_legacybackoff_reseed(struct net_device *dev) |
1783 | { | |
1784 | u8 __iomem *base = get_hwbase(dev); | |
1785 | u32 reg; | |
1786 | u32 low; | |
1787 | int tx_status = 0; | |
1788 | ||
1789 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
1790 | get_random_bytes(&low, sizeof(low)); | |
1791 | reg |= low & NVREG_SLOTTIME_MASK; | |
1792 | ||
1793 | /* Need to stop tx before change takes effect. | |
1794 | * Caller has already gained np->lock. | |
1795 | */ | |
1796 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
1797 | if (tx_status) | |
1798 | nv_stop_tx(dev); | |
1799 | nv_stop_rx(dev); | |
1800 | writel(reg, base + NvRegSlotTime); | |
1801 | if (tx_status) | |
1802 | nv_start_tx(dev); | |
1803 | nv_start_rx(dev); | |
1804 | } | |
1805 | ||
1806 | /* Gear Backoff Seeds */ | |
1807 | #define BACKOFF_SEEDSET_ROWS 8 | |
1808 | #define BACKOFF_SEEDSET_LFSRS 15 | |
1809 | ||
1810 | /* Known Good seed sets */ | |
1811 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
1812 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
1813 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
1814 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
1815 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
1816 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
1817 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
1818 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
1819 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}}; | |
1820 | ||
1821 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
1822 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
1823 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
1824 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
1825 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
1826 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
1827 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
1828 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
1829 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}}; | |
1830 | ||
1831 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
1832 | { | |
1833 | u8 __iomem *base = get_hwbase(dev); | |
1834 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
1835 | u32 temp, seedset, combinedSeed; | |
1836 | int i; | |
1837 | ||
1838 | /* Setup seed for free running LFSR */ | |
1839 | /* We are going to read the time stamp counter 3 times | |
1840 | and swizzle bits around to increase randomness */ | |
1841 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
1842 | miniseed1 &= 0x0fff; | |
1843 | if (miniseed1 == 0) | |
1844 | miniseed1 = 0xabc; | |
1845 | ||
1846 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
1847 | miniseed2 &= 0x0fff; | |
1848 | if (miniseed2 == 0) | |
1849 | miniseed2 = 0xabc; | |
1850 | miniseed2_reversed = | |
1851 | ((miniseed2 & 0xF00) >> 8) | | |
1852 | (miniseed2 & 0x0F0) | | |
1853 | ((miniseed2 & 0x00F) << 8); | |
1854 | ||
1855 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
1856 | miniseed3 &= 0x0fff; | |
1857 | if (miniseed3 == 0) | |
1858 | miniseed3 = 0xabc; | |
1859 | miniseed3_reversed = | |
1860 | ((miniseed3 & 0xF00) >> 8) | | |
1861 | (miniseed3 & 0x0F0) | | |
1862 | ((miniseed3 & 0x00F) << 8); | |
1863 | ||
1864 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
1865 | (miniseed2 ^ miniseed3_reversed); | |
1866 | ||
1867 | /* Seeds can not be zero */ | |
1868 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
1869 | combinedSeed |= 0x08; | |
1870 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
1871 | combinedSeed |= 0x8000; | |
1872 | ||
1873 | /* No need to disable tx here */ | |
1874 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
1875 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
1876 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
1877 | writel(temp,base + NvRegBackOffControl); | |
1878 | ||
1879 | /* Setup seeds for all gear LFSRs. */ | |
1880 | get_random_bytes(&seedset, sizeof(seedset)); | |
1881 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
1882 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) | |
1883 | { | |
1884 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); | |
1885 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
1886 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
1887 | writel(temp, base + NvRegBackOffControl); | |
1888 | } | |
1889 | } | |
1890 | ||
1da177e4 LT |
1891 | /* |
1892 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 1893 | * Called with netif_tx_lock held. |
1da177e4 LT |
1894 | */ |
1895 | static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1896 | { | |
ac9c1897 | 1897 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 1898 | u32 tx_flags = 0; |
ac9c1897 AA |
1899 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
1900 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 1901 | unsigned int i; |
fa45459e AA |
1902 | u32 offset = 0; |
1903 | u32 bcnt; | |
1904 | u32 size = skb->len-skb->data_len; | |
1905 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
761fcd9e | 1906 | u32 empty_slots; |
86b22b0d AA |
1907 | struct ring_desc* put_tx; |
1908 | struct ring_desc* start_tx; | |
1909 | struct ring_desc* prev_tx; | |
761fcd9e | 1910 | struct nv_skb_map* prev_tx_ctx; |
bd6ca637 | 1911 | unsigned long flags; |
fa45459e AA |
1912 | |
1913 | /* add fragments to entries count */ | |
1914 | for (i = 0; i < fragments; i++) { | |
1915 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
1916 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
1917 | } | |
ac9c1897 | 1918 | |
761fcd9e | 1919 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 1920 | if (unlikely(empty_slots <= entries)) { |
bd6ca637 | 1921 | spin_lock_irqsave(&np->lock, flags); |
ac9c1897 | 1922 | netif_stop_queue(dev); |
aaa37d2d | 1923 | np->tx_stop = 1; |
bd6ca637 | 1924 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
1925 | return NETDEV_TX_BUSY; |
1926 | } | |
1da177e4 | 1927 | |
86b22b0d | 1928 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 1929 | |
fa45459e AA |
1930 | /* setup the header buffer */ |
1931 | do { | |
761fcd9e AA |
1932 | prev_tx = put_tx; |
1933 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 1934 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e | 1935 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
fa45459e | 1936 | PCI_DMA_TODEVICE); |
761fcd9e | 1937 | np->put_tx_ctx->dma_len = bcnt; |
86b22b0d AA |
1938 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
1939 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 1940 | |
fa45459e AA |
1941 | tx_flags = np->tx_flags; |
1942 | offset += bcnt; | |
1943 | size -= bcnt; | |
445583b8 | 1944 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 1945 | put_tx = np->first_tx.orig; |
445583b8 | 1946 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 1947 | np->put_tx_ctx = np->first_tx_ctx; |
f82a9352 | 1948 | } while (size); |
fa45459e AA |
1949 | |
1950 | /* setup the fragments */ | |
1951 | for (i = 0; i < fragments; i++) { | |
1952 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
1953 | u32 size = frag->size; | |
1954 | offset = 0; | |
1955 | ||
1956 | do { | |
761fcd9e AA |
1957 | prev_tx = put_tx; |
1958 | prev_tx_ctx = np->put_tx_ctx; | |
fa45459e | 1959 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
761fcd9e AA |
1960 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
1961 | PCI_DMA_TODEVICE); | |
1962 | np->put_tx_ctx->dma_len = bcnt; | |
86b22b0d AA |
1963 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
1964 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 1965 | |
fa45459e AA |
1966 | offset += bcnt; |
1967 | size -= bcnt; | |
445583b8 | 1968 | if (unlikely(put_tx++ == np->last_tx.orig)) |
86b22b0d | 1969 | put_tx = np->first_tx.orig; |
445583b8 | 1970 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 1971 | np->put_tx_ctx = np->first_tx_ctx; |
fa45459e AA |
1972 | } while (size); |
1973 | } | |
ac9c1897 | 1974 | |
fa45459e | 1975 | /* set last fragment flag */ |
86b22b0d | 1976 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 1977 | |
761fcd9e AA |
1978 | /* save skb in this slot's context area */ |
1979 | prev_tx_ctx->skb = skb; | |
fa45459e | 1980 | |
89114afd | 1981 | if (skb_is_gso(skb)) |
7967168c | 1982 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 1983 | else |
1d39ed56 | 1984 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 1985 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 1986 | |
bd6ca637 | 1987 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 1988 | |
fa45459e | 1989 | /* set tx flags */ |
86b22b0d AA |
1990 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
1991 | np->put_tx.orig = put_tx; | |
1da177e4 | 1992 | |
bd6ca637 | 1993 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e AA |
1994 | |
1995 | dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n", | |
1996 | dev->name, entries, tx_flags_extra); | |
1da177e4 LT |
1997 | { |
1998 | int j; | |
1999 | for (j=0; j<64; j++) { | |
2000 | if ((j%16) == 0) | |
2001 | dprintk("\n%03x:", j); | |
2002 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2003 | } | |
2004 | dprintk("\n"); | |
2005 | } | |
2006 | ||
1da177e4 | 2007 | dev->trans_start = jiffies; |
8a4ae7f2 | 2008 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2009 | return NETDEV_TX_OK; |
1da177e4 LT |
2010 | } |
2011 | ||
86b22b0d AA |
2012 | static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) |
2013 | { | |
2014 | struct fe_priv *np = netdev_priv(dev); | |
2015 | u32 tx_flags = 0; | |
445583b8 | 2016 | u32 tx_flags_extra; |
86b22b0d AA |
2017 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2018 | unsigned int i; | |
2019 | u32 offset = 0; | |
2020 | u32 bcnt; | |
2021 | u32 size = skb->len-skb->data_len; | |
2022 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2023 | u32 empty_slots; | |
86b22b0d AA |
2024 | struct ring_desc_ex* put_tx; |
2025 | struct ring_desc_ex* start_tx; | |
2026 | struct ring_desc_ex* prev_tx; | |
2027 | struct nv_skb_map* prev_tx_ctx; | |
3b446c3e | 2028 | struct nv_skb_map* start_tx_ctx; |
bd6ca637 | 2029 | unsigned long flags; |
86b22b0d AA |
2030 | |
2031 | /* add fragments to entries count */ | |
2032 | for (i = 0; i < fragments; i++) { | |
2033 | entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + | |
2034 | ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
2035 | } | |
2036 | ||
2037 | empty_slots = nv_get_empty_tx_slots(np); | |
445583b8 | 2038 | if (unlikely(empty_slots <= entries)) { |
bd6ca637 | 2039 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2040 | netif_stop_queue(dev); |
aaa37d2d | 2041 | np->tx_stop = 1; |
bd6ca637 | 2042 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2043 | return NETDEV_TX_BUSY; |
2044 | } | |
2045 | ||
2046 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2047 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2048 | |
2049 | /* setup the header buffer */ | |
2050 | do { | |
2051 | prev_tx = put_tx; | |
2052 | prev_tx_ctx = np->put_tx_ctx; | |
2053 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2054 | np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, | |
2055 | PCI_DMA_TODEVICE); | |
2056 | np->put_tx_ctx->dma_len = bcnt; | |
5bb7ea26 AV |
2057 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2058 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2059 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2060 | |
2061 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2062 | offset += bcnt; |
2063 | size -= bcnt; | |
445583b8 | 2064 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2065 | put_tx = np->first_tx.ex; |
445583b8 | 2066 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2067 | np->put_tx_ctx = np->first_tx_ctx; |
2068 | } while (size); | |
2069 | ||
2070 | /* setup the fragments */ | |
2071 | for (i = 0; i < fragments; i++) { | |
2072 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2073 | u32 size = frag->size; | |
2074 | offset = 0; | |
2075 | ||
2076 | do { | |
2077 | prev_tx = put_tx; | |
2078 | prev_tx_ctx = np->put_tx_ctx; | |
2079 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
2080 | np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, | |
2081 | PCI_DMA_TODEVICE); | |
2082 | np->put_tx_ctx->dma_len = bcnt; | |
5bb7ea26 AV |
2083 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2084 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2085 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2086 | |
86b22b0d AA |
2087 | offset += bcnt; |
2088 | size -= bcnt; | |
445583b8 | 2089 | if (unlikely(put_tx++ == np->last_tx.ex)) |
86b22b0d | 2090 | put_tx = np->first_tx.ex; |
445583b8 | 2091 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2092 | np->put_tx_ctx = np->first_tx_ctx; |
2093 | } while (size); | |
2094 | } | |
2095 | ||
2096 | /* set last fragment flag */ | |
445583b8 | 2097 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2098 | |
2099 | /* save skb in this slot's context area */ | |
2100 | prev_tx_ctx->skb = skb; | |
2101 | ||
2102 | if (skb_is_gso(skb)) | |
2103 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2104 | else | |
2105 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2106 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2107 | ||
2108 | /* vlan tag */ | |
445583b8 AA |
2109 | if (likely(!np->vlangrp)) { |
2110 | start_tx->txvlan = 0; | |
2111 | } else { | |
2112 | if (vlan_tx_tag_present(skb)) | |
2113 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb)); | |
2114 | else | |
2115 | start_tx->txvlan = 0; | |
86b22b0d AA |
2116 | } |
2117 | ||
bd6ca637 | 2118 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2119 | |
3b446c3e AA |
2120 | if (np->tx_limit) { |
2121 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2122 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2123 | * to that descriptor and also for next skb_map element. | |
2124 | */ | |
2125 | ||
2126 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2127 | if (!np->tx_change_owner) | |
2128 | np->tx_change_owner = start_tx_ctx; | |
2129 | ||
2130 | /* remove VALID bit */ | |
2131 | tx_flags &= ~NV_TX2_VALID; | |
2132 | start_tx_ctx->first_tx_desc = start_tx; | |
2133 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2134 | np->tx_end_flip = np->put_tx_ctx; | |
2135 | } else { | |
2136 | np->tx_pkts_in_progress++; | |
2137 | } | |
2138 | } | |
2139 | ||
86b22b0d | 2140 | /* set tx flags */ |
86b22b0d AA |
2141 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2142 | np->put_tx.ex = put_tx; | |
2143 | ||
bd6ca637 | 2144 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2145 | |
2146 | dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n", | |
2147 | dev->name, entries, tx_flags_extra); | |
2148 | { | |
2149 | int j; | |
2150 | for (j=0; j<64; j++) { | |
2151 | if ((j%16) == 0) | |
2152 | dprintk("\n%03x:", j); | |
2153 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2154 | } | |
2155 | dprintk("\n"); | |
2156 | } | |
2157 | ||
2158 | dev->trans_start = jiffies; | |
2159 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
86b22b0d AA |
2160 | return NETDEV_TX_OK; |
2161 | } | |
2162 | ||
3b446c3e AA |
2163 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2164 | { | |
2165 | struct fe_priv *np = netdev_priv(dev); | |
2166 | ||
2167 | np->tx_pkts_in_progress--; | |
2168 | if (np->tx_change_owner) { | |
30ecce90 AV |
2169 | np->tx_change_owner->first_tx_desc->flaglen |= |
2170 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2171 | np->tx_pkts_in_progress++; |
2172 | ||
2173 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2174 | if (np->tx_change_owner == np->tx_end_flip) | |
2175 | np->tx_change_owner = NULL; | |
2176 | ||
2177 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2178 | } | |
2179 | } | |
2180 | ||
1da177e4 LT |
2181 | /* |
2182 | * nv_tx_done: check for completed packets, release the skbs. | |
2183 | * | |
2184 | * Caller must own np->lock. | |
2185 | */ | |
2186 | static void nv_tx_done(struct net_device *dev) | |
2187 | { | |
ac9c1897 | 2188 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2189 | u32 flags; |
aaa37d2d | 2190 | struct ring_desc* orig_get_tx = np->get_tx.orig; |
1da177e4 | 2191 | |
445583b8 AA |
2192 | while ((np->get_tx.orig != np->put_tx.orig) && |
2193 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) { | |
1da177e4 | 2194 | |
761fcd9e AA |
2195 | dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n", |
2196 | dev->name, flags); | |
445583b8 AA |
2197 | |
2198 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
2199 | np->get_tx_ctx->dma_len, | |
2200 | PCI_DMA_TODEVICE); | |
2201 | np->get_tx_ctx->dma = 0; | |
2202 | ||
1da177e4 | 2203 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2204 | if (flags & NV_TX_LASTPACKET) { |
445583b8 | 2205 | if (flags & NV_TX_ERROR) { |
f82a9352 | 2206 | if (flags & NV_TX_UNDERFLOW) |
8148ff45 | 2207 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2208 | if (flags & NV_TX_CARRIERLOST) |
8148ff45 | 2209 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2210 | if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK)) |
2211 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2212 | dev->stats.tx_errors++; |
ac9c1897 | 2213 | } else { |
8148ff45 JG |
2214 | dev->stats.tx_packets++; |
2215 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
ac9c1897 | 2216 | } |
445583b8 AA |
2217 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2218 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
2219 | } |
2220 | } else { | |
f82a9352 | 2221 | if (flags & NV_TX2_LASTPACKET) { |
445583b8 | 2222 | if (flags & NV_TX2_ERROR) { |
f82a9352 | 2223 | if (flags & NV_TX2_UNDERFLOW) |
8148ff45 | 2224 | dev->stats.tx_fifo_errors++; |
f82a9352 | 2225 | if (flags & NV_TX2_CARRIERLOST) |
8148ff45 | 2226 | dev->stats.tx_carrier_errors++; |
a433686c AA |
2227 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) |
2228 | nv_legacybackoff_reseed(dev); | |
8148ff45 | 2229 | dev->stats.tx_errors++; |
ac9c1897 | 2230 | } else { |
8148ff45 JG |
2231 | dev->stats.tx_packets++; |
2232 | dev->stats.tx_bytes += np->get_tx_ctx->skb->len; | |
f3b197ac | 2233 | } |
445583b8 AA |
2234 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2235 | np->get_tx_ctx->skb = NULL; | |
1da177e4 LT |
2236 | } |
2237 | } | |
445583b8 | 2238 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
86b22b0d | 2239 | np->get_tx.orig = np->first_tx.orig; |
445583b8 | 2240 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
86b22b0d AA |
2241 | np->get_tx_ctx = np->first_tx_ctx; |
2242 | } | |
445583b8 | 2243 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2244 | np->tx_stop = 0; |
86b22b0d | 2245 | netif_wake_queue(dev); |
aaa37d2d | 2246 | } |
86b22b0d AA |
2247 | } |
2248 | ||
4e16ed1b | 2249 | static void nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2250 | { |
2251 | struct fe_priv *np = netdev_priv(dev); | |
2252 | u32 flags; | |
aaa37d2d | 2253 | struct ring_desc_ex* orig_get_tx = np->get_tx.ex; |
86b22b0d | 2254 | |
445583b8 | 2255 | while ((np->get_tx.ex != np->put_tx.ex) && |
4e16ed1b AA |
2256 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) && |
2257 | (limit-- > 0)) { | |
86b22b0d AA |
2258 | |
2259 | dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n", | |
2260 | dev->name, flags); | |
445583b8 AA |
2261 | |
2262 | pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, | |
2263 | np->get_tx_ctx->dma_len, | |
2264 | PCI_DMA_TODEVICE); | |
2265 | np->get_tx_ctx->dma = 0; | |
2266 | ||
86b22b0d | 2267 | if (flags & NV_TX2_LASTPACKET) { |
21828163 | 2268 | if (!(flags & NV_TX2_ERROR)) |
8148ff45 | 2269 | dev->stats.tx_packets++; |
a433686c AA |
2270 | else { |
2271 | if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
2272 | if (np->driver_data & DEV_HAS_GEAR_MODE) | |
2273 | nv_gear_backoff_reseed(dev); | |
2274 | else | |
2275 | nv_legacybackoff_reseed(dev); | |
2276 | } | |
2277 | } | |
2278 | ||
445583b8 AA |
2279 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2280 | np->get_tx_ctx->skb = NULL; | |
3b446c3e AA |
2281 | |
2282 | if (np->tx_limit) { | |
2283 | nv_tx_flip_ownership(dev); | |
2284 | } | |
761fcd9e | 2285 | } |
445583b8 | 2286 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
86b22b0d | 2287 | np->get_tx.ex = np->first_tx.ex; |
445583b8 | 2288 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
761fcd9e | 2289 | np->get_tx_ctx = np->first_tx_ctx; |
1da177e4 | 2290 | } |
445583b8 | 2291 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2292 | np->tx_stop = 0; |
1da177e4 | 2293 | netif_wake_queue(dev); |
aaa37d2d | 2294 | } |
1da177e4 LT |
2295 | } |
2296 | ||
2297 | /* | |
2298 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2299 | * Called with netif_tx_lock held. |
1da177e4 LT |
2300 | */ |
2301 | static void nv_tx_timeout(struct net_device *dev) | |
2302 | { | |
ac9c1897 | 2303 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2304 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
2305 | u32 status; |
2306 | ||
2307 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2308 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2309 | else | |
2310 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2311 | |
d33a73c8 | 2312 | printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
1da177e4 | 2313 | |
c2dba06d MS |
2314 | { |
2315 | int i; | |
2316 | ||
761fcd9e AA |
2317 | printk(KERN_INFO "%s: Ring at %lx\n", |
2318 | dev->name, (unsigned long)np->ring_addr); | |
c2dba06d | 2319 | printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
86a0f043 | 2320 | for (i=0;i<=np->register_size;i+= 32) { |
c2dba06d MS |
2321 | printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2322 | i, | |
2323 | readl(base + i + 0), readl(base + i + 4), | |
2324 | readl(base + i + 8), readl(base + i + 12), | |
2325 | readl(base + i + 16), readl(base + i + 20), | |
2326 | readl(base + i + 24), readl(base + i + 28)); | |
2327 | } | |
2328 | printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); | |
eafa59f6 | 2329 | for (i=0;i<np->tx_ring_size;i+= 4) { |
36b30ea9 | 2330 | if (!nv_optimized(np)) { |
ee73362c | 2331 | printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
f3b197ac | 2332 | i, |
f82a9352 SH |
2333 | le32_to_cpu(np->tx_ring.orig[i].buf), |
2334 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2335 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2336 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2337 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2338 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2339 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2340 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
ee73362c MS |
2341 | } else { |
2342 | printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", | |
f3b197ac | 2343 | i, |
f82a9352 SH |
2344 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
2345 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2346 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2347 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2348 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2349 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2350 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2351 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2352 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2353 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2354 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2355 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
ee73362c | 2356 | } |
c2dba06d MS |
2357 | } |
2358 | } | |
2359 | ||
1da177e4 LT |
2360 | spin_lock_irq(&np->lock); |
2361 | ||
2362 | /* 1) stop tx engine */ | |
2363 | nv_stop_tx(dev); | |
2364 | ||
2365 | /* 2) check that the packets were not sent already: */ | |
36b30ea9 | 2366 | if (!nv_optimized(np)) |
86b22b0d AA |
2367 | nv_tx_done(dev); |
2368 | else | |
4e16ed1b | 2369 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 LT |
2370 | |
2371 | /* 3) if there are dead entries: clear everything */ | |
761fcd9e | 2372 | if (np->get_tx_ctx != np->put_tx_ctx) { |
1da177e4 LT |
2373 | printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
2374 | nv_drain_tx(dev); | |
761fcd9e | 2375 | nv_init_tx(dev); |
0832b25a | 2376 | setup_hw_rings(dev, NV_SETUP_TX_RING); |
1da177e4 LT |
2377 | } |
2378 | ||
3ba4d093 AA |
2379 | netif_wake_queue(dev); |
2380 | ||
1da177e4 LT |
2381 | /* 4) restart tx engine */ |
2382 | nv_start_tx(dev); | |
2383 | spin_unlock_irq(&np->lock); | |
2384 | } | |
2385 | ||
22c6d143 MS |
2386 | /* |
2387 | * Called when the nic notices a mismatch between the actual data len on the | |
2388 | * wire and the len indicated in the 802 header | |
2389 | */ | |
2390 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2391 | { | |
2392 | int hdrlen; /* length of the 802 header */ | |
2393 | int protolen; /* length as stored in the proto field */ | |
2394 | ||
2395 | /* 1) calculate len according to header */ | |
f82a9352 | 2396 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
22c6d143 MS |
2397 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
2398 | hdrlen = VLAN_HLEN; | |
2399 | } else { | |
2400 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | |
2401 | hdrlen = ETH_HLEN; | |
2402 | } | |
2403 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | |
2404 | dev->name, datalen, protolen, hdrlen); | |
2405 | if (protolen > ETH_DATA_LEN) | |
2406 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2407 | ||
2408 | protolen += hdrlen; | |
2409 | /* consistency checks: */ | |
2410 | if (datalen > ETH_ZLEN) { | |
2411 | if (datalen >= protolen) { | |
2412 | /* more data on wire than in 802 header, trim of | |
2413 | * additional data. | |
2414 | */ | |
2415 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2416 | dev->name, protolen); | |
2417 | return protolen; | |
2418 | } else { | |
2419 | /* less data on wire than mentioned in header. | |
2420 | * Discard the packet. | |
2421 | */ | |
2422 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | |
2423 | dev->name); | |
2424 | return -1; | |
2425 | } | |
2426 | } else { | |
2427 | /* short packet. Accept only if 802 values are also short */ | |
2428 | if (protolen > ETH_ZLEN) { | |
2429 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | |
2430 | dev->name); | |
2431 | return -1; | |
2432 | } | |
2433 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | |
2434 | dev->name, datalen); | |
2435 | return datalen; | |
2436 | } | |
2437 | } | |
2438 | ||
e27cdba5 | 2439 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2440 | { |
ac9c1897 | 2441 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2442 | u32 flags; |
bcb5febb | 2443 | int rx_work = 0; |
b01867cb AA |
2444 | struct sk_buff *skb; |
2445 | int len; | |
1da177e4 | 2446 | |
b01867cb AA |
2447 | while((np->get_rx.orig != np->put_rx.orig) && |
2448 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && | |
bcb5febb | 2449 | (rx_work < limit)) { |
1da177e4 | 2450 | |
761fcd9e AA |
2451 | dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n", |
2452 | dev->name, flags); | |
1da177e4 | 2453 | |
1da177e4 LT |
2454 | /* |
2455 | * the packet is for us - immediately tear down the pci mapping. | |
2456 | * TODO: check if a prefetch of the first cacheline improves | |
2457 | * the performance. | |
2458 | */ | |
761fcd9e AA |
2459 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2460 | np->get_rx_ctx->dma_len, | |
1da177e4 | 2461 | PCI_DMA_FROMDEVICE); |
0d63fb32 AA |
2462 | skb = np->get_rx_ctx->skb; |
2463 | np->get_rx_ctx->skb = NULL; | |
1da177e4 LT |
2464 | |
2465 | { | |
2466 | int j; | |
f82a9352 | 2467 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); |
1da177e4 LT |
2468 | for (j=0; j<64; j++) { |
2469 | if ((j%16) == 0) | |
2470 | dprintk("\n%03x:", j); | |
0d63fb32 | 2471 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
1da177e4 LT |
2472 | } |
2473 | dprintk("\n"); | |
2474 | } | |
2475 | /* look at what we actually got: */ | |
2476 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2477 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2478 | len = flags & LEN_MASK_V1; | |
2479 | if (unlikely(flags & NV_RX_ERROR)) { | |
2480 | if (flags & NV_RX_ERROR4) { | |
2481 | len = nv_getlen(dev, skb->data, len); | |
2482 | if (len < 0) { | |
8148ff45 | 2483 | dev->stats.rx_errors++; |
b01867cb AA |
2484 | dev_kfree_skb(skb); |
2485 | goto next_pkt; | |
2486 | } | |
2487 | } | |
2488 | /* framing errors are soft errors */ | |
2489 | else if (flags & NV_RX_FRAMINGERR) { | |
2490 | if (flags & NV_RX_SUBSTRACT1) { | |
2491 | len--; | |
2492 | } | |
2493 | } | |
2494 | /* the rest are hard errors */ | |
2495 | else { | |
2496 | if (flags & NV_RX_MISSEDFRAME) | |
8148ff45 | 2497 | dev->stats.rx_missed_errors++; |
b01867cb | 2498 | if (flags & NV_RX_CRCERR) |
8148ff45 | 2499 | dev->stats.rx_crc_errors++; |
b01867cb | 2500 | if (flags & NV_RX_OVERFLOW) |
8148ff45 JG |
2501 | dev->stats.rx_over_errors++; |
2502 | dev->stats.rx_errors++; | |
0d63fb32 | 2503 | dev_kfree_skb(skb); |
a971c324 AA |
2504 | goto next_pkt; |
2505 | } | |
2506 | } | |
b01867cb | 2507 | } else { |
0d63fb32 | 2508 | dev_kfree_skb(skb); |
1da177e4 | 2509 | goto next_pkt; |
0d63fb32 | 2510 | } |
b01867cb AA |
2511 | } else { |
2512 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2513 | len = flags & LEN_MASK_V2; | |
2514 | if (unlikely(flags & NV_RX2_ERROR)) { | |
2515 | if (flags & NV_RX2_ERROR4) { | |
2516 | len = nv_getlen(dev, skb->data, len); | |
2517 | if (len < 0) { | |
8148ff45 | 2518 | dev->stats.rx_errors++; |
b01867cb AA |
2519 | dev_kfree_skb(skb); |
2520 | goto next_pkt; | |
2521 | } | |
2522 | } | |
2523 | /* framing errors are soft errors */ | |
2524 | else if (flags & NV_RX2_FRAMINGERR) { | |
2525 | if (flags & NV_RX2_SUBSTRACT1) { | |
2526 | len--; | |
2527 | } | |
2528 | } | |
2529 | /* the rest are hard errors */ | |
2530 | else { | |
2531 | if (flags & NV_RX2_CRCERR) | |
8148ff45 | 2532 | dev->stats.rx_crc_errors++; |
b01867cb | 2533 | if (flags & NV_RX2_OVERFLOW) |
8148ff45 JG |
2534 | dev->stats.rx_over_errors++; |
2535 | dev->stats.rx_errors++; | |
0d63fb32 | 2536 | dev_kfree_skb(skb); |
a971c324 AA |
2537 | goto next_pkt; |
2538 | } | |
2539 | } | |
bfaffe8f AA |
2540 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2541 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2542 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2543 | } else { |
2544 | dev_kfree_skb(skb); | |
2545 | goto next_pkt; | |
1da177e4 LT |
2546 | } |
2547 | } | |
2548 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2549 | skb_put(skb, len); |
2550 | skb->protocol = eth_type_trans(skb, dev); | |
761fcd9e AA |
2551 | dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n", |
2552 | dev->name, len, skb->protocol); | |
e27cdba5 | 2553 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2554 | netif_receive_skb(skb); |
e27cdba5 | 2555 | #else |
b01867cb | 2556 | netif_rx(skb); |
e27cdba5 | 2557 | #endif |
1da177e4 | 2558 | dev->last_rx = jiffies; |
8148ff45 JG |
2559 | dev->stats.rx_packets++; |
2560 | dev->stats.rx_bytes += len; | |
1da177e4 | 2561 | next_pkt: |
b01867cb | 2562 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
86b22b0d | 2563 | np->get_rx.orig = np->first_rx.orig; |
b01867cb | 2564 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
86b22b0d | 2565 | np->get_rx_ctx = np->first_rx_ctx; |
bcb5febb IM |
2566 | |
2567 | rx_work++; | |
86b22b0d AA |
2568 | } |
2569 | ||
bcb5febb | 2570 | return rx_work; |
86b22b0d AA |
2571 | } |
2572 | ||
2573 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2574 | { | |
2575 | struct fe_priv *np = netdev_priv(dev); | |
2576 | u32 flags; | |
2577 | u32 vlanflags = 0; | |
c1b7151a | 2578 | int rx_work = 0; |
b01867cb AA |
2579 | struct sk_buff *skb; |
2580 | int len; | |
86b22b0d | 2581 | |
b01867cb AA |
2582 | while((np->get_rx.ex != np->put_rx.ex) && |
2583 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && | |
c1b7151a | 2584 | (rx_work < limit)) { |
86b22b0d AA |
2585 | |
2586 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n", | |
2587 | dev->name, flags); | |
2588 | ||
86b22b0d AA |
2589 | /* |
2590 | * the packet is for us - immediately tear down the pci mapping. | |
2591 | * TODO: check if a prefetch of the first cacheline improves | |
2592 | * the performance. | |
2593 | */ | |
2594 | pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, | |
2595 | np->get_rx_ctx->dma_len, | |
2596 | PCI_DMA_FROMDEVICE); | |
2597 | skb = np->get_rx_ctx->skb; | |
2598 | np->get_rx_ctx->skb = NULL; | |
2599 | ||
2600 | { | |
2601 | int j; | |
2602 | dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); | |
2603 | for (j=0; j<64; j++) { | |
2604 | if ((j%16) == 0) | |
2605 | dprintk("\n%03x:", j); | |
2606 | dprintk(" %02x", ((unsigned char*)skb->data)[j]); | |
2607 | } | |
2608 | dprintk("\n"); | |
761fcd9e | 2609 | } |
86b22b0d | 2610 | /* look at what we actually got: */ |
b01867cb AA |
2611 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2612 | len = flags & LEN_MASK_V2; | |
2613 | if (unlikely(flags & NV_RX2_ERROR)) { | |
2614 | if (flags & NV_RX2_ERROR4) { | |
2615 | len = nv_getlen(dev, skb->data, len); | |
2616 | if (len < 0) { | |
b01867cb AA |
2617 | dev_kfree_skb(skb); |
2618 | goto next_pkt; | |
2619 | } | |
2620 | } | |
2621 | /* framing errors are soft errors */ | |
2622 | else if (flags & NV_RX2_FRAMINGERR) { | |
2623 | if (flags & NV_RX2_SUBSTRACT1) { | |
2624 | len--; | |
2625 | } | |
2626 | } | |
2627 | /* the rest are hard errors */ | |
2628 | else { | |
86b22b0d AA |
2629 | dev_kfree_skb(skb); |
2630 | goto next_pkt; | |
2631 | } | |
2632 | } | |
b01867cb | 2633 | |
bfaffe8f AA |
2634 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2635 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2636 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2637 | |
2638 | /* got a valid packet - forward it to the network core */ | |
2639 | skb_put(skb, len); | |
2640 | skb->protocol = eth_type_trans(skb, dev); | |
2641 | prefetch(skb->data); | |
2642 | ||
2643 | dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n", | |
2644 | dev->name, len, skb->protocol); | |
2645 | ||
2646 | if (likely(!np->vlangrp)) { | |
86b22b0d | 2647 | #ifdef CONFIG_FORCEDETH_NAPI |
b01867cb | 2648 | netif_receive_skb(skb); |
86b22b0d | 2649 | #else |
b01867cb | 2650 | netif_rx(skb); |
86b22b0d | 2651 | #endif |
b01867cb AA |
2652 | } else { |
2653 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); | |
2654 | if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) { | |
2655 | #ifdef CONFIG_FORCEDETH_NAPI | |
2656 | vlan_hwaccel_receive_skb(skb, np->vlangrp, | |
2657 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2658 | #else | |
2659 | vlan_hwaccel_rx(skb, np->vlangrp, | |
2660 | vlanflags & NV_RX3_VLAN_TAG_MASK); | |
2661 | #endif | |
2662 | } else { | |
2663 | #ifdef CONFIG_FORCEDETH_NAPI | |
2664 | netif_receive_skb(skb); | |
2665 | #else | |
2666 | netif_rx(skb); | |
2667 | #endif | |
2668 | } | |
2669 | } | |
2670 | ||
2671 | dev->last_rx = jiffies; | |
8148ff45 JG |
2672 | dev->stats.rx_packets++; |
2673 | dev->stats.rx_bytes += len; | |
b01867cb AA |
2674 | } else { |
2675 | dev_kfree_skb(skb); | |
2676 | } | |
86b22b0d | 2677 | next_pkt: |
b01867cb | 2678 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
86b22b0d | 2679 | np->get_rx.ex = np->first_rx.ex; |
b01867cb | 2680 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
761fcd9e | 2681 | np->get_rx_ctx = np->first_rx_ctx; |
c1b7151a IM |
2682 | |
2683 | rx_work++; | |
1da177e4 | 2684 | } |
e27cdba5 | 2685 | |
c1b7151a | 2686 | return rx_work; |
1da177e4 LT |
2687 | } |
2688 | ||
d81c0983 MS |
2689 | static void set_bufsize(struct net_device *dev) |
2690 | { | |
2691 | struct fe_priv *np = netdev_priv(dev); | |
2692 | ||
2693 | if (dev->mtu <= ETH_DATA_LEN) | |
2694 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
2695 | else | |
2696 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
2697 | } | |
2698 | ||
1da177e4 LT |
2699 | /* |
2700 | * nv_change_mtu: dev->change_mtu function | |
2701 | * Called with dev_base_lock held for read. | |
2702 | */ | |
2703 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
2704 | { | |
ac9c1897 | 2705 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
2706 | int old_mtu; |
2707 | ||
2708 | if (new_mtu < 64 || new_mtu > np->pkt_limit) | |
1da177e4 | 2709 | return -EINVAL; |
d81c0983 MS |
2710 | |
2711 | old_mtu = dev->mtu; | |
1da177e4 | 2712 | dev->mtu = new_mtu; |
d81c0983 MS |
2713 | |
2714 | /* return early if the buffer sizes will not change */ | |
2715 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
2716 | return 0; | |
2717 | if (old_mtu == new_mtu) | |
2718 | return 0; | |
2719 | ||
2720 | /* synchronized against open : rtnl_lock() held by caller */ | |
2721 | if (netif_running(dev)) { | |
25097d4b | 2722 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
2723 | /* |
2724 | * It seems that the nic preloads valid ring entries into an | |
2725 | * internal buffer. The procedure for flushing everything is | |
2726 | * guessed, there is probably a simpler approach. | |
2727 | * Changing the MTU is a rare event, it shouldn't matter. | |
2728 | */ | |
84b3932b | 2729 | nv_disable_irq(dev); |
932ff279 | 2730 | netif_tx_lock_bh(dev); |
d81c0983 MS |
2731 | spin_lock(&np->lock); |
2732 | /* stop engines */ | |
36b30ea9 | 2733 | nv_stop_rxtx(dev); |
d81c0983 MS |
2734 | nv_txrx_reset(dev); |
2735 | /* drain rx queue */ | |
36b30ea9 | 2736 | nv_drain_rxtx(dev); |
d81c0983 | 2737 | /* reinit driver view of the rx queue */ |
d81c0983 | 2738 | set_bufsize(dev); |
eafa59f6 | 2739 | if (nv_init_ring(dev)) { |
d81c0983 MS |
2740 | if (!np->in_shutdown) |
2741 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
2742 | } | |
2743 | /* reinit nic view of the rx queue */ | |
2744 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 2745 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 2746 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
2747 | base + NvRegRingSizes); |
2748 | pci_push(base); | |
8a4ae7f2 | 2749 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
2750 | pci_push(base); |
2751 | ||
2752 | /* restart rx engine */ | |
36b30ea9 | 2753 | nv_start_rxtx(dev); |
d81c0983 | 2754 | spin_unlock(&np->lock); |
932ff279 | 2755 | netif_tx_unlock_bh(dev); |
84b3932b | 2756 | nv_enable_irq(dev); |
d81c0983 | 2757 | } |
1da177e4 LT |
2758 | return 0; |
2759 | } | |
2760 | ||
72b31782 MS |
2761 | static void nv_copy_mac_to_hw(struct net_device *dev) |
2762 | { | |
25097d4b | 2763 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
2764 | u32 mac[2]; |
2765 | ||
2766 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
2767 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
2768 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
2769 | ||
2770 | writel(mac[0], base + NvRegMacAddrA); | |
2771 | writel(mac[1], base + NvRegMacAddrB); | |
2772 | } | |
2773 | ||
2774 | /* | |
2775 | * nv_set_mac_address: dev->set_mac_address function | |
2776 | * Called with rtnl_lock() held. | |
2777 | */ | |
2778 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
2779 | { | |
ac9c1897 | 2780 | struct fe_priv *np = netdev_priv(dev); |
72b31782 MS |
2781 | struct sockaddr *macaddr = (struct sockaddr*)addr; |
2782 | ||
f82a9352 | 2783 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
2784 | return -EADDRNOTAVAIL; |
2785 | ||
2786 | /* synchronized against open : rtnl_lock() held by caller */ | |
2787 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
2788 | ||
2789 | if (netif_running(dev)) { | |
932ff279 | 2790 | netif_tx_lock_bh(dev); |
72b31782 MS |
2791 | spin_lock_irq(&np->lock); |
2792 | ||
2793 | /* stop rx engine */ | |
2794 | nv_stop_rx(dev); | |
2795 | ||
2796 | /* set mac address */ | |
2797 | nv_copy_mac_to_hw(dev); | |
2798 | ||
2799 | /* restart rx engine */ | |
2800 | nv_start_rx(dev); | |
2801 | spin_unlock_irq(&np->lock); | |
932ff279 | 2802 | netif_tx_unlock_bh(dev); |
72b31782 MS |
2803 | } else { |
2804 | nv_copy_mac_to_hw(dev); | |
2805 | } | |
2806 | return 0; | |
2807 | } | |
2808 | ||
1da177e4 LT |
2809 | /* |
2810 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 2811 | * Called with netif_tx_lock held. |
1da177e4 LT |
2812 | */ |
2813 | static void nv_set_multicast(struct net_device *dev) | |
2814 | { | |
ac9c1897 | 2815 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
2816 | u8 __iomem *base = get_hwbase(dev); |
2817 | u32 addr[2]; | |
2818 | u32 mask[2]; | |
b6d0773f | 2819 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
2820 | |
2821 | memset(addr, 0, sizeof(addr)); | |
2822 | memset(mask, 0, sizeof(mask)); | |
2823 | ||
2824 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 2825 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 2826 | } else { |
b6d0773f | 2827 | pff |= NVREG_PFF_MYADDR; |
1da177e4 LT |
2828 | |
2829 | if (dev->flags & IFF_ALLMULTI || dev->mc_list) { | |
2830 | u32 alwaysOff[2]; | |
2831 | u32 alwaysOn[2]; | |
2832 | ||
2833 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
2834 | if (dev->flags & IFF_ALLMULTI) { | |
2835 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
2836 | } else { | |
2837 | struct dev_mc_list *walk; | |
2838 | ||
2839 | walk = dev->mc_list; | |
2840 | while (walk != NULL) { | |
2841 | u32 a, b; | |
5bb7ea26 AV |
2842 | a = le32_to_cpu(*(__le32 *) walk->dmi_addr); |
2843 | b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4])); | |
1da177e4 LT |
2844 | alwaysOn[0] &= a; |
2845 | alwaysOff[0] &= ~a; | |
2846 | alwaysOn[1] &= b; | |
2847 | alwaysOff[1] &= ~b; | |
2848 | walk = walk->next; | |
2849 | } | |
2850 | } | |
2851 | addr[0] = alwaysOn[0]; | |
2852 | addr[1] = alwaysOn[1]; | |
2853 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
2854 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
2855 | } else { |
2856 | mask[0] = NVREG_MCASTMASKA_NONE; | |
2857 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
2858 | } |
2859 | } | |
2860 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
2861 | pff |= NVREG_PFF_ALWAYS; | |
2862 | spin_lock_irq(&np->lock); | |
2863 | nv_stop_rx(dev); | |
2864 | writel(addr[0], base + NvRegMulticastAddrA); | |
2865 | writel(addr[1], base + NvRegMulticastAddrB); | |
2866 | writel(mask[0], base + NvRegMulticastMaskA); | |
2867 | writel(mask[1], base + NvRegMulticastMaskB); | |
2868 | writel(pff, base + NvRegPacketFilterFlags); | |
2869 | dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", | |
2870 | dev->name); | |
2871 | nv_start_rx(dev); | |
2872 | spin_unlock_irq(&np->lock); | |
2873 | } | |
2874 | ||
c7985051 | 2875 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
2876 | { |
2877 | struct fe_priv *np = netdev_priv(dev); | |
2878 | u8 __iomem *base = get_hwbase(dev); | |
2879 | ||
2880 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
2881 | ||
2882 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
2883 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
2884 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
2885 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
2886 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
2887 | } else { | |
2888 | writel(pff, base + NvRegPacketFilterFlags); | |
2889 | } | |
2890 | } | |
2891 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
2892 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
2893 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
2894 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
2895 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
2896 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
2897 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) | |
2898 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; | |
2899 | writel(pause_enable, base + NvRegTxPauseFrame); | |
b6d0773f AA |
2900 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
2901 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
2902 | } else { | |
2903 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
2904 | writel(regmisc, base + NvRegMisc1); | |
2905 | } | |
2906 | } | |
2907 | } | |
2908 | ||
4ea7f299 AA |
2909 | /** |
2910 | * nv_update_linkspeed: Setup the MAC according to the link partner | |
2911 | * @dev: Network device to be configured | |
2912 | * | |
2913 | * The function queries the PHY and checks if there is a link partner. | |
2914 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
2915 | * set to 10 MBit HD. | |
2916 | * | |
2917 | * The function returns 0 if there is no link partner and 1 if there is | |
2918 | * a good link partner. | |
2919 | */ | |
1da177e4 LT |
2920 | static int nv_update_linkspeed(struct net_device *dev) |
2921 | { | |
ac9c1897 | 2922 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2923 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
2924 | int adv = 0; |
2925 | int lpa = 0; | |
2926 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
2927 | int newls = np->linkspeed; |
2928 | int newdup = np->duplex; | |
2929 | int mii_status; | |
2930 | int retval = 0; | |
9744e218 | 2931 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 2932 | u32 txrxFlags = 0; |
fd9b558c | 2933 | u32 phy_exp; |
1da177e4 LT |
2934 | |
2935 | /* BMSR_LSTATUS is latched, read it twice: | |
2936 | * we want the current value. | |
2937 | */ | |
2938 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
2939 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
2940 | ||
2941 | if (!(mii_status & BMSR_LSTATUS)) { | |
2942 | dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", | |
2943 | dev->name); | |
2944 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2945 | newdup = 0; | |
2946 | retval = 0; | |
2947 | goto set_speed; | |
2948 | } | |
2949 | ||
2950 | if (np->autoneg == 0) { | |
2951 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", | |
2952 | dev->name, np->fixed_mode); | |
2953 | if (np->fixed_mode & LPA_100FULL) { | |
2954 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
2955 | newdup = 1; | |
2956 | } else if (np->fixed_mode & LPA_100HALF) { | |
2957 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
2958 | newdup = 0; | |
2959 | } else if (np->fixed_mode & LPA_10FULL) { | |
2960 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2961 | newdup = 1; | |
2962 | } else { | |
2963 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2964 | newdup = 0; | |
2965 | } | |
2966 | retval = 1; | |
2967 | goto set_speed; | |
2968 | } | |
2969 | /* check auto negotiation is complete */ | |
2970 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
2971 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
2972 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
2973 | newdup = 0; | |
2974 | retval = 0; | |
2975 | dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); | |
2976 | goto set_speed; | |
2977 | } | |
2978 | ||
b6d0773f AA |
2979 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
2980 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
2981 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", | |
2982 | dev->name, adv, lpa); | |
2983 | ||
1da177e4 LT |
2984 | retval = 1; |
2985 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
2986 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
2987 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
2988 | |
2989 | if ((control_1000 & ADVERTISE_1000FULL) && | |
2990 | (status_1000 & LPA_1000FULL)) { | |
2991 | dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", | |
2992 | dev->name); | |
2993 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; | |
2994 | newdup = 1; | |
2995 | goto set_speed; | |
2996 | } | |
2997 | } | |
2998 | ||
1da177e4 | 2999 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3000 | adv_lpa = lpa & adv; |
3001 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3002 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3003 | newdup = 1; | |
eb91f61b | 3004 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3005 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3006 | newdup = 0; | |
eb91f61b | 3007 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3008 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3009 | newdup = 1; | |
eb91f61b | 3010 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3011 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3012 | newdup = 0; | |
3013 | } else { | |
eb91f61b | 3014 | dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); |
1da177e4 LT |
3015 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3016 | newdup = 0; | |
3017 | } | |
3018 | ||
3019 | set_speed: | |
3020 | if (np->duplex == newdup && np->linkspeed == newls) | |
3021 | return retval; | |
3022 | ||
3023 | dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", | |
3024 | dev->name, np->linkspeed, np->duplex, newls, newdup); | |
3025 | ||
3026 | np->duplex = newdup; | |
3027 | np->linkspeed = newls; | |
3028 | ||
b2976d23 AA |
3029 | /* The transmitter and receiver must be restarted for safe update */ |
3030 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3031 | txrxFlags |= NV_RESTART_TX; | |
3032 | nv_stop_tx(dev); | |
3033 | } | |
3034 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3035 | txrxFlags |= NV_RESTART_RX; | |
3036 | nv_stop_rx(dev); | |
3037 | } | |
3038 | ||
1da177e4 | 3039 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3040 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3041 | phyreg &= ~(0x3FF00); |
a433686c AA |
3042 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3043 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3044 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3045 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3046 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3047 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3048 | } |
3049 | ||
3050 | phyreg = readl(base + NvRegPhyInterface); | |
3051 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3052 | if (np->duplex == 0) | |
3053 | phyreg |= PHY_HALF; | |
3054 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3055 | phyreg |= PHY_100; | |
3056 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3057 | phyreg |= PHY_1000; | |
3058 | writel(phyreg, base + NvRegPhyInterface); | |
3059 | ||
fd9b558c | 3060 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3061 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3062 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3063 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3064 | } else { |
3065 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3066 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3067 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3068 | else | |
3069 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3070 | } else { | |
3071 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3072 | } | |
3073 | } | |
9744e218 | 3074 | } else { |
fd9b558c AA |
3075 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3076 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3077 | else | |
3078 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3079 | } |
3080 | writel(txreg, base + NvRegTxDeferral); | |
3081 | ||
95d161cb AA |
3082 | if (np->desc_ver == DESC_VER_1) { |
3083 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3084 | } else { | |
3085 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3086 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3087 | else | |
3088 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3089 | } | |
3090 | writel(txreg, base + NvRegTxWatermark); | |
3091 | ||
1da177e4 LT |
3092 | writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
3093 | base + NvRegMisc1); | |
3094 | pci_push(base); | |
3095 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3096 | pci_push(base); | |
3097 | ||
b6d0773f AA |
3098 | pause_flags = 0; |
3099 | /* setup pause frame */ | |
eb91f61b | 3100 | if (np->duplex != 0) { |
b6d0773f AA |
3101 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
3102 | adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); | |
3103 | lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); | |
3104 | ||
3105 | switch (adv_pause) { | |
f82a9352 | 3106 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3107 | if (lpa_pause & LPA_PAUSE_CAP) { |
3108 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3109 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3110 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3111 | } | |
3112 | break; | |
f82a9352 | 3113 | case ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
3114 | if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) |
3115 | { | |
3116 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3117 | } | |
3118 | break; | |
f82a9352 | 3119 | case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: |
b6d0773f AA |
3120 | if (lpa_pause & LPA_PAUSE_CAP) |
3121 | { | |
3122 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3123 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3124 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3125 | } | |
3126 | if (lpa_pause == LPA_PAUSE_ASYM) | |
3127 | { | |
3128 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3129 | } | |
3130 | break; | |
f3b197ac | 3131 | } |
eb91f61b | 3132 | } else { |
b6d0773f | 3133 | pause_flags = np->pause_flags; |
eb91f61b AA |
3134 | } |
3135 | } | |
b6d0773f | 3136 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3137 | |
b2976d23 AA |
3138 | if (txrxFlags & NV_RESTART_TX) |
3139 | nv_start_tx(dev); | |
3140 | if (txrxFlags & NV_RESTART_RX) | |
3141 | nv_start_rx(dev); | |
3142 | ||
1da177e4 LT |
3143 | return retval; |
3144 | } | |
3145 | ||
3146 | static void nv_linkchange(struct net_device *dev) | |
3147 | { | |
3148 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3149 | if (!netif_carrier_ok(dev)) { |
1da177e4 LT |
3150 | netif_carrier_on(dev); |
3151 | printk(KERN_INFO "%s: link up.\n", dev->name); | |
4ea7f299 | 3152 | nv_start_rx(dev); |
1da177e4 | 3153 | } |
1da177e4 LT |
3154 | } else { |
3155 | if (netif_carrier_ok(dev)) { | |
3156 | netif_carrier_off(dev); | |
3157 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
3158 | nv_stop_rx(dev); | |
3159 | } | |
3160 | } | |
3161 | } | |
3162 | ||
3163 | static void nv_link_irq(struct net_device *dev) | |
3164 | { | |
3165 | u8 __iomem *base = get_hwbase(dev); | |
3166 | u32 miistat; | |
3167 | ||
3168 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3169 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3170 | dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
3171 | ||
3172 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3173 | nv_linkchange(dev); | |
3174 | dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); | |
3175 | } | |
3176 | ||
7d12e780 | 3177 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3178 | { |
3179 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3180 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3181 | u8 __iomem *base = get_hwbase(dev); |
3182 | u32 events; | |
3183 | int i; | |
3184 | ||
3185 | dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); | |
3186 | ||
3187 | for (i=0; ; i++) { | |
d33a73c8 AA |
3188 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3189 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3190 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3191 | } else { | |
3192 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3193 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
3194 | } | |
1da177e4 LT |
3195 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3196 | if (!(events & np->irqmask)) | |
3197 | break; | |
3198 | ||
a971c324 AA |
3199 | spin_lock(&np->lock); |
3200 | nv_tx_done(dev); | |
3201 | spin_unlock(&np->lock); | |
f3b197ac | 3202 | |
f0734ab6 AA |
3203 | #ifdef CONFIG_FORCEDETH_NAPI |
3204 | if (events & NVREG_IRQ_RX_ALL) { | |
bea3348e | 3205 | netif_rx_schedule(dev, &np->napi); |
f0734ab6 AA |
3206 | |
3207 | /* Disable furthur receive irq's */ | |
3208 | spin_lock(&np->lock); | |
3209 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | |
3210 | ||
3211 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3212 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3213 | else | |
3214 | writel(np->irqmask, base + NvRegIrqMask); | |
3215 | spin_unlock(&np->lock); | |
3216 | } | |
3217 | #else | |
bea3348e | 3218 | if (nv_rx_process(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3219 | if (unlikely(nv_alloc_rx(dev))) { |
3220 | spin_lock(&np->lock); | |
3221 | if (!np->in_shutdown) | |
3222 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3223 | spin_unlock(&np->lock); | |
3224 | } | |
3225 | } | |
3226 | #endif | |
3227 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
1da177e4 LT |
3228 | spin_lock(&np->lock); |
3229 | nv_link_irq(dev); | |
3230 | spin_unlock(&np->lock); | |
3231 | } | |
f0734ab6 | 3232 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
1da177e4 LT |
3233 | spin_lock(&np->lock); |
3234 | nv_linkchange(dev); | |
3235 | spin_unlock(&np->lock); | |
3236 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3237 | } | |
f0734ab6 | 3238 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
1da177e4 LT |
3239 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3240 | dev->name, events); | |
3241 | } | |
f0734ab6 | 3242 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
1da177e4 LT |
3243 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
3244 | dev->name, events); | |
3245 | } | |
c5cf9101 AA |
3246 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { |
3247 | spin_lock(&np->lock); | |
3248 | /* disable interrupts on the nic */ | |
3249 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3250 | writel(0, base + NvRegIrqMask); | |
3251 | else | |
3252 | writel(np->irqmask, base + NvRegIrqMask); | |
3253 | pci_push(base); | |
3254 | ||
3255 | if (!np->in_shutdown) { | |
3256 | np->nic_poll_irq = np->irqmask; | |
3257 | np->recover_error = 1; | |
3258 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3259 | } | |
3260 | spin_unlock(&np->lock); | |
3261 | break; | |
3262 | } | |
f0734ab6 | 3263 | if (unlikely(i > max_interrupt_work)) { |
1da177e4 LT |
3264 | spin_lock(&np->lock); |
3265 | /* disable interrupts on the nic */ | |
d33a73c8 AA |
3266 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
3267 | writel(0, base + NvRegIrqMask); | |
3268 | else | |
3269 | writel(np->irqmask, base + NvRegIrqMask); | |
1da177e4 LT |
3270 | pci_push(base); |
3271 | ||
d33a73c8 AA |
3272 | if (!np->in_shutdown) { |
3273 | np->nic_poll_irq = np->irqmask; | |
1da177e4 | 3274 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
d33a73c8 | 3275 | } |
1da177e4 | 3276 | spin_unlock(&np->lock); |
1a2b7330 | 3277 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
1da177e4 LT |
3278 | break; |
3279 | } | |
3280 | ||
3281 | } | |
3282 | dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); | |
3283 | ||
3284 | return IRQ_RETVAL(i); | |
3285 | } | |
3286 | ||
f0734ab6 AA |
3287 | /** |
3288 | * All _optimized functions are used to help increase performance | |
3289 | * (reduce CPU and increase throughput). They use descripter version 3, | |
3290 | * compiler directives, and reduce memory accesses. | |
3291 | */ | |
86b22b0d AA |
3292 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3293 | { | |
3294 | struct net_device *dev = (struct net_device *) data; | |
3295 | struct fe_priv *np = netdev_priv(dev); | |
3296 | u8 __iomem *base = get_hwbase(dev); | |
3297 | u32 events; | |
3298 | int i; | |
3299 | ||
3300 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name); | |
3301 | ||
3302 | for (i=0; ; i++) { | |
3303 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3304 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3305 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
3306 | } else { | |
3307 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3308 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
3309 | } | |
86b22b0d AA |
3310 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3311 | if (!(events & np->irqmask)) | |
3312 | break; | |
3313 | ||
3314 | spin_lock(&np->lock); | |
4e16ed1b | 3315 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
86b22b0d AA |
3316 | spin_unlock(&np->lock); |
3317 | ||
f0734ab6 AA |
3318 | #ifdef CONFIG_FORCEDETH_NAPI |
3319 | if (events & NVREG_IRQ_RX_ALL) { | |
bea3348e | 3320 | netif_rx_schedule(dev, &np->napi); |
f0734ab6 AA |
3321 | |
3322 | /* Disable furthur receive irq's */ | |
3323 | spin_lock(&np->lock); | |
3324 | np->irqmask &= ~NVREG_IRQ_RX_ALL; | |
3325 | ||
3326 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3327 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3328 | else | |
3329 | writel(np->irqmask, base + NvRegIrqMask); | |
3330 | spin_unlock(&np->lock); | |
3331 | } | |
3332 | #else | |
bea3348e | 3333 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3334 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3335 | spin_lock(&np->lock); | |
3336 | if (!np->in_shutdown) | |
3337 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3338 | spin_unlock(&np->lock); | |
3339 | } | |
3340 | } | |
3341 | #endif | |
3342 | if (unlikely(events & NVREG_IRQ_LINK)) { | |
86b22b0d AA |
3343 | spin_lock(&np->lock); |
3344 | nv_link_irq(dev); | |
3345 | spin_unlock(&np->lock); | |
3346 | } | |
f0734ab6 | 3347 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
86b22b0d AA |
3348 | spin_lock(&np->lock); |
3349 | nv_linkchange(dev); | |
3350 | spin_unlock(&np->lock); | |
3351 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3352 | } | |
f0734ab6 | 3353 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
86b22b0d AA |
3354 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3355 | dev->name, events); | |
3356 | } | |
f0734ab6 | 3357 | if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { |
86b22b0d AA |
3358 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
3359 | dev->name, events); | |
3360 | } | |
3361 | if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { | |
3362 | spin_lock(&np->lock); | |
3363 | /* disable interrupts on the nic */ | |
3364 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3365 | writel(0, base + NvRegIrqMask); | |
3366 | else | |
3367 | writel(np->irqmask, base + NvRegIrqMask); | |
3368 | pci_push(base); | |
3369 | ||
3370 | if (!np->in_shutdown) { | |
3371 | np->nic_poll_irq = np->irqmask; | |
3372 | np->recover_error = 1; | |
3373 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3374 | } | |
3375 | spin_unlock(&np->lock); | |
3376 | break; | |
3377 | } | |
3378 | ||
f0734ab6 | 3379 | if (unlikely(i > max_interrupt_work)) { |
86b22b0d AA |
3380 | spin_lock(&np->lock); |
3381 | /* disable interrupts on the nic */ | |
3382 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
3383 | writel(0, base + NvRegIrqMask); | |
3384 | else | |
3385 | writel(np->irqmask, base + NvRegIrqMask); | |
3386 | pci_push(base); | |
3387 | ||
3388 | if (!np->in_shutdown) { | |
3389 | np->nic_poll_irq = np->irqmask; | |
3390 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3391 | } | |
86b22b0d | 3392 | spin_unlock(&np->lock); |
1a2b7330 | 3393 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
86b22b0d AA |
3394 | break; |
3395 | } | |
3396 | ||
3397 | } | |
3398 | dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name); | |
3399 | ||
3400 | return IRQ_RETVAL(i); | |
3401 | } | |
3402 | ||
7d12e780 | 3403 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3404 | { |
3405 | struct net_device *dev = (struct net_device *) data; | |
3406 | struct fe_priv *np = netdev_priv(dev); | |
3407 | u8 __iomem *base = get_hwbase(dev); | |
3408 | u32 events; | |
3409 | int i; | |
0a07bc64 | 3410 | unsigned long flags; |
d33a73c8 AA |
3411 | |
3412 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); | |
3413 | ||
3414 | for (i=0; ; i++) { | |
3415 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; | |
3416 | writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3417 | dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
3418 | if (!(events & np->irqmask)) | |
3419 | break; | |
3420 | ||
0a07bc64 | 3421 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3422 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3423 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3424 | |
f0734ab6 | 3425 | if (unlikely(events & (NVREG_IRQ_TX_ERR))) { |
d33a73c8 AA |
3426 | dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3427 | dev->name, events); | |
3428 | } | |
f0734ab6 | 3429 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3430 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3431 | /* disable interrupts on the nic */ |
3432 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3433 | pci_push(base); | |
3434 | ||
3435 | if (!np->in_shutdown) { | |
3436 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3437 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3438 | } | |
0a07bc64 | 3439 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3440 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
d33a73c8 AA |
3441 | break; |
3442 | } | |
3443 | ||
3444 | } | |
3445 | dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); | |
3446 | ||
3447 | return IRQ_RETVAL(i); | |
3448 | } | |
3449 | ||
e27cdba5 | 3450 | #ifdef CONFIG_FORCEDETH_NAPI |
bea3348e | 3451 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3452 | { |
bea3348e SH |
3453 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3454 | struct net_device *dev = np->dev; | |
e27cdba5 | 3455 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3456 | unsigned long flags; |
bea3348e | 3457 | int pkts, retcode; |
e27cdba5 | 3458 | |
36b30ea9 | 3459 | if (!nv_optimized(np)) { |
bea3348e | 3460 | pkts = nv_rx_process(dev, budget); |
e0379a14 AA |
3461 | retcode = nv_alloc_rx(dev); |
3462 | } else { | |
bea3348e | 3463 | pkts = nv_rx_process_optimized(dev, budget); |
e0379a14 AA |
3464 | retcode = nv_alloc_rx_optimized(dev); |
3465 | } | |
e27cdba5 | 3466 | |
e0379a14 | 3467 | if (retcode) { |
d15e9c4d | 3468 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3469 | if (!np->in_shutdown) |
3470 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3471 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3472 | } |
3473 | ||
bea3348e | 3474 | if (pkts < budget) { |
e27cdba5 | 3475 | /* re-enable receive interrupts */ |
d15e9c4d FR |
3476 | spin_lock_irqsave(&np->lock, flags); |
3477 | ||
bea3348e SH |
3478 | __netif_rx_complete(dev, napi); |
3479 | ||
e27cdba5 SH |
3480 | np->irqmask |= NVREG_IRQ_RX_ALL; |
3481 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
3482 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3483 | else | |
3484 | writel(np->irqmask, base + NvRegIrqMask); | |
d15e9c4d FR |
3485 | |
3486 | spin_unlock_irqrestore(&np->lock, flags); | |
e27cdba5 | 3487 | } |
bea3348e | 3488 | return pkts; |
e27cdba5 SH |
3489 | } |
3490 | #endif | |
3491 | ||
3492 | #ifdef CONFIG_FORCEDETH_NAPI | |
7d12e780 | 3493 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
e27cdba5 SH |
3494 | { |
3495 | struct net_device *dev = (struct net_device *) data; | |
bea3348e | 3496 | struct fe_priv *np = netdev_priv(dev); |
e27cdba5 SH |
3497 | u8 __iomem *base = get_hwbase(dev); |
3498 | u32 events; | |
3499 | ||
3500 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
3501 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
3502 | ||
3503 | if (events) { | |
bea3348e | 3504 | netif_rx_schedule(dev, &np->napi); |
e27cdba5 SH |
3505 | /* disable receive interrupts on the nic */ |
3506 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3507 | pci_push(base); | |
3508 | } | |
3509 | return IRQ_HANDLED; | |
3510 | } | |
3511 | #else | |
7d12e780 | 3512 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3513 | { |
3514 | struct net_device *dev = (struct net_device *) data; | |
3515 | struct fe_priv *np = netdev_priv(dev); | |
3516 | u8 __iomem *base = get_hwbase(dev); | |
3517 | u32 events; | |
3518 | int i; | |
0a07bc64 | 3519 | unsigned long flags; |
d33a73c8 AA |
3520 | |
3521 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); | |
3522 | ||
3523 | for (i=0; ; i++) { | |
3524 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; | |
3525 | writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3526 | dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
3527 | if (!(events & np->irqmask)) | |
3528 | break; | |
f3b197ac | 3529 | |
bea3348e | 3530 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3531 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3532 | spin_lock_irqsave(&np->lock, flags); | |
3533 | if (!np->in_shutdown) | |
3534 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3535 | spin_unlock_irqrestore(&np->lock, flags); | |
3536 | } | |
d33a73c8 | 3537 | } |
f3b197ac | 3538 | |
f0734ab6 | 3539 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3540 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3541 | /* disable interrupts on the nic */ |
3542 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3543 | pci_push(base); | |
3544 | ||
3545 | if (!np->in_shutdown) { | |
3546 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3547 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3548 | } | |
0a07bc64 | 3549 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3550 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
d33a73c8 AA |
3551 | break; |
3552 | } | |
d33a73c8 AA |
3553 | } |
3554 | dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); | |
3555 | ||
3556 | return IRQ_RETVAL(i); | |
3557 | } | |
e27cdba5 | 3558 | #endif |
d33a73c8 | 3559 | |
7d12e780 | 3560 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3561 | { |
3562 | struct net_device *dev = (struct net_device *) data; | |
3563 | struct fe_priv *np = netdev_priv(dev); | |
3564 | u8 __iomem *base = get_hwbase(dev); | |
3565 | u32 events; | |
3566 | int i; | |
0a07bc64 | 3567 | unsigned long flags; |
d33a73c8 AA |
3568 | |
3569 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); | |
3570 | ||
3571 | for (i=0; ; i++) { | |
3572 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; | |
3573 | writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); | |
d33a73c8 AA |
3574 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3575 | if (!(events & np->irqmask)) | |
3576 | break; | |
f3b197ac | 3577 | |
4e16ed1b AA |
3578 | /* check tx in case we reached max loop limit in tx isr */ |
3579 | spin_lock_irqsave(&np->lock, flags); | |
3580 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3581 | spin_unlock_irqrestore(&np->lock, flags); | |
3582 | ||
d33a73c8 | 3583 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3584 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3585 | nv_link_irq(dev); |
0a07bc64 | 3586 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3587 | } |
3588 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3589 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3590 | nv_linkchange(dev); |
0a07bc64 | 3591 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3592 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3593 | } | |
c5cf9101 AA |
3594 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
3595 | spin_lock_irq(&np->lock); | |
3596 | /* disable interrupts on the nic */ | |
3597 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3598 | pci_push(base); | |
3599 | ||
3600 | if (!np->in_shutdown) { | |
3601 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3602 | np->recover_error = 1; | |
3603 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3604 | } | |
3605 | spin_unlock_irq(&np->lock); | |
3606 | break; | |
3607 | } | |
d33a73c8 AA |
3608 | if (events & (NVREG_IRQ_UNKNOWN)) { |
3609 | printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", | |
3610 | dev->name, events); | |
3611 | } | |
f0734ab6 | 3612 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3613 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3614 | /* disable interrupts on the nic */ |
3615 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3616 | pci_push(base); | |
3617 | ||
3618 | if (!np->in_shutdown) { | |
3619 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3620 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3621 | } | |
0a07bc64 | 3622 | spin_unlock_irqrestore(&np->lock, flags); |
1a2b7330 | 3623 | printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
d33a73c8 AA |
3624 | break; |
3625 | } | |
3626 | ||
3627 | } | |
3628 | dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); | |
3629 | ||
3630 | return IRQ_RETVAL(i); | |
3631 | } | |
3632 | ||
7d12e780 | 3633 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3634 | { |
3635 | struct net_device *dev = (struct net_device *) data; | |
3636 | struct fe_priv *np = netdev_priv(dev); | |
3637 | u8 __iomem *base = get_hwbase(dev); | |
3638 | u32 events; | |
3639 | ||
3640 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); | |
3641 | ||
3642 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
3643 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
3644 | writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); | |
3645 | } else { | |
3646 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
3647 | writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); | |
3648 | } | |
3649 | pci_push(base); | |
3650 | dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); | |
3651 | if (!(events & NVREG_IRQ_TIMER)) | |
3652 | return IRQ_RETVAL(0); | |
3653 | ||
3654 | spin_lock(&np->lock); | |
3655 | np->intr_test = 1; | |
3656 | spin_unlock(&np->lock); | |
3657 | ||
3658 | dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); | |
3659 | ||
3660 | return IRQ_RETVAL(1); | |
3661 | } | |
3662 | ||
7a1854b7 AA |
3663 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3664 | { | |
3665 | u8 __iomem *base = get_hwbase(dev); | |
3666 | int i; | |
3667 | u32 msixmap = 0; | |
3668 | ||
3669 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3670 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3671 | * the remaining 8 interrupts. | |
3672 | */ | |
3673 | for (i = 0; i < 8; i++) { | |
3674 | if ((irqmask >> i) & 0x1) { | |
3675 | msixmap |= vector << (i << 2); | |
3676 | } | |
3677 | } | |
3678 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3679 | ||
3680 | msixmap = 0; | |
3681 | for (i = 0; i < 8; i++) { | |
3682 | if ((irqmask >> (i + 8)) & 0x1) { | |
3683 | msixmap |= vector << (i << 2); | |
3684 | } | |
3685 | } | |
3686 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3687 | } | |
3688 | ||
9589c77a | 3689 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3690 | { |
3691 | struct fe_priv *np = get_nvpriv(dev); | |
3692 | u8 __iomem *base = get_hwbase(dev); | |
3693 | int ret = 1; | |
3694 | int i; | |
86b22b0d AA |
3695 | irqreturn_t (*handler)(int foo, void *data); |
3696 | ||
3697 | if (intr_test) { | |
3698 | handler = nv_nic_irq_test; | |
3699 | } else { | |
36b30ea9 | 3700 | if (nv_optimized(np)) |
86b22b0d AA |
3701 | handler = nv_nic_irq_optimized; |
3702 | else | |
3703 | handler = nv_nic_irq; | |
3704 | } | |
7a1854b7 AA |
3705 | |
3706 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
3707 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
3708 | np->msi_x_entry[i].entry = i; | |
3709 | } | |
3710 | if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { | |
3711 | np->msi_flags |= NV_MSI_X_ENABLED; | |
9589c77a | 3712 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3713 | /* Request irq for rx handling */ |
1fb9df5d | 3714 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3715 | printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3716 | pci_disable_msix(np->pci_dev); | |
3717 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3718 | goto out_err; | |
3719 | } | |
3720 | /* Request irq for tx handling */ | |
1fb9df5d | 3721 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3722 | printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3723 | pci_disable_msix(np->pci_dev); | |
3724 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3725 | goto out_free_rx; | |
3726 | } | |
3727 | /* Request irq for link and timer handling */ | |
1fb9df5d | 3728 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3729 | printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3730 | pci_disable_msix(np->pci_dev); | |
3731 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3732 | goto out_free_tx; | |
3733 | } | |
3734 | /* map interrupts to their respective vector */ | |
3735 | writel(0, base + NvRegMSIXMap0); | |
3736 | writel(0, base + NvRegMSIXMap1); | |
3737 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
3738 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
3739 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
3740 | } else { | |
3741 | /* Request irq for all interrupts */ | |
86b22b0d | 3742 | if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3743 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3744 | pci_disable_msix(np->pci_dev); | |
3745 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3746 | goto out_err; | |
3747 | } | |
3748 | ||
3749 | /* map interrupts to vector 0 */ | |
3750 | writel(0, base + NvRegMSIXMap0); | |
3751 | writel(0, base + NvRegMSIXMap1); | |
3752 | } | |
3753 | } | |
3754 | } | |
3755 | if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { | |
3756 | if ((ret = pci_enable_msi(np->pci_dev)) == 0) { | |
3757 | np->msi_flags |= NV_MSI_ENABLED; | |
a7475906 | 3758 | dev->irq = np->pci_dev->irq; |
86b22b0d | 3759 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { |
7a1854b7 AA |
3760 | printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3761 | pci_disable_msi(np->pci_dev); | |
3762 | np->msi_flags &= ~NV_MSI_ENABLED; | |
a7475906 | 3763 | dev->irq = np->pci_dev->irq; |
7a1854b7 AA |
3764 | goto out_err; |
3765 | } | |
3766 | ||
3767 | /* map interrupts to vector 0 */ | |
3768 | writel(0, base + NvRegMSIMap0); | |
3769 | writel(0, base + NvRegMSIMap1); | |
3770 | /* enable msi vector 0 */ | |
3771 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3772 | } | |
3773 | } | |
3774 | if (ret != 0) { | |
86b22b0d | 3775 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
7a1854b7 | 3776 | goto out_err; |
9589c77a | 3777 | |
7a1854b7 AA |
3778 | } |
3779 | ||
3780 | return 0; | |
3781 | out_free_tx: | |
3782 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
3783 | out_free_rx: | |
3784 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
3785 | out_err: | |
3786 | return 1; | |
3787 | } | |
3788 | ||
3789 | static void nv_free_irq(struct net_device *dev) | |
3790 | { | |
3791 | struct fe_priv *np = get_nvpriv(dev); | |
3792 | int i; | |
3793 | ||
3794 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
3795 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { | |
3796 | free_irq(np->msi_x_entry[i].vector, dev); | |
3797 | } | |
3798 | pci_disable_msix(np->pci_dev); | |
3799 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3800 | } else { | |
3801 | free_irq(np->pci_dev->irq, dev); | |
3802 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3803 | pci_disable_msi(np->pci_dev); | |
3804 | np->msi_flags &= ~NV_MSI_ENABLED; | |
3805 | } | |
3806 | } | |
3807 | } | |
3808 | ||
1da177e4 LT |
3809 | static void nv_do_nic_poll(unsigned long data) |
3810 | { | |
3811 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3812 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3813 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 3814 | u32 mask = 0; |
1da177e4 | 3815 | |
1da177e4 | 3816 | /* |
d33a73c8 | 3817 | * First disable irq(s) and then |
1da177e4 LT |
3818 | * reenable interrupts on the nic, we have to do this before calling |
3819 | * nv_nic_irq because that may decide to do otherwise | |
3820 | */ | |
d33a73c8 | 3821 | |
84b3932b AA |
3822 | if (!using_multi_irqs(dev)) { |
3823 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
8688cfce | 3824 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3825 | else |
a7475906 | 3826 | disable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3827 | mask = np->irqmask; |
3828 | } else { | |
3829 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
8688cfce | 3830 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3831 | mask |= NVREG_IRQ_RX_ALL; |
3832 | } | |
3833 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
8688cfce | 3834 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3835 | mask |= NVREG_IRQ_TX_ALL; |
3836 | } | |
3837 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
8688cfce | 3838 | disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3839 | mask |= NVREG_IRQ_OTHER; |
3840 | } | |
3841 | } | |
3842 | np->nic_poll_irq = 0; | |
3843 | ||
a7475906 MS |
3844 | /* disable_irq() contains synchronize_irq, thus no irq handler can run now */ |
3845 | ||
c5cf9101 AA |
3846 | if (np->recover_error) { |
3847 | np->recover_error = 0; | |
3848 | printk(KERN_INFO "forcedeth: MAC in recoverable error state\n"); | |
3849 | if (netif_running(dev)) { | |
3850 | netif_tx_lock_bh(dev); | |
3851 | spin_lock(&np->lock); | |
3852 | /* stop engines */ | |
36b30ea9 | 3853 | nv_stop_rxtx(dev); |
c5cf9101 AA |
3854 | nv_txrx_reset(dev); |
3855 | /* drain rx queue */ | |
36b30ea9 | 3856 | nv_drain_rxtx(dev); |
c5cf9101 AA |
3857 | /* reinit driver view of the rx queue */ |
3858 | set_bufsize(dev); | |
3859 | if (nv_init_ring(dev)) { | |
3860 | if (!np->in_shutdown) | |
3861 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3862 | } | |
3863 | /* reinit nic view of the rx queue */ | |
3864 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
3865 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
3866 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
3867 | base + NvRegRingSizes); | |
3868 | pci_push(base); | |
3869 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
3870 | pci_push(base); | |
3871 | ||
3872 | /* restart rx engine */ | |
36b30ea9 | 3873 | nv_start_rxtx(dev); |
c5cf9101 AA |
3874 | spin_unlock(&np->lock); |
3875 | netif_tx_unlock_bh(dev); | |
3876 | } | |
3877 | } | |
3878 | ||
f3b197ac | 3879 | |
d33a73c8 | 3880 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 3881 | pci_push(base); |
d33a73c8 | 3882 | |
84b3932b | 3883 | if (!using_multi_irqs(dev)) { |
36b30ea9 | 3884 | if (nv_optimized(np)) |
fcc5f266 AA |
3885 | nv_nic_irq_optimized(0, dev); |
3886 | else | |
3887 | nv_nic_irq(0, dev); | |
84b3932b | 3888 | if (np->msi_flags & NV_MSI_X_ENABLED) |
8688cfce | 3889 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
84b3932b | 3890 | else |
a7475906 | 3891 | enable_irq_lockdep(np->pci_dev->irq); |
d33a73c8 AA |
3892 | } else { |
3893 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
7d12e780 | 3894 | nv_nic_irq_rx(0, dev); |
8688cfce | 3895 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
d33a73c8 AA |
3896 | } |
3897 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
7d12e780 | 3898 | nv_nic_irq_tx(0, dev); |
8688cfce | 3899 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
d33a73c8 AA |
3900 | } |
3901 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
7d12e780 | 3902 | nv_nic_irq_other(0, dev); |
8688cfce | 3903 | enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
d33a73c8 AA |
3904 | } |
3905 | } | |
1da177e4 LT |
3906 | } |
3907 | ||
2918c35d MS |
3908 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3909 | static void nv_poll_controller(struct net_device *dev) | |
3910 | { | |
3911 | nv_do_nic_poll((unsigned long) dev); | |
3912 | } | |
3913 | #endif | |
3914 | ||
52da3578 AA |
3915 | static void nv_do_stats_poll(unsigned long data) |
3916 | { | |
3917 | struct net_device *dev = (struct net_device *) data; | |
3918 | struct fe_priv *np = netdev_priv(dev); | |
52da3578 | 3919 | |
57fff698 | 3920 | nv_get_hw_stats(dev); |
52da3578 AA |
3921 | |
3922 | if (!np->in_shutdown) | |
bfebbb88 DD |
3923 | mod_timer(&np->stats_poll, |
3924 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
3925 | } |
3926 | ||
1da177e4 LT |
3927 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
3928 | { | |
ac9c1897 | 3929 | struct fe_priv *np = netdev_priv(dev); |
3f88ce49 | 3930 | strcpy(info->driver, DRV_NAME); |
1da177e4 LT |
3931 | strcpy(info->version, FORCEDETH_VERSION); |
3932 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
3933 | } | |
3934 | ||
3935 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3936 | { | |
ac9c1897 | 3937 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3938 | wolinfo->supported = WAKE_MAGIC; |
3939 | ||
3940 | spin_lock_irq(&np->lock); | |
3941 | if (np->wolenabled) | |
3942 | wolinfo->wolopts = WAKE_MAGIC; | |
3943 | spin_unlock_irq(&np->lock); | |
3944 | } | |
3945 | ||
3946 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
3947 | { | |
ac9c1897 | 3948 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3949 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 3950 | u32 flags = 0; |
1da177e4 | 3951 | |
1da177e4 | 3952 | if (wolinfo->wolopts == 0) { |
1da177e4 | 3953 | np->wolenabled = 0; |
c42d9df9 | 3954 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 3955 | np->wolenabled = 1; |
c42d9df9 AA |
3956 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
3957 | } | |
3958 | if (netif_running(dev)) { | |
3959 | spin_lock_irq(&np->lock); | |
3960 | writel(flags, base + NvRegWakeUpFlags); | |
3961 | spin_unlock_irq(&np->lock); | |
1da177e4 | 3962 | } |
1da177e4 LT |
3963 | return 0; |
3964 | } | |
3965 | ||
3966 | static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
3967 | { | |
3968 | struct fe_priv *np = netdev_priv(dev); | |
3969 | int adv; | |
3970 | ||
3971 | spin_lock_irq(&np->lock); | |
3972 | ecmd->port = PORT_MII; | |
3973 | if (!netif_running(dev)) { | |
3974 | /* We do not track link speed / duplex setting if the | |
3975 | * interface is disabled. Force a link check */ | |
f9430a01 AA |
3976 | if (nv_update_linkspeed(dev)) { |
3977 | if (!netif_carrier_ok(dev)) | |
3978 | netif_carrier_on(dev); | |
3979 | } else { | |
3980 | if (netif_carrier_ok(dev)) | |
3981 | netif_carrier_off(dev); | |
3982 | } | |
1da177e4 | 3983 | } |
f9430a01 AA |
3984 | |
3985 | if (netif_carrier_ok(dev)) { | |
3986 | switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { | |
1da177e4 LT |
3987 | case NVREG_LINKSPEED_10: |
3988 | ecmd->speed = SPEED_10; | |
3989 | break; | |
3990 | case NVREG_LINKSPEED_100: | |
3991 | ecmd->speed = SPEED_100; | |
3992 | break; | |
3993 | case NVREG_LINKSPEED_1000: | |
3994 | ecmd->speed = SPEED_1000; | |
3995 | break; | |
f9430a01 AA |
3996 | } |
3997 | ecmd->duplex = DUPLEX_HALF; | |
3998 | if (np->duplex) | |
3999 | ecmd->duplex = DUPLEX_FULL; | |
4000 | } else { | |
4001 | ecmd->speed = -1; | |
4002 | ecmd->duplex = -1; | |
1da177e4 | 4003 | } |
1da177e4 LT |
4004 | |
4005 | ecmd->autoneg = np->autoneg; | |
4006 | ||
4007 | ecmd->advertising = ADVERTISED_MII; | |
4008 | if (np->autoneg) { | |
4009 | ecmd->advertising |= ADVERTISED_Autoneg; | |
4010 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
f9430a01 AA |
4011 | if (adv & ADVERTISE_10HALF) |
4012 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
4013 | if (adv & ADVERTISE_10FULL) | |
4014 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
4015 | if (adv & ADVERTISE_100HALF) | |
4016 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
4017 | if (adv & ADVERTISE_100FULL) | |
4018 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
4019 | if (np->gigabit == PHY_GIGABIT) { | |
4020 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4021 | if (adv & ADVERTISE_1000FULL) | |
4022 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
4023 | } | |
1da177e4 | 4024 | } |
1da177e4 LT |
4025 | ecmd->supported = (SUPPORTED_Autoneg | |
4026 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
4027 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4028 | SUPPORTED_MII); | |
4029 | if (np->gigabit == PHY_GIGABIT) | |
4030 | ecmd->supported |= SUPPORTED_1000baseT_Full; | |
4031 | ||
4032 | ecmd->phy_address = np->phyaddr; | |
4033 | ecmd->transceiver = XCVR_EXTERNAL; | |
4034 | ||
4035 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4036 | spin_unlock_irq(&np->lock); | |
4037 | return 0; | |
4038 | } | |
4039 | ||
4040 | static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
4041 | { | |
4042 | struct fe_priv *np = netdev_priv(dev); | |
4043 | ||
4044 | if (ecmd->port != PORT_MII) | |
4045 | return -EINVAL; | |
4046 | if (ecmd->transceiver != XCVR_EXTERNAL) | |
4047 | return -EINVAL; | |
4048 | if (ecmd->phy_address != np->phyaddr) { | |
4049 | /* TODO: support switching between multiple phys. Should be | |
4050 | * trivial, but not enabled due to lack of test hardware. */ | |
4051 | return -EINVAL; | |
4052 | } | |
4053 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
4054 | u32 mask; | |
4055 | ||
4056 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4057 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4058 | if (np->gigabit == PHY_GIGABIT) | |
4059 | mask |= ADVERTISED_1000baseT_Full; | |
4060 | ||
4061 | if ((ecmd->advertising & mask) == 0) | |
4062 | return -EINVAL; | |
4063 | ||
4064 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
4065 | /* Note: autonegotiation disable, speed 1000 intentionally | |
4066 | * forbidden - noone should need that. */ | |
4067 | ||
4068 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
4069 | return -EINVAL; | |
4070 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
4071 | return -EINVAL; | |
4072 | } else { | |
4073 | return -EINVAL; | |
4074 | } | |
4075 | ||
f9430a01 AA |
4076 | netif_carrier_off(dev); |
4077 | if (netif_running(dev)) { | |
4078 | nv_disable_irq(dev); | |
58dfd9c1 | 4079 | netif_tx_lock_bh(dev); |
f9430a01 AA |
4080 | spin_lock(&np->lock); |
4081 | /* stop engines */ | |
36b30ea9 | 4082 | nv_stop_rxtx(dev); |
f9430a01 | 4083 | spin_unlock(&np->lock); |
58dfd9c1 | 4084 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4085 | } |
4086 | ||
1da177e4 LT |
4087 | if (ecmd->autoneg == AUTONEG_ENABLE) { |
4088 | int adv, bmcr; | |
4089 | ||
4090 | np->autoneg = 1; | |
4091 | ||
4092 | /* advertise only what has been requested */ | |
4093 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4094 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4095 | if (ecmd->advertising & ADVERTISED_10baseT_Half) |
4096 | adv |= ADVERTISE_10HALF; | |
4097 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
b6d0773f | 4098 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4099 | if (ecmd->advertising & ADVERTISED_100baseT_Half) |
4100 | adv |= ADVERTISE_100HALF; | |
4101 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
b6d0773f AA |
4102 | adv |= ADVERTISE_100FULL; |
4103 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4104 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4105 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4106 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4107 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4108 | ||
4109 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4110 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 LT |
4111 | adv &= ~ADVERTISE_1000FULL; |
4112 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
4113 | adv |= ADVERTISE_1000FULL; | |
eb91f61b | 4114 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4115 | } |
4116 | ||
f9430a01 AA |
4117 | if (netif_running(dev)) |
4118 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
1da177e4 | 4119 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4120 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4121 | bmcr |= BMCR_ANENABLE; | |
4122 | /* reset the phy in order for settings to stick, | |
4123 | * and cause autoneg to start */ | |
4124 | if (phy_reset(dev, bmcr)) { | |
4125 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4126 | return -EINVAL; | |
4127 | } | |
4128 | } else { | |
4129 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4130 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4131 | } | |
1da177e4 LT |
4132 | } else { |
4133 | int adv, bmcr; | |
4134 | ||
4135 | np->autoneg = 0; | |
4136 | ||
4137 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4138 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
1da177e4 LT |
4139 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
4140 | adv |= ADVERTISE_10HALF; | |
4141 | if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f | 4142 | adv |= ADVERTISE_10FULL; |
1da177e4 LT |
4143 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
4144 | adv |= ADVERTISE_100HALF; | |
4145 | if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) | |
b6d0773f AA |
4146 | adv |= ADVERTISE_100FULL; |
4147 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4148 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ | |
4149 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4150 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4151 | } | |
4152 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4153 | adv |= ADVERTISE_PAUSE_ASYM; | |
4154 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4155 | } | |
1da177e4 LT |
4156 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4157 | np->fixed_mode = adv; | |
4158 | ||
4159 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4160 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4161 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4162 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4163 | } |
4164 | ||
4165 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4166 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4167 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4168 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4169 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4170 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4171 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4172 | /* reset the phy in order for forced mode settings to stick */ |
4173 | if (phy_reset(dev, bmcr)) { | |
f9430a01 AA |
4174 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4175 | return -EINVAL; | |
4176 | } | |
edf7e5ec AA |
4177 | } else { |
4178 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4179 | if (netif_running(dev)) { | |
4180 | /* Wait a bit and then reconfigure the nic. */ | |
4181 | udelay(10); | |
4182 | nv_linkchange(dev); | |
4183 | } | |
1da177e4 LT |
4184 | } |
4185 | } | |
f9430a01 AA |
4186 | |
4187 | if (netif_running(dev)) { | |
36b30ea9 | 4188 | nv_start_rxtx(dev); |
f9430a01 AA |
4189 | nv_enable_irq(dev); |
4190 | } | |
1da177e4 LT |
4191 | |
4192 | return 0; | |
4193 | } | |
4194 | ||
dc8216c1 | 4195 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4196 | |
4197 | static int nv_get_regs_len(struct net_device *dev) | |
4198 | { | |
86a0f043 AA |
4199 | struct fe_priv *np = netdev_priv(dev); |
4200 | return np->register_size; | |
dc8216c1 MS |
4201 | } |
4202 | ||
4203 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4204 | { | |
ac9c1897 | 4205 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4206 | u8 __iomem *base = get_hwbase(dev); |
4207 | u32 *rbuf = buf; | |
4208 | int i; | |
4209 | ||
4210 | regs->version = FORCEDETH_REGS_VER; | |
4211 | spin_lock_irq(&np->lock); | |
86a0f043 | 4212 | for (i = 0;i <= np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4213 | rbuf[i] = readl(base + i*sizeof(u32)); |
4214 | spin_unlock_irq(&np->lock); | |
4215 | } | |
4216 | ||
4217 | static int nv_nway_reset(struct net_device *dev) | |
4218 | { | |
ac9c1897 | 4219 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4220 | int ret; |
4221 | ||
dc8216c1 MS |
4222 | if (np->autoneg) { |
4223 | int bmcr; | |
4224 | ||
f9430a01 AA |
4225 | netif_carrier_off(dev); |
4226 | if (netif_running(dev)) { | |
4227 | nv_disable_irq(dev); | |
58dfd9c1 | 4228 | netif_tx_lock_bh(dev); |
f9430a01 AA |
4229 | spin_lock(&np->lock); |
4230 | /* stop engines */ | |
36b30ea9 | 4231 | nv_stop_rxtx(dev); |
f9430a01 | 4232 | spin_unlock(&np->lock); |
58dfd9c1 | 4233 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4234 | printk(KERN_INFO "%s: link down.\n", dev->name); |
4235 | } | |
4236 | ||
dc8216c1 | 4237 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4238 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4239 | bmcr |= BMCR_ANENABLE; | |
4240 | /* reset the phy in order for settings to stick*/ | |
4241 | if (phy_reset(dev, bmcr)) { | |
4242 | printk(KERN_INFO "%s: phy reset failed\n", dev->name); | |
4243 | return -EINVAL; | |
4244 | } | |
4245 | } else { | |
4246 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4247 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4248 | } | |
dc8216c1 | 4249 | |
f9430a01 | 4250 | if (netif_running(dev)) { |
36b30ea9 | 4251 | nv_start_rxtx(dev); |
f9430a01 AA |
4252 | nv_enable_irq(dev); |
4253 | } | |
dc8216c1 MS |
4254 | ret = 0; |
4255 | } else { | |
4256 | ret = -EINVAL; | |
4257 | } | |
dc8216c1 MS |
4258 | |
4259 | return ret; | |
4260 | } | |
4261 | ||
0674d594 ZA |
4262 | static int nv_set_tso(struct net_device *dev, u32 value) |
4263 | { | |
4264 | struct fe_priv *np = netdev_priv(dev); | |
4265 | ||
4266 | if ((np->driver_data & DEV_HAS_CHECKSUM)) | |
4267 | return ethtool_op_set_tso(dev, value); | |
4268 | else | |
6a78814f | 4269 | return -EOPNOTSUPP; |
0674d594 | 4270 | } |
0674d594 | 4271 | |
eafa59f6 AA |
4272 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4273 | { | |
4274 | struct fe_priv *np = netdev_priv(dev); | |
4275 | ||
4276 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4277 | ring->rx_mini_max_pending = 0; | |
4278 | ring->rx_jumbo_max_pending = 0; | |
4279 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
4280 | ||
4281 | ring->rx_pending = np->rx_ring_size; | |
4282 | ring->rx_mini_pending = 0; | |
4283 | ring->rx_jumbo_pending = 0; | |
4284 | ring->tx_pending = np->tx_ring_size; | |
4285 | } | |
4286 | ||
4287 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4288 | { | |
4289 | struct fe_priv *np = netdev_priv(dev); | |
4290 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4291 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4292 | dma_addr_t ring_addr; |
4293 | ||
4294 | if (ring->rx_pending < RX_RING_MIN || | |
4295 | ring->tx_pending < TX_RING_MIN || | |
4296 | ring->rx_mini_pending != 0 || | |
4297 | ring->rx_jumbo_pending != 0 || | |
4298 | (np->desc_ver == DESC_VER_1 && | |
4299 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4300 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4301 | (np->desc_ver != DESC_VER_1 && | |
4302 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4303 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4304 | return -EINVAL; | |
4305 | } | |
4306 | ||
4307 | /* allocate new rings */ | |
36b30ea9 | 4308 | if (!nv_optimized(np)) { |
eafa59f6 AA |
4309 | rxtx_ring = pci_alloc_consistent(np->pci_dev, |
4310 | sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), | |
4311 | &ring_addr); | |
4312 | } else { | |
4313 | rxtx_ring = pci_alloc_consistent(np->pci_dev, | |
4314 | sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4315 | &ring_addr); | |
4316 | } | |
761fcd9e AA |
4317 | rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
4318 | tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); | |
4319 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { | |
eafa59f6 | 4320 | /* fall back to old rings */ |
36b30ea9 | 4321 | if (!nv_optimized(np)) { |
f82a9352 | 4322 | if (rxtx_ring) |
eafa59f6 AA |
4323 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
4324 | rxtx_ring, ring_addr); | |
4325 | } else { | |
4326 | if (rxtx_ring) | |
4327 | pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), | |
4328 | rxtx_ring, ring_addr); | |
4329 | } | |
4330 | if (rx_skbuff) | |
4331 | kfree(rx_skbuff); | |
eafa59f6 AA |
4332 | if (tx_skbuff) |
4333 | kfree(tx_skbuff); | |
eafa59f6 AA |
4334 | goto exit; |
4335 | } | |
4336 | ||
4337 | if (netif_running(dev)) { | |
4338 | nv_disable_irq(dev); | |
58dfd9c1 | 4339 | netif_tx_lock_bh(dev); |
eafa59f6 AA |
4340 | spin_lock(&np->lock); |
4341 | /* stop engines */ | |
36b30ea9 | 4342 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4343 | nv_txrx_reset(dev); |
4344 | /* drain queues */ | |
36b30ea9 | 4345 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4346 | /* delete queues */ |
4347 | free_rings(dev); | |
4348 | } | |
4349 | ||
4350 | /* set new values */ | |
4351 | np->rx_ring_size = ring->rx_pending; | |
4352 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4353 | |
4354 | if (!nv_optimized(np)) { | |
eafa59f6 AA |
4355 | np->rx_ring.orig = (struct ring_desc*)rxtx_ring; |
4356 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; | |
4357 | } else { | |
4358 | np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; | |
4359 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; | |
4360 | } | |
761fcd9e AA |
4361 | np->rx_skb = (struct nv_skb_map*)rx_skbuff; |
4362 | np->tx_skb = (struct nv_skb_map*)tx_skbuff; | |
eafa59f6 AA |
4363 | np->ring_addr = ring_addr; |
4364 | ||
761fcd9e AA |
4365 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4366 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4367 | |
4368 | if (netif_running(dev)) { | |
4369 | /* reinit driver view of the queues */ | |
4370 | set_bufsize(dev); | |
4371 | if (nv_init_ring(dev)) { | |
4372 | if (!np->in_shutdown) | |
4373 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4374 | } | |
4375 | ||
4376 | /* reinit nic view of the queues */ | |
4377 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4378 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4379 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4380 | base + NvRegRingSizes); | |
4381 | pci_push(base); | |
4382 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4383 | pci_push(base); | |
4384 | ||
4385 | /* restart engines */ | |
36b30ea9 | 4386 | nv_start_rxtx(dev); |
eafa59f6 | 4387 | spin_unlock(&np->lock); |
58dfd9c1 | 4388 | netif_tx_unlock_bh(dev); |
eafa59f6 AA |
4389 | nv_enable_irq(dev); |
4390 | } | |
4391 | return 0; | |
4392 | exit: | |
4393 | return -ENOMEM; | |
4394 | } | |
4395 | ||
b6d0773f AA |
4396 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4397 | { | |
4398 | struct fe_priv *np = netdev_priv(dev); | |
4399 | ||
4400 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4401 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4402 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4403 | } | |
4404 | ||
4405 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4406 | { | |
4407 | struct fe_priv *np = netdev_priv(dev); | |
4408 | int adv, bmcr; | |
4409 | ||
4410 | if ((!np->autoneg && np->duplex == 0) || | |
4411 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
4412 | printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", | |
4413 | dev->name); | |
4414 | return -EINVAL; | |
4415 | } | |
4416 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
4417 | printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); | |
4418 | return -EINVAL; | |
4419 | } | |
4420 | ||
4421 | netif_carrier_off(dev); | |
4422 | if (netif_running(dev)) { | |
4423 | nv_disable_irq(dev); | |
58dfd9c1 | 4424 | netif_tx_lock_bh(dev); |
b6d0773f AA |
4425 | spin_lock(&np->lock); |
4426 | /* stop engines */ | |
36b30ea9 | 4427 | nv_stop_rxtx(dev); |
b6d0773f | 4428 | spin_unlock(&np->lock); |
58dfd9c1 | 4429 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4430 | } |
4431 | ||
4432 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4433 | if (pause->rx_pause) | |
4434 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4435 | if (pause->tx_pause) | |
4436 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4437 | ||
4438 | if (np->autoneg && pause->autoneg) { | |
4439 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4440 | ||
4441 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4442 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
4443 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ | |
4444 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
4445 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4446 | adv |= ADVERTISE_PAUSE_ASYM; | |
4447 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4448 | ||
4449 | if (netif_running(dev)) | |
4450 | printk(KERN_INFO "%s: link down.\n", dev->name); | |
4451 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4452 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4453 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4454 | } else { | |
4455 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4456 | if (pause->rx_pause) | |
4457 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4458 | if (pause->tx_pause) | |
4459 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4460 | ||
4461 | if (!netif_running(dev)) | |
4462 | nv_update_linkspeed(dev); | |
4463 | else | |
4464 | nv_update_pause(dev, np->pause_flags); | |
4465 | } | |
4466 | ||
4467 | if (netif_running(dev)) { | |
36b30ea9 | 4468 | nv_start_rxtx(dev); |
b6d0773f AA |
4469 | nv_enable_irq(dev); |
4470 | } | |
4471 | return 0; | |
4472 | } | |
4473 | ||
5ed2616f AA |
4474 | static u32 nv_get_rx_csum(struct net_device *dev) |
4475 | { | |
4476 | struct fe_priv *np = netdev_priv(dev); | |
f2ad2d9b | 4477 | return (np->rx_csum) != 0; |
5ed2616f AA |
4478 | } |
4479 | ||
4480 | static int nv_set_rx_csum(struct net_device *dev, u32 data) | |
4481 | { | |
4482 | struct fe_priv *np = netdev_priv(dev); | |
4483 | u8 __iomem *base = get_hwbase(dev); | |
4484 | int retcode = 0; | |
4485 | ||
4486 | if (np->driver_data & DEV_HAS_CHECKSUM) { | |
5ed2616f | 4487 | if (data) { |
f2ad2d9b | 4488 | np->rx_csum = 1; |
5ed2616f | 4489 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5ed2616f | 4490 | } else { |
f2ad2d9b AA |
4491 | np->rx_csum = 0; |
4492 | /* vlan is dependent on rx checksum offload */ | |
4493 | if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) | |
4494 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4495 | } |
5ed2616f AA |
4496 | if (netif_running(dev)) { |
4497 | spin_lock_irq(&np->lock); | |
4498 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
4499 | spin_unlock_irq(&np->lock); | |
4500 | } | |
4501 | } else { | |
4502 | return -EINVAL; | |
4503 | } | |
4504 | ||
4505 | return retcode; | |
4506 | } | |
4507 | ||
4508 | static int nv_set_tx_csum(struct net_device *dev, u32 data) | |
4509 | { | |
4510 | struct fe_priv *np = netdev_priv(dev); | |
4511 | ||
4512 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4513 | return ethtool_op_set_tx_hw_csum(dev, data); | |
4514 | else | |
4515 | return -EOPNOTSUPP; | |
4516 | } | |
4517 | ||
4518 | static int nv_set_sg(struct net_device *dev, u32 data) | |
4519 | { | |
4520 | struct fe_priv *np = netdev_priv(dev); | |
4521 | ||
4522 | if (np->driver_data & DEV_HAS_CHECKSUM) | |
4523 | return ethtool_op_set_sg(dev, data); | |
4524 | else | |
4525 | return -EOPNOTSUPP; | |
4526 | } | |
4527 | ||
b9f2c044 | 4528 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4529 | { |
4530 | struct fe_priv *np = netdev_priv(dev); | |
4531 | ||
b9f2c044 JG |
4532 | switch (sset) { |
4533 | case ETH_SS_TEST: | |
4534 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4535 | return NV_TEST_COUNT_EXTENDED; | |
4536 | else | |
4537 | return NV_TEST_COUNT_BASE; | |
4538 | case ETH_SS_STATS: | |
4539 | if (np->driver_data & DEV_HAS_STATISTICS_V1) | |
4540 | return NV_DEV_STATISTICS_V1_COUNT; | |
4541 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) | |
4542 | return NV_DEV_STATISTICS_V2_COUNT; | |
4543 | else | |
4544 | return 0; | |
4545 | default: | |
4546 | return -EOPNOTSUPP; | |
4547 | } | |
52da3578 AA |
4548 | } |
4549 | ||
4550 | static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) | |
4551 | { | |
4552 | struct fe_priv *np = netdev_priv(dev); | |
4553 | ||
4554 | /* update stats */ | |
4555 | nv_do_stats_poll((unsigned long)dev); | |
4556 | ||
b9f2c044 | 4557 | memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); |
9589c77a AA |
4558 | } |
4559 | ||
4560 | static int nv_link_test(struct net_device *dev) | |
4561 | { | |
4562 | struct fe_priv *np = netdev_priv(dev); | |
4563 | int mii_status; | |
4564 | ||
4565 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4566 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4567 | ||
4568 | /* check phy link status */ | |
4569 | if (!(mii_status & BMSR_LSTATUS)) | |
4570 | return 0; | |
4571 | else | |
4572 | return 1; | |
4573 | } | |
4574 | ||
4575 | static int nv_register_test(struct net_device *dev) | |
4576 | { | |
4577 | u8 __iomem *base = get_hwbase(dev); | |
4578 | int i = 0; | |
4579 | u32 orig_read, new_read; | |
4580 | ||
4581 | do { | |
4582 | orig_read = readl(base + nv_registers_test[i].reg); | |
4583 | ||
4584 | /* xor with mask to toggle bits */ | |
4585 | orig_read ^= nv_registers_test[i].mask; | |
4586 | ||
4587 | writel(orig_read, base + nv_registers_test[i].reg); | |
4588 | ||
4589 | new_read = readl(base + nv_registers_test[i].reg); | |
4590 | ||
4591 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4592 | return 0; | |
4593 | ||
4594 | /* restore original value */ | |
4595 | orig_read ^= nv_registers_test[i].mask; | |
4596 | writel(orig_read, base + nv_registers_test[i].reg); | |
4597 | ||
4598 | } while (nv_registers_test[++i].reg != 0); | |
4599 | ||
4600 | return 1; | |
4601 | } | |
4602 | ||
4603 | static int nv_interrupt_test(struct net_device *dev) | |
4604 | { | |
4605 | struct fe_priv *np = netdev_priv(dev); | |
4606 | u8 __iomem *base = get_hwbase(dev); | |
4607 | int ret = 1; | |
4608 | int testcnt; | |
4609 | u32 save_msi_flags, save_poll_interval = 0; | |
4610 | ||
4611 | if (netif_running(dev)) { | |
4612 | /* free current irq */ | |
4613 | nv_free_irq(dev); | |
4614 | save_poll_interval = readl(base+NvRegPollingInterval); | |
4615 | } | |
4616 | ||
4617 | /* flag to test interrupt handler */ | |
4618 | np->intr_test = 0; | |
4619 | ||
4620 | /* setup test irq */ | |
4621 | save_msi_flags = np->msi_flags; | |
4622 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
4623 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
4624 | if (nv_request_irq(dev, 1)) | |
4625 | return 0; | |
4626 | ||
4627 | /* setup timer interrupt */ | |
4628 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
4629 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4630 | ||
4631 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4632 | ||
4633 | /* wait for at least one interrupt */ | |
4634 | msleep(100); | |
4635 | ||
4636 | spin_lock_irq(&np->lock); | |
4637 | ||
4638 | /* flag should be set within ISR */ | |
4639 | testcnt = np->intr_test; | |
4640 | if (!testcnt) | |
4641 | ret = 2; | |
4642 | ||
4643 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
4644 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4645 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4646 | else | |
4647 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4648 | ||
4649 | spin_unlock_irq(&np->lock); | |
4650 | ||
4651 | nv_free_irq(dev); | |
4652 | ||
4653 | np->msi_flags = save_msi_flags; | |
4654 | ||
4655 | if (netif_running(dev)) { | |
4656 | writel(save_poll_interval, base + NvRegPollingInterval); | |
4657 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
4658 | /* restore original irq */ | |
4659 | if (nv_request_irq(dev, 0)) | |
4660 | return 0; | |
4661 | } | |
4662 | ||
4663 | return ret; | |
4664 | } | |
4665 | ||
4666 | static int nv_loopback_test(struct net_device *dev) | |
4667 | { | |
4668 | struct fe_priv *np = netdev_priv(dev); | |
4669 | u8 __iomem *base = get_hwbase(dev); | |
4670 | struct sk_buff *tx_skb, *rx_skb; | |
4671 | dma_addr_t test_dma_addr; | |
4672 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 4673 | u32 flags; |
9589c77a AA |
4674 | int len, i, pkt_len; |
4675 | u8 *pkt_data; | |
4676 | u32 filter_flags = 0; | |
4677 | u32 misc1_flags = 0; | |
4678 | int ret = 1; | |
4679 | ||
4680 | if (netif_running(dev)) { | |
4681 | nv_disable_irq(dev); | |
4682 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
4683 | misc1_flags = readl(base + NvRegMisc1); | |
4684 | } else { | |
4685 | nv_txrx_reset(dev); | |
4686 | } | |
4687 | ||
4688 | /* reinit driver view of the rx queue */ | |
4689 | set_bufsize(dev); | |
4690 | nv_init_ring(dev); | |
4691 | ||
4692 | /* setup hardware for loopback */ | |
4693 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
4694 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
4695 | ||
4696 | /* reinit nic view of the rx queue */ | |
4697 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4698 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4699 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4700 | base + NvRegRingSizes); | |
4701 | pci_push(base); | |
4702 | ||
4703 | /* restart rx engine */ | |
36b30ea9 | 4704 | nv_start_rxtx(dev); |
9589c77a AA |
4705 | |
4706 | /* setup packet for tx */ | |
4707 | pkt_len = ETH_DATA_LEN; | |
4708 | tx_skb = dev_alloc_skb(pkt_len); | |
46798c89 JJ |
4709 | if (!tx_skb) { |
4710 | printk(KERN_ERR "dev_alloc_skb() failed during loopback test" | |
4711 | " of %s\n", dev->name); | |
4712 | ret = 0; | |
4713 | goto out; | |
4714 | } | |
8b5be268 ACM |
4715 | test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
4716 | skb_tailroom(tx_skb), | |
4717 | PCI_DMA_FROMDEVICE); | |
9589c77a AA |
4718 | pkt_data = skb_put(tx_skb, pkt_len); |
4719 | for (i = 0; i < pkt_len; i++) | |
4720 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 4721 | |
36b30ea9 | 4722 | if (!nv_optimized(np)) { |
f82a9352 SH |
4723 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
4724 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 4725 | } else { |
5bb7ea26 AV |
4726 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
4727 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 4728 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
4729 | } |
4730 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4731 | pci_push(get_hwbase(dev)); | |
4732 | ||
4733 | msleep(500); | |
4734 | ||
4735 | /* check for rx of the packet */ | |
36b30ea9 | 4736 | if (!nv_optimized(np)) { |
f82a9352 | 4737 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
4738 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4739 | ||
4740 | } else { | |
f82a9352 | 4741 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
4742 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4743 | } | |
4744 | ||
f82a9352 | 4745 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
4746 | ret = 0; |
4747 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 4748 | if (flags & NV_RX_ERROR) |
9589c77a AA |
4749 | ret = 0; |
4750 | } else { | |
f82a9352 | 4751 | if (flags & NV_RX2_ERROR) { |
9589c77a AA |
4752 | ret = 0; |
4753 | } | |
4754 | } | |
4755 | ||
4756 | if (ret) { | |
4757 | if (len != pkt_len) { | |
4758 | ret = 0; | |
4759 | dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", | |
4760 | dev->name, len, pkt_len); | |
4761 | } else { | |
761fcd9e | 4762 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
4763 | for (i = 0; i < pkt_len; i++) { |
4764 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
4765 | ret = 0; | |
4766 | dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", | |
4767 | dev->name, i); | |
4768 | break; | |
4769 | } | |
4770 | } | |
4771 | } | |
4772 | } else { | |
4773 | dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); | |
4774 | } | |
4775 | ||
4776 | pci_unmap_page(np->pci_dev, test_dma_addr, | |
4305b541 | 4777 | (skb_end_pointer(tx_skb) - tx_skb->data), |
9589c77a AA |
4778 | PCI_DMA_TODEVICE); |
4779 | dev_kfree_skb_any(tx_skb); | |
46798c89 | 4780 | out: |
9589c77a | 4781 | /* stop engines */ |
36b30ea9 | 4782 | nv_stop_rxtx(dev); |
9589c77a AA |
4783 | nv_txrx_reset(dev); |
4784 | /* drain rx queue */ | |
36b30ea9 | 4785 | nv_drain_rxtx(dev); |
9589c77a AA |
4786 | |
4787 | if (netif_running(dev)) { | |
4788 | writel(misc1_flags, base + NvRegMisc1); | |
4789 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
4790 | nv_enable_irq(dev); | |
4791 | } | |
4792 | ||
4793 | return ret; | |
4794 | } | |
4795 | ||
4796 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
4797 | { | |
4798 | struct fe_priv *np = netdev_priv(dev); | |
4799 | u8 __iomem *base = get_hwbase(dev); | |
4800 | int result; | |
b9f2c044 | 4801 | memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64)); |
9589c77a AA |
4802 | |
4803 | if (!nv_link_test(dev)) { | |
4804 | test->flags |= ETH_TEST_FL_FAILED; | |
4805 | buffer[0] = 1; | |
4806 | } | |
4807 | ||
4808 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
4809 | if (netif_running(dev)) { | |
4810 | netif_stop_queue(dev); | |
bea3348e SH |
4811 | #ifdef CONFIG_FORCEDETH_NAPI |
4812 | napi_disable(&np->napi); | |
4813 | #endif | |
58dfd9c1 | 4814 | netif_tx_lock_bh(dev); |
9589c77a AA |
4815 | spin_lock_irq(&np->lock); |
4816 | nv_disable_hw_interrupts(dev, np->irqmask); | |
4817 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { | |
4818 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4819 | } else { | |
4820 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
4821 | } | |
4822 | /* stop engines */ | |
36b30ea9 | 4823 | nv_stop_rxtx(dev); |
9589c77a AA |
4824 | nv_txrx_reset(dev); |
4825 | /* drain rx queue */ | |
36b30ea9 | 4826 | nv_drain_rxtx(dev); |
9589c77a | 4827 | spin_unlock_irq(&np->lock); |
58dfd9c1 | 4828 | netif_tx_unlock_bh(dev); |
9589c77a AA |
4829 | } |
4830 | ||
4831 | if (!nv_register_test(dev)) { | |
4832 | test->flags |= ETH_TEST_FL_FAILED; | |
4833 | buffer[1] = 1; | |
4834 | } | |
4835 | ||
4836 | result = nv_interrupt_test(dev); | |
4837 | if (result != 1) { | |
4838 | test->flags |= ETH_TEST_FL_FAILED; | |
4839 | buffer[2] = 1; | |
4840 | } | |
4841 | if (result == 0) { | |
4842 | /* bail out */ | |
4843 | return; | |
4844 | } | |
4845 | ||
4846 | if (!nv_loopback_test(dev)) { | |
4847 | test->flags |= ETH_TEST_FL_FAILED; | |
4848 | buffer[3] = 1; | |
4849 | } | |
4850 | ||
4851 | if (netif_running(dev)) { | |
4852 | /* reinit driver view of the rx queue */ | |
4853 | set_bufsize(dev); | |
4854 | if (nv_init_ring(dev)) { | |
4855 | if (!np->in_shutdown) | |
4856 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4857 | } | |
4858 | /* reinit nic view of the rx queue */ | |
4859 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4860 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
4861 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), | |
4862 | base + NvRegRingSizes); | |
4863 | pci_push(base); | |
4864 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4865 | pci_push(base); | |
4866 | /* restart rx engine */ | |
36b30ea9 | 4867 | nv_start_rxtx(dev); |
9589c77a | 4868 | netif_start_queue(dev); |
bea3348e SH |
4869 | #ifdef CONFIG_FORCEDETH_NAPI |
4870 | napi_enable(&np->napi); | |
4871 | #endif | |
9589c77a AA |
4872 | nv_enable_hw_interrupts(dev, np->irqmask); |
4873 | } | |
4874 | } | |
4875 | } | |
4876 | ||
52da3578 AA |
4877 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
4878 | { | |
4879 | switch (stringset) { | |
4880 | case ETH_SS_STATS: | |
b9f2c044 | 4881 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 4882 | break; |
9589c77a | 4883 | case ETH_SS_TEST: |
b9f2c044 | 4884 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 4885 | break; |
52da3578 AA |
4886 | } |
4887 | } | |
4888 | ||
7282d491 | 4889 | static const struct ethtool_ops ops = { |
1da177e4 LT |
4890 | .get_drvinfo = nv_get_drvinfo, |
4891 | .get_link = ethtool_op_get_link, | |
4892 | .get_wol = nv_get_wol, | |
4893 | .set_wol = nv_set_wol, | |
4894 | .get_settings = nv_get_settings, | |
4895 | .set_settings = nv_set_settings, | |
dc8216c1 MS |
4896 | .get_regs_len = nv_get_regs_len, |
4897 | .get_regs = nv_get_regs, | |
4898 | .nway_reset = nv_nway_reset, | |
6a78814f | 4899 | .set_tso = nv_set_tso, |
eafa59f6 AA |
4900 | .get_ringparam = nv_get_ringparam, |
4901 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
4902 | .get_pauseparam = nv_get_pauseparam, |
4903 | .set_pauseparam = nv_set_pauseparam, | |
5ed2616f AA |
4904 | .get_rx_csum = nv_get_rx_csum, |
4905 | .set_rx_csum = nv_set_rx_csum, | |
5ed2616f | 4906 | .set_tx_csum = nv_set_tx_csum, |
5ed2616f | 4907 | .set_sg = nv_set_sg, |
52da3578 | 4908 | .get_strings = nv_get_strings, |
52da3578 | 4909 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 4910 | .get_sset_count = nv_get_sset_count, |
9589c77a | 4911 | .self_test = nv_self_test, |
1da177e4 LT |
4912 | }; |
4913 | ||
ee407b02 AA |
4914 | static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
4915 | { | |
4916 | struct fe_priv *np = get_nvpriv(dev); | |
4917 | ||
4918 | spin_lock_irq(&np->lock); | |
4919 | ||
4920 | /* save vlan group */ | |
4921 | np->vlangrp = grp; | |
4922 | ||
4923 | if (grp) { | |
4924 | /* enable vlan on MAC */ | |
4925 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; | |
4926 | } else { | |
4927 | /* disable vlan on MAC */ | |
4928 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
4929 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
4930 | } | |
4931 | ||
4932 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4933 | ||
4934 | spin_unlock_irq(&np->lock); | |
25805dcf | 4935 | } |
ee407b02 | 4936 | |
7e680c22 AA |
4937 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
4938 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
4939 | { | |
4940 | u8 __iomem *base = get_hwbase(dev); | |
4941 | int i; | |
4942 | u32 tx_ctrl, mgmt_sema; | |
4943 | ||
4944 | for (i = 0; i < 10; i++) { | |
4945 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
4946 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4947 | break; | |
4948 | msleep(500); | |
4949 | } | |
4950 | ||
4951 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
4952 | return 0; | |
4953 | ||
4954 | for (i = 0; i < 2; i++) { | |
4955 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4956 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
4957 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
4958 | ||
4959 | /* verify that semaphore was acquired */ | |
4960 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
4961 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
4962 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) | |
4963 | return 1; | |
4964 | else | |
4965 | udelay(50); | |
4966 | } | |
4967 | ||
4968 | return 0; | |
4969 | } | |
4970 | ||
1da177e4 LT |
4971 | static int nv_open(struct net_device *dev) |
4972 | { | |
ac9c1897 | 4973 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4974 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
4975 | int ret = 1; |
4976 | int oom, i; | |
a433686c | 4977 | u32 low; |
1da177e4 LT |
4978 | |
4979 | dprintk(KERN_DEBUG "nv_open: begin\n"); | |
4980 | ||
f1489653 | 4981 | /* erase previous misconfiguration */ |
86a0f043 AA |
4982 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
4983 | nv_mac_reset(dev); | |
1da177e4 LT |
4984 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
4985 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
4986 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
4987 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
4988 | writel(0, base + NvRegPacketFilterFlags); |
4989 | ||
4990 | writel(0, base + NvRegTransmitterControl); | |
4991 | writel(0, base + NvRegReceiverControl); | |
4992 | ||
4993 | writel(0, base + NvRegAdapterControl); | |
4994 | ||
eb91f61b AA |
4995 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
4996 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
4997 | ||
f1489653 | 4998 | /* initialize descriptor rings */ |
d81c0983 | 4999 | set_bufsize(dev); |
1da177e4 LT |
5000 | oom = nv_init_ring(dev); |
5001 | ||
5002 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5003 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5004 | nv_txrx_reset(dev); |
5005 | writel(0, base + NvRegUnknownSetupReg6); | |
5006 | ||
5007 | np->in_shutdown = 0; | |
5008 | ||
f1489653 | 5009 | /* give hw rings */ |
0832b25a | 5010 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
eafa59f6 | 5011 | writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5012 | base + NvRegRingSizes); |
5013 | ||
1da177e4 | 5014 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5015 | if (np->desc_ver == DESC_VER_1) |
5016 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5017 | else | |
5018 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5019 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5020 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5021 | pci_push(base); |
8a4ae7f2 | 5022 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
5023 | reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
5024 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, | |
5025 | KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); | |
5026 | ||
7e680c22 | 5027 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5028 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5029 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5030 | |
1da177e4 LT |
5031 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5032 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5033 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5034 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5035 | |
5036 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5037 | |
5038 | get_random_bytes(&low, sizeof(low)); | |
5039 | low &= NVREG_SLOTTIME_MASK; | |
5040 | if (np->desc_ver == DESC_VER_1) { | |
5041 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5042 | } else { | |
5043 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5044 | /* setup legacy backoff */ | |
5045 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5046 | } else { | |
5047 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5048 | nv_gear_backoff_reseed(dev); | |
5049 | } | |
5050 | } | |
9744e218 AA |
5051 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5052 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5053 | if (poll_interval == -1) { |
5054 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5055 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5056 | else | |
5057 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
5058 | } | |
5059 | else | |
5060 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); | |
1da177e4 LT |
5061 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5062 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5063 | base + NvRegAdapterControl); | |
5064 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5065 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5066 | if (np->wolenabled) |
5067 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5068 | |
5069 | i = readl(base + NvRegPowerState); | |
5070 | if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) | |
5071 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); | |
5072 | ||
5073 | pci_push(base); | |
5074 | udelay(10); | |
5075 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5076 | ||
84b3932b | 5077 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5078 | pci_push(base); |
eb798428 | 5079 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5080 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5081 | pci_push(base); | |
5082 | ||
9589c77a | 5083 | if (nv_request_irq(dev, 0)) { |
84b3932b | 5084 | goto out_drain; |
d33a73c8 | 5085 | } |
1da177e4 LT |
5086 | |
5087 | /* ask for interrupts */ | |
84b3932b | 5088 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5089 | |
5090 | spin_lock_irq(&np->lock); | |
5091 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5092 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5093 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5094 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5095 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5096 | /* One manual link speed update: Interrupts are enabled, future link | |
5097 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5098 | */ | |
5099 | { | |
5100 | u32 miistat; | |
5101 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 5102 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5103 | dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
5104 | } | |
1b1b3c9b MS |
5105 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5106 | * to init hw */ | |
5107 | np->linkspeed = 0; | |
1da177e4 | 5108 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5109 | nv_start_rxtx(dev); |
1da177e4 | 5110 | netif_start_queue(dev); |
bea3348e SH |
5111 | #ifdef CONFIG_FORCEDETH_NAPI |
5112 | napi_enable(&np->napi); | |
5113 | #endif | |
e27cdba5 | 5114 | |
1da177e4 LT |
5115 | if (ret) { |
5116 | netif_carrier_on(dev); | |
5117 | } else { | |
f7ab697d | 5118 | printk(KERN_INFO "%s: no link during initialization.\n", dev->name); |
1da177e4 LT |
5119 | netif_carrier_off(dev); |
5120 | } | |
5121 | if (oom) | |
5122 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5123 | |
5124 | /* start statistics timer */ | |
57fff698 | 5125 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) |
bfebbb88 DD |
5126 | mod_timer(&np->stats_poll, |
5127 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5128 | |
1da177e4 LT |
5129 | spin_unlock_irq(&np->lock); |
5130 | ||
5131 | return 0; | |
5132 | out_drain: | |
36b30ea9 | 5133 | nv_drain_rxtx(dev); |
1da177e4 LT |
5134 | return ret; |
5135 | } | |
5136 | ||
5137 | static int nv_close(struct net_device *dev) | |
5138 | { | |
ac9c1897 | 5139 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5140 | u8 __iomem *base; |
5141 | ||
5142 | spin_lock_irq(&np->lock); | |
5143 | np->in_shutdown = 1; | |
5144 | spin_unlock_irq(&np->lock); | |
bea3348e SH |
5145 | #ifdef CONFIG_FORCEDETH_NAPI |
5146 | napi_disable(&np->napi); | |
5147 | #endif | |
a7475906 | 5148 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5149 | |
5150 | del_timer_sync(&np->oom_kick); | |
5151 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5152 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5153 | |
5154 | netif_stop_queue(dev); | |
5155 | spin_lock_irq(&np->lock); | |
36b30ea9 | 5156 | nv_stop_rxtx(dev); |
1da177e4 LT |
5157 | nv_txrx_reset(dev); |
5158 | ||
5159 | /* disable interrupts on the nic or we will lock up */ | |
5160 | base = get_hwbase(dev); | |
84b3932b | 5161 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5162 | pci_push(base); |
5163 | dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); | |
5164 | ||
5165 | spin_unlock_irq(&np->lock); | |
5166 | ||
84b3932b | 5167 | nv_free_irq(dev); |
1da177e4 | 5168 | |
36b30ea9 | 5169 | nv_drain_rxtx(dev); |
1da177e4 | 5170 | |
2cc49a5c TM |
5171 | if (np->wolenabled) { |
5172 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); | |
1da177e4 | 5173 | nv_start_rx(dev); |
2cc49a5c | 5174 | } |
1da177e4 LT |
5175 | |
5176 | /* FIXME: power down nic */ | |
5177 | ||
5178 | return 0; | |
5179 | } | |
5180 | ||
5181 | static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) | |
5182 | { | |
5183 | struct net_device *dev; | |
5184 | struct fe_priv *np; | |
5185 | unsigned long addr; | |
5186 | u8 __iomem *base; | |
5187 | int err, i; | |
5070d340 | 5188 | u32 powerstate, txreg; |
7e680c22 AA |
5189 | u32 phystate_orig = 0, phystate; |
5190 | int phyinitialized = 0; | |
0795af57 | 5191 | DECLARE_MAC_BUF(mac); |
3f88ce49 JG |
5192 | static int printed_version; |
5193 | ||
5194 | if (!printed_version++) | |
5195 | printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" | |
5196 | " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); | |
1da177e4 LT |
5197 | |
5198 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5199 | err = -ENOMEM; | |
5200 | if (!dev) | |
5201 | goto out; | |
5202 | ||
ac9c1897 | 5203 | np = netdev_priv(dev); |
bea3348e | 5204 | np->dev = dev; |
1da177e4 LT |
5205 | np->pci_dev = pci_dev; |
5206 | spin_lock_init(&np->lock); | |
1da177e4 LT |
5207 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
5208 | ||
5209 | init_timer(&np->oom_kick); | |
5210 | np->oom_kick.data = (unsigned long) dev; | |
5211 | np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ | |
5212 | init_timer(&np->nic_poll); | |
5213 | np->nic_poll.data = (unsigned long) dev; | |
5214 | np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ | |
52da3578 AA |
5215 | init_timer(&np->stats_poll); |
5216 | np->stats_poll.data = (unsigned long) dev; | |
5217 | np->stats_poll.function = &nv_do_stats_poll; /* timer handler */ | |
1da177e4 LT |
5218 | |
5219 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5220 | if (err) |
1da177e4 | 5221 | goto out_free; |
1da177e4 LT |
5222 | |
5223 | pci_set_master(pci_dev); | |
5224 | ||
5225 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5226 | if (err < 0) | |
5227 | goto out_disable; | |
5228 | ||
57fff698 AA |
5229 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2)) |
5230 | np->register_size = NV_PCI_REGSZ_VER3; | |
5231 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5232 | np->register_size = NV_PCI_REGSZ_VER2; |
5233 | else | |
5234 | np->register_size = NV_PCI_REGSZ_VER1; | |
5235 | ||
1da177e4 LT |
5236 | err = -EINVAL; |
5237 | addr = 0; | |
5238 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
5239 | dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", | |
5240 | pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), | |
5241 | pci_resource_len(pci_dev, i), | |
5242 | pci_resource_flags(pci_dev, i)); | |
5243 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && | |
86a0f043 | 5244 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5245 | addr = pci_resource_start(pci_dev, i); |
5246 | break; | |
5247 | } | |
5248 | } | |
5249 | if (i == DEVICE_COUNT_RESOURCE) { | |
3f88ce49 JG |
5250 | dev_printk(KERN_INFO, &pci_dev->dev, |
5251 | "Couldn't find register window\n"); | |
1da177e4 LT |
5252 | goto out_relreg; |
5253 | } | |
5254 | ||
86a0f043 AA |
5255 | /* copy of driver data */ |
5256 | np->driver_data = id->driver_data; | |
5257 | ||
1da177e4 | 5258 | /* handle different descriptor versions */ |
ee73362c MS |
5259 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5260 | /* packet format 3: supports 40-bit addressing */ | |
5261 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5262 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5263 | if (dma_64bit) { |
3f88ce49 JG |
5264 | if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) |
5265 | dev_printk(KERN_INFO, &pci_dev->dev, | |
5266 | "64-bit DMA failed, using 32-bit addressing\n"); | |
5267 | else | |
69fe3fd7 | 5268 | dev->features |= NETIF_F_HIGHDMA; |
69fe3fd7 | 5269 | if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
3f88ce49 JG |
5270 | dev_printk(KERN_INFO, &pci_dev->dev, |
5271 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5272 | } |
ee73362c MS |
5273 | } |
5274 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5275 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5276 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5277 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5278 | } else { |
5279 | /* original packet format */ | |
5280 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5281 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5282 | } |
ee73362c MS |
5283 | |
5284 | np->pkt_limit = NV_PKTLIMIT_1; | |
5285 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5286 | np->pkt_limit = NV_PKTLIMIT_2; | |
5287 | ||
8a4ae7f2 | 5288 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
f2ad2d9b | 5289 | np->rx_csum = 1; |
8a4ae7f2 | 5290 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
ac9c1897 | 5291 | dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
fa45459e | 5292 | dev->features |= NETIF_F_TSO; |
21828163 | 5293 | } |
8a4ae7f2 | 5294 | |
ee407b02 AA |
5295 | np->vlanctl_bits = 0; |
5296 | if (id->driver_data & DEV_HAS_VLAN) { | |
5297 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
5298 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; | |
5299 | dev->vlan_rx_register = nv_vlan_rx_register; | |
ee407b02 AA |
5300 | } |
5301 | ||
d33a73c8 | 5302 | np->msi_flags = 0; |
69fe3fd7 | 5303 | if ((id->driver_data & DEV_HAS_MSI) && msi) { |
d33a73c8 AA |
5304 | np->msi_flags |= NV_MSI_CAPABLE; |
5305 | } | |
69fe3fd7 | 5306 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
d33a73c8 AA |
5307 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5308 | } | |
5309 | ||
b6d0773f | 5310 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5311 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5312 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5313 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5314 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5315 | } |
f3b197ac | 5316 | |
eb91f61b | 5317 | |
1da177e4 | 5318 | err = -ENOMEM; |
86a0f043 | 5319 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5320 | if (!np->base) |
5321 | goto out_relreg; | |
5322 | dev->base_addr = (unsigned long)np->base; | |
ee73362c | 5323 | |
1da177e4 | 5324 | dev->irq = pci_dev->irq; |
ee73362c | 5325 | |
eafa59f6 AA |
5326 | np->rx_ring_size = RX_RING_DEFAULT; |
5327 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5328 | |
36b30ea9 | 5329 | if (!nv_optimized(np)) { |
ee73362c | 5330 | np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
eafa59f6 | 5331 | sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5332 | &np->ring_addr); |
5333 | if (!np->rx_ring.orig) | |
5334 | goto out_unmap; | |
eafa59f6 | 5335 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c MS |
5336 | } else { |
5337 | np->rx_ring.ex = pci_alloc_consistent(pci_dev, | |
eafa59f6 | 5338 | sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
ee73362c MS |
5339 | &np->ring_addr); |
5340 | if (!np->rx_ring.ex) | |
5341 | goto out_unmap; | |
eafa59f6 AA |
5342 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5343 | } | |
dd00cc48 YP |
5344 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5345 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5346 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5347 | goto out_freering; |
1da177e4 LT |
5348 | |
5349 | dev->open = nv_open; | |
5350 | dev->stop = nv_close; | |
36b30ea9 JG |
5351 | |
5352 | if (!nv_optimized(np)) | |
86b22b0d AA |
5353 | dev->hard_start_xmit = nv_start_xmit; |
5354 | else | |
5355 | dev->hard_start_xmit = nv_start_xmit_optimized; | |
1da177e4 LT |
5356 | dev->get_stats = nv_get_stats; |
5357 | dev->change_mtu = nv_change_mtu; | |
72b31782 | 5358 | dev->set_mac_address = nv_set_mac_address; |
1da177e4 | 5359 | dev->set_multicast_list = nv_set_multicast; |
2918c35d MS |
5360 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5361 | dev->poll_controller = nv_poll_controller; | |
e27cdba5 | 5362 | #endif |
e27cdba5 | 5363 | #ifdef CONFIG_FORCEDETH_NAPI |
bea3348e | 5364 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
2918c35d | 5365 | #endif |
1da177e4 LT |
5366 | SET_ETHTOOL_OPS(dev, &ops); |
5367 | dev->tx_timeout = nv_tx_timeout; | |
5368 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; | |
5369 | ||
5370 | pci_set_drvdata(pci_dev, dev); | |
5371 | ||
5372 | /* read the mac address */ | |
5373 | base = get_hwbase(dev); | |
5374 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5375 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5376 | ||
5070d340 AA |
5377 | /* check the workaround bit for correct mac address order */ |
5378 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5379 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5380 | /* mac address is already in correct order */ |
5381 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5382 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5383 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5384 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5385 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5386 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5387 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5388 | /* mac address is already in correct order */ | |
5389 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5390 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5391 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5392 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5393 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5394 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5395 | /* | |
5396 | * Set orig mac address back to the reversed version. | |
5397 | * This flag will be cleared during low power transition. | |
5398 | * Therefore, we should always put back the reversed address. | |
5399 | */ | |
5400 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5401 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5402 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5403 | } else { |
5404 | /* need to reverse mac address to correct order */ | |
5405 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5406 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5407 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5408 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5409 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5410 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 AA |
5411 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
5412 | } | |
c704b856 | 5413 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 5414 | |
c704b856 | 5415 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
5416 | /* |
5417 | * Bad mac address. At least one bios sets the mac address | |
5418 | * to 01:23:45:67:89:ab | |
5419 | */ | |
3f88ce49 JG |
5420 | dev_printk(KERN_ERR, &pci_dev->dev, |
5421 | "Invalid Mac address detected: %s\n", | |
5422 | print_mac(mac, dev->dev_addr)); | |
5423 | dev_printk(KERN_ERR, &pci_dev->dev, | |
5424 | "Please complain to your hardware vendor. Switching to a random MAC.\n"); | |
1da177e4 LT |
5425 | dev->dev_addr[0] = 0x00; |
5426 | dev->dev_addr[1] = 0x00; | |
5427 | dev->dev_addr[2] = 0x6c; | |
5428 | get_random_bytes(&dev->dev_addr[3], 3); | |
5429 | } | |
5430 | ||
0795af57 JP |
5431 | dprintk(KERN_DEBUG "%s: MAC Address %s\n", |
5432 | pci_name(pci_dev), print_mac(mac, dev->dev_addr)); | |
1da177e4 | 5433 | |
f1489653 AA |
5434 | /* set mac address */ |
5435 | nv_copy_mac_to_hw(dev); | |
5436 | ||
1da177e4 LT |
5437 | /* disable WOL */ |
5438 | writel(0, base + NvRegWakeUpFlags); | |
5439 | np->wolenabled = 0; | |
5440 | ||
86a0f043 | 5441 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5442 | |
5443 | /* take phy and nic out of low power mode */ | |
5444 | powerstate = readl(base + NvRegPowerState2); | |
5445 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
5446 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || | |
5447 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && | |
44c10138 | 5448 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5449 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5450 | writel(powerstate, base + NvRegPowerState2); | |
5451 | } | |
5452 | ||
1da177e4 | 5453 | if (np->desc_ver == DESC_VER_1) { |
ac9c1897 | 5454 | np->tx_flags = NV_TX_VALID; |
1da177e4 | 5455 | } else { |
ac9c1897 | 5456 | np->tx_flags = NV_TX2_VALID; |
1da177e4 | 5457 | } |
d33a73c8 | 5458 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
a971c324 | 5459 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
d33a73c8 AA |
5460 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5461 | np->msi_flags |= 0x0003; | |
5462 | } else { | |
a971c324 | 5463 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5464 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5465 | np->msi_flags |= 0x0001; | |
5466 | } | |
a971c324 | 5467 | |
1da177e4 LT |
5468 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5469 | np->irqmask |= NVREG_IRQ_TIMER; | |
5470 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
5471 | dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); | |
5472 | np->need_linktimer = 1; | |
5473 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5474 | } else { | |
5475 | dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); | |
5476 | np->need_linktimer = 0; | |
5477 | } | |
5478 | ||
3b446c3e AA |
5479 | /* Limit the number of tx's outstanding for hw bug */ |
5480 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5481 | np->tx_limit = 1; | |
5482 | if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 || | |
5483 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 || | |
5484 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 || | |
5485 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 || | |
5486 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 || | |
5487 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 || | |
5488 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 || | |
5489 | id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) && | |
5490 | pci_dev->revision >= 0xA2) | |
5491 | np->tx_limit = 0; | |
5492 | } | |
5493 | ||
7e680c22 AA |
5494 | /* clear phy state and temporarily halt phy interrupts */ |
5495 | writel(0, base + NvRegMIIMask); | |
5496 | phystate = readl(base + NvRegAdapterControl); | |
5497 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5498 | phystate_orig = 1; | |
5499 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5500 | writel(phystate, base + NvRegAdapterControl); | |
5501 | } | |
eb798428 | 5502 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5503 | |
5504 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5505 | /* management unit running on the mac? */ |
f35723ec AA |
5506 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) { |
5507 | np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; | |
5508 | dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use); | |
9e555930 AA |
5509 | if (nv_mgmt_acquire_sema(dev)) { |
5510 | /* management unit setup the phy already? */ | |
5511 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5512 | NVREG_XMITCTL_SYNC_PHY_INIT) { | |
5513 | /* phy is inited by mgmt unit */ | |
5514 | phyinitialized = 1; | |
5515 | dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev)); | |
5516 | } else { | |
5517 | /* we need to init the phy */ | |
7e680c22 | 5518 | } |
7e680c22 AA |
5519 | } |
5520 | } | |
5521 | } | |
5522 | ||
1da177e4 | 5523 | /* find a suitable phy */ |
7a33e45a | 5524 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5525 | int id1, id2; |
7a33e45a | 5526 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5527 | |
5528 | spin_lock_irq(&np->lock); | |
7a33e45a | 5529 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5530 | spin_unlock_irq(&np->lock); |
5531 | if (id1 < 0 || id1 == 0xffff) | |
5532 | continue; | |
5533 | spin_lock_irq(&np->lock); | |
7a33e45a | 5534 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5535 | spin_unlock_irq(&np->lock); |
5536 | if (id2 < 0 || id2 == 0xffff) | |
5537 | continue; | |
5538 | ||
edf7e5ec | 5539 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5540 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5541 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
5542 | dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", | |
7a33e45a AA |
5543 | pci_name(pci_dev), id1, id2, phyaddr); |
5544 | np->phyaddr = phyaddr; | |
1da177e4 LT |
5545 | np->phy_oui = id1 | id2; |
5546 | break; | |
5547 | } | |
7a33e45a | 5548 | if (i == 33) { |
3f88ce49 JG |
5549 | dev_printk(KERN_INFO, &pci_dev->dev, |
5550 | "open: Could not find a valid PHY.\n"); | |
eafa59f6 | 5551 | goto out_error; |
1da177e4 | 5552 | } |
f3b197ac | 5553 | |
7e680c22 AA |
5554 | if (!phyinitialized) { |
5555 | /* reset it */ | |
5556 | phy_init(dev); | |
f35723ec AA |
5557 | } else { |
5558 | /* see if it is a gigabit phy */ | |
5559 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
5560 | if (mii_status & PHY_GIGABIT) { | |
5561 | np->gigabit = PHY_GIGABIT; | |
5562 | } | |
7e680c22 | 5563 | } |
1da177e4 LT |
5564 | |
5565 | /* set default link speed settings */ | |
5566 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
5567 | np->duplex = 0; | |
5568 | np->autoneg = 1; | |
5569 | ||
5570 | err = register_netdev(dev); | |
5571 | if (err) { | |
3f88ce49 JG |
5572 | dev_printk(KERN_INFO, &pci_dev->dev, |
5573 | "unable to register netdev: %d\n", err); | |
eafa59f6 | 5574 | goto out_error; |
1da177e4 | 5575 | } |
3f88ce49 JG |
5576 | |
5577 | dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, " | |
5578 | "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", | |
5579 | dev->name, | |
5580 | np->phy_oui, | |
5581 | np->phyaddr, | |
5582 | dev->dev_addr[0], | |
5583 | dev->dev_addr[1], | |
5584 | dev->dev_addr[2], | |
5585 | dev->dev_addr[3], | |
5586 | dev->dev_addr[4], | |
5587 | dev->dev_addr[5]); | |
5588 | ||
5589 | dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", | |
5590 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", | |
5591 | dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ? | |
5592 | "csum " : "", | |
5593 | dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? | |
5594 | "vlan " : "", | |
5595 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", | |
5596 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
5597 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
5598 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
5599 | np->need_linktimer ? "lnktim " : "", | |
5600 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
5601 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
5602 | np->desc_ver); | |
1da177e4 LT |
5603 | |
5604 | return 0; | |
5605 | ||
eafa59f6 | 5606 | out_error: |
7e680c22 AA |
5607 | if (phystate_orig) |
5608 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
1da177e4 | 5609 | pci_set_drvdata(pci_dev, NULL); |
eafa59f6 AA |
5610 | out_freering: |
5611 | free_rings(dev); | |
1da177e4 LT |
5612 | out_unmap: |
5613 | iounmap(get_hwbase(dev)); | |
5614 | out_relreg: | |
5615 | pci_release_regions(pci_dev); | |
5616 | out_disable: | |
5617 | pci_disable_device(pci_dev); | |
5618 | out_free: | |
5619 | free_netdev(dev); | |
5620 | out: | |
5621 | return err; | |
5622 | } | |
5623 | ||
5624 | static void __devexit nv_remove(struct pci_dev *pci_dev) | |
5625 | { | |
5626 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
5627 | struct fe_priv *np = netdev_priv(dev); |
5628 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 LT |
5629 | |
5630 | unregister_netdev(dev); | |
5631 | ||
f1489653 AA |
5632 | /* special op: write back the misordered MAC address - otherwise |
5633 | * the next nv_probe would see a wrong address. | |
5634 | */ | |
5635 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
5636 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |
2e3884b5 BS |
5637 | writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, |
5638 | base + NvRegTransmitPoll); | |
f1489653 | 5639 | |
1da177e4 | 5640 | /* free all structures */ |
eafa59f6 | 5641 | free_rings(dev); |
1da177e4 LT |
5642 | iounmap(get_hwbase(dev)); |
5643 | pci_release_regions(pci_dev); | |
5644 | pci_disable_device(pci_dev); | |
5645 | free_netdev(dev); | |
5646 | pci_set_drvdata(pci_dev, NULL); | |
5647 | } | |
5648 | ||
a189317f FR |
5649 | #ifdef CONFIG_PM |
5650 | static int nv_suspend(struct pci_dev *pdev, pm_message_t state) | |
5651 | { | |
5652 | struct net_device *dev = pci_get_drvdata(pdev); | |
5653 | struct fe_priv *np = netdev_priv(dev); | |
5654 | ||
5655 | if (!netif_running(dev)) | |
5656 | goto out; | |
5657 | ||
5658 | netif_device_detach(dev); | |
5659 | ||
5660 | // Gross. | |
5661 | nv_close(dev); | |
5662 | ||
5663 | pci_save_state(pdev); | |
5664 | pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled); | |
5665 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
5666 | out: | |
5667 | return 0; | |
5668 | } | |
5669 | ||
5670 | static int nv_resume(struct pci_dev *pdev) | |
5671 | { | |
5672 | struct net_device *dev = pci_get_drvdata(pdev); | |
a376e79c | 5673 | u8 __iomem *base = get_hwbase(dev); |
a189317f | 5674 | int rc = 0; |
a376e79c | 5675 | u32 txreg; |
a189317f FR |
5676 | |
5677 | if (!netif_running(dev)) | |
5678 | goto out; | |
5679 | ||
5680 | netif_device_attach(dev); | |
5681 | ||
5682 | pci_set_power_state(pdev, PCI_D0); | |
5683 | pci_restore_state(pdev); | |
5684 | pci_enable_wake(pdev, PCI_D0, 0); | |
5685 | ||
a376e79c AA |
5686 | /* restore mac address reverse flag */ |
5687 | txreg = readl(base + NvRegTransmitPoll); | |
5688 | txreg |= NVREG_TRANSMITPOLL_MAC_ADDR_REV; | |
5689 | writel(txreg, base + NvRegTransmitPoll); | |
5690 | ||
a189317f FR |
5691 | rc = nv_open(dev); |
5692 | out: | |
5693 | return rc; | |
5694 | } | |
5695 | #else | |
5696 | #define nv_suspend NULL | |
5697 | #define nv_resume NULL | |
5698 | #endif /* CONFIG_PM */ | |
5699 | ||
1da177e4 LT |
5700 | static struct pci_device_id pci_tbl[] = { |
5701 | { /* nForce Ethernet Controller */ | |
dc8216c1 | 5702 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
c2dba06d | 5703 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5704 | }, |
5705 | { /* nForce2 Ethernet Controller */ | |
dc8216c1 | 5706 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
c2dba06d | 5707 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5708 | }, |
5709 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5710 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
c2dba06d | 5711 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
1da177e4 LT |
5712 | }, |
5713 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5714 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
8a4ae7f2 | 5715 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5716 | }, |
5717 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5718 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
8a4ae7f2 | 5719 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5720 | }, |
5721 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5722 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
8a4ae7f2 | 5723 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5724 | }, |
5725 | { /* nForce3 Ethernet Controller */ | |
dc8216c1 | 5726 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
8a4ae7f2 | 5727 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
1da177e4 LT |
5728 | }, |
5729 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 5730 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
3b446c3e | 5731 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
5732 | }, |
5733 | { /* CK804 Ethernet Controller */ | |
dc8216c1 | 5734 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
3b446c3e | 5735 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
5736 | }, |
5737 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 5738 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
3b446c3e | 5739 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 LT |
5740 | }, |
5741 | { /* MCP04 Ethernet Controller */ | |
dc8216c1 | 5742 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
3b446c3e | 5743 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT, |
1da177e4 | 5744 | }, |
9992d4aa | 5745 | { /* MCP51 Ethernet Controller */ |
dc8216c1 | 5746 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
57fff698 | 5747 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, |
9992d4aa MS |
5748 | }, |
5749 | { /* MCP51 Ethernet Controller */ | |
dc8216c1 | 5750 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
57fff698 | 5751 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1, |
9992d4aa | 5752 | }, |
f49d16ef | 5753 | { /* MCP55 Ethernet Controller */ |
dc8216c1 | 5754 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
3b446c3e | 5755 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, |
f49d16ef MS |
5756 | }, |
5757 | { /* MCP55 Ethernet Controller */ | |
dc8216c1 | 5758 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
3b446c3e | 5759 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT, |
f49d16ef | 5760 | }, |
c99ce7ee AA |
5761 | { /* MCP61 Ethernet Controller */ |
5762 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), | |
5289b4c4 | 5763 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
5764 | }, |
5765 | { /* MCP61 Ethernet Controller */ | |
5766 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), | |
5289b4c4 | 5767 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
5768 | }, |
5769 | { /* MCP61 Ethernet Controller */ | |
5770 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), | |
5289b4c4 | 5771 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
5772 | }, |
5773 | { /* MCP61 Ethernet Controller */ | |
5774 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), | |
5289b4c4 | 5775 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, |
c99ce7ee AA |
5776 | }, |
5777 | { /* MCP65 Ethernet Controller */ | |
5778 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), | |
a433686c | 5779 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
5780 | }, |
5781 | { /* MCP65 Ethernet Controller */ | |
5782 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), | |
a433686c | 5783 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
5784 | }, |
5785 | { /* MCP65 Ethernet Controller */ | |
5786 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), | |
a433686c | 5787 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee AA |
5788 | }, |
5789 | { /* MCP65 Ethernet Controller */ | |
5790 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), | |
a433686c | 5791 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
c99ce7ee | 5792 | }, |
f4344848 AA |
5793 | { /* MCP67 Ethernet Controller */ |
5794 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), | |
a433686c | 5795 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
5796 | }, |
5797 | { /* MCP67 Ethernet Controller */ | |
5798 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), | |
a433686c | 5799 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
5800 | }, |
5801 | { /* MCP67 Ethernet Controller */ | |
5802 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), | |
a433686c | 5803 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 AA |
5804 | }, |
5805 | { /* MCP67 Ethernet Controller */ | |
5806 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), | |
a433686c | 5807 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE, |
f4344848 | 5808 | }, |
1398661b AA |
5809 | { /* MCP73 Ethernet Controller */ |
5810 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), | |
a433686c | 5811 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
5812 | }, |
5813 | { /* MCP73 Ethernet Controller */ | |
5814 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), | |
a433686c | 5815 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
5816 | }, |
5817 | { /* MCP73 Ethernet Controller */ | |
5818 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), | |
a433686c | 5819 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b AA |
5820 | }, |
5821 | { /* MCP73 Ethernet Controller */ | |
5822 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), | |
a433686c | 5823 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE, |
1398661b | 5824 | }, |
96fd4cd3 AA |
5825 | { /* MCP77 Ethernet Controller */ |
5826 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), | |
a433686c | 5827 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
5828 | }, |
5829 | { /* MCP77 Ethernet Controller */ | |
5830 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), | |
a433686c | 5831 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
5832 | }, |
5833 | { /* MCP77 Ethernet Controller */ | |
5834 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), | |
a433686c | 5835 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 AA |
5836 | }, |
5837 | { /* MCP77 Ethernet Controller */ | |
5838 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), | |
a433686c | 5839 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
96fd4cd3 | 5840 | }, |
490dde89 AA |
5841 | { /* MCP79 Ethernet Controller */ |
5842 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), | |
a433686c | 5843 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
5844 | }, |
5845 | { /* MCP79 Ethernet Controller */ | |
5846 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), | |
a433686c | 5847 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
5848 | }, |
5849 | { /* MCP79 Ethernet Controller */ | |
5850 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), | |
a433686c | 5851 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 AA |
5852 | }, |
5853 | { /* MCP79 Ethernet Controller */ | |
5854 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), | |
a433686c | 5855 | .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE, |
490dde89 | 5856 | }, |
1da177e4 LT |
5857 | {0,}, |
5858 | }; | |
5859 | ||
5860 | static struct pci_driver driver = { | |
3f88ce49 JG |
5861 | .name = DRV_NAME, |
5862 | .id_table = pci_tbl, | |
5863 | .probe = nv_probe, | |
5864 | .remove = __devexit_p(nv_remove), | |
5865 | .suspend = nv_suspend, | |
5866 | .resume = nv_resume, | |
1da177e4 LT |
5867 | }; |
5868 | ||
1da177e4 LT |
5869 | static int __init init_nic(void) |
5870 | { | |
29917620 | 5871 | return pci_register_driver(&driver); |
1da177e4 LT |
5872 | } |
5873 | ||
5874 | static void __exit exit_nic(void) | |
5875 | { | |
5876 | pci_unregister_driver(&driver); | |
5877 | } | |
5878 | ||
5879 | module_param(max_interrupt_work, int, 0); | |
5880 | MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); | |
a971c324 AA |
5881 | module_param(optimization_mode, int, 0); |
5882 | MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); | |
5883 | module_param(poll_interval, int, 0); | |
5884 | MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); | |
69fe3fd7 AA |
5885 | module_param(msi, int, 0); |
5886 | MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
5887 | module_param(msix, int, 0); | |
5888 | MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); | |
5889 | module_param(dma_64bit, int, 0); | |
5890 | MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); | |
1da177e4 LT |
5891 | |
5892 | MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); | |
5893 | MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); | |
5894 | MODULE_LICENSE("GPL"); | |
5895 | ||
5896 | MODULE_DEVICE_TABLE(pci, pci_tbl); | |
5897 | ||
5898 | module_init(init_nic); | |
5899 | module_exit(exit_nic); |